// this file is generated by topld.pl 
// please don't edit it. 
// input pins 
// output pins 
// internal nodes 
// code nodes 
// equations 
// c1: cpol_use 
// c2: c_us 
// c3: c_us 
// c4: c_us 
// c5: c_us 
// c6: c_us 
// c7: c_us 
// c8: c_us 
// c9: c_us 
// c10: c_us 
// c11: cpol_use 
// c12: c_us 
// c13: cpol_use 
// c14: c_us 
// c15: cpol_use 
// c16: c_us 
// c17: cpol_use 
// c18: c_us 
// c19: c_us 
// e1: sn7474 
module m710b (n_t_21x, n_t_4x, ac10, ac11, ac4, ac5, ac6, ac7, ac8, ac9, clear_l, clocka, clockb, del_pun1, feed_sw_l, initialize_l, io_in_int_l, io_in_skip_l, iop1, iop2, iop4, iop_02, mb3_lp_0_rp, mb4_lp_0_rp, mb5_lp_0_rp, mb6_lp_0_rp, mb7_lp_1_rp, mb8_lp_0_rp, n4_5usec, n_t_10x, n_t_11x, n_t_12x, n_t_19x, n_t_1x, n_t_23x, n_t_6x, n_t_9x, pb0, pb1, pb2, pb3, pb4, pb5, pb6, pb7, pun_active_l, pun_done, sync_bias, sync_pun);
input n_t_21x;
input n_t_4x;
input ac10;
input ac11;
input ac4;
input ac5;
input ac6;
input ac7;
input ac8;
input ac9;
inout clear_l;
inout clocka;
inout clockb;
input del_pun1;
input feed_sw_l;
input initialize_l;
output io_in_int_l;
output io_in_skip_l;
input iop1;
input iop2;
input iop4;
inout iop_02;
input mb3_lp_0_rp;
input mb4_lp_0_rp;
input mb5_lp_0_rp;
input mb6_lp_0_rp;
input mb7_lp_1_rp;
input mb8_lp_0_rp;
output n4_5usec;
output n_t_10x;
inout n_t_11x;
inout n_t_12x;
output n_t_19x;
inout n_t_1x;
output n_t_23x;
inout n_t_6x;
output n_t_9x;
output reg pb0;
output reg pb1;
output reg pb2;
output reg pb3;
output reg pb4;
output reg pb5;
output reg pb6;
output reg pb7;
inout pun_active_l;
output pun_done;
output sync_bias;
output sync_pun;

reg n_t_26x_m;
reg pb0_m;
reg pb1_m;
reg pb2_m;
reg pb3_m;
reg pb4_m;
reg pb5_m;
reg pb6_m;
reg pb7_m;
reg pun_flag_m;

reg n_t_26x;
reg pun_flag;
wire clock_l;
wire n_t_22x;
wire n_t_5x;
wire n_t_7x;
always @(clocka, clear_l, ac4)
  if (~clear_l) begin
    pb0_m <= 1'b0;
  end else
  if (~(clocka)) begin
    pb0_m <= ac4;
  end
always @(clocka, clear_l, pb0_m)
  if (~clear_l) begin
    pb0 <= 1'b0;
  end else
  if (clocka) begin
    pb0 <= pb0_m;
  end
always @(clocka, clear_l, ac5)
  if (~clear_l) begin
    pb1_m <= 1'b0;
  end else
  if (~(clocka)) begin
    pb1_m <= ac5;
  end
always @(clocka, clear_l, pb1_m)
  if (~clear_l) begin
    pb1 <= 1'b0;
  end else
  if (clocka) begin
    pb1 <= pb1_m;
  end
// e2: sn7474 
always @(clocka, clear_l, ac6)
  if (~clear_l) begin
    pb2_m <= 1'b0;
  end else
  if (~(clocka)) begin
    pb2_m <= ac6;
  end
always @(clocka, clear_l, pb2_m)
  if (~clear_l) begin
    pb2 <= 1'b0;
  end else
  if (clocka) begin
    pb2 <= pb2_m;
  end
always @(clocka, clear_l, ac7)
  if (~clear_l) begin
    pb3_m <= 1'b0;
  end else
  if (~(clocka)) begin
    pb3_m <= ac7;
  end
always @(clocka, clear_l, pb3_m)
  if (~clear_l) begin
    pb3 <= 1'b0;
  end else
  if (clocka) begin
    pb3 <= pb3_m;
  end
// e3: sn7474 
always @(clockb, clear_l, ac8)
  if (~clear_l) begin
    pb4_m <= 1'b0;
  end else
  if (~(clockb)) begin
    pb4_m <= ac8;
  end
always @(clockb, clear_l, pb4_m)
  if (~clear_l) begin
    pb4 <= 1'b0;
  end else
  if (clockb) begin
    pb4 <= pb4_m;
  end
always @(clockb, clear_l, ac9)
  if (~clear_l) begin
    pb5_m <= 1'b0;
  end else
  if (~(clockb)) begin
    pb5_m <= ac9;
  end
always @(clockb, clear_l, pb5_m)
  if (~clear_l) begin
    pb5 <= 1'b0;
  end else
  if (clockb) begin
    pb5 <= pb5_m;
  end
// e4: sn7474 
always @(clockb, clear_l, ac10)
  if (~clear_l) begin
    pb6_m <= 1'b0;
  end else
  if (~(clockb)) begin
    pb6_m <= ac10;
  end
always @(clockb, clear_l, pb6_m)
  if (~clear_l) begin
    pb6 <= 1'b0;
  end else
  if (clockb) begin
    pb6 <= pb6_m;
  end
always @(clockb, clear_l, ac11)
  if (~clear_l) begin
    pb7_m <= 1'b0;
  end else
  if (~(clockb)) begin
    pb7_m <= ac11;
  end
always @(clockb, clear_l, pb7_m)
  if (~clear_l) begin
    pb7 <= 1'b0;
  end else
  if (clockb) begin
    pb7 <= pb7_m;
  end
// e5: sn7400 
assign clock_l = ~(iop4 & ~n_t_5x);
assign n_t_7x = ~(iop2 & ~n_t_5x);
assign iop_02 = ~(~(~n_t_5x & iop1));
// e6: sn7410 
assign clocka = ~clock_l;
assign clear_l = ~(~(initialize_l & feed_sw_l & n_t_7x));
assign clockb = ~clock_l;
// e7: sn7400 
assign n_t_1x = ~n_t_21x;
assign n_t_23x = ~(del_pun1 & n_t_22x);
assign n_t_22x = ~(pun_active_l & feed_sw_l);
// e8: sn7430 
assign n_t_5x = ~(mb4_lp_0_rp & mb5_lp_0_rp & mb6_lp_0_rp & mb8_lp_0_rp & mb3_lp_0_rp & mb3_lp_0_rp & mb8_lp_0_rp & mb7_lp_1_rp);
// e9: sn7440 
assign pun_done = ~n_t_1x;
// e10: sn7474 
always @(n_t_1x, clear_l, clock_l, 1'b0)
  if (~clear_l) begin
    n_t_26x_m <= 1'b0;
  end else
  if (~clock_l) begin
    n_t_26x_m <= 1'b1;
  end else
  if (~(n_t_1x)) begin
    n_t_26x_m <= 1'b0;
  end
always @(n_t_1x, clear_l, clock_l, n_t_26x_m)
  if (~clear_l) begin
    n_t_26x <= 1'b0;
  end else
  if (~clock_l) begin
    n_t_26x <= 1'b1;
  end else
  if (n_t_1x) begin
    n_t_26x <= n_t_26x_m;
  end
assign pun_active_l = ~n_t_26x;
always @(n_t_1x, clear_l, n_t_26x)
  if (~clear_l) begin
    pun_flag_m <= 1'b0;
  end else
  if (~(n_t_1x)) begin
    pun_flag_m <= n_t_26x;
  end
always @(n_t_1x, clear_l, pun_flag_m)
  if (~clear_l) begin
    pun_flag <= 1'b0;
  end else
  if (n_t_1x) begin
    pun_flag <= pun_flag_m;
  end
// e11: sn7460 
// n_t_11x = !(pun_flag & iop_02); 
// n_t_10x = !n_t_11x; 
// n_t_12x = !pun_flag; 
// n_t_9x = !n_t_12x; 
// e12: sn7460 
// n_t_6x = !n_t_4x; 
// !n_t_6x = !n_t_6x; 
// n_t_6x = n_t_6x; 
// n_t_19x = !n_t_6x; 
// open collector 'wire-or's 
assign n_t_10x = n_t_11x? ~n_t_11x: 1'bz;
assign n_t_11x = (pun_flag & iop_02)? 1'b0: 1'bz;
assign n_t_12x = pun_flag? ~pun_flag: 1'bz;
assign n_t_19x = n_t_6x? ~n_t_6x: 1'bz;
assign n_t_6x = n_t_4x
                 | (~(1'b0))? 1'b0: 1'bz;
assign n_t_9x = n_t_12x? ~n_t_12x: 1'bz;
endmodule