~/Verilog/bin/topld.pl M710B
info: cpol_use ne cpol_use15_5axial
info: cpol_use ne cpol_use15_5axial
info: cpol_use ne cpol_use15_5axial
info: cpol_use ne cpol_use15_5axial
info: cpol_use ne cpol_use15_5axial
info: 1n3606 ne diode_sod61b
warning: making d2/1n3606/ a connector
info: 1n3606 ne diode_sod61b
warning: making d3/1n3606/ a connector
info: 1n3606 ne diode_sod61b
warning: making d4/1n3606/ a connector
info: 7460n ne dil14
info: 7460n ne dil14
info: 7400n ne dil14
info: 7410n ne dil14
info: 7400n ne dil14
info: 7430n ne dil14
info: 7440n ne dil14
info: dec6534b ne _pnp_to92_ebc
warning: making q1/dec6534b/ a connector
info: dec6534b ne _pnp_to92_ebc
warning: making q2/dec6534b/ a connector
info: dec3009b ne _npn_to92_ebc
warning: making q3/dec3009b/ a connector
info: dec6534b ne _pnp_to92_ebc
warning: making q4/dec6534b/ a connector
info: dec3009b ne _npn_to92_ebc
warning: making q5/dec3009b/ a connector
info: dec3009b ne _npn_to92_ebc
warning: making q6/dec3009b/ a connector
info: double ne edge_con4
warning: making u$2/double/ a connector
warning: non-bypass capacitor deleted: c1
warning: non-bypass capacitor deleted: c18
warning: non-bypass capacitor deleted: c19
~/Verilog/bin/smaller.pl M710B.PLD >vv || (rm vv; exit 1)
4 signals were removed:
  n_t_16x: !iop_02
  n_t_2x: !clear_l
  n_t_3x: !n_t_6x
  n_t_8x: !n_t_5x
~/Verilog/bin/smaller.pl vv >M710BX.PLD || (rm M710BX.PLD; exit 1)
0 signals were removed:
~/Verilog/bin/cupl2v.pl M710BX.PLD >vv || (rm vv; exit 1)
mv vv M710B.v
rm M710BX.PLD