~/Verilog/bin/topld.pl M710H
info: cpol_use ne cpol_use20_8axial
info: cpol_use ne cpol_use20_8axial
info: cpol_use ne cpol_use20_8axial
info: cpol_use ne cpol_use20_8axial
info: cpol_use ne cpol_use20_8axial
info: 1n3606 ne 1n4004
warning: making d1/1n3606/ a connector
info: 1n3606 ne 1n4004
warning: making d2/1n3606/ a connector
info: 1n3606 ne 1n4004
warning: making d3/1n3606/ a connector
info: 9601 ne dil14
warning: making e10/9601/ a connector
info: 7430n ne dil14
info: 7440 ne 7420n
info: 7400n ne dil14
info: 9601 ne dil14
warning: making e15/9601/ a connector
info: 7404n ne dil14
info: 9601 ne dil14
warning: making e5/9601/ a connector
info: 7404n ne dil14
info: 7400n ne dil14
info: dec6534d ne 2n2905
warning: making q1/dec6534d/ a connector
info: dec6534d ne 2n2905
warning: making q2/dec6534d/ a connector
info: 50k ne trim_eu_rj6
warning: making r4/50k/ a connector
info: double ne edge_con4
warning: making u$2/double/ a connector
warning: non-bypass capacitor deleted: c22
warning: non-bypass capacitor deleted: c23
warning: non-bypass capacitor deleted: c24
warning: non-bypass capacitor deleted: c25
warning: non-bypass capacitor deleted: c26
~/Verilog/bin/smaller.pl M710H.PLD >vv || (rm vv; exit 1)
8 signals were removed:
  n_t_13x: !pb2
  n_t_14x: !pb3
  n_t_16x: !iop_02
  n_t_2x: !pb0
  n_t_3x: !pb1
  n_t_41x: !feed_sw_l
  n_t_6x: !clear_l
  n_t_8x: !n_t_5x
~/Verilog/bin/smaller.pl vv >M710HX.PLD || (rm M710HX.PLD; exit 1)
0 signals were removed:
~/Verilog/bin/cupl2v.pl M710HX.PLD >vv || (rm vv; exit 1)
mv vv M710H.v
rm M710HX.PLD