// this file is generated by topld.pl 
// please don't edit it. 
// input pins 
// output pins 
// internal nodes 
// code nodes 
// equations 
// c1: c_us 
// c2: c_us 
// c3: c_us 
// c4: c_us 
// c5: c_us 
// c6: c_us 
// c7: c_us 
// c8: c_us 
// c9: c_us 
// c10: c_us 
// c11: c_us 
// c12: c_us 
// c13: c_us 
// c14: c_us 
// c15: c_us 
// c16: c_us 
// c17: c_us 
// c18: cpol_use 
// c19: cpol_use 
// c20: cpol_use 
// c21: cpol_use 
// c22: cpol_use 
// c23: cpol_use 
// c24: cpol_use 
// c25: cpol_use 
// c26: c_us 
// e1: sn7474 
module m710x (n_t_26x, ac10, ac11, ac4, ac5, ac6, ac7, ac8, ac9, clear_l, clocka, clockb, del_pun1, del_pun2, feed_l, feed_sw_l, initialize_l, io_in_int_l, io_in_skip_l, iop1, iop2, iop4, iop_02, mb3_lp_0_rp, mb4_lp_0_rp, mb5_lp_0_rp, mb6_lp_0_rp, mb7_lp_1_rp, mb8_lp_0_rp, motor, n4_5ms, n4_sec, n_t_15x, n_t_1x, n_t_40x, n_t_49x, n_t_4x, n_t_56x, n_t_57x, n_t_59x, n_t_61x, n_t_63x, pb0, pb1, pb2, pb3, pb4, pb5, pb6, pb7, pun_active_l, pun_done, scr_active_l, sync_bias, sync_pun, sync_pun0);
input n_t_26x;
input ac10;
input ac11;
input ac4;
input ac5;
input ac6;
input ac7;
input ac8;
input ac9;
inout clear_l;
inout clocka;
inout clockb;
input del_pun1;
output reg del_pun2;
inout feed_l;
input feed_sw_l;
input initialize_l;
output io_in_int_l;
output io_in_skip_l;
input iop1;
input iop2;
input iop4;
inout iop_02;
input mb3_lp_0_rp;
input mb4_lp_0_rp;
input mb5_lp_0_rp;
input mb6_lp_0_rp;
input mb7_lp_1_rp;
input mb8_lp_0_rp;
input motor;
output n4_5ms;
output n4_sec;
input n_t_15x;
inout n_t_1x;
output n_t_40x;
output n_t_49x;
output n_t_4x;
output n_t_56x;
output n_t_57x;
output n_t_59x;
input n_t_61x;
output n_t_63x;
output reg pb0;
output reg pb1;
output reg pb2;
output reg pb3;
output pb4;
output pb5;
output pb6;
output pb7;
inout reg pun_active_l;
output pun_done;
output scr_active_l;
output sync_bias;
output sync_pun;
input sync_pun0;

reg del_pun2_m;
reg n_t_10x_m;
reg n_t_11x_m;
reg n_t_12x_m;
reg n_t_53x_m;
reg n_t_9x_m;
reg pb0_m;
reg pb1_m;
reg pb2_m;
reg pb3_m;
reg pun_active_l_m;
reg pun_flag_m;

reg n_t_12x;
reg n_t_11x;
reg n_t_9x;
reg n_t_10x;
reg pun_flag;
reg n_t_53x;
wire clockb_l;
wire n_t_54x;
wire n_t_5x;
wire n_t_7x;
always @(clockb, n_t_26x, feed_l, ac11)
  if (~n_t_26x) begin
    n_t_12x_m <= 1'b0;
  end else
  if (~feed_l) begin
    n_t_12x_m <= 1'b1;
  end else
  if (~(clockb)) begin
    n_t_12x_m <= ~ac11;
  end
always @(clockb, n_t_26x, feed_l, n_t_12x_m)
  if (~n_t_26x) begin
    n_t_12x <= 1'b0;
  end else
  if (~feed_l) begin
    n_t_12x <= 1'b1;
  end else
  if (clockb) begin
    n_t_12x <= n_t_12x_m;
  end
always @(clockb, n_t_26x, feed_l, ac10)
  if (~n_t_26x) begin
    n_t_11x_m <= 1'b0;
  end else
  if (~feed_l) begin
    n_t_11x_m <= 1'b1;
  end else
  if (~(clockb)) begin
    n_t_11x_m <= ~ac10;
  end
always @(clockb, n_t_26x, feed_l, n_t_11x_m)
  if (~n_t_26x) begin
    n_t_11x <= 1'b0;
  end else
  if (~feed_l) begin
    n_t_11x <= 1'b1;
  end else
  if (clockb) begin
    n_t_11x <= n_t_11x_m;
  end
// e2: sn7474 
always @(clockb, n_t_26x, feed_l, ac8)
  if (~n_t_26x) begin
    n_t_9x_m <= 1'b0;
  end else
  if (~feed_l) begin
    n_t_9x_m <= 1'b1;
  end else
  if (~(clockb)) begin
    n_t_9x_m <= ~ac8;
  end
always @(clockb, n_t_26x, feed_l, n_t_9x_m)
  if (~n_t_26x) begin
    n_t_9x <= 1'b0;
  end else
  if (~feed_l) begin
    n_t_9x <= 1'b1;
  end else
  if (clockb) begin
    n_t_9x <= n_t_9x_m;
  end
always @(clockb, n_t_26x, feed_l, ac9)
  if (~n_t_26x) begin
    n_t_10x_m <= 1'b0;
  end else
  if (~feed_l) begin
    n_t_10x_m <= 1'b1;
  end else
  if (~(clockb)) begin
    n_t_10x_m <= ~ac9;
  end
always @(clockb, n_t_26x, feed_l, n_t_10x_m)
  if (~n_t_26x) begin
    n_t_10x <= 1'b0;
  end else
  if (~feed_l) begin
    n_t_10x <= 1'b1;
  end else
  if (clockb) begin
    n_t_10x <= n_t_10x_m;
  end
// e3: sn7404 
assign pb7 = ~n_t_12x;
assign pb4 = ~n_t_9x;
assign pb5 = ~n_t_10x;
assign pb6 = ~n_t_11x;
// e4: sn7474 
always @(clocka, n_t_26x, feed_l, ac5)
  if (~(~n_t_26x)) begin
    pb1_m <= 1'b0;
  end else
  if (~(~feed_l)) begin
    pb1_m <= 1'b1;
  end else
  if (~(~clocka)) begin
    pb1_m <= ~(~ac5);
  end
always @(clocka, n_t_26x, feed_l, pb1_m)
  if (~(~n_t_26x)) begin
    pb1 <= 1'b0;
  end else
  if (~(~feed_l)) begin
    pb1 <= 1'b1;
  end else
  if (~clocka) begin
    pb1 <= pb1_m;
  end
always @(clocka, n_t_26x, feed_l, ac4)
  if (~(~n_t_26x)) begin
    pb0_m <= 1'b0;
  end else
  if (~(~feed_l)) begin
    pb0_m <= 1'b1;
  end else
  if (~(~clocka)) begin
    pb0_m <= ~(~ac4);
  end
always @(clocka, n_t_26x, feed_l, pb0_m)
  if (~(~n_t_26x)) begin
    pb0 <= 1'b0;
  end else
  if (~(~feed_l)) begin
    pb0 <= 1'b1;
  end else
  if (~clocka) begin
    pb0 <= pb0_m;
  end
// e6: sn7404 
assign clocka = ~clockb_l;
assign clockb = ~clockb_l;
// e7: sn7474 
always @(clocka, n_t_26x, feed_l, ac7)
  if (~(~n_t_26x)) begin
    pb3_m <= 1'b0;
  end else
  if (~(~feed_l)) begin
    pb3_m <= 1'b1;
  end else
  if (~(~clocka)) begin
    pb3_m <= ~(~ac7);
  end
always @(clocka, n_t_26x, feed_l, pb3_m)
  if (~(~n_t_26x)) begin
    pb3 <= 1'b0;
  end else
  if (~(~feed_l)) begin
    pb3 <= 1'b1;
  end else
  if (~clocka) begin
    pb3 <= pb3_m;
  end
always @(clocka, n_t_26x, feed_l, ac6)
  if (~(~n_t_26x)) begin
    pb2_m <= 1'b0;
  end else
  if (~(~feed_l)) begin
    pb2_m <= 1'b1;
  end else
  if (~(~clocka)) begin
    pb2_m <= ~(~ac6);
  end
always @(clocka, n_t_26x, feed_l, pb2_m)
  if (~(~n_t_26x)) begin
    pb2 <= 1'b0;
  end else
  if (~(~feed_l)) begin
    pb2 <= 1'b1;
  end else
  if (~clocka) begin
    pb2 <= pb2_m;
  end
// e8: sn7400 
assign clear_l = ~(~(n_t_7x & initialize_l));
assign iop_02 = ~(~(~n_t_5x & iop1));
assign n_t_7x = ~(iop2 & ~n_t_5x);
assign clockb_l = ~(iop4 & ~n_t_5x);
// e9: sn7474 
always @(n_t_15x, clockb_l, clear_l, 1'b1)
  if (~clockb_l) begin
    pun_active_l_m <= 1'b0;
  end else
  if (~clear_l) begin
    pun_active_l_m <= 1'b1;
  end else
  if (~(n_t_15x)) begin
    pun_active_l_m <= 1'b1;
  end
always @(n_t_15x, clockb_l, clear_l, pun_active_l_m)
  if (~clockb_l) begin
    pun_active_l <= 1'b0;
  end else
  if (~clear_l) begin
    pun_active_l <= 1'b1;
  end else
  if (n_t_15x) begin
    pun_active_l <= pun_active_l_m;
  end
always @(pun_active_l, clear_l, n_t_26x, n_t_26x)
  if (~clear_l) begin
    pun_flag_m <= 1'b0;
  end else
  if (~n_t_26x) begin
    pun_flag_m <= 1'b1;
  end else
  if (~(pun_active_l)) begin
    pun_flag_m <= n_t_26x;
  end
always @(pun_active_l, clear_l, n_t_26x, pun_flag_m)
  if (~clear_l) begin
    pun_flag <= 1'b0;
  end else
  if (~n_t_26x) begin
    pun_flag <= 1'b1;
  end else
  if (pun_active_l) begin
    pun_flag <= pun_flag_m;
  end
// e11: sn7430 
assign n_t_5x = ~(mb3_lp_0_rp & mb7_lp_1_rp & mb5_lp_0_rp & mb8_lp_0_rp & mb6_lp_0_rp & mb4_lp_0_rp & mb4_lp_0_rp);
// e12: sn7401 
// pun_done = !n_t_15x; 
// pun_done = !n_t_15x; 
// io_in_int_l = !pun_flag; 
// io_in_skip_l = !(pun_flag & iop_02); 
// e13: sn7440 
assign feed_l = ~(n_t_53x & ~feed_sw_l & ~feed_sw_l & ~feed_sw_l);
assign scr_active_l = ~motor;
// e14: sn7400 
assign n_t_54x = ~(del_pun1 & n_t_1x);
assign n_t_1x = ~(feed_l & pun_active_l);
// e16: sn7474 
always @(n_t_61x, motor, n_t_26x, n_t_26x)
  if (~motor) begin
    del_pun2_m <= 1'b0;
  end else
  if (~n_t_26x) begin
    del_pun2_m <= 1'b1;
  end else
  if (~(n_t_61x)) begin
    del_pun2_m <= n_t_26x;
  end
always @(n_t_61x, motor, n_t_26x, del_pun2_m)
  if (~motor) begin
    del_pun2 <= 1'b0;
  end else
  if (~n_t_26x) begin
    del_pun2 <= 1'b1;
  end else
  if (n_t_61x) begin
    del_pun2 <= del_pun2_m;
  end
always @(sync_pun0, n_t_26x, n_t_15x, n_t_54x)
  if (~n_t_26x) begin
    n_t_53x_m <= 1'b0;
  end else
  if (~n_t_15x) begin
    n_t_53x_m <= 1'b1;
  end else
  if (~(sync_pun0)) begin
    n_t_53x_m <= n_t_54x;
  end
always @(sync_pun0, n_t_26x, n_t_15x, n_t_53x_m)
  if (~n_t_26x) begin
    n_t_53x <= 1'b0;
  end else
  if (~n_t_15x) begin
    n_t_53x <= 1'b1;
  end else
  if (sync_pun0) begin
    n_t_53x <= n_t_53x_m;
  end
assign n_t_4x = ~n_t_53x;
// open collector 'wire-or's 
assign io_in_int_l = pun_flag? ~pun_flag: 1'bz;
assign io_in_skip_l = (pun_flag & iop_02)? 1'b0: 1'bz;
assign pun_done = n_t_15x? ~n_t_15x: 1'bz;
endmodule