// this file is generated by topld.pl 
// please don't edit it. 
// input pins 
// output pins 
// internal nodes 
// code nodes 
// equations 
// c1: c_us 
// c2: c_us 
// c3: c_us 
// c4: cpol_use 
// e1: sn7404 
// e2: sn7400 
module m7347b (d, e, f, h, j, n15v, n_t_26x);
input d;
input e;
input f;
input h;
input j;
output n15v;
output reg n_t_26x;

reg n_t_26x_m;

wire n_t_6x;
wire n_t_9x;
assign n_t_6x = ~(d & ~e);
assign n_t_9x = ~(f & ~h);
// e3: sn7474 
always @(n_t_6x, j, n_t_9x, 1'b0)
  if (~j) begin
    n_t_26x_m <= 1'b0;
  end else
  if (n_t_9x) begin
    n_t_26x_m <= 1'b1;
  end else
  if (~(n_t_6x)) begin
    n_t_26x_m <= 1'b0;
  end
always @(n_t_6x, j, n_t_9x, n_t_26x_m)
  if (~j) begin
    n_t_26x <= 1'b0;
  end else
  if (n_t_9x) begin
    n_t_26x <= 1'b1;
  end else
  if (n_t_6x) begin
    n_t_26x <= n_t_26x_m;
  end
// open collector 'wire-or's 
endmodule