// this file is generated by topld.pl 
// please don't edit it. 
// input pins 
// output pins 
// internal nodes 
// code nodes 
// equations 
// c1: c_us 
// c2: c_us 
// c3: c_us 
// c4: c_us 
// c5: c_us 
// c6: c_us 
// c7: c_us 
// c8: c_us 
// c9: c_us 
// c10: c_us 
// c11: c_us 
// c12: c_us 
// c13: cpol_use 
// c14: cpol_use 
// c15: cpol_use 
// c16: cpol_use 
// e1: sn74821 
module m7672n (af1, aj1, ak1, al1, am1, ar2, as2, at2, au2, av2, bd1, be1, bh1, bh2, bj1, bj2, bl1, bm1, br2, bs2, bt2, bv1, n3v, n_t_13x, n_t_14x, n_t_17x, n_t_18x, n_t_5x, n_t_6x, n_t_8x, ad2, ae2, af2, ah1, ah2, aj2, ak2, al2, am2, an1, an2, ap1, ap2, ar1, as1, au1, av1, ba1, bb1, bf1, bf2, bk1, bk2, bl2, bm2, bn1, bn2, bp1, bp2, br1, bs1, bu1, bu2, n_t_12x, n_t_16x, n_t_1x, n_t_2x, n_t_3x, n_t_7x);
input af1;
input aj1;
input ak1;
input al1;
input am1;
input ar2;
input as2;
input at2;
input au2;
input av2;
input bd1;
input be1;
input bh1;
input bh2;
input bj1;
input bj2;
output bl1;
output bm1;
input br2;
input bs2;
input bt2;
output bv1;
input n3v;
output n_t_13x;
output n_t_14x;
output n_t_17x;
output n_t_18x;
output n_t_5x;
output n_t_6x;
output n_t_8x;
output reg ad2;
output reg ae2;
output reg af2;
input ah1;
output reg ah2;
output reg aj2;
output reg ak2;
output reg al2;
output reg am2;
output an1;
inout reg an2;
output ap1;
output reg ap2;
inout reg ar1;
output as1;
output au1;
inout reg av1;
inout reg ba1;
inout reg bb1;
input bf1;
inout bf2;
output bk1;
output bk2;
output bl2;
inout reg bm2;
output bn1;
inout reg bn2;
inout reg bp1;
inout bp2;
inout br1;
input bs1;
input bu1;
inout bu2;
output n_t_12x;
output n_t_16x;
inout n_t_1x;
inout n_t_2x;
inout n_t_3x;
output n_t_7x;

reg ar1_m;
reg av1_m;
reg ba1_m;
reg bb1_m;
reg bm2_m;
reg bn2_m;
reg bp1_m;
reg gdollar_0_m;

reg gdollar_0;
wire n_t_10x;
wire n_t_4x;
wire n_t_9x;
always @(negedge aj1)
  if (~aj1) begin
    ap2 <= ~n_t_1x;
  end
always @(negedge aj1)
  if (~aj1) begin
    an2 <= ~ak1;
  end
always @(negedge aj1)
  if (~aj1) begin
    am2 <= ~n_t_2x;
  end
always @(negedge aj1)
  if (~aj1) begin
    al2 <= ~al1;
  end
always @(negedge aj1)
  if (~aj1) begin
    ak2 <= ~am1;
  end
always @(negedge aj1)
  if (~aj1) begin
    ad2 <= ~av2;
  end
always @(negedge aj1)
  if (~aj1) begin
    ae2 <= ~au2;
  end
always @(negedge aj1)
  if (~aj1) begin
    af2 <= ~at2;
  end
always @(negedge aj1)
  if (~aj1) begin
    ah2 <= ~as2;
  end
always @(negedge aj1)
  if (~aj1) begin
    aj2 <= ~ar2;
  end
// e2: sn7401 
// n_t_3x = !(bf1 & an2); 
// n_t_7x = !ah1; 
// n_t_2x = !(n_t_1x & af1); 
// n_t_1x = !(ak1 & af1); 
// e4: sn7475 
always @(bf1, bj1, bf1, bj1, 1'b0)
  if (bf1 & ~bj1) begin
    bb1_m <= 1'b0;
  end else
  if (bf1 & bj1) begin
    bb1_m <= 1'b1;
  end else
  if (~(1'b0)) begin
    bb1_m <= 1'b0;
  end
always @(bf1, bj1, bf1, bj1, bb1_m)
  if (bf1 & ~bj1) begin
    bb1 <= 1'b0;
  end else
  if (bf1 & bj1) begin
    bb1 <= 1'b1;
  end else
  if (1'b0) begin
    bb1 <= bb1_m;
  end
always @(bf1, bh1, bf1, bh1, 1'b0)
  if (bf1 & ~bh1) begin
    ar1_m <= 1'b0;
  end else
  if (bf1 & bh1) begin
    ar1_m <= 1'b1;
  end else
  if (~(1'b0)) begin
    ar1_m <= 1'b0;
  end
always @(bf1, bh1, bf1, bh1, ar1_m)
  if (bf1 & ~bh1) begin
    ar1 <= 1'b0;
  end else
  if (bf1 & bh1) begin
    ar1 <= 1'b1;
  end else
  if (1'b0) begin
    ar1 <= ar1_m;
  end
always @(bf1, be1, bf1, be1, 1'b0)
  if (bf1 & ~be1) begin
    av1_m <= 1'b0;
  end else
  if (bf1 & be1) begin
    av1_m <= 1'b1;
  end else
  if (~(1'b0)) begin
    av1_m <= 1'b0;
  end
always @(bf1, be1, bf1, be1, av1_m)
  if (bf1 & ~be1) begin
    av1 <= 1'b0;
  end else
  if (bf1 & be1) begin
    av1 <= 1'b1;
  end else
  if (1'b0) begin
    av1 <= av1_m;
  end
always @(bf1, bd1, bf1, bd1, 1'b0)
  if (bf1 & ~bd1) begin
    ba1_m <= 1'b0;
  end else
  if (bf1 & bd1) begin
    ba1_m <= 1'b1;
  end else
  if (~(1'b0)) begin
    ba1_m <= 1'b0;
  end
always @(bf1, bd1, bf1, bd1, ba1_m)
  if (bf1 & ~bd1) begin
    ba1 <= 1'b0;
  end else
  if (bf1 & bd1) begin
    ba1 <= 1'b1;
  end else
  if (1'b0) begin
    ba1 <= ba1_m;
  end
assign bk1 = ~bb1;
assign as1 = ~ar1;
assign au1 = ~av1;
assign bf2 = ~ba1;
// e5: sn7420 
assign n_t_12x = ~(bu1 & bf2 & bh2 & bj2);
assign n_t_16x = ~(n_t_10x & n_t_9x & n_t_4x & n3v);
// e6: sn7486 
assign n_t_4x = bs2
                 ^ bp2;
assign bl2 = n_t_3x
              ^ n3v;
assign n_t_10x = br2
                  ^ br1;
assign n_t_9x = bu2
                 ^ bt2;
// e8: sn7475 
always @(bs1, bt2, bs1, bt2, 1'b0)
  if (bs1 & ~bt2) begin
    bm2_m <= 1'b0;
  end else
  if (bs1 & bt2) begin
    bm2_m <= 1'b1;
  end else
  if (~(1'b0)) begin
    bm2_m <= 1'b0;
  end
always @(bs1, bt2, bs1, bt2, bm2_m)
  if (bs1 & ~bt2) begin
    bm2 <= 1'b0;
  end else
  if (bs1 & bt2) begin
    bm2 <= 1'b1;
  end else
  if (1'b0) begin
    bm2 <= bm2_m;
  end
always @(bs1, bs2, bs1, bs2, 1'b0)
  if (bs1 & ~bs2) begin
    bn2_m <= 1'b0;
  end else
  if (bs1 & bs2) begin
    bn2_m <= 1'b1;
  end else
  if (~(1'b0)) begin
    bn2_m <= 1'b0;
  end
always @(bs1, bs2, bs1, bs2, bn2_m)
  if (bs1 & ~bs2) begin
    bn2 <= 1'b0;
  end else
  if (bs1 & bs2) begin
    bn2 <= 1'b1;
  end else
  if (1'b0) begin
    bn2 <= bn2_m;
  end
always @(bs1, br2, bs1, br2, 1'b0)
  if (bs1 & ~br2) begin
    bp1_m <= 1'b0;
  end else
  if (bs1 & br2) begin
    bp1_m <= 1'b1;
  end else
  if (~(1'b0)) begin
    bp1_m <= 1'b0;
  end
always @(bs1, br2, bs1, br2, bp1_m)
  if (bs1 & ~br2) begin
    bp1 <= 1'b0;
  end else
  if (bs1 & br2) begin
    bp1 <= 1'b1;
  end else
  if (1'b0) begin
    bp1 <= bp1_m;
  end
always @(bs1, n3v, bs1, n3v, 1'b0)
  if (bs1 & ~n3v) begin
    gdollar_0_m <= 1'b0;
  end else
  if (bs1 & n3v) begin
    gdollar_0_m <= 1'b1;
  end else
  if (~(1'b0)) begin
    gdollar_0_m <= 1'b0;
  end
always @(bs1, n3v, bs1, n3v, gdollar_0_m)
  if (bs1 & ~n3v) begin
    gdollar_0 <= 1'b0;
  end else
  if (bs1 & n3v) begin
    gdollar_0 <= 1'b1;
  end else
  if (1'b0) begin
    gdollar_0 <= gdollar_0_m;
  end
assign bu2 = ~bm2;
assign bp2 = ~bn2;
assign br1 = ~bp1;
// ic1: sn7404 
// open collector 'wire-or's 
assign n_t_1x = (ak1 & af1)? 1'b0: 1'bz;
assign n_t_2x = (n_t_1x & af1)? 1'b0: 1'bz;
assign n_t_3x = (bf1 & an2)? 1'b0: 1'bz;
assign n_t_7x = ah1? ~ah1: 1'bz;
endmodule