~/Verilog/bin/topld.pl M7672n
info: 1n4148 ne do35_10
warning: making d1/1n4148/ a connector
info: 1n4148 ne do35_10
warning: making d2/1n4148/ a connector
info: 74821nt ne dil24_6
info: 7401n ne dil14
info: 74123n ne dil16
warning: making e3/sn74123/ a connector
info: 7475n ne dil16
info: 7420n ne dil14
info: 7486n ne dil14
info: 74123n ne dil16
warning: making e7/sn74123/ a connector
info: 7475n ne dil16
info: double ne edge_con4
warning: making edge/double/ a connector
info: 7404n ne dil14
warning: non-bypass capacitor deleted: c9
warning: non-bypass capacitor deleted: c10
warning: non-bypass capacitor deleted: c11
warning: non-bypass capacitor deleted: c12
warning: non-bypass capacitor deleted: c15
warning: non-bypass capacitor deleted: c16
!oe is 'b'0
~/Verilog/bin/smaller.pl M7672n.PLD >vv || (rm vv; exit 1)
1 signals were removed:
  n_t_11x: !aj1
~/Verilog/bin/smaller.pl vv >M7672nX.PLD || (rm M7672nX.PLD; exit 1)
0 signals were removed:
~/Verilog/bin/cupl2v.pl M7672nX.PLD >vv || (rm vv; exit 1)
mv vv M7672n.v
rm M7672nX.PLD