// this file is generated by topld.pl 
// please don't edit it. 
// input pins 
// output pins 
// internal nodes 
// code nodes 
// equations 
// c1: cpol_use 
// c2: cpol_use 
// c3: cpol_use 
// c4: c_us 
// c5: c_us 
// c6: c_us 
// c7: c_us 
// c8: c_us 
// c9: c_us 
// c10: c_us 
// c11: c_us 
// c12: c_us 
// c13: c_us 
// c14: c_us 
// c15: c_us 
// e1: n8881n 
// ma03_l = !(cpma3 & !mac_l); 
// ma02_l = !(!mac_l & cpma2); 
// ma00_l = !(!mac_l & cpma0); 
// ma01_l = !(!mac_l & cpma1); 
// e2: n8881n 
// md03_l = !(mb03 & md_dir_l); 
// md02_l = !(md_dir_l & mb02); 
// md00_l = !(md_dir_l & mb00); 
// md01_l = !(md_dir_l & mb01); 
// e3: dec8271 
module m8300b (ac2bus_l, ac_load_l, adlk_l, al2mq_ena_l, carry_in_l, cpma_load_l, data_f, data_t, en0, en1, en2, left_l, mac_l, mb_load_l, mq2bus_l, mq_data_l, mq_load_l, pagez, pc_load_l, right_l, shl_ena_l, twice_l, ac00, ac01, ac02, ac03, ac04_11eq0_l, ad00_l, ad01_l, ad10_l, ad11_l, carry_out_l, data00, data01, data02, data03, data04, data05, data06, data07, data08, data09, data10, data11, init, ma00_l, ma01_l, ma02_l, ma03_l, ma04_l, ma05_l, ma06_l, ma07_l, ma08_l, ma09_l, ma10_l, ma11_l, md00_l, md01_l, md02_l, md03_l, md04_l, md05_l, md06_l, md07_l, md08_l, md09_l, md10_l, md11_l, md_dir_l, mq00_03eq0_l, mq00_l, mq04_11eq0_l, mq10_l, mq11_l);
input ac2bus_l;
input ac_load_l;
input adlk_l;
input al2mq_ena_l;
input carry_in_l;
input cpma_load_l;
input data_f;
input data_t;
input en0;
output en1;
input en2;
input left_l;
input mac_l;
input mb_load_l;
input mq2bus_l;
input mq_data_l;
input mq_load_l;
input pagez;
input pc_load_l;
input right_l;
input shl_ena_l;
input twice_l;
inout reg ac00;
inout reg ac01;
inout reg ac02;
inout reg ac03;
output ac04_11eq0_l;
inout ad00_l;
inout ad01_l;
inout ad10_l;
inout ad11_l;
output carry_out_l;
inout data00;
inout data01;
inout data02;
inout data03;
inout data04;
inout data05;
inout data06;
inout data07;
inout data08;
inout data09;
inout data10;
inout data11;
input init;
inout ma00_l;
inout ma01_l;
inout ma02_l;
inout ma03_l;
inout ma04_l;
inout ma05_l;
inout ma06_l;
inout ma07_l;
inout ma08_l;
inout ma09_l;
inout ma10_l;
inout ma11_l;
inout md00_l;
inout md01_l;
inout md02_l;
inout md03_l;
inout md04_l;
inout md05_l;
inout md06_l;
inout md07_l;
inout md08_l;
inout md09_l;
inout md10_l;
inout md11_l;
input md_dir_l;
output mq00_03eq0_l;
inout reg mq00_l;
output mq04_11eq0_l;
inout reg mq10_l;
inout reg mq11_l;

reg ac00_m;
reg ac01_m;
reg ac02_m;
reg ac03_m;
reg ac04_m;
reg ac05_m;
reg ac06_m;
reg ac07_m;
reg ac08_m;
reg ac09_m;
reg ac10_m;
reg ac11_m;

reg mb02;
reg mb03;
reg mb01;
reg mb00;
reg cpma3;
reg cpma2;
reg cpma0;
reg cpma1;
reg mq01_l;
reg mq02_l;
reg mq03_l;
reg pc03_l;
reg pc02_l;
reg pc00_l;
reg pc01_l;
reg mb06;
reg mb07;
reg mb05;
reg mb04;
reg cpma7;
reg cpma6;
reg cpma4;
reg cpma5;
reg ac06;
reg ac07;
reg ac05;
reg ac04;
reg mq04_l;
reg mq05_l;
reg mq06_l;
reg mq07_l;
reg pc07_l;
reg pc06_l;
reg pc04_l;
reg pc05_l;
reg cpma10;
reg cpma11;
reg cpma8;
reg cpma9;
reg pc08_l;
reg pc09_l;
reg pc10_l;
reg pc11_l;
reg mb10;
reg mb11;
reg mb09;
reg mb08;
reg mq08_l;
reg mq09_l;
reg ac10;
reg ac11;
reg ac09;
reg ac08;
wire a00_l;
wire a01_l;
wire a02_l;
wire a03_l;
wire a04_l;
wire a05_l;
wire a06_l;
wire a07_l;
wire a08_l;
wire a09_l;
wire a10_l;
wire a11_l;
wire ad02_l;
wire ad03_l;
wire ad04_l;
wire ad05_l;
wire ad06_l;
wire ad07_l;
wire ad08_l;
wire ad09_l;
wire and00_l;
wire and01_l;
wire and02_l;
wire and03_l;
wire and04_l;
wire and05_l;
wire and06_l;
wire and07_l;
wire and08_l;
wire and09_l;
wire and10_l;
wire and11_l;
wire b00_l;
wire b01_l;
wire b02_l;
wire b03_l;
wire b04_l;
wire b05_l;
wire b06_l;
wire b07_l;
wire b08_l;
wire b09_l;
wire b10_l;
wire b11_l;
wire carry04_l;
wire carry08_l;
wire n_t_10x;
wire n_t_11x;
wire n_t_13x;
wire n_t_18x;
wire n_t_19x;
wire n_t_20x;
wire n_t_21x;
wire n_t_22x;
wire n_t_23x;
wire n_t_24x;
wire n_t_28x;
wire n_t_29x;
wire n_t_2x;
wire n_t_30x;
wire n_t_31x;
wire n_t_36x;
wire n_t_37x;
wire n_t_38x;
wire n_t_39x;
wire n_t_3x;
wire n_t_40x;
wire n_t_42x;
wire n_t_43x;
wire n_t_4x;
wire n_t_6x;
wire n_t_7x;
wire n_t_8x;
wire n_t_9x;
wire pg00_l;
wire pg01_l;
wire pg02_l;
wire pg03_l;
wire pg04_l;
wire regbus00_l;
wire regbus01_l;
wire regbus02_l;
wire regbus03_l;
wire regbus04_l;
wire regbus05_l;
wire regbus06_l;
wire regbus07_l;
wire regbus08_l;
wire regbus09_l;
wire regbus10_l;
wire regbus11_l;
always @(negedge mb_load_l)
  if (~mb_load_l) begin
    mb02 <= ~regbus02_l;
  end
always @(negedge mb_load_l)
  if (~mb_load_l) begin
    mb03 <= ~regbus03_l;
  end
always @(negedge mb_load_l)
  if (~mb_load_l) begin
    mb01 <= ~regbus01_l;
  end
always @(negedge mb_load_l)
  if (~mb_load_l) begin
    mb00 <= ~regbus00_l;
  end
// e4: dec8271 
always @(negedge cpma_load_l)
  if (~cpma_load_l) begin
    cpma3 <= ~regbus03_l;
  end
always @(negedge cpma_load_l)
  if (~cpma_load_l) begin
    cpma2 <= ~regbus02_l;
  end
always @(negedge cpma_load_l)
  if (~cpma_load_l) begin
    cpma0 <= ~regbus00_l;
  end
always @(negedge cpma_load_l)
  if (~cpma_load_l) begin
    cpma1 <= ~regbus01_l;
  end
// e5: mc8266 
assign pg02_l = ~(~ma02_l & ~pagez
                   |  & pagez & ~pagez);
assign pg03_l = ~(~ma03_l & ~pagez
                   |  & pagez & ~pagez);
assign pg01_l = ~(~ma01_l & ~pagez
                   | pagez & ~pagez);
assign pg00_l = ~(~ma00_l & ~pagez
                   | pagez & ~pagez);
// e6: sn74151 
assign regbus00_l = ad00_l & right_l & left_l & twice_l
                     | ad06_l & right_l & left_l & ~twice_l
                     | ad01_l & right_l & ~left_l & twice_l
                     | ad02_l & right_l & ~left_l & ~twice_l
                     | adlk_l & ~right_l & left_l & twice_l
                     | ad11_l & ~right_l & left_l & ~twice_l
                     | and00_l & ~right_l & ~left_l & twice_l
                     | pg00_l & ~right_l & ~left_l & ~twice_l;
// e7: dec8235 
// data03 = !(!mq03_l & !mq2bus_l
//       # ac03 & !ac2bus_l); 
// data02 = !(!mq02_l & !mq2bus_l
//       # ac02 & !ac2bus_l); 
// data00 = !(!mq00_l & !mq2bus_l
//       # ac00 & !ac2bus_l); 
// data01 = !(!mq01_l & !mq2bus_l
//       # ac01 & !ac2bus_l); 
// e8: dec8271 
always @(ac_load_l, init, regbus02_l)
  if (init) begin
    ac02_m <= 1'b0;
  end else
  if (~(~ac_load_l)) begin
    ac02_m <= ~regbus02_l;
  end
always @(ac_load_l, init, ac02_m)
  if (init) begin
    ac02 <= 1'b0;
  end else
  if (~ac_load_l) begin
    ac02 <= ac02_m;
  end
always @(ac_load_l, init, regbus03_l)
  if (init) begin
    ac03_m <= 1'b0;
  end else
  if (~(~ac_load_l)) begin
    ac03_m <= ~regbus03_l;
  end
always @(ac_load_l, init, ac03_m)
  if (init) begin
    ac03 <= 1'b0;
  end else
  if (~ac_load_l) begin
    ac03 <= ac03_m;
  end
always @(ac_load_l, init, regbus01_l)
  if (init) begin
    ac01_m <= 1'b0;
  end else
  if (~(~ac_load_l)) begin
    ac01_m <= ~regbus01_l;
  end
always @(ac_load_l, init, ac01_m)
  if (init) begin
    ac01 <= 1'b0;
  end else
  if (~ac_load_l) begin
    ac01 <= ac01_m;
  end
always @(ac_load_l, init, regbus00_l)
  if (init) begin
    ac00_m <= 1'b0;
  end else
  if (~(~ac_load_l)) begin
    ac00_m <= ~regbus00_l;
  end
always @(ac_load_l, init, ac00_m)
  if (init) begin
    ac00 <= 1'b0;
  end else
  if (~ac_load_l) begin
    ac00 <= ac00_m;
  end
// e9: sn74153 
assign n_t_9x = (~pad{1} & ~en2 & pc00_l
                         | ~pad{1} & en2 & md00_l
                         | pad{1} & ~en2 & mq00_l
                         | pad{1} & en2 & ma00_l);
assign n_t_8x = (~pad{1} & ~en2 & pc01_l
                         | ~pad{1} & en2 & md01_l
                         | pad{1} & ~en2 & mq01_l
                         | pad{1} & en2 & ma01_l);
// e10: sn7487 
assign b02_l = data_t & ~data_f
                | data_f & data02
                | ~data_f & ~data02;
assign b03_l = data_t & ~data_f
                | data_f & data03
                | ~data_f & ~data03;
assign b01_l = data_t & ~data_f
                | data_f & data01
                | ~data_f & ~data01;
assign b00_l = data_t & ~data_f
                | data_f & data00
                | ~data_f & ~data00;
// e11: sn74151 
assign regbus01_l = ad01_l & right_l & left_l & twice_l
                     | ad07_l & right_l & left_l & ~twice_l
                     | ad02_l & right_l & ~left_l & twice_l
                     | ad03_l & right_l & ~left_l & ~twice_l
                     | ad00_l & ~right_l & left_l & twice_l
                     | adlk_l & ~right_l & left_l & ~twice_l
                     | and01_l & ~right_l & ~left_l & twice_l
                     | pg01_l & ~right_l & ~left_l & ~twice_l;
// e12: mc8266 
assign n_t_2x = ~(~mq02_l & ~shl_ena_l
                   | ac01 & shl_ena_l & ~al2mq_ena_l);
assign n_t_6x = ~(~mq01_l & ~shl_ena_l
                   | ac00 & shl_ena_l & ~al2mq_ena_l);
assign n_t_23x = ~(~mq04_l & ~shl_ena_l
                    | ac03 & shl_ena_l & ~al2mq_ena_l);
assign n_t_24x = ~(~mq03_l & ~shl_ena_l
                    | ac02 & shl_ena_l & ~al2mq_ena_l);
// e13: sn7400 
assign and00_l = ~(mb00 & ac00);
assign and01_l = ~(ac01 & mb01);
assign and03_l = ~(mb03 & ac03);
assign and02_l = ~(mb02 & ac02);
// e14: mc8266 
assign a02_l = ~(~n_t_21x & ~en0
                  | n_t_21x & en0 & ~en0);
assign a03_l = ~(~n_t_13x & ~en0
                  | n_t_13x & en0 & ~en0);
assign a01_l = ~(~n_t_8x & ~en0
                  | n_t_8x & en0 & ~en0);
assign a00_l = ~(~n_t_9x & ~en0
                  | n_t_9x & en0 & ~en0);
// e15: sn7483 
assign ad03_l = a03_l
                 ^ b03_l
                 ^ carry04_l;
assign gdollar_0 = a03_l & b03_l
                    | a03_l & carry04_l
                    | pad{11} & carry04_l;
assign ad02_l = a02_l
                 ^ b02_l
                 ^ gdollar_0;
assign gdollar_1 = a02_l & b02_l
                    | a02_l & gdollar_0
                    | pad{7} & gdollar_0;
assign ad01_l = b01_l
                 ^ a01_l
                 ^ gdollar_1;
assign gdollar_2 = b01_l & a01_l
                    | b01_l & gdollar_1
                    | pad{4} & gdollar_1;
assign ad00_l = b00_l
                 ^ a00_l
                 ^ gdollar_2;
assign carry_out_l = b00_l & a00_l
                      | b00_l & gdollar_2
                      | pad{16} & gdollar_2;
// e16: sn74151 
assign regbus02_l = ad02_l & right_l & left_l & twice_l
                     | ad08_l & right_l & left_l & ~twice_l
                     | ad03_l & right_l & ~left_l & twice_l
                     | ad04_l & right_l & ~left_l & ~twice_l
                     | ad01_l & ~right_l & left_l & twice_l
                     | ad00_l & ~right_l & left_l & ~twice_l
                     | and02_l & ~right_l & ~left_l & twice_l
                     | pg02_l & ~right_l & ~left_l & ~twice_l;
// e17: dec8271 
always @(negedge mq_load_l)
  if (~mq_load_l) begin
    mq00_l <= ad11_l & ~right_l
                   | n_t_6x & right_l;
  end
always @(negedge mq_load_l)
  if (~mq_load_l) begin
    mq01_l <= mq00_l & ~right_l
                   | n_t_2x & right_l;
  end
always @(negedge mq_load_l)
  if (~mq_load_l) begin
    mq02_l <= mq01_l & ~right_l
                   | n_t_24x & right_l;
  end
always @(negedge mq_load_l)
  if (~mq_load_l) begin
    mq03_l <= mq02_l & ~right_l
                   | n_t_23x & right_l;
  end
// e18: sn7420 
assign ac04_11eq0_l = ~(n_t_31x & n_t_29x & n_t_28x & n_t_30x);
assign mq00_03eq0_l = ~(mq03_l & mq02_l & mq00_l & mq01_l);
// e19: sn74153 
assign n_t_21x = (~pad{1} & ~en2 & pc02_l
                          | ~pad{1} & en2 & md02_l
                          | pad{1} & ~en2 & mq02_l
                          | pad{1} & en2 & ma02_l);
assign n_t_13x = (~pad{1} & ~en2 & pc03_l
                          | ~pad{1} & en2 & md03_l
                          | pad{1} & ~en2 & mq03_l
                          | pad{1} & en2 & ma03_l);
// e20: dec8271 
always @(negedge pc_load_l)
  if (~pc_load_l) begin
    pc03_l <= regbus03_l;
  end
always @(negedge pc_load_l)
  if (~pc_load_l) begin
    pc02_l <= regbus02_l;
  end
always @(negedge pc_load_l)
  if (~pc_load_l) begin
    pc00_l <= regbus00_l;
  end
always @(negedge pc_load_l)
  if (~pc_load_l) begin
    pc01_l <= regbus01_l;
  end
// e21: sn74151 
assign regbus03_l = ad03_l & right_l & left_l & twice_l
                     | ad09_l & right_l & left_l & ~twice_l
                     | ad04_l & right_l & ~left_l & twice_l
                     | ad05_l & right_l & ~left_l & ~twice_l
                     | ad02_l & ~right_l & left_l & twice_l
                     | ad01_l & ~right_l & left_l & ~twice_l
                     | and03_l & ~right_l & ~left_l & twice_l
                     | pg03_l & ~right_l & ~left_l & ~twice_l;
// e22: n8881n 
// ma07_l = !(cpma7 & !mac_l); 
// ma06_l = !(!mac_l & cpma6); 
// ma04_l = !(!mac_l & cpma4); 
// ma05_l = !(!mac_l & cpma5); 
// e23: sn74151 
assign regbus04_l = ad04_l & right_l & left_l & twice_l
                     | ad10_l & right_l & left_l & ~twice_l
                     | ad05_l & right_l & ~left_l & twice_l
                     | ad06_l & right_l & ~left_l & ~twice_l
                     | ad03_l & ~right_l & left_l & twice_l
                     | ad02_l & ~right_l & left_l & ~twice_l
                     | and04_l & ~right_l & ~left_l & twice_l
                     | pg04_l & ~right_l & ~left_l & ~twice_l;
// e24: dec8271 
always @(negedge mb_load_l)
  if (~mb_load_l) begin
    mb06 <= ~regbus06_l;
  end
always @(negedge mb_load_l)
  if (~mb_load_l) begin
    mb07 <= ~regbus07_l;
  end
always @(negedge mb_load_l)
  if (~mb_load_l) begin
    mb05 <= ~regbus05_l;
  end
always @(negedge mb_load_l)
  if (~mb_load_l) begin
    mb04 <= ~regbus04_l;
  end
// e25: dec8271 
always @(negedge cpma_load_l)
  if (~cpma_load_l) begin
    cpma7 <= ~regbus07_l;
  end
always @(negedge cpma_load_l)
  if (~cpma_load_l) begin
    cpma6 <= ~regbus06_l;
  end
always @(negedge cpma_load_l)
  if (~cpma_load_l) begin
    cpma4 <= ~regbus04_l;
  end
always @(negedge cpma_load_l)
  if (~cpma_load_l) begin
    cpma5 <= ~regbus05_l;
  end
// e26: mc8266 
assign pg04_l = ~(~ma04_l & ~pagez
                   | pagez & ~pagez);
// e27: n8881n 
// md07_l = !(mb07 & md_dir_l); 
// md06_l = !(md_dir_l & mb06); 
// md04_l = !(md_dir_l & mb04); 
// md05_l = !(md_dir_l & mb05); 
// e28: sn74151 
assign regbus05_l = ad05_l & right_l & left_l & twice_l
                     | ad11_l & right_l & left_l & ~twice_l
                     | ad06_l & right_l & ~left_l & twice_l
                     | ad07_l & right_l & ~left_l & ~twice_l
                     | ad04_l & ~right_l & left_l & twice_l
                     | ad03_l & ~right_l & left_l & ~twice_l
                     | and05_l & ~right_l & ~left_l & twice_l
                     | md05_l & ~right_l & ~left_l & ~twice_l;
// e29: dec8271 
always @(ac_load_l, init, regbus06_l)
  if (init) begin
    ac06_m <= 1'b0;
  end else
  if (~(~ac_load_l)) begin
    ac06_m <= ~regbus06_l;
  end
always @(ac_load_l, init, ac06_m)
  if (init) begin
    ac06 <= 1'b0;
  end else
  if (~ac_load_l) begin
    ac06 <= ac06_m;
  end
always @(ac_load_l, init, regbus07_l)
  if (init) begin
    ac07_m <= 1'b0;
  end else
  if (~(~ac_load_l)) begin
    ac07_m <= ~regbus07_l;
  end
always @(ac_load_l, init, ac07_m)
  if (init) begin
    ac07 <= 1'b0;
  end else
  if (~ac_load_l) begin
    ac07 <= ac07_m;
  end
always @(ac_load_l, init, regbus05_l)
  if (init) begin
    ac05_m <= 1'b0;
  end else
  if (~(~ac_load_l)) begin
    ac05_m <= ~regbus05_l;
  end
always @(ac_load_l, init, ac05_m)
  if (init) begin
    ac05 <= 1'b0;
  end else
  if (~ac_load_l) begin
    ac05 <= ac05_m;
  end
always @(ac_load_l, init, regbus04_l)
  if (init) begin
    ac04_m <= 1'b0;
  end else
  if (~(~ac_load_l)) begin
    ac04_m <= ~regbus04_l;
  end
always @(ac_load_l, init, ac04_m)
  if (init) begin
    ac04 <= 1'b0;
  end else
  if (~ac_load_l) begin
    ac04 <= ac04_m;
  end
// e30: sn74153 
assign n_t_36x = (~pad{1} & ~en2 & pc04_l
                          | ~pad{1} & en2 & md04_l
                          | pad{1} & ~en2 & mq04_l
                          | pad{1} & en2 & ma04_l);
assign n_t_37x = (~pad{1} & ~en2 & pc05_l
                          | ~pad{1} & en2 & md05_l
                          | pad{1} & ~en2 & mq05_l
                          | pad{1} & en2 & ma05_l);
// e31: sn7487 
assign b04_l = data_t & ~data_f
                | data_f & data04
                | ~data_f & ~data04;
assign b07_l = data_t & ~data_f
                | data_f & data07
                | ~data_f & ~data07;
assign b06_l = data_t & ~data_f
                | data_f & data06
                | ~data_f & ~data06;
assign b05_l = data_t & ~data_f
                | data_f & data05
                | ~data_f & ~data05;
// e32: dec8235 
// data07 = !(!mq07_l & !mq2bus_l
//       # ac07 & !ac2bus_l); 
// data06 = !(!mq06_l & !mq2bus_l
//       # ac06 & !ac2bus_l); 
// data04 = !(!mq04_l & !mq2bus_l
//       # ac04 & !ac2bus_l); 
// data05 = !(!mq05_l & !mq2bus_l
//       # ac05 & !ac2bus_l); 
// e33: sn74151 
assign regbus06_l = ad06_l & right_l & left_l & twice_l
                     | ad00_l & right_l & left_l & ~twice_l
                     | ad07_l & right_l & ~left_l & twice_l
                     | ad08_l & right_l & ~left_l & ~twice_l
                     | ad05_l & ~right_l & left_l & twice_l
                     | ad04_l & ~right_l & left_l & ~twice_l
                     | and06_l & ~right_l & ~left_l & twice_l
                     | md06_l & ~right_l & ~left_l & ~twice_l;
// e34: mc8266 
assign n_t_11x = ~(~mq06_l & ~shl_ena_l
                    | ac05 & shl_ena_l & ~al2mq_ena_l);
assign n_t_4x = ~(~mq05_l & ~shl_ena_l
                   | ac04 & shl_ena_l & ~al2mq_ena_l);
assign n_t_3x = ~(~mq08_l & ~shl_ena_l
                   | ac07 & shl_ena_l & ~al2mq_ena_l);
assign n_t_18x = ~(~mq07_l & ~shl_ena_l
                    | ac06 & shl_ena_l & ~al2mq_ena_l);
// e35: sn7400 
assign and04_l = ~(mb04 & ac04);
assign and05_l = ~(ac05 & mb05);
assign and07_l = ~(mb07 & ac07);
assign and06_l = ~(mb06 & ac06);
// e36: mc8266 
assign a06_l = ~(~n_t_39x & ~en0
                  | n_t_39x & en0 & ~en0);
assign a07_l = ~(~n_t_38x & ~en0
                  | n_t_38x & en0 & ~en0);
assign a05_l = ~(~n_t_37x & ~en0
                  | n_t_37x & en0 & ~en0);
assign a04_l = ~(~n_t_36x & ~en0
                  | n_t_36x & en0 & ~en0);
// e37: sn7483 
assign ad07_l = a07_l
                 ^ b07_l
                 ^ carry08_l;
assign gdollar_3 = a07_l & b07_l
                    | a07_l & carry08_l
                    | pad{11} & carry08_l;
assign ad06_l = a06_l
                 ^ b06_l
                 ^ gdollar_3;
assign gdollar_4 = a06_l & b06_l
                    | a06_l & gdollar_3
                    | pad{7} & gdollar_3;
assign ad05_l = b05_l
                 ^ a05_l
                 ^ gdollar_4;
assign gdollar_5 = b05_l & a05_l
                    | b05_l & gdollar_4
                    | pad{4} & gdollar_4;
assign ad04_l = b04_l
                 ^ a04_l
                 ^ gdollar_5;
assign carry04_l = b04_l & a04_l
                    | b04_l & gdollar_5
                    | pad{16} & gdollar_5;
// e38: sn74151 
assign regbus07_l = ad07_l & right_l & left_l & twice_l
                     | ad01_l & right_l & left_l & ~twice_l
                     | ad08_l & right_l & ~left_l & twice_l
                     | ad09_l & right_l & ~left_l & ~twice_l
                     | ad06_l & ~right_l & left_l & twice_l
                     | ad05_l & ~right_l & left_l & ~twice_l
                     | and07_l & ~right_l & ~left_l & twice_l
                     | md07_l & ~right_l & ~left_l & ~twice_l;
// e39: dec8271 
always @(negedge mq_load_l)
  if (~mq_load_l) begin
    mq04_l <= mq03_l & ~right_l
                   | n_t_4x & right_l;
  end
always @(negedge mq_load_l)
  if (~mq_load_l) begin
    mq05_l <= mq04_l & ~right_l
                   | n_t_11x & right_l;
  end
always @(negedge mq_load_l)
  if (~mq_load_l) begin
    mq06_l <= mq05_l & ~right_l
                   | n_t_18x & right_l;
  end
always @(negedge mq_load_l)
  if (~mq_load_l) begin
    mq07_l <= mq06_l & ~right_l
                   | n_t_3x & right_l;
  end
// e40: sn7402 
assign n_t_28x = ~(ac08
                    | ac09);
assign n_t_30x = ~(ac10
                    | ac11);
assign n_t_31x = ~(ac05
                    | ac04);
assign n_t_29x = ~(ac07
                    | ac06);
// e41: sn74153 
assign n_t_39x = (~pad{1} & ~en2 & pc06_l
                          | ~pad{1} & en2 & md06_l
                          | pad{1} & ~en2 & mq06_l
                          | pad{1} & en2 & ma06_l);
assign n_t_38x = (~pad{1} & ~en2 & pc07_l
                          | ~pad{1} & en2 & md07_l
                          | pad{1} & ~en2 & mq07_l
                          | pad{1} & en2 & ma07_l);
// e42: dec8271 
always @(negedge pc_load_l)
  if (~pc_load_l) begin
    pc07_l <= regbus07_l;
  end
always @(negedge pc_load_l)
  if (~pc_load_l) begin
    pc06_l <= regbus06_l;
  end
always @(negedge pc_load_l)
  if (~pc_load_l) begin
    pc04_l <= regbus04_l;
  end
always @(negedge pc_load_l)
  if (~pc_load_l) begin
    pc05_l <= regbus05_l;
  end
// e43: sn74151 
assign regbus08_l = ad08_l & right_l & left_l & twice_l
                     | ad02_l & right_l & left_l & ~twice_l
                     | ad09_l & right_l & ~left_l & twice_l
                     | ad10_l & right_l & ~left_l & ~twice_l
                     | ad07_l & ~right_l & left_l & twice_l
                     | ad06_l & ~right_l & left_l & ~twice_l
                     | and08_l & ~right_l & ~left_l & twice_l
                     | md08_l & ~right_l & ~left_l & ~twice_l;
// e44: n8881n 
// ma11_l = !(cpma11 & !mac_l); 
// ma10_l = !(!mac_l & cpma10); 
// ma08_l = !(cpma8 & !mac_l); 
// ma09_l = !(!mac_l & cpma9); 
// e45: sn7430 
assign mq04_11eq0_l = ~(mq11_l & mq10_l & mq09_l & mq08_l & mq06_l & mq07_l & mq05_l & mq04_l);
// e46: dec8271 
always @(negedge cpma_load_l)
  if (~cpma_load_l) begin
    cpma10 <= ~regbus10_l;
  end
always @(negedge cpma_load_l)
  if (~cpma_load_l) begin
    cpma11 <= ~regbus11_l;
  end
always @(negedge cpma_load_l)
  if (~cpma_load_l) begin
    cpma8 <= ~regbus08_l;
  end
always @(negedge cpma_load_l)
  if (~cpma_load_l) begin
    cpma9 <= ~regbus09_l;
  end
// e47: dec8271 
always @(negedge pc_load_l)
  if (~pc_load_l) begin
    pc08_l <= regbus08_l;
  end
always @(negedge pc_load_l)
  if (~pc_load_l) begin
    pc09_l <= regbus09_l;
  end
always @(negedge pc_load_l)
  if (~pc_load_l) begin
    pc10_l <= regbus10_l;
  end
always @(negedge pc_load_l)
  if (~pc_load_l) begin
    pc11_l <= regbus11_l;
  end
// e48: sn74151 
assign regbus09_l = ad09_l & right_l & left_l & twice_l
                     | ad03_l & right_l & left_l & ~twice_l
                     | ad10_l & right_l & ~left_l & twice_l
                     | ad11_l & right_l & ~left_l & ~twice_l
                     | ad08_l & ~right_l & left_l & twice_l
                     | ad07_l & ~right_l & left_l & ~twice_l
                     | and09_l & ~right_l & ~left_l & twice_l
                     | md09_l & ~right_l & ~left_l & ~twice_l;
// e49: n8881n 
// md11_l = !(mb11 & md_dir_l); 
// md10_l = !(md_dir_l & mb10); 
// md08_l = !(mb08 & md_dir_l); 
// md09_l = !(mb09 & md_dir_l); 
// e50: dec8271 
always @(negedge mb_load_l)
  if (~mb_load_l) begin
    mb10 <= ~regbus10_l;
  end
always @(negedge mb_load_l)
  if (~mb_load_l) begin
    mb11 <= ~regbus11_l;
  end
always @(negedge mb_load_l)
  if (~mb_load_l) begin
    mb09 <= ~regbus09_l;
  end
always @(negedge mb_load_l)
  if (~mb_load_l) begin
    mb08 <= ~regbus08_l;
  end
// e51: sn74153 
assign n_t_10x = (~pad{1} & ~en2 & pc08_l
                          | ~pad{1} & en2 & md08_l
                          | pad{1} & ~en2 & mq08_l
                          | pad{1} & en2 & ma08_l);
assign n_t_40x = (~pad{1} & ~en2 & pc09_l
                          | ~pad{1} & en2 & md09_l
                          | pad{1} & ~en2 & mq09_l
                          | pad{1} & en2 & ma09_l);
// e52: sn7483 
assign ad11_l = a11_l
                 ^ b11_l
                 ^ carry_in_l;
assign gdollar_6 = a11_l & b11_l
                    | a11_l & carry_in_l
                    | pad{11} & carry_in_l;
assign ad10_l = a10_l
                 ^ b10_l
                 ^ gdollar_6;
assign gdollar_7 = a10_l & b10_l
                    | a10_l & gdollar_6
                    | pad{7} & gdollar_6;
assign ad09_l = b09_l
                 ^ a09_l
                 ^ gdollar_7;
assign gdollar_8 = b09_l & a09_l
                    | b09_l & gdollar_7
                    | pad{4} & gdollar_7;
assign ad08_l = a08_l
                 ^ b08_l
                 ^ gdollar_8;
assign carry08_l = a08_l & b08_l
                    | a08_l & gdollar_8
                    | pad{16} & gdollar_8;
// e53: sn74151 
assign regbus10_l = ad10_l & right_l & left_l & twice_l
                     | ad04_l & right_l & left_l & ~twice_l
                     | ad11_l & right_l & ~left_l & twice_l
                     | adlk_l & right_l & ~left_l & ~twice_l
                     | ad09_l & ~right_l & left_l & twice_l
                     | ad08_l & ~right_l & left_l & ~twice_l
                     | and10_l & ~right_l & ~left_l & twice_l
                     | md10_l & ~right_l & ~left_l & ~twice_l;
// e54: dec8271 
always @(negedge mq_load_l)
  if (~mq_load_l) begin
    mq08_l <= mq07_l & ~right_l
                   | n_t_22x & right_l;
  end
always @(negedge mq_load_l)
  if (~mq_load_l) begin
    mq09_l <= mq08_l & ~right_l
                   | n_t_19x & right_l;
  end
always @(negedge mq_load_l)
  if (~mq_load_l) begin
    mq10_l <= mq09_l & ~right_l
                   | n_t_7x & right_l;
  end
always @(negedge mq_load_l)
  if (~mq_load_l) begin
    mq11_l <= mq10_l & ~right_l
                   | n_t_20x & right_l;
  end
// e55: dec8271 
always @(ac_load_l, init, regbus10_l)
  if (init) begin
    ac10_m <= 1'b0;
  end else
  if (~(~ac_load_l)) begin
    ac10_m <= ~regbus10_l;
  end
always @(ac_load_l, init, ac10_m)
  if (init) begin
    ac10 <= 1'b0;
  end else
  if (~ac_load_l) begin
    ac10 <= ac10_m;
  end
always @(ac_load_l, init, regbus11_l)
  if (init) begin
    ac11_m <= 1'b0;
  end else
  if (~(~ac_load_l)) begin
    ac11_m <= ~regbus11_l;
  end
always @(ac_load_l, init, ac11_m)
  if (init) begin
    ac11 <= 1'b0;
  end else
  if (~ac_load_l) begin
    ac11 <= ac11_m;
  end
always @(ac_load_l, init, regbus09_l)
  if (init) begin
    ac09_m <= 1'b0;
  end else
  if (~(~ac_load_l)) begin
    ac09_m <= ~regbus09_l;
  end
always @(ac_load_l, init, ac09_m)
  if (init) begin
    ac09 <= 1'b0;
  end else
  if (~ac_load_l) begin
    ac09 <= ac09_m;
  end
always @(ac_load_l, init, regbus08_l)
  if (init) begin
    ac08_m <= 1'b0;
  end else
  if (~(~ac_load_l)) begin
    ac08_m <= ~regbus08_l;
  end
always @(ac_load_l, init, ac08_m)
  if (init) begin
    ac08 <= 1'b0;
  end else
  if (~ac_load_l) begin
    ac08 <= ac08_m;
  end
// e56: mc8266 
assign a11_l = ~(~n_t_43x & ~en0
                  | n_t_43x & en0 & ~en0);
assign a10_l = ~(~n_t_42x & ~en0
                  | n_t_42x & en0 & ~en0);
assign a08_l = ~(~n_t_10x & ~en0
                  | n_t_10x & en0 & ~en0);
assign a09_l = ~(~n_t_40x & ~en0
                  | n_t_40x & en0 & ~en0);
// e57: sn7487 
assign b08_l = data_t & ~data_f
                | data_f & data08
                | ~data_f & ~data08;
assign b11_l = data_t & ~data_f
                | data_f & data11
                | ~data_f & ~data11;
assign b10_l = data_t & ~data_f
                | data_f & data10
                | ~data_f & ~data10;
assign b09_l = data_t & ~data_f
                | data_f & data09
                | ~data_f & ~data09;
// e58: sn74151 
assign regbus11_l = ad11_l & right_l & left_l & twice_l
                     | ad05_l & right_l & left_l & ~twice_l
                     | adlk_l & right_l & ~left_l & twice_l
                     | ad00_l & right_l & ~left_l & ~twice_l
                     | ad10_l & ~right_l & left_l & twice_l
                     | ad09_l & ~right_l & left_l & ~twice_l
                     | and11_l & ~right_l & ~left_l & twice_l
                     | md11_l & ~right_l & ~left_l & ~twice_l;
// e59: mc8266 
assign n_t_7x = ~(~mq11_l & ~shl_ena_l
                   | ac10 & shl_ena_l & ~al2mq_ena_l);
assign n_t_20x = ~(~mq_data_l & ~shl_ena_l
                    | ac11 & shl_ena_l & ~al2mq_ena_l);
assign n_t_22x = ~(~mq09_l & ~shl_ena_l
                    | ac08 & shl_ena_l & ~al2mq_ena_l);
assign n_t_19x = ~(~mq10_l & ~shl_ena_l
                    | ac09 & shl_ena_l & ~al2mq_ena_l);
// e60: dec8235 
// data09 = !(!mq09_l & !mq2bus_l
//       # ac09 & !ac2bus_l); 
// data08 = !(!mq08_l & !mq2bus_l
//       # ac08 & !ac2bus_l); 
// data10 = !(!mq10_l & !mq2bus_l
//       # ac10 & !ac2bus_l); 
// data11 = !(!mq11_l & !mq2bus_l
//       # ac11 & !ac2bus_l); 
// e61: sn7400 
assign and08_l = ~(mb08 & ac08);
assign and09_l = ~(mb09 & ac09);
assign and11_l = ~(ac11 & mb11);
assign and10_l = ~(ac10 & mb10);
// e62: sn74153 
assign n_t_42x = (~pad{1} & ~en2 & pc10_l
                          | ~pad{1} & en2 & md10_l
                          | pad{1} & ~en2 & mq10_l
                          | pad{1} & en2 & ma10_l);
assign n_t_43x = (~pad{1} & ~en2 & pc11_l
                          | ~pad{1} & en2 & md11_l
                          | pad{1} & ~en2 & mq11_l
                          | pad{1} & en2 & ma11_l);
// e63: sn74h04 
// e64: sn74h04 
// open collector 'wire-or's 
assign data00 = (~mq00_l & ~mq2bus_l
                  | ac00 & ~ac2bus_l)? 1'b0: 1'bz;
assign data01 = (~mq01_l & ~mq2bus_l
                  | ac01 & ~ac2bus_l)? 1'b0: 1'bz;
assign data02 = (~mq02_l & ~mq2bus_l
                  | ac02 & ~ac2bus_l)? 1'b0: 1'bz;
assign data03 = (~mq03_l & ~mq2bus_l
                  | ac03 & ~ac2bus_l)? 1'b0: 1'bz;
assign data04 = (~mq04_l & ~mq2bus_l
                  | ac04 & ~ac2bus_l)? 1'b0: 1'bz;
assign data05 = (~mq05_l & ~mq2bus_l
                  | ac05 & ~ac2bus_l)? 1'b0: 1'bz;
assign data06 = (~mq06_l & ~mq2bus_l
                  | ac06 & ~ac2bus_l)? 1'b0: 1'bz;
assign data07 = (~mq07_l & ~mq2bus_l
                  | ac07 & ~ac2bus_l)? 1'b0: 1'bz;
assign data08 = (~mq08_l & ~mq2bus_l
                  | ac08 & ~ac2bus_l)? 1'b0: 1'bz;
assign data09 = (~mq09_l & ~mq2bus_l
                  | ac09 & ~ac2bus_l)? 1'b0: 1'bz;
assign data10 = (~mq10_l & ~mq2bus_l
                  | ac10 & ~ac2bus_l)? 1'b0: 1'bz;
assign data11 = (~mq11_l & ~mq2bus_l
                  | ac11 & ~ac2bus_l)? 1'b0: 1'bz;
assign ma00_l = (~mac_l & cpma0)? 1'b0: 1'bz;
assign ma01_l = (~mac_l & cpma1)? 1'b0: 1'bz;
assign ma02_l = (~mac_l & cpma2)? 1'b0: 1'bz;
assign ma03_l = (cpma3 & ~mac_l)? 1'b0: 1'bz;
assign ma04_l = (~mac_l & cpma4)? 1'b0: 1'bz;
assign ma05_l = (~mac_l & cpma5)? 1'b0: 1'bz;
assign ma06_l = (~mac_l & cpma6)? 1'b0: 1'bz;
assign ma07_l = (cpma7 & ~mac_l)? 1'b0: 1'bz;
assign ma08_l = (cpma8 & ~mac_l)? 1'b0: 1'bz;
assign ma09_l = (~mac_l & cpma9)? 1'b0: 1'bz;
assign ma10_l = (~mac_l & cpma10)? 1'b0: 1'bz;
assign ma11_l = (cpma11 & ~mac_l)? 1'b0: 1'bz;
assign md00_l = (md_dir_l & mb00)? 1'b0: 1'bz;
assign md01_l = (md_dir_l & mb01)? 1'b0: 1'bz;
assign md02_l = (md_dir_l & mb02)? 1'b0: 1'bz;
assign md03_l = (mb03 & md_dir_l)? 1'b0: 1'bz;
assign md04_l = (md_dir_l & mb04)? 1'b0: 1'bz;
assign md05_l = (md_dir_l & mb05)? 1'b0: 1'bz;
assign md06_l = (md_dir_l & mb06)? 1'b0: 1'bz;
assign md07_l = (mb07 & md_dir_l)? 1'b0: 1'bz;
assign md08_l = (mb08 & md_dir_l)? 1'b0: 1'bz;
assign md09_l = (mb09 & md_dir_l)? 1'b0: 1'bz;
assign md10_l = (md_dir_l & mb10)? 1'b0: 1'bz;
assign md11_l = (mb11 & md_dir_l)? 1'b0: 1'bz;
endmodule