~/Verilog/bin/topld.pl M8310F
info: cpol_use ne cpol_use20_8axial
info: cpol_use ne cpol_use20_8axial
info: edge_top ne edge_con2
warning: making e/edge_top/ a connector
info: n8881n ne dil14
info: 7405n ne dil14
info: 7412n ne dil14
info: 7410n ne dil14
info: 7412n ne dil14
info: 74h04n ne 7404n
info: n8881n ne dil14
info: 7404n ne dil14
info: 74h00n ne 7400n
info: 7402n ne dil14
info: n8881n ne dil14
info: 7404n ne dil14
info: 74h00n ne 7400n
info: 7402n ne dil14
info: n8881n ne dil14
info: 74151n ne dil16
info: 7402n ne dil14
info: 7404n ne dil14
info: 7405n ne dil14
info: 7405n ne dil14
info: sp384n ne dil14
info: n8881n ne dil14
info: 7410n ne dil14
info: 7404n ne dil14
info: 74h00n ne 7400n
info: 74h04n ne 7404n
info: 7402n ne dil14
info: 7486n ne dil14
info: n8881n ne dil14
info: 74h74n ne 7474n
info: 7402n ne dil14
info: n8881n ne dil14
info: n8881n ne dil14
info: 74h74n ne 7474n
info: dec8251 ne dil16
info: 7404n ne dil14
info: 7404n ne dil14
info: n8881n ne dil14
info: n8881n ne dil14
info: 7402n ne dil14
info: n8881n ne dil14
info: n8881n ne dil14
info: 7404n ne dil14
info: 7405n ne dil14
info: 7412n ne dil14
info: edge_top ne edge_con2
warning: making f/edge_top/ a connector
info: edge_top ne edge_con2
warning: making h/edge_top/ a connector
info: 2n3009 ne _npn_to5
warning: making q1/2n3009/ a connector
info: quad ne edge_con8
warning: making u$2/quad/ a connector
warning: non-bypass capacitor deleted: c1
~/Verilog/bin/smaller.pl M8310F.PLD >vv || (rm vv; exit 1)
55 signals were removed:
  bd: !d_l
  be: !e_l
  bf: !f_l
  bkc: !keycontrol_l
  bmd05: !md05_l
  bmd06: !md06_l
  bmd07: !md07_l
  bmd08: !md08_l
  bmd09: !md09_l
  bmd10: !md10_l
  bmd11: !md11_l
  bms_dis: !ms_dis_l
  btp2: tp2
  bts1: !ts1_l
  bts2: !ts2_l
  bts3: !ts3_l
  bts4: !ts4_l
  bus_strobe: !bus_strobe_l
  cpma_load: !cpma_load_l
  eset_l: !eset
  fset: !fset_l
  jmp: !jmp_l
  ms_dis_l: ms_ir_dis_l
  n_t_10x: !link_load_l
  n_t_11x: !pagez
  n_t_15x: !n_t_23x
  n_t_22x: !link
  n_t_24x: !carry_out_l
  n_t_25x: !pwr_ok
  n_t_31x: !c2_l
  n_t_33x: !skip1
  n_t_38x: !la_enable_l
  n_t_40x: !c0_l
  n_t_41x: !tp3
  n_t_42x: !n_t_44x
  n_t_46x: !n_t_2x
  n_t_47x: !ind2
  n_t_48x: !en2
  n_t_49x: !en1
  n_t_51x: !and_l
  n_t_52x: !tad_l
  n_t_53x: !dca_l
  n_t_54x: !tp4_not_malc
  n_t_57x: !dcaets2
  n_t_65x: !n_t_64x
  n_t_66x: !d_not_jmp
  n_t_67x: !bts3
  n_t_70x: !opets3
  n_t_71x: !op2ts3
  n_t_74x: !dset_l
  n_t_76x: !n_t_46x
  n_t_79x: !ts4fset_not_ms_dis
  n_t_7x: !initialize
  opr_iot_l: !opr_iot
  oprf_l: !oprf
~/Verilog/bin/smaller.pl vv >M8310FX.PLD || (rm M8310FX.PLD; exit 1)
3 signals were removed:
  btp3: tp3
  bts3: !ts3_l
  n_t_46x: !n_t_2x
~/Verilog/bin/cupl2v.pl M8310FX.PLD >vv || (rm vv; exit 1)
mv vv M8310F.v
rm M8310FX.PLD