// this file is generated by topld.pl 
// please don't edit it. 
// input pins 
// output pins 
// internal nodes 
// code nodes 
// equations 
// c1: c_us 
// c2: c_us 
// c3: c_us 
// c4: c_us 
// c6: c_us 
// c7: c_us 
// c8: c_us 
// c9: c_us 
// c10: c_us 
// c11: c_us 
// c12: c_us 
// c14: c_us 
// c15: c_us 
// c16: c_us 
// c17: c_us 
// c18: c_us 
// c19: c_us 
// c20: c_us 
// c21: c_us 
// c22: c_us 
// c23: c_us 
// c24: c_us 
// c25: c_us 
// c26: c_us 
// c27: c_us 
// c28: c_us 
// c29: c_us 
// c30: c_us 
// c31: c_us 
// c32: c_us 
// c33: c_us 
// c34: c_us 
// c35: cpol_use 
// c36: cpol_use 
// c37: cpol_use 
// e1: sn97401 
// n0_to_eir = !(!n_t_51x & int_in_prog); 
// n0_to_eir = !(!fetch & tp1); 
// fe_set = !(ex1 & !e); 
// c0 = !(n_t_26x & modeb); 
// e2: sn74h04 
module m8340e (incr_sc, n3v, n3v0, tp2_d, adlk_dis_l, c0, dad_or_dst, dad_or_dst_l, data10, data11, data7, data8, data9, data_to_sc, defer, div_12_l, e, eir2, eir3, fd_set, fe_set, fetch, init, int_in_prog, last_step_l, ma_ms_lc, md0, md1, md10, md11, md2, md3, md4, md5, md6, md7, md8, md9, modeb, n0_to_eir, n_t_44x, next_loc, rom_11_l, rom_12_l, rom_13_l, rom_14_l, rom_15_l, rom_17_l, rom_19_l, rom_21_l, rom_22_l, rom_23_l, rom_24_l, rom_25_l, rom_26_l, sc_0_l, tp1, tp2, tp3, tp4, ts3);
input incr_sc;
input n3v;
input n3v0;
input tp2_d;
output adlk_dis_l;
output c0;
inout dad_or_dst;
inout dad_or_dst_l;
inout data10;
inout data11;
inout data7;
inout data8;
inout data9;
inout data_to_sc;
input defer;
inout div_12_l;
input e;
inout eir2;
inout eir3;
output fd_set;
output fe_set;
input fetch;
input init;
input int_in_prog;
output last_step_l;
input ma_ms_lc;
input md0;
input md1;
input md10;
input md11;
input md2;
input md3;
input md4;
input md5;
input md6;
input md7;
input md8;
input md9;
inout modeb;
inout n0_to_eir;
inout n_t_44x;
output next_loc;
output rom_11_l;
inout rom_12_l;
output rom_13_l;
inout rom_14_l;
output rom_15_l;
output rom_17_l;
inout rom_19_l;
inout rom_21_l;
output rom_22_l;
inout rom_23_l;
output rom_24_l;
inout rom_25_l;
inout rom_26_l;
output sc_0_l;
input tp1;
input tp2;
input tp3;
input tp4;
input ts3;

reg ex1_m;
reg gdollar_0_m;
reg gdollar_1_m;
reg gdollar_2_m;
reg modea_m;
reg n_t_10x_m;
reg n_t_11x_m;
reg n_t_14x_m;
reg n_t_17x_m;
reg n_t_18x_m;
reg n_t_19x_m;
reg n_t_1x_m;
reg n_t_26x_m;
reg n_t_2x_m;
reg n_t_38x_m;
reg n_t_39x_m;
reg n_t_3x_m;
reg n_t_40x_m;
reg n_t_42x_m;
reg n_t_4x_m;
reg n_t_5x_m;
reg n_t_7x_m;
reg n_t_8x_m;

reg modea;
reg n_t_1x;
reg n_t_2x;
reg n_t_4x;
reg n_t_5x;
reg n_t_3x;
reg n_t_8x;
reg n_t_14x;
reg n_t_10x;
reg n_t_11x;
reg n_t_17x;
reg n_t_18x;
reg n_t_7x;
reg n_t_26x;
reg ex1;
reg n_t_38x;
reg gdollar_0;
reg gdollar_1;
reg gdollar_2;
reg n_t_39x;
reg n_t_40x;
reg n_t_19x;
reg n_t_42x;
wire eae_inst;
wire exec_divide;
wire exec_multiply;
wire ld_eir;
wire n0_to_sc;
wire n_t_21x;
wire n_t_24x;
wire n_t_25x;
wire n_t_27x;
wire n_t_34x;
wire n_t_35x;
wire n_t_36x;
wire n_t_37x;
wire n_t_43x;
wire n_t_46x;
wire n_t_48x;
wire n_t_49x;
wire n_t_51x;
wire n_t_53x;
wire n_t_54x;
wire sc_load_l;
wire sc_to_data;
wire swab;
wire swba;
assign modeb = ~modea;
// e3: sn74h20 
assign n_t_25x = ~(swab & swba & n_t_24x & eae_inst);
assign n_t_21x = ~(eae_inst & ~fetch & swba & swab);
// e4: sn74h106 
always @(n_t_27x, n3v0, init, swba, swab, modea)
  if (~n3v0) begin
    modea_m <= 1'b0;
  end else
  if (init) begin
    modea_m <= 1'b1;
  end else
  if (~(n_t_27x)) begin
    modea_m <= ~swba? (~swab? ~modea: 1'b1) : (~swab? 1'b0: modea);
  end
always @(n_t_27x, n3v0, init, modea_m)
  if (~n3v0) begin
    modea <= 1'b0;
  end else
  if (init) begin
    modea <= 1'b1;
  end else
  if (n_t_27x) begin
    modea <= modea_m;
  end
// e6: sn7474 
always @(ld_eir, n0_to_eir, n3v0, md0)
  if (~n0_to_eir) begin
    n_t_1x_m <= 1'b0;
  end else
  if (~n3v0) begin
    n_t_1x_m <= 1'b1;
  end else
  if (~(ld_eir)) begin
    n_t_1x_m <= ~md0;
  end
always @(ld_eir, n0_to_eir, n3v0, n_t_1x_m)
  if (~n0_to_eir) begin
    n_t_1x <= 1'b0;
  end else
  if (~n3v0) begin
    n_t_1x <= 1'b1;
  end else
  if (ld_eir) begin
    n_t_1x <= n_t_1x_m;
  end
always @(ld_eir, n0_to_eir, n3v0, md1)
  if (~n0_to_eir) begin
    n_t_2x_m <= 1'b0;
  end else
  if (~n3v0) begin
    n_t_2x_m <= 1'b1;
  end else
  if (~(ld_eir)) begin
    n_t_2x_m <= ~md1;
  end
always @(ld_eir, n0_to_eir, n3v0, n_t_2x_m)
  if (~n0_to_eir) begin
    n_t_2x <= 1'b0;
  end else
  if (~n3v0) begin
    n_t_2x <= 1'b1;
  end else
  if (ld_eir) begin
    n_t_2x <= n_t_2x_m;
  end
// e7: sn74h30 
assign eae_inst = ~(~(n3v0 & n_t_1x & n_t_2x & n_t_4x & n_t_5x & n_t_7x & n3v0 & n3v0));
// e8: sn7402 
assign exec_multiply = ~(rom_12_l
                          | exec_divide);
assign exec_divide = ~(rom_12_l
                        | rom_14_l);
assign n0_to_sc = ~(~tp3
                     | rom_23_l);
// e9: sn97401 
// n_t_44x = !(data_to_sc & data7); 
// data7 = !(sc_to_data & n_t_38x); 
// n_t_44x = !n_t_43x; 
// e10: sn7474 
always @(ld_eir, n0_to_eir, n3v0, md2)
  if (~n0_to_eir) begin
    n_t_4x_m <= 1'b0;
  end else
  if (~n3v0) begin
    n_t_4x_m <= 1'b1;
  end else
  if (~(ld_eir)) begin
    n_t_4x_m <= ~md2;
  end
always @(ld_eir, n0_to_eir, n3v0, n_t_4x_m)
  if (~n0_to_eir) begin
    n_t_4x <= 1'b0;
  end else
  if (~n3v0) begin
    n_t_4x <= 1'b1;
  end else
  if (ld_eir) begin
    n_t_4x <= n_t_4x_m;
  end
always @(ld_eir, n0_to_eir, n3v0, md3)
  if (~n0_to_eir) begin
    n_t_5x_m <= 1'b0;
  end else
  if (~n3v0) begin
    n_t_5x_m <= 1'b1;
  end else
  if (~(ld_eir)) begin
    n_t_5x_m <= ~md3;
  end
always @(ld_eir, n0_to_eir, n3v0, n_t_5x_m)
  if (~n0_to_eir) begin
    n_t_5x <= 1'b0;
  end else
  if (~n3v0) begin
    n_t_5x <= 1'b1;
  end else
  if (ld_eir) begin
    n_t_5x <= n_t_5x_m;
  end
// e11: dec23001a1 
assign e11_10x01 = (eir3 & ~eir2 & ~dad_or_dst & n_t_21x);
assign e11_1011x = (eir3 & ~eir2 & ~n_t_11x & dad_or_dst);
// rom_11_l = !(!n_t_25x & (e11_10x01
//                     # e11_1011x)); 
assign e11_00x10 = (~eir3 & ~eir2 & dad_or_dst & ~n_t_21x);
assign e11_x1001 = (eir2 & n_t_11x & ~dad_or_dst & n_t_21x);
assign e11_0x111 = (~eir3 & ~n_t_11x & dad_or_dst & n_t_21x);
assign e11_01101 = (~eir3 & eir2 & ~n_t_11x & ~dad_or_dst & n_t_21x);
assign e11_01110 = (~eir3 & eir2 & ~n_t_11x & dad_or_dst & ~n_t_21x);
assign e11_10011 = (eir3 & ~eir2 & n_t_11x & dad_or_dst & n_t_21x);
// rom_12_l = !(!n_t_25x & (e11_00x10
//                     # e11_x1001
//                     # e11_0x111
//                     # e11_10x01
//                     # e11_01101
//                     # e11_01110
//                     # e11_10011)); 
assign e11_00010 = (~eir3 & ~eir2 & n_t_11x & dad_or_dst & ~n_t_21x);
assign e11_00100 = (~eir3 & ~eir2 & ~n_t_11x & ~dad_or_dst & ~n_t_21x);
assign e11_100x1 = (eir3 & ~eir2 & n_t_11x & n_t_21x);
// rom_13_l = !(!n_t_25x & (e11_00010
//                     # e11_00100
//                     # e11_x1001
//                     # e11_100x1)); 
assign e11_0111x = (~eir3 & eir2 & ~n_t_11x & dad_or_dst);
assign e11_10010 = (eir3 & ~eir2 & n_t_11x & dad_or_dst & ~n_t_21x);
// rom_14_l = !(!n_t_25x & (e11_00100
//                     # e11_0111x
//                     # e11_10x01
//                     # e11_10010)); 
assign e11_01x01 = (~eir3 & eir2 & ~dad_or_dst & n_t_21x);
assign e11_00111 = (~eir3 & ~eir2 & ~n_t_11x & dad_or_dst & n_t_21x);
// rom_15_l = !(!n_t_25x & (e11_00x10
//                     # e11_00100
//                     # e11_01x01
//                     # e11_00111)); 
assign e11_x0010 = (~eir2 & n_t_11x & dad_or_dst & ~n_t_21x);
assign e11_011x1 = (~eir3 & eir2 & ~n_t_11x & n_t_21x);
// adlk_dis_l = !(!n_t_25x & (e11_x0010
//                       # e11_011x1
//                       # e11_01110
//                       # e11_100x1)); 
// rom_17_l = !(!n_t_25x & (e11_x0010
//                     # e11_100x1)); 
assign e11_x0111 = (~eir2 & ~n_t_11x & dad_or_dst & n_t_21x);
assign e11_10x10 = (eir3 & ~eir2 & dad_or_dst & ~n_t_21x);
assign e11_10101 = (eir3 & ~eir2 & ~n_t_11x & ~dad_or_dst & n_t_21x);
// rom_19_l = !(!n_t_25x & (e11_00x10
//                     # e11_00100
//                     # e11_x0111
//                     # e11_10x10
//                     # e11_011x1
//                     # e11_01110
//                     # e11_100x1
//                     # e11_10101)); 
// e12: sn74h11 
assign ld_eir = tp2 & ~fetch & ~fetch;
// e14: sn7474 
always @(ld_eir, n3v0, n0_to_eir, md4)
  if (~n3v0) begin
    n_t_3x_m <= 1'b0;
  end else
  if (~n0_to_eir) begin
    n_t_3x_m <= 1'b1;
  end else
  if (~(ld_eir)) begin
    n_t_3x_m <= md4;
  end
always @(ld_eir, n3v0, n0_to_eir, n_t_3x_m)
  if (~n3v0) begin
    n_t_3x <= 1'b0;
  end else
  if (~n0_to_eir) begin
    n_t_3x <= 1'b1;
  end else
  if (ld_eir) begin
    n_t_3x <= n_t_3x_m;
  end
always @(ld_eir, n3v0, n0_to_eir, md5)
  if (~n3v0) begin
    n_t_8x_m <= 1'b0;
  end else
  if (~n0_to_eir) begin
    n_t_8x_m <= 1'b1;
  end else
  if (~(ld_eir)) begin
    n_t_8x_m <= md5;
  end
always @(ld_eir, n3v0, n0_to_eir, n_t_8x_m)
  if (~n3v0) begin
    n_t_8x <= 1'b0;
  end else
  if (~n0_to_eir) begin
    n_t_8x <= 1'b1;
  end else
  if (ld_eir) begin
    n_t_8x <= n_t_8x_m;
  end
// e15: sn74h30 
assign swba = ~(n_t_3x & n_t_8x & ~n_t_14x & n_t_10x & n_t_11x & eir2 & eir3 & n3v0);
// e16: sn74h04 
assign dad_or_dst_l = ~dad_or_dst;
assign data_to_sc = ~rom_21_l;
// e17: sp384n 
// e18: sn7474 
always @(ld_eir, n3v0, n0_to_eir, md6)
  if (~n3v0) begin
    n_t_14x_m <= 1'b0;
  end else
  if (~n0_to_eir) begin
    n_t_14x_m <= 1'b1;
  end else
  if (~(ld_eir)) begin
    n_t_14x_m <= md6;
  end
always @(ld_eir, n3v0, n0_to_eir, n_t_14x_m)
  if (~n3v0) begin
    n_t_14x <= 1'b0;
  end else
  if (~n0_to_eir) begin
    n_t_14x <= 1'b1;
  end else
  if (ld_eir) begin
    n_t_14x <= n_t_14x_m;
  end
always @(ld_eir, n3v0, n0_to_eir, md7)
  if (~n3v0) begin
    n_t_10x_m <= 1'b0;
  end else
  if (~n0_to_eir) begin
    n_t_10x_m <= 1'b1;
  end else
  if (~(ld_eir)) begin
    n_t_10x_m <= md7;
  end
always @(ld_eir, n3v0, n0_to_eir, n_t_10x_m)
  if (~n3v0) begin
    n_t_10x <= 1'b0;
  end else
  if (~n0_to_eir) begin
    n_t_10x <= 1'b1;
  end else
  if (ld_eir) begin
    n_t_10x <= n_t_10x_m;
  end
// e19: dec23002a1 
assign e19_001x1 = (~eir3 & ~eir2 & ~n_t_11x & modea);
assign e19_x0110 = (~eir2 & ~n_t_11x & ~n_t_14x & ~modea);
assign e19_1111x = (eir3 & eir2 & ~n_t_11x & ~n_t_14x);
assign e19_100x1 = (eir3 & ~eir2 & n_t_11x & modea);
assign e19_1x010 = (eir3 & n_t_11x & ~n_t_14x & ~modea);
assign e19_110x1 = (eir3 & eir2 & n_t_11x & modea);
assign e19_1x101 = (eir3 & ~n_t_11x & n_t_14x & modea);
assign e19_10111 = (eir3 & ~eir2 & ~n_t_11x & ~n_t_14x & modea);
// rom_21_l = !(!n_t_21x & (e19_001x1
//                     # e19_x0110
//                     # e19_1111x
//                     # e19_100x1
//                     # e19_1x010
//                     # e19_110x1
//                     # e19_1x101
//                     # e19_10111)); 
assign e19_0001x = (~eir3 & ~eir2 & n_t_11x & ~n_t_14x);
assign e19_00101 = (~eir3 & ~eir2 & ~n_t_11x & n_t_14x & modea);
assign e19_x1001 = (eir2 & n_t_11x & n_t_14x & modea);
assign e19_01010 = (~eir3 & eir2 & n_t_11x & ~n_t_14x & ~modea);
assign e19_10001 = (eir3 & ~eir2 & n_t_11x & n_t_14x & modea);
// rom_22_l = !(!n_t_21x & (e19_0001x
//                     # e19_1x101
//                     # e19_00101
//                     # e19_x1001
//                     # e19_01010
//                     # e19_10001)); 
assign e19_1x011 = (eir3 & n_t_11x & ~n_t_14x & modea);
assign e19_x1010 = (eir2 & n_t_11x & ~n_t_14x & ~modea);
assign e19_10010 = (eir3 & ~eir2 & n_t_11x & ~n_t_14x & ~modea);
// rom_23_l = !(!n_t_21x & (e19_0001x
//                     # e19_1x011
//                     # e19_x1001
//                     # e19_x1010
//                     # e19_10001
//                     # e19_10010)); 
assign e19_x0101 = (~eir2 & ~n_t_11x & n_t_14x & modea);
assign e19_010x0 = (~eir3 & eir2 & n_t_11x & ~modea);
assign e19_11x00 = (eir3 & eir2 & n_t_14x & ~modea);
assign e19_1101x = (eir3 & eir2 & n_t_11x & ~n_t_14x);
// rom_24_l = !(!n_t_21x & (e19_x0101
//                     # e19_010x0
//                     # e19_1111x
//                     # e19_10001
//                     # e19_11x00
//                     # e19_1101x)); 
assign e19_11x11 = (eir3 & eir2 & ~n_t_14x & modea);
assign e19_00110 = (~eir3 & ~eir2 & ~n_t_11x & ~n_t_14x & ~modea);
assign e19_11x10 = (eir3 & eir2 & ~n_t_14x & ~modea);
assign e19_0100x = (~eir3 & eir2 & n_t_11x & n_t_14x);
assign e19_01100 = (~eir3 & eir2 & ~n_t_11x & n_t_14x & ~modea);
// rom_25_l = !(!n_t_21x & (e19_0001x
//                     # e19_11x11
//                     # e19_001x1
//                     # e19_00110
//                     # e19_11x10
//                     # e19_0100x
//                     # e19_01100)); 
assign e19_1110x = (eir3 & eir2 & ~n_t_11x & n_t_14x);
assign e19_0x100 = (~eir3 & ~n_t_11x & n_t_14x & ~modea);
assign e19_10100 = (eir3 & ~eir2 & ~n_t_11x & n_t_14x & ~modea);
// rom_26_l = !(!n_t_21x & (e19_0001x
//                     # e19_1110x
//                     # e19_0x100
//                     # e19_1x011
//                     # e19_10001
//                     # e19_1x010
//                     # e19_10100)); 
assign e19_011x1 = (~eir3 & eir2 & ~n_t_11x & modea);
assign e19_01110 = (~eir3 & eir2 & ~n_t_11x & ~n_t_14x & ~modea);
// fd_set = !(!n_t_21x & (e19_0001x
//                   # e19_1x011
//                   # e19_011x1
//                   # e19_01110
//                   # e19_1x010
//                   # e19_10001)); 
assign e19_000x1 = (~eir3 & ~eir2 & n_t_11x & modea);
assign e19_00x10 = (~eir3 & ~eir2 & ~n_t_14x & ~modea);
assign e19_0010x = (~eir3 & ~eir2 & ~n_t_11x & n_t_14x);
assign e19_0x111 = (~eir3 & ~n_t_11x & ~n_t_14x & modea);
assign e19_0110x = (~eir3 & eir2 & ~n_t_11x & n_t_14x);
assign e19_1011x = (eir3 & ~eir2 & ~n_t_11x & ~n_t_14x);
assign e19_10x01 = (eir3 & ~eir2 & n_t_14x & modea);
// fe_set = !(!n_t_21x & (e19_000x1
//                   # e19_00x10
//                   # e19_1111x
//                   # e19_0010x
//                   # e19_1110x
//                   # e19_1x011
//                   # e19_0x111
//                   # e19_0110x
//                   # e19_1011x
//                   # e19_01110
//                   # e19_10x01
//                   # e19_10100
//                   # e19_1x010)); 
// e20: sp380n 
assign n_t_53x = ~(dad_or_dst_l
                    | defer);
// e21: sp384n 
// e22: sn7474 
always @(ld_eir, n3v, n0_to_eir, md8)
  if (~n3v) begin
    n_t_11x_m <= 1'b0;
  end else
  if (~n0_to_eir) begin
    n_t_11x_m <= 1'b1;
  end else
  if (~(ld_eir)) begin
    n_t_11x_m <= md8;
  end
always @(ld_eir, n3v, n0_to_eir, n_t_11x_m)
  if (~n3v) begin
    n_t_11x <= 1'b0;
  end else
  if (~n0_to_eir) begin
    n_t_11x <= 1'b1;
  end else
  if (ld_eir) begin
    n_t_11x <= n_t_11x_m;
  end
always @(ld_eir, n3v, n0_to_eir, md9)
  if (~n3v) begin
    n_t_17x_m <= 1'b0;
  end else
  if (~n0_to_eir) begin
    n_t_17x_m <= 1'b1;
  end else
  if (~(ld_eir)) begin
    n_t_17x_m <= md9;
  end
always @(ld_eir, n3v, n0_to_eir, n_t_17x_m)
  if (~n3v) begin
    n_t_17x <= 1'b0;
  end else
  if (~n0_to_eir) begin
    n_t_17x <= 1'b1;
  end else
  if (ld_eir) begin
    n_t_17x <= n_t_17x_m;
  end
assign eir2 = ~n_t_17x;
// e23: sn74h30 
assign swab = ~(n_t_3x & n_t_8x & n_t_14x & ~n_t_10x & ~n_t_11x & n_t_17x & n_t_18x & n3v);
// e24: sn7410 
assign sc_0_l = ~(~n_t_39x & n_t_48x & n_t_49x);
// e25: sp380n 
assign n_t_43x = ~(data_to_sc
                    | md7);
assign sc_to_data = ~(ts3
                       | rom_25_l);
// e26: sn7474 
always @(ld_eir, n3v, n0_to_eir, md10)
  if (~n3v) begin
    n_t_18x_m <= 1'b0;
  end else
  if (~n0_to_eir) begin
    n_t_18x_m <= 1'b1;
  end else
  if (~(ld_eir)) begin
    n_t_18x_m <= md10;
  end
always @(ld_eir, n3v, n0_to_eir, n_t_18x_m)
  if (~n3v) begin
    n_t_18x <= 1'b0;
  end else
  if (~n0_to_eir) begin
    n_t_18x <= 1'b1;
  end else
  if (ld_eir) begin
    n_t_18x <= n_t_18x_m;
  end
assign eir3 = ~n_t_18x;
always @(ld_eir, n0_to_eir, n3v, md11)
  if (~n0_to_eir) begin
    n_t_7x_m <= 1'b0;
  end else
  if (~n3v) begin
    n_t_7x_m <= 1'b1;
  end else
  if (~(ld_eir)) begin
    n_t_7x_m <= ~md11;
  end
always @(ld_eir, n0_to_eir, n3v, n_t_7x_m)
  if (~n0_to_eir) begin
    n_t_7x <= 1'b0;
  end else
  if (~n3v) begin
    n_t_7x <= 1'b1;
  end else
  if (ld_eir) begin
    n_t_7x <= n_t_7x_m;
  end
// e27: sn74h00 
assign next_loc = ~(rom_26_l & ~ex1);
assign n_t_24x = ~(e & fetch);
assign n_t_51x = ~(tp4 & ma_ms_lc);
// e28: sn74h11 
assign n_t_27x = eae_inst & ld_eir;
assign div_12_l = ~(n_t_42x & n_t_39x & n_t_40x);
assign dad_or_dst = ~n_t_14x & modeb & eae_inst;
// e29: sp384n 
// e30: sn74h74 
always @(tp2_d, tp3, n3v, rom_21_l)
  if (tp3) begin
    n_t_26x_m <= 1'b0;
  end else
  if (~n3v) begin
    n_t_26x_m <= 1'b1;
  end else
  if (~(tp2_d)) begin
    n_t_26x_m <= ~rom_21_l;
  end
always @(tp2_d, tp3, n3v, n_t_26x_m)
  if (tp3) begin
    n_t_26x <= 1'b0;
  end else
  if (~n3v) begin
    n_t_26x <= 1'b1;
  end else
  if (tp2_d) begin
    n_t_26x <= n_t_26x_m;
  end
always @(n_t_51x, fetch, n3v, n_t_53x)
  if (~fetch) begin
    ex1_m <= 1'b0;
  end else
  if (~n3v) begin
    ex1_m <= 1'b1;
  end else
  if (~(~n_t_51x)) begin
    ex1_m <= n_t_53x;
  end
always @(n_t_51x, fetch, n3v, ex1_m)
  if (~fetch) begin
    ex1 <= 1'b0;
  end else
  if (~n3v) begin
    ex1 <= 1'b1;
  end else
  if (~n_t_51x) begin
    ex1 <= ex1_m;
  end
// e31: sn7402 
assign n_t_49x = ~(n_t_38x
                    | n_t_19x);
assign n_t_48x = ~(n_t_42x
                    | n_t_40x);
assign sc_load_l = ~(n_t_54x
                      | n_t_26x);
assign n_t_54x = ~(rom_19_l
                    | ~tp2_d);
// e32: sp384n 
// e33: sn7412 
// last_step_l = !(n_t_38x & n_t_19x & !div_12_l); 
// last_step_l = !(n_t_19x & exec_divide & n_t_42x); 
// last_step_l = !(exec_multiply & n_t_49x & !div_12_l); 
// e34: sn74193 
always @(n3v, n_t_46x, n0_to_sc, sc_load_l, n_t_44x, sc_load_l, n_t_44x, n_t_38x)
  if (n0_to_sc
                     | ~sc_load_l & ~n_t_44x) begin
    n_t_38x_m <= 1'b0;
  end else
  if (~sc_load_l & n_t_44x) begin
    n_t_38x_m <= 1'b1;
  end else
  if (~(~(~n3v
                       | ~n_t_46x))) begin
    n_t_38x_m <= ~n_t_38x;
  end
always @(n3v, n_t_46x, n0_to_sc, sc_load_l, n_t_44x, sc_load_l, n_t_44x, n_t_38x_m)
  if (n0_to_sc
                     | ~sc_load_l & ~n_t_44x) begin
    n_t_38x <= 1'b0;
  end else
  if (~sc_load_l & n_t_44x) begin
    n_t_38x <= 1'b1;
  end else
  if (~(~n3v
                       | ~n_t_46x)) begin
    n_t_38x <= n_t_38x_m;
  end
always @(n3v, n_t_38x, n_t_46x, n_t_38x, n0_to_sc, sc_load_l, gdollar_0)
  if (n0_to_sc
                       | ~sc_load_l) begin
    gdollar_0_m <= 1'b0;
  end else
  if (~(~(~n3v & ~n_t_38x
                         | ~n_t_46x & n_t_38x))) begin
    gdollar_0_m <= ~gdollar_0;
  end
always @(n3v, n_t_38x, n_t_46x, n_t_38x, n0_to_sc, sc_load_l, gdollar_0_m)
  if (n0_to_sc
                       | ~sc_load_l) begin
    gdollar_0 <= 1'b0;
  end else
  if (~(~n3v & ~n_t_38x
                         | ~n_t_46x & n_t_38x)) begin
    gdollar_0 <= gdollar_0_m;
  end
always @(n3v, n_t_38x, gdollar_0, n_t_46x, n_t_38x, gdollar_0, n0_to_sc, sc_load_l, gdollar_1)
  if (n0_to_sc
                       | ~sc_load_l) begin
    gdollar_1_m <= 1'b0;
  end else
  if (~(~(~n3v & ~n_t_38x & ~gdollar_0
                         | ~n_t_46x & n_t_38x & gdollar_0))) begin
    gdollar_1_m <= ~gdollar_1;
  end
always @(n3v, n_t_38x, gdollar_0, n_t_46x, n_t_38x, gdollar_0, n0_to_sc, sc_load_l, gdollar_1_m)
  if (n0_to_sc
                       | ~sc_load_l) begin
    gdollar_1 <= 1'b0;
  end else
  if (~(~n3v & ~n_t_38x & ~gdollar_0
                         | ~n_t_46x & n_t_38x & gdollar_0)) begin
    gdollar_1 <= gdollar_1_m;
  end
always @(n3v, gdollar_1, n_t_38x, gdollar_0, n_t_46x, gdollar_1, n_t_38x, gdollar_0, n0_to_sc, sc_load_l, gdollar_2)
  if (n0_to_sc
                       | ~sc_load_l) begin
    gdollar_2_m <= 1'b0;
  end else
  if (~(~(~n3v & ~gdollar_1 & ~n_t_38x & ~gdollar_0
                         | ~n_t_46x & gdollar_1 & n_t_38x & gdollar_0))) begin
    gdollar_2_m <= ~gdollar_2;
  end
always @(n3v, gdollar_1, n_t_38x, gdollar_0, n_t_46x, gdollar_1, n_t_38x, gdollar_0, n0_to_sc, sc_load_l, gdollar_2_m)
  if (n0_to_sc
                       | ~sc_load_l) begin
    gdollar_2 <= 1'b0;
  end else
  if (~(~n3v & ~gdollar_1 & ~n_t_38x & ~gdollar_0
                         | ~n_t_46x & gdollar_1 & n_t_38x & gdollar_0)) begin
    gdollar_2 <= gdollar_2_m;
  end
// e35: sn97401 
// data11 = !(n_t_39x & sc_to_data); 
// data10 = !(n_t_40x & sc_to_data); 
// data8 = !(sc_to_data & n_t_42x); 
// data9 = !(sc_to_data & n_t_19x); 
// e36: mc8266 
assign n_t_37x = ~(~md8 & ~data_to_sc
                    | data8 & data_to_sc);
assign n_t_36x = ~(~md9 & ~data_to_sc
                    | data9 & data_to_sc);
assign n_t_35x = ~(~md10 & ~data_to_sc
                    | data10 & data_to_sc);
assign n_t_34x = ~(~md11 & ~data_to_sc
                    | data11 & data_to_sc);
// e37: sn74193 
always @(n3v, incr_sc, n0_to_sc, sc_load_l, n_t_34x, sc_load_l, n_t_34x, n_t_39x)
  if (n0_to_sc
                     | ~sc_load_l & ~n_t_34x) begin
    n_t_39x_m <= 1'b0;
  end else
  if (~sc_load_l & n_t_34x) begin
    n_t_39x_m <= 1'b1;
  end else
  if (~(~(~n3v
                       | ~incr_sc))) begin
    n_t_39x_m <= ~n_t_39x;
  end
always @(n3v, incr_sc, n0_to_sc, sc_load_l, n_t_34x, sc_load_l, n_t_34x, n_t_39x_m)
  if (n0_to_sc
                     | ~sc_load_l & ~n_t_34x) begin
    n_t_39x <= 1'b0;
  end else
  if (~sc_load_l & n_t_34x) begin
    n_t_39x <= 1'b1;
  end else
  if (~(~n3v
                       | ~incr_sc)) begin
    n_t_39x <= n_t_39x_m;
  end
always @(n3v, n_t_39x, incr_sc, n_t_39x, n0_to_sc, sc_load_l, n_t_35x, sc_load_l, n_t_35x, n_t_40x)
  if (n0_to_sc
                     | ~sc_load_l & ~n_t_35x) begin
    n_t_40x_m <= 1'b0;
  end else
  if (~sc_load_l & n_t_35x) begin
    n_t_40x_m <= 1'b1;
  end else
  if (~(~(~n3v & ~n_t_39x
                       | ~incr_sc & n_t_39x))) begin
    n_t_40x_m <= ~n_t_40x;
  end
always @(n3v, n_t_39x, incr_sc, n_t_39x, n0_to_sc, sc_load_l, n_t_35x, sc_load_l, n_t_35x, n_t_40x_m)
  if (n0_to_sc
                     | ~sc_load_l & ~n_t_35x) begin
    n_t_40x <= 1'b0;
  end else
  if (~sc_load_l & n_t_35x) begin
    n_t_40x <= 1'b1;
  end else
  if (~(~n3v & ~n_t_39x
                       | ~incr_sc & n_t_39x)) begin
    n_t_40x <= n_t_40x_m;
  end
always @(n3v, n_t_39x, n_t_40x, incr_sc, n_t_39x, n_t_40x, n0_to_sc, sc_load_l, n_t_36x, sc_load_l, n_t_36x, n_t_19x)
  if (n0_to_sc
                     | ~sc_load_l & ~n_t_36x) begin
    n_t_19x_m <= 1'b0;
  end else
  if (~sc_load_l & n_t_36x) begin
    n_t_19x_m <= 1'b1;
  end else
  if (~(~(~n3v & ~n_t_39x & ~n_t_40x
                       | ~incr_sc & n_t_39x & n_t_40x))) begin
    n_t_19x_m <= ~n_t_19x;
  end
always @(n3v, n_t_39x, n_t_40x, incr_sc, n_t_39x, n_t_40x, n0_to_sc, sc_load_l, n_t_36x, sc_load_l, n_t_36x, n_t_19x_m)
  if (n0_to_sc
                     | ~sc_load_l & ~n_t_36x) begin
    n_t_19x <= 1'b0;
  end else
  if (~sc_load_l & n_t_36x) begin
    n_t_19x <= 1'b1;
  end else
  if (~(~n3v & ~n_t_39x & ~n_t_40x
                       | ~incr_sc & n_t_39x & n_t_40x)) begin
    n_t_19x <= n_t_19x_m;
  end
always @(n3v, n_t_19x, n_t_39x, n_t_40x, incr_sc, n_t_19x, n_t_39x, n_t_40x, n0_to_sc, sc_load_l, n_t_37x, sc_load_l, n_t_37x, n_t_42x)
  if (n0_to_sc
                     | ~sc_load_l & ~n_t_37x) begin
    n_t_42x_m <= 1'b0;
  end else
  if (~sc_load_l & n_t_37x) begin
    n_t_42x_m <= 1'b1;
  end else
  if (~(~(~n3v & ~n_t_19x & ~n_t_39x & ~n_t_40x
                       | ~incr_sc & n_t_19x & n_t_39x & n_t_40x))) begin
    n_t_42x_m <= ~n_t_42x;
  end
always @(n3v, n_t_19x, n_t_39x, n_t_40x, incr_sc, n_t_19x, n_t_39x, n_t_40x, n0_to_sc, sc_load_l, n_t_37x, sc_load_l, n_t_37x, n_t_42x_m)
  if (n0_to_sc
                     | ~sc_load_l & ~n_t_37x) begin
    n_t_42x <= 1'b0;
  end else
  if (~sc_load_l & n_t_37x) begin
    n_t_42x <= 1'b1;
  end else
  if (~(~n3v & ~n_t_19x & ~n_t_39x & ~n_t_40x
                       | ~incr_sc & n_t_19x & n_t_39x & n_t_40x)) begin
    n_t_42x <= n_t_42x_m;
  end
assign n_t_46x = n_t_39x & n_t_40x & n_t_19x & n_t_42x;
// open collector 'wire-or's 
assign adlk_dis_l = (~n_t_25x & (e11_x0010
                                  | e11_011x1
                                  | e11_01110
                                  | e11_100x1))? 1'b0: 1'bz;
assign c0 = (n_t_26x & modeb)? 1'b0: 1'bz;
assign data10 = (n_t_40x & sc_to_data)? 1'b0: 1'bz;
assign data11 = (n_t_39x & sc_to_data)? 1'b0: 1'bz;
assign data7 = (sc_to_data & n_t_38x)? 1'b0: 1'bz;
assign data8 = (sc_to_data & n_t_42x)? 1'b0: 1'bz;
assign data9 = (sc_to_data & n_t_19x)? 1'b0: 1'bz;
assign fd_set = (~n_t_21x & (e19_0001x
                              | e19_1x011
                              | e19_011x1
                              | e19_01110
                              | e19_1x010
                              | e19_10001))? 1'b0: 1'bz;
assign fe_set = (ex1 & ~e)
                 | (~n_t_21x & (e19_000x1
                                | e19_00x10
                                | e19_1111x
                                | e19_0010x
                                | e19_1110x
                                | e19_1x011
                                | e19_0x111
                                | e19_0110x
                                | e19_1011x
                                | e19_01110
                                | e19_10x01
                                | e19_10100
                                | e19_1x010))? 1'b0: 1'bz;
assign last_step_l = (n_t_38x & n_t_19x & ~div_12_l)
                      | (n_t_19x & exec_divide & n_t_42x)
                      | (exec_multiply & n_t_49x & ~div_12_l)? 1'b0: 1'bz;
assign n0_to_eir = (~n_t_51x & int_in_prog)
                    | (~fetch & tp1)? 1'b0: 1'bz;
assign n_t_44x = (data_to_sc & data7)
                  | n_t_43x? 1'b0: 1'bz;
assign rom_11_l = (~n_t_25x & (e11_10x01
                                | e11_1011x))? 1'b0: 1'bz;
assign rom_12_l = (~n_t_25x & (e11_00x10
                                | e11_x1001
                                | e11_0x111
                                | e11_10x01
                                | e11_01101
                                | e11_01110
                                | e11_10011))? 1'b0: 1'bz;
assign rom_13_l = (~n_t_25x & (e11_00010
                                | e11_00100
                                | e11_x1001
                                | e11_100x1))? 1'b0: 1'bz;
assign rom_14_l = (~n_t_25x & (e11_00100
                                | e11_0111x
                                | e11_10x01
                                | e11_10010))? 1'b0: 1'bz;
assign rom_15_l = (~n_t_25x & (e11_00x10
                                | e11_00100
                                | e11_01x01
                                | e11_00111))? 1'b0: 1'bz;
assign rom_17_l = (~n_t_25x & (e11_x0010
                                | e11_100x1))? 1'b0: 1'bz;
assign rom_19_l = (~n_t_25x & (e11_00x10
                                | e11_00100
                                | e11_x0111
                                | e11_10x10
                                | e11_011x1
                                | e11_01110
                                | e11_100x1
                                | e11_10101))? 1'b0: 1'bz;
assign rom_21_l = (~n_t_21x & (e19_001x1
                                | e19_x0110
                                | e19_1111x
                                | e19_100x1
                                | e19_1x010
                                | e19_110x1
                                | e19_1x101
                                | e19_10111))? 1'b0: 1'bz;
assign rom_22_l = (~n_t_21x & (e19_0001x
                                | e19_1x101
                                | e19_00101
                                | e19_x1001
                                | e19_01010
                                | e19_10001))? 1'b0: 1'bz;
assign rom_23_l = (~n_t_21x & (e19_0001x
                                | e19_1x011
                                | e19_x1001
                                | e19_x1010
                                | e19_10001
                                | e19_10010))? 1'b0: 1'bz;
assign rom_24_l = (~n_t_21x & (e19_x0101
                                | e19_010x0
                                | e19_1111x
                                | e19_10001
                                | e19_11x00
                                | e19_1101x))? 1'b0: 1'bz;
assign rom_25_l = (~n_t_21x & (e19_0001x
                                | e19_11x11
                                | e19_001x1
                                | e19_00110
                                | e19_11x10
                                | e19_0100x
                                | e19_01100))? 1'b0: 1'bz;
assign rom_26_l = (~n_t_21x & (e19_0001x
                                | e19_1110x
                                | e19_0x100
                                | e19_1x011
                                | e19_10001
                                | e19_1x010
                                | e19_10100))? 1'b0: 1'bz;
endmodule