~/Verilog/bin/topld.pl M8341D
info: cpol_use ne cpol_use20_8axial
info: cpol_use ne cpol_use20_8axial
info: cpol_use ne cpol_use20_8axial
info: 74h74n ne 7474n
info: 7486n ne dil14
info: 74h11n ne 7411n
info: 74h74n ne 7474n
info: 7410n ne dil14
info: 7412n ne dil14
info: dec8235 ne dil16
info: 74h74n ne 7474n
info: sn97401 ne 7401n
info: 7410n ne dil14
info: dec8235 ne dil16
info: 74h74n ne 7474n
info: n8881n ne dil14
info: 7416n ne dil14
info: dec8235 ne dil16
info: sn97401 ne 7401n
info: 7486n ne dil14
info: dec8235 ne dil16
info: sp380n ne dil14
info: sp380n ne dil14
info: sp384n ne dil14
info: dec8235 ne dil16
info: n8881n ne dil14
info: 7410n ne dil14
info: 7402n ne dil14
info: 7410n ne dil14
info: n8881n ne dil14
info: sn97401 ne 7401n
info: sp380n ne dil14
info: 74h74n ne 7474n
info: dm8093 ne 74125n
info: 74h74n ne 7474n
info: 7402n ne dil14
info: 74h53n ne dil14
info: 7402n ne dil14
info: edge_top ne edge_con2
warning: making f/edge_top/ a connector
info: edge_top ne edge_con2
warning: making h/edge_top/ a connector
info: quad ne edge_con8
warning: making u$2/quad/ a connector
~/Verilog/bin/smaller.pl M8341D.PLD >vv || (rm vv; exit 1)
40 signals were removed:
  bmq0: !mq0_l
  btp3: tp3
  clock_l: !clock
  eae_on_l: !eae_on
  fetch_l: !fetch
  gdollar_0: shift_ok
  gdollar_1: !gdollar_0
  init_l: !init
  n3va: 'b'1
  n3vb: 'b'1
  n3vc: 'b'1
  n_t_11x: !bac0
  n_t_12x: !n_t_33x
  n_t_14x: !rom_24_l
  n_t_16x: !ad0_l
  n_t_17x: !n_t_77x
  n_t_1x: !mq11_l
  n_t_20x: !n_t_19x
  n_t_25x: !btp3
  n_t_29x: !n_t_28x
  n_t_2x: !tp2
  n_t_30x: !last_step_l
  n_t_31x: !ac_to_mq_ena_l
  n_t_37x: !ac_load_l
  n_t_39x: !sgt_l
  n_t_41x: !n_t_43x
  n_t_50x: !rom_11_l
  n_t_55x: !msir_disable
  n_t_57x: !en2
  n_t_58x: !rom_14_l
  n_t_59x: !tp2_d
  n_t_62x: !n_t_23x
  n_t_6x: !ac4_11_0
  n_t_71x: !rom_17_l
  n_t_7x: !n_t_84x
  n_t_8x: !rom_12
  n_t_91x: !last_step_l
  rom_12: !rom_12_l
  shift3: !rom_15_l
  ts3_l: !ts3
~/Verilog/bin/smaller.pl vv >M8341DX.PLD || (rm M8341DX.PLD; exit 1)
1 signals were removed:
  gdollar_0: shift_ok
~/Verilog/bin/cupl2v.pl M8341DX.PLD >vv || (rm vv; exit 1)
mv vv M8341D.v
rm M8341DX.PLD