// this file is generated by topld.pl // please don't edit it. // input pins // output pins // internal nodes // code nodes // equations // c1: c_us // c2: c_us // c3: c_us // c4: c_us // c5: c_us // c6: c_us // c7: c_us // c8: c_us // c9: c_us // c10: c_us // c11: c_us // c12: c_us // c13: c_us // c14: c_us // c15: c_us // c16: c_us // c17: c_us // c18: c_us // c19: c_us // c20: c_us // c21: c_us // c22: c_us // c23: c_us // c24: c_us // c25: c_us // c26: c_us // c27: c_us // c28: c_us // c29: c_us // c30: c_us // c31: c_us // c32: c_us // c33: c_us // c34: c_us // c35: c_us // c36: c_us // c37: c_us // c38: c_us // c39: c_us // c40: c_us // c41: c_us // c42: c_us // c43: c_us // c44: c_us // c45: cpol_use // c46: cpol_use // c47: cpol_use // c48: c_us // c49: c_us // c50: c_us // c51: c_us // c52: c_us // e1: sn7402 module m843e (data_strobe, i00, i01, i02, i03, i04, i05, i06, i07, i08, i09, i10, i11, n3v, n_t_13x, n_t_18x, n_t_22x, n_t_25x, n_t_34x, aj2, ak2, al2, c1_l, data0_l, data10_l, data11_l, data1_l, data2_l, data3_l, data4_l, data5_l, data6_l, data7_l, data8_l, data9_l, dclr, initialize, int_rqst_l, internal_io_l, io_pause_l, itclk, md03_l, md04_l, md05_l, md06_l, md07_l, md08_l, md09_l, md10_l, md11_l, n_t_11x, n_t_12x, n_t_14x, n_t_28x, n_t_6x, n_t_7x, n_t_9x, rcni, rcra, rcrb, rcrc, rcse, rdy, rdy2_l, read, skip_l, tclr_l, tp3); output data_strobe; input i00; input i01; input i02; input i03; input i04; input i05; input i06; input i07; input i08; input i09; input i10; input i11; input n3v; input n_t_13x; input n_t_18x; input n_t_22x; input n_t_25x; input n_t_34x; output aj2; output ak2; output al2; output c1_l; output data0_l; inout data10_l; inout data11_l; output data1_l; output data2_l; output data3_l; output data4_l; output data5_l; output data6_l; output data7_l; output data8_l; output data9_l; inout dclr; input initialize; output int_rqst_l; output internal_io_l; input io_pause_l; inout itclk; input md03_l; input md04_l; input md05_l; input md06_l; input md07_l; input md08_l; input md09_l; input md10_l; input md11_l; output n_t_11x; output n_t_12x; output n_t_14x; inout n_t_28x; input n_t_6x; output n_t_7x; output n_t_9x; inout rcni; inout rcra; inout rcrb; inout rcrc; inout rcse; inout rdy; inout rdy2_l; output read; output skip_l; inout tclr_l; input tp3; reg cdone_m; reg drdy_m; reg int_m; reg read_l_m; reg transit_m; reg trbl_m; reg zone1_m; reg zone10_m; reg zone11_m; reg zone12_m; reg zone2_m; reg zone3_m; reg zone4_m; reg zone5_m; reg zone6_m; reg zone7_m; reg zone8_m; reg zone9_m; reg read_l; reg transit; reg zone1; reg zone10; reg zone11; reg zone12; reg drdy; reg cdone; reg zone5; reg zone4; reg zone3; reg zone2; reg int; reg trbl; reg zone9; reg zone8; reg zone7; reg zone6; wire bcd1; wire bcd2; wire bcd4; wire cerr; wire iot63; wire iot67; wire md05p; wire md06p; wire md09p; wire md10p; wire md11p; wire n_t_10x; wire n_t_15x; wire n_t_19x; wire n_t_1x; wire n_t_20x; wire n_t_21x; wire n_t_23x; wire n_t_24x; wire n_t_29x; wire n_t_31x; wire n_t_32x; wire n_t_33x; wire n_t_35x; wire n_t_37x; wire n_t_38x; wire n_t_40x; wire n_t_41x; wire n_t_45x; wire n_t_46x; wire n_t_47x; wire n_t_4x; wire n_t_5x; wire n_t_8x; wire rcni_l; wire rcno_l; wire rcr; wire rcra_l; wire rcrb_l; wire rcrc_l; wire rcrd_l; wire rcsd_l; wire rcse_l; wire rcsf_l; wire rcsi_l; wire rctf_l; wire rdy1_l; wire strobe; assign n_t_46x = ~(rctf_l | ~tp3); assign tclr_l = ~(n_t_46x | initialize); assign rcni = ~rcni_l; assign itclk = ~(~tp3 | rcno_l); // e2: dec8251 assign rcsf_l = ~(iot63 & ~md09p & ~md10p & md11p); assign rcra_l = ~(iot63 & ~md09p & md10p & ~md11p); assign rcrb_l = ~(iot63 & md09p & ~md10p & ~md11p); assign rcno_l = ~(iot63 & md09p & ~md10p & md11p); assign rcrc_l = ~(iot63 & md09p & md10p & ~md11p); assign rcni_l = ~(iot63 & md09p & md10p & md11p); // e3: dec8251 assign rcsd_l = ~(iot67 & ~md09p & ~md10p & md11p); assign rcse_l = ~(iot67 & ~md09p & md10p & ~md11p); assign rcrd_l = ~(iot67 & md09p & ~md10p & ~md11p); assign rcsi_l = ~(iot67 & md09p & ~md10p & md11p); assign = ~(iot67 & md09p & md10p & ~md11p); assign rctf_l = ~(iot67 & md09p & md10p & md11p); // e4: sp380n assign md09p = ~(md09_l | io_pause_l); assign md10p = ~(md10_l | io_pause_l); assign md11p = ~(io_pause_l | md11_l); // e5: n8881n // data1_l = !(cdone & rcni); // data0_l = !(rcni & drdy); // data2_l = !(rdy2_l & n_t_5x); // data3_l = !(rdy & n_t_5x); // e6: sn7400 assign n_t_20x = ~(~zone10 & ~zone12); assign n_t_23x = ~(~zone12 & ~zone11); assign n_t_4x = ~(n_t_29x & ~initialize); // e7: sn7474 always @(dclr, n_t_38x, n_t_35x, 1'b1) if (~n_t_38x) begin read_l_m <= 1'b0; end else if (~n_t_35x) begin read_l_m <= 1'b1; end else if (~(dclr)) begin read_l_m <= 1'b1; end always @(dclr, n_t_38x, n_t_35x, read_l_m) if (~n_t_38x) begin read_l <= 1'b0; end else if (~n_t_35x) begin read_l <= 1'b1; end else if (dclr) begin read_l <= read_l_m; end always @(tclr_l, n_t_31x, 1'b0) if (~tclr_l) begin transit_m <= 1'b0; end else if (~n_t_31x) begin transit_m <= 1'b1; end else if (~(1'b0)) begin transit_m <= 1'b0; end always @(tclr_l, n_t_31x, transit_m) if (~tclr_l) begin transit <= 1'b0; end else if (~n_t_31x) begin transit <= 1'b1; end else if (1'b0) begin transit <= transit_m; end // e8: sn7404 assign rdy2_l = ~rdy; // e9: n8881n // data3_l = !(rcrb & zone1); // data2_l = !(rcrb & zone10); // data1_l = !(zone11 & rcrb); // data0_l = !(zone12 & rcrb); // e10: sn7475 always @(strobe, i03, strobe, i03, 1'b0) if (strobe & ~i03) begin zone1_m <= 1'b0; end else if (strobe & i03) begin zone1_m <= 1'b1; end else if (~(1'b0)) begin zone1_m <= 1'b0; end always @(strobe, i03, strobe, i03, zone1_m) if (strobe & ~i03) begin zone1 <= 1'b0; end else if (strobe & i03) begin zone1 <= 1'b1; end else if (1'b0) begin zone1 <= zone1_m; end always @(strobe, i02, strobe, i02, 1'b0) if (strobe & ~i02) begin zone10_m <= 1'b0; end else if (strobe & i02) begin zone10_m <= 1'b1; end else if (~(1'b0)) begin zone10_m <= 1'b0; end always @(strobe, i02, strobe, i02, zone10_m) if (strobe & ~i02) begin zone10 <= 1'b0; end else if (strobe & i02) begin zone10 <= 1'b1; end else if (1'b0) begin zone10 <= zone10_m; end always @(strobe, i01, strobe, i01, 1'b0) if (strobe & ~i01) begin zone11_m <= 1'b0; end else if (strobe & i01) begin zone11_m <= 1'b1; end else if (~(1'b0)) begin zone11_m <= 1'b0; end always @(strobe, i01, strobe, i01, zone11_m) if (strobe & ~i01) begin zone11 <= 1'b0; end else if (strobe & i01) begin zone11 <= 1'b1; end else if (1'b0) begin zone11 <= zone11_m; end always @(strobe, i00, strobe, i00, 1'b0) if (strobe & ~i00) begin zone12_m <= 1'b0; end else if (strobe & i00) begin zone12_m <= 1'b1; end else if (~(1'b0)) begin zone12_m <= 1'b0; end always @(strobe, i00, strobe, i00, zone12_m) if (strobe & ~i00) begin zone12 <= 1'b0; end else if (strobe & i00) begin zone12 <= 1'b1; end else if (1'b0) begin zone12 <= zone12_m; end // e11: sn7474 always @(strobe, n_t_4x, n3v, n_t_34x) if (n_t_4x) begin drdy_m <= 1'b0; end else if (~n3v) begin drdy_m <= 1'b1; end else if (~(strobe)) begin drdy_m <= n_t_34x; end always @(strobe, n_t_4x, n3v, drdy_m) if (n_t_4x) begin drdy <= 1'b0; end else if (~n3v) begin drdy <= 1'b1; end else if (strobe) begin drdy <= drdy_m; end always @(dclr, n_t_28x, n3v, n_t_34x) if (n_t_28x) begin cdone_m <= 1'b0; end else if (~n3v) begin cdone_m <= 1'b1; end else if (~(~dclr)) begin cdone_m <= n_t_34x; end always @(dclr, n_t_28x, n3v, cdone_m) if (n_t_28x) begin cdone <= 1'b0; end else if (~n3v) begin cdone <= 1'b1; end else if (~dclr) begin cdone <= cdone_m; end // e12: sp314n assign iot67 = ~(md06_l | md05p | md04_l | md03_l | io_pause_l | md07_l | md08_l); // e13: n8881n // data7_l = !(zone5 & rcrb); // data6_l = !(rcrb & zone4); // data0_l = !(rcrc & cerr); // e14: sn7440 assign rcrc = ~rcrc_l; assign rcrb = ~rcrb_l; // e15: n8881n // int_rqst_l = !(transit & trbl); // int_rqst_l = !(int & drdy); // int_rqst_l = !(int & cdone); // e16: sp314n assign iot63 = ~(md08_l | md07_l | md03_l | io_pause_l | md04_l | md05p | md06p); // e17: n8881n // data5_l = !(zone3 & rcrb); // data4_l = !(rcrb & zone2); // data4_l = !(zone9 & rcrc); // data5_l = !(rcrc & zone12); // e18: sn7475 always @(strobe, i07, strobe, i07, 1'b0) if (strobe & ~i07) begin zone5_m <= 1'b0; end else if (strobe & i07) begin zone5_m <= 1'b1; end else if (~(1'b0)) begin zone5_m <= 1'b0; end always @(strobe, i07, strobe, i07, zone5_m) if (strobe & ~i07) begin zone5 <= 1'b0; end else if (strobe & i07) begin zone5 <= 1'b1; end else if (1'b0) begin zone5 <= zone5_m; end always @(strobe, i06, strobe, i06, 1'b0) if (strobe & ~i06) begin zone4_m <= 1'b0; end else if (strobe & i06) begin zone4_m <= 1'b1; end else if (~(1'b0)) begin zone4_m <= 1'b0; end always @(strobe, i06, strobe, i06, zone4_m) if (strobe & ~i06) begin zone4 <= 1'b0; end else if (strobe & i06) begin zone4 <= 1'b1; end else if (1'b0) begin zone4 <= zone4_m; end always @(strobe, i05, strobe, i05, 1'b0) if (strobe & ~i05) begin zone3_m <= 1'b0; end else if (strobe & i05) begin zone3_m <= 1'b1; end else if (~(1'b0)) begin zone3_m <= 1'b0; end always @(strobe, i05, strobe, i05, zone3_m) if (strobe & ~i05) begin zone3 <= 1'b0; end else if (strobe & i05) begin zone3 <= 1'b1; end else if (1'b0) begin zone3 <= zone3_m; end always @(strobe, i04, strobe, i04, 1'b0) if (strobe & ~i04) begin zone2_m <= 1'b0; end else if (strobe & i04) begin zone2_m <= 1'b1; end else if (~(1'b0)) begin zone2_m <= 1'b0; end always @(strobe, i04, strobe, i04, zone2_m) if (strobe & ~i04) begin zone2 <= 1'b0; end else if (strobe & i04) begin zone2 <= 1'b1; end else if (1'b0) begin zone2 <= zone2_m; end // e19: sn7450 assign n_t_15x = ~(trbl & transit | int & n_t_40x); assign n_t_31x = ~(rdy & n_t_22x | ~n_t_22x & rdy2_l); // e20: n8881n // skip_l = !(rdy & rcse); // skip_l = !(!rcsi_l & !n_t_15x); // skip_l = !(drdy & !rcsf_l); // skip_l = !(cdone & !rcsd_l); // e21: n8881n // data7_l = !(zone10 & rcrc); // data6_l = !(rcrc & zone11); // data6_l = !(n_t_23x & rcra); // data7_l = !(rcra & n_t_20x); // e22: sn7420 assign bcd2 = ~(~zone6 & ~zone3 & ~zone7 & ~zone2); assign bcd1 = ~(~zone1 & ~zone7 & ~zone3 & ~zone5); // e23: sn7474 always @(itclk, n3v, initialize, n_t_37x) if (~n3v) begin int_m <= 1'b0; end else if (initialize) begin int_m <= 1'b1; end else if (~(itclk)) begin int_m <= n_t_37x; end always @(itclk, n3v, initialize, int_m) if (~n3v) begin int <= 1'b0; end else if (initialize) begin int <= 1'b1; end else if (itclk) begin int <= int_m; end always @(itclk, initialize, n3v, n_t_45x) if (initialize) begin trbl_m <= 1'b0; end else if (~n3v) begin trbl_m <= 1'b1; end else if (~(itclk)) begin trbl_m <= n_t_45x; end always @(itclk, initialize, n3v, trbl_m) if (initialize) begin trbl <= 1'b0; end else if (~n3v) begin trbl <= 1'b1; end else if (itclk) begin trbl <= trbl_m; end // e24: sn7400 assign n_t_28x = ~(~initialize & n_t_41x); assign n_t_41x = ~(tp3 & n_t_47x); assign n_t_47x = ~(rcrd_l & rcse_l); assign rcse = ~rcse_l; // e25: sp380n // e26: sn7410 assign n_t_32x = ~(~zone3 & ~zone1 & ~zone2); assign cerr = ~(n_t_1x & n_t_8x & n_t_19x); assign n_t_33x = ~(~zone5 & ~zone4 & ~zone1); // e27: sn7410 assign n_t_38x = ~(tp3 & rdy & rcse); assign rcr = ~(rcra_l & rcrc_l & rcrb_l); // e28: sp380n assign md06p = ~(io_pause_l | md06_l); // e29: sp380n assign n_t_37x = ~(data11_l | io_pause_l); assign n_t_45x = ~(io_pause_l | data10_l); assign md05p = ~(io_pause_l | md05_l); // e30: sn7400 assign n_t_29x = ~(rcr & tp3); assign n_t_19x = ~(n_t_32x & bcd4); assign n_t_8x = ~(n_t_10x & bcd1); assign n_t_1x = ~(bcd2 & n_t_33x); // e31: n8881n // c1_l = !rcr; // internal_io_l = !iot67; // internal_io_l = !iot63; // c1_l = !rcni; // e33: n8881n // data11_l = !(bcd1 & rcrc); // data10_l = !(rcrc & bcd2); // data10_l = !(zone8 & rcrb); // data11_l = !(rcrb & zone9); // e34: sn7420 assign n_t_10x = ~(~zone2 & ~zone4 & ~zone6 & ~zone6); assign bcd4 = ~(~zone7 & ~zone6 & ~zone4 & ~zone5); // e35: sn7402 assign n_t_5x = ~(rcni_l | ~transit); assign n_t_35x = ~(initialize | rdy1_l); // e36: sn7404 // e37: n8881n // data9_l = !(zone7 & rcrb); // data8_l = !(rcrb & zone6); // data8_l = !(zone8 & rcrc); // data9_l = !(rcrc & bcd4); // e38: sn7475 always @(strobe, i11, strobe, i11, 1'b0) if (strobe & ~i11) begin zone9_m <= 1'b0; end else if (strobe & i11) begin zone9_m <= 1'b1; end else if (~(1'b0)) begin zone9_m <= 1'b0; end always @(strobe, i11, strobe, i11, zone9_m) if (strobe & ~i11) begin zone9 <= 1'b0; end else if (strobe & i11) begin zone9 <= 1'b1; end else if (1'b0) begin zone9 <= zone9_m; end always @(strobe, i10, strobe, i10, 1'b0) if (strobe & ~i10) begin zone8_m <= 1'b0; end else if (strobe & i10) begin zone8_m <= 1'b1; end else if (~(1'b0)) begin zone8_m <= 1'b0; end always @(strobe, i10, strobe, i10, zone8_m) if (strobe & ~i10) begin zone8 <= 1'b0; end else if (strobe & i10) begin zone8 <= 1'b1; end else if (1'b0) begin zone8 <= zone8_m; end always @(strobe, i09, strobe, i09, 1'b0) if (strobe & ~i09) begin zone7_m <= 1'b0; end else if (strobe & i09) begin zone7_m <= 1'b1; end else if (~(1'b0)) begin zone7_m <= 1'b0; end always @(strobe, i09, strobe, i09, zone7_m) if (strobe & ~i09) begin zone7 <= 1'b0; end else if (strobe & i09) begin zone7 <= 1'b1; end else if (1'b0) begin zone7 <= zone7_m; end always @(strobe, i08, strobe, i08, 1'b0) if (strobe & ~i08) begin zone6_m <= 1'b0; end else if (strobe & i08) begin zone6_m <= 1'b1; end else if (~(1'b0)) begin zone6_m <= 1'b0; end always @(strobe, i08, strobe, i08, zone6_m) if (strobe & ~i08) begin zone6 <= 1'b0; end else if (strobe & i08) begin zone6 <= 1'b1; end else if (1'b0) begin zone6 <= zone6_m; end // e39: sn7440 assign read = ~read_l; assign strobe = ~n_t_6x; // e40: sp380n assign dclr = ~(~n_t_13x); assign rdy1_l = ~(n_t_25x | n_t_18x); assign rdy = ~rdy1_l; // e41: n8881n // data11_l = !(n_t_21x & rcra); // data10_l = !(rcra & bcd2); // data8_l = !(n_t_24x & rcra); // data9_l = !(rcra & bcd4); // e42: sn7400 assign rcra = ~rcra_l; assign n_t_21x = ~(~bcd1 & ~zone9); assign n_t_24x = ~(~zone9 & ~zone8); assign n_t_40x = ~(~drdy & ~cdone); // open collector 'wire-or's assign c1_l = rcr | rcni? 1'b0: 1'bz; assign data0_l = (rcni & drdy) | (zone12 & rcrb) | (rcrc & cerr)? 1'b0: 1'bz; assign data10_l = (rcrc & bcd2) | (zone8 & rcrb) | (rcra & bcd2)? 1'b0: 1'bz; assign data11_l = (bcd1 & rcrc) | (rcrb & zone9) | (n_t_21x & rcra)? 1'b0: 1'bz; assign data1_l = (cdone & rcni) | (zone11 & rcrb)? 1'b0: 1'bz; assign data2_l = (rdy2_l & n_t_5x) | (rcrb & zone10)? 1'b0: 1'bz; assign data3_l = (rdy & n_t_5x) | (rcrb & zone1)? 1'b0: 1'bz; assign data4_l = (rcrb & zone2) | (zone9 & rcrc)? 1'b0: 1'bz; assign data5_l = (zone3 & rcrb) | (rcrc & zone12)? 1'b0: 1'bz; assign data6_l = (rcrb & zone4) | (rcrc & zone11) | (n_t_23x & rcra)? 1'b0: 1'bz; assign data7_l = (zone5 & rcrb) | (zone10 & rcrc) | (rcra & n_t_20x)? 1'b0: 1'bz; assign data8_l = (rcrb & zone6) | (zone8 & rcrc) | (n_t_24x & rcra)? 1'b0: 1'bz; assign data9_l = (zone7 & rcrb) | (rcrc & bcd4) | (rcra & bcd4)? 1'b0: 1'bz; assign int_rqst_l = (transit & trbl) | (int & drdy) | (int & cdone)? 1'b0: 1'bz; assign internal_io_l = iot67 | iot63? 1'b0: 1'bz; assign skip_l = (rdy & rcse) | (~rcsi_l & ~n_t_15x) | (drdy & ~rcsf_l) | (cdone & ~rcsd_l)? 1'b0: 1'bz; endmodule