// this file is generated by topld.pl 
// please don't edit it. 
// input pins 
// output pins 
// internal nodes 
// code nodes 
// equations 
// c1: c_us 
// c2: c_us 
// c3: c_us 
// c4: c_us 
// c5: c_us 
// c6: c_us 
// c7: c_us 
// c8: c_us 
// c9: c_us 
// c10: c_us 
// c11: c_us 
// c12: c_us 
// c13: c_us 
// c14: c_us 
// c15: c_us 
// c16: c_us 
// c17: c_us 
// c18: c_us 
// c19: c_us 
// c20: c_us 
// c21: c_us 
// c22: c_us 
// c23: c_us 
// c24: c_us 
// c25: c_us 
// c26: c_us 
// c27: c_us 
// c28: c_us 
// c29: cpol_use 
// c30: cpol_use 
// c31: cpol_use 
// c32: cpol_use 
// c33: c_us 
// c36: c_us 
// c37: c_us 
// c38: c_us 
// c39: c_us 
// c40: c_us 
// e3: sn7402 
module m869d (n_t_15x, n_t_30x, n_t_31x, n_t_32x, n_t_33x, n_t_36x, n_t_37x, n_t_39x, n_t_40x, n_t_41x, n_t_42x, z_pulse, b_dixy_l, bit10, bit11, btp3, c0_l, c1_l, chan_l, clear, clear_l, col_red_l, color, color_l, data00_l, data06_l, data07_l, data08_l, data09_l, data10_l, data11_l, del_1_l, dile_l, dire_l, erase_l, grn_delay, initialize, intens, internal_io_l, interrupt_l, iot_l, ld_del_l, load_data_l, load_en_l, load_x, load_y, md10_l, md11_l, md3_l, md4_l, md5_l, md6_l, md7_l, md8_l, md9_l, n15v, n3v, n_t_14x, n_t_25x, n_t_27x, n_t_28x, n_t_29x, n_t_34x, n_t_35x, n_t_43x, n_t_45x, n_t_47x, n_t_48x, n_t_49x, n_t_6x, n_t_8x, n_t_9x, non_store_l, pause_l, red_delay, set_done, set_done_l, skip_l, tp3, write_thru_l);
input n_t_15x;
output n_t_30x;
output n_t_31x;
output n_t_32x;
output n_t_33x;
output n_t_36x;
output n_t_37x;
output n_t_39x;
output n_t_40x;
output n_t_41x;
output n_t_42x;
input z_pulse;
inout b_dixy_l;
inout bit10;
inout bit11;
inout btp3;
inout c0_l;
output c1_l;
output chan_l;
inout clear;
inout clear_l;
output col_red_l;
inout reg color;
inout color_l;
output data00_l;
inout data06_l;
inout data07_l;
input data08_l;
inout data09_l;
inout data10_l;
inout data11_l;
input del_1_l;
inout dile_l;
inout dire_l;
output erase_l;
input grn_delay;
input initialize;
output intens;
output internal_io_l;
output interrupt_l;
inout iot_l;
input ld_del_l;
inout load_data_l;
inout load_en_l;
output load_x;
output load_y;
input md10_l;
input md11_l;
input md3_l;
input md4_l;
input md5_l;
input md6_l;
input md7_l;
input md8_l;
input md9_l;
output n15v;
inout n3v;
output n_t_14x;
inout n_t_25x;
output n_t_27x;
output n_t_28x;
output n_t_29x;
output n_t_34x;
input n_t_35x;
output n_t_43x;
output n_t_45x;
output n_t_47x;
output n_t_48x;
output n_t_49x;
inout n_t_6x;
inout n_t_8x;
output n_t_9x;
output non_store_l;
input pause_l;
input red_delay;
input set_done;
input set_done_l;
output skip_l;
input tp3;
output write_thru_l;

reg chan_m;
reg color_m;
reg erase_m;
reg int_en_m;
reg n_t_1x_m;
reg store_m;
reg write_thru_m;

reg write_thru;
reg store;
reg erase;
reg chan;
reg int_en;
reg n_t_1x;
wire b_dicd_l;
wire b_load_en_l;
wire cl_done_l;
wire clear_done_l;
wire dicd_l;
wire dicl_l;
wire dilx_l;
wire dily_l;
wire disd_l;
wire dixy_l;
wire dly_done_l;
wire iot;
wire ld_en_reg;
wire n_t_10x;
wire n_t_11x;
wire n_t_12x;
wire n_t_13x;
wire n_t_17x;
wire n_t_19x;
wire n_t_20x;
wire n_t_21x;
wire n_t_22x;
wire n_t_23x;
wire n_t_24x;
wire n_t_26x;
wire n_t_2x;
wire n_t_3x;
assign dly_done_l = ~(red_delay
                       | grn_delay);
assign n_t_26x = ~(clear
                    | set_done);
assign n_t_34x = ~(grn_delay
                    | red_delay);
assign clear_done_l = ~(n_t_35x
                         | erase);
// e5: sn7474 
always @(ld_en_reg, clear_l, n3v, n_t_13x)
  if (~clear_l) begin
    write_thru_m <= 1'b0;
  end else
  if (~n3v) begin
    write_thru_m <= 1'b1;
  end else
  if (~(ld_en_reg)) begin
    write_thru_m <= n_t_13x;
  end
always @(ld_en_reg, clear_l, n3v, write_thru_m)
  if (~clear_l) begin
    write_thru <= 1'b0;
  end else
  if (~n3v) begin
    write_thru <= 1'b1;
  end else
  if (ld_en_reg) begin
    write_thru <= write_thru_m;
  end
always @(ld_en_reg, clear_l, n3v, n_t_22x)
  if (~clear_l) begin
    store_m <= 1'b0;
  end else
  if (~n3v) begin
    store_m <= 1'b1;
  end else
  if (~(ld_en_reg)) begin
    store_m <= n_t_22x;
  end
always @(ld_en_reg, clear_l, n3v, store_m)
  if (~clear_l) begin
    store <= 1'b0;
  end else
  if (~n3v) begin
    store <= 1'b1;
  end else
  if (ld_en_reg) begin
    store <= store_m;
  end
// e6: sn7474 
always @(ld_en_reg, n_t_26x, n3v, n_t_24x)
  if (~n_t_26x) begin
    erase_m <= 1'b0;
  end else
  if (~n3v) begin
    erase_m <= 1'b1;
  end else
  if (~(ld_en_reg)) begin
    erase_m <= n_t_24x;
  end
always @(ld_en_reg, n_t_26x, n3v, erase_m)
  if (~n_t_26x) begin
    erase <= 1'b0;
  end else
  if (~n3v) begin
    erase <= 1'b1;
  end else
  if (ld_en_reg) begin
    erase <= erase_m;
  end
always @(ld_en_reg, clear_l, n3v, n_t_11x)
  if (~clear_l) begin
    color_m <= 1'b0;
  end else
  if (~n3v) begin
    color_m <= 1'b1;
  end else
  if (~(ld_en_reg)) begin
    color_m <= n_t_11x;
  end
always @(ld_en_reg, clear_l, n3v, color_m)
  if (~clear_l) begin
    color <= 1'b0;
  end else
  if (~n3v) begin
    color <= 1'b1;
  end else
  if (ld_en_reg) begin
    color <= color_m;
  end
assign color_l = ~color;
// e7: n8881n 
// col_red_l = !color; 
// n_t_25x = !(!store & color_l); 
// e8: n8881n 
// data07_l = !(!dire_l & store); 
// data09_l = !(color & !dire_l); 
// data06_l = !(!dire_l & write_thru); 
// e9: sp380n 
assign n_t_24x = ~(data08_l
                    | load_data_l);
assign n_t_22x = ~(load_data_l
                    | data07_l);
assign n_t_13x = ~(data06_l
                    | load_data_l);
assign n_t_11x = ~(load_data_l
                    | data09_l);
// e10: sn7406 
// erase_l = !erase; 
// n_t_27x = !n_t_25x; 
// write_thru_l = !write_thru; 
// n_t_43x = !color_l; 
// non_store_l = store; 
// e11: sp380n 
assign n_t_14x = ~(md5_l
                    | n_t_6x);
assign n_t_17x = ~(n_t_6x
                    | md7_l);
assign n_t_12x = ~(md4_l
                    | n_t_6x);
assign n_t_10x = ~(n_t_6x
                    | md3_l);
// e12: sp314n 
assign iot = ~(n_t_15x
                | n_t_6x
                | n_t_17x
                | n_t_12x
                | n_t_10x
                | md6_l
                | md8_l);
// e13: sp380n 
assign bit10 = ~(data10_l
                  | load_data_l);
assign bit11 = ~(data11_l
                  | load_data_l);
// e14: sn7404 
assign n3v = 1'b1;
assign btp3 = tp3;
assign n_t_6x = pause_l;
assign n3v = 1'b1;
// e16: n8881n 
// data10_l = !(chan & !dire_l); 
// data11_l = !(!dire_l & int_en); 
// c0_l = c0_l; 
// c1_l = dire_l; 
// e17: n8881n 
// skip_l = !(!disd_l & n_t_1x); 
// interrupt_l = !(n_t_1x & int_en); 
// internal_io_l = !iot; 
// data00_l = !(n_t_1x & !dire_l); 
// e18: sn7474 
always @(ld_en_reg, clear_l, n3v, bit10)
  if (~clear_l) begin
    chan_m <= 1'b0;
  end else
  if (~n3v) begin
    chan_m <= 1'b1;
  end else
  if (~(ld_en_reg)) begin
    chan_m <= bit10;
  end
always @(ld_en_reg, clear_l, n3v, chan_m)
  if (~clear_l) begin
    chan <= 1'b0;
  end else
  if (~n3v) begin
    chan <= 1'b1;
  end else
  if (ld_en_reg) begin
    chan <= chan_m;
  end
always @(ld_en_reg, clear_l, n3v, bit11)
  if (~clear_l) begin
    int_en_m <= 1'b0;
  end else
  if (~n3v) begin
    int_en_m <= 1'b1;
  end else
  if (~(ld_en_reg)) begin
    int_en_m <= bit11;
  end
always @(ld_en_reg, clear_l, n3v, int_en_m)
  if (~clear_l) begin
    int_en <= 1'b0;
  end else
  if (~n3v) begin
    int_en <= 1'b1;
  end else
  if (ld_en_reg) begin
    int_en <= int_en_m;
  end
// e19: sn7474 
always @(n_t_3x, cl_done_l, n3v, n3v)
  if (~cl_done_l) begin
    n_t_1x_m <= 1'b0;
  end else
  if (~n3v) begin
    n_t_1x_m <= 1'b1;
  end else
  if (~(n_t_3x)) begin
    n_t_1x_m <= n3v;
  end
always @(n_t_3x, cl_done_l, n3v, n_t_1x_m)
  if (~cl_done_l) begin
    n_t_1x <= 1'b0;
  end else
  if (~n3v) begin
    n_t_1x <= 1'b1;
  end else
  if (n_t_3x) begin
    n_t_1x <= n_t_1x_m;
  end
// e20: sn7402 
assign ld_en_reg = ~(dile_l
                      | ~tp3);
assign load_en_l = ~(~dilx_l
                      | ~dily_l);
assign n_t_23x = ~(dicl_l
                    | ~tp3);
// e21: sn7404 
// e22: sn7400 
assign b_dicd_l = ~(btp3 & ~dicd_l);
assign b_dixy_l = ~(btp3 & ~dixy_l);
assign load_x = ~(~dilx_l & btp3);
assign load_y = ~(btp3 & ~dily_l);
// e23: sn74h21 
assign cl_done_l = clear_l & b_load_en_l & b_dixy_l & b_dicd_l;
assign n_t_3x = del_1_l & set_done_l & dly_done_l & ld_del_l;
// e24: sp380n 
assign n_t_19x = ~(md11_l
                    | iot_l);
assign n_t_20x = ~(iot_l
                    | md10_l);
assign n_t_21x = ~(md9_l
                    | iot_l);
// e25: dec8251 
assign dicl_l = ~(~iot_l & ~n_t_21x & ~n_t_20x & ~n_t_19x);
assign dicd_l = ~(~iot_l & ~n_t_21x & ~n_t_20x & n_t_19x);
assign disd_l = ~(~iot_l & ~n_t_21x & n_t_20x & ~n_t_19x);
assign dilx_l = ~(~iot_l & ~n_t_21x & n_t_20x & n_t_19x);
assign dily_l = ~(~iot_l & n_t_21x & ~n_t_20x & ~n_t_19x);
assign dixy_l = ~(~iot_l & n_t_21x & ~n_t_20x & n_t_19x);
assign dile_l = ~(~iot_l & n_t_21x & n_t_20x & ~n_t_19x);
assign dire_l = ~(~iot_l & n_t_21x & n_t_20x & n_t_19x);
// e26: sn7400 
assign n_t_2x = ~(load_en_l & clear_done_l);
assign b_load_en_l = ~(n_t_2x & btp3);
// e27: sn7400 
assign n_t_8x = ~(z_pulse & del_1_l);
// e28: sn7416 
// chan_l = !chan; 
// n_t_9x = !n_t_8x; 
// clear_l = !clear; 
// clear = clear; 
// iot_l = !iot; 
// load_data_l = load_data_l; 
// open collector 'wire-or's 
assign c0_l = ~(~(~(dile_l & dire_l)))? ~(~(dile_l & dire_l)): 1'bz;
assign c1_l = ~dire_l? 1'b0: 1'bz;
assign chan_l = chan? ~chan: 1'bz;
assign clear = ~(initialize
                | n_t_23x)? initialize
                | n_t_23x: 1'bz;
assign clear_l = clear? ~clear: 1'bz;
assign col_red_l = color? ~color: 1'bz;
assign data00_l = (n_t_1x & ~dire_l)? 1'b0: 1'bz;
assign data06_l = (~dire_l & write_thru)? 1'b0: 1'bz;
assign data07_l = (~dire_l & store)? 1'b0: 1'bz;
assign data09_l = (color & ~dire_l)? 1'b0: 1'bz;
assign data10_l = (chan & ~dire_l)? 1'b0: 1'bz;
assign data11_l = (~dire_l & int_en)? 1'b0: 1'bz;
assign erase_l = erase? ~erase: 1'bz;
assign internal_io_l = iot? ~iot: 1'bz;
assign interrupt_l = (n_t_1x & int_en)? 1'b0: 1'bz;
assign iot_l = iot? ~iot: 1'bz;
assign load_data_l = ~(~(~(dile_l & load_en_l)))? ~(~(dile_l & load_en_l)): 1'bz;
assign n_t_25x = (~store & color_l)? 1'b0: 1'bz;
assign n_t_27x = n_t_25x? ~n_t_25x: 1'bz;
assign n_t_43x = color_l? ~color_l: 1'bz;
assign n_t_9x = n_t_8x? ~n_t_8x: 1'bz;
assign non_store_l = ~store? 1'b0: 1'bz;
assign skip_l = (~disd_l & n_t_1x)? 1'b0: 1'bz;
assign write_thru_l = write_thru? ~write_thru: 1'bz;
endmodule