// this file is generated by topld.pl 
// please don't edit it. 
// input pins 
// output pins 
// internal nodes 
// code nodes 
// equations 
// c1: c_us 
// c2: c_us 
// c3: c_us 
// c4: c_us 
// c5: c_us 
// c6: c_us 
// c7: c_us 
// c8: c_us 
// e1: sn7486 
module m896n (a1, c1, e1, h1, l1, l2, m1, m2, p1, s1, t2, u2, v1, b1, d1, f1, j1, k1, n1, n2, r1, s2, u1, v2);
input a1;
input c1;
input e1;
input h1;
input l1;
input l2;
input m1;
input m2;
input p1;
input s1;
input t2;
input u2;
input v1;
inout reg b1;
inout reg d1;
inout reg f1;
inout reg j1;
inout reg k1;
inout reg n1;
inout reg n2;
inout reg r1;
output s2;
inout reg u1;
inout v2;

reg b1_m;
reg d1_m;
reg f1_m;
reg j1_m;
reg k1_m;
reg n1_m;
reg n2_m;
reg r1_m;
reg u1_m;

wire n_t_10x;
wire n_t_12x;
wire n_t_13x;
wire n_t_14x;
wire n_t_15x;
wire n_t_1x;
wire n_t_2x;
wire n_t_3x;
wire n_t_4x;
wire n_t_5x;
wire n_t_6x;
wire n_t_7x;
wire n_t_8x;
wire n_t_9x;
assign n_t_6x = b1
                 ^ a1;
// e2: sn7486 
assign n_t_14x = n_t_1x
                  ^ n_t_2x;
assign n_t_12x = n_t_1x
                  ^ n_t_3x;
assign n_t_15x = n_t_4x
                  ^ n_t_1x;
assign n_t_13x = n_t_5x
                  ^ n_t_1x;
// e3: sn7430 
assign v2 = ~(n_t_7x & n_t_4x & n_t_1x & n_t_10x & n_t_6x & ~n_t_8x & n_t_9x & n_t_2x);
// e4: sn7486 
assign n_t_3x = l1
                 ^ k1;
assign n_t_4x = h1
                 ^ j1;
assign n_t_5x = f1
                 ^ e1;
assign n_t_7x = d1
                 ^ c1;
// e6: sn7486 
assign n_t_1x = v1
                 ^ u1;
assign n_t_10x = s1
                  ^ r1;
assign n_t_9x = m1
                 ^ n2;
assign n_t_2x = n1
                 ^ p1;
// e7: sn74174 
always @(l2, m2, n_t_14x)
  if (~m2) begin
    k1_m <= 1'b0;
  end else
  if (~(~l2)) begin
    k1_m <= n_t_14x;
  end
always @(l2, m2, k1_m)
  if (~m2) begin
    k1 <= 1'b0;
  end else
  if (~l2) begin
    k1 <= k1_m;
  end
always @(l2, m2, n_t_13x)
  if (~m2) begin
    d1_m <= 1'b0;
  end else
  if (~(~l2)) begin
    d1_m <= n_t_13x;
  end
always @(l2, m2, d1_m)
  if (~m2) begin
    d1 <= 1'b0;
  end else
  if (~l2) begin
    d1 <= d1_m;
  end
always @(l2, m2, n_t_15x)
  if (~m2) begin
    f1_m <= 1'b0;
  end else
  if (~(~l2)) begin
    f1_m <= n_t_15x;
  end
always @(l2, m2, f1_m)
  if (~m2) begin
    f1 <= 1'b0;
  end else
  if (~l2) begin
    f1 <= f1_m;
  end
always @(l2, m2, n_t_6x)
  if (~m2) begin
    u1_m <= 1'b0;
  end else
  if (~(~l2)) begin
    u1_m <= n_t_6x;
  end
always @(l2, m2, u1_m)
  if (~m2) begin
    u1 <= 1'b0;
  end else
  if (~l2) begin
    u1 <= u1_m;
  end
// e8: sn74174 
always @(l2, m2, n_t_1x)
  if (~m2) begin
    r1_m <= 1'b0;
  end else
  if (~(~l2)) begin
    r1_m <= n_t_1x;
  end
always @(l2, m2, r1_m)
  if (~m2) begin
    r1 <= 1'b0;
  end else
  if (~l2) begin
    r1 <= r1_m;
  end
always @(l2, m2, n_t_10x)
  if (~m2) begin
    n2_m <= 1'b0;
  end else
  if (~(~l2)) begin
    n2_m <= n_t_10x;
  end
always @(l2, m2, n2_m)
  if (~m2) begin
    n2 <= 1'b0;
  end else
  if (~l2) begin
    n2 <= n2_m;
  end
always @(l2, m2, n_t_9x)
  if (~m2) begin
    n1_m <= 1'b0;
  end else
  if (~(~l2)) begin
    n1_m <= n_t_9x;
  end
always @(l2, m2, n1_m)
  if (~m2) begin
    n1 <= 1'b0;
  end else
  if (~l2) begin
    n1 <= n1_m;
  end
always @(l2, m2, n_t_7x)
  if (~m2) begin
    b1_m <= 1'b0;
  end else
  if (~(~l2)) begin
    b1_m <= n_t_7x;
  end
always @(l2, m2, b1_m)
  if (~m2) begin
    b1 <= 1'b0;
  end else
  if (~l2) begin
    b1 <= b1_m;
  end
always @(l2, m2, n_t_12x)
  if (~m2) begin
    j1_m <= 1'b0;
  end else
  if (~(~l2)) begin
    j1_m <= n_t_12x;
  end
always @(l2, m2, j1_m)
  if (~m2) begin
    j1 <= 1'b0;
  end else
  if (~l2) begin
    j1 <= j1_m;
  end
// ic1: sn7410 
assign n_t_8x = ~(n_t_12x & n_t_13x);
assign s2 = ~(t2 & u2 & v2);
// open collector 'wire-or's 
endmodule