// this file is generated by topld.pl 
// please don't edit it. 
// input pins 
// output pins 
// internal nodes 
// code nodes 
// equations 
// r1: r_us_ 
// r2: r_us_ 
// r3: r_us_ 
// r4: r_us_ 
// open collector 'wire-or's 
endmodule