// this file is generated by topld.pl 
// please don't edit it. 
// input pins 
// output pins 
// internal nodes 
// code nodes 
// equations 
// c1: c_us 
// c2: c_us 
// c3: c_us 
// c4: c_us 
// c5: cpol_use 
// c6: c_us 
// c7: c_us 
// r1: r_us_ 
// r2: r_us_ 
// open collector 'wire-or's 
endmodule