{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" {  } {  } 3 0 "*******************************************************************" 0 0 "Quartus II" 0 -1 1700313832024 ""}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Analysis & Synthesis Quartus II 64-Bit " "Running Quartus II 64-Bit Analysis & Synthesis" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition " "Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition" {  } {  } 0 0 "%1!s!" 0 0 "Quartus II" 0 -1 1700313832027 ""} { "Info" "IQEXE_START_BANNER_TIME" "Sat Nov 18 05:23:51 2023 " "Processing started: Sat Nov 18 05:23:51 2023" {  } {  } 0 0 "Processing started: %1!s!" 0 0 "Quartus II" 0 -1 1700313832027 ""}  } {  } 4 0 "Running %2!s! %1!s!" 0 0 "Quartus II" 0 -1 1700313832027 ""}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --read_settings_files=on --write_settings_files=off cpld -c cpld " "Command: quartus_map --read_settings_files=on --write_settings_files=off cpld -c cpld" {  } {  } 0 0 "Command: %1!s!" 0 0 "Quartus II" 0 -1 1700313832027 ""}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "m837cc.v 1 1 " "Found 1 design units, including 1 entities, in source file m837cc.v" { { "Info" "ISGN_ENTITY_NAME" "1 m837cc " "Found entity 1: m837cc" {  } { { "M837cc.v" "" { Text "//wsl.localhost/Debian/home/vrs/Verilog/projects/32k-Omnibus/M837cc.v" 76 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1700313832784 ""}  } {  } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1700313832784 ""}
{ "Warning" "WVRFX_L3_VERI_CONST_EVENT_EXPR" "M8650D.v(346) " "Verilog HDL Event Control warning at M8650D.v(346): event expression is a constant" {  } { { "M8650D.v" "" { Text "//wsl.localhost/Debian/home/vrs/Verilog/projects/32k-Omnibus/M8650D.v" 346 0 0 } }  } 0 10262 "Verilog HDL Event Control warning at %1!s!: event expression is a constant" 1 0 "Quartus II" 0 -1 1700313832914 ""}
{ "Warning" "WVRFX_L3_VERI_CONST_EVENT_EXPR" "M8650D.v(490) " "Verilog HDL Event Control warning at M8650D.v(490): event expression is a constant" {  } { { "M8650D.v" "" { Text "//wsl.localhost/Debian/home/vrs/Verilog/projects/32k-Omnibus/M8650D.v" 490 0 0 } }  } 0 10262 "Verilog HDL Event Control warning at %1!s!: event expression is a constant" 1 0 "Quartus II" 0 -1 1700313832919 ""}
{ "Warning" "WVRFX_L3_VERI_CONST_EVENT_EXPR" "M8650D.v(510) " "Verilog HDL Event Control warning at M8650D.v(510): event expression is a constant" {  } { { "M8650D.v" "" { Text "//wsl.localhost/Debian/home/vrs/Verilog/projects/32k-Omnibus/M8650D.v" 510 0 0 } }  } 0 10262 "Verilog HDL Event Control warning at %1!s!: event expression is a constant" 1 0 "Quartus II" 0 -1 1700313832919 ""}
{ "Warning" "WVRFX_L3_VERI_CONST_EVENT_EXPR" "M8650D.v(702) " "Verilog HDL Event Control warning at M8650D.v(702): event expression is a constant" {  } { { "M8650D.v" "" { Text "//wsl.localhost/Debian/home/vrs/Verilog/projects/32k-Omnibus/M8650D.v" 702 0 0 } }  } 0 10262 "Verilog HDL Event Control warning at %1!s!: event expression is a constant" 1 0 "Quartus II" 0 -1 1700313832919 ""}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "m8650d.v 1 1 " "Found 1 design units, including 1 entities, in source file m8650d.v" { { "Info" "ISGN_ENTITY_NAME" "1 m8650d " "Found entity 1: m8650d" {  } { { "M8650D.v" "" { Text "//wsl.localhost/Debian/home/vrs/Verilog/projects/32k-Omnibus/M8650D.v" 76 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1700313832935 ""}  } {  } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1700313832935 ""}
{ "Warning" "WVRFX_L2_VERI_INGORE_DANGLING_COMMA" "cpld.v(321) " "Verilog HDL Module Instantiation warning at cpld.v(321): ignored dangling comma in List of Port Connections" {  } { { "cpld.v" "" { Text "//wsl.localhost/Debian/home/vrs/Verilog/projects/32k-Omnibus/cpld.v" 321 0 0 } }  } 0 10275 "Verilog HDL Module Instantiation warning at %1!s!: ignored dangling comma in List of Port Connections" 0 0 "Quartus II" 0 -1 1700313833030 ""}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "cpld.v 1 1 " "Found 1 design units, including 1 entities, in source file cpld.v" { { "Info" "ISGN_ENTITY_NAME" "1 cpld " "Found entity 1: cpld" {  } { { "cpld.v" "" { Text "//wsl.localhost/Debian/home/vrs/Verilog/projects/32k-Omnibus/cpld.v" 16 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1700313833045 ""}  } {  } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1700313833045 ""}
{ "Warning" "WVRFX_L2_VERI_CREATED_IMPLICIT_NET" "n_t_60x_d M8650D.v(959) " "Verilog HDL Implicit Net warning at M8650D.v(959): created implicit net for \"n_t_60x_d\"" {  } { { "M8650D.v" "" { Text "//wsl.localhost/Debian/home/vrs/Verilog/projects/32k-Omnibus/M8650D.v" 959 0 0 } }  } 0 10236 "Verilog HDL Implicit Net warning at %2!s!: created implicit net for \"%1!s!\"" 0 0 "Quartus II" 0 -1 1700313833045 ""}
{ "Info" "ISGN_START_ELABORATION_TOP" "cpld " "Elaborating entity \"cpld\" for the top level hierarchy" {  } {  } 0 12127 "Elaborating entity \"%1!s!\" for the top level hierarchy" 0 0 "Quartus II" 0 -1 1700313833144 ""}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "m8650d m8650d:m8650d " "Elaborating entity \"m8650d\" for hierarchy \"m8650d:m8650d\"" {  } { { "cpld.v" "m8650d" { Text "//wsl.localhost/Debian/home/vrs/Verilog/projects/32k-Omnibus/cpld.v" 321 0 0 } }  } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1700313833236 ""}
{ "Warning" "WVRFX_L2_VERI_ALWAYS_ID_HOLDS_VALUE" "rx_div_m M8650D.v(326) " "Verilog HDL Always Construct warning at M8650D.v(326): inferring latch(es) for variable \"rx_div_m\", which holds its previous value in one or more paths through the always construct" {  } { { "M8650D.v" "" { Text "//wsl.localhost/Debian/home/vrs/Verilog/projects/32k-Omnibus/M8650D.v" 326 0 0 } }  } 0 10240 "Verilog HDL Always Construct warning at %2!s!: inferring latch(es) for variable \"%1!s!\", which holds its previous value in one or more paths through the always construct" 0 0 "Quartus II" 0 -1 1700313833252 "|cpld|m8650d:m8650d"}
{ "Warning" "WVRFX_L2_VERI_ALWAYS_ID_HOLDS_VALUE" "rx_div M8650D.v(336) " "Verilog HDL Always Construct warning at M8650D.v(336): inferring latch(es) for variable \"rx_div\", which holds its previous value in one or more paths through the always construct" {  } { { "M8650D.v" "" { Text "//wsl.localhost/Debian/home/vrs/Verilog/projects/32k-Omnibus/M8650D.v" 336 0 0 } }  } 0 10240 "Verilog HDL Always Construct warning at %2!s!: inferring latch(es) for variable \"%1!s!\", which holds its previous value in one or more paths through the always construct" 0 0 "Quartus II" 0 -1 1700313833252 "|cpld|m8650d:m8650d"}
{ "Warning" "WVRFX_L2_VERI_ALWAYS_ID_HOLDS_VALUE" "ck_pulse_m M8650D.v(346) " "Verilog HDL Always Construct warning at M8650D.v(346): inferring latch(es) for variable \"ck_pulse_m\", which holds its previous value in one or more paths through the always construct" {  } { { "M8650D.v" "" { Text "//wsl.localhost/Debian/home/vrs/Verilog/projects/32k-Omnibus/M8650D.v" 346 0 0 } }  } 0 10240 "Verilog HDL Always Construct warning at %2!s!: inferring latch(es) for variable \"%1!s!\", which holds its previous value in one or more paths through the always construct" 0 0 "Quartus II" 0 -1 1700313833254 "|cpld|m8650d:m8650d"}
{ "Warning" "WVRFX_L2_VERI_ALWAYS_ID_HOLDS_VALUE" "ck_pulse M8650D.v(356) " "Verilog HDL Always Construct warning at M8650D.v(356): inferring latch(es) for variable \"ck_pulse\", which holds its previous value in one or more paths through the always construct" {  } { { "M8650D.v" "" { Text "//wsl.localhost/Debian/home/vrs/Verilog/projects/32k-Omnibus/M8650D.v" 356 0 0 } }  } 0 10240 "Verilog HDL Always Construct warning at %2!s!: inferring latch(es) for variable \"%1!s!\", which holds its previous value in one or more paths through the always construct" 0 0 "Quartus II" 0 -1 1700313833254 "|cpld|m8650d:m8650d"}
{ "Warning" "WVRFX_L2_VERI_ALWAYS_ID_HOLDS_VALUE" "n_t_43x_m M8650D.v(367) " "Verilog HDL Always Construct warning at M8650D.v(367): inferring latch(es) for variable \"n_t_43x_m\", which holds its previous value in one or more paths through the always construct" {  } { { "M8650D.v" "" { Text "//wsl.localhost/Debian/home/vrs/Verilog/projects/32k-Omnibus/M8650D.v" 367 0 0 } }  } 0 10240 "Verilog HDL Always Construct warning at %2!s!: inferring latch(es) for variable \"%1!s!\", which holds its previous value in one or more paths through the always construct" 0 0 "Quartus II" 0 -1 1700313833254 "|cpld|m8650d:m8650d"}
{ "Warning" "WVRFX_L2_VERI_ALWAYS_ID_HOLDS_VALUE" "n_t_43x M8650D.v(377) " "Verilog HDL Always Construct warning at M8650D.v(377): inferring latch(es) for variable \"n_t_43x\", which holds its previous value in one or more paths through the always construct" {  } { { "M8650D.v" "" { Text "//wsl.localhost/Debian/home/vrs/Verilog/projects/32k-Omnibus/M8650D.v" 377 0 0 } }  } 0 10240 "Verilog HDL Always Construct warning at %2!s!: inferring latch(es) for variable \"%1!s!\", which holds its previous value in one or more paths through the always construct" 0 0 "Quartus II" 0 -1 1700313833254 "|cpld|m8650d:m8650d"}
{ "Warning" "WVRFX_L2_VERI_ALWAYS_ID_HOLDS_VALUE" "n_t_75x_m M8650D.v(387) " "Verilog HDL Always Construct warning at M8650D.v(387): inferring latch(es) for variable \"n_t_75x_m\", which holds its previous value in one or more paths through the always construct" {  } { { "M8650D.v" "" { Text "//wsl.localhost/Debian/home/vrs/Verilog/projects/32k-Omnibus/M8650D.v" 387 0 0 } }  } 0 10240 "Verilog HDL Always Construct warning at %2!s!: inferring latch(es) for variable \"%1!s!\", which holds its previous value in one or more paths through the always construct" 0 0 "Quartus II" 0 -1 1700313833254 "|cpld|m8650d:m8650d"}
{ "Warning" "WVRFX_L2_VERI_ALWAYS_ID_HOLDS_VALUE" "n_t_75x M8650D.v(397) " "Verilog HDL Always Construct warning at M8650D.v(397): inferring latch(es) for variable \"n_t_75x\", which holds its previous value in one or more paths through the always construct" {  } { { "M8650D.v" "" { Text "//wsl.localhost/Debian/home/vrs/Verilog/projects/32k-Omnibus/M8650D.v" 397 0 0 } }  } 0 10240 "Verilog HDL Always Construct warning at %2!s!: inferring latch(es) for variable \"%1!s!\", which holds its previous value in one or more paths through the always construct" 0 0 "Quartus II" 0 -1 1700313833254 "|cpld|m8650d:m8650d"}
{ "Warning" "WVRFX_L2_VERI_ALWAYS_ID_HOLDS_VALUE" "n_t_30x_m M8650D.v(425) " "Verilog HDL Always Construct warning at M8650D.v(425): inferring latch(es) for variable \"n_t_30x_m\", which holds its previous value in one or more paths through the always construct" {  } { { "M8650D.v" "" { Text "//wsl.localhost/Debian/home/vrs/Verilog/projects/32k-Omnibus/M8650D.v" 425 0 0 } }  } 0 10240 "Verilog HDL Always Construct warning at %2!s!: inferring latch(es) for variable \"%1!s!\", which holds its previous value in one or more paths through the always construct" 0 0 "Quartus II" 0 -1 1700313833254 "|cpld|m8650d:m8650d"}
{ "Warning" "WVRFX_L2_VERI_ALWAYS_ID_HOLDS_VALUE" "n_t_30x M8650D.v(434) " "Verilog HDL Always Construct warning at M8650D.v(434): inferring latch(es) for variable \"n_t_30x\", which holds its previous value in one or more paths through the always construct" {  } { { "M8650D.v" "" { Text "//wsl.localhost/Debian/home/vrs/Verilog/projects/32k-Omnibus/M8650D.v" 434 0 0 } }  } 0 10240 "Verilog HDL Always Construct warning at %2!s!: inferring latch(es) for variable \"%1!s!\", which holds its previous value in one or more paths through the always construct" 0 0 "Quartus II" 0 -1 1700313833254 "|cpld|m8650d:m8650d"}
{ "Warning" "WVRFX_L2_VERI_ALWAYS_ID_HOLDS_VALUE" "n_t_34x_m M8650D.v(441) " "Verilog HDL Always Construct warning at M8650D.v(441): inferring latch(es) for variable \"n_t_34x_m\", which holds its previous value in one or more paths through the always construct" {  } { { "M8650D.v" "" { Text "//wsl.localhost/Debian/home/vrs/Verilog/projects/32k-Omnibus/M8650D.v" 441 0 0 } }  } 0 10240 "Verilog HDL Always Construct warning at %2!s!: inferring latch(es) for variable \"%1!s!\", which holds its previous value in one or more paths through the always construct" 0 0 "Quartus II" 0 -1 1700313833254 "|cpld|m8650d:m8650d"}
{ "Warning" "WVRFX_L2_VERI_ALWAYS_ID_HOLDS_VALUE" "n_t_34x M8650D.v(450) " "Verilog HDL Always Construct warning at M8650D.v(450): inferring latch(es) for variable \"n_t_34x\", which holds its previous value in one or more paths through the always construct" {  } { { "M8650D.v" "" { Text "//wsl.localhost/Debian/home/vrs/Verilog/projects/32k-Omnibus/M8650D.v" 450 0 0 } }  } 0 10240 "Verilog HDL Always Construct warning at %2!s!: inferring latch(es) for variable \"%1!s!\", which holds its previous value in one or more paths through the always construct" 0 0 "Quartus II" 0 -1 1700313833254 "|cpld|m8650d:m8650d"}
{ "Warning" "WVRFX_L2_VERI_ALWAYS_ID_HOLDS_VALUE" "n_t_36x_m M8650D.v(457) " "Verilog HDL Always Construct warning at M8650D.v(457): inferring latch(es) for variable \"n_t_36x_m\", which holds its previous value in one or more paths through the always construct" {  } { { "M8650D.v" "" { Text "//wsl.localhost/Debian/home/vrs/Verilog/projects/32k-Omnibus/M8650D.v" 457 0 0 } }  } 0 10240 "Verilog HDL Always Construct warning at %2!s!: inferring latch(es) for variable \"%1!s!\", which holds its previous value in one or more paths through the always construct" 0 0 "Quartus II" 0 -1 1700313833254 "|cpld|m8650d:m8650d"}
{ "Warning" "WVRFX_L2_VERI_ALWAYS_ID_HOLDS_VALUE" "n_t_36x M8650D.v(466) " "Verilog HDL Always Construct warning at M8650D.v(466): inferring latch(es) for variable \"n_t_36x\", which holds its previous value in one or more paths through the always construct" {  } { { "M8650D.v" "" { Text "//wsl.localhost/Debian/home/vrs/Verilog/projects/32k-Omnibus/M8650D.v" 466 0 0 } }  } 0 10240 "Verilog HDL Always Construct warning at %2!s!: inferring latch(es) for variable \"%1!s!\", which holds its previous value in one or more paths through the always construct" 0 0 "Quartus II" 0 -1 1700313833254 "|cpld|m8650d:m8650d"}
{ "Warning" "WVRFX_L2_VERI_ALWAYS_ID_HOLDS_VALUE" "n_t_35x_m M8650D.v(473) " "Verilog HDL Always Construct warning at M8650D.v(473): inferring latch(es) for variable \"n_t_35x_m\", which holds its previous value in one or more paths through the always construct" {  } { { "M8650D.v" "" { Text "//wsl.localhost/Debian/home/vrs/Verilog/projects/32k-Omnibus/M8650D.v" 473 0 0 } }  } 0 10240 "Verilog HDL Always Construct warning at %2!s!: inferring latch(es) for variable \"%1!s!\", which holds its previous value in one or more paths through the always construct" 0 0 "Quartus II" 0 -1 1700313833254 "|cpld|m8650d:m8650d"}
{ "Warning" "WVRFX_L2_VERI_ALWAYS_ID_HOLDS_VALUE" "n_t_35x M8650D.v(482) " "Verilog HDL Always Construct warning at M8650D.v(482): inferring latch(es) for variable \"n_t_35x\", which holds its previous value in one or more paths through the always construct" {  } { { "M8650D.v" "" { Text "//wsl.localhost/Debian/home/vrs/Verilog/projects/32k-Omnibus/M8650D.v" 482 0 0 } }  } 0 10240 "Verilog HDL Always Construct warning at %2!s!: inferring latch(es) for variable \"%1!s!\", which holds its previous value in one or more paths through the always construct" 0 0 "Quartus II" 0 -1 1700313833254 "|cpld|m8650d:m8650d"}
{ "Warning" "WVRFX_L2_VERI_ALWAYS_ID_HOLDS_VALUE" "rx_active_m M8650D.v(490) " "Verilog HDL Always Construct warning at M8650D.v(490): inferring latch(es) for variable \"rx_active_m\", which holds its previous value in one or more paths through the always construct" {  } { { "M8650D.v" "" { Text "//wsl.localhost/Debian/home/vrs/Verilog/projects/32k-Omnibus/M8650D.v" 490 0 0 } }  } 0 10240 "Verilog HDL Always Construct warning at %2!s!: inferring latch(es) for variable \"%1!s!\", which holds its previous value in one or more paths through the always construct" 0 0 "Quartus II" 0 -1 1700313833254 "|cpld|m8650d:m8650d"}
{ "Warning" "WVRFX_L2_VERI_ALWAYS_ID_HOLDS_VALUE" "rx_active M8650D.v(500) " "Verilog HDL Always Construct warning at M8650D.v(500): inferring latch(es) for variable \"rx_active\", which holds its previous value in one or more paths through the always construct" {  } { { "M8650D.v" "" { Text "//wsl.localhost/Debian/home/vrs/Verilog/projects/32k-Omnibus/M8650D.v" 500 0 0 } }  } 0 10240 "Verilog HDL Always Construct warning at %2!s!: inferring latch(es) for variable \"%1!s!\", which holds its previous value in one or more paths through the always construct" 0 0 "Quartus II" 0 -1 1700313833254 "|cpld|m8650d:m8650d"}
{ "Warning" "WVRFX_L2_VERI_ALWAYS_ID_HOLDS_VALUE" "p_pulse_l_m M8650D.v(510) " "Verilog HDL Always Construct warning at M8650D.v(510): inferring latch(es) for variable \"p_pulse_l_m\", which holds its previous value in one or more paths through the always construct" {  } { { "M8650D.v" "" { Text "//wsl.localhost/Debian/home/vrs/Verilog/projects/32k-Omnibus/M8650D.v" 510 0 0 } }  } 0 10240 "Verilog HDL Always Construct warning at %2!s!: inferring latch(es) for variable \"%1!s!\", which holds its previous value in one or more paths through the always construct" 0 0 "Quartus II" 0 -1 1700313833254 "|cpld|m8650d:m8650d"}
{ "Warning" "WVRFX_L2_VERI_ALWAYS_ID_HOLDS_VALUE" "p_pulse_l M8650D.v(520) " "Verilog HDL Always Construct warning at M8650D.v(520): inferring latch(es) for variable \"p_pulse_l\", which holds its previous value in one or more paths through the always construct" {  } { { "M8650D.v" "" { Text "//wsl.localhost/Debian/home/vrs/Verilog/projects/32k-Omnibus/M8650D.v" 520 0 0 } }  } 0 10240 "Verilog HDL Always Construct warning at %2!s!: inferring latch(es) for variable \"%1!s!\", which holds its previous value in one or more paths through the always construct" 0 0 "Quartus II" 0 -1 1700313833254 "|cpld|m8650d:m8650d"}
{ "Warning" "WVRFX_L2_VERI_ALWAYS_ID_HOLDS_VALUE" "last_unit_m M8650D.v(531) " "Verilog HDL Always Construct warning at M8650D.v(531): inferring latch(es) for variable \"last_unit_m\", which holds its previous value in one or more paths through the always construct" {  } { { "M8650D.v" "" { Text "//wsl.localhost/Debian/home/vrs/Verilog/projects/32k-Omnibus/M8650D.v" 531 0 0 } }  } 0 10240 "Verilog HDL Always Construct warning at %2!s!: inferring latch(es) for variable \"%1!s!\", which holds its previous value in one or more paths through the always construct" 0 0 "Quartus II" 0 -1 1700313833254 "|cpld|m8650d:m8650d"}
{ "Warning" "WVRFX_L2_VERI_ALWAYS_ID_HOLDS_VALUE" "last_unit M8650D.v(541) " "Verilog HDL Always Construct warning at M8650D.v(541): inferring latch(es) for variable \"last_unit\", which holds its previous value in one or more paths through the always construct" {  } { { "M8650D.v" "" { Text "//wsl.localhost/Debian/home/vrs/Verilog/projects/32k-Omnibus/M8650D.v" 541 0 0 } }  } 0 10240 "Verilog HDL Always Construct warning at %2!s!: inferring latch(es) for variable \"%1!s!\", which holds its previous value in one or more paths through the always construct" 0 0 "Quartus II" 0 -1 1700313833254 "|cpld|m8650d:m8650d"}
{ "Warning" "WVRFX_L2_VERI_ALWAYS_ID_HOLDS_VALUE" "n_t_88x_m M8650D.v(551) " "Verilog HDL Always Construct warning at M8650D.v(551): inferring latch(es) for variable \"n_t_88x_m\", which holds its previous value in one or more paths through the always construct" {  } { { "M8650D.v" "" { Text "//wsl.localhost/Debian/home/vrs/Verilog/projects/32k-Omnibus/M8650D.v" 551 0 0 } }  } 0 10240 "Verilog HDL Always Construct warning at %2!s!: inferring latch(es) for variable \"%1!s!\", which holds its previous value in one or more paths through the always construct" 0 0 "Quartus II" 0 -1 1700313833254 "|cpld|m8650d:m8650d"}
{ "Warning" "WVRFX_L2_VERI_ALWAYS_ID_HOLDS_VALUE" "n_t_88x M8650D.v(561) " "Verilog HDL Always Construct warning at M8650D.v(561): inferring latch(es) for variable \"n_t_88x\", which holds its previous value in one or more paths through the always construct" {  } { { "M8650D.v" "" { Text "//wsl.localhost/Debian/home/vrs/Verilog/projects/32k-Omnibus/M8650D.v" 561 0 0 } }  } 0 10240 "Verilog HDL Always Construct warning at %2!s!: inferring latch(es) for variable \"%1!s!\", which holds its previous value in one or more paths through the always construct" 0 0 "Quartus II" 0 -1 1700313833254 "|cpld|m8650d:m8650d"}
{ "Warning" "WVRFX_L2_VERI_ALWAYS_ID_HOLDS_VALUE" "n_t_37x_m M8650D.v(580) " "Verilog HDL Always Construct warning at M8650D.v(580): inferring latch(es) for variable \"n_t_37x_m\", which holds its previous value in one or more paths through the always construct" {  } { { "M8650D.v" "" { Text "//wsl.localhost/Debian/home/vrs/Verilog/projects/32k-Omnibus/M8650D.v" 580 0 0 } }  } 0 10240 "Verilog HDL Always Construct warning at %2!s!: inferring latch(es) for variable \"%1!s!\", which holds its previous value in one or more paths through the always construct" 0 0 "Quartus II" 0 -1 1700313833254 "|cpld|m8650d:m8650d"}
{ "Warning" "WVRFX_L2_VERI_ALWAYS_ID_HOLDS_VALUE" "n_t_37x M8650D.v(589) " "Verilog HDL Always Construct warning at M8650D.v(589): inferring latch(es) for variable \"n_t_37x\", which holds its previous value in one or more paths through the always construct" {  } { { "M8650D.v" "" { Text "//wsl.localhost/Debian/home/vrs/Verilog/projects/32k-Omnibus/M8650D.v" 589 0 0 } }  } 0 10240 "Verilog HDL Always Construct warning at %2!s!: inferring latch(es) for variable \"%1!s!\", which holds its previous value in one or more paths through the always construct" 0 0 "Quartus II" 0 -1 1700313833259 "|cpld|m8650d:m8650d"}
{ "Warning" "WVRFX_L2_VERI_ALWAYS_ID_HOLDS_VALUE" "n_t_38x_m M8650D.v(596) " "Verilog HDL Always Construct warning at M8650D.v(596): inferring latch(es) for variable \"n_t_38x_m\", which holds its previous value in one or more paths through the always construct" {  } { { "M8650D.v" "" { Text "//wsl.localhost/Debian/home/vrs/Verilog/projects/32k-Omnibus/M8650D.v" 596 0 0 } }  } 0 10240 "Verilog HDL Always Construct warning at %2!s!: inferring latch(es) for variable \"%1!s!\", which holds its previous value in one or more paths through the always construct" 0 0 "Quartus II" 0 -1 1700313833259 "|cpld|m8650d:m8650d"}
{ "Warning" "WVRFX_L2_VERI_ALWAYS_ID_HOLDS_VALUE" "n_t_38x M8650D.v(605) " "Verilog HDL Always Construct warning at M8650D.v(605): inferring latch(es) for variable \"n_t_38x\", which holds its previous value in one or more paths through the always construct" {  } { { "M8650D.v" "" { Text "//wsl.localhost/Debian/home/vrs/Verilog/projects/32k-Omnibus/M8650D.v" 605 0 0 } }  } 0 10240 "Verilog HDL Always Construct warning at %2!s!: inferring latch(es) for variable \"%1!s!\", which holds its previous value in one or more paths through the always construct" 0 0 "Quartus II" 0 -1 1700313833259 "|cpld|m8650d:m8650d"}
{ "Warning" "WVRFX_L2_VERI_ALWAYS_ID_HOLDS_VALUE" "n_t_39x_m M8650D.v(612) " "Verilog HDL Always Construct warning at M8650D.v(612): inferring latch(es) for variable \"n_t_39x_m\", which holds its previous value in one or more paths through the always construct" {  } { { "M8650D.v" "" { Text "//wsl.localhost/Debian/home/vrs/Verilog/projects/32k-Omnibus/M8650D.v" 612 0 0 } }  } 0 10240 "Verilog HDL Always Construct warning at %2!s!: inferring latch(es) for variable \"%1!s!\", which holds its previous value in one or more paths through the always construct" 0 0 "Quartus II" 0 -1 1700313833259 "|cpld|m8650d:m8650d"}
{ "Warning" "WVRFX_L2_VERI_ALWAYS_ID_HOLDS_VALUE" "n_t_39x M8650D.v(621) " "Verilog HDL Always Construct warning at M8650D.v(621): inferring latch(es) for variable \"n_t_39x\", which holds its previous value in one or more paths through the always construct" {  } { { "M8650D.v" "" { Text "//wsl.localhost/Debian/home/vrs/Verilog/projects/32k-Omnibus/M8650D.v" 621 0 0 } }  } 0 10240 "Verilog HDL Always Construct warning at %2!s!: inferring latch(es) for variable \"%1!s!\", which holds its previous value in one or more paths through the always construct" 0 0 "Quartus II" 0 -1 1700313833259 "|cpld|m8650d:m8650d"}
{ "Warning" "WVRFX_L2_VERI_ALWAYS_ID_HOLDS_VALUE" "n_t_40x_m M8650D.v(628) " "Verilog HDL Always Construct warning at M8650D.v(628): inferring latch(es) for variable \"n_t_40x_m\", which holds its previous value in one or more paths through the always construct" {  } { { "M8650D.v" "" { Text "//wsl.localhost/Debian/home/vrs/Verilog/projects/32k-Omnibus/M8650D.v" 628 0 0 } }  } 0 10240 "Verilog HDL Always Construct warning at %2!s!: inferring latch(es) for variable \"%1!s!\", which holds its previous value in one or more paths through the always construct" 0 0 "Quartus II" 0 -1 1700313833259 "|cpld|m8650d:m8650d"}
{ "Warning" "WVRFX_L2_VERI_ALWAYS_ID_HOLDS_VALUE" "n_t_40x M8650D.v(637) " "Verilog HDL Always Construct warning at M8650D.v(637): inferring latch(es) for variable \"n_t_40x\", which holds its previous value in one or more paths through the always construct" {  } { { "M8650D.v" "" { Text "//wsl.localhost/Debian/home/vrs/Verilog/projects/32k-Omnibus/M8650D.v" 637 0 0 } }  } 0 10240 "Verilog HDL Always Construct warning at %2!s!: inferring latch(es) for variable \"%1!s!\", which holds its previous value in one or more paths through the always construct" 0 0 "Quartus II" 0 -1 1700313833260 "|cpld|m8650d:m8650d"}
{ "Warning" "WVRFX_L2_VERI_ALWAYS_ID_HOLDS_VALUE" "tx_div_m M8650D.v(681) " "Verilog HDL Always Construct warning at M8650D.v(681): inferring latch(es) for variable \"tx_div_m\", which holds its previous value in one or more paths through the always construct" {  } { { "M8650D.v" "" { Text "//wsl.localhost/Debian/home/vrs/Verilog/projects/32k-Omnibus/M8650D.v" 681 0 0 } }  } 0 10240 "Verilog HDL Always Construct warning at %2!s!: inferring latch(es) for variable \"%1!s!\", which holds its previous value in one or more paths through the always construct" 0 0 "Quartus II" 0 -1 1700313833260 "|cpld|m8650d:m8650d"}
{ "Warning" "WVRFX_L2_VERI_ALWAYS_ID_HOLDS_VALUE" "tx_div M8650D.v(691) " "Verilog HDL Always Construct warning at M8650D.v(691): inferring latch(es) for variable \"tx_div\", which holds its previous value in one or more paths through the always construct" {  } { { "M8650D.v" "" { Text "//wsl.localhost/Debian/home/vrs/Verilog/projects/32k-Omnibus/M8650D.v" 691 0 0 } }  } 0 10240 "Verilog HDL Always Construct warning at %2!s!: inferring latch(es) for variable \"%1!s!\", which holds its previous value in one or more paths through the always construct" 0 0 "Quartus II" 0 -1 1700313833260 "|cpld|m8650d:m8650d"}
{ "Warning" "WVRFX_L2_VERI_ALWAYS_ID_HOLDS_VALUE" "spike_det_l_m M8650D.v(702) " "Verilog HDL Always Construct warning at M8650D.v(702): inferring latch(es) for variable \"spike_det_l_m\", which holds its previous value in one or more paths through the always construct" {  } { { "M8650D.v" "" { Text "//wsl.localhost/Debian/home/vrs/Verilog/projects/32k-Omnibus/M8650D.v" 702 0 0 } }  } 0 10240 "Verilog HDL Always Construct warning at %2!s!: inferring latch(es) for variable \"%1!s!\", which holds its previous value in one or more paths through the always construct" 0 0 "Quartus II" 0 -1 1700313833260 "|cpld|m8650d:m8650d"}
{ "Warning" "WVRFX_L2_VERI_ALWAYS_ID_HOLDS_VALUE" "spike_det_l M8650D.v(712) " "Verilog HDL Always Construct warning at M8650D.v(712): inferring latch(es) for variable \"spike_det_l\", which holds its previous value in one or more paths through the always construct" {  } { { "M8650D.v" "" { Text "//wsl.localhost/Debian/home/vrs/Verilog/projects/32k-Omnibus/M8650D.v" 712 0 0 } }  } 0 10240 "Verilog HDL Always Construct warning at %2!s!: inferring latch(es) for variable \"%1!s!\", which holds its previous value in one or more paths through the always construct" 0 0 "Quartus II" 0 -1 1700313833260 "|cpld|m8650d:m8650d"}
{ "Warning" "WVRFX_L2_VERI_ALWAYS_ID_HOLDS_VALUE" "tx_active_l_m M8650D.v(744) " "Verilog HDL Always Construct warning at M8650D.v(744): inferring latch(es) for variable \"tx_active_l_m\", which holds its previous value in one or more paths through the always construct" {  } { { "M8650D.v" "" { Text "//wsl.localhost/Debian/home/vrs/Verilog/projects/32k-Omnibus/M8650D.v" 744 0 0 } }  } 0 10240 "Verilog HDL Always Construct warning at %2!s!: inferring latch(es) for variable \"%1!s!\", which holds its previous value in one or more paths through the always construct" 0 0 "Quartus II" 0 -1 1700313833260 "|cpld|m8650d:m8650d"}
{ "Warning" "WVRFX_L2_VERI_ALWAYS_ID_HOLDS_VALUE" "tx_active_l M8650D.v(754) " "Verilog HDL Always Construct warning at M8650D.v(754): inferring latch(es) for variable \"tx_active_l\", which holds its previous value in one or more paths through the always construct" {  } { { "M8650D.v" "" { Text "//wsl.localhost/Debian/home/vrs/Verilog/projects/32k-Omnibus/M8650D.v" 754 0 0 } }  } 0 10240 "Verilog HDL Always Construct warning at %2!s!: inferring latch(es) for variable \"%1!s!\", which holds its previous value in one or more paths through the always construct" 0 0 "Quartus II" 0 -1 1700313833260 "|cpld|m8650d:m8650d"}
{ "Warning" "WVRFX_L2_VERI_ALWAYS_ID_HOLDS_VALUE" "start_l_m M8650D.v(765) " "Verilog HDL Always Construct warning at M8650D.v(765): inferring latch(es) for variable \"start_l_m\", which holds its previous value in one or more paths through the always construct" {  } { { "M8650D.v" "" { Text "//wsl.localhost/Debian/home/vrs/Verilog/projects/32k-Omnibus/M8650D.v" 765 0 0 } }  } 0 10240 "Verilog HDL Always Construct warning at %2!s!: inferring latch(es) for variable \"%1!s!\", which holds its previous value in one or more paths through the always construct" 0 0 "Quartus II" 0 -1 1700313833260 "|cpld|m8650d:m8650d"}
{ "Warning" "WVRFX_L2_VERI_ALWAYS_ID_HOLDS_VALUE" "start_l M8650D.v(775) " "Verilog HDL Always Construct warning at M8650D.v(775): inferring latch(es) for variable \"start_l\", which holds its previous value in one or more paths through the always construct" {  } { { "M8650D.v" "" { Text "//wsl.localhost/Debian/home/vrs/Verilog/projects/32k-Omnibus/M8650D.v" 775 0 0 } }  } 0 10240 "Verilog HDL Always Construct warning at %2!s!: inferring latch(es) for variable \"%1!s!\", which holds its previous value in one or more paths through the always construct" 0 0 "Quartus II" 0 -1 1700313833260 "|cpld|m8650d:m8650d"}
{ "Warning" "WVRFX_L2_VERI_ALWAYS_ID_HOLDS_VALUE" "gdollar_4_m M8650D.v(788) " "Verilog HDL Always Construct warning at M8650D.v(788): inferring latch(es) for variable \"gdollar_4_m\", which holds its previous value in one or more paths through the always construct" {  } { { "M8650D.v" "" { Text "//wsl.localhost/Debian/home/vrs/Verilog/projects/32k-Omnibus/M8650D.v" 788 0 0 } }  } 0 10240 "Verilog HDL Always Construct warning at %2!s!: inferring latch(es) for variable \"%1!s!\", which holds its previous value in one or more paths through the always construct" 0 0 "Quartus II" 0 -1 1700313833260 "|cpld|m8650d:m8650d"}
{ "Warning" "WVRFX_L2_VERI_ALWAYS_ID_HOLDS_VALUE" "gdollar_4 M8650D.v(796) " "Verilog HDL Always Construct warning at M8650D.v(796): inferring latch(es) for variable \"gdollar_4\", which holds its previous value in one or more paths through the always construct" {  } { { "M8650D.v" "" { Text "//wsl.localhost/Debian/home/vrs/Verilog/projects/32k-Omnibus/M8650D.v" 796 0 0 } }  } 0 10240 "Verilog HDL Always Construct warning at %2!s!: inferring latch(es) for variable \"%1!s!\", which holds its previous value in one or more paths through the always construct" 0 0 "Quartus II" 0 -1 1700313833260 "|cpld|m8650d:m8650d"}
{ "Warning" "WVRFX_L2_VERI_ALWAYS_ID_HOLDS_VALUE" "gdollar_5_m M8650D.v(804) " "Verilog HDL Always Construct warning at M8650D.v(804): inferring latch(es) for variable \"gdollar_5_m\", which holds its previous value in one or more paths through the always construct" {  } { { "M8650D.v" "" { Text "//wsl.localhost/Debian/home/vrs/Verilog/projects/32k-Omnibus/M8650D.v" 804 0 0 } }  } 0 10240 "Verilog HDL Always Construct warning at %2!s!: inferring latch(es) for variable \"%1!s!\", which holds its previous value in one or more paths through the always construct" 0 0 "Quartus II" 0 -1 1700313833260 "|cpld|m8650d:m8650d"}
{ "Warning" "WVRFX_L2_VERI_ALWAYS_ID_HOLDS_VALUE" "gdollar_5 M8650D.v(812) " "Verilog HDL Always Construct warning at M8650D.v(812): inferring latch(es) for variable \"gdollar_5\", which holds its previous value in one or more paths through the always construct" {  } { { "M8650D.v" "" { Text "//wsl.localhost/Debian/home/vrs/Verilog/projects/32k-Omnibus/M8650D.v" 812 0 0 } }  } 0 10240 "Verilog HDL Always Construct warning at %2!s!: inferring latch(es) for variable \"%1!s!\", which holds its previous value in one or more paths through the always construct" 0 0 "Quartus II" 0 -1 1700313833260 "|cpld|m8650d:m8650d"}
{ "Warning" "WVRFX_L2_VERI_ALWAYS_ID_HOLDS_VALUE" "gdollar_6_m M8650D.v(820) " "Verilog HDL Always Construct warning at M8650D.v(820): inferring latch(es) for variable \"gdollar_6_m\", which holds its previous value in one or more paths through the always construct" {  } { { "M8650D.v" "" { Text "//wsl.localhost/Debian/home/vrs/Verilog/projects/32k-Omnibus/M8650D.v" 820 0 0 } }  } 0 10240 "Verilog HDL Always Construct warning at %2!s!: inferring latch(es) for variable \"%1!s!\", which holds its previous value in one or more paths through the always construct" 0 0 "Quartus II" 0 -1 1700313833260 "|cpld|m8650d:m8650d"}
{ "Warning" "WVRFX_L2_VERI_ALWAYS_ID_HOLDS_VALUE" "gdollar_6 M8650D.v(828) " "Verilog HDL Always Construct warning at M8650D.v(828): inferring latch(es) for variable \"gdollar_6\", which holds its previous value in one or more paths through the always construct" {  } { { "M8650D.v" "" { Text "//wsl.localhost/Debian/home/vrs/Verilog/projects/32k-Omnibus/M8650D.v" 828 0 0 } }  } 0 10240 "Verilog HDL Always Construct warning at %2!s!: inferring latch(es) for variable \"%1!s!\", which holds its previous value in one or more paths through the always construct" 0 0 "Quartus II" 0 -1 1700313833260 "|cpld|m8650d:m8650d"}
{ "Warning" "WVRFX_L2_VERI_ALWAYS_ID_HOLDS_VALUE" "n_t_154x_m M8650D.v(836) " "Verilog HDL Always Construct warning at M8650D.v(836): inferring latch(es) for variable \"n_t_154x_m\", which holds its previous value in one or more paths through the always construct" {  } { { "M8650D.v" "" { Text "//wsl.localhost/Debian/home/vrs/Verilog/projects/32k-Omnibus/M8650D.v" 836 0 0 } }  } 0 10240 "Verilog HDL Always Construct warning at %2!s!: inferring latch(es) for variable \"%1!s!\", which holds its previous value in one or more paths through the always construct" 0 0 "Quartus II" 0 -1 1700313833260 "|cpld|m8650d:m8650d"}
{ "Warning" "WVRFX_L2_VERI_ALWAYS_ID_HOLDS_VALUE" "n_t_154x M8650D.v(844) " "Verilog HDL Always Construct warning at M8650D.v(844): inferring latch(es) for variable \"n_t_154x\", which holds its previous value in one or more paths through the always construct" {  } { { "M8650D.v" "" { Text "//wsl.localhost/Debian/home/vrs/Verilog/projects/32k-Omnibus/M8650D.v" 844 0 0 } }  } 0 10240 "Verilog HDL Always Construct warning at %2!s!: inferring latch(es) for variable \"%1!s!\", which holds its previous value in one or more paths through the always construct" 0 0 "Quartus II" 0 -1 1700313833260 "|cpld|m8650d:m8650d"}
{ "Warning" "WVRFX_L2_VERI_ALWAYS_ID_HOLDS_VALUE" "n_t_146x_m M8650D.v(876) " "Verilog HDL Always Construct warning at M8650D.v(876): inferring latch(es) for variable \"n_t_146x_m\", which holds its previous value in one or more paths through the always construct" {  } { { "M8650D.v" "" { Text "//wsl.localhost/Debian/home/vrs/Verilog/projects/32k-Omnibus/M8650D.v" 876 0 0 } }  } 0 10240 "Verilog HDL Always Construct warning at %2!s!: inferring latch(es) for variable \"%1!s!\", which holds its previous value in one or more paths through the always construct" 0 0 "Quartus II" 0 -1 1700313833260 "|cpld|m8650d:m8650d"}
{ "Warning" "WVRFX_L2_VERI_ALWAYS_ID_HOLDS_VALUE" "n_t_146x M8650D.v(885) " "Verilog HDL Always Construct warning at M8650D.v(885): inferring latch(es) for variable \"n_t_146x\", which holds its previous value in one or more paths through the always construct" {  } { { "M8650D.v" "" { Text "//wsl.localhost/Debian/home/vrs/Verilog/projects/32k-Omnibus/M8650D.v" 885 0 0 } }  } 0 10240 "Verilog HDL Always Construct warning at %2!s!: inferring latch(es) for variable \"%1!s!\", which holds its previous value in one or more paths through the always construct" 0 0 "Quartus II" 0 -1 1700313833260 "|cpld|m8650d:m8650d"}
{ "Warning" "WVRFX_L2_VERI_ALWAYS_ID_HOLDS_VALUE" "gdollar_7_m M8650D.v(892) " "Verilog HDL Always Construct warning at M8650D.v(892): inferring latch(es) for variable \"gdollar_7_m\", which holds its previous value in one or more paths through the always construct" {  } { { "M8650D.v" "" { Text "//wsl.localhost/Debian/home/vrs/Verilog/projects/32k-Omnibus/M8650D.v" 892 0 0 } }  } 0 10240 "Verilog HDL Always Construct warning at %2!s!: inferring latch(es) for variable \"%1!s!\", which holds its previous value in one or more paths through the always construct" 0 0 "Quartus II" 0 -1 1700313833260 "|cpld|m8650d:m8650d"}
{ "Warning" "WVRFX_L2_VERI_ALWAYS_ID_HOLDS_VALUE" "gdollar_7 M8650D.v(901) " "Verilog HDL Always Construct warning at M8650D.v(901): inferring latch(es) for variable \"gdollar_7\", which holds its previous value in one or more paths through the always construct" {  } { { "M8650D.v" "" { Text "//wsl.localhost/Debian/home/vrs/Verilog/projects/32k-Omnibus/M8650D.v" 901 0 0 } }  } 0 10240 "Verilog HDL Always Construct warning at %2!s!: inferring latch(es) for variable \"%1!s!\", which holds its previous value in one or more paths through the always construct" 0 0 "Quartus II" 0 -1 1700313833264 "|cpld|m8650d:m8650d"}
{ "Warning" "WVRFX_L2_VERI_ALWAYS_ID_HOLDS_VALUE" "n_t_119x_m M8650D.v(908) " "Verilog HDL Always Construct warning at M8650D.v(908): inferring latch(es) for variable \"n_t_119x_m\", which holds its previous value in one or more paths through the always construct" {  } { { "M8650D.v" "" { Text "//wsl.localhost/Debian/home/vrs/Verilog/projects/32k-Omnibus/M8650D.v" 908 0 0 } }  } 0 10240 "Verilog HDL Always Construct warning at %2!s!: inferring latch(es) for variable \"%1!s!\", which holds its previous value in one or more paths through the always construct" 0 0 "Quartus II" 0 -1 1700313833264 "|cpld|m8650d:m8650d"}
{ "Warning" "WVRFX_L2_VERI_ALWAYS_ID_HOLDS_VALUE" "n_t_119x M8650D.v(917) " "Verilog HDL Always Construct warning at M8650D.v(917): inferring latch(es) for variable \"n_t_119x\", which holds its previous value in one or more paths through the always construct" {  } { { "M8650D.v" "" { Text "//wsl.localhost/Debian/home/vrs/Verilog/projects/32k-Omnibus/M8650D.v" 917 0 0 } }  } 0 10240 "Verilog HDL Always Construct warning at %2!s!: inferring latch(es) for variable \"%1!s!\", which holds its previous value in one or more paths through the always construct" 0 0 "Quartus II" 0 -1 1700313833264 "|cpld|m8650d:m8650d"}
{ "Warning" "WVRFX_L2_VERI_ALWAYS_ID_HOLDS_VALUE" "gdollar_8_m M8650D.v(924) " "Verilog HDL Always Construct warning at M8650D.v(924): inferring latch(es) for variable \"gdollar_8_m\", which holds its previous value in one or more paths through the always construct" {  } { { "M8650D.v" "" { Text "//wsl.localhost/Debian/home/vrs/Verilog/projects/32k-Omnibus/M8650D.v" 924 0 0 } }  } 0 10240 "Verilog HDL Always Construct warning at %2!s!: inferring latch(es) for variable \"%1!s!\", which holds its previous value in one or more paths through the always construct" 0 0 "Quartus II" 0 -1 1700313833264 "|cpld|m8650d:m8650d"}
{ "Warning" "WVRFX_L2_VERI_ALWAYS_ID_HOLDS_VALUE" "gdollar_8 M8650D.v(933) " "Verilog HDL Always Construct warning at M8650D.v(933): inferring latch(es) for variable \"gdollar_8\", which holds its previous value in one or more paths through the always construct" {  } { { "M8650D.v" "" { Text "//wsl.localhost/Debian/home/vrs/Verilog/projects/32k-Omnibus/M8650D.v" 933 0 0 } }  } 0 10240 "Verilog HDL Always Construct warning at %2!s!: inferring latch(es) for variable \"%1!s!\", which holds its previous value in one or more paths through the always construct" 0 0 "Quartus II" 0 -1 1700313833264 "|cpld|m8650d:m8650d"}
{ "Warning" "WVRFX_VERI_INCOMPLETE_SENSITIVITY_LIST" "n_t_60x_d M8650D.v(967) " "Verilog HDL Always Construct warning at M8650D.v(967): variable \"n_t_60x_d\" is read inside the Always Construct but isn't in the Always Construct's Event Control" {  } { { "M8650D.v" "" { Text "//wsl.localhost/Debian/home/vrs/Verilog/projects/32k-Omnibus/M8650D.v" 967 0 0 } }  } 0 10235 "Verilog HDL Always Construct warning at %2!s!: variable \"%1!s!\" is read inside the Always Construct but isn't in the Always Construct's Event Control" 0 0 "Quartus II" 0 -1 1700313833264 "|cpld|m8650d:m8650d"}
{ "Warning" "WVRFX_L2_VERI_ALWAYS_ID_HOLDS_VALUE" "n_t_60x_m M8650D.v(962) " "Verilog HDL Always Construct warning at M8650D.v(962): inferring latch(es) for variable \"n_t_60x_m\", which holds its previous value in one or more paths through the always construct" {  } { { "M8650D.v" "" { Text "//wsl.localhost/Debian/home/vrs/Verilog/projects/32k-Omnibus/M8650D.v" 962 0 0 } }  } 0 10240 "Verilog HDL Always Construct warning at %2!s!: inferring latch(es) for variable \"%1!s!\", which holds its previous value in one or more paths through the always construct" 0 0 "Quartus II" 0 -1 1700313833264 "|cpld|m8650d:m8650d"}
{ "Warning" "WVRFX_L2_VERI_ALWAYS_ID_HOLDS_VALUE" "n_t_60x M8650D.v(968) " "Verilog HDL Always Construct warning at M8650D.v(968): inferring latch(es) for variable \"n_t_60x\", which holds its previous value in one or more paths through the always construct" {  } { { "M8650D.v" "" { Text "//wsl.localhost/Debian/home/vrs/Verilog/projects/32k-Omnibus/M8650D.v" 968 0 0 } }  } 0 10240 "Verilog HDL Always Construct warning at %2!s!: inferring latch(es) for variable \"%1!s!\", which holds its previous value in one or more paths through the always construct" 0 0 "Quartus II" 0 -1 1700313833264 "|cpld|m8650d:m8650d"}
{ "Warning" "WVRFX_L2_VERI_ALWAYS_ID_HOLDS_VALUE" "n_t_62x_m M8650D.v(975) " "Verilog HDL Always Construct warning at M8650D.v(975): inferring latch(es) for variable \"n_t_62x_m\", which holds its previous value in one or more paths through the always construct" {  } { { "M8650D.v" "" { Text "//wsl.localhost/Debian/home/vrs/Verilog/projects/32k-Omnibus/M8650D.v" 975 0 0 } }  } 0 10240 "Verilog HDL Always Construct warning at %2!s!: inferring latch(es) for variable \"%1!s!\", which holds its previous value in one or more paths through the always construct" 0 0 "Quartus II" 0 -1 1700313833264 "|cpld|m8650d:m8650d"}
{ "Warning" "WVRFX_L2_VERI_ALWAYS_ID_HOLDS_VALUE" "n_t_62x M8650D.v(984) " "Verilog HDL Always Construct warning at M8650D.v(984): inferring latch(es) for variable \"n_t_62x\", which holds its previous value in one or more paths through the always construct" {  } { { "M8650D.v" "" { Text "//wsl.localhost/Debian/home/vrs/Verilog/projects/32k-Omnibus/M8650D.v" 984 0 0 } }  } 0 10240 "Verilog HDL Always Construct warning at %2!s!: inferring latch(es) for variable \"%1!s!\", which holds its previous value in one or more paths through the always construct" 0 0 "Quartus II" 0 -1 1700313833264 "|cpld|m8650d:m8650d"}
{ "Warning" "WVRFX_L2_VERI_ALWAYS_ID_HOLDS_VALUE" "n_t_56x_m M8650D.v(991) " "Verilog HDL Always Construct warning at M8650D.v(991): inferring latch(es) for variable \"n_t_56x_m\", which holds its previous value in one or more paths through the always construct" {  } { { "M8650D.v" "" { Text "//wsl.localhost/Debian/home/vrs/Verilog/projects/32k-Omnibus/M8650D.v" 991 0 0 } }  } 0 10240 "Verilog HDL Always Construct warning at %2!s!: inferring latch(es) for variable \"%1!s!\", which holds its previous value in one or more paths through the always construct" 0 0 "Quartus II" 0 -1 1700313833264 "|cpld|m8650d:m8650d"}
{ "Warning" "WVRFX_L2_VERI_ALWAYS_ID_HOLDS_VALUE" "n_t_56x M8650D.v(1000) " "Verilog HDL Always Construct warning at M8650D.v(1000): inferring latch(es) for variable \"n_t_56x\", which holds its previous value in one or more paths through the always construct" {  } { { "M8650D.v" "" { Text "//wsl.localhost/Debian/home/vrs/Verilog/projects/32k-Omnibus/M8650D.v" 1000 0 0 } }  } 0 10240 "Verilog HDL Always Construct warning at %2!s!: inferring latch(es) for variable \"%1!s!\", which holds its previous value in one or more paths through the always construct" 0 0 "Quartus II" 0 -1 1700313833264 "|cpld|m8650d:m8650d"}
{ "Warning" "WVRFX_L2_VERI_ALWAYS_ID_HOLDS_VALUE" "n_t_61x_m M8650D.v(1007) " "Verilog HDL Always Construct warning at M8650D.v(1007): inferring latch(es) for variable \"n_t_61x_m\", which holds its previous value in one or more paths through the always construct" {  } { { "M8650D.v" "" { Text "//wsl.localhost/Debian/home/vrs/Verilog/projects/32k-Omnibus/M8650D.v" 1007 0 0 } }  } 0 10240 "Verilog HDL Always Construct warning at %2!s!: inferring latch(es) for variable \"%1!s!\", which holds its previous value in one or more paths through the always construct" 0 0 "Quartus II" 0 -1 1700313833264 "|cpld|m8650d:m8650d"}
{ "Warning" "WVRFX_L2_VERI_ALWAYS_ID_HOLDS_VALUE" "n_t_61x M8650D.v(1016) " "Verilog HDL Always Construct warning at M8650D.v(1016): inferring latch(es) for variable \"n_t_61x\", which holds its previous value in one or more paths through the always construct" {  } { { "M8650D.v" "" { Text "//wsl.localhost/Debian/home/vrs/Verilog/projects/32k-Omnibus/M8650D.v" 1016 0 0 } }  } 0 10240 "Verilog HDL Always Construct warning at %2!s!: inferring latch(es) for variable \"%1!s!\", which holds its previous value in one or more paths through the always construct" 0 0 "Quartus II" 0 -1 1700313833264 "|cpld|m8650d:m8650d"}
{ "Warning" "WVRFX_L2_VERI_ALWAYS_ID_HOLDS_VALUE" "line_m M8650D.v(1024) " "Verilog HDL Always Construct warning at M8650D.v(1024): inferring latch(es) for variable \"line_m\", which holds its previous value in one or more paths through the always construct" {  } { { "M8650D.v" "" { Text "//wsl.localhost/Debian/home/vrs/Verilog/projects/32k-Omnibus/M8650D.v" 1024 0 0 } }  } 0 10240 "Verilog HDL Always Construct warning at %2!s!: inferring latch(es) for variable \"%1!s!\", which holds its previous value in one or more paths through the always construct" 0 0 "Quartus II" 0 -1 1700313833264 "|cpld|m8650d:m8650d"}
{ "Warning" "WVRFX_L2_VERI_ALWAYS_ID_HOLDS_VALUE" "line M8650D.v(1034) " "Verilog HDL Always Construct warning at M8650D.v(1034): inferring latch(es) for variable \"line\", which holds its previous value in one or more paths through the always construct" {  } { { "M8650D.v" "" { Text "//wsl.localhost/Debian/home/vrs/Verilog/projects/32k-Omnibus/M8650D.v" 1034 0 0 } }  } 0 10240 "Verilog HDL Always Construct warning at %2!s!: inferring latch(es) for variable \"%1!s!\", which holds its previous value in one or more paths through the always construct" 0 0 "Quartus II" 0 -1 1700313833264 "|cpld|m8650d:m8650d"}
{ "Warning" "WVRFX_L2_VERI_ALWAYS_ID_HOLDS_VALUE" "enab_m M8650D.v(1045) " "Verilog HDL Always Construct warning at M8650D.v(1045): inferring latch(es) for variable \"enab_m\", which holds its previous value in one or more paths through the always construct" {  } { { "M8650D.v" "" { Text "//wsl.localhost/Debian/home/vrs/Verilog/projects/32k-Omnibus/M8650D.v" 1045 0 0 } }  } 0 10240 "Verilog HDL Always Construct warning at %2!s!: inferring latch(es) for variable \"%1!s!\", which holds its previous value in one or more paths through the always construct" 0 0 "Quartus II" 0 -1 1700313833264 "|cpld|m8650d:m8650d"}
{ "Warning" "WVRFX_L2_VERI_ALWAYS_ID_HOLDS_VALUE" "enab M8650D.v(1055) " "Verilog HDL Always Construct warning at M8650D.v(1055): inferring latch(es) for variable \"enab\", which holds its previous value in one or more paths through the always construct" {  } { { "M8650D.v" "" { Text "//wsl.localhost/Debian/home/vrs/Verilog/projects/32k-Omnibus/M8650D.v" 1055 0 0 } }  } 0 10240 "Verilog HDL Always Construct warning at %2!s!: inferring latch(es) for variable \"%1!s!\", which holds its previous value in one or more paths through the always construct" 0 0 "Quartus II" 0 -1 1700313833264 "|cpld|m8650d:m8650d"}
{ "Warning" "WVRFX_L2_VERI_ALWAYS_ID_HOLDS_VALUE" "n_t_63x_m M8650D.v(1075) " "Verilog HDL Always Construct warning at M8650D.v(1075): inferring latch(es) for variable \"n_t_63x_m\", which holds its previous value in one or more paths through the always construct" {  } { { "M8650D.v" "" { Text "//wsl.localhost/Debian/home/vrs/Verilog/projects/32k-Omnibus/M8650D.v" 1075 0 0 } }  } 0 10240 "Verilog HDL Always Construct warning at %2!s!: inferring latch(es) for variable \"%1!s!\", which holds its previous value in one or more paths through the always construct" 0 0 "Quartus II" 0 -1 1700313833264 "|cpld|m8650d:m8650d"}
{ "Warning" "WVRFX_L2_VERI_ALWAYS_ID_HOLDS_VALUE" "n_t_63x M8650D.v(1084) " "Verilog HDL Always Construct warning at M8650D.v(1084): inferring latch(es) for variable \"n_t_63x\", which holds its previous value in one or more paths through the always construct" {  } { { "M8650D.v" "" { Text "//wsl.localhost/Debian/home/vrs/Verilog/projects/32k-Omnibus/M8650D.v" 1084 0 0 } }  } 0 10240 "Verilog HDL Always Construct warning at %2!s!: inferring latch(es) for variable \"%1!s!\", which holds its previous value in one or more paths through the always construct" 0 0 "Quartus II" 0 -1 1700313833264 "|cpld|m8650d:m8650d"}
{ "Warning" "WVRFX_L2_VERI_ALWAYS_ID_HOLDS_VALUE" "n_t_65x_m M8650D.v(1091) " "Verilog HDL Always Construct warning at M8650D.v(1091): inferring latch(es) for variable \"n_t_65x_m\", which holds its previous value in one or more paths through the always construct" {  } { { "M8650D.v" "" { Text "//wsl.localhost/Debian/home/vrs/Verilog/projects/32k-Omnibus/M8650D.v" 1091 0 0 } }  } 0 10240 "Verilog HDL Always Construct warning at %2!s!: inferring latch(es) for variable \"%1!s!\", which holds its previous value in one or more paths through the always construct" 0 0 "Quartus II" 0 -1 1700313833264 "|cpld|m8650d:m8650d"}
{ "Warning" "WVRFX_L2_VERI_ALWAYS_ID_HOLDS_VALUE" "n_t_65x M8650D.v(1100) " "Verilog HDL Always Construct warning at M8650D.v(1100): inferring latch(es) for variable \"n_t_65x\", which holds its previous value in one or more paths through the always construct" {  } { { "M8650D.v" "" { Text "//wsl.localhost/Debian/home/vrs/Verilog/projects/32k-Omnibus/M8650D.v" 1100 0 0 } }  } 0 10240 "Verilog HDL Always Construct warning at %2!s!: inferring latch(es) for variable \"%1!s!\", which holds its previous value in one or more paths through the always construct" 0 0 "Quartus II" 0 -1 1700313833264 "|cpld|m8650d:m8650d"}
{ "Warning" "WVRFX_L2_VERI_ALWAYS_ID_HOLDS_VALUE" "n_t_66x_m M8650D.v(1107) " "Verilog HDL Always Construct warning at M8650D.v(1107): inferring latch(es) for variable \"n_t_66x_m\", which holds its previous value in one or more paths through the always construct" {  } { { "M8650D.v" "" { Text "//wsl.localhost/Debian/home/vrs/Verilog/projects/32k-Omnibus/M8650D.v" 1107 0 0 } }  } 0 10240 "Verilog HDL Always Construct warning at %2!s!: inferring latch(es) for variable \"%1!s!\", which holds its previous value in one or more paths through the always construct" 0 0 "Quartus II" 0 -1 1700313833264 "|cpld|m8650d:m8650d"}
{ "Warning" "WVRFX_L2_VERI_ALWAYS_ID_HOLDS_VALUE" "n_t_66x M8650D.v(1116) " "Verilog HDL Always Construct warning at M8650D.v(1116): inferring latch(es) for variable \"n_t_66x\", which holds its previous value in one or more paths through the always construct" {  } { { "M8650D.v" "" { Text "//wsl.localhost/Debian/home/vrs/Verilog/projects/32k-Omnibus/M8650D.v" 1116 0 0 } }  } 0 10240 "Verilog HDL Always Construct warning at %2!s!: inferring latch(es) for variable \"%1!s!\", which holds its previous value in one or more paths through the always construct" 0 0 "Quartus II" 0 -1 1700313833264 "|cpld|m8650d:m8650d"}
{ "Warning" "WVRFX_L2_VERI_ALWAYS_ID_HOLDS_VALUE" "tx_data_m M8650D.v(1123) " "Verilog HDL Always Construct warning at M8650D.v(1123): inferring latch(es) for variable \"tx_data_m\", which holds its previous value in one or more paths through the always construct" {  } { { "M8650D.v" "" { Text "//wsl.localhost/Debian/home/vrs/Verilog/projects/32k-Omnibus/M8650D.v" 1123 0 0 } }  } 0 10240 "Verilog HDL Always Construct warning at %2!s!: inferring latch(es) for variable \"%1!s!\", which holds its previous value in one or more paths through the always construct" 0 0 "Quartus II" 0 -1 1700313833264 "|cpld|m8650d:m8650d"}
{ "Warning" "WVRFX_L2_VERI_ALWAYS_ID_HOLDS_VALUE" "tx_data M8650D.v(1132) " "Verilog HDL Always Construct warning at M8650D.v(1132): inferring latch(es) for variable \"tx_data\", which holds its previous value in one or more paths through the always construct" {  } { { "M8650D.v" "" { Text "//wsl.localhost/Debian/home/vrs/Verilog/projects/32k-Omnibus/M8650D.v" 1132 0 0 } }  } 0 10240 "Verilog HDL Always Construct warning at %2!s!: inferring latch(es) for variable \"%1!s!\", which holds its previous value in one or more paths through the always construct" 0 0 "Quartus II" 0 -1 1700313833264 "|cpld|m8650d:m8650d"}
{ "Warning" "WVRFX_L2_VERI_ALWAYS_ID_HOLDS_VALUE" "tflg_l_m M8650D.v(1159) " "Verilog HDL Always Construct warning at M8650D.v(1159): inferring latch(es) for variable \"tflg_l_m\", which holds its previous value in one or more paths through the always construct" {  } { { "M8650D.v" "" { Text "//wsl.localhost/Debian/home/vrs/Verilog/projects/32k-Omnibus/M8650D.v" 1159 0 0 } }  } 0 10240 "Verilog HDL Always Construct warning at %2!s!: inferring latch(es) for variable \"%1!s!\", which holds its previous value in one or more paths through the always construct" 0 0 "Quartus II" 0 -1 1700313833268 "|cpld|m8650d:m8650d"}
{ "Warning" "WVRFX_L2_VERI_ALWAYS_ID_HOLDS_VALUE" "tflg_l M8650D.v(1169) " "Verilog HDL Always Construct warning at M8650D.v(1169): inferring latch(es) for variable \"tflg_l\", which holds its previous value in one or more paths through the always construct" {  } { { "M8650D.v" "" { Text "//wsl.localhost/Debian/home/vrs/Verilog/projects/32k-Omnibus/M8650D.v" 1169 0 0 } }  } 0 10240 "Verilog HDL Always Construct warning at %2!s!: inferring latch(es) for variable \"%1!s!\", which holds its previous value in one or more paths through the always construct" 0 0 "Quartus II" 0 -1 1700313833268 "|cpld|m8650d:m8650d"}
{ "Warning" "WVRFX_L2_VERI_ALWAYS_ID_HOLDS_VALUE" "int_enab_l_m M8650D.v(1179) " "Verilog HDL Always Construct warning at M8650D.v(1179): inferring latch(es) for variable \"int_enab_l_m\", which holds its previous value in one or more paths through the always construct" {  } { { "M8650D.v" "" { Text "//wsl.localhost/Debian/home/vrs/Verilog/projects/32k-Omnibus/M8650D.v" 1179 0 0 } }  } 0 10240 "Verilog HDL Always Construct warning at %2!s!: inferring latch(es) for variable \"%1!s!\", which holds its previous value in one or more paths through the always construct" 0 0 "Quartus II" 0 -1 1700313833268 "|cpld|m8650d:m8650d"}
{ "Warning" "WVRFX_L2_VERI_ALWAYS_ID_HOLDS_VALUE" "int_enab_l M8650D.v(1189) " "Verilog HDL Always Construct warning at M8650D.v(1189): inferring latch(es) for variable \"int_enab_l\", which holds its previous value in one or more paths through the always construct" {  } { { "M8650D.v" "" { Text "//wsl.localhost/Debian/home/vrs/Verilog/projects/32k-Omnibus/M8650D.v" 1189 0 0 } }  } 0 10240 "Verilog HDL Always Construct warning at %2!s!: inferring latch(es) for variable \"%1!s!\", which holds its previous value in one or more paths through the always construct" 0 0 "Quartus II" 0 -1 1700313833268 "|cpld|m8650d:m8650d"}
{ "Warning" "WVRFX_L2_VERI_ALWAYS_ID_HOLDS_VALUE" "rflg_l_m M8650D.v(1254) " "Verilog HDL Always Construct warning at M8650D.v(1254): inferring latch(es) for variable \"rflg_l_m\", which holds its previous value in one or more paths through the always construct" {  } { { "M8650D.v" "" { Text "//wsl.localhost/Debian/home/vrs/Verilog/projects/32k-Omnibus/M8650D.v" 1254 0 0 } }  } 0 10240 "Verilog HDL Always Construct warning at %2!s!: inferring latch(es) for variable \"%1!s!\", which holds its previous value in one or more paths through the always construct" 0 0 "Quartus II" 0 -1 1700313833268 "|cpld|m8650d:m8650d"}
{ "Warning" "WVRFX_L2_VERI_ALWAYS_ID_HOLDS_VALUE" "rflg_l M8650D.v(1264) " "Verilog HDL Always Construct warning at M8650D.v(1264): inferring latch(es) for variable \"rflg_l\", which holds its previous value in one or more paths through the always construct" {  } { { "M8650D.v" "" { Text "//wsl.localhost/Debian/home/vrs/Verilog/projects/32k-Omnibus/M8650D.v" 1264 0 0 } }  } 0 10240 "Verilog HDL Always Construct warning at %2!s!: inferring latch(es) for variable \"%1!s!\", which holds its previous value in one or more paths through the always construct" 0 0 "Quartus II" 0 -1 1700313833268 "|cpld|m8650d:m8650d"}
{ "Warning" "WVRFX_L2_VERI_ALWAYS_ID_HOLDS_VALUE" "r_run_l_m M8650D.v(1274) " "Verilog HDL Always Construct warning at M8650D.v(1274): inferring latch(es) for variable \"r_run_l_m\", which holds its previous value in one or more paths through the always construct" {  } { { "M8650D.v" "" { Text "//wsl.localhost/Debian/home/vrs/Verilog/projects/32k-Omnibus/M8650D.v" 1274 0 0 } }  } 0 10240 "Verilog HDL Always Construct warning at %2!s!: inferring latch(es) for variable \"%1!s!\", which holds its previous value in one or more paths through the always construct" 0 0 "Quartus II" 0 -1 1700313833268 "|cpld|m8650d:m8650d"}
{ "Warning" "WVRFX_L2_VERI_ALWAYS_ID_HOLDS_VALUE" "r_run_l M8650D.v(1284) " "Verilog HDL Always Construct warning at M8650D.v(1284): inferring latch(es) for variable \"r_run_l\", which holds its previous value in one or more paths through the always construct" {  } { { "M8650D.v" "" { Text "//wsl.localhost/Debian/home/vrs/Verilog/projects/32k-Omnibus/M8650D.v" 1284 0 0 } }  } 0 10240 "Verilog HDL Always Construct warning at %2!s!: inferring latch(es) for variable \"%1!s!\", which holds its previous value in one or more paths through the always construct" 0 0 "Quartus II" 0 -1 1700313833268 "|cpld|m8650d:m8650d"}
{ "Warning" "WVRFX_L2_VDB_DRIVERLESS_OUTPUT_PORT" "n_t_77x M8650D.v(88) " "Output port \"n_t_77x\" at M8650D.v(88) has no driver" {  } { { "M8650D.v" "" { Text "//wsl.localhost/Debian/home/vrs/Verilog/projects/32k-Omnibus/M8650D.v" 88 0 0 } }  } 0 10034 "Output port \"%1!s!\" at %2!s! has no driver" 0 0 "Quartus II" 0 -1 1700313833268 "|cpld|m8650d:m8650d"}
{ "Warning" "WVRFX_L2_VDB_DRIVERLESS_OUTPUT_PORT" "eia_in M8650D.v(114) " "Output port \"eia_in\" at M8650D.v(114) has no driver" {  } { { "M8650D.v" "" { Text "//wsl.localhost/Debian/home/vrs/Verilog/projects/32k-Omnibus/M8650D.v" 114 0 0 } }  } 0 10034 "Output port \"%1!s!\" at %2!s! has no driver" 0 0 "Quartus II" 0 -1 1700313833268 "|cpld|m8650d:m8650d"}
{ "Warning" "WVRFX_L2_VDB_DRIVERLESS_OUTPUT_PORT" "eia_out M8650D.v(115) " "Output port \"eia_out\" at M8650D.v(115) has no driver" {  } { { "M8650D.v" "" { Text "//wsl.localhost/Debian/home/vrs/Verilog/projects/32k-Omnibus/M8650D.v" 115 0 0 } }  } 0 10034 "Output port \"%1!s!\" at %2!s! has no driver" 0 0 "Quartus II" 0 -1 1700313833268 "|cpld|m8650d:m8650d"}
{ "Warning" "WVRFX_L2_VDB_DRIVERLESS_OUTPUT_PORT" "n15v M8650D.v(133) " "Output port \"n15v\" at M8650D.v(133) has no driver" {  } { { "M8650D.v" "" { Text "//wsl.localhost/Debian/home/vrs/Verilog/projects/32k-Omnibus/M8650D.v" 133 0 0 } }  } 0 10034 "Output port \"%1!s!\" at %2!s! has no driver" 0 0 "Quartus II" 0 -1 1700313833268 "|cpld|m8650d:m8650d"}
{ "Warning" "WVRFX_L2_VDB_DRIVERLESS_OUTPUT_PORT" "reader_run M8650D.v(150) " "Output port \"reader_run\" at M8650D.v(150) has no driver" {  } { { "M8650D.v" "" { Text "//wsl.localhost/Debian/home/vrs/Verilog/projects/32k-Omnibus/M8650D.v" 150 0 0 } }  } 0 10034 "Output port \"%1!s!\" at %2!s! has no driver" 0 0 "Quartus II" 0 -1 1700313833268 "|cpld|m8650d:m8650d"}
{ "Warning" "WVRFX_L2_VDB_DRIVERLESS_OUTPUT_PORT" "reader_run_or M8650D.v(151) " "Output port \"reader_run_or\" at M8650D.v(151) has no driver" {  } { { "M8650D.v" "" { Text "//wsl.localhost/Debian/home/vrs/Verilog/projects/32k-Omnibus/M8650D.v" 151 0 0 } }  } 0 10034 "Output port \"%1!s!\" at %2!s! has no driver" 0 0 "Quartus II" 0 -1 1700313833268 "|cpld|m8650d:m8650d"}
{ "Warning" "WVRFX_L2_VDB_DRIVERLESS_OUTPUT_PORT" "rtsdtr M8650D.v(152) " "Output port \"rtsdtr\" at M8650D.v(152) has no driver" {  } { { "M8650D.v" "" { Text "//wsl.localhost/Debian/home/vrs/Verilog/projects/32k-Omnibus/M8650D.v" 152 0 0 } }  } 0 10034 "Output port \"%1!s!\" at %2!s! has no driver" 0 0 "Quartus II" 0 -1 1700313833268 "|cpld|m8650d:m8650d"}
{ "Warning" "WVRFX_L2_VDB_DRIVERLESS_OUTPUT_PORT" "rx_20ma M8650D.v(154) " "Output port \"rx_20ma\" at M8650D.v(154) has no driver" {  } { { "M8650D.v" "" { Text "//wsl.localhost/Debian/home/vrs/Verilog/projects/32k-Omnibus/M8650D.v" 154 0 0 } }  } 0 10034 "Output port \"%1!s!\" at %2!s! has no driver" 0 0 "Quartus II" 0 -1 1700313833268 "|cpld|m8650d:m8650d"}
{ "Warning" "WVRFX_L2_VDB_DRIVERLESS_OUTPUT_PORT" "rx_20ma_or M8650D.v(155) " "Output port \"rx_20ma_or\" at M8650D.v(155) has no driver" {  } { { "M8650D.v" "" { Text "//wsl.localhost/Debian/home/vrs/Verilog/projects/32k-Omnibus/M8650D.v" 155 0 0 } }  } 0 10034 "Output port \"%1!s!\" at %2!s! has no driver" 0 0 "Quartus II" 0 -1 1700313833268 "|cpld|m8650d:m8650d"}
{ "Warning" "WVRFX_L2_VDB_DRIVERLESS_OUTPUT_PORT" "tx_20ma M8650D.v(165) " "Output port \"tx_20ma\" at M8650D.v(165) has no driver" {  } { { "M8650D.v" "" { Text "//wsl.localhost/Debian/home/vrs/Verilog/projects/32k-Omnibus/M8650D.v" 165 0 0 } }  } 0 10034 "Output port \"%1!s!\" at %2!s! has no driver" 0 0 "Quartus II" 0 -1 1700313833268 "|cpld|m8650d:m8650d"}
{ "Warning" "WVRFX_L2_VDB_DRIVERLESS_OUTPUT_PORT" "tx_20ma_or M8650D.v(166) " "Output port \"tx_20ma_or\" at M8650D.v(166) has no driver" {  } { { "M8650D.v" "" { Text "//wsl.localhost/Debian/home/vrs/Verilog/projects/32k-Omnibus/M8650D.v" 166 0 0 } }  } 0 10034 "Output port \"%1!s!\" at %2!s! has no driver" 0 0 "Quartus II" 0 -1 1700313833268 "|cpld|m8650d:m8650d"}
{ "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "r_run_l M8650D.v(1284) " "Inferred latch for \"r_run_l\" at M8650D.v(1284)" {  } { { "M8650D.v" "" { Text "//wsl.localhost/Debian/home/vrs/Verilog/projects/32k-Omnibus/M8650D.v" 1284 0 0 } }  } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "Quartus II" 0 -1 1700313833268 "|cpld|m8650d:m8650d"}
{ "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "r_run_l_m M8650D.v(1274) " "Inferred latch for \"r_run_l_m\" at M8650D.v(1274)" {  } { { "M8650D.v" "" { Text "//wsl.localhost/Debian/home/vrs/Verilog/projects/32k-Omnibus/M8650D.v" 1274 0 0 } }  } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "Quartus II" 0 -1 1700313833268 "|cpld|m8650d:m8650d"}
{ "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "rflg_l M8650D.v(1264) " "Inferred latch for \"rflg_l\" at M8650D.v(1264)" {  } { { "M8650D.v" "" { Text "//wsl.localhost/Debian/home/vrs/Verilog/projects/32k-Omnibus/M8650D.v" 1264 0 0 } }  } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "Quartus II" 0 -1 1700313833268 "|cpld|m8650d:m8650d"}
{ "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "rflg_l_m M8650D.v(1254) " "Inferred latch for \"rflg_l_m\" at M8650D.v(1254)" {  } { { "M8650D.v" "" { Text "//wsl.localhost/Debian/home/vrs/Verilog/projects/32k-Omnibus/M8650D.v" 1254 0 0 } }  } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "Quartus II" 0 -1 1700313833268 "|cpld|m8650d:m8650d"}
{ "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "int_enab_l M8650D.v(1189) " "Inferred latch for \"int_enab_l\" at M8650D.v(1189)" {  } { { "M8650D.v" "" { Text "//wsl.localhost/Debian/home/vrs/Verilog/projects/32k-Omnibus/M8650D.v" 1189 0 0 } }  } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "Quartus II" 0 -1 1700313833268 "|cpld|m8650d:m8650d"}
{ "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "int_enab_l_m M8650D.v(1179) " "Inferred latch for \"int_enab_l_m\" at M8650D.v(1179)" {  } { { "M8650D.v" "" { Text "//wsl.localhost/Debian/home/vrs/Verilog/projects/32k-Omnibus/M8650D.v" 1179 0 0 } }  } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "Quartus II" 0 -1 1700313833268 "|cpld|m8650d:m8650d"}
{ "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "tflg_l M8650D.v(1169) " "Inferred latch for \"tflg_l\" at M8650D.v(1169)" {  } { { "M8650D.v" "" { Text "//wsl.localhost/Debian/home/vrs/Verilog/projects/32k-Omnibus/M8650D.v" 1169 0 0 } }  } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "Quartus II" 0 -1 1700313833268 "|cpld|m8650d:m8650d"}
{ "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "tflg_l_m M8650D.v(1159) " "Inferred latch for \"tflg_l_m\" at M8650D.v(1159)" {  } { { "M8650D.v" "" { Text "//wsl.localhost/Debian/home/vrs/Verilog/projects/32k-Omnibus/M8650D.v" 1159 0 0 } }  } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "Quartus II" 0 -1 1700313833268 "|cpld|m8650d:m8650d"}
{ "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "tx_data M8650D.v(1132) " "Inferred latch for \"tx_data\" at M8650D.v(1132)" {  } { { "M8650D.v" "" { Text "//wsl.localhost/Debian/home/vrs/Verilog/projects/32k-Omnibus/M8650D.v" 1132 0 0 } }  } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "Quartus II" 0 -1 1700313833268 "|cpld|m8650d:m8650d"}
{ "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "tx_data_m M8650D.v(1123) " "Inferred latch for \"tx_data_m\" at M8650D.v(1123)" {  } { { "M8650D.v" "" { Text "//wsl.localhost/Debian/home/vrs/Verilog/projects/32k-Omnibus/M8650D.v" 1123 0 0 } }  } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "Quartus II" 0 -1 1700313833268 "|cpld|m8650d:m8650d"}
{ "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "n_t_66x M8650D.v(1116) " "Inferred latch for \"n_t_66x\" at M8650D.v(1116)" {  } { { "M8650D.v" "" { Text "//wsl.localhost/Debian/home/vrs/Verilog/projects/32k-Omnibus/M8650D.v" 1116 0 0 } }  } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "Quartus II" 0 -1 1700313833268 "|cpld|m8650d:m8650d"}
{ "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "n_t_66x_m M8650D.v(1107) " "Inferred latch for \"n_t_66x_m\" at M8650D.v(1107)" {  } { { "M8650D.v" "" { Text "//wsl.localhost/Debian/home/vrs/Verilog/projects/32k-Omnibus/M8650D.v" 1107 0 0 } }  } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "Quartus II" 0 -1 1700313833268 "|cpld|m8650d:m8650d"}
{ "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "n_t_65x M8650D.v(1100) " "Inferred latch for \"n_t_65x\" at M8650D.v(1100)" {  } { { "M8650D.v" "" { Text "//wsl.localhost/Debian/home/vrs/Verilog/projects/32k-Omnibus/M8650D.v" 1100 0 0 } }  } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "Quartus II" 0 -1 1700313833268 "|cpld|m8650d:m8650d"}
{ "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "n_t_65x_m M8650D.v(1091) " "Inferred latch for \"n_t_65x_m\" at M8650D.v(1091)" {  } { { "M8650D.v" "" { Text "//wsl.localhost/Debian/home/vrs/Verilog/projects/32k-Omnibus/M8650D.v" 1091 0 0 } }  } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "Quartus II" 0 -1 1700313833268 "|cpld|m8650d:m8650d"}
{ "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "n_t_63x M8650D.v(1084) " "Inferred latch for \"n_t_63x\" at M8650D.v(1084)" {  } { { "M8650D.v" "" { Text "//wsl.localhost/Debian/home/vrs/Verilog/projects/32k-Omnibus/M8650D.v" 1084 0 0 } }  } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "Quartus II" 0 -1 1700313833274 "|cpld|m8650d:m8650d"}
{ "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "n_t_63x_m M8650D.v(1075) " "Inferred latch for \"n_t_63x_m\" at M8650D.v(1075)" {  } { { "M8650D.v" "" { Text "//wsl.localhost/Debian/home/vrs/Verilog/projects/32k-Omnibus/M8650D.v" 1075 0 0 } }  } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "Quartus II" 0 -1 1700313833274 "|cpld|m8650d:m8650d"}
{ "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "enab M8650D.v(1055) " "Inferred latch for \"enab\" at M8650D.v(1055)" {  } { { "M8650D.v" "" { Text "//wsl.localhost/Debian/home/vrs/Verilog/projects/32k-Omnibus/M8650D.v" 1055 0 0 } }  } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "Quartus II" 0 -1 1700313833274 "|cpld|m8650d:m8650d"}
{ "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "enab_m M8650D.v(1045) " "Inferred latch for \"enab_m\" at M8650D.v(1045)" {  } { { "M8650D.v" "" { Text "//wsl.localhost/Debian/home/vrs/Verilog/projects/32k-Omnibus/M8650D.v" 1045 0 0 } }  } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "Quartus II" 0 -1 1700313833274 "|cpld|m8650d:m8650d"}
{ "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "line M8650D.v(1034) " "Inferred latch for \"line\" at M8650D.v(1034)" {  } { { "M8650D.v" "" { Text "//wsl.localhost/Debian/home/vrs/Verilog/projects/32k-Omnibus/M8650D.v" 1034 0 0 } }  } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "Quartus II" 0 -1 1700313833274 "|cpld|m8650d:m8650d"}
{ "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "line_m M8650D.v(1024) " "Inferred latch for \"line_m\" at M8650D.v(1024)" {  } { { "M8650D.v" "" { Text "//wsl.localhost/Debian/home/vrs/Verilog/projects/32k-Omnibus/M8650D.v" 1024 0 0 } }  } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "Quartus II" 0 -1 1700313833274 "|cpld|m8650d:m8650d"}
{ "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "n_t_61x M8650D.v(1016) " "Inferred latch for \"n_t_61x\" at M8650D.v(1016)" {  } { { "M8650D.v" "" { Text "//wsl.localhost/Debian/home/vrs/Verilog/projects/32k-Omnibus/M8650D.v" 1016 0 0 } }  } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "Quartus II" 0 -1 1700313833274 "|cpld|m8650d:m8650d"}
{ "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "n_t_61x_m M8650D.v(1007) " "Inferred latch for \"n_t_61x_m\" at M8650D.v(1007)" {  } { { "M8650D.v" "" { Text "//wsl.localhost/Debian/home/vrs/Verilog/projects/32k-Omnibus/M8650D.v" 1007 0 0 } }  } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "Quartus II" 0 -1 1700313833274 "|cpld|m8650d:m8650d"}
{ "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "n_t_56x M8650D.v(1000) " "Inferred latch for \"n_t_56x\" at M8650D.v(1000)" {  } { { "M8650D.v" "" { Text "//wsl.localhost/Debian/home/vrs/Verilog/projects/32k-Omnibus/M8650D.v" 1000 0 0 } }  } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "Quartus II" 0 -1 1700313833274 "|cpld|m8650d:m8650d"}
{ "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "n_t_56x_m M8650D.v(991) " "Inferred latch for \"n_t_56x_m\" at M8650D.v(991)" {  } { { "M8650D.v" "" { Text "//wsl.localhost/Debian/home/vrs/Verilog/projects/32k-Omnibus/M8650D.v" 991 0 0 } }  } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "Quartus II" 0 -1 1700313833274 "|cpld|m8650d:m8650d"}
{ "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "n_t_62x M8650D.v(984) " "Inferred latch for \"n_t_62x\" at M8650D.v(984)" {  } { { "M8650D.v" "" { Text "//wsl.localhost/Debian/home/vrs/Verilog/projects/32k-Omnibus/M8650D.v" 984 0 0 } }  } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "Quartus II" 0 -1 1700313833274 "|cpld|m8650d:m8650d"}
{ "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "n_t_62x_m M8650D.v(975) " "Inferred latch for \"n_t_62x_m\" at M8650D.v(975)" {  } { { "M8650D.v" "" { Text "//wsl.localhost/Debian/home/vrs/Verilog/projects/32k-Omnibus/M8650D.v" 975 0 0 } }  } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "Quartus II" 0 -1 1700313833274 "|cpld|m8650d:m8650d"}
{ "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "n_t_60x M8650D.v(968) " "Inferred latch for \"n_t_60x\" at M8650D.v(968)" {  } { { "M8650D.v" "" { Text "//wsl.localhost/Debian/home/vrs/Verilog/projects/32k-Omnibus/M8650D.v" 968 0 0 } }  } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "Quartus II" 0 -1 1700313833274 "|cpld|m8650d:m8650d"}
{ "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "n_t_60x_m M8650D.v(962) " "Inferred latch for \"n_t_60x_m\" at M8650D.v(962)" {  } { { "M8650D.v" "" { Text "//wsl.localhost/Debian/home/vrs/Verilog/projects/32k-Omnibus/M8650D.v" 962 0 0 } }  } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "Quartus II" 0 -1 1700313833274 "|cpld|m8650d:m8650d"}
{ "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "n_t_119x M8650D.v(917) " "Inferred latch for \"n_t_119x\" at M8650D.v(917)" {  } { { "M8650D.v" "" { Text "//wsl.localhost/Debian/home/vrs/Verilog/projects/32k-Omnibus/M8650D.v" 917 0 0 } }  } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "Quartus II" 0 -1 1700313833274 "|cpld|m8650d:m8650d"}
{ "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "n_t_119x_m M8650D.v(908) " "Inferred latch for \"n_t_119x_m\" at M8650D.v(908)" {  } { { "M8650D.v" "" { Text "//wsl.localhost/Debian/home/vrs/Verilog/projects/32k-Omnibus/M8650D.v" 908 0 0 } }  } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "Quartus II" 0 -1 1700313833274 "|cpld|m8650d:m8650d"}
{ "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "gdollar_7 M8650D.v(901) " "Inferred latch for \"gdollar_7\" at M8650D.v(901)" {  } { { "M8650D.v" "" { Text "//wsl.localhost/Debian/home/vrs/Verilog/projects/32k-Omnibus/M8650D.v" 901 0 0 } }  } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "Quartus II" 0 -1 1700313833274 "|cpld|m8650d:m8650d"}
{ "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "gdollar_7_m M8650D.v(892) " "Inferred latch for \"gdollar_7_m\" at M8650D.v(892)" {  } { { "M8650D.v" "" { Text "//wsl.localhost/Debian/home/vrs/Verilog/projects/32k-Omnibus/M8650D.v" 892 0 0 } }  } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "Quartus II" 0 -1 1700313833274 "|cpld|m8650d:m8650d"}
{ "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "n_t_146x M8650D.v(885) " "Inferred latch for \"n_t_146x\" at M8650D.v(885)" {  } { { "M8650D.v" "" { Text "//wsl.localhost/Debian/home/vrs/Verilog/projects/32k-Omnibus/M8650D.v" 885 0 0 } }  } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "Quartus II" 0 -1 1700313833274 "|cpld|m8650d:m8650d"}
{ "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "n_t_146x_m M8650D.v(876) " "Inferred latch for \"n_t_146x_m\" at M8650D.v(876)" {  } { { "M8650D.v" "" { Text "//wsl.localhost/Debian/home/vrs/Verilog/projects/32k-Omnibus/M8650D.v" 876 0 0 } }  } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "Quartus II" 0 -1 1700313833274 "|cpld|m8650d:m8650d"}
{ "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "n_t_154x M8650D.v(844) " "Inferred latch for \"n_t_154x\" at M8650D.v(844)" {  } { { "M8650D.v" "" { Text "//wsl.localhost/Debian/home/vrs/Verilog/projects/32k-Omnibus/M8650D.v" 844 0 0 } }  } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "Quartus II" 0 -1 1700313833274 "|cpld|m8650d:m8650d"}
{ "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "n_t_154x_m M8650D.v(836) " "Inferred latch for \"n_t_154x_m\" at M8650D.v(836)" {  } { { "M8650D.v" "" { Text "//wsl.localhost/Debian/home/vrs/Verilog/projects/32k-Omnibus/M8650D.v" 836 0 0 } }  } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "Quartus II" 0 -1 1700313833274 "|cpld|m8650d:m8650d"}
{ "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "gdollar_6 M8650D.v(828) " "Inferred latch for \"gdollar_6\" at M8650D.v(828)" {  } { { "M8650D.v" "" { Text "//wsl.localhost/Debian/home/vrs/Verilog/projects/32k-Omnibus/M8650D.v" 828 0 0 } }  } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "Quartus II" 0 -1 1700313833274 "|cpld|m8650d:m8650d"}
{ "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "gdollar_6_m M8650D.v(820) " "Inferred latch for \"gdollar_6_m\" at M8650D.v(820)" {  } { { "M8650D.v" "" { Text "//wsl.localhost/Debian/home/vrs/Verilog/projects/32k-Omnibus/M8650D.v" 820 0 0 } }  } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "Quartus II" 0 -1 1700313833274 "|cpld|m8650d:m8650d"}
{ "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "gdollar_5 M8650D.v(812) " "Inferred latch for \"gdollar_5\" at M8650D.v(812)" {  } { { "M8650D.v" "" { Text "//wsl.localhost/Debian/home/vrs/Verilog/projects/32k-Omnibus/M8650D.v" 812 0 0 } }  } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "Quartus II" 0 -1 1700313833274 "|cpld|m8650d:m8650d"}
{ "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "gdollar_5_m M8650D.v(804) " "Inferred latch for \"gdollar_5_m\" at M8650D.v(804)" {  } { { "M8650D.v" "" { Text "//wsl.localhost/Debian/home/vrs/Verilog/projects/32k-Omnibus/M8650D.v" 804 0 0 } }  } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "Quartus II" 0 -1 1700313833274 "|cpld|m8650d:m8650d"}
{ "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "gdollar_4 M8650D.v(796) " "Inferred latch for \"gdollar_4\" at M8650D.v(796)" {  } { { "M8650D.v" "" { Text "//wsl.localhost/Debian/home/vrs/Verilog/projects/32k-Omnibus/M8650D.v" 796 0 0 } }  } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "Quartus II" 0 -1 1700313833274 "|cpld|m8650d:m8650d"}
{ "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "gdollar_4_m M8650D.v(788) " "Inferred latch for \"gdollar_4_m\" at M8650D.v(788)" {  } { { "M8650D.v" "" { Text "//wsl.localhost/Debian/home/vrs/Verilog/projects/32k-Omnibus/M8650D.v" 788 0 0 } }  } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "Quartus II" 0 -1 1700313833274 "|cpld|m8650d:m8650d"}
{ "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "start_l M8650D.v(775) " "Inferred latch for \"start_l\" at M8650D.v(775)" {  } { { "M8650D.v" "" { Text "//wsl.localhost/Debian/home/vrs/Verilog/projects/32k-Omnibus/M8650D.v" 775 0 0 } }  } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "Quartus II" 0 -1 1700313833274 "|cpld|m8650d:m8650d"}
{ "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "start_l_m M8650D.v(765) " "Inferred latch for \"start_l_m\" at M8650D.v(765)" {  } { { "M8650D.v" "" { Text "//wsl.localhost/Debian/home/vrs/Verilog/projects/32k-Omnibus/M8650D.v" 765 0 0 } }  } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "Quartus II" 0 -1 1700313833274 "|cpld|m8650d:m8650d"}
{ "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "tx_active_l M8650D.v(754) " "Inferred latch for \"tx_active_l\" at M8650D.v(754)" {  } { { "M8650D.v" "" { Text "//wsl.localhost/Debian/home/vrs/Verilog/projects/32k-Omnibus/M8650D.v" 754 0 0 } }  } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "Quartus II" 0 -1 1700313833274 "|cpld|m8650d:m8650d"}
{ "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "tx_active_l_m M8650D.v(744) " "Inferred latch for \"tx_active_l_m\" at M8650D.v(744)" {  } { { "M8650D.v" "" { Text "//wsl.localhost/Debian/home/vrs/Verilog/projects/32k-Omnibus/M8650D.v" 744 0 0 } }  } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "Quartus II" 0 -1 1700313833274 "|cpld|m8650d:m8650d"}
{ "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "spike_det_l M8650D.v(712) " "Inferred latch for \"spike_det_l\" at M8650D.v(712)" {  } { { "M8650D.v" "" { Text "//wsl.localhost/Debian/home/vrs/Verilog/projects/32k-Omnibus/M8650D.v" 712 0 0 } }  } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "Quartus II" 0 -1 1700313833274 "|cpld|m8650d:m8650d"}
{ "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "spike_det_l_m M8650D.v(702) " "Inferred latch for \"spike_det_l_m\" at M8650D.v(702)" {  } { { "M8650D.v" "" { Text "//wsl.localhost/Debian/home/vrs/Verilog/projects/32k-Omnibus/M8650D.v" 702 0 0 } }  } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "Quartus II" 0 -1 1700313833274 "|cpld|m8650d:m8650d"}
{ "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "tx_div M8650D.v(691) " "Inferred latch for \"tx_div\" at M8650D.v(691)" {  } { { "M8650D.v" "" { Text "//wsl.localhost/Debian/home/vrs/Verilog/projects/32k-Omnibus/M8650D.v" 691 0 0 } }  } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "Quartus II" 0 -1 1700313833274 "|cpld|m8650d:m8650d"}
{ "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "tx_div_m M8650D.v(681) " "Inferred latch for \"tx_div_m\" at M8650D.v(681)" {  } { { "M8650D.v" "" { Text "//wsl.localhost/Debian/home/vrs/Verilog/projects/32k-Omnibus/M8650D.v" 681 0 0 } }  } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "Quartus II" 0 -1 1700313833274 "|cpld|m8650d:m8650d"}
{ "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "n_t_40x M8650D.v(637) " "Inferred latch for \"n_t_40x\" at M8650D.v(637)" {  } { { "M8650D.v" "" { Text "//wsl.localhost/Debian/home/vrs/Verilog/projects/32k-Omnibus/M8650D.v" 637 0 0 } }  } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "Quartus II" 0 -1 1700313833274 "|cpld|m8650d:m8650d"}
{ "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "n_t_40x_m M8650D.v(628) " "Inferred latch for \"n_t_40x_m\" at M8650D.v(628)" {  } { { "M8650D.v" "" { Text "//wsl.localhost/Debian/home/vrs/Verilog/projects/32k-Omnibus/M8650D.v" 628 0 0 } }  } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "Quartus II" 0 -1 1700313833274 "|cpld|m8650d:m8650d"}
{ "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "n_t_39x M8650D.v(621) " "Inferred latch for \"n_t_39x\" at M8650D.v(621)" {  } { { "M8650D.v" "" { Text "//wsl.localhost/Debian/home/vrs/Verilog/projects/32k-Omnibus/M8650D.v" 621 0 0 } }  } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "Quartus II" 0 -1 1700313833274 "|cpld|m8650d:m8650d"}
{ "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "n_t_39x_m M8650D.v(612) " "Inferred latch for \"n_t_39x_m\" at M8650D.v(612)" {  } { { "M8650D.v" "" { Text "//wsl.localhost/Debian/home/vrs/Verilog/projects/32k-Omnibus/M8650D.v" 612 0 0 } }  } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "Quartus II" 0 -1 1700313833274 "|cpld|m8650d:m8650d"}
{ "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "n_t_38x M8650D.v(605) " "Inferred latch for \"n_t_38x\" at M8650D.v(605)" {  } { { "M8650D.v" "" { Text "//wsl.localhost/Debian/home/vrs/Verilog/projects/32k-Omnibus/M8650D.v" 605 0 0 } }  } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "Quartus II" 0 -1 1700313833274 "|cpld|m8650d:m8650d"}
{ "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "n_t_38x_m M8650D.v(596) " "Inferred latch for \"n_t_38x_m\" at M8650D.v(596)" {  } { { "M8650D.v" "" { Text "//wsl.localhost/Debian/home/vrs/Verilog/projects/32k-Omnibus/M8650D.v" 596 0 0 } }  } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "Quartus II" 0 -1 1700313833274 "|cpld|m8650d:m8650d"}
{ "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "n_t_37x M8650D.v(589) " "Inferred latch for \"n_t_37x\" at M8650D.v(589)" {  } { { "M8650D.v" "" { Text "//wsl.localhost/Debian/home/vrs/Verilog/projects/32k-Omnibus/M8650D.v" 589 0 0 } }  } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "Quartus II" 0 -1 1700313833274 "|cpld|m8650d:m8650d"}
{ "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "n_t_37x_m M8650D.v(580) " "Inferred latch for \"n_t_37x_m\" at M8650D.v(580)" {  } { { "M8650D.v" "" { Text "//wsl.localhost/Debian/home/vrs/Verilog/projects/32k-Omnibus/M8650D.v" 580 0 0 } }  } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "Quartus II" 0 -1 1700313833274 "|cpld|m8650d:m8650d"}
{ "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "n_t_88x M8650D.v(561) " "Inferred latch for \"n_t_88x\" at M8650D.v(561)" {  } { { "M8650D.v" "" { Text "//wsl.localhost/Debian/home/vrs/Verilog/projects/32k-Omnibus/M8650D.v" 561 0 0 } }  } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "Quartus II" 0 -1 1700313833274 "|cpld|m8650d:m8650d"}
{ "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "n_t_88x_m M8650D.v(551) " "Inferred latch for \"n_t_88x_m\" at M8650D.v(551)" {  } { { "M8650D.v" "" { Text "//wsl.localhost/Debian/home/vrs/Verilog/projects/32k-Omnibus/M8650D.v" 551 0 0 } }  } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "Quartus II" 0 -1 1700313833274 "|cpld|m8650d:m8650d"}
{ "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "last_unit M8650D.v(541) " "Inferred latch for \"last_unit\" at M8650D.v(541)" {  } { { "M8650D.v" "" { Text "//wsl.localhost/Debian/home/vrs/Verilog/projects/32k-Omnibus/M8650D.v" 541 0 0 } }  } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "Quartus II" 0 -1 1700313833274 "|cpld|m8650d:m8650d"}
{ "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "last_unit_m M8650D.v(531) " "Inferred latch for \"last_unit_m\" at M8650D.v(531)" {  } { { "M8650D.v" "" { Text "//wsl.localhost/Debian/home/vrs/Verilog/projects/32k-Omnibus/M8650D.v" 531 0 0 } }  } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "Quartus II" 0 -1 1700313833274 "|cpld|m8650d:m8650d"}
{ "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "p_pulse_l M8650D.v(520) " "Inferred latch for \"p_pulse_l\" at M8650D.v(520)" {  } { { "M8650D.v" "" { Text "//wsl.localhost/Debian/home/vrs/Verilog/projects/32k-Omnibus/M8650D.v" 520 0 0 } }  } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "Quartus II" 0 -1 1700313833274 "|cpld|m8650d:m8650d"}
{ "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "p_pulse_l_m M8650D.v(510) " "Inferred latch for \"p_pulse_l_m\" at M8650D.v(510)" {  } { { "M8650D.v" "" { Text "//wsl.localhost/Debian/home/vrs/Verilog/projects/32k-Omnibus/M8650D.v" 510 0 0 } }  } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "Quartus II" 0 -1 1700313833274 "|cpld|m8650d:m8650d"}
{ "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "rx_active M8650D.v(500) " "Inferred latch for \"rx_active\" at M8650D.v(500)" {  } { { "M8650D.v" "" { Text "//wsl.localhost/Debian/home/vrs/Verilog/projects/32k-Omnibus/M8650D.v" 500 0 0 } }  } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "Quartus II" 0 -1 1700313833274 "|cpld|m8650d:m8650d"}
{ "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "rx_active_m M8650D.v(490) " "Inferred latch for \"rx_active_m\" at M8650D.v(490)" {  } { { "M8650D.v" "" { Text "//wsl.localhost/Debian/home/vrs/Verilog/projects/32k-Omnibus/M8650D.v" 490 0 0 } }  } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "Quartus II" 0 -1 1700313833274 "|cpld|m8650d:m8650d"}
{ "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "n_t_35x M8650D.v(482) " "Inferred latch for \"n_t_35x\" at M8650D.v(482)" {  } { { "M8650D.v" "" { Text "//wsl.localhost/Debian/home/vrs/Verilog/projects/32k-Omnibus/M8650D.v" 482 0 0 } }  } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "Quartus II" 0 -1 1700313833274 "|cpld|m8650d:m8650d"}
{ "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "n_t_35x_m M8650D.v(473) " "Inferred latch for \"n_t_35x_m\" at M8650D.v(473)" {  } { { "M8650D.v" "" { Text "//wsl.localhost/Debian/home/vrs/Verilog/projects/32k-Omnibus/M8650D.v" 473 0 0 } }  } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "Quartus II" 0 -1 1700313833274 "|cpld|m8650d:m8650d"}
{ "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "n_t_36x M8650D.v(466) " "Inferred latch for \"n_t_36x\" at M8650D.v(466)" {  } { { "M8650D.v" "" { Text "//wsl.localhost/Debian/home/vrs/Verilog/projects/32k-Omnibus/M8650D.v" 466 0 0 } }  } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "Quartus II" 0 -1 1700313833274 "|cpld|m8650d:m8650d"}
{ "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "n_t_36x_m M8650D.v(457) " "Inferred latch for \"n_t_36x_m\" at M8650D.v(457)" {  } { { "M8650D.v" "" { Text "//wsl.localhost/Debian/home/vrs/Verilog/projects/32k-Omnibus/M8650D.v" 457 0 0 } }  } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "Quartus II" 0 -1 1700313833274 "|cpld|m8650d:m8650d"}
{ "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "n_t_34x M8650D.v(450) " "Inferred latch for \"n_t_34x\" at M8650D.v(450)" {  } { { "M8650D.v" "" { Text "//wsl.localhost/Debian/home/vrs/Verilog/projects/32k-Omnibus/M8650D.v" 450 0 0 } }  } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "Quartus II" 0 -1 1700313833274 "|cpld|m8650d:m8650d"}
{ "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "n_t_34x_m M8650D.v(441) " "Inferred latch for \"n_t_34x_m\" at M8650D.v(441)" {  } { { "M8650D.v" "" { Text "//wsl.localhost/Debian/home/vrs/Verilog/projects/32k-Omnibus/M8650D.v" 441 0 0 } }  } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "Quartus II" 0 -1 1700313833274 "|cpld|m8650d:m8650d"}
{ "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "n_t_30x M8650D.v(434) " "Inferred latch for \"n_t_30x\" at M8650D.v(434)" {  } { { "M8650D.v" "" { Text "//wsl.localhost/Debian/home/vrs/Verilog/projects/32k-Omnibus/M8650D.v" 434 0 0 } }  } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "Quartus II" 0 -1 1700313833274 "|cpld|m8650d:m8650d"}
{ "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "n_t_30x_m M8650D.v(425) " "Inferred latch for \"n_t_30x_m\" at M8650D.v(425)" {  } { { "M8650D.v" "" { Text "//wsl.localhost/Debian/home/vrs/Verilog/projects/32k-Omnibus/M8650D.v" 425 0 0 } }  } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "Quartus II" 0 -1 1700313833274 "|cpld|m8650d:m8650d"}
{ "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "n_t_75x M8650D.v(397) " "Inferred latch for \"n_t_75x\" at M8650D.v(397)" {  } { { "M8650D.v" "" { Text "//wsl.localhost/Debian/home/vrs/Verilog/projects/32k-Omnibus/M8650D.v" 397 0 0 } }  } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "Quartus II" 0 -1 1700313833274 "|cpld|m8650d:m8650d"}
{ "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "n_t_75x_m M8650D.v(387) " "Inferred latch for \"n_t_75x_m\" at M8650D.v(387)" {  } { { "M8650D.v" "" { Text "//wsl.localhost/Debian/home/vrs/Verilog/projects/32k-Omnibus/M8650D.v" 387 0 0 } }  } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "Quartus II" 0 -1 1700313833274 "|cpld|m8650d:m8650d"}
{ "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "n_t_43x M8650D.v(377) " "Inferred latch for \"n_t_43x\" at M8650D.v(377)" {  } { { "M8650D.v" "" { Text "//wsl.localhost/Debian/home/vrs/Verilog/projects/32k-Omnibus/M8650D.v" 377 0 0 } }  } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "Quartus II" 0 -1 1700313833274 "|cpld|m8650d:m8650d"}
{ "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "n_t_43x_m M8650D.v(367) " "Inferred latch for \"n_t_43x_m\" at M8650D.v(367)" {  } { { "M8650D.v" "" { Text "//wsl.localhost/Debian/home/vrs/Verilog/projects/32k-Omnibus/M8650D.v" 367 0 0 } }  } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "Quartus II" 0 -1 1700313833274 "|cpld|m8650d:m8650d"}
{ "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "ck_pulse M8650D.v(356) " "Inferred latch for \"ck_pulse\" at M8650D.v(356)" {  } { { "M8650D.v" "" { Text "//wsl.localhost/Debian/home/vrs/Verilog/projects/32k-Omnibus/M8650D.v" 356 0 0 } }  } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "Quartus II" 0 -1 1700313833274 "|cpld|m8650d:m8650d"}
{ "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "ck_pulse_m M8650D.v(346) " "Inferred latch for \"ck_pulse_m\" at M8650D.v(346)" {  } { { "M8650D.v" "" { Text "//wsl.localhost/Debian/home/vrs/Verilog/projects/32k-Omnibus/M8650D.v" 346 0 0 } }  } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "Quartus II" 0 -1 1700313833274 "|cpld|m8650d:m8650d"}
{ "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "rx_div M8650D.v(336) " "Inferred latch for \"rx_div\" at M8650D.v(336)" {  } { { "M8650D.v" "" { Text "//wsl.localhost/Debian/home/vrs/Verilog/projects/32k-Omnibus/M8650D.v" 336 0 0 } }  } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "Quartus II" 0 -1 1700313833274 "|cpld|m8650d:m8650d"}
{ "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "rx_div_m M8650D.v(326) " "Inferred latch for \"rx_div_m\" at M8650D.v(326)" {  } { { "M8650D.v" "" { Text "//wsl.localhost/Debian/home/vrs/Verilog/projects/32k-Omnibus/M8650D.v" 326 0 0 } }  } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "Quartus II" 0 -1 1700313833274 "|cpld|m8650d:m8650d"}
{ "Warning" "WCDB_SGATE_CDB_WARN_LATCH_DISABLED" "m8650d:m8650d\|spike_det_l_m " "LATCH primitive \"m8650d:m8650d\|spike_det_l_m\" is permanently disabled" {  } { { "M8650D.v" "" { Text "//wsl.localhost/Debian/home/vrs/Verilog/projects/32k-Omnibus/M8650D.v" 207 -1 0 } }  } 0 14025 "LATCH primitive \"%1!s!\" is permanently disabled" 0 0 "Quartus II" 0 -1 1700313833454 ""}
{ "Warning" "WCDB_SGATE_CDB_WARN_LATCH_DISABLED" "m8650d:m8650d\|p_pulse_l " "LATCH primitive \"m8650d:m8650d\|p_pulse_l\" is permanently disabled" {  } { { "M8650D.v" "" { Text "//wsl.localhost/Debian/home/vrs/Verilog/projects/32k-Omnibus/M8650D.v" 224 -1 0 } }  } 0 14025 "LATCH primitive \"%1!s!\" is permanently disabled" 0 0 "Quartus II" 0 -1 1700313833454 ""}
{ "Warning" "WCDB_SGATE_CDB_WARN_LATCH_DISABLED" "m8650d:m8650d\|ck_pulse " "LATCH primitive \"m8650d:m8650d\|ck_pulse\" is permanently disabled" {  } { { "M8650D.v" "" { Text "//wsl.localhost/Debian/home/vrs/Verilog/projects/32k-Omnibus/M8650D.v" 215 -1 0 } }  } 0 14025 "LATCH primitive \"%1!s!\" is permanently disabled" 0 0 "Quartus II" 0 -1 1700313833454 ""}
{ "Warning" "WCDB_SGATE_CDB_WARN_LATCH_DISABLED" "m8650d:m8650d\|last_unit " "LATCH primitive \"m8650d:m8650d\|last_unit\" is permanently disabled" {  } { { "M8650D.v" "" { Text "//wsl.localhost/Debian/home/vrs/Verilog/projects/32k-Omnibus/M8650D.v" 225 -1 0 } }  } 0 14025 "LATCH primitive \"%1!s!\" is permanently disabled" 0 0 "Quartus II" 0 -1 1700313833454 ""}
{ "Warning" "WCDB_SGATE_CDB_WARN_LATCH_DISABLED" "m8650d:m8650d\|rflg_l " "LATCH primitive \"m8650d:m8650d\|rflg_l\" is permanently disabled" {  } { { "M8650D.v" "" { Text "//wsl.localhost/Debian/home/vrs/Verilog/projects/32k-Omnibus/M8650D.v" 254 -1 0 } }  } 0 14025 "LATCH primitive \"%1!s!\" is permanently disabled" 0 0 "Quartus II" 0 -1 1700313833454 ""}
{ "Warning" "WCDB_SGATE_CDB_WARN_TRIVIAL_USE_LATCH" "m8650d:m8650d\|n_t_40x_m " "LATCH primitive \"m8650d:m8650d\|n_t_40x_m\" is permanently enabled" {  } { { "M8650D.v" "" { Text "//wsl.localhost/Debian/home/vrs/Verilog/projects/32k-Omnibus/M8650D.v" 191 -1 0 } }  } 0 14026 "LATCH primitive \"%1!s!\" is permanently enabled" 0 0 "Quartus II" 0 -1 1700313833454 ""}
{ "Warning" "WCDB_SGATE_CDB_WARN_LATCH_DISABLED" "m8650d:m8650d\|n_t_39x " "LATCH primitive \"m8650d:m8650d\|n_t_39x\" is permanently disabled" {  } { { "M8650D.v" "" { Text "//wsl.localhost/Debian/home/vrs/Verilog/projects/32k-Omnibus/M8650D.v" 229 -1 0 } }  } 0 14025 "LATCH primitive \"%1!s!\" is permanently disabled" 0 0 "Quartus II" 0 -1 1700313833454 ""}
{ "Warning" "WCDB_SGATE_CDB_WARN_LATCH_DISABLED" "m8650d:m8650d\|n_t_38x " "LATCH primitive \"m8650d:m8650d\|n_t_38x\" is permanently disabled" {  } { { "M8650D.v" "" { Text "//wsl.localhost/Debian/home/vrs/Verilog/projects/32k-Omnibus/M8650D.v" 228 -1 0 } }  } 0 14025 "LATCH primitive \"%1!s!\" is permanently disabled" 0 0 "Quartus II" 0 -1 1700313833454 ""}
{ "Warning" "WCDB_SGATE_CDB_WARN_LATCH_DISABLED" "m8650d:m8650d\|n_t_37x " "LATCH primitive \"m8650d:m8650d\|n_t_37x\" is permanently disabled" {  } { { "M8650D.v" "" { Text "//wsl.localhost/Debian/home/vrs/Verilog/projects/32k-Omnibus/M8650D.v" 227 -1 0 } }  } 0 14025 "LATCH primitive \"%1!s!\" is permanently disabled" 0 0 "Quartus II" 0 -1 1700313833454 ""}
{ "Warning" "WCDB_SGATE_CDB_WARN_TRIVIAL_USE_LATCH" "m8650d:m8650d\|n_t_35x_m " "LATCH primitive \"m8650d:m8650d\|n_t_35x_m\" is permanently enabled" {  } { { "M8650D.v" "" { Text "//wsl.localhost/Debian/home/vrs/Verilog/projects/32k-Omnibus/M8650D.v" 186 -1 0 } }  } 0 14026 "LATCH primitive \"%1!s!\" is permanently enabled" 0 0 "Quartus II" 0 -1 1700313833454 ""}
{ "Warning" "WCDB_SGATE_CDB_WARN_LATCH_DISABLED" "m8650d:m8650d\|n_t_36x " "LATCH primitive \"m8650d:m8650d\|n_t_36x\" is permanently disabled" {  } { { "M8650D.v" "" { Text "//wsl.localhost/Debian/home/vrs/Verilog/projects/32k-Omnibus/M8650D.v" 222 -1 0 } }  } 0 14025 "LATCH primitive \"%1!s!\" is permanently disabled" 0 0 "Quartus II" 0 -1 1700313833454 ""}
{ "Warning" "WSGN_CONNECTIVITY_WARNINGS" "1 " "1 hierarchies have connectivity warnings - see the Connectivity Checks report folder" {  } {  } 0 12241 "%1!d! hierarchies have connectivity warnings - see the Connectivity Checks report folder" 0 0 "Quartus II" 0 -1 1700313833556 ""}
{ "Warning" "WMLS_OPT_INSERTED_ALWAYS_DISABLED_TRI_HDR" "" "The following bidir pins have no drivers" { { "Warning" "WMLS_OPT_INSERTED_ALWAYS_DISABLED_TRI" "data03_l " "Bidir \"data03_l\" has no driver" {  } { { "cpld.v" "" { Text "//wsl.localhost/Debian/home/vrs/Verilog/projects/32k-Omnibus/cpld.v" 147 -1 0 } }  } 0 13040 "Bidir \"%1!s!\" has no driver" 0 0 "Quartus II" 0 -1 1700313833660 ""} { "Warning" "WMLS_OPT_INSERTED_ALWAYS_DISABLED_TRI" "data02_l " "Bidir \"data02_l\" has no driver" {  } { { "cpld.v" "" { Text "//wsl.localhost/Debian/home/vrs/Verilog/projects/32k-Omnibus/cpld.v" 148 -1 0 } }  } 0 13040 "Bidir \"%1!s!\" has no driver" 0 0 "Quartus II" 0 -1 1700313833660 ""} { "Warning" "WMLS_OPT_INSERTED_ALWAYS_DISABLED_TRI" "data01_l " "Bidir \"data01_l\" has no driver" {  } { { "cpld.v" "" { Text "//wsl.localhost/Debian/home/vrs/Verilog/projects/32k-Omnibus/cpld.v" 149 -1 0 } }  } 0 13040 "Bidir \"%1!s!\" has no driver" 0 0 "Quartus II" 0 -1 1700313833660 ""} { "Warning" "WMLS_OPT_INSERTED_ALWAYS_DISABLED_TRI" "data00_l " "Bidir \"data00_l\" has no driver" {  } { { "cpld.v" "" { Text "//wsl.localhost/Debian/home/vrs/Verilog/projects/32k-Omnibus/cpld.v" 150 -1 0 } }  } 0 13040 "Bidir \"%1!s!\" has no driver" 0 0 "Quartus II" 0 -1 1700313833660 ""}  } {  } 0 13039 "The following bidir pins have no drivers" 0 0 "Quartus II" 0 -1 1700313833660 ""}
{ "Warning" "WMLS_MLS_STUCK_PIN_HDR" "" "Output pins are stuck at VCC or GND" { { "Warning" "WMLS_MLS_STUCK_PIN" "rxdttl GND " "Pin \"rxdttl\" is stuck at GND" {  } { { "cpld.v" "" { Text "//wsl.localhost/Debian/home/vrs/Verilog/projects/32k-Omnibus/cpld.v" 168 -1 0 } }  } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "Quartus II" 0 -1 1700313833724 "|cpld|rxdttl"}  } {  } 0 13024 "Output pins are stuck at VCC or GND" 0 0 "Quartus II" 0 -1 1700313833724 ""}
{ "Info" "IMTM_MTM_PROMOTE_GLOBAL" "" "Promoted pin-driven signal(s) to global signal" { { "Info" "IMTM_MTM_PROMOTE_GLOBAL_CLOCK" "clk " "Promoted clock signal driven by pin \"clk\" to global clock signal" {  } {  } 0 280014 "Promoted clock signal driven by pin \"%1!s!\" to global clock signal" 0 0 "Quartus II" 0 -1 1700313833764 ""}  } {  } 0 280013 "Promoted pin-driven signal(s) to global signal" 0 0 "Quartus II" 0 -1 1700313833764 ""}
{ "Warning" "WCUT_CUT_UNNECESSARY_INPUT_PIN_HDR" "26 " "Design contains 26 input pin(s) that do not drive logic" { { "Warning" "WCUT_CUT_UNNECESSARY_INPUT_PIN" "pulse_la " "No output dependent on input pin \"pulse_la\"" {  } { { "cpld.v" "" { Text "//wsl.localhost/Debian/home/vrs/Verilog/projects/32k-Omnibus/cpld.v" 88 -1 0 } }  } 0 15610 "No output dependent on input pin \"%1!s!\"" 0 0 "Quartus II" 0 -1 1700313833974 "|cpld|pulse_la"} { "Warning" "WCUT_CUT_UNNECESSARY_INPUT_PIN" "f_set_l " "No output dependent on input pin \"f_set_l\"" {  } { { "cpld.v" "" { Text "//wsl.localhost/Debian/home/vrs/Verilog/projects/32k-Omnibus/cpld.v" 90 -1 0 } }  } 0 15610 "No output dependent on input pin \"%1!s!\"" 0 0 "Quartus II" 0 -1 1700313833974 "|cpld|f_set_l"} { "Warning" "WCUT_CUT_UNNECESSARY_INPUT_PIN" "user_mode_l " "No output dependent on input pin \"user_mode_l\"" {  } { { "cpld.v" "" { Text "//wsl.localhost/Debian/home/vrs/Verilog/projects/32k-Omnibus/cpld.v" 92 -1 0 } }  } 0 15610 "No output dependent on input pin \"%1!s!\"" 0 0 "Quartus II" 0 -1 1700313833974 "|cpld|user_mode_l"} { "Warning" "WCUT_CUT_UNNECESSARY_INPUT_PIN" "d_l " "No output dependent on input pin \"d_l\"" {  } { { "cpld.v" "" { Text "//wsl.localhost/Debian/home/vrs/Verilog/projects/32k-Omnibus/cpld.v" 99 -1 0 } }  } 0 15610 "No output dependent on input pin \"%1!s!\"" 0 0 "Quartus II" 0 -1 1700313833974 "|cpld|d_l"} { "Warning" "WCUT_CUT_UNNECESSARY_INPUT_PIN" "f_l " "No output dependent on input pin \"f_l\"" {  } { { "cpld.v" "" { Text "//wsl.localhost/Debian/home/vrs/Verilog/projects/32k-Omnibus/cpld.v" 101 -1 0 } }  } 0 15610 "No output dependent on input pin \"%1!s!\"" 0 0 "Quartus II" 0 -1 1700313833974 "|cpld|f_l"} { "Warning" "WCUT_CUT_UNNECESSARY_INPUT_PIN" "ir01_l " "No output dependent on input pin \"ir01_l\"" {  } { { "cpld.v" "" { Text "//wsl.localhost/Debian/home/vrs/Verilog/projects/32k-Omnibus/cpld.v" 102 -1 0 } }  } 0 15610 "No output dependent on input pin \"%1!s!\"" 0 0 "Quartus II" 0 -1 1700313833974 "|cpld|ir01_l"} { "Warning" "WCUT_CUT_UNNECESSARY_INPUT_PIN" "ir00_l " "No output dependent on input pin \"ir00_l\"" {  } { { "cpld.v" "" { Text "//wsl.localhost/Debian/home/vrs/Verilog/projects/32k-Omnibus/cpld.v" 103 -1 0 } }  } 0 15610 "No output dependent on input pin \"%1!s!\"" 0 0 "Quartus II" 0 -1 1700313833974 "|cpld|ir00_l"} { "Warning" "WCUT_CUT_UNNECESSARY_INPUT_PIN" "ind2_l " "No output dependent on input pin \"ind2_l\"" {  } { { "cpld.v" "" { Text "//wsl.localhost/Debian/home/vrs/Verilog/projects/32k-Omnibus/cpld.v" 104 -1 0 } }  } 0 15610 "No output dependent on input pin \"%1!s!\"" 0 0 "Quartus II" 0 -1 1700313833974 "|cpld|ind2_l"} { "Warning" "WCUT_CUT_UNNECESSARY_INPUT_PIN" "ind1_l " "No output dependent on input pin \"ind1_l\"" {  } { { "cpld.v" "" { Text "//wsl.localhost/Debian/home/vrs/Verilog/projects/32k-Omnibus/cpld.v" 105 -1 0 } }  } 0 15610 "No output dependent on input pin \"%1!s!\"" 0 0 "Quartus II" 0 -1 1700313833974 "|cpld|ind1_l"} { "Warning" "WCUT_CUT_UNNECESSARY_INPUT_PIN" "cpma_disable_l " "No output dependent on input pin \"cpma_disable_l\"" {  } { { "cpld.v" "" { Text "//wsl.localhost/Debian/home/vrs/Verilog/projects/32k-Omnibus/cpld.v" 106 -1 0 } }  } 0 15610 "No output dependent on input pin \"%1!s!\"" 0 0 "Quartus II" 0 -1 1700313833974 "|cpld|cpma_disable_l"} { "Warning" "WCUT_CUT_UNNECESSARY_INPUT_PIN" "ts3_l " "No output dependent on input pin \"ts3_l\"" {  } { { "cpld.v" "" { Text "//wsl.localhost/Debian/home/vrs/Verilog/projects/32k-Omnibus/cpld.v" 110 -1 0 } }  } 0 15610 "No output dependent on input pin \"%1!s!\"" 0 0 "Quartus II" 0 -1 1700313833974 "|cpld|ts3_l"} { "Warning" "WCUT_CUT_UNNECESSARY_INPUT_PIN" "ts1_l " "No output dependent on input pin \"ts1_l\"" {  } { { "cpld.v" "" { Text "//wsl.localhost/Debian/home/vrs/Verilog/projects/32k-Omnibus/cpld.v" 112 -1 0 } }  } 0 15610 "No output dependent on input pin \"%1!s!\"" 0 0 "Quartus II" 0 -1 1700313833974 "|cpld|ts1_l"} { "Warning" "WCUT_CUT_UNNECESSARY_INPUT_PIN" "tp4 " "No output dependent on input pin \"tp4\"" {  } { { "cpld.v" "" { Text "//wsl.localhost/Debian/home/vrs/Verilog/projects/32k-Omnibus/cpld.v" 113 -1 0 } }  } 0 15610 "No output dependent on input pin \"%1!s!\"" 0 0 "Quartus II" 0 -1 1700313833974 "|cpld|tp4"} { "Warning" "WCUT_CUT_UNNECESSARY_INPUT_PIN" "tp2 " "No output dependent on input pin \"tp2\"" {  } { { "cpld.v" "" { Text "//wsl.localhost/Debian/home/vrs/Verilog/projects/32k-Omnibus/cpld.v" 116 -1 0 } }  } 0 15610 "No output dependent on input pin \"%1!s!\"" 0 0 "Quartus II" 0 -1 1700313833974 "|cpld|tp2"} { "Warning" "WCUT_CUT_UNNECESSARY_INPUT_PIN" "df_enable " "No output dependent on input pin \"df_enable\"" {  } { { "cpld.v" "" { Text "//wsl.localhost/Debian/home/vrs/Verilog/projects/32k-Omnibus/cpld.v" 120 -1 0 } }  } 0 15610 "No output dependent on input pin \"%1!s!\"" 0 0 "Quartus II" 0 -1 1700313833974 "|cpld|df_enable"} { "Warning" "WCUT_CUT_UNNECESSARY_INPUT_PIN" "power_ok " "No output dependent on input pin \"power_ok\"" {  } { { "cpld.v" "" { Text "//wsl.localhost/Debian/home/vrs/Verilog/projects/32k-Omnibus/cpld.v" 124 -1 0 } }  } 0 15610 "No output dependent on input pin \"%1!s!\"" 0 0 "Quartus II" 0 -1 1700313833974 "|cpld|power_ok"} { "Warning" "WCUT_CUT_UNNECESSARY_INPUT_PIN" "run_l " "No output dependent on input pin \"run_l\"" {  } { { "cpld.v" "" { Text "//wsl.localhost/Debian/home/vrs/Verilog/projects/32k-Omnibus/cpld.v" 126 -1 0 } }  } 0 15610 "No output dependent on input pin \"%1!s!\"" 0 0 "Quartus II" 0 -1 1700313833974 "|cpld|run_l"} { "Warning" "WCUT_CUT_UNNECESSARY_INPUT_PIN" "int_in_prog_l " "No output dependent on input pin \"int_in_prog_l\"" {  } { { "cpld.v" "" { Text "//wsl.localhost/Debian/home/vrs/Verilog/projects/32k-Omnibus/cpld.v" 131 -1 0 } }  } 0 15610 "No output dependent on input pin \"%1!s!\"" 0 0 "Quartus II" 0 -1 1700313833974 "|cpld|int_in_prog_l"} { "Warning" "WCUT_CUT_UNNECESSARY_INPUT_PIN" "load_cont_l " "No output dependent on input pin \"load_cont_l\"" {  } { { "cpld.v" "" { Text "//wsl.localhost/Debian/home/vrs/Verilog/projects/32k-Omnibus/cpld.v" 139 -1 0 } }  } 0 15610 "No output dependent on input pin \"%1!s!\"" 0 0 "Quartus II" 0 -1 1700313833974 "|cpld|load_cont_l"} { "Warning" "WCUT_CUT_UNNECESSARY_INPUT_PIN" "md02_l " "No output dependent on input pin \"md02_l\"" {  } { { "cpld.v" "" { Text "//wsl.localhost/Debian/home/vrs/Verilog/projects/32k-Omnibus/cpld.v" 152 -1 0 } }  } 0 15610 "No output dependent on input pin \"%1!s!\"" 0 0 "Quartus II" 0 -1 1700313833974 "|cpld|md02_l"} { "Warning" "WCUT_CUT_UNNECESSARY_INPUT_PIN" "md01_l " "No output dependent on input pin \"md01_l\"" {  } { { "cpld.v" "" { Text "//wsl.localhost/Debian/home/vrs/Verilog/projects/32k-Omnibus/cpld.v" 153 -1 0 } }  } 0 15610 "No output dependent on input pin \"%1!s!\"" 0 0 "Quartus II" 0 -1 1700313833974 "|cpld|md01_l"} { "Warning" "WCUT_CUT_UNNECESSARY_INPUT_PIN" "md00_l " "No output dependent on input pin \"md00_l\"" {  } { { "cpld.v" "" { Text "//wsl.localhost/Debian/home/vrs/Verilog/projects/32k-Omnibus/cpld.v" 154 -1 0 } }  } 0 15610 "No output dependent on input pin \"%1!s!\"" 0 0 "Quartus II" 0 -1 1700313833974 "|cpld|md00_l"} { "Warning" "WCUT_CUT_UNNECESSARY_INPUT_PIN" "ema2_l " "No output dependent on input pin \"ema2_l\"" {  } { { "cpld.v" "" { Text "//wsl.localhost/Debian/home/vrs/Verilog/projects/32k-Omnibus/cpld.v" 156 -1 0 } }  } 0 15610 "No output dependent on input pin \"%1!s!\"" 0 0 "Quartus II" 0 -1 1700313833974 "|cpld|ema2_l"} { "Warning" "WCUT_CUT_UNNECESSARY_INPUT_PIN" "ema1_l " "No output dependent on input pin \"ema1_l\"" {  } { { "cpld.v" "" { Text "//wsl.localhost/Debian/home/vrs/Verilog/projects/32k-Omnibus/cpld.v" 157 -1 0 } }  } 0 15610 "No output dependent on input pin \"%1!s!\"" 0 0 "Quartus II" 0 -1 1700313833974 "|cpld|ema1_l"} { "Warning" "WCUT_CUT_UNNECESSARY_INPUT_PIN" "ema0_l " "No output dependent on input pin \"ema0_l\"" {  } { { "cpld.v" "" { Text "//wsl.localhost/Debian/home/vrs/Verilog/projects/32k-Omnibus/cpld.v" 158 -1 0 } }  } 0 15610 "No output dependent on input pin \"%1!s!\"" 0 0 "Quartus II" 0 -1 1700313833974 "|cpld|ema0_l"} { "Warning" "WCUT_CUT_UNNECESSARY_INPUT_PIN" "key_ctl_l " "No output dependent on input pin \"key_ctl_l\"" {  } { { "cpld.v" "" { Text "//wsl.localhost/Debian/home/vrs/Verilog/projects/32k-Omnibus/cpld.v" 171 -1 0 } }  } 0 15610 "No output dependent on input pin \"%1!s!\"" 0 0 "Quartus II" 0 -1 1700313833974 "|cpld|key_ctl_l"}  } {  } 0 21074 "Design contains %1!d! input pin(s) that do not drive logic" 0 0 "Quartus II" 0 -1 1700313833974 ""}
{ "Info" "ICUT_CUT_TM_SUMMARY" "157 " "Implemented 157 device resources after synthesis - the final resource count might be different" { { "Info" "ICUT_CUT_TM_IPINS" "45 " "Implemented 45 input pins" {  } {  } 0 21058 "Implemented %1!d! input pins" 0 0 "Quartus II" 0 -1 1700313833979 ""} { "Info" "ICUT_CUT_TM_OPINS" "7 " "Implemented 7 output pins" {  } {  } 0 21059 "Implemented %1!d! output pins" 0 0 "Quartus II" 0 -1 1700313833979 ""} { "Info" "ICUT_CUT_TM_BIDIRS" "12 " "Implemented 12 bidirectional pins" {  } {  } 0 21060 "Implemented %1!d! bidirectional pins" 0 0 "Quartus II" 0 -1 1700313833979 ""} { "Info" "ICUT_CUT_TM_MCELLS" "86 " "Implemented 86 macrocells" {  } {  } 0 21063 "Implemented %1!d! macrocells" 0 0 "Quartus II" 0 -1 1700313833979 ""} { "Info" "ICUT_CUT_TM_SEXPS" "7 " "Implemented 7 shareable expanders" {  } {  } 0 21073 "Implemented %1!d! shareable expanders" 0 0 "Quartus II" 0 -1 1700313833979 ""}  } {  } 0 21057 "Implemented %1!d! device resources after synthesis - the final resource count might be different" 0 0 "Quartus II" 0 -1 1700313833979 ""}
{ "Info" "IRDB_WROTE_SUPPRESSED_MSGS" "//wsl.localhost/Debian/home/vrs/Verilog/projects/32k-Omnibus/output_files/cpld.map.smsg " "Generated suppressed messages file //wsl.localhost/Debian/home/vrs/Verilog/projects/32k-Omnibus/output_files/cpld.map.smsg" {  } {  } 0 144001 "Generated suppressed messages file %1!s!" 0 0 "Quartus II" 0 -1 1700313834284 ""}
{ "Info" "IQEXE_ERROR_COUNT" "Analysis & Synthesis 0 s 144 s Quartus II 64-Bit " "Quartus II 64-Bit Analysis & Synthesis was successful. 0 errors, 144 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "4577 " "Peak virtual memory: 4577 megabytes" {  } {  } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Quartus II" 0 -1 1700313834338 ""} { "Info" "IQEXE_END_BANNER_TIME" "Sat Nov 18 05:23:54 2023 " "Processing ended: Sat Nov 18 05:23:54 2023" {  } {  } 0 0 "Processing ended: %1!s!" 0 0 "Quartus II" 0 -1 1700313834338 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:03 " "Elapsed time: 00:00:03" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0 "Quartus II" 0 -1 1700313834338 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:01 " "Total CPU time (on all processors): 00:00:01" {  } {  } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Quartus II" 0 -1 1700313834338 ""}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Quartus II" 0 -1 1700313834338 ""}