{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "Quartus II" 0 -1 1699430706944 ""} { "Info" "IQEXE_START_BANNER_PRODUCT" "Analysis & Synthesis Quartus II 64-Bit " "Running Quartus II 64-Bit Analysis & Synthesis" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition " "Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition" { } { } 0 0 "%1!s!" 0 0 "Quartus II" 0 -1 1699430706944 ""} { "Info" "IQEXE_START_BANNER_TIME" "Wed Nov 08 00:05:06 2023 " "Processing started: Wed Nov 08 00:05:06 2023" { } { } 0 0 "Processing started: %1!s!" 0 0 "Quartus II" 0 -1 1699430706944 ""} } { } 4 0 "Running %2!s! %1!s!" 0 0 "Quartus II" 0 -1 1699430706944 ""} { "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --read_settings_files=on --write_settings_files=off cpld -c cpld " "Command: quartus_map --read_settings_files=on --write_settings_files=off cpld -c cpld" { } { } 0 0 "Command: %1!s!" 0 0 "Quartus II" 0 -1 1699430706944 ""} { "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "m837cc.v 1 1 " "Found 1 design units, including 1 entities, in source file m837cc.v" { { "Info" "ISGN_ENTITY_NAME" "1 m837cc " "Found entity 1: m837cc" { } { { "M837cc.v" "" { Text "//wsl.localhost/Debian/home/vrs/Verilog/projects/32k-Omnibus/M837cc.v" 76 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1699430707495 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1699430707495 ""} { "Warning" "WVRFX_L3_VERI_CONST_EVENT_EXPR" "M8650D.v(346) " "Verilog HDL Event Control warning at M8650D.v(346): event expression is a constant" { } { { "M8650D.v" "" { Text "//wsl.localhost/Debian/home/vrs/Verilog/projects/32k-Omnibus/M8650D.v" 346 0 0 } } } 0 10262 "Verilog HDL Event Control warning at %1!s!: event expression is a constant" 1 0 "Quartus II" 0 -1 1699430707637 ""} { "Warning" "WVRFX_L3_VERI_CONST_EVENT_EXPR" "M8650D.v(490) " "Verilog HDL Event Control warning at M8650D.v(490): event expression is a constant" { } { { "M8650D.v" "" { Text "//wsl.localhost/Debian/home/vrs/Verilog/projects/32k-Omnibus/M8650D.v" 490 0 0 } } } 0 10262 "Verilog HDL Event Control warning at %1!s!: event expression is a constant" 1 0 "Quartus II" 0 -1 1699430707637 ""} { "Warning" "WVRFX_L3_VERI_CONST_EVENT_EXPR" "M8650D.v(510) " "Verilog HDL Event Control warning at M8650D.v(510): event expression is a constant" { } { { "M8650D.v" "" { Text "//wsl.localhost/Debian/home/vrs/Verilog/projects/32k-Omnibus/M8650D.v" 510 0 0 } } } 0 10262 "Verilog HDL Event Control warning at %1!s!: event expression is a constant" 1 0 "Quartus II" 0 -1 1699430707637 ""} { "Warning" "WVRFX_L3_VERI_CONST_EVENT_EXPR" "M8650D.v(702) " "Verilog HDL Event Control warning at M8650D.v(702): event expression is a constant" { } { { "M8650D.v" "" { Text "//wsl.localhost/Debian/home/vrs/Verilog/projects/32k-Omnibus/M8650D.v" 702 0 0 } } } 0 10262 "Verilog HDL Event Control warning at %1!s!: event expression is a constant" 1 0 "Quartus II" 0 -1 1699430707637 ""} { "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "m8650d.v 1 1 " "Found 1 design units, including 1 entities, in source file m8650d.v" { { "Info" "ISGN_ENTITY_NAME" "1 m8650d " "Found entity 1: m8650d" { } { { "M8650D.v" "" { Text "//wsl.localhost/Debian/home/vrs/Verilog/projects/32k-Omnibus/M8650D.v" 76 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1699430707652 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1699430707652 ""} { "Warning" "WVRFX_L2_VERI_INGORE_DANGLING_COMMA" "cpld.v(316) " "Verilog HDL Module Instantiation warning at cpld.v(316): ignored dangling comma in List of Port Connections" { } { { "cpld.v" "" { Text "//wsl.localhost/Debian/home/vrs/Verilog/projects/32k-Omnibus/cpld.v" 316 0 0 } } } 0 10275 "Verilog HDL Module Instantiation warning at %1!s!: ignored dangling comma in List of Port Connections" 0 0 "Quartus II" 0 -1 1699430707747 ""} { "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "cpld.v 1 1 " "Found 1 design units, including 1 entities, in source file cpld.v" { { "Info" "ISGN_ENTITY_NAME" "1 cpld " "Found entity 1: cpld" { } { { "cpld.v" "" { Text "//wsl.localhost/Debian/home/vrs/Verilog/projects/32k-Omnibus/cpld.v" 16 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1699430707762 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1699430707762 ""} { "Info" "ISGN_START_ELABORATION_TOP" "cpld " "Elaborating entity \"cpld\" for the top level hierarchy" { } { } 0 12127 "Elaborating entity \"%1!s!\" for the top level hierarchy" 0 0 "Quartus II" 0 -1 1699430707825 ""} { "Info" "ISGN_START_ELABORATION_HIERARCHY" "m8650d m8650d:m8650d " "Elaborating entity \"m8650d\" for hierarchy \"m8650d:m8650d\"" { } { { "cpld.v" "m8650d" { Text "//wsl.localhost/Debian/home/vrs/Verilog/projects/32k-Omnibus/cpld.v" 316 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1699430707903 ""} { "Warning" "WVRFX_L2_VERI_ALWAYS_ID_HOLDS_VALUE" "rx_div_m M8650D.v(326) " "Verilog HDL Always Construct warning at M8650D.v(326): inferring latch(es) for variable \"rx_div_m\", which holds its previous value in one or more paths through the always construct" { } { { "M8650D.v" "" { Text "//wsl.localhost/Debian/home/vrs/Verilog/projects/32k-Omnibus/M8650D.v" 326 0 0 } } } 0 10240 "Verilog HDL Always Construct warning at %2!s!: inferring latch(es) for variable \"%1!s!\", which holds its previous value in one or more paths through the always construct" 0 0 "Quartus II" 0 -1 1699430707903 "|cpld|m8650d:m8650d"} { "Warning" "WVRFX_L2_VERI_ALWAYS_ID_HOLDS_VALUE" "rx_div M8650D.v(336) " "Verilog HDL Always Construct warning at M8650D.v(336): inferring latch(es) for variable \"rx_div\", which holds its previous value in one or more paths through the always construct" { } { { "M8650D.v" "" { Text "//wsl.localhost/Debian/home/vrs/Verilog/projects/32k-Omnibus/M8650D.v" 336 0 0 } } } 0 10240 "Verilog HDL Always Construct warning at %2!s!: inferring latch(es) for variable \"%1!s!\", which holds its previous value in one or more paths through the always construct" 0 0 "Quartus II" 0 -1 1699430707903 "|cpld|m8650d:m8650d"} { "Warning" "WVRFX_L2_VERI_ALWAYS_ID_HOLDS_VALUE" "ck_pulse_m M8650D.v(346) " "Verilog HDL Always Construct warning at M8650D.v(346): inferring latch(es) for variable \"ck_pulse_m\", which holds its previous value in one or more paths through the always construct" { } { { "M8650D.v" "" { Text "//wsl.localhost/Debian/home/vrs/Verilog/projects/32k-Omnibus/M8650D.v" 346 0 0 } } } 0 10240 "Verilog HDL Always Construct warning at %2!s!: inferring latch(es) for variable \"%1!s!\", which holds its previous value in one or more paths through the always construct" 0 0 "Quartus II" 0 -1 1699430707903 "|cpld|m8650d:m8650d"} { "Warning" "WVRFX_L2_VERI_ALWAYS_ID_HOLDS_VALUE" "ck_pulse M8650D.v(356) " "Verilog HDL Always Construct warning at M8650D.v(356): inferring latch(es) for variable \"ck_pulse\", which holds its previous value in one or more paths through the always construct" { } { { "M8650D.v" "" { Text "//wsl.localhost/Debian/home/vrs/Verilog/projects/32k-Omnibus/M8650D.v" 356 0 0 } } } 0 10240 "Verilog HDL Always Construct warning at %2!s!: inferring latch(es) for variable \"%1!s!\", which holds its previous value in one or more paths through the always construct" 0 0 "Quartus II" 0 -1 1699430707903 "|cpld|m8650d:m8650d"} { "Warning" "WVRFX_L2_VERI_ALWAYS_ID_HOLDS_VALUE" "n_t_43x_m M8650D.v(367) " "Verilog HDL Always Construct warning at M8650D.v(367): inferring latch(es) for variable \"n_t_43x_m\", which holds its previous value in one or more paths through the always construct" { } { { "M8650D.v" "" { Text "//wsl.localhost/Debian/home/vrs/Verilog/projects/32k-Omnibus/M8650D.v" 367 0 0 } } } 0 10240 "Verilog HDL Always Construct warning at %2!s!: inferring latch(es) for variable \"%1!s!\", which holds its previous value in one or more paths through the always construct" 0 0 "Quartus II" 0 -1 1699430707903 "|cpld|m8650d:m8650d"} { "Warning" "WVRFX_L2_VERI_ALWAYS_ID_HOLDS_VALUE" "n_t_43x M8650D.v(377) " "Verilog HDL Always Construct warning at M8650D.v(377): inferring latch(es) for variable \"n_t_43x\", which holds its previous value in one or more paths through the always construct" { } { { "M8650D.v" "" { Text "//wsl.localhost/Debian/home/vrs/Verilog/projects/32k-Omnibus/M8650D.v" 377 0 0 } } } 0 10240 "Verilog HDL Always Construct warning at %2!s!: inferring latch(es) for variable \"%1!s!\", which holds its previous value in one or more paths through the always construct" 0 0 "Quartus II" 0 -1 1699430707903 "|cpld|m8650d:m8650d"} { "Warning" "WVRFX_L2_VERI_ALWAYS_ID_HOLDS_VALUE" "n_t_75x_m M8650D.v(387) " "Verilog HDL Always Construct warning at M8650D.v(387): inferring latch(es) for variable \"n_t_75x_m\", which holds its previous value in one or more paths through the always construct" { } { { "M8650D.v" "" { Text "//wsl.localhost/Debian/home/vrs/Verilog/projects/32k-Omnibus/M8650D.v" 387 0 0 } } } 0 10240 "Verilog HDL Always Construct warning at %2!s!: inferring latch(es) for variable \"%1!s!\", which holds its previous value in one or more paths through the always construct" 0 0 "Quartus II" 0 -1 1699430707903 "|cpld|m8650d:m8650d"} { "Warning" "WVRFX_L2_VERI_ALWAYS_ID_HOLDS_VALUE" "n_t_75x M8650D.v(397) " "Verilog HDL Always Construct warning at M8650D.v(397): inferring latch(es) for variable \"n_t_75x\", which holds its previous value in one or more paths through the always construct" { } { { "M8650D.v" "" { Text "//wsl.localhost/Debian/home/vrs/Verilog/projects/32k-Omnibus/M8650D.v" 397 0 0 } } } 0 10240 "Verilog HDL Always Construct warning at %2!s!: inferring latch(es) for variable \"%1!s!\", which holds its previous value in one or more paths through the always construct" 0 0 "Quartus II" 0 -1 1699430707903 "|cpld|m8650d:m8650d"} { "Warning" "WVRFX_L2_VERI_ALWAYS_ID_HOLDS_VALUE" "n_t_30x_m M8650D.v(425) " "Verilog HDL Always Construct warning at M8650D.v(425): inferring latch(es) for variable \"n_t_30x_m\", which holds its previous value in one or more paths through the always construct" { } { { "M8650D.v" "" { Text "//wsl.localhost/Debian/home/vrs/Verilog/projects/32k-Omnibus/M8650D.v" 425 0 0 } } } 0 10240 "Verilog HDL Always Construct warning at %2!s!: inferring latch(es) for variable \"%1!s!\", which holds its previous value in one or more paths through the always construct" 0 0 "Quartus II" 0 -1 1699430707903 "|cpld|m8650d:m8650d"} { "Warning" "WVRFX_L2_VERI_ALWAYS_ID_HOLDS_VALUE" "n_t_30x M8650D.v(434) " "Verilog HDL Always Construct warning at M8650D.v(434): inferring latch(es) for variable \"n_t_30x\", which holds its previous value in one or more paths through the always construct" { } { { "M8650D.v" "" { Text "//wsl.localhost/Debian/home/vrs/Verilog/projects/32k-Omnibus/M8650D.v" 434 0 0 } } } 0 10240 "Verilog HDL Always Construct warning at %2!s!: inferring latch(es) for variable \"%1!s!\", which holds its previous value in one or more paths through the always construct" 0 0 "Quartus II" 0 -1 1699430707903 "|cpld|m8650d:m8650d"} { "Warning" "WVRFX_L2_VERI_ALWAYS_ID_HOLDS_VALUE" "n_t_34x_m M8650D.v(441) " "Verilog HDL Always Construct warning at M8650D.v(441): inferring latch(es) for variable \"n_t_34x_m\", which holds its previous value in one or more paths through the always construct" { } { { "M8650D.v" "" { Text "//wsl.localhost/Debian/home/vrs/Verilog/projects/32k-Omnibus/M8650D.v" 441 0 0 } } } 0 10240 "Verilog HDL Always Construct warning at %2!s!: inferring latch(es) for variable \"%1!s!\", which holds its previous value in one or more paths through the always construct" 0 0 "Quartus II" 0 -1 1699430707903 "|cpld|m8650d:m8650d"} { "Warning" "WVRFX_L2_VERI_ALWAYS_ID_HOLDS_VALUE" "n_t_34x M8650D.v(450) " "Verilog HDL Always Construct warning at M8650D.v(450): inferring latch(es) for variable \"n_t_34x\", which holds its previous value in one or more paths through the always construct" { } { { "M8650D.v" "" { Text "//wsl.localhost/Debian/home/vrs/Verilog/projects/32k-Omnibus/M8650D.v" 450 0 0 } } } 0 10240 "Verilog HDL Always Construct warning at %2!s!: inferring latch(es) for variable \"%1!s!\", which holds its previous value in one or more paths through the always construct" 0 0 "Quartus II" 0 -1 1699430707903 "|cpld|m8650d:m8650d"} { "Warning" "WVRFX_L2_VERI_ALWAYS_ID_HOLDS_VALUE" "n_t_36x_m M8650D.v(457) " "Verilog HDL Always Construct warning at M8650D.v(457): inferring latch(es) for variable \"n_t_36x_m\", which holds its previous value in one or more paths through the always construct" { } { { "M8650D.v" "" { Text "//wsl.localhost/Debian/home/vrs/Verilog/projects/32k-Omnibus/M8650D.v" 457 0 0 } } } 0 10240 "Verilog HDL Always Construct warning at %2!s!: inferring latch(es) for variable \"%1!s!\", which holds its previous value in one or more paths through the always construct" 0 0 "Quartus II" 0 -1 1699430707903 "|cpld|m8650d:m8650d"} { "Warning" "WVRFX_L2_VERI_ALWAYS_ID_HOLDS_VALUE" "n_t_36x M8650D.v(466) " "Verilog HDL Always Construct warning at M8650D.v(466): inferring latch(es) for variable \"n_t_36x\", which holds its previous value in one or more paths through the always construct" { } { { "M8650D.v" "" { Text "//wsl.localhost/Debian/home/vrs/Verilog/projects/32k-Omnibus/M8650D.v" 466 0 0 } } } 0 10240 "Verilog HDL Always Construct warning at %2!s!: inferring latch(es) for variable \"%1!s!\", which holds its previous value in one or more paths through the always construct" 0 0 "Quartus II" 0 -1 1699430707903 "|cpld|m8650d:m8650d"} { "Warning" "WVRFX_L2_VERI_ALWAYS_ID_HOLDS_VALUE" "n_t_35x_m M8650D.v(473) " "Verilog HDL Always Construct warning at M8650D.v(473): inferring latch(es) for variable \"n_t_35x_m\", which holds its previous value in one or more paths through the always construct" { } { { "M8650D.v" "" { Text "//wsl.localhost/Debian/home/vrs/Verilog/projects/32k-Omnibus/M8650D.v" 473 0 0 } } } 0 10240 "Verilog HDL Always Construct warning at %2!s!: inferring latch(es) for variable \"%1!s!\", which holds its previous value in one or more paths through the always construct" 0 0 "Quartus II" 0 -1 1699430707903 "|cpld|m8650d:m8650d"} { "Warning" "WVRFX_L2_VERI_ALWAYS_ID_HOLDS_VALUE" "n_t_35x M8650D.v(482) " "Verilog HDL Always Construct warning at M8650D.v(482): inferring latch(es) for variable \"n_t_35x\", which holds its previous value in one or more paths through the always construct" { } { { "M8650D.v" "" { Text "//wsl.localhost/Debian/home/vrs/Verilog/projects/32k-Omnibus/M8650D.v" 482 0 0 } } } 0 10240 "Verilog HDL Always Construct warning at %2!s!: inferring latch(es) for variable \"%1!s!\", which holds its previous value in one or more paths through the always construct" 0 0 "Quartus II" 0 -1 1699430707903 "|cpld|m8650d:m8650d"} { "Warning" "WVRFX_L2_VERI_ALWAYS_ID_HOLDS_VALUE" "rx_active_m M8650D.v(490) " "Verilog HDL Always Construct warning at M8650D.v(490): inferring latch(es) for variable \"rx_active_m\", which holds its previous value in one or more paths through the always construct" { } { { "M8650D.v" "" { Text "//wsl.localhost/Debian/home/vrs/Verilog/projects/32k-Omnibus/M8650D.v" 490 0 0 } } } 0 10240 "Verilog HDL Always Construct warning at %2!s!: inferring latch(es) for variable \"%1!s!\", which holds its previous value in one or more paths through the always construct" 0 0 "Quartus II" 0 -1 1699430707903 "|cpld|m8650d:m8650d"} { "Warning" "WVRFX_L2_VERI_ALWAYS_ID_HOLDS_VALUE" "rx_active M8650D.v(500) " "Verilog HDL Always Construct warning at M8650D.v(500): inferring latch(es) for variable \"rx_active\", which holds its previous value in one or more paths through the always construct" { } { { "M8650D.v" "" { Text "//wsl.localhost/Debian/home/vrs/Verilog/projects/32k-Omnibus/M8650D.v" 500 0 0 } } } 0 10240 "Verilog HDL Always Construct warning at %2!s!: inferring latch(es) for variable \"%1!s!\", which holds its previous value in one or more paths through the always construct" 0 0 "Quartus II" 0 -1 1699430707903 "|cpld|m8650d:m8650d"} { "Warning" "WVRFX_L2_VERI_ALWAYS_ID_HOLDS_VALUE" "p_pulse_l_m M8650D.v(510) " "Verilog HDL Always Construct warning at M8650D.v(510): inferring latch(es) for variable \"p_pulse_l_m\", which holds its previous value in one or more paths through the always construct" { } { { "M8650D.v" "" { Text "//wsl.localhost/Debian/home/vrs/Verilog/projects/32k-Omnibus/M8650D.v" 510 0 0 } } } 0 10240 "Verilog HDL Always Construct warning at %2!s!: inferring latch(es) for variable \"%1!s!\", which holds its previous value in one or more paths through the always construct" 0 0 "Quartus II" 0 -1 1699430707903 "|cpld|m8650d:m8650d"} { "Warning" "WVRFX_L2_VERI_ALWAYS_ID_HOLDS_VALUE" "p_pulse_l M8650D.v(520) " "Verilog HDL Always Construct warning at M8650D.v(520): inferring latch(es) for variable \"p_pulse_l\", which holds its previous value in one or more paths through the always construct" { } { { "M8650D.v" "" { Text "//wsl.localhost/Debian/home/vrs/Verilog/projects/32k-Omnibus/M8650D.v" 520 0 0 } } } 0 10240 "Verilog HDL Always Construct warning at %2!s!: inferring latch(es) for variable \"%1!s!\", which holds its previous value in one or more paths through the always construct" 0 0 "Quartus II" 0 -1 1699430707903 "|cpld|m8650d:m8650d"} { "Warning" "WVRFX_L2_VERI_ALWAYS_ID_HOLDS_VALUE" "last_unit_m M8650D.v(531) " "Verilog HDL Always Construct warning at M8650D.v(531): inferring latch(es) for variable \"last_unit_m\", which holds its previous value in one or more paths through the always construct" { } { { "M8650D.v" "" { Text "//wsl.localhost/Debian/home/vrs/Verilog/projects/32k-Omnibus/M8650D.v" 531 0 0 } } } 0 10240 "Verilog HDL Always Construct warning at %2!s!: inferring latch(es) for variable \"%1!s!\", which holds its previous value in one or more paths through the always construct" 0 0 "Quartus II" 0 -1 1699430707903 "|cpld|m8650d:m8650d"} { "Warning" "WVRFX_L2_VERI_ALWAYS_ID_HOLDS_VALUE" "last_unit M8650D.v(541) " "Verilog HDL Always Construct warning at M8650D.v(541): inferring latch(es) for variable \"last_unit\", which holds its previous value in one or more paths through the always construct" { } { { "M8650D.v" "" { Text "//wsl.localhost/Debian/home/vrs/Verilog/projects/32k-Omnibus/M8650D.v" 541 0 0 } } } 0 10240 "Verilog HDL Always Construct warning at %2!s!: inferring latch(es) for variable \"%1!s!\", which holds its previous value in one or more paths through the always construct" 0 0 "Quartus II" 0 -1 1699430707903 "|cpld|m8650d:m8650d"} { "Warning" "WVRFX_L2_VERI_ALWAYS_ID_HOLDS_VALUE" "n_t_88x_m M8650D.v(551) " "Verilog HDL Always Construct warning at M8650D.v(551): inferring latch(es) for variable \"n_t_88x_m\", which holds its previous value in one or more paths through the always construct" { } { { "M8650D.v" "" { Text "//wsl.localhost/Debian/home/vrs/Verilog/projects/32k-Omnibus/M8650D.v" 551 0 0 } } } 0 10240 "Verilog HDL Always Construct warning at %2!s!: inferring latch(es) for variable \"%1!s!\", which holds its previous value in one or more paths through the always construct" 0 0 "Quartus II" 0 -1 1699430707903 "|cpld|m8650d:m8650d"} { "Warning" "WVRFX_L2_VERI_ALWAYS_ID_HOLDS_VALUE" "n_t_88x M8650D.v(561) " "Verilog HDL Always Construct warning at M8650D.v(561): inferring latch(es) for variable \"n_t_88x\", which holds its previous value in one or more paths through the always construct" { } { { "M8650D.v" "" { Text "//wsl.localhost/Debian/home/vrs/Verilog/projects/32k-Omnibus/M8650D.v" 561 0 0 } } } 0 10240 "Verilog HDL Always Construct warning at %2!s!: inferring latch(es) for variable \"%1!s!\", which holds its previous value in one or more paths through the always construct" 0 0 "Quartus II" 0 -1 1699430707903 "|cpld|m8650d:m8650d"} { "Warning" "WVRFX_L2_VERI_ALWAYS_ID_HOLDS_VALUE" "n_t_37x_m M8650D.v(580) " "Verilog HDL Always Construct warning at M8650D.v(580): inferring latch(es) for variable \"n_t_37x_m\", which holds its previous value in one or more paths through the always construct" { } { { "M8650D.v" "" { Text "//wsl.localhost/Debian/home/vrs/Verilog/projects/32k-Omnibus/M8650D.v" 580 0 0 } } } 0 10240 "Verilog HDL Always Construct warning at %2!s!: inferring latch(es) for variable \"%1!s!\", which holds its previous value in one or more paths through the always construct" 0 0 "Quartus II" 0 -1 1699430707903 "|cpld|m8650d:m8650d"} { "Warning" "WVRFX_L2_VERI_ALWAYS_ID_HOLDS_VALUE" "n_t_37x M8650D.v(589) " "Verilog HDL Always Construct warning at M8650D.v(589): inferring latch(es) for variable \"n_t_37x\", which holds its previous value in one or more paths through the always construct" { } { { "M8650D.v" "" { Text "//wsl.localhost/Debian/home/vrs/Verilog/projects/32k-Omnibus/M8650D.v" 589 0 0 } } } 0 10240 "Verilog HDL Always Construct warning at %2!s!: inferring latch(es) for variable \"%1!s!\", which holds its previous value in one or more paths through the always construct" 0 0 "Quartus II" 0 -1 1699430707903 "|cpld|m8650d:m8650d"} { "Warning" "WVRFX_L2_VERI_ALWAYS_ID_HOLDS_VALUE" "n_t_38x_m M8650D.v(596) " "Verilog HDL Always Construct warning at M8650D.v(596): inferring latch(es) for variable \"n_t_38x_m\", which holds its previous value in one or more paths through the always construct" { } { { "M8650D.v" "" { Text "//wsl.localhost/Debian/home/vrs/Verilog/projects/32k-Omnibus/M8650D.v" 596 0 0 } } } 0 10240 "Verilog HDL Always Construct warning at %2!s!: inferring latch(es) for variable \"%1!s!\", which holds its previous value in one or more paths through the always construct" 0 0 "Quartus II" 0 -1 1699430707903 "|cpld|m8650d:m8650d"} { "Warning" "WVRFX_L2_VERI_ALWAYS_ID_HOLDS_VALUE" "n_t_38x M8650D.v(605) " "Verilog HDL Always Construct warning at M8650D.v(605): inferring latch(es) for variable \"n_t_38x\", which holds its previous value in one or more paths through the always construct" { } { { "M8650D.v" "" { Text "//wsl.localhost/Debian/home/vrs/Verilog/projects/32k-Omnibus/M8650D.v" 605 0 0 } } } 0 10240 "Verilog HDL Always Construct warning at %2!s!: inferring latch(es) for variable \"%1!s!\", which holds its previous value in one or more paths through the always construct" 0 0 "Quartus II" 0 -1 1699430707903 "|cpld|m8650d:m8650d"} { "Warning" "WVRFX_L2_VERI_ALWAYS_ID_HOLDS_VALUE" "n_t_39x_m M8650D.v(612) " "Verilog HDL Always Construct warning at M8650D.v(612): inferring latch(es) for variable \"n_t_39x_m\", which holds its previous value in one or more paths through the always construct" { } { { "M8650D.v" "" { Text "//wsl.localhost/Debian/home/vrs/Verilog/projects/32k-Omnibus/M8650D.v" 612 0 0 } } } 0 10240 "Verilog HDL Always Construct warning at %2!s!: inferring latch(es) for variable \"%1!s!\", which holds its previous value in one or more paths through the always construct" 0 0 "Quartus II" 0 -1 1699430707903 "|cpld|m8650d:m8650d"} { "Warning" "WVRFX_L2_VERI_ALWAYS_ID_HOLDS_VALUE" "n_t_39x M8650D.v(621) " "Verilog HDL Always Construct warning at M8650D.v(621): inferring latch(es) for variable \"n_t_39x\", which holds its previous value in one or more paths through the always construct" { } { { "M8650D.v" "" { Text "//wsl.localhost/Debian/home/vrs/Verilog/projects/32k-Omnibus/M8650D.v" 621 0 0 } } } 0 10240 "Verilog HDL Always Construct warning at %2!s!: inferring latch(es) for variable \"%1!s!\", which holds its previous value in one or more paths through the always construct" 0 0 "Quartus II" 0 -1 1699430707903 "|cpld|m8650d:m8650d"} { "Warning" "WVRFX_L2_VERI_ALWAYS_ID_HOLDS_VALUE" "n_t_40x_m M8650D.v(628) " "Verilog HDL Always Construct warning at M8650D.v(628): inferring latch(es) for variable \"n_t_40x_m\", which holds its previous value in one or more paths through the always construct" { } { { "M8650D.v" "" { Text "//wsl.localhost/Debian/home/vrs/Verilog/projects/32k-Omnibus/M8650D.v" 628 0 0 } } } 0 10240 "Verilog HDL Always Construct warning at %2!s!: inferring latch(es) for variable \"%1!s!\", which holds its previous value in one or more paths through the always construct" 0 0 "Quartus II" 0 -1 1699430707903 "|cpld|m8650d:m8650d"} { "Warning" "WVRFX_L2_VERI_ALWAYS_ID_HOLDS_VALUE" "n_t_40x M8650D.v(637) " "Verilog HDL Always Construct warning at M8650D.v(637): inferring latch(es) for variable \"n_t_40x\", which holds its previous value in one or more paths through the always construct" { } { { "M8650D.v" "" { Text "//wsl.localhost/Debian/home/vrs/Verilog/projects/32k-Omnibus/M8650D.v" 637 0 0 } } } 0 10240 "Verilog HDL Always Construct warning at %2!s!: inferring latch(es) for variable \"%1!s!\", which holds its previous value in one or more paths through the always construct" 0 0 "Quartus II" 0 -1 1699430707903 "|cpld|m8650d:m8650d"} { "Warning" "WVRFX_L2_VERI_ALWAYS_ID_HOLDS_VALUE" "tx_div_m M8650D.v(681) " "Verilog HDL Always Construct warning at M8650D.v(681): inferring latch(es) for variable \"tx_div_m\", which holds its previous value in one or more paths through the always construct" { } { { "M8650D.v" "" { Text "//wsl.localhost/Debian/home/vrs/Verilog/projects/32k-Omnibus/M8650D.v" 681 0 0 } } } 0 10240 "Verilog HDL Always Construct warning at %2!s!: inferring latch(es) for variable \"%1!s!\", which holds its previous value in one or more paths through the always construct" 0 0 "Quartus II" 0 -1 1699430707903 "|cpld|m8650d:m8650d"} { "Warning" "WVRFX_L2_VERI_ALWAYS_ID_HOLDS_VALUE" "tx_div M8650D.v(691) " "Verilog HDL Always Construct warning at M8650D.v(691): inferring latch(es) for variable \"tx_div\", which holds its previous value in one or more paths through the always construct" { } { { "M8650D.v" "" { Text "//wsl.localhost/Debian/home/vrs/Verilog/projects/32k-Omnibus/M8650D.v" 691 0 0 } } } 0 10240 "Verilog HDL Always Construct warning at %2!s!: inferring latch(es) for variable \"%1!s!\", which holds its previous value in one or more paths through the always construct" 0 0 "Quartus II" 0 -1 1699430707903 "|cpld|m8650d:m8650d"} { "Warning" "WVRFX_L2_VERI_ALWAYS_ID_HOLDS_VALUE" "spike_det_l_m M8650D.v(702) " "Verilog HDL Always Construct warning at M8650D.v(702): inferring latch(es) for variable \"spike_det_l_m\", which holds its previous value in one or more paths through the always construct" { } { { "M8650D.v" "" { Text "//wsl.localhost/Debian/home/vrs/Verilog/projects/32k-Omnibus/M8650D.v" 702 0 0 } } } 0 10240 "Verilog HDL Always Construct warning at %2!s!: inferring latch(es) for variable \"%1!s!\", which holds its previous value in one or more paths through the always construct" 0 0 "Quartus II" 0 -1 1699430707903 "|cpld|m8650d:m8650d"} { "Warning" "WVRFX_L2_VERI_ALWAYS_ID_HOLDS_VALUE" "spike_det_l M8650D.v(712) " "Verilog HDL Always Construct warning at M8650D.v(712): inferring latch(es) for variable \"spike_det_l\", which holds its previous value in one or more paths through the always construct" { } { { "M8650D.v" "" { Text "//wsl.localhost/Debian/home/vrs/Verilog/projects/32k-Omnibus/M8650D.v" 712 0 0 } } } 0 10240 "Verilog HDL Always Construct warning at %2!s!: inferring latch(es) for variable \"%1!s!\", which holds its previous value in one or more paths through the always construct" 0 0 "Quartus II" 0 -1 1699430707903 "|cpld|m8650d:m8650d"} { "Warning" "WVRFX_L2_VERI_ALWAYS_ID_HOLDS_VALUE" "tx_active_l_m M8650D.v(744) " "Verilog HDL Always Construct warning at M8650D.v(744): inferring latch(es) for variable \"tx_active_l_m\", which holds its previous value in one or more paths through the always construct" { } { { "M8650D.v" "" { Text "//wsl.localhost/Debian/home/vrs/Verilog/projects/32k-Omnibus/M8650D.v" 744 0 0 } } } 0 10240 "Verilog HDL Always Construct warning at %2!s!: inferring latch(es) for variable \"%1!s!\", which holds its previous value in one or more paths through the always construct" 0 0 "Quartus II" 0 -1 1699430707903 "|cpld|m8650d:m8650d"} { "Warning" "WVRFX_L2_VERI_ALWAYS_ID_HOLDS_VALUE" "tx_active_l M8650D.v(754) " "Verilog HDL Always Construct warning at M8650D.v(754): inferring latch(es) for variable \"tx_active_l\", which holds its previous value in one or more paths through the always construct" { } { { "M8650D.v" "" { Text "//wsl.localhost/Debian/home/vrs/Verilog/projects/32k-Omnibus/M8650D.v" 754 0 0 } } } 0 10240 "Verilog HDL Always Construct warning at %2!s!: inferring latch(es) for variable \"%1!s!\", which holds its previous value in one or more paths through the always construct" 0 0 "Quartus II" 0 -1 1699430707903 "|cpld|m8650d:m8650d"} { "Warning" "WVRFX_L2_VERI_ALWAYS_ID_HOLDS_VALUE" "start_l_m M8650D.v(765) " "Verilog HDL Always Construct warning at M8650D.v(765): inferring latch(es) for variable \"start_l_m\", which holds its previous value in one or more paths through the always construct" { } { { "M8650D.v" "" { Text "//wsl.localhost/Debian/home/vrs/Verilog/projects/32k-Omnibus/M8650D.v" 765 0 0 } } } 0 10240 "Verilog HDL Always Construct warning at %2!s!: inferring latch(es) for variable \"%1!s!\", which holds its previous value in one or more paths through the always construct" 0 0 "Quartus II" 0 -1 1699430707903 "|cpld|m8650d:m8650d"} { "Warning" "WVRFX_L2_VERI_ALWAYS_ID_HOLDS_VALUE" "start_l M8650D.v(775) " "Verilog HDL Always Construct warning at M8650D.v(775): inferring latch(es) for variable \"start_l\", which holds its previous value in one or more paths through the always construct" { } { { "M8650D.v" "" { Text "//wsl.localhost/Debian/home/vrs/Verilog/projects/32k-Omnibus/M8650D.v" 775 0 0 } } } 0 10240 "Verilog HDL Always Construct warning at %2!s!: inferring latch(es) for variable \"%1!s!\", which holds its previous value in one or more paths through the always construct" 0 0 "Quartus II" 0 -1 1699430707903 "|cpld|m8650d:m8650d"} { "Warning" "WVRFX_L2_VERI_ALWAYS_ID_HOLDS_VALUE" "gdollar_4_m M8650D.v(788) " "Verilog HDL Always Construct warning at M8650D.v(788): inferring latch(es) for variable \"gdollar_4_m\", which holds its previous value in one or more paths through the always construct" { } { { "M8650D.v" "" { Text "//wsl.localhost/Debian/home/vrs/Verilog/projects/32k-Omnibus/M8650D.v" 788 0 0 } } } 0 10240 "Verilog HDL Always Construct warning at %2!s!: inferring latch(es) for variable \"%1!s!\", which holds its previous value in one or more paths through the always construct" 0 0 "Quartus II" 0 -1 1699430707903 "|cpld|m8650d:m8650d"} { "Warning" "WVRFX_L2_VERI_ALWAYS_ID_HOLDS_VALUE" "gdollar_4 M8650D.v(796) " "Verilog HDL Always Construct warning at M8650D.v(796): inferring latch(es) for variable \"gdollar_4\", which holds its previous value in one or more paths through the always construct" { } { { "M8650D.v" "" { Text "//wsl.localhost/Debian/home/vrs/Verilog/projects/32k-Omnibus/M8650D.v" 796 0 0 } } } 0 10240 "Verilog HDL Always Construct warning at %2!s!: inferring latch(es) for variable \"%1!s!\", which holds its previous value in one or more paths through the always construct" 0 0 "Quartus II" 0 -1 1699430707903 "|cpld|m8650d:m8650d"} { "Warning" "WVRFX_L2_VERI_ALWAYS_ID_HOLDS_VALUE" "gdollar_5_m M8650D.v(804) " "Verilog HDL Always Construct warning at M8650D.v(804): inferring latch(es) for variable \"gdollar_5_m\", which holds its previous value in one or more paths through the always construct" { } { { "M8650D.v" "" { Text "//wsl.localhost/Debian/home/vrs/Verilog/projects/32k-Omnibus/M8650D.v" 804 0 0 } } } 0 10240 "Verilog HDL Always Construct warning at %2!s!: inferring latch(es) for variable \"%1!s!\", which holds its previous value in one or more paths through the always construct" 0 0 "Quartus II" 0 -1 1699430707903 "|cpld|m8650d:m8650d"} { "Warning" "WVRFX_L2_VERI_ALWAYS_ID_HOLDS_VALUE" "gdollar_5 M8650D.v(812) " "Verilog HDL Always Construct warning at M8650D.v(812): inferring latch(es) for variable \"gdollar_5\", which holds its previous value in one or more paths through the always construct" { } { { "M8650D.v" "" { Text "//wsl.localhost/Debian/home/vrs/Verilog/projects/32k-Omnibus/M8650D.v" 812 0 0 } } } 0 10240 "Verilog HDL Always Construct warning at %2!s!: inferring latch(es) for variable \"%1!s!\", which holds its previous value in one or more paths through the always construct" 0 0 "Quartus II" 0 -1 1699430707903 "|cpld|m8650d:m8650d"} { "Warning" "WVRFX_L2_VERI_ALWAYS_ID_HOLDS_VALUE" "gdollar_6_m M8650D.v(820) " "Verilog HDL Always Construct warning at M8650D.v(820): inferring latch(es) for variable \"gdollar_6_m\", which holds its previous value in one or more paths through the always construct" { } { { "M8650D.v" "" { Text "//wsl.localhost/Debian/home/vrs/Verilog/projects/32k-Omnibus/M8650D.v" 820 0 0 } } } 0 10240 "Verilog HDL Always Construct warning at %2!s!: inferring latch(es) for variable \"%1!s!\", which holds its previous value in one or more paths through the always construct" 0 0 "Quartus II" 0 -1 1699430707903 "|cpld|m8650d:m8650d"} { "Warning" "WVRFX_L2_VERI_ALWAYS_ID_HOLDS_VALUE" "gdollar_6 M8650D.v(828) " "Verilog HDL Always Construct warning at M8650D.v(828): inferring latch(es) for variable \"gdollar_6\", which holds its previous value in one or more paths through the always construct" { } { { "M8650D.v" "" { Text "//wsl.localhost/Debian/home/vrs/Verilog/projects/32k-Omnibus/M8650D.v" 828 0 0 } } } 0 10240 "Verilog HDL Always Construct warning at %2!s!: inferring latch(es) for variable \"%1!s!\", which holds its previous value in one or more paths through the always construct" 0 0 "Quartus II" 0 -1 1699430707903 "|cpld|m8650d:m8650d"} { "Warning" "WVRFX_L2_VERI_ALWAYS_ID_HOLDS_VALUE" "n_t_154x_m M8650D.v(836) " "Verilog HDL Always Construct warning at M8650D.v(836): inferring latch(es) for variable \"n_t_154x_m\", which holds its previous value in one or more paths through the always construct" { } { { "M8650D.v" "" { Text "//wsl.localhost/Debian/home/vrs/Verilog/projects/32k-Omnibus/M8650D.v" 836 0 0 } } } 0 10240 "Verilog HDL Always Construct warning at %2!s!: inferring latch(es) for variable \"%1!s!\", which holds its previous value in one or more paths through the always construct" 0 0 "Quartus II" 0 -1 1699430707903 "|cpld|m8650d:m8650d"} { "Warning" "WVRFX_L2_VERI_ALWAYS_ID_HOLDS_VALUE" "n_t_154x M8650D.v(844) " "Verilog HDL Always Construct warning at M8650D.v(844): inferring latch(es) for variable \"n_t_154x\", which holds its previous value in one or more paths through the always construct" { } { { "M8650D.v" "" { Text "//wsl.localhost/Debian/home/vrs/Verilog/projects/32k-Omnibus/M8650D.v" 844 0 0 } } } 0 10240 "Verilog HDL Always Construct warning at %2!s!: inferring latch(es) for variable \"%1!s!\", which holds its previous value in one or more paths through the always construct" 0 0 "Quartus II" 0 -1 1699430707903 "|cpld|m8650d:m8650d"} { "Warning" "WVRFX_L2_VERI_ALWAYS_ID_HOLDS_VALUE" "n_t_146x_m M8650D.v(876) " "Verilog HDL Always Construct warning at M8650D.v(876): inferring latch(es) for variable \"n_t_146x_m\", which holds its previous value in one or more paths through the always construct" { } { { "M8650D.v" "" { Text "//wsl.localhost/Debian/home/vrs/Verilog/projects/32k-Omnibus/M8650D.v" 876 0 0 } } } 0 10240 "Verilog HDL Always Construct warning at %2!s!: inferring latch(es) for variable \"%1!s!\", which holds its previous value in one or more paths through the always construct" 0 0 "Quartus II" 0 -1 1699430707903 "|cpld|m8650d:m8650d"} { "Warning" "WVRFX_L2_VERI_ALWAYS_ID_HOLDS_VALUE" "n_t_146x M8650D.v(885) " "Verilog HDL Always Construct warning at M8650D.v(885): inferring latch(es) for variable \"n_t_146x\", which holds its previous value in one or more paths through the always construct" { } { { "M8650D.v" "" { Text "//wsl.localhost/Debian/home/vrs/Verilog/projects/32k-Omnibus/M8650D.v" 885 0 0 } } } 0 10240 "Verilog HDL Always Construct warning at %2!s!: inferring latch(es) for variable \"%1!s!\", which holds its previous value in one or more paths through the always construct" 0 0 "Quartus II" 0 -1 1699430707903 "|cpld|m8650d:m8650d"} { "Warning" "WVRFX_L2_VERI_ALWAYS_ID_HOLDS_VALUE" "gdollar_7_m M8650D.v(892) " "Verilog HDL Always Construct warning at M8650D.v(892): inferring latch(es) for variable \"gdollar_7_m\", which holds its previous value in one or more paths through the always construct" { } { { "M8650D.v" "" { Text "//wsl.localhost/Debian/home/vrs/Verilog/projects/32k-Omnibus/M8650D.v" 892 0 0 } } } 0 10240 "Verilog HDL Always Construct warning at %2!s!: inferring latch(es) for variable \"%1!s!\", which holds its previous value in one or more paths through the always construct" 0 0 "Quartus II" 0 -1 1699430707903 "|cpld|m8650d:m8650d"} { "Warning" "WVRFX_L2_VERI_ALWAYS_ID_HOLDS_VALUE" "gdollar_7 M8650D.v(901) " "Verilog HDL Always Construct warning at M8650D.v(901): inferring latch(es) for variable \"gdollar_7\", which holds its previous value in one or more paths through the always construct" { } { { "M8650D.v" "" { Text "//wsl.localhost/Debian/home/vrs/Verilog/projects/32k-Omnibus/M8650D.v" 901 0 0 } } } 0 10240 "Verilog HDL Always Construct warning at %2!s!: inferring latch(es) for variable \"%1!s!\", which holds its previous value in one or more paths through the always construct" 0 0 "Quartus II" 0 -1 1699430707903 "|cpld|m8650d:m8650d"} { "Warning" "WVRFX_L2_VERI_ALWAYS_ID_HOLDS_VALUE" "n_t_119x_m M8650D.v(908) " "Verilog HDL Always Construct warning at M8650D.v(908): inferring latch(es) for variable \"n_t_119x_m\", which holds its previous value in one or more paths through the always construct" { } { { "M8650D.v" "" { Text "//wsl.localhost/Debian/home/vrs/Verilog/projects/32k-Omnibus/M8650D.v" 908 0 0 } } } 0 10240 "Verilog HDL Always Construct warning at %2!s!: inferring latch(es) for variable \"%1!s!\", which holds its previous value in one or more paths through the always construct" 0 0 "Quartus II" 0 -1 1699430707903 "|cpld|m8650d:m8650d"} { "Warning" "WVRFX_L2_VERI_ALWAYS_ID_HOLDS_VALUE" "n_t_119x M8650D.v(917) " "Verilog HDL Always Construct warning at M8650D.v(917): inferring latch(es) for variable \"n_t_119x\", which holds its previous value in one or more paths through the always construct" { } { { "M8650D.v" "" { Text "//wsl.localhost/Debian/home/vrs/Verilog/projects/32k-Omnibus/M8650D.v" 917 0 0 } } } 0 10240 "Verilog HDL Always Construct warning at %2!s!: inferring latch(es) for variable \"%1!s!\", which holds its previous value in one or more paths through the always construct" 0 0 "Quartus II" 0 -1 1699430707903 "|cpld|m8650d:m8650d"} { "Warning" "WVRFX_L2_VERI_ALWAYS_ID_HOLDS_VALUE" "gdollar_8_m M8650D.v(924) " "Verilog HDL Always Construct warning at M8650D.v(924): inferring latch(es) for variable \"gdollar_8_m\", which holds its previous value in one or more paths through the always construct" { } { { "M8650D.v" "" { Text "//wsl.localhost/Debian/home/vrs/Verilog/projects/32k-Omnibus/M8650D.v" 924 0 0 } } } 0 10240 "Verilog HDL Always Construct warning at %2!s!: inferring latch(es) for variable \"%1!s!\", which holds its previous value in one or more paths through the always construct" 0 0 "Quartus II" 0 -1 1699430707903 "|cpld|m8650d:m8650d"} { "Warning" "WVRFX_L2_VERI_ALWAYS_ID_HOLDS_VALUE" "gdollar_8 M8650D.v(933) " "Verilog HDL Always Construct warning at M8650D.v(933): inferring latch(es) for variable \"gdollar_8\", which holds its previous value in one or more paths through the always construct" { } { { "M8650D.v" "" { Text "//wsl.localhost/Debian/home/vrs/Verilog/projects/32k-Omnibus/M8650D.v" 933 0 0 } } } 0 10240 "Verilog HDL Always Construct warning at %2!s!: inferring latch(es) for variable \"%1!s!\", which holds its previous value in one or more paths through the always construct" 0 0 "Quartus II" 0 -1 1699430707903 "|cpld|m8650d:m8650d"} { "Warning" "WVRFX_L2_VERI_ALWAYS_ID_HOLDS_VALUE" "n_t_60x_m M8650D.v(950) " "Verilog HDL Always Construct warning at M8650D.v(950): inferring latch(es) for variable \"n_t_60x_m\", which holds its previous value in one or more paths through the always construct" { } { { "M8650D.v" "" { Text "//wsl.localhost/Debian/home/vrs/Verilog/projects/32k-Omnibus/M8650D.v" 950 0 0 } } } 0 10240 "Verilog HDL Always Construct warning at %2!s!: inferring latch(es) for variable \"%1!s!\", which holds its previous value in one or more paths through the always construct" 0 0 "Quartus II" 0 -1 1699430707903 "|cpld|m8650d:m8650d"} { "Warning" "WVRFX_L2_VERI_ALWAYS_ID_HOLDS_VALUE" "n_t_60x M8650D.v(959) " "Verilog HDL Always Construct warning at M8650D.v(959): inferring latch(es) for variable \"n_t_60x\", which holds its previous value in one or more paths through the always construct" { } { { "M8650D.v" "" { Text "//wsl.localhost/Debian/home/vrs/Verilog/projects/32k-Omnibus/M8650D.v" 959 0 0 } } } 0 10240 "Verilog HDL Always Construct warning at %2!s!: inferring latch(es) for variable \"%1!s!\", which holds its previous value in one or more paths through the always construct" 0 0 "Quartus II" 0 -1 1699430707903 "|cpld|m8650d:m8650d"} { "Warning" "WVRFX_L2_VERI_ALWAYS_ID_HOLDS_VALUE" "n_t_62x_m M8650D.v(966) " "Verilog HDL Always Construct warning at M8650D.v(966): inferring latch(es) for variable \"n_t_62x_m\", which holds its previous value in one or more paths through the always construct" { } { { "M8650D.v" "" { Text "//wsl.localhost/Debian/home/vrs/Verilog/projects/32k-Omnibus/M8650D.v" 966 0 0 } } } 0 10240 "Verilog HDL Always Construct warning at %2!s!: inferring latch(es) for variable \"%1!s!\", which holds its previous value in one or more paths through the always construct" 0 0 "Quartus II" 0 -1 1699430707903 "|cpld|m8650d:m8650d"} { "Warning" "WVRFX_L2_VERI_ALWAYS_ID_HOLDS_VALUE" "n_t_62x M8650D.v(975) " "Verilog HDL Always Construct warning at M8650D.v(975): inferring latch(es) for variable \"n_t_62x\", which holds its previous value in one or more paths through the always construct" { } { { "M8650D.v" "" { Text "//wsl.localhost/Debian/home/vrs/Verilog/projects/32k-Omnibus/M8650D.v" 975 0 0 } } } 0 10240 "Verilog HDL Always Construct warning at %2!s!: inferring latch(es) for variable \"%1!s!\", which holds its previous value in one or more paths through the always construct" 0 0 "Quartus II" 0 -1 1699430707903 "|cpld|m8650d:m8650d"} { "Warning" "WVRFX_L2_VERI_ALWAYS_ID_HOLDS_VALUE" "n_t_56x_m M8650D.v(982) " "Verilog HDL Always Construct warning at M8650D.v(982): inferring latch(es) for variable \"n_t_56x_m\", which holds its previous value in one or more paths through the always construct" { } { { "M8650D.v" "" { Text "//wsl.localhost/Debian/home/vrs/Verilog/projects/32k-Omnibus/M8650D.v" 982 0 0 } } } 0 10240 "Verilog HDL Always Construct warning at %2!s!: inferring latch(es) for variable \"%1!s!\", which holds its previous value in one or more paths through the always construct" 0 0 "Quartus II" 0 -1 1699430707903 "|cpld|m8650d:m8650d"} { "Warning" "WVRFX_L2_VERI_ALWAYS_ID_HOLDS_VALUE" "n_t_56x M8650D.v(991) " "Verilog HDL Always Construct warning at M8650D.v(991): inferring latch(es) for variable \"n_t_56x\", which holds its previous value in one or more paths through the always construct" { } { { "M8650D.v" "" { Text "//wsl.localhost/Debian/home/vrs/Verilog/projects/32k-Omnibus/M8650D.v" 991 0 0 } } } 0 10240 "Verilog HDL Always Construct warning at %2!s!: inferring latch(es) for variable \"%1!s!\", which holds its previous value in one or more paths through the always construct" 0 0 "Quartus II" 0 -1 1699430707903 "|cpld|m8650d:m8650d"} { "Warning" "WVRFX_L2_VERI_ALWAYS_ID_HOLDS_VALUE" "n_t_61x_m M8650D.v(998) " "Verilog HDL Always Construct warning at M8650D.v(998): inferring latch(es) for variable \"n_t_61x_m\", which holds its previous value in one or more paths through the always construct" { } { { "M8650D.v" "" { Text "//wsl.localhost/Debian/home/vrs/Verilog/projects/32k-Omnibus/M8650D.v" 998 0 0 } } } 0 10240 "Verilog HDL Always Construct warning at %2!s!: inferring latch(es) for variable \"%1!s!\", which holds its previous value in one or more paths through the always construct" 0 0 "Quartus II" 0 -1 1699430707903 "|cpld|m8650d:m8650d"} { "Warning" "WVRFX_L2_VERI_ALWAYS_ID_HOLDS_VALUE" "n_t_61x M8650D.v(1007) " "Verilog HDL Always Construct warning at M8650D.v(1007): inferring latch(es) for variable \"n_t_61x\", which holds its previous value in one or more paths through the always construct" { } { { "M8650D.v" "" { Text "//wsl.localhost/Debian/home/vrs/Verilog/projects/32k-Omnibus/M8650D.v" 1007 0 0 } } } 0 10240 "Verilog HDL Always Construct warning at %2!s!: inferring latch(es) for variable \"%1!s!\", which holds its previous value in one or more paths through the always construct" 0 0 "Quartus II" 0 -1 1699430707903 "|cpld|m8650d:m8650d"} { "Warning" "WVRFX_L2_VERI_ALWAYS_ID_HOLDS_VALUE" "line_m M8650D.v(1015) " "Verilog HDL Always Construct warning at M8650D.v(1015): inferring latch(es) for variable \"line_m\", which holds its previous value in one or more paths through the always construct" { } { { "M8650D.v" "" { Text "//wsl.localhost/Debian/home/vrs/Verilog/projects/32k-Omnibus/M8650D.v" 1015 0 0 } } } 0 10240 "Verilog HDL Always Construct warning at %2!s!: inferring latch(es) for variable \"%1!s!\", which holds its previous value in one or more paths through the always construct" 0 0 "Quartus II" 0 -1 1699430707903 "|cpld|m8650d:m8650d"} { "Warning" "WVRFX_L2_VERI_ALWAYS_ID_HOLDS_VALUE" "line M8650D.v(1025) " "Verilog HDL Always Construct warning at M8650D.v(1025): inferring latch(es) for variable \"line\", which holds its previous value in one or more paths through the always construct" { } { { "M8650D.v" "" { Text "//wsl.localhost/Debian/home/vrs/Verilog/projects/32k-Omnibus/M8650D.v" 1025 0 0 } } } 0 10240 "Verilog HDL Always Construct warning at %2!s!: inferring latch(es) for variable \"%1!s!\", which holds its previous value in one or more paths through the always construct" 0 0 "Quartus II" 0 -1 1699430707919 "|cpld|m8650d:m8650d"} { "Warning" "WVRFX_L2_VERI_ALWAYS_ID_HOLDS_VALUE" "enab_m M8650D.v(1036) " "Verilog HDL Always Construct warning at M8650D.v(1036): inferring latch(es) for variable \"enab_m\", which holds its previous value in one or more paths through the always construct" { } { { "M8650D.v" "" { Text "//wsl.localhost/Debian/home/vrs/Verilog/projects/32k-Omnibus/M8650D.v" 1036 0 0 } } } 0 10240 "Verilog HDL Always Construct warning at %2!s!: inferring latch(es) for variable \"%1!s!\", which holds its previous value in one or more paths through the always construct" 0 0 "Quartus II" 0 -1 1699430707919 "|cpld|m8650d:m8650d"} { "Warning" "WVRFX_L2_VERI_ALWAYS_ID_HOLDS_VALUE" "enab M8650D.v(1046) " "Verilog HDL Always Construct warning at M8650D.v(1046): inferring latch(es) for variable \"enab\", which holds its previous value in one or more paths through the always construct" { } { { "M8650D.v" "" { Text "//wsl.localhost/Debian/home/vrs/Verilog/projects/32k-Omnibus/M8650D.v" 1046 0 0 } } } 0 10240 "Verilog HDL Always Construct warning at %2!s!: inferring latch(es) for variable \"%1!s!\", which holds its previous value in one or more paths through the always construct" 0 0 "Quartus II" 0 -1 1699430707919 "|cpld|m8650d:m8650d"} { "Warning" "WVRFX_L2_VERI_ALWAYS_ID_HOLDS_VALUE" "n_t_63x_m M8650D.v(1066) " "Verilog HDL Always Construct warning at M8650D.v(1066): inferring latch(es) for variable \"n_t_63x_m\", which holds its previous value in one or more paths through the always construct" { } { { "M8650D.v" "" { Text "//wsl.localhost/Debian/home/vrs/Verilog/projects/32k-Omnibus/M8650D.v" 1066 0 0 } } } 0 10240 "Verilog HDL Always Construct warning at %2!s!: inferring latch(es) for variable \"%1!s!\", which holds its previous value in one or more paths through the always construct" 0 0 "Quartus II" 0 -1 1699430707919 "|cpld|m8650d:m8650d"} { "Warning" "WVRFX_L2_VERI_ALWAYS_ID_HOLDS_VALUE" "n_t_63x M8650D.v(1075) " "Verilog HDL Always Construct warning at M8650D.v(1075): inferring latch(es) for variable \"n_t_63x\", which holds its previous value in one or more paths through the always construct" { } { { "M8650D.v" "" { Text "//wsl.localhost/Debian/home/vrs/Verilog/projects/32k-Omnibus/M8650D.v" 1075 0 0 } } } 0 10240 "Verilog HDL Always Construct warning at %2!s!: inferring latch(es) for variable \"%1!s!\", which holds its previous value in one or more paths through the always construct" 0 0 "Quartus II" 0 -1 1699430707919 "|cpld|m8650d:m8650d"} { "Warning" "WVRFX_L2_VERI_ALWAYS_ID_HOLDS_VALUE" "n_t_65x_m M8650D.v(1082) " "Verilog HDL Always Construct warning at M8650D.v(1082): inferring latch(es) for variable \"n_t_65x_m\", which holds its previous value in one or more paths through the always construct" { } { { "M8650D.v" "" { Text "//wsl.localhost/Debian/home/vrs/Verilog/projects/32k-Omnibus/M8650D.v" 1082 0 0 } } } 0 10240 "Verilog HDL Always Construct warning at %2!s!: inferring latch(es) for variable \"%1!s!\", which holds its previous value in one or more paths through the always construct" 0 0 "Quartus II" 0 -1 1699430707919 "|cpld|m8650d:m8650d"} { "Warning" "WVRFX_L2_VERI_ALWAYS_ID_HOLDS_VALUE" "n_t_65x M8650D.v(1091) " "Verilog HDL Always Construct warning at M8650D.v(1091): inferring latch(es) for variable \"n_t_65x\", which holds its previous value in one or more paths through the always construct" { } { { "M8650D.v" "" { Text "//wsl.localhost/Debian/home/vrs/Verilog/projects/32k-Omnibus/M8650D.v" 1091 0 0 } } } 0 10240 "Verilog HDL Always Construct warning at %2!s!: inferring latch(es) for variable \"%1!s!\", which holds its previous value in one or more paths through the always construct" 0 0 "Quartus II" 0 -1 1699430707919 "|cpld|m8650d:m8650d"} { "Warning" "WVRFX_L2_VERI_ALWAYS_ID_HOLDS_VALUE" "n_t_66x_m M8650D.v(1098) " "Verilog HDL Always Construct warning at M8650D.v(1098): inferring latch(es) for variable \"n_t_66x_m\", which holds its previous value in one or more paths through the always construct" { } { { "M8650D.v" "" { Text "//wsl.localhost/Debian/home/vrs/Verilog/projects/32k-Omnibus/M8650D.v" 1098 0 0 } } } 0 10240 "Verilog HDL Always Construct warning at %2!s!: inferring latch(es) for variable \"%1!s!\", which holds its previous value in one or more paths through the always construct" 0 0 "Quartus II" 0 -1 1699430707919 "|cpld|m8650d:m8650d"} { "Warning" "WVRFX_L2_VERI_ALWAYS_ID_HOLDS_VALUE" "n_t_66x M8650D.v(1107) " "Verilog HDL Always Construct warning at M8650D.v(1107): inferring latch(es) for variable \"n_t_66x\", which holds its previous value in one or more paths through the always construct" { } { { "M8650D.v" "" { Text "//wsl.localhost/Debian/home/vrs/Verilog/projects/32k-Omnibus/M8650D.v" 1107 0 0 } } } 0 10240 "Verilog HDL Always Construct warning at %2!s!: inferring latch(es) for variable \"%1!s!\", which holds its previous value in one or more paths through the always construct" 0 0 "Quartus II" 0 -1 1699430707919 "|cpld|m8650d:m8650d"} { "Warning" "WVRFX_L2_VERI_ALWAYS_ID_HOLDS_VALUE" "tx_data_m M8650D.v(1114) " "Verilog HDL Always Construct warning at M8650D.v(1114): inferring latch(es) for variable \"tx_data_m\", which holds its previous value in one or more paths through the always construct" { } { { "M8650D.v" "" { Text "//wsl.localhost/Debian/home/vrs/Verilog/projects/32k-Omnibus/M8650D.v" 1114 0 0 } } } 0 10240 "Verilog HDL Always Construct warning at %2!s!: inferring latch(es) for variable \"%1!s!\", which holds its previous value in one or more paths through the always construct" 0 0 "Quartus II" 0 -1 1699430707919 "|cpld|m8650d:m8650d"} { "Warning" "WVRFX_L2_VERI_ALWAYS_ID_HOLDS_VALUE" "tx_data M8650D.v(1123) " "Verilog HDL Always Construct warning at M8650D.v(1123): inferring latch(es) for variable \"tx_data\", which holds its previous value in one or more paths through the always construct" { } { { "M8650D.v" "" { Text "//wsl.localhost/Debian/home/vrs/Verilog/projects/32k-Omnibus/M8650D.v" 1123 0 0 } } } 0 10240 "Verilog HDL Always Construct warning at %2!s!: inferring latch(es) for variable \"%1!s!\", which holds its previous value in one or more paths through the always construct" 0 0 "Quartus II" 0 -1 1699430707919 "|cpld|m8650d:m8650d"} { "Warning" "WVRFX_L2_VERI_ALWAYS_ID_HOLDS_VALUE" "tflg_l_m M8650D.v(1150) " "Verilog HDL Always Construct warning at M8650D.v(1150): inferring latch(es) for variable \"tflg_l_m\", which holds its previous value in one or more paths through the always construct" { } { { "M8650D.v" "" { Text "//wsl.localhost/Debian/home/vrs/Verilog/projects/32k-Omnibus/M8650D.v" 1150 0 0 } } } 0 10240 "Verilog HDL Always Construct warning at %2!s!: inferring latch(es) for variable \"%1!s!\", which holds its previous value in one or more paths through the always construct" 0 0 "Quartus II" 0 -1 1699430707919 "|cpld|m8650d:m8650d"} { "Warning" "WVRFX_L2_VERI_ALWAYS_ID_HOLDS_VALUE" "tflg_l M8650D.v(1160) " "Verilog HDL Always Construct warning at M8650D.v(1160): inferring latch(es) for variable \"tflg_l\", which holds its previous value in one or more paths through the always construct" { } { { "M8650D.v" "" { Text "//wsl.localhost/Debian/home/vrs/Verilog/projects/32k-Omnibus/M8650D.v" 1160 0 0 } } } 0 10240 "Verilog HDL Always Construct warning at %2!s!: inferring latch(es) for variable \"%1!s!\", which holds its previous value in one or more paths through the always construct" 0 0 "Quartus II" 0 -1 1699430707919 "|cpld|m8650d:m8650d"} { "Warning" "WVRFX_L2_VERI_ALWAYS_ID_HOLDS_VALUE" "int_enab_l_m M8650D.v(1170) " "Verilog HDL Always Construct warning at M8650D.v(1170): inferring latch(es) for variable \"int_enab_l_m\", which holds its previous value in one or more paths through the always construct" { } { { "M8650D.v" "" { Text "//wsl.localhost/Debian/home/vrs/Verilog/projects/32k-Omnibus/M8650D.v" 1170 0 0 } } } 0 10240 "Verilog HDL Always Construct warning at %2!s!: inferring latch(es) for variable \"%1!s!\", which holds its previous value in one or more paths through the always construct" 0 0 "Quartus II" 0 -1 1699430707919 "|cpld|m8650d:m8650d"} { "Warning" "WVRFX_L2_VERI_ALWAYS_ID_HOLDS_VALUE" "int_enab_l M8650D.v(1180) " "Verilog HDL Always Construct warning at M8650D.v(1180): inferring latch(es) for variable \"int_enab_l\", which holds its previous value in one or more paths through the always construct" { } { { "M8650D.v" "" { Text "//wsl.localhost/Debian/home/vrs/Verilog/projects/32k-Omnibus/M8650D.v" 1180 0 0 } } } 0 10240 "Verilog HDL Always Construct warning at %2!s!: inferring latch(es) for variable \"%1!s!\", which holds its previous value in one or more paths through the always construct" 0 0 "Quartus II" 0 -1 1699430707919 "|cpld|m8650d:m8650d"} { "Warning" "WVRFX_L2_VERI_ALWAYS_ID_HOLDS_VALUE" "rflg_l_m M8650D.v(1245) " "Verilog HDL Always Construct warning at M8650D.v(1245): inferring latch(es) for variable \"rflg_l_m\", which holds its previous value in one or more paths through the always construct" { } { { "M8650D.v" "" { Text "//wsl.localhost/Debian/home/vrs/Verilog/projects/32k-Omnibus/M8650D.v" 1245 0 0 } } } 0 10240 "Verilog HDL Always Construct warning at %2!s!: inferring latch(es) for variable \"%1!s!\", which holds its previous value in one or more paths through the always construct" 0 0 "Quartus II" 0 -1 1699430707919 "|cpld|m8650d:m8650d"} { "Warning" "WVRFX_L2_VERI_ALWAYS_ID_HOLDS_VALUE" "rflg_l M8650D.v(1255) " "Verilog HDL Always Construct warning at M8650D.v(1255): inferring latch(es) for variable \"rflg_l\", which holds its previous value in one or more paths through the always construct" { } { { "M8650D.v" "" { Text "//wsl.localhost/Debian/home/vrs/Verilog/projects/32k-Omnibus/M8650D.v" 1255 0 0 } } } 0 10240 "Verilog HDL Always Construct warning at %2!s!: inferring latch(es) for variable \"%1!s!\", which holds its previous value in one or more paths through the always construct" 0 0 "Quartus II" 0 -1 1699430707919 "|cpld|m8650d:m8650d"} { "Warning" "WVRFX_L2_VERI_ALWAYS_ID_HOLDS_VALUE" "r_run_l_m M8650D.v(1265) " "Verilog HDL Always Construct warning at M8650D.v(1265): inferring latch(es) for variable \"r_run_l_m\", which holds its previous value in one or more paths through the always construct" { } { { "M8650D.v" "" { Text "//wsl.localhost/Debian/home/vrs/Verilog/projects/32k-Omnibus/M8650D.v" 1265 0 0 } } } 0 10240 "Verilog HDL Always Construct warning at %2!s!: inferring latch(es) for variable \"%1!s!\", which holds its previous value in one or more paths through the always construct" 0 0 "Quartus II" 0 -1 1699430707919 "|cpld|m8650d:m8650d"} { "Warning" "WVRFX_L2_VERI_ALWAYS_ID_HOLDS_VALUE" "r_run_l M8650D.v(1275) " "Verilog HDL Always Construct warning at M8650D.v(1275): inferring latch(es) for variable \"r_run_l\", which holds its previous value in one or more paths through the always construct" { } { { "M8650D.v" "" { Text "//wsl.localhost/Debian/home/vrs/Verilog/projects/32k-Omnibus/M8650D.v" 1275 0 0 } } } 0 10240 "Verilog HDL Always Construct warning at %2!s!: inferring latch(es) for variable \"%1!s!\", which holds its previous value in one or more paths through the always construct" 0 0 "Quartus II" 0 -1 1699430707919 "|cpld|m8650d:m8650d"} { "Warning" "WVRFX_L2_VDB_DRIVERLESS_OUTPUT_PORT" "n_t_77x M8650D.v(88) " "Output port \"n_t_77x\" at M8650D.v(88) has no driver" { } { { "M8650D.v" "" { Text "//wsl.localhost/Debian/home/vrs/Verilog/projects/32k-Omnibus/M8650D.v" 88 0 0 } } } 0 10034 "Output port \"%1!s!\" at %2!s! has no driver" 0 0 "Quartus II" 0 -1 1699430707919 "|cpld|m8650d:m8650d"} { "Warning" "WVRFX_L2_VDB_DRIVERLESS_OUTPUT_PORT" "eia_in M8650D.v(114) " "Output port \"eia_in\" at M8650D.v(114) has no driver" { } { { "M8650D.v" "" { Text "//wsl.localhost/Debian/home/vrs/Verilog/projects/32k-Omnibus/M8650D.v" 114 0 0 } } } 0 10034 "Output port \"%1!s!\" at %2!s! has no driver" 0 0 "Quartus II" 0 -1 1699430707919 "|cpld|m8650d:m8650d"} { "Warning" "WVRFX_L2_VDB_DRIVERLESS_OUTPUT_PORT" "eia_out M8650D.v(115) " "Output port \"eia_out\" at M8650D.v(115) has no driver" { } { { "M8650D.v" "" { Text "//wsl.localhost/Debian/home/vrs/Verilog/projects/32k-Omnibus/M8650D.v" 115 0 0 } } } 0 10034 "Output port \"%1!s!\" at %2!s! has no driver" 0 0 "Quartus II" 0 -1 1699430707919 "|cpld|m8650d:m8650d"} { "Warning" "WVRFX_L2_VDB_DRIVERLESS_OUTPUT_PORT" "n15v M8650D.v(133) " "Output port \"n15v\" at M8650D.v(133) has no driver" { } { { "M8650D.v" "" { Text "//wsl.localhost/Debian/home/vrs/Verilog/projects/32k-Omnibus/M8650D.v" 133 0 0 } } } 0 10034 "Output port \"%1!s!\" at %2!s! has no driver" 0 0 "Quartus II" 0 -1 1699430707919 "|cpld|m8650d:m8650d"} { "Warning" "WVRFX_L2_VDB_DRIVERLESS_OUTPUT_PORT" "reader_run M8650D.v(150) " "Output port \"reader_run\" at M8650D.v(150) has no driver" { } { { "M8650D.v" "" { Text "//wsl.localhost/Debian/home/vrs/Verilog/projects/32k-Omnibus/M8650D.v" 150 0 0 } } } 0 10034 "Output port \"%1!s!\" at %2!s! has no driver" 0 0 "Quartus II" 0 -1 1699430707919 "|cpld|m8650d:m8650d"} { "Warning" "WVRFX_L2_VDB_DRIVERLESS_OUTPUT_PORT" "reader_run_or M8650D.v(151) " "Output port \"reader_run_or\" at M8650D.v(151) has no driver" { } { { "M8650D.v" "" { Text "//wsl.localhost/Debian/home/vrs/Verilog/projects/32k-Omnibus/M8650D.v" 151 0 0 } } } 0 10034 "Output port \"%1!s!\" at %2!s! has no driver" 0 0 "Quartus II" 0 -1 1699430707919 "|cpld|m8650d:m8650d"} { "Warning" "WVRFX_L2_VDB_DRIVERLESS_OUTPUT_PORT" "rtsdtr M8650D.v(152) " "Output port \"rtsdtr\" at M8650D.v(152) has no driver" { } { { "M8650D.v" "" { Text "//wsl.localhost/Debian/home/vrs/Verilog/projects/32k-Omnibus/M8650D.v" 152 0 0 } } } 0 10034 "Output port \"%1!s!\" at %2!s! has no driver" 0 0 "Quartus II" 0 -1 1699430707919 "|cpld|m8650d:m8650d"} { "Warning" "WVRFX_L2_VDB_DRIVERLESS_OUTPUT_PORT" "rx_20ma M8650D.v(154) " "Output port \"rx_20ma\" at M8650D.v(154) has no driver" { } { { "M8650D.v" "" { Text "//wsl.localhost/Debian/home/vrs/Verilog/projects/32k-Omnibus/M8650D.v" 154 0 0 } } } 0 10034 "Output port \"%1!s!\" at %2!s! has no driver" 0 0 "Quartus II" 0 -1 1699430707919 "|cpld|m8650d:m8650d"} { "Warning" "WVRFX_L2_VDB_DRIVERLESS_OUTPUT_PORT" "rx_20ma_or M8650D.v(155) " "Output port \"rx_20ma_or\" at M8650D.v(155) has no driver" { } { { "M8650D.v" "" { Text "//wsl.localhost/Debian/home/vrs/Verilog/projects/32k-Omnibus/M8650D.v" 155 0 0 } } } 0 10034 "Output port \"%1!s!\" at %2!s! has no driver" 0 0 "Quartus II" 0 -1 1699430707919 "|cpld|m8650d:m8650d"} { "Warning" "WVRFX_L2_VDB_DRIVERLESS_OUTPUT_PORT" "tx_20ma M8650D.v(165) " "Output port \"tx_20ma\" at M8650D.v(165) has no driver" { } { { "M8650D.v" "" { Text "//wsl.localhost/Debian/home/vrs/Verilog/projects/32k-Omnibus/M8650D.v" 165 0 0 } } } 0 10034 "Output port \"%1!s!\" at %2!s! has no driver" 0 0 "Quartus II" 0 -1 1699430707919 "|cpld|m8650d:m8650d"} { "Warning" "WVRFX_L2_VDB_DRIVERLESS_OUTPUT_PORT" "tx_20ma_or M8650D.v(166) " "Output port \"tx_20ma_or\" at M8650D.v(166) has no driver" { } { { "M8650D.v" "" { Text "//wsl.localhost/Debian/home/vrs/Verilog/projects/32k-Omnibus/M8650D.v" 166 0 0 } } } 0 10034 "Output port \"%1!s!\" at %2!s! has no driver" 0 0 "Quartus II" 0 -1 1699430707919 "|cpld|m8650d:m8650d"} { "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "r_run_l M8650D.v(1275) " "Inferred latch for \"r_run_l\" at M8650D.v(1275)" { } { { "M8650D.v" "" { Text "//wsl.localhost/Debian/home/vrs/Verilog/projects/32k-Omnibus/M8650D.v" 1275 0 0 } } } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "Quartus II" 0 -1 1699430707919 "|cpld|m8650d:m8650d"} { "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "r_run_l_m M8650D.v(1265) " "Inferred latch for \"r_run_l_m\" at M8650D.v(1265)" { } { { "M8650D.v" "" { Text "//wsl.localhost/Debian/home/vrs/Verilog/projects/32k-Omnibus/M8650D.v" 1265 0 0 } } } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "Quartus II" 0 -1 1699430707919 "|cpld|m8650d:m8650d"} { "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "rflg_l M8650D.v(1255) " "Inferred latch for \"rflg_l\" at M8650D.v(1255)" { } { { "M8650D.v" "" { Text "//wsl.localhost/Debian/home/vrs/Verilog/projects/32k-Omnibus/M8650D.v" 1255 0 0 } } } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "Quartus II" 0 -1 1699430707919 "|cpld|m8650d:m8650d"} { "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "rflg_l_m M8650D.v(1245) " "Inferred latch for \"rflg_l_m\" at M8650D.v(1245)" { } { { "M8650D.v" "" { Text "//wsl.localhost/Debian/home/vrs/Verilog/projects/32k-Omnibus/M8650D.v" 1245 0 0 } } } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "Quartus II" 0 -1 1699430707919 "|cpld|m8650d:m8650d"} { "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "int_enab_l M8650D.v(1180) " "Inferred latch for \"int_enab_l\" at M8650D.v(1180)" { } { { "M8650D.v" "" { Text "//wsl.localhost/Debian/home/vrs/Verilog/projects/32k-Omnibus/M8650D.v" 1180 0 0 } } } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "Quartus II" 0 -1 1699430707919 "|cpld|m8650d:m8650d"} { "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "int_enab_l_m M8650D.v(1170) " "Inferred latch for \"int_enab_l_m\" at M8650D.v(1170)" { } { { "M8650D.v" "" { Text "//wsl.localhost/Debian/home/vrs/Verilog/projects/32k-Omnibus/M8650D.v" 1170 0 0 } } } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "Quartus II" 0 -1 1699430707919 "|cpld|m8650d:m8650d"} { "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "tflg_l M8650D.v(1160) " "Inferred latch for \"tflg_l\" at M8650D.v(1160)" { } { { "M8650D.v" "" { Text "//wsl.localhost/Debian/home/vrs/Verilog/projects/32k-Omnibus/M8650D.v" 1160 0 0 } } } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "Quartus II" 0 -1 1699430707919 "|cpld|m8650d:m8650d"} { "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "tflg_l_m M8650D.v(1150) " "Inferred latch for \"tflg_l_m\" at M8650D.v(1150)" { } { { "M8650D.v" "" { Text "//wsl.localhost/Debian/home/vrs/Verilog/projects/32k-Omnibus/M8650D.v" 1150 0 0 } } } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "Quartus II" 0 -1 1699430707919 "|cpld|m8650d:m8650d"} { "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "tx_data M8650D.v(1123) " "Inferred latch for \"tx_data\" at M8650D.v(1123)" { } { { "M8650D.v" "" { Text "//wsl.localhost/Debian/home/vrs/Verilog/projects/32k-Omnibus/M8650D.v" 1123 0 0 } } } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "Quartus II" 0 -1 1699430707919 "|cpld|m8650d:m8650d"} { "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "tx_data_m M8650D.v(1114) " "Inferred latch for \"tx_data_m\" at M8650D.v(1114)" { } { { "M8650D.v" "" { Text "//wsl.localhost/Debian/home/vrs/Verilog/projects/32k-Omnibus/M8650D.v" 1114 0 0 } } } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "Quartus II" 0 -1 1699430707919 "|cpld|m8650d:m8650d"} { "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "n_t_66x M8650D.v(1107) " "Inferred latch for \"n_t_66x\" at M8650D.v(1107)" { } { { "M8650D.v" "" { Text "//wsl.localhost/Debian/home/vrs/Verilog/projects/32k-Omnibus/M8650D.v" 1107 0 0 } } } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "Quartus II" 0 -1 1699430707919 "|cpld|m8650d:m8650d"} { "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "n_t_66x_m M8650D.v(1098) " "Inferred latch for \"n_t_66x_m\" at M8650D.v(1098)" { } { { "M8650D.v" "" { Text "//wsl.localhost/Debian/home/vrs/Verilog/projects/32k-Omnibus/M8650D.v" 1098 0 0 } } } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "Quartus II" 0 -1 1699430707919 "|cpld|m8650d:m8650d"} { "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "n_t_65x M8650D.v(1091) " "Inferred latch for \"n_t_65x\" at M8650D.v(1091)" { } { { "M8650D.v" "" { Text "//wsl.localhost/Debian/home/vrs/Verilog/projects/32k-Omnibus/M8650D.v" 1091 0 0 } } } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "Quartus II" 0 -1 1699430707919 "|cpld|m8650d:m8650d"} { "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "n_t_65x_m M8650D.v(1082) " "Inferred latch for \"n_t_65x_m\" at M8650D.v(1082)" { } { { "M8650D.v" "" { Text "//wsl.localhost/Debian/home/vrs/Verilog/projects/32k-Omnibus/M8650D.v" 1082 0 0 } } } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "Quartus II" 0 -1 1699430707919 "|cpld|m8650d:m8650d"} { "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "n_t_63x M8650D.v(1075) " "Inferred latch for \"n_t_63x\" at M8650D.v(1075)" { } { { "M8650D.v" "" { Text "//wsl.localhost/Debian/home/vrs/Verilog/projects/32k-Omnibus/M8650D.v" 1075 0 0 } } } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "Quartus II" 0 -1 1699430707919 "|cpld|m8650d:m8650d"} { "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "n_t_63x_m M8650D.v(1066) " "Inferred latch for \"n_t_63x_m\" at M8650D.v(1066)" { } { { "M8650D.v" "" { Text "//wsl.localhost/Debian/home/vrs/Verilog/projects/32k-Omnibus/M8650D.v" 1066 0 0 } } } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "Quartus II" 0 -1 1699430707919 "|cpld|m8650d:m8650d"} { "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "enab M8650D.v(1046) " "Inferred latch for \"enab\" at M8650D.v(1046)" { } { { "M8650D.v" "" { Text "//wsl.localhost/Debian/home/vrs/Verilog/projects/32k-Omnibus/M8650D.v" 1046 0 0 } } } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "Quartus II" 0 -1 1699430707919 "|cpld|m8650d:m8650d"} { "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "enab_m M8650D.v(1036) " "Inferred latch for \"enab_m\" at M8650D.v(1036)" { } { { "M8650D.v" "" { Text "//wsl.localhost/Debian/home/vrs/Verilog/projects/32k-Omnibus/M8650D.v" 1036 0 0 } } } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "Quartus II" 0 -1 1699430707919 "|cpld|m8650d:m8650d"} { "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "line M8650D.v(1025) " "Inferred latch for \"line\" at M8650D.v(1025)" { } { { "M8650D.v" "" { Text "//wsl.localhost/Debian/home/vrs/Verilog/projects/32k-Omnibus/M8650D.v" 1025 0 0 } } } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "Quartus II" 0 -1 1699430707919 "|cpld|m8650d:m8650d"} { "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "line_m M8650D.v(1015) " "Inferred latch for \"line_m\" at M8650D.v(1015)" { } { { "M8650D.v" "" { Text "//wsl.localhost/Debian/home/vrs/Verilog/projects/32k-Omnibus/M8650D.v" 1015 0 0 } } } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "Quartus II" 0 -1 1699430707919 "|cpld|m8650d:m8650d"} { "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "n_t_61x M8650D.v(1007) " "Inferred latch for \"n_t_61x\" at M8650D.v(1007)" { } { { "M8650D.v" "" { Text "//wsl.localhost/Debian/home/vrs/Verilog/projects/32k-Omnibus/M8650D.v" 1007 0 0 } } } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "Quartus II" 0 -1 1699430707919 "|cpld|m8650d:m8650d"} { "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "n_t_61x_m M8650D.v(998) " "Inferred latch for \"n_t_61x_m\" at M8650D.v(998)" { } { { "M8650D.v" "" { Text "//wsl.localhost/Debian/home/vrs/Verilog/projects/32k-Omnibus/M8650D.v" 998 0 0 } } } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "Quartus II" 0 -1 1699430707919 "|cpld|m8650d:m8650d"} { "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "n_t_56x M8650D.v(991) " "Inferred latch for \"n_t_56x\" at M8650D.v(991)" { } { { "M8650D.v" "" { Text "//wsl.localhost/Debian/home/vrs/Verilog/projects/32k-Omnibus/M8650D.v" 991 0 0 } } } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "Quartus II" 0 -1 1699430707919 "|cpld|m8650d:m8650d"} { "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "n_t_56x_m M8650D.v(982) " "Inferred latch for \"n_t_56x_m\" at M8650D.v(982)" { } { { "M8650D.v" "" { Text "//wsl.localhost/Debian/home/vrs/Verilog/projects/32k-Omnibus/M8650D.v" 982 0 0 } } } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "Quartus II" 0 -1 1699430707919 "|cpld|m8650d:m8650d"} { "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "n_t_62x M8650D.v(975) " "Inferred latch for \"n_t_62x\" at M8650D.v(975)" { } { { "M8650D.v" "" { Text "//wsl.localhost/Debian/home/vrs/Verilog/projects/32k-Omnibus/M8650D.v" 975 0 0 } } } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "Quartus II" 0 -1 1699430707919 "|cpld|m8650d:m8650d"} { "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "n_t_62x_m M8650D.v(966) " "Inferred latch for \"n_t_62x_m\" at M8650D.v(966)" { } { { "M8650D.v" "" { Text "//wsl.localhost/Debian/home/vrs/Verilog/projects/32k-Omnibus/M8650D.v" 966 0 0 } } } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "Quartus II" 0 -1 1699430707919 "|cpld|m8650d:m8650d"} { "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "n_t_60x M8650D.v(959) " "Inferred latch for \"n_t_60x\" at M8650D.v(959)" { } { { "M8650D.v" "" { Text "//wsl.localhost/Debian/home/vrs/Verilog/projects/32k-Omnibus/M8650D.v" 959 0 0 } } } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "Quartus II" 0 -1 1699430707919 "|cpld|m8650d:m8650d"} { "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "n_t_60x_m M8650D.v(950) " "Inferred latch for \"n_t_60x_m\" at M8650D.v(950)" { } { { "M8650D.v" "" { Text "//wsl.localhost/Debian/home/vrs/Verilog/projects/32k-Omnibus/M8650D.v" 950 0 0 } } } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "Quartus II" 0 -1 1699430707919 "|cpld|m8650d:m8650d"} { "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "n_t_119x M8650D.v(917) " "Inferred latch for \"n_t_119x\" at M8650D.v(917)" { } { { "M8650D.v" "" { Text "//wsl.localhost/Debian/home/vrs/Verilog/projects/32k-Omnibus/M8650D.v" 917 0 0 } } } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "Quartus II" 0 -1 1699430707919 "|cpld|m8650d:m8650d"} { "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "n_t_119x_m M8650D.v(908) " "Inferred latch for \"n_t_119x_m\" at M8650D.v(908)" { } { { "M8650D.v" "" { Text "//wsl.localhost/Debian/home/vrs/Verilog/projects/32k-Omnibus/M8650D.v" 908 0 0 } } } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "Quartus II" 0 -1 1699430707919 "|cpld|m8650d:m8650d"} { "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "gdollar_7 M8650D.v(901) " "Inferred latch for \"gdollar_7\" at M8650D.v(901)" { } { { "M8650D.v" "" { Text "//wsl.localhost/Debian/home/vrs/Verilog/projects/32k-Omnibus/M8650D.v" 901 0 0 } } } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "Quartus II" 0 -1 1699430707919 "|cpld|m8650d:m8650d"} { "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "gdollar_7_m M8650D.v(892) " "Inferred latch for \"gdollar_7_m\" at M8650D.v(892)" { } { { "M8650D.v" "" { Text "//wsl.localhost/Debian/home/vrs/Verilog/projects/32k-Omnibus/M8650D.v" 892 0 0 } } } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "Quartus II" 0 -1 1699430707919 "|cpld|m8650d:m8650d"} { "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "n_t_146x M8650D.v(885) " "Inferred latch for \"n_t_146x\" at M8650D.v(885)" { } { { "M8650D.v" "" { Text "//wsl.localhost/Debian/home/vrs/Verilog/projects/32k-Omnibus/M8650D.v" 885 0 0 } } } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "Quartus II" 0 -1 1699430707919 "|cpld|m8650d:m8650d"} { "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "n_t_146x_m M8650D.v(876) " "Inferred latch for \"n_t_146x_m\" at M8650D.v(876)" { } { { "M8650D.v" "" { Text "//wsl.localhost/Debian/home/vrs/Verilog/projects/32k-Omnibus/M8650D.v" 876 0 0 } } } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "Quartus II" 0 -1 1699430707919 "|cpld|m8650d:m8650d"} { "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "n_t_154x M8650D.v(844) " "Inferred latch for \"n_t_154x\" at M8650D.v(844)" { } { { "M8650D.v" "" { Text "//wsl.localhost/Debian/home/vrs/Verilog/projects/32k-Omnibus/M8650D.v" 844 0 0 } } } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "Quartus II" 0 -1 1699430707919 "|cpld|m8650d:m8650d"} { "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "n_t_154x_m M8650D.v(836) " "Inferred latch for \"n_t_154x_m\" at M8650D.v(836)" { } { { "M8650D.v" "" { Text "//wsl.localhost/Debian/home/vrs/Verilog/projects/32k-Omnibus/M8650D.v" 836 0 0 } } } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "Quartus II" 0 -1 1699430707919 "|cpld|m8650d:m8650d"} { "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "gdollar_6 M8650D.v(828) " "Inferred latch for \"gdollar_6\" at M8650D.v(828)" { } { { "M8650D.v" "" { Text "//wsl.localhost/Debian/home/vrs/Verilog/projects/32k-Omnibus/M8650D.v" 828 0 0 } } } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "Quartus II" 0 -1 1699430707919 "|cpld|m8650d:m8650d"} { "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "gdollar_6_m M8650D.v(820) " "Inferred latch for \"gdollar_6_m\" at M8650D.v(820)" { } { { "M8650D.v" "" { Text "//wsl.localhost/Debian/home/vrs/Verilog/projects/32k-Omnibus/M8650D.v" 820 0 0 } } } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "Quartus II" 0 -1 1699430707919 "|cpld|m8650d:m8650d"} { "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "gdollar_5 M8650D.v(812) " "Inferred latch for \"gdollar_5\" at M8650D.v(812)" { } { { "M8650D.v" "" { Text "//wsl.localhost/Debian/home/vrs/Verilog/projects/32k-Omnibus/M8650D.v" 812 0 0 } } } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "Quartus II" 0 -1 1699430707919 "|cpld|m8650d:m8650d"} { "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "gdollar_5_m M8650D.v(804) " "Inferred latch for \"gdollar_5_m\" at M8650D.v(804)" { } { { "M8650D.v" "" { Text "//wsl.localhost/Debian/home/vrs/Verilog/projects/32k-Omnibus/M8650D.v" 804 0 0 } } } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "Quartus II" 0 -1 1699430707919 "|cpld|m8650d:m8650d"} { "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "gdollar_4 M8650D.v(796) " "Inferred latch for \"gdollar_4\" at M8650D.v(796)" { } { { "M8650D.v" "" { Text "//wsl.localhost/Debian/home/vrs/Verilog/projects/32k-Omnibus/M8650D.v" 796 0 0 } } } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "Quartus II" 0 -1 1699430707919 "|cpld|m8650d:m8650d"} { "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "gdollar_4_m M8650D.v(788) " "Inferred latch for \"gdollar_4_m\" at M8650D.v(788)" { } { { "M8650D.v" "" { Text "//wsl.localhost/Debian/home/vrs/Verilog/projects/32k-Omnibus/M8650D.v" 788 0 0 } } } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "Quartus II" 0 -1 1699430707919 "|cpld|m8650d:m8650d"} { "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "start_l M8650D.v(775) " "Inferred latch for \"start_l\" at M8650D.v(775)" { } { { "M8650D.v" "" { Text "//wsl.localhost/Debian/home/vrs/Verilog/projects/32k-Omnibus/M8650D.v" 775 0 0 } } } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "Quartus II" 0 -1 1699430707919 "|cpld|m8650d:m8650d"} { "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "start_l_m M8650D.v(765) " "Inferred latch for \"start_l_m\" at M8650D.v(765)" { } { { "M8650D.v" "" { Text "//wsl.localhost/Debian/home/vrs/Verilog/projects/32k-Omnibus/M8650D.v" 765 0 0 } } } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "Quartus II" 0 -1 1699430707919 "|cpld|m8650d:m8650d"} { "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "tx_active_l M8650D.v(754) " "Inferred latch for \"tx_active_l\" at M8650D.v(754)" { } { { "M8650D.v" "" { Text "//wsl.localhost/Debian/home/vrs/Verilog/projects/32k-Omnibus/M8650D.v" 754 0 0 } } } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "Quartus II" 0 -1 1699430707919 "|cpld|m8650d:m8650d"} { "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "tx_active_l_m M8650D.v(744) " "Inferred latch for \"tx_active_l_m\" at M8650D.v(744)" { } { { "M8650D.v" "" { Text "//wsl.localhost/Debian/home/vrs/Verilog/projects/32k-Omnibus/M8650D.v" 744 0 0 } } } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "Quartus II" 0 -1 1699430707919 "|cpld|m8650d:m8650d"} { "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "spike_det_l M8650D.v(712) " "Inferred latch for \"spike_det_l\" at M8650D.v(712)" { } { { "M8650D.v" "" { Text "//wsl.localhost/Debian/home/vrs/Verilog/projects/32k-Omnibus/M8650D.v" 712 0 0 } } } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "Quartus II" 0 -1 1699430707930 "|cpld|m8650d:m8650d"} { "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "spike_det_l_m M8650D.v(702) " "Inferred latch for \"spike_det_l_m\" at M8650D.v(702)" { } { { "M8650D.v" "" { Text "//wsl.localhost/Debian/home/vrs/Verilog/projects/32k-Omnibus/M8650D.v" 702 0 0 } } } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "Quartus II" 0 -1 1699430707930 "|cpld|m8650d:m8650d"} { "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "tx_div M8650D.v(691) " "Inferred latch for \"tx_div\" at M8650D.v(691)" { } { { "M8650D.v" "" { Text "//wsl.localhost/Debian/home/vrs/Verilog/projects/32k-Omnibus/M8650D.v" 691 0 0 } } } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "Quartus II" 0 -1 1699430707930 "|cpld|m8650d:m8650d"} { "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "tx_div_m M8650D.v(681) " "Inferred latch for \"tx_div_m\" at M8650D.v(681)" { } { { "M8650D.v" "" { Text "//wsl.localhost/Debian/home/vrs/Verilog/projects/32k-Omnibus/M8650D.v" 681 0 0 } } } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "Quartus II" 0 -1 1699430707930 "|cpld|m8650d:m8650d"} { "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "n_t_40x M8650D.v(637) " "Inferred latch for \"n_t_40x\" at M8650D.v(637)" { } { { "M8650D.v" "" { Text "//wsl.localhost/Debian/home/vrs/Verilog/projects/32k-Omnibus/M8650D.v" 637 0 0 } } } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "Quartus II" 0 -1 1699430707930 "|cpld|m8650d:m8650d"} { "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "n_t_40x_m M8650D.v(628) " "Inferred latch for \"n_t_40x_m\" at M8650D.v(628)" { } { { "M8650D.v" "" { Text "//wsl.localhost/Debian/home/vrs/Verilog/projects/32k-Omnibus/M8650D.v" 628 0 0 } } } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "Quartus II" 0 -1 1699430707930 "|cpld|m8650d:m8650d"} { "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "n_t_39x M8650D.v(621) " "Inferred latch for \"n_t_39x\" at M8650D.v(621)" { } { { "M8650D.v" "" { Text "//wsl.localhost/Debian/home/vrs/Verilog/projects/32k-Omnibus/M8650D.v" 621 0 0 } } } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "Quartus II" 0 -1 1699430707930 "|cpld|m8650d:m8650d"} { "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "n_t_39x_m M8650D.v(612) " "Inferred latch for \"n_t_39x_m\" at M8650D.v(612)" { } { { "M8650D.v" "" { Text "//wsl.localhost/Debian/home/vrs/Verilog/projects/32k-Omnibus/M8650D.v" 612 0 0 } } } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "Quartus II" 0 -1 1699430707930 "|cpld|m8650d:m8650d"} { "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "n_t_38x M8650D.v(605) " "Inferred latch for \"n_t_38x\" at M8650D.v(605)" { } { { "M8650D.v" "" { Text "//wsl.localhost/Debian/home/vrs/Verilog/projects/32k-Omnibus/M8650D.v" 605 0 0 } } } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "Quartus II" 0 -1 1699430707930 "|cpld|m8650d:m8650d"} { "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "n_t_38x_m M8650D.v(596) " "Inferred latch for \"n_t_38x_m\" at M8650D.v(596)" { } { { "M8650D.v" "" { Text "//wsl.localhost/Debian/home/vrs/Verilog/projects/32k-Omnibus/M8650D.v" 596 0 0 } } } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "Quartus II" 0 -1 1699430707930 "|cpld|m8650d:m8650d"} { "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "n_t_37x M8650D.v(589) " "Inferred latch for \"n_t_37x\" at M8650D.v(589)" { } { { "M8650D.v" "" { Text "//wsl.localhost/Debian/home/vrs/Verilog/projects/32k-Omnibus/M8650D.v" 589 0 0 } } } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "Quartus II" 0 -1 1699430707930 "|cpld|m8650d:m8650d"} { "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "n_t_37x_m M8650D.v(580) " "Inferred latch for \"n_t_37x_m\" at M8650D.v(580)" { } { { "M8650D.v" "" { Text "//wsl.localhost/Debian/home/vrs/Verilog/projects/32k-Omnibus/M8650D.v" 580 0 0 } } } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "Quartus II" 0 -1 1699430707930 "|cpld|m8650d:m8650d"} { "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "n_t_88x M8650D.v(561) " "Inferred latch for \"n_t_88x\" at M8650D.v(561)" { } { { "M8650D.v" "" { Text "//wsl.localhost/Debian/home/vrs/Verilog/projects/32k-Omnibus/M8650D.v" 561 0 0 } } } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "Quartus II" 0 -1 1699430707930 "|cpld|m8650d:m8650d"} { "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "n_t_88x_m M8650D.v(551) " "Inferred latch for \"n_t_88x_m\" at M8650D.v(551)" { } { { "M8650D.v" "" { Text "//wsl.localhost/Debian/home/vrs/Verilog/projects/32k-Omnibus/M8650D.v" 551 0 0 } } } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "Quartus II" 0 -1 1699430707930 "|cpld|m8650d:m8650d"} { "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "last_unit M8650D.v(541) " "Inferred latch for \"last_unit\" at M8650D.v(541)" { } { { "M8650D.v" "" { Text "//wsl.localhost/Debian/home/vrs/Verilog/projects/32k-Omnibus/M8650D.v" 541 0 0 } } } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "Quartus II" 0 -1 1699430707930 "|cpld|m8650d:m8650d"} { "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "last_unit_m M8650D.v(531) " "Inferred latch for \"last_unit_m\" at M8650D.v(531)" { } { { "M8650D.v" "" { Text "//wsl.localhost/Debian/home/vrs/Verilog/projects/32k-Omnibus/M8650D.v" 531 0 0 } } } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "Quartus II" 0 -1 1699430707930 "|cpld|m8650d:m8650d"} { "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "p_pulse_l M8650D.v(520) " "Inferred latch for \"p_pulse_l\" at M8650D.v(520)" { } { { "M8650D.v" "" { Text "//wsl.localhost/Debian/home/vrs/Verilog/projects/32k-Omnibus/M8650D.v" 520 0 0 } } } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "Quartus II" 0 -1 1699430707930 "|cpld|m8650d:m8650d"} { "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "p_pulse_l_m M8650D.v(510) " "Inferred latch for \"p_pulse_l_m\" at M8650D.v(510)" { } { { "M8650D.v" "" { Text "//wsl.localhost/Debian/home/vrs/Verilog/projects/32k-Omnibus/M8650D.v" 510 0 0 } } } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "Quartus II" 0 -1 1699430707930 "|cpld|m8650d:m8650d"} { "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "rx_active M8650D.v(500) " "Inferred latch for \"rx_active\" at M8650D.v(500)" { } { { "M8650D.v" "" { Text "//wsl.localhost/Debian/home/vrs/Verilog/projects/32k-Omnibus/M8650D.v" 500 0 0 } } } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "Quartus II" 0 -1 1699430707930 "|cpld|m8650d:m8650d"} { "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "rx_active_m M8650D.v(490) " "Inferred latch for \"rx_active_m\" at M8650D.v(490)" { } { { "M8650D.v" "" { Text "//wsl.localhost/Debian/home/vrs/Verilog/projects/32k-Omnibus/M8650D.v" 490 0 0 } } } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "Quartus II" 0 -1 1699430707930 "|cpld|m8650d:m8650d"} { "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "n_t_35x M8650D.v(482) " "Inferred latch for \"n_t_35x\" at M8650D.v(482)" { } { { "M8650D.v" "" { Text "//wsl.localhost/Debian/home/vrs/Verilog/projects/32k-Omnibus/M8650D.v" 482 0 0 } } } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "Quartus II" 0 -1 1699430707930 "|cpld|m8650d:m8650d"} { "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "n_t_35x_m M8650D.v(473) " "Inferred latch for \"n_t_35x_m\" at M8650D.v(473)" { } { { "M8650D.v" "" { Text "//wsl.localhost/Debian/home/vrs/Verilog/projects/32k-Omnibus/M8650D.v" 473 0 0 } } } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "Quartus II" 0 -1 1699430707930 "|cpld|m8650d:m8650d"} { "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "n_t_36x M8650D.v(466) " "Inferred latch for \"n_t_36x\" at M8650D.v(466)" { } { { "M8650D.v" "" { Text "//wsl.localhost/Debian/home/vrs/Verilog/projects/32k-Omnibus/M8650D.v" 466 0 0 } } } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "Quartus II" 0 -1 1699430707930 "|cpld|m8650d:m8650d"} { "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "n_t_36x_m M8650D.v(457) " "Inferred latch for \"n_t_36x_m\" at M8650D.v(457)" { } { { "M8650D.v" "" { Text "//wsl.localhost/Debian/home/vrs/Verilog/projects/32k-Omnibus/M8650D.v" 457 0 0 } } } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "Quartus II" 0 -1 1699430707930 "|cpld|m8650d:m8650d"} { "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "n_t_34x M8650D.v(450) " "Inferred latch for \"n_t_34x\" at M8650D.v(450)" { } { { "M8650D.v" "" { Text "//wsl.localhost/Debian/home/vrs/Verilog/projects/32k-Omnibus/M8650D.v" 450 0 0 } } } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "Quartus II" 0 -1 1699430707930 "|cpld|m8650d:m8650d"} { "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "n_t_34x_m M8650D.v(441) " "Inferred latch for \"n_t_34x_m\" at M8650D.v(441)" { } { { "M8650D.v" "" { Text "//wsl.localhost/Debian/home/vrs/Verilog/projects/32k-Omnibus/M8650D.v" 441 0 0 } } } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "Quartus II" 0 -1 1699430707930 "|cpld|m8650d:m8650d"} { "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "n_t_30x M8650D.v(434) " "Inferred latch for \"n_t_30x\" at M8650D.v(434)" { } { { "M8650D.v" "" { Text "//wsl.localhost/Debian/home/vrs/Verilog/projects/32k-Omnibus/M8650D.v" 434 0 0 } } } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "Quartus II" 0 -1 1699430707930 "|cpld|m8650d:m8650d"} { "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "n_t_30x_m M8650D.v(425) " "Inferred latch for \"n_t_30x_m\" at M8650D.v(425)" { } { { "M8650D.v" "" { Text "//wsl.localhost/Debian/home/vrs/Verilog/projects/32k-Omnibus/M8650D.v" 425 0 0 } } } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "Quartus II" 0 -1 1699430707930 "|cpld|m8650d:m8650d"} { "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "n_t_75x M8650D.v(397) " "Inferred latch for \"n_t_75x\" at M8650D.v(397)" { } { { "M8650D.v" "" { Text "//wsl.localhost/Debian/home/vrs/Verilog/projects/32k-Omnibus/M8650D.v" 397 0 0 } } } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "Quartus II" 0 -1 1699430707930 "|cpld|m8650d:m8650d"} { "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "n_t_75x_m M8650D.v(387) " "Inferred latch for \"n_t_75x_m\" at M8650D.v(387)" { } { { "M8650D.v" "" { Text "//wsl.localhost/Debian/home/vrs/Verilog/projects/32k-Omnibus/M8650D.v" 387 0 0 } } } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "Quartus II" 0 -1 1699430707930 "|cpld|m8650d:m8650d"} { "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "n_t_43x M8650D.v(377) " "Inferred latch for \"n_t_43x\" at M8650D.v(377)" { } { { "M8650D.v" "" { Text "//wsl.localhost/Debian/home/vrs/Verilog/projects/32k-Omnibus/M8650D.v" 377 0 0 } } } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "Quartus II" 0 -1 1699430707930 "|cpld|m8650d:m8650d"} { "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "n_t_43x_m M8650D.v(367) " "Inferred latch for \"n_t_43x_m\" at M8650D.v(367)" { } { { "M8650D.v" "" { Text "//wsl.localhost/Debian/home/vrs/Verilog/projects/32k-Omnibus/M8650D.v" 367 0 0 } } } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "Quartus II" 0 -1 1699430707930 "|cpld|m8650d:m8650d"} { "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "ck_pulse M8650D.v(356) " "Inferred latch for \"ck_pulse\" at M8650D.v(356)" { } { { "M8650D.v" "" { Text "//wsl.localhost/Debian/home/vrs/Verilog/projects/32k-Omnibus/M8650D.v" 356 0 0 } } } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "Quartus II" 0 -1 1699430707930 "|cpld|m8650d:m8650d"} { "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "ck_pulse_m M8650D.v(346) " "Inferred latch for \"ck_pulse_m\" at M8650D.v(346)" { } { { "M8650D.v" "" { Text "//wsl.localhost/Debian/home/vrs/Verilog/projects/32k-Omnibus/M8650D.v" 346 0 0 } } } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "Quartus II" 0 -1 1699430707930 "|cpld|m8650d:m8650d"} { "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "rx_div M8650D.v(336) " "Inferred latch for \"rx_div\" at M8650D.v(336)" { } { { "M8650D.v" "" { Text "//wsl.localhost/Debian/home/vrs/Verilog/projects/32k-Omnibus/M8650D.v" 336 0 0 } } } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "Quartus II" 0 -1 1699430707930 "|cpld|m8650d:m8650d"} { "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "rx_div_m M8650D.v(326) " "Inferred latch for \"rx_div_m\" at M8650D.v(326)" { } { { "M8650D.v" "" { Text "//wsl.localhost/Debian/home/vrs/Verilog/projects/32k-Omnibus/M8650D.v" 326 0 0 } } } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "Quartus II" 0 -1 1699430707930 "|cpld|m8650d:m8650d"} { "Warning" "WSGN_CONNECTIVITY_WARNINGS" "1 " "1 hierarchies have connectivity warnings - see the Connectivity Checks report folder" { } { } 0 12241 "%1!d! hierarchies have connectivity warnings - see the Connectivity Checks report folder" 0 0 "Quartus II" 0 -1 1699430708155 ""} { "Warning" "WMLS_OPT_INSERTED_ALWAYS_DISABLED_TRI_HDR" "" "The following bidir pins have no drivers" { { "Warning" "WMLS_OPT_INSERTED_ALWAYS_DISABLED_TRI" "data03_l " "Bidir \"data03_l\" has no driver" { } { { "cpld.v" "" { Text "//wsl.localhost/Debian/home/vrs/Verilog/projects/32k-Omnibus/cpld.v" 143 -1 0 } } } 0 13040 "Bidir \"%1!s!\" has no driver" 0 0 "Quartus II" 0 -1 1699430708249 ""} { "Warning" "WMLS_OPT_INSERTED_ALWAYS_DISABLED_TRI" "data02_l " "Bidir \"data02_l\" has no driver" { } { { "cpld.v" "" { Text "//wsl.localhost/Debian/home/vrs/Verilog/projects/32k-Omnibus/cpld.v" 144 -1 0 } } } 0 13040 "Bidir \"%1!s!\" has no driver" 0 0 "Quartus II" 0 -1 1699430708249 ""} { "Warning" "WMLS_OPT_INSERTED_ALWAYS_DISABLED_TRI" "data01_l " "Bidir \"data01_l\" has no driver" { } { { "cpld.v" "" { Text "//wsl.localhost/Debian/home/vrs/Verilog/projects/32k-Omnibus/cpld.v" 145 -1 0 } } } 0 13040 "Bidir \"%1!s!\" has no driver" 0 0 "Quartus II" 0 -1 1699430708249 ""} { "Warning" "WMLS_OPT_INSERTED_ALWAYS_DISABLED_TRI" "data00_l " "Bidir \"data00_l\" has no driver" { } { { "cpld.v" "" { Text "//wsl.localhost/Debian/home/vrs/Verilog/projects/32k-Omnibus/cpld.v" 146 -1 0 } } } 0 13040 "Bidir \"%1!s!\" has no driver" 0 0 "Quartus II" 0 -1 1699430708249 ""} } { } 0 13039 "The following bidir pins have no drivers" 0 0 "Quartus II" 0 -1 1699430708249 ""} { "Info" "IMTM_MTM_PROMOTE_GLOBAL" "" "Promoted pin-driven signal(s) to global signal" { { "Info" "IMTM_MTM_PROMOTE_GLOBAL_CLOCK" "clk " "Promoted clock signal driven by pin \"clk\" to global clock signal" { } { } 0 280014 "Promoted clock signal driven by pin \"%1!s!\" to global clock signal" 0 0 "Quartus II" 0 -1 1699430708359 ""} } { } 0 280013 "Promoted pin-driven signal(s) to global signal" 0 0 "Quartus II" 0 -1 1699430708359 ""} { "Warning" "WCUT_CUT_UNNECESSARY_INPUT_PIN_HDR" "25 " "Design contains 25 input pin(s) that do not drive logic" { { "Warning" "WCUT_CUT_UNNECESSARY_INPUT_PIN" "pulse_la " "No output dependent on input pin \"pulse_la\"" { } { { "cpld.v" "" { Text "//wsl.localhost/Debian/home/vrs/Verilog/projects/32k-Omnibus/cpld.v" 84 -1 0 } } } 0 15610 "No output dependent on input pin \"%1!s!\"" 0 0 "Quartus II" 0 -1 1699430708547 "|cpld|pulse_la"} { "Warning" "WCUT_CUT_UNNECESSARY_INPUT_PIN" "f_set_l " "No output dependent on input pin \"f_set_l\"" { } { { "cpld.v" "" { Text "//wsl.localhost/Debian/home/vrs/Verilog/projects/32k-Omnibus/cpld.v" 86 -1 0 } } } 0 15610 "No output dependent on input pin \"%1!s!\"" 0 0 "Quartus II" 0 -1 1699430708547 "|cpld|f_set_l"} { "Warning" "WCUT_CUT_UNNECESSARY_INPUT_PIN" "user_mode_l " "No output dependent on input pin \"user_mode_l\"" { } { { "cpld.v" "" { Text "//wsl.localhost/Debian/home/vrs/Verilog/projects/32k-Omnibus/cpld.v" 88 -1 0 } } } 0 15610 "No output dependent on input pin \"%1!s!\"" 0 0 "Quartus II" 0 -1 1699430708547 "|cpld|user_mode_l"} { "Warning" "WCUT_CUT_UNNECESSARY_INPUT_PIN" "d_l " "No output dependent on input pin \"d_l\"" { } { { "cpld.v" "" { Text "//wsl.localhost/Debian/home/vrs/Verilog/projects/32k-Omnibus/cpld.v" 95 -1 0 } } } 0 15610 "No output dependent on input pin \"%1!s!\"" 0 0 "Quartus II" 0 -1 1699430708547 "|cpld|d_l"} { "Warning" "WCUT_CUT_UNNECESSARY_INPUT_PIN" "f_l " "No output dependent on input pin \"f_l\"" { } { { "cpld.v" "" { Text "//wsl.localhost/Debian/home/vrs/Verilog/projects/32k-Omnibus/cpld.v" 97 -1 0 } } } 0 15610 "No output dependent on input pin \"%1!s!\"" 0 0 "Quartus II" 0 -1 1699430708547 "|cpld|f_l"} { "Warning" "WCUT_CUT_UNNECESSARY_INPUT_PIN" "ir01_l " "No output dependent on input pin \"ir01_l\"" { } { { "cpld.v" "" { Text "//wsl.localhost/Debian/home/vrs/Verilog/projects/32k-Omnibus/cpld.v" 98 -1 0 } } } 0 15610 "No output dependent on input pin \"%1!s!\"" 0 0 "Quartus II" 0 -1 1699430708547 "|cpld|ir01_l"} { "Warning" "WCUT_CUT_UNNECESSARY_INPUT_PIN" "ir00_l " "No output dependent on input pin \"ir00_l\"" { } { { "cpld.v" "" { Text "//wsl.localhost/Debian/home/vrs/Verilog/projects/32k-Omnibus/cpld.v" 99 -1 0 } } } 0 15610 "No output dependent on input pin \"%1!s!\"" 0 0 "Quartus II" 0 -1 1699430708547 "|cpld|ir00_l"} { "Warning" "WCUT_CUT_UNNECESSARY_INPUT_PIN" "ind2_l " "No output dependent on input pin \"ind2_l\"" { } { { "cpld.v" "" { Text "//wsl.localhost/Debian/home/vrs/Verilog/projects/32k-Omnibus/cpld.v" 100 -1 0 } } } 0 15610 "No output dependent on input pin \"%1!s!\"" 0 0 "Quartus II" 0 -1 1699430708547 "|cpld|ind2_l"} { "Warning" "WCUT_CUT_UNNECESSARY_INPUT_PIN" "ind1_l " "No output dependent on input pin \"ind1_l\"" { } { { "cpld.v" "" { Text "//wsl.localhost/Debian/home/vrs/Verilog/projects/32k-Omnibus/cpld.v" 101 -1 0 } } } 0 15610 "No output dependent on input pin \"%1!s!\"" 0 0 "Quartus II" 0 -1 1699430708547 "|cpld|ind1_l"} { "Warning" "WCUT_CUT_UNNECESSARY_INPUT_PIN" "cpma_disable_l " "No output dependent on input pin \"cpma_disable_l\"" { } { { "cpld.v" "" { Text "//wsl.localhost/Debian/home/vrs/Verilog/projects/32k-Omnibus/cpld.v" 102 -1 0 } } } 0 15610 "No output dependent on input pin \"%1!s!\"" 0 0 "Quartus II" 0 -1 1699430708547 "|cpld|cpma_disable_l"} { "Warning" "WCUT_CUT_UNNECESSARY_INPUT_PIN" "ts3_l " "No output dependent on input pin \"ts3_l\"" { } { { "cpld.v" "" { Text "//wsl.localhost/Debian/home/vrs/Verilog/projects/32k-Omnibus/cpld.v" 106 -1 0 } } } 0 15610 "No output dependent on input pin \"%1!s!\"" 0 0 "Quartus II" 0 -1 1699430708547 "|cpld|ts3_l"} { "Warning" "WCUT_CUT_UNNECESSARY_INPUT_PIN" "ts1_l " "No output dependent on input pin \"ts1_l\"" { } { { "cpld.v" "" { Text "//wsl.localhost/Debian/home/vrs/Verilog/projects/32k-Omnibus/cpld.v" 108 -1 0 } } } 0 15610 "No output dependent on input pin \"%1!s!\"" 0 0 "Quartus II" 0 -1 1699430708547 "|cpld|ts1_l"} { "Warning" "WCUT_CUT_UNNECESSARY_INPUT_PIN" "tp4 " "No output dependent on input pin \"tp4\"" { } { { "cpld.v" "" { Text "//wsl.localhost/Debian/home/vrs/Verilog/projects/32k-Omnibus/cpld.v" 109 -1 0 } } } 0 15610 "No output dependent on input pin \"%1!s!\"" 0 0 "Quartus II" 0 -1 1699430708547 "|cpld|tp4"} { "Warning" "WCUT_CUT_UNNECESSARY_INPUT_PIN" "tp2 " "No output dependent on input pin \"tp2\"" { } { { "cpld.v" "" { Text "//wsl.localhost/Debian/home/vrs/Verilog/projects/32k-Omnibus/cpld.v" 112 -1 0 } } } 0 15610 "No output dependent on input pin \"%1!s!\"" 0 0 "Quartus II" 0 -1 1699430708547 "|cpld|tp2"} { "Warning" "WCUT_CUT_UNNECESSARY_INPUT_PIN" "df_enable " "No output dependent on input pin \"df_enable\"" { } { { "cpld.v" "" { Text "//wsl.localhost/Debian/home/vrs/Verilog/projects/32k-Omnibus/cpld.v" 116 -1 0 } } } 0 15610 "No output dependent on input pin \"%1!s!\"" 0 0 "Quartus II" 0 -1 1699430708547 "|cpld|df_enable"} { "Warning" "WCUT_CUT_UNNECESSARY_INPUT_PIN" "run_l " "No output dependent on input pin \"run_l\"" { } { { "cpld.v" "" { Text "//wsl.localhost/Debian/home/vrs/Verilog/projects/32k-Omnibus/cpld.v" 122 -1 0 } } } 0 15610 "No output dependent on input pin \"%1!s!\"" 0 0 "Quartus II" 0 -1 1699430708547 "|cpld|run_l"} { "Warning" "WCUT_CUT_UNNECESSARY_INPUT_PIN" "int_in_prog_l " "No output dependent on input pin \"int_in_prog_l\"" { } { { "cpld.v" "" { Text "//wsl.localhost/Debian/home/vrs/Verilog/projects/32k-Omnibus/cpld.v" 127 -1 0 } } } 0 15610 "No output dependent on input pin \"%1!s!\"" 0 0 "Quartus II" 0 -1 1699430708547 "|cpld|int_in_prog_l"} { "Warning" "WCUT_CUT_UNNECESSARY_INPUT_PIN" "load_cont_l " "No output dependent on input pin \"load_cont_l\"" { } { { "cpld.v" "" { Text "//wsl.localhost/Debian/home/vrs/Verilog/projects/32k-Omnibus/cpld.v" 135 -1 0 } } } 0 15610 "No output dependent on input pin \"%1!s!\"" 0 0 "Quartus II" 0 -1 1699430708547 "|cpld|load_cont_l"} { "Warning" "WCUT_CUT_UNNECESSARY_INPUT_PIN" "md02_l " "No output dependent on input pin \"md02_l\"" { } { { "cpld.v" "" { Text "//wsl.localhost/Debian/home/vrs/Verilog/projects/32k-Omnibus/cpld.v" 148 -1 0 } } } 0 15610 "No output dependent on input pin \"%1!s!\"" 0 0 "Quartus II" 0 -1 1699430708547 "|cpld|md02_l"} { "Warning" "WCUT_CUT_UNNECESSARY_INPUT_PIN" "md01_l " "No output dependent on input pin \"md01_l\"" { } { { "cpld.v" "" { Text "//wsl.localhost/Debian/home/vrs/Verilog/projects/32k-Omnibus/cpld.v" 149 -1 0 } } } 0 15610 "No output dependent on input pin \"%1!s!\"" 0 0 "Quartus II" 0 -1 1699430708547 "|cpld|md01_l"} { "Warning" "WCUT_CUT_UNNECESSARY_INPUT_PIN" "md00_l " "No output dependent on input pin \"md00_l\"" { } { { "cpld.v" "" { Text "//wsl.localhost/Debian/home/vrs/Verilog/projects/32k-Omnibus/cpld.v" 150 -1 0 } } } 0 15610 "No output dependent on input pin \"%1!s!\"" 0 0 "Quartus II" 0 -1 1699430708547 "|cpld|md00_l"} { "Warning" "WCUT_CUT_UNNECESSARY_INPUT_PIN" "ema2_l " "No output dependent on input pin \"ema2_l\"" { } { { "cpld.v" "" { Text "//wsl.localhost/Debian/home/vrs/Verilog/projects/32k-Omnibus/cpld.v" 152 -1 0 } } } 0 15610 "No output dependent on input pin \"%1!s!\"" 0 0 "Quartus II" 0 -1 1699430708547 "|cpld|ema2_l"} { "Warning" "WCUT_CUT_UNNECESSARY_INPUT_PIN" "ema1_l " "No output dependent on input pin \"ema1_l\"" { } { { "cpld.v" "" { Text "//wsl.localhost/Debian/home/vrs/Verilog/projects/32k-Omnibus/cpld.v" 153 -1 0 } } } 0 15610 "No output dependent on input pin \"%1!s!\"" 0 0 "Quartus II" 0 -1 1699430708547 "|cpld|ema1_l"} { "Warning" "WCUT_CUT_UNNECESSARY_INPUT_PIN" "ema0_l " "No output dependent on input pin \"ema0_l\"" { } { { "cpld.v" "" { Text "//wsl.localhost/Debian/home/vrs/Verilog/projects/32k-Omnibus/cpld.v" 154 -1 0 } } } 0 15610 "No output dependent on input pin \"%1!s!\"" 0 0 "Quartus II" 0 -1 1699430708547 "|cpld|ema0_l"} { "Warning" "WCUT_CUT_UNNECESSARY_INPUT_PIN" "key_ctl_l " "No output dependent on input pin \"key_ctl_l\"" { } { { "cpld.v" "" { Text "//wsl.localhost/Debian/home/vrs/Verilog/projects/32k-Omnibus/cpld.v" 167 -1 0 } } } 0 15610 "No output dependent on input pin \"%1!s!\"" 0 0 "Quartus II" 0 -1 1699430708547 "|cpld|key_ctl_l"} } { } 0 21074 "Design contains %1!d! input pin(s) that do not drive logic" 0 0 "Quartus II" 0 -1 1699430708547 ""} { "Info" "ICUT_CUT_TM_SUMMARY" "208 " "Implemented 208 device resources after synthesis - the final resource count might be different" { { "Info" "ICUT_CUT_TM_IPINS" "46 " "Implemented 46 input pins" { } { } 0 21058 "Implemented %1!d! input pins" 0 0 "Quartus II" 0 -1 1699430708563 ""} { "Info" "ICUT_CUT_TM_OPINS" "6 " "Implemented 6 output pins" { } { } 0 21059 "Implemented %1!d! output pins" 0 0 "Quartus II" 0 -1 1699430708563 ""} { "Info" "ICUT_CUT_TM_BIDIRS" "12 " "Implemented 12 bidirectional pins" { } { } 0 21060 "Implemented %1!d! bidirectional pins" 0 0 "Quartus II" 0 -1 1699430708563 ""} { "Info" "ICUT_CUT_TM_MCELLS" "123 " "Implemented 123 macrocells" { } { } 0 21063 "Implemented %1!d! macrocells" 0 0 "Quartus II" 0 -1 1699430708563 ""} { "Info" "ICUT_CUT_TM_SEXPS" "21 " "Implemented 21 shareable expanders" { } { } 0 21073 "Implemented %1!d! shareable expanders" 0 0 "Quartus II" 0 -1 1699430708563 ""} } { } 0 21057 "Implemented %1!d! device resources after synthesis - the final resource count might be different" 0 0 "Quartus II" 0 -1 1699430708563 ""} { "Info" "IRDB_WROTE_SUPPRESSED_MSGS" "//wsl.localhost/Debian/home/vrs/Verilog/projects/32k-Omnibus/output_files/cpld.map.smsg " "Generated suppressed messages file //wsl.localhost/Debian/home/vrs/Verilog/projects/32k-Omnibus/output_files/cpld.map.smsg" { } { } 0 144001 "Generated suppressed messages file %1!s!" 0 0 "Quartus II" 0 -1 1699430708814 ""} { "Info" "IQEXE_ERROR_COUNT" "Analysis & Synthesis 0 s 128 s Quartus II 64-Bit " "Quartus II 64-Bit Analysis & Synthesis was successful. 0 errors, 128 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "4571 " "Peak virtual memory: 4571 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Quartus II" 0 -1 1699430708877 ""} { "Info" "IQEXE_END_BANNER_TIME" "Wed Nov 08 00:05:08 2023 " "Processing ended: Wed Nov 08 00:05:08 2023" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Quartus II" 0 -1 1699430708877 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:02 " "Elapsed time: 00:00:02" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Quartus II" 0 -1 1699430708877 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:01 " "Total CPU time (on all processors): 00:00:01" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Quartus II" 0 -1 1699430708877 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Quartus II" 0 -1 1699430708877 ""} { "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "Quartus II" 0 -1 1699430710181 ""} { "Info" "IQEXE_START_BANNER_PRODUCT" "Fitter Quartus II 64-Bit " "Running Quartus II 64-Bit Fitter" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition " "Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition" { } { } 0 0 "%1!s!" 0 0 "Quartus II" 0 -1 1699430710181 ""} { "Info" "IQEXE_START_BANNER_TIME" "Wed Nov 08 00:05:09 2023 " "Processing started: Wed Nov 08 00:05:09 2023" { } { } 0 0 "Processing started: %1!s!" 0 0 "Quartus II" 0 -1 1699430710181 ""} } { } 4 0 "Running %2!s! %1!s!" 0 0 "Fitter" 0 -1 1699430710181 ""} { "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_fit --read_settings_files=off --write_settings_files=off cpld -c cpld " "Command: quartus_fit --read_settings_files=off --write_settings_files=off cpld -c cpld" { } { } 0 0 "Command: %1!s!" 0 0 "Fitter" 0 -1 1699430710181 ""} { "Info" "0" "" "qfit2_default_script.tcl version: #1" { } { } 0 0 "qfit2_default_script.tcl version: #1" 0 0 "Fitter" 0 0 1699430711061 ""} { "Info" "0" "" "Project = cpld" { } { } 0 0 "Project = cpld" 0 0 "Fitter" 0 0 1699430711061 ""} { "Info" "0" "" "Revision = cpld" { } { } 0 0 "Revision = cpld" 0 0 "Fitter" 0 0 1699430711061 ""} { "Info" "IMPP_MPP_USER_DEVICE" "cpld EPM7128SLI84-10 " "Selected device EPM7128SLI84-10 for design \"cpld\"" { } { } 0 119006 "Selected device %2!s! for design \"%1!s!\"" 0 0 "Fitter" 0 -1 1699430711281 ""} { "Info" "IQEXE_ERROR_COUNT" "Fitter 0 s 0 s Quartus II 64-Bit " "Quartus II 64-Bit Fitter was successful. 0 errors, 0 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "4701 " "Peak virtual memory: 4701 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Quartus II" 0 -1 1699430711705 ""} { "Info" "IQEXE_END_BANNER_TIME" "Wed Nov 08 00:05:11 2023 " "Processing ended: Wed Nov 08 00:05:11 2023" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Quartus II" 0 -1 1699430711705 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:02 " "Elapsed time: 00:00:02" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Quartus II" 0 -1 1699430711705 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:00 " "Total CPU time (on all processors): 00:00:00" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Quartus II" 0 -1 1699430711705 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Fitter" 0 -1 1699430711705 ""} { "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "Fitter" 0 -1 1699430712819 ""} { "Info" "IQEXE_START_BANNER_PRODUCT" "Assembler Quartus II 64-Bit " "Running Quartus II 64-Bit Assembler" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition " "Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition" { } { } 0 0 "%1!s!" 0 0 "Quartus II" 0 -1 1699430712819 ""} { "Info" "IQEXE_START_BANNER_TIME" "Wed Nov 08 00:05:12 2023 " "Processing started: Wed Nov 08 00:05:12 2023" { } { } 0 0 "Processing started: %1!s!" 0 0 "Quartus II" 0 -1 1699430712819 ""} } { } 4 0 "Running %2!s! %1!s!" 0 0 "Assembler" 0 -1 1699430712819 ""} { "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_asm --read_settings_files=off --write_settings_files=off cpld -c cpld " "Command: quartus_asm --read_settings_files=off --write_settings_files=off cpld -c cpld" { } { } 0 0 "Command: %1!s!" 0 0 "Assembler" 0 -1 1699430712819 ""} { "Info" "IASM_ASM_GENERATING_PROGRAMMING_FILES" "" "Assembler is generating device programming files" { } { } 0 115030 "Assembler is generating device programming files" 0 0 "Assembler" 0 -1 1699430713054 ""} { "Info" "IQEXE_ERROR_COUNT" "Assembler 0 s 0 s Quartus II 64-Bit " "Quartus II 64-Bit Assembler was successful. 0 errors, 0 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "4515 " "Peak virtual memory: 4515 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Quartus II" 0 -1 1699430713305 ""} { "Info" "IQEXE_END_BANNER_TIME" "Wed Nov 08 00:05:13 2023 " "Processing ended: Wed Nov 08 00:05:13 2023" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Quartus II" 0 -1 1699430713305 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:01 " "Elapsed time: 00:00:01" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Quartus II" 0 -1 1699430713305 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:00 " "Total CPU time (on all processors): 00:00:00" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Quartus II" 0 -1 1699430713305 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Assembler" 0 -1 1699430713305 ""} { "Info" "IFLOW_DISABLED_MODULE" "PowerPlay Power Analyzer FLOW_ENABLE_POWER_ANALYZER " "Skipped module PowerPlay Power Analyzer due to the assignment FLOW_ENABLE_POWER_ANALYZER" { } { } 0 293026 "Skipped module %1!s! due to the assignment %2!s!" 0 0 "Assembler" 0 -1 1699430713949 ""} { "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "Assembler" 0 -1 1699430714560 ""} { "Info" "IQEXE_START_BANNER_PRODUCT" "TimeQuest Timing Analyzer Quartus II 64-Bit " "Running Quartus II 64-Bit TimeQuest Timing Analyzer" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition " "Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition" { } { } 0 0 "%1!s!" 0 0 "Quartus II" 0 -1 1699430714560 ""} { "Info" "IQEXE_START_BANNER_TIME" "Wed Nov 08 00:05:14 2023 " "Processing started: Wed Nov 08 00:05:14 2023" { } { } 0 0 "Processing started: %1!s!" 0 0 "Quartus II" 0 -1 1699430714560 ""} } { } 4 0 "Running %2!s! %1!s!" 0 0 "Quartus II" 0 -1 1699430714560 ""} { "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_sta cpld -c cpld " "Command: quartus_sta cpld -c cpld" { } { } 0 0 "Command: %1!s!" 0 0 "Quartus II" 0 -1 1699430714560 ""} { "Info" "0" "" "qsta_default_script.tcl version: #1" { } { } 0 0 "qsta_default_script.tcl version: #1" 0 0 "Quartus II" 0 0 1699430714644 ""} { "Info" "IDAT_DAT_STARTED" "" "Started post-fitting delay annotation" { } { } 0 306004 "Started post-fitting delay annotation" 0 0 "Quartus II" 0 -1 1699430714844 ""} { "Info" "IDAT_DAT_COMPLETED" "" "Delay annotation completed successfully" { } { } 0 306005 "Delay annotation completed successfully" 0 0 "Quartus II" 0 -1 1699430714844 ""} { "Warning" "WTDB_ANALYZE_COMB_LATCHES_NOT_SUPPORTED" "" "TimeQuest Timing Analyzer does not support the analysis of latches as synchronous elements for the currently selected device family." { } { } 0 335095 "TimeQuest Timing Analyzer does not support the analysis of latches as synchronous elements for the currently selected device family." 0 0 "Quartus II" 0 -1 1699430714905 ""} { "Critical Warning" "WSTA_SDC_NOT_FOUND" "cpld.sdc " "Synopsys Design Constraints File file not found: 'cpld.sdc'. A Synopsys Design Constraints File is required by the TimeQuest Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design." { } { } 1 332012 "Synopsys Design Constraints File file not found: '%1!s!'. A Synopsys Design Constraints File is required by the TimeQuest Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design." 0 0 "Quartus II" 0 -1 1699430714953 ""} { "Info" "ISTA_NO_CLOCK_FOUND_DERIVING" "base clocks \"derive_clocks -period 1.0\" " "No user constrained base clocks found in the design. Calling \"derive_clocks -period 1.0\"" { } { } 0 332142 "No user constrained %1!s! found in the design. Calling %2!s!" 0 0 "Quartus II" 0 -1 1699430714953 ""} { "Info" "ISTA_DERIVE_CLOCKS_INFO" "Deriving Clocks " "Deriving Clocks" { { "Info" "ISTA_DERIVE_CLOCKS_INFO" "create_clock -period 1.000 -name cf0 cf0 " "create_clock -period 1.000 -name cf0 cf0" { } { } 0 332105 "%1!s!" 0 0 "Quartus II" 0 -1 1699430714953 ""} { "Info" "ISTA_DERIVE_CLOCKS_INFO" "create_clock -period 1.000 -name bd2400 bd2400 " "create_clock -period 1.000 -name bd2400 bd2400" { } { } 0 332105 "%1!s!" 0 0 "Quartus II" 0 -1 1699430714953 ""} { "Info" "ISTA_DERIVE_CLOCKS_INFO" "create_clock -period 1.000 -name bd4800 bd4800 " "create_clock -period 1.000 -name bd4800 bd4800" { } { } 0 332105 "%1!s!" 0 0 "Quartus II" 0 -1 1699430714953 ""} { "Info" "ISTA_DERIVE_CLOCKS_INFO" "create_clock -period 1.000 -name bd9600 bd9600 " "create_clock -period 1.000 -name bd9600 bd9600" { } { } 0 332105 "%1!s!" 0 0 "Quartus II" 0 -1 1699430714953 ""} { "Info" "ISTA_DERIVE_CLOCKS_INFO" "create_clock -period 1.000 -name bd19200 bd19200 " "create_clock -period 1.000 -name bd19200 bd19200" { } { } 0 332105 "%1!s!" 0 0 "Quartus II" 0 -1 1699430714953 ""} { "Info" "ISTA_DERIVE_CLOCKS_INFO" "create_clock -period 1.000 -name bd38400 bd38400 " "create_clock -period 1.000 -name bd38400 bd38400" { } { } 0 332105 "%1!s!" 0 0 "Quartus II" 0 -1 1699430714953 ""} { "Info" "ISTA_DERIVE_CLOCKS_INFO" "create_clock -period 1.000 -name n_t_1x n_t_1x " "create_clock -period 1.000 -name n_t_1x n_t_1x" { } { } 0 332105 "%1!s!" 0 0 "Quartus II" 0 -1 1699430714953 ""} { "Info" "ISTA_DERIVE_CLOCKS_INFO" "create_clock -period 1.000 -name bd115200 bd115200 " "create_clock -period 1.000 -name bd115200 bd115200" { } { } 0 332105 "%1!s!" 0 0 "Quartus II" 0 -1 1699430714953 ""} { "Info" "ISTA_DERIVE_CLOCKS_INFO" "create_clock -period 1.000 -name clk clk " "create_clock -period 1.000 -name clk clk" { } { } 0 332105 "%1!s!" 0 0 "Quartus II" 0 -1 1699430714953 ""} { "Info" "ISTA_DERIVE_CLOCKS_INFO" "create_clock -period 1.000 -name bd1200 bd1200 " "create_clock -period 1.000 -name bd1200 bd1200" { } { } 0 332105 "%1!s!" 0 0 "Quartus II" 0 -1 1699430714953 ""} { "Info" "ISTA_DERIVE_CLOCKS_INFO" "create_clock -period 1.000 -name bd600 bd600 " "create_clock -period 1.000 -name bd600 bd600" { } { } 0 332105 "%1!s!" 0 0 "Quartus II" 0 -1 1699430714953 ""} } { } 0 332105 "%1!s!" 0 0 "Quartus II" 0 -1 1699430714953 ""} { "Warning" "WSTA_SCC_LOOP" "2 " "Found combinational loop of 2 nodes" { { "Warning" "WSTA_SCC_NODE" "m8650d\|line~10\|\[3\] " "Node \"m8650d\|line~10\|\[3\]\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1699430714953 ""} { "Warning" "WSTA_SCC_NODE" "m8650d\|line~10\|dataout " "Node \"m8650d\|line~10\|dataout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1699430714953 ""} } { { "M8650D.v" "" { Text "//wsl.localhost/Debian/home/vrs/Verilog/projects/32k-Omnibus/M8650D.v" 122 -1 0 } } } 0 332125 "Found combinational loop of %1!d! nodes" 0 0 "Quartus II" 0 -1 1699430714953 ""} { "Warning" "WSTA_SCC_LOOP" "2 " "Found combinational loop of 2 nodes" { { "Warning" "WSTA_SCC_NODE" "m8650d\|line_m~10\|dataout " "Node \"m8650d\|line_m~10\|dataout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1699430714953 ""} { "Warning" "WSTA_SCC_NODE" "m8650d\|line_m~10\|\[3\] " "Node \"m8650d\|line_m~10\|\[3\]\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1699430714953 ""} } { { "M8650D.v" "" { Text "//wsl.localhost/Debian/home/vrs/Verilog/projects/32k-Omnibus/M8650D.v" 180 -1 0 } } } 0 332125 "Found combinational loop of %1!d! nodes" 0 0 "Quartus II" 0 -1 1699430714953 ""} { "Warning" "WSTA_SCC_LOOP" "2 " "Found combinational loop of 2 nodes" { { "Warning" "WSTA_SCC_NODE" "m8650d\|tx_data~9\|dataout " "Node \"m8650d\|tx_data~9\|dataout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1699430714953 ""} { "Warning" "WSTA_SCC_NODE" "m8650d\|tx_data~9\|\[3\] " "Node \"m8650d\|tx_data~9\|\[3\]\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1699430714953 ""} } { { "M8650D.v" "" { Text "//wsl.localhost/Debian/home/vrs/Verilog/projects/32k-Omnibus/M8650D.v" 251 -1 0 } } } 0 332125 "Found combinational loop of %1!d! nodes" 0 0 "Quartus II" 0 -1 1699430714953 ""} { "Warning" "WSTA_SCC_LOOP" "2 " "Found combinational loop of 2 nodes" { { "Warning" "WSTA_SCC_NODE" "m8650d\|tx_data_m~16\|dataout " "Node \"m8650d\|tx_data_m~16\|dataout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1699430714953 ""} { "Warning" "WSTA_SCC_NODE" "m8650d\|tx_data_m~16\|\[2\] " "Node \"m8650d\|tx_data_m~16\|\[2\]\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1699430714953 ""} } { { "M8650D.v" "" { Text "//wsl.localhost/Debian/home/vrs/Verilog/projects/32k-Omnibus/M8650D.v" 211 -1 0 } } } 0 332125 "Found combinational loop of %1!d! nodes" 0 0 "Quartus II" 0 -1 1699430714953 ""} { "Warning" "WSTA_SCC_LOOP" "2 " "Found combinational loop of 2 nodes" { { "Warning" "WSTA_SCC_NODE" "m8650d\|start_l~9\|dataout " "Node \"m8650d\|start_l~9\|dataout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1699430714953 ""} { "Warning" "WSTA_SCC_NODE" "m8650d\|start_l~9\|\[2\] " "Node \"m8650d\|start_l~9\|\[2\]\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1699430714953 ""} } { { "M8650D.v" "" { Text "//wsl.localhost/Debian/home/vrs/Verilog/projects/32k-Omnibus/M8650D.v" 236 -1 0 } } } 0 332125 "Found combinational loop of %1!d! nodes" 0 0 "Quartus II" 0 -1 1699430714953 ""} { "Warning" "WSTA_SCC_LOOP" "2 " "Found combinational loop of 2 nodes" { { "Warning" "WSTA_SCC_NODE" "m8650d\|start_l_m~8\|dataout " "Node \"m8650d\|start_l_m~8\|dataout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1699430714953 ""} { "Warning" "WSTA_SCC_NODE" "m8650d\|start_l_m~8\|\[1\] " "Node \"m8650d\|start_l_m~8\|\[1\]\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1699430714953 ""} } { { "M8650D.v" "" { Text "//wsl.localhost/Debian/home/vrs/Verilog/projects/32k-Omnibus/M8650D.v" 208 -1 0 } } } 0 332125 "Found combinational loop of %1!d! nodes" 0 0 "Quartus II" 0 -1 1699430714953 ""} { "Warning" "WSTA_SCC_LOOP" "2 " "Found combinational loop of 2 nodes" { { "Warning" "WSTA_SCC_NODE" "m8650d\|rflg_l~9\|dataout " "Node \"m8650d\|rflg_l~9\|dataout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1699430714953 ""} { "Warning" "WSTA_SCC_NODE" "m8650d\|rflg_l~9\|\[2\] " "Node \"m8650d\|rflg_l~9\|\[2\]\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1699430714953 ""} } { { "M8650D.v" "" { Text "//wsl.localhost/Debian/home/vrs/Verilog/projects/32k-Omnibus/M8650D.v" 254 -1 0 } } } 0 332125 "Found combinational loop of %1!d! nodes" 0 0 "Quartus II" 0 -1 1699430714953 ""} { "Warning" "WSTA_SCC_LOOP" "2 " "Found combinational loop of 2 nodes" { { "Warning" "WSTA_SCC_NODE" "m8650d\|rflg_l_m~9\|dataout " "Node \"m8650d\|rflg_l_m~9\|dataout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1699430714953 ""} { "Warning" "WSTA_SCC_NODE" "m8650d\|rflg_l_m~9\|\[2\] " "Node \"m8650d\|rflg_l_m~9\|\[2\]\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1699430714953 ""} } { { "M8650D.v" "" { Text "//wsl.localhost/Debian/home/vrs/Verilog/projects/32k-Omnibus/M8650D.v" 204 -1 0 } } } 0 332125 "Found combinational loop of %1!d! nodes" 0 0 "Quartus II" 0 -1 1699430714953 ""} { "Warning" "WSTA_SCC_LOOP" "212 " "Found combinational loop of 212 nodes" { { "Warning" "WSTA_SCC_NODE" "m8650d\|n_t_40x~6\|dataout " "Node \"m8650d\|n_t_40x~6\|dataout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1699430714953 ""} { "Warning" "WSTA_SCC_NODE" "m8650d\|n_t_40x~6\|\[2\] " "Node \"m8650d\|n_t_40x~6\|\[2\]\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1699430714953 ""} { "Warning" "WSTA_SCC_NODE" "m8650d\|last_unit_m~9\|\[0\] " "Node \"m8650d\|last_unit_m~9\|\[0\]\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1699430714953 ""} { "Warning" "WSTA_SCC_NODE" "m8650d\|last_unit_m~9\|dataout " "Node \"m8650d\|last_unit_m~9\|dataout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1699430714953 ""} { "Warning" "WSTA_SCC_NODE" "m8650d\|last_unit_m~9\|\[2\] " "Node \"m8650d\|last_unit_m~9\|\[2\]\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1699430714953 ""} { "Warning" "WSTA_SCC_NODE" "m8650d\|last_unit~9\|\[0\] " "Node \"m8650d\|last_unit~9\|\[0\]\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1699430714953 ""} { "Warning" "WSTA_SCC_NODE" "m8650d\|last_unit~9\|dataout " "Node \"m8650d\|last_unit~9\|dataout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1699430714953 ""} { "Warning" "WSTA_SCC_NODE" "m8650d\|n_t_43x~9\|\[4\] " "Node \"m8650d\|n_t_43x~9\|\[4\]\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1699430714953 ""} { "Warning" "WSTA_SCC_NODE" "m8650d\|n_t_43x~9\|dataout " "Node \"m8650d\|n_t_43x~9\|dataout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1699430714953 ""} { "Warning" "WSTA_SCC_NODE" "m8650d\|n_t_43x~9\|\[2\] " "Node \"m8650d\|n_t_43x~9\|\[2\]\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1699430714953 ""} { "Warning" "WSTA_SCC_NODE" "m8650d\|n_t_75x~9\|\[1\] " "Node \"m8650d\|n_t_75x~9\|\[1\]\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1699430714953 ""} { "Warning" "WSTA_SCC_NODE" "m8650d\|n_t_75x~9\|dataout " "Node \"m8650d\|n_t_75x~9\|dataout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1699430714953 ""} { "Warning" "WSTA_SCC_NODE" "m8650d\|p_pulse_l~9\|\[3\] " "Node \"m8650d\|p_pulse_l~9\|\[3\]\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1699430714953 ""} { "Warning" "WSTA_SCC_NODE" "m8650d\|p_pulse_l~9\|dataout " "Node \"m8650d\|p_pulse_l~9\|dataout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1699430714953 ""} { "Warning" "WSTA_SCC_NODE" "m8650d\|n_t_37x_m~2sexp\|datain\[1\] " "Node \"m8650d\|n_t_37x_m~2sexp\|datain\[1\]\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1699430714953 ""} { "Warning" "WSTA_SCC_NODE" "m8650d\|n_t_37x_m~2sexp\|dataout " "Node \"m8650d\|n_t_37x_m~2sexp\|dataout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1699430714953 ""} { "Warning" "WSTA_SCC_NODE" "m8650d\|n_t_37x_m~10\|\[2\] " "Node \"m8650d\|n_t_37x_m~10\|\[2\]\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1699430714953 ""} { "Warning" "WSTA_SCC_NODE" "m8650d\|n_t_37x_m~10\|dataout " "Node \"m8650d\|n_t_37x_m~10\|dataout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1699430714953 ""} { "Warning" "WSTA_SCC_NODE" "m8650d\|n_t_37x_m~10\|\[1\] " "Node \"m8650d\|n_t_37x_m~10\|\[1\]\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1699430714953 ""} { "Warning" "WSTA_SCC_NODE" "m8650d\|n_t_37x~6\|\[0\] " "Node \"m8650d\|n_t_37x~6\|\[0\]\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1699430714953 ""} { "Warning" "WSTA_SCC_NODE" "m8650d\|n_t_37x~6\|dataout " "Node \"m8650d\|n_t_37x~6\|dataout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1699430714953 ""} { "Warning" "WSTA_SCC_NODE" "m8650d\|n_t_37x~6\|\[2\] " "Node \"m8650d\|n_t_37x~6\|\[2\]\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1699430714953 ""} { "Warning" "WSTA_SCC_NODE" "m8650d\|n_t_38x_m~2sexp\|datain\[1\] " "Node \"m8650d\|n_t_38x_m~2sexp\|datain\[1\]\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1699430714953 ""} { "Warning" "WSTA_SCC_NODE" "m8650d\|n_t_38x_m~2sexp\|dataout " "Node \"m8650d\|n_t_38x_m~2sexp\|dataout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1699430714953 ""} { "Warning" "WSTA_SCC_NODE" "m8650d\|n_t_38x_m~10\|\[2\] " "Node \"m8650d\|n_t_38x_m~10\|\[2\]\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1699430714953 ""} { "Warning" "WSTA_SCC_NODE" "m8650d\|n_t_38x_m~10\|dataout " "Node \"m8650d\|n_t_38x_m~10\|dataout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1699430714953 ""} { "Warning" "WSTA_SCC_NODE" "m8650d\|n_t_38x_m~10\|\[1\] " "Node \"m8650d\|n_t_38x_m~10\|\[1\]\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1699430714953 ""} { "Warning" "WSTA_SCC_NODE" "m8650d\|n_t_38x~6\|\[0\] " "Node \"m8650d\|n_t_38x~6\|\[0\]\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1699430714953 ""} { "Warning" "WSTA_SCC_NODE" "m8650d\|n_t_38x~6\|dataout " "Node \"m8650d\|n_t_38x~6\|dataout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1699430714953 ""} { "Warning" "WSTA_SCC_NODE" "m8650d\|n_t_38x~6\|\[2\] " "Node \"m8650d\|n_t_38x~6\|\[2\]\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1699430714953 ""} { "Warning" "WSTA_SCC_NODE" "m8650d\|n_t_39x_m~2sexp\|datain\[1\] " "Node \"m8650d\|n_t_39x_m~2sexp\|datain\[1\]\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1699430714953 ""} { "Warning" "WSTA_SCC_NODE" "m8650d\|n_t_39x_m~2sexp\|dataout " "Node \"m8650d\|n_t_39x_m~2sexp\|dataout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1699430714953 ""} { "Warning" "WSTA_SCC_NODE" "m8650d\|n_t_39x_m~10\|\[2\] " "Node \"m8650d\|n_t_39x_m~10\|\[2\]\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1699430714953 ""} { "Warning" "WSTA_SCC_NODE" "m8650d\|n_t_39x_m~10\|dataout " "Node \"m8650d\|n_t_39x_m~10\|dataout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1699430714953 ""} { "Warning" "WSTA_SCC_NODE" "m8650d\|n_t_39x_m~10\|\[1\] " "Node \"m8650d\|n_t_39x_m~10\|\[1\]\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1699430714953 ""} { "Warning" "WSTA_SCC_NODE" "m8650d\|n_t_39x~6\|\[0\] " "Node \"m8650d\|n_t_39x~6\|\[0\]\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1699430714953 ""} { "Warning" "WSTA_SCC_NODE" "m8650d\|n_t_39x~6\|dataout " "Node \"m8650d\|n_t_39x~6\|dataout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1699430714953 ""} { "Warning" "WSTA_SCC_NODE" "m8650d\|n_t_39x~6\|\[2\] " "Node \"m8650d\|n_t_39x~6\|\[2\]\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1699430714953 ""} { "Warning" "WSTA_SCC_NODE" "m8650d\|n_t_40x_m~2sexp\|datain\[1\] " "Node \"m8650d\|n_t_40x_m~2sexp\|datain\[1\]\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1699430714953 ""} { "Warning" "WSTA_SCC_NODE" "m8650d\|n_t_40x_m~2sexp\|dataout " "Node \"m8650d\|n_t_40x_m~2sexp\|dataout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1699430714953 ""} { "Warning" "WSTA_SCC_NODE" "m8650d\|n_t_40x_m~10\|\[2\] " "Node \"m8650d\|n_t_40x_m~10\|\[2\]\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1699430714953 ""} { "Warning" "WSTA_SCC_NODE" "m8650d\|n_t_40x_m~10\|dataout " "Node \"m8650d\|n_t_40x_m~10\|dataout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1699430714953 ""} { "Warning" "WSTA_SCC_NODE" "m8650d\|n_t_40x_m~10\|\[1\] " "Node \"m8650d\|n_t_40x_m~10\|\[1\]\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1699430714953 ""} { "Warning" "WSTA_SCC_NODE" "m8650d\|n_t_40x~6\|\[0\] " "Node \"m8650d\|n_t_40x~6\|\[0\]\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1699430714953 ""} { "Warning" "WSTA_SCC_NODE" "m8650d\|n_t_30x_m~2sexp\|datain\[1\] " "Node \"m8650d\|n_t_30x_m~2sexp\|datain\[1\]\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1699430714953 ""} { "Warning" "WSTA_SCC_NODE" "m8650d\|n_t_30x_m~2sexp\|dataout " "Node \"m8650d\|n_t_30x_m~2sexp\|dataout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1699430714953 ""} { "Warning" "WSTA_SCC_NODE" "m8650d\|n_t_30x_m~10\|\[2\] " "Node \"m8650d\|n_t_30x_m~10\|\[2\]\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1699430714953 ""} { "Warning" "WSTA_SCC_NODE" "m8650d\|n_t_30x_m~10\|dataout " "Node \"m8650d\|n_t_30x_m~10\|dataout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1699430714953 ""} { "Warning" "WSTA_SCC_NODE" "m8650d\|n_t_30x_m~10\|\[1\] " "Node \"m8650d\|n_t_30x_m~10\|\[1\]\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1699430714953 ""} { "Warning" "WSTA_SCC_NODE" "m8650d\|n_t_30x~6\|\[0\] " "Node \"m8650d\|n_t_30x~6\|\[0\]\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1699430714953 ""} { "Warning" "WSTA_SCC_NODE" "m8650d\|n_t_30x~6\|dataout " "Node \"m8650d\|n_t_30x~6\|dataout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1699430714953 ""} { "Warning" "WSTA_SCC_NODE" "m8650d\|n_t_30x~6\|\[2\] " "Node \"m8650d\|n_t_30x~6\|\[2\]\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1699430714953 ""} { "Warning" "WSTA_SCC_NODE" "m8650d\|n_t_34x_m~2sexp\|datain\[1\] " "Node \"m8650d\|n_t_34x_m~2sexp\|datain\[1\]\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1699430714953 ""} { "Warning" "WSTA_SCC_NODE" "m8650d\|n_t_34x_m~2sexp\|dataout " "Node \"m8650d\|n_t_34x_m~2sexp\|dataout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1699430714953 ""} { "Warning" "WSTA_SCC_NODE" "m8650d\|n_t_34x_m~10\|\[2\] " "Node \"m8650d\|n_t_34x_m~10\|\[2\]\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1699430714953 ""} { "Warning" "WSTA_SCC_NODE" "m8650d\|n_t_34x_m~10\|dataout " "Node \"m8650d\|n_t_34x_m~10\|dataout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1699430714953 ""} { "Warning" "WSTA_SCC_NODE" "m8650d\|n_t_34x_m~10\|\[1\] " "Node \"m8650d\|n_t_34x_m~10\|\[1\]\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1699430714953 ""} { "Warning" "WSTA_SCC_NODE" "m8650d\|n_t_34x~6\|\[0\] " "Node \"m8650d\|n_t_34x~6\|\[0\]\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1699430714953 ""} { "Warning" "WSTA_SCC_NODE" "m8650d\|n_t_34x~6\|dataout " "Node \"m8650d\|n_t_34x~6\|dataout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1699430714953 ""} { "Warning" "WSTA_SCC_NODE" "m8650d\|n_t_34x~6\|\[2\] " "Node \"m8650d\|n_t_34x~6\|\[2\]\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1699430714953 ""} { "Warning" "WSTA_SCC_NODE" "m8650d\|n_t_36x_m~2sexp\|datain\[1\] " "Node \"m8650d\|n_t_36x_m~2sexp\|datain\[1\]\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1699430714953 ""} { "Warning" "WSTA_SCC_NODE" "m8650d\|n_t_36x_m~2sexp\|dataout " "Node \"m8650d\|n_t_36x_m~2sexp\|dataout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1699430714953 ""} { "Warning" "WSTA_SCC_NODE" "m8650d\|n_t_36x_m~10\|\[2\] " "Node \"m8650d\|n_t_36x_m~10\|\[2\]\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1699430714953 ""} { "Warning" "WSTA_SCC_NODE" "m8650d\|n_t_36x_m~10\|dataout " "Node \"m8650d\|n_t_36x_m~10\|dataout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1699430714953 ""} { "Warning" "WSTA_SCC_NODE" "m8650d\|n_t_36x_m~10\|\[1\] " "Node \"m8650d\|n_t_36x_m~10\|\[1\]\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1699430714953 ""} { "Warning" "WSTA_SCC_NODE" "m8650d\|n_t_36x~6\|\[0\] " "Node \"m8650d\|n_t_36x~6\|\[0\]\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1699430714953 ""} { "Warning" "WSTA_SCC_NODE" "m8650d\|n_t_36x~6\|dataout " "Node \"m8650d\|n_t_36x~6\|dataout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1699430714953 ""} { "Warning" "WSTA_SCC_NODE" "m8650d\|n_t_36x~6\|\[2\] " "Node \"m8650d\|n_t_36x~6\|\[2\]\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1699430714953 ""} { "Warning" "WSTA_SCC_NODE" "m8650d\|n_t_35x_m~2sexp\|datain\[1\] " "Node \"m8650d\|n_t_35x_m~2sexp\|datain\[1\]\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1699430714953 ""} { "Warning" "WSTA_SCC_NODE" "m8650d\|n_t_35x_m~2sexp\|dataout " "Node \"m8650d\|n_t_35x_m~2sexp\|dataout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1699430714953 ""} { "Warning" "WSTA_SCC_NODE" "m8650d\|n_t_35x_m~10\|\[2\] " "Node \"m8650d\|n_t_35x_m~10\|\[2\]\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1699430714953 ""} { "Warning" "WSTA_SCC_NODE" "m8650d\|n_t_35x_m~10\|dataout " "Node \"m8650d\|n_t_35x_m~10\|dataout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1699430714953 ""} { "Warning" "WSTA_SCC_NODE" "m8650d\|n_t_35x_m~10\|\[1\] " "Node \"m8650d\|n_t_35x_m~10\|\[1\]\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1699430714953 ""} { "Warning" "WSTA_SCC_NODE" "m8650d\|n_t_35x~6\|\[0\] " "Node \"m8650d\|n_t_35x~6\|\[0\]\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1699430714953 ""} { "Warning" "WSTA_SCC_NODE" "m8650d\|n_t_35x~6\|dataout " "Node \"m8650d\|n_t_35x~6\|dataout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1699430714953 ""} { "Warning" "WSTA_SCC_NODE" "m8650d\|n_t_35x~6\|\[2\] " "Node \"m8650d\|n_t_35x~6\|\[2\]\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1699430714953 ""} { "Warning" "WSTA_SCC_NODE" "m8650d\|n_t_37x_m~2sexp\|datain\[0\] " "Node \"m8650d\|n_t_37x_m~2sexp\|datain\[0\]\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1699430714953 ""} { "Warning" "WSTA_SCC_NODE" "m8650d\|n_t_34x_m~2sexp\|datain\[0\] " "Node \"m8650d\|n_t_34x_m~2sexp\|datain\[0\]\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1699430714953 ""} { "Warning" "WSTA_SCC_NODE" "m8650d\|n_t_36x_m~2sexp\|datain\[0\] " "Node \"m8650d\|n_t_36x_m~2sexp\|datain\[0\]\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1699430714953 ""} { "Warning" "WSTA_SCC_NODE" "m8650d\|n_t_35x_m~2sexp\|datain\[0\] " "Node \"m8650d\|n_t_35x_m~2sexp\|datain\[0\]\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1699430714953 ""} { "Warning" "WSTA_SCC_NODE" "m8650d\|n_t_38x_m~2sexp\|datain\[0\] " "Node \"m8650d\|n_t_38x_m~2sexp\|datain\[0\]\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1699430714953 ""} { "Warning" "WSTA_SCC_NODE" "m8650d\|n_t_39x_m~2sexp\|datain\[0\] " "Node \"m8650d\|n_t_39x_m~2sexp\|datain\[0\]\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1699430714953 ""} { "Warning" "WSTA_SCC_NODE" "m8650d\|n_t_40x_m~2sexp\|datain\[0\] " "Node \"m8650d\|n_t_40x_m~2sexp\|datain\[0\]\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1699430714953 ""} { "Warning" "WSTA_SCC_NODE" "m8650d\|p_pulse_l~9\|\[2\] " "Node \"m8650d\|p_pulse_l~9\|\[2\]\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1699430714953 ""} { "Warning" "WSTA_SCC_NODE" "m8650d\|n_t_41x~1\|\[1\] " "Node \"m8650d\|n_t_41x~1\|\[1\]\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1699430714953 ""} { "Warning" "WSTA_SCC_NODE" "m8650d\|n_t_41x~1\|dataout " "Node \"m8650d\|n_t_41x~1\|dataout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1699430714953 ""} { "Warning" "WSTA_SCC_NODE" "m8650d\|n_t_40x~6\|\[1\] " "Node \"m8650d\|n_t_40x~6\|\[1\]\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1699430714953 ""} { "Warning" "WSTA_SCC_NODE" "m8650d\|n_t_39x~6\|\[1\] " "Node \"m8650d\|n_t_39x~6\|\[1\]\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1699430714953 ""} { "Warning" "WSTA_SCC_NODE" "m8650d\|n_t_38x~6\|\[1\] " "Node \"m8650d\|n_t_38x~6\|\[1\]\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1699430714953 ""} { "Warning" "WSTA_SCC_NODE" "m8650d\|n_t_37x~6\|\[1\] " "Node \"m8650d\|n_t_37x~6\|\[1\]\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1699430714953 ""} { "Warning" "WSTA_SCC_NODE" "m8650d\|n_t_35x~6\|\[1\] " "Node \"m8650d\|n_t_35x~6\|\[1\]\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1699430714953 ""} { "Warning" "WSTA_SCC_NODE" "m8650d\|n_t_36x~6\|\[1\] " "Node \"m8650d\|n_t_36x~6\|\[1\]\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1699430714953 ""} { "Warning" "WSTA_SCC_NODE" "m8650d\|n_t_34x~6\|\[1\] " "Node \"m8650d\|n_t_34x~6\|\[1\]\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1699430714953 ""} { "Warning" "WSTA_SCC_NODE" "m8650d\|n_t_30x~6\|\[1\] " "Node \"m8650d\|n_t_30x~6\|\[1\]\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1699430714953 ""} { "Warning" "WSTA_SCC_NODE" "m8650d\|n_t_30x_m~10\|\[0\] " "Node \"m8650d\|n_t_30x_m~10\|\[0\]\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1699430714953 ""} { "Warning" "WSTA_SCC_NODE" "m8650d\|n_t_34x_m~10\|\[0\] " "Node \"m8650d\|n_t_34x_m~10\|\[0\]\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1699430714953 ""} { "Warning" "WSTA_SCC_NODE" "m8650d\|n_t_36x_m~10\|\[0\] " "Node \"m8650d\|n_t_36x_m~10\|\[0\]\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1699430714953 ""} { "Warning" "WSTA_SCC_NODE" "m8650d\|n_t_35x_m~10\|\[0\] " "Node \"m8650d\|n_t_35x_m~10\|\[0\]\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1699430714953 ""} { "Warning" "WSTA_SCC_NODE" "m8650d\|n_t_37x_m~10\|\[0\] " "Node \"m8650d\|n_t_37x_m~10\|\[0\]\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1699430714953 ""} { "Warning" "WSTA_SCC_NODE" "m8650d\|n_t_38x_m~10\|\[0\] " "Node \"m8650d\|n_t_38x_m~10\|\[0\]\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1699430714953 ""} { "Warning" "WSTA_SCC_NODE" "m8650d\|n_t_39x_m~10\|\[0\] " "Node \"m8650d\|n_t_39x_m~10\|\[0\]\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1699430714953 ""} { "Warning" "WSTA_SCC_NODE" "m8650d\|n_t_40x_m~10\|\[0\] " "Node \"m8650d\|n_t_40x_m~10\|\[0\]\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1699430714953 ""} { "Warning" "WSTA_SCC_NODE" "m8650d\|comb~13sexp\|datain\[0\] " "Node \"m8650d\|comb~13sexp\|datain\[0\]\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1699430714953 ""} { "Warning" "WSTA_SCC_NODE" "m8650d\|comb~13sexp\|dataout " "Node \"m8650d\|comb~13sexp\|dataout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1699430714953 ""} { "Warning" "WSTA_SCC_NODE" "m8650d\|p_pulse_l_m~9\|\[2\] " "Node \"m8650d\|p_pulse_l_m~9\|\[2\]\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1699430714953 ""} { "Warning" "WSTA_SCC_NODE" "m8650d\|p_pulse_l_m~9\|dataout " "Node \"m8650d\|p_pulse_l_m~9\|dataout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1699430714953 ""} { "Warning" "WSTA_SCC_NODE" "m8650d\|p_pulse_l_m~9\|\[1\] " "Node \"m8650d\|p_pulse_l_m~9\|\[1\]\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1699430714953 ""} { "Warning" "WSTA_SCC_NODE" "m8650d\|p_pulse_l~9\|\[0\] " "Node \"m8650d\|p_pulse_l~9\|\[0\]\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1699430714953 ""} { "Warning" "WSTA_SCC_NODE" "m8650d\|p_pulse_l_m~9\|\[0\] " "Node \"m8650d\|p_pulse_l_m~9\|\[0\]\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1699430714953 ""} { "Warning" "WSTA_SCC_NODE" "m8650d\|n_t_88x~9\|\[1\] " "Node \"m8650d\|n_t_88x~9\|\[1\]\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1699430714953 ""} { "Warning" "WSTA_SCC_NODE" "m8650d\|n_t_88x~9\|dataout " "Node \"m8650d\|n_t_88x~9\|dataout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1699430714953 ""} { "Warning" "WSTA_SCC_NODE" "m8650d\|spike_det_l~10\|\[5\] " "Node \"m8650d\|spike_det_l~10\|\[5\]\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1699430714953 ""} { "Warning" "WSTA_SCC_NODE" "m8650d\|spike_det_l~10\|dataout " "Node \"m8650d\|spike_det_l~10\|dataout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1699430714953 ""} { "Warning" "WSTA_SCC_NODE" "m8650d\|spike_det_l~10\|\[2\] " "Node \"m8650d\|spike_det_l~10\|\[2\]\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1699430714953 ""} { "Warning" "WSTA_SCC_NODE" "m8650d\|n_t_70x~4\|\[2\] " "Node \"m8650d\|n_t_70x~4\|\[2\]\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1699430714953 ""} { "Warning" "WSTA_SCC_NODE" "m8650d\|n_t_70x~4\|dataout " "Node \"m8650d\|n_t_70x~4\|dataout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1699430714953 ""} { "Warning" "WSTA_SCC_NODE" "m8650d\|rx_active~10\|\[1\] " "Node \"m8650d\|rx_active~10\|\[1\]\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1699430714953 ""} { "Warning" "WSTA_SCC_NODE" "m8650d\|rx_active~10\|dataout " "Node \"m8650d\|rx_active~10\|dataout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1699430714953 ""} { "Warning" "WSTA_SCC_NODE" "m8650d\|p_pulse_l~9\|\[1\] " "Node \"m8650d\|p_pulse_l~9\|\[1\]\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1699430714953 ""} { "Warning" "WSTA_SCC_NODE" "m8650d\|comb~13sexp\|datain\[1\] " "Node \"m8650d\|comb~13sexp\|datain\[1\]\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1699430714953 ""} { "Warning" "WSTA_SCC_NODE" "m8650d\|n_t_43x~9\|\[3\] " "Node \"m8650d\|n_t_43x~9\|\[3\]\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1699430714953 ""} { "Warning" "WSTA_SCC_NODE" "m8650d\|n_t_43x_m~9\|\[3\] " "Node \"m8650d\|n_t_43x_m~9\|\[3\]\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1699430714953 ""} { "Warning" "WSTA_SCC_NODE" "m8650d\|n_t_43x_m~9\|dataout " "Node \"m8650d\|n_t_43x_m~9\|dataout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1699430714953 ""} { "Warning" "WSTA_SCC_NODE" "m8650d\|n_t_43x_m~9\|\[2\] " "Node \"m8650d\|n_t_43x_m~9\|\[2\]\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1699430714953 ""} { "Warning" "WSTA_SCC_NODE" "m8650d\|n_t_43x~9\|\[0\] " "Node \"m8650d\|n_t_43x~9\|\[0\]\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1699430714953 ""} { "Warning" "WSTA_SCC_NODE" "m8650d\|rx_active~10\|\[3\] " "Node \"m8650d\|rx_active~10\|\[3\]\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1699430714953 ""} { "Warning" "WSTA_SCC_NODE" "m8650d\|rx_active_m~13\|\[5\] " "Node \"m8650d\|rx_active_m~13\|\[5\]\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1699430714953 ""} { "Warning" "WSTA_SCC_NODE" "m8650d\|rx_active_m~13\|dataout " "Node \"m8650d\|rx_active_m~13\|dataout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1699430714953 ""} { "Warning" "WSTA_SCC_NODE" "m8650d\|rx_active_m~13\|\[1\] " "Node \"m8650d\|rx_active_m~13\|\[1\]\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1699430714953 ""} { "Warning" "WSTA_SCC_NODE" "m8650d\|rx_active~10\|\[0\] " "Node \"m8650d\|rx_active~10\|\[0\]\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1699430714953 ""} { "Warning" "WSTA_SCC_NODE" "m8650d\|spike_det_l~10\|\[4\] " "Node \"m8650d\|spike_det_l~10\|\[4\]\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1699430714953 ""} { "Warning" "WSTA_SCC_NODE" "m8650d\|n_t_71x~2sexp\|datain\[2\] " "Node \"m8650d\|n_t_71x~2sexp\|datain\[2\]\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1699430714953 ""} { "Warning" "WSTA_SCC_NODE" "m8650d\|n_t_71x~2sexp\|dataout " "Node \"m8650d\|n_t_71x~2sexp\|dataout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1699430714953 ""} { "Warning" "WSTA_SCC_NODE" "m8650d\|spike_det_l~10\|\[6\] " "Node \"m8650d\|spike_det_l~10\|\[6\]\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1699430714953 ""} { "Warning" "WSTA_SCC_NODE" "m8650d\|spike_det_l_m~13\|\[1\] " "Node \"m8650d\|spike_det_l_m~13\|\[1\]\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1699430714953 ""} { "Warning" "WSTA_SCC_NODE" "m8650d\|spike_det_l_m~13\|dataout " "Node \"m8650d\|spike_det_l_m~13\|dataout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1699430714953 ""} { "Warning" "WSTA_SCC_NODE" "m8650d\|spike_det_l_m~13\|\[0\] " "Node \"m8650d\|spike_det_l_m~13\|\[0\]\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1699430714953 ""} { "Warning" "WSTA_SCC_NODE" "m8650d\|spike_det_l~10\|\[0\] " "Node \"m8650d\|spike_det_l~10\|\[0\]\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1699430714953 ""} { "Warning" "WSTA_SCC_NODE" "m8650d\|n_t_91x~1sexp\|datain\[0\] " "Node \"m8650d\|n_t_91x~1sexp\|datain\[0\]\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1699430714953 ""} { "Warning" "WSTA_SCC_NODE" "m8650d\|n_t_91x~1sexp\|dataout " "Node \"m8650d\|n_t_91x~1sexp\|dataout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1699430714953 ""} { "Warning" "WSTA_SCC_NODE" "m8650d\|last_unit~9\|\[3\] " "Node \"m8650d\|last_unit~9\|\[3\]\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1699430714953 ""} { "Warning" "WSTA_SCC_NODE" "m8650d\|last_unit_m~9\|\[3\] " "Node \"m8650d\|last_unit_m~9\|\[3\]\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1699430714953 ""} { "Warning" "WSTA_SCC_NODE" "m8650d\|ck_pulse~9\|\[3\] " "Node \"m8650d\|ck_pulse~9\|\[3\]\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1699430714953 ""} { "Warning" "WSTA_SCC_NODE" "m8650d\|ck_pulse~9\|dataout " "Node \"m8650d\|ck_pulse~9\|dataout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1699430714953 ""} { "Warning" "WSTA_SCC_NODE" "m8650d\|n_t_41x~1\|\[2\] " "Node \"m8650d\|n_t_41x~1\|\[2\]\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1699430714953 ""} { "Warning" "WSTA_SCC_NODE" "m8650d\|n_t_70x~4\|\[3\] " "Node \"m8650d\|n_t_70x~4\|\[3\]\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1699430714953 ""} { "Warning" "WSTA_SCC_NODE" "m8650d\|last_unit~9\|\[1\] " "Node \"m8650d\|last_unit~9\|\[1\]\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1699430714953 ""} { "Warning" "WSTA_SCC_NODE" "m8650d\|ck_pulse~9\|\[2\] " "Node \"m8650d\|ck_pulse~9\|\[2\]\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1699430714953 ""} { "Warning" "WSTA_SCC_NODE" "m8650d\|last_unit_m~9\|\[1\] " "Node \"m8650d\|last_unit_m~9\|\[1\]\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1699430714953 ""} { "Warning" "WSTA_SCC_NODE" "m8650d\|n_t_27x~1sexp\|datain\[0\] " "Node \"m8650d\|n_t_27x~1sexp\|datain\[0\]\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1699430714953 ""} { "Warning" "WSTA_SCC_NODE" "m8650d\|n_t_27x~1sexp\|dataout " "Node \"m8650d\|n_t_27x~1sexp\|dataout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1699430714953 ""} { "Warning" "WSTA_SCC_NODE" "m8650d\|n_t_88x~9\|\[3\] " "Node \"m8650d\|n_t_88x~9\|\[3\]\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1699430714953 ""} { "Warning" "WSTA_SCC_NODE" "m8650d\|n_t_88x_m~9\|\[3\] " "Node \"m8650d\|n_t_88x_m~9\|\[3\]\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1699430714953 ""} { "Warning" "WSTA_SCC_NODE" "m8650d\|n_t_88x_m~9\|dataout " "Node \"m8650d\|n_t_88x_m~9\|dataout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1699430714953 ""} { "Warning" "WSTA_SCC_NODE" "m8650d\|n_t_88x_m~9\|\[2\] " "Node \"m8650d\|n_t_88x_m~9\|\[2\]\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1699430714953 ""} { "Warning" "WSTA_SCC_NODE" "m8650d\|n_t_88x~9\|\[0\] " "Node \"m8650d\|n_t_88x~9\|\[0\]\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1699430714953 ""} { "Warning" "WSTA_SCC_NODE" "m8650d\|n_t_75x~9\|\[3\] " "Node \"m8650d\|n_t_75x~9\|\[3\]\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1699430714953 ""} { "Warning" "WSTA_SCC_NODE" "m8650d\|n_t_75x_m~9\|\[3\] " "Node \"m8650d\|n_t_75x_m~9\|\[3\]\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1699430714953 ""} { "Warning" "WSTA_SCC_NODE" "m8650d\|n_t_75x_m~9\|dataout " "Node \"m8650d\|n_t_75x_m~9\|dataout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1699430714953 ""} { "Warning" "WSTA_SCC_NODE" "m8650d\|n_t_75x_m~9\|\[2\] " "Node \"m8650d\|n_t_75x_m~9\|\[2\]\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1699430714953 ""} { "Warning" "WSTA_SCC_NODE" "m8650d\|n_t_75x~9\|\[0\] " "Node \"m8650d\|n_t_75x~9\|\[0\]\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1699430714953 ""} { "Warning" "WSTA_SCC_NODE" "m8650d\|n_t_80x~1sexp\|datain\[0\] " "Node \"m8650d\|n_t_80x~1sexp\|datain\[0\]\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1699430714953 ""} { "Warning" "WSTA_SCC_NODE" "m8650d\|n_t_80x~1sexp\|dataout " "Node \"m8650d\|n_t_80x~1sexp\|dataout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1699430714953 ""} { "Warning" "WSTA_SCC_NODE" "m8650d\|spike_det_l~10\|\[3\] " "Node \"m8650d\|spike_det_l~10\|\[3\]\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1699430714953 ""} { "Warning" "WSTA_SCC_NODE" "m8650d\|spike_det_l_m~5sexp\|datain\[1\] " "Node \"m8650d\|spike_det_l_m~5sexp\|datain\[1\]\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1699430714953 ""} { "Warning" "WSTA_SCC_NODE" "m8650d\|spike_det_l_m~5sexp\|dataout " "Node \"m8650d\|spike_det_l_m~5sexp\|dataout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1699430714953 ""} { "Warning" "WSTA_SCC_NODE" "m8650d\|spike_det_l_m~13\|\[2\] " "Node \"m8650d\|spike_det_l_m~13\|\[2\]\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1699430714953 ""} { "Warning" "WSTA_SCC_NODE" "m8650d\|n_t_70x~4\|\[4\] " "Node \"m8650d\|n_t_70x~4\|\[4\]\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1699430714953 ""} { "Warning" "WSTA_SCC_NODE" "m8650d\|ck_pulse~9\|\[5\] " "Node \"m8650d\|ck_pulse~9\|\[5\]\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1699430714953 ""} { "Warning" "WSTA_SCC_NODE" "m8650d\|ck_pulse_m~9\|\[2\] " "Node \"m8650d\|ck_pulse_m~9\|\[2\]\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1699430714953 ""} { "Warning" "WSTA_SCC_NODE" "m8650d\|ck_pulse_m~9\|dataout " "Node \"m8650d\|ck_pulse_m~9\|dataout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1699430714953 ""} { "Warning" "WSTA_SCC_NODE" "m8650d\|ck_pulse_m~9\|\[1\] " "Node \"m8650d\|ck_pulse_m~9\|\[1\]\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1699430714953 ""} { "Warning" "WSTA_SCC_NODE" "m8650d\|ck_pulse~9\|\[0\] " "Node \"m8650d\|ck_pulse~9\|\[0\]\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1699430714953 ""} { "Warning" "WSTA_SCC_NODE" "m8650d\|comb~12\|\[4\] " "Node \"m8650d\|comb~12\|\[4\]\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1699430714953 ""} { "Warning" "WSTA_SCC_NODE" "m8650d\|comb~12\|dataout " "Node \"m8650d\|comb~12\|dataout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1699430714953 ""} { "Warning" "WSTA_SCC_NODE" "m8650d\|rx_active_m~13\|\[0\] " "Node \"m8650d\|rx_active_m~13\|\[0\]\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1699430714953 ""} { "Warning" "WSTA_SCC_NODE" "m8650d\|n_t_27x~4\|datain\[0\] " "Node \"m8650d\|n_t_27x~4\|datain\[0\]\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1699430714953 ""} { "Warning" "WSTA_SCC_NODE" "m8650d\|n_t_27x~4\|dataout " "Node \"m8650d\|n_t_27x~4\|dataout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1699430714953 ""} { "Warning" "WSTA_SCC_NODE" "m8650d\|n_t_76x~1sexp\|datain\[1\] " "Node \"m8650d\|n_t_76x~1sexp\|datain\[1\]\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1699430714953 ""} { "Warning" "WSTA_SCC_NODE" "m8650d\|n_t_76x~1sexp\|dataout " "Node \"m8650d\|n_t_76x~1sexp\|dataout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1699430714953 ""} { "Warning" "WSTA_SCC_NODE" "m8650d\|rx_div_m~6\|\[2\] " "Node \"m8650d\|rx_div_m~6\|\[2\]\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1699430714953 ""} { "Warning" "WSTA_SCC_NODE" "m8650d\|rx_div_m~6\|dataout " "Node \"m8650d\|rx_div_m~6\|dataout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1699430714953 ""} { "Warning" "WSTA_SCC_NODE" "m8650d\|rx_div_m~6\|\[1\] " "Node \"m8650d\|rx_div_m~6\|\[1\]\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1699430714953 ""} { "Warning" "WSTA_SCC_NODE" "m8650d\|rx_div~6\|\[0\] " "Node \"m8650d\|rx_div~6\|\[0\]\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1699430714953 ""} { "Warning" "WSTA_SCC_NODE" "m8650d\|rx_div~6\|dataout " "Node \"m8650d\|rx_div~6\|dataout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1699430714953 ""} { "Warning" "WSTA_SCC_NODE" "m8650d\|n_t_43x~9\|\[1\] " "Node \"m8650d\|n_t_43x~9\|\[1\]\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1699430714953 ""} { "Warning" "WSTA_SCC_NODE" "m8650d\|rx_div~6\|\[2\] " "Node \"m8650d\|rx_div~6\|\[2\]\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1699430714953 ""} { "Warning" "WSTA_SCC_NODE" "m8650d\|n_t_76x~1sexp\|datain\[0\] " "Node \"m8650d\|n_t_76x~1sexp\|datain\[0\]\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1699430714953 ""} { "Warning" "WSTA_SCC_NODE" "m8650d\|n_t_43x_m~9\|\[1\] " "Node \"m8650d\|n_t_43x_m~9\|\[1\]\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1699430714953 ""} { "Warning" "WSTA_SCC_NODE" "m8650d\|comb~12\|\[1\] " "Node \"m8650d\|comb~12\|\[1\]\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1699430714953 ""} { "Warning" "WSTA_SCC_NODE" "m8650d\|n_t_91x~1sexp\|datain\[1\] " "Node \"m8650d\|n_t_91x~1sexp\|datain\[1\]\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1699430714953 ""} { "Warning" "WSTA_SCC_NODE" "m8650d\|ck_pulse~9\|\[4\] " "Node \"m8650d\|ck_pulse~9\|\[4\]\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1699430714953 ""} { "Warning" "WSTA_SCC_NODE" "m8650d\|n_t_88x~9\|\[2\] " "Node \"m8650d\|n_t_88x~9\|\[2\]\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1699430714953 ""} { "Warning" "WSTA_SCC_NODE" "m8650d\|n_t_88x_m~9\|\[0\] " "Node \"m8650d\|n_t_88x_m~9\|\[0\]\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1699430714953 ""} { "Warning" "WSTA_SCC_NODE" "m8650d\|n_t_80x~1sexp\|datain\[1\] " "Node \"m8650d\|n_t_80x~1sexp\|datain\[1\]\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1699430714953 ""} { "Warning" "WSTA_SCC_NODE" "m8650d\|n_t_75x~9\|\[2\] " "Node \"m8650d\|n_t_75x~9\|\[2\]\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1699430714953 ""} { "Warning" "WSTA_SCC_NODE" "m8650d\|n_t_75x_m~9\|\[0\] " "Node \"m8650d\|n_t_75x_m~9\|\[0\]\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1699430714953 ""} { "Warning" "WSTA_SCC_NODE" "m8650d\|n_t_88x_m~9\|\[1\] " "Node \"m8650d\|n_t_88x_m~9\|\[1\]\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1699430714953 ""} { "Warning" "WSTA_SCC_NODE" "m8650d\|n_t_75x_m~9\|\[1\] " "Node \"m8650d\|n_t_75x_m~9\|\[1\]\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1699430714953 ""} { "Warning" "WSTA_SCC_NODE" "m8650d\|n_t_43x_m~9\|\[0\] " "Node \"m8650d\|n_t_43x_m~9\|\[0\]\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1699430714953 ""} { "Warning" "WSTA_SCC_NODE" "m8650d\|n_t_41x~1\|\[0\] " "Node \"m8650d\|n_t_41x~1\|\[0\]\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1699430714953 ""} { "Warning" "WSTA_SCC_NODE" "m8650d\|n_t_43x_m~9\|\[4\] " "Node \"m8650d\|n_t_43x_m~9\|\[4\]\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1699430714953 ""} { "Warning" "WSTA_SCC_NODE" "m8650d\|n_t_27x~4\|datain\[1\] " "Node \"m8650d\|n_t_27x~4\|datain\[1\]\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1699430714953 ""} { "Warning" "WSTA_SCC_NODE" "m8650d\|rx_active~10\|\[6\] " "Node \"m8650d\|rx_active~10\|\[6\]\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1699430714953 ""} { "Warning" "WSTA_SCC_NODE" "m8650d\|rx_active_m~13\|\[6\] " "Node \"m8650d\|rx_active_m~13\|\[6\]\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1699430714953 ""} { "Warning" "WSTA_SCC_NODE" "m8650d\|n_t_71x~2sexp\|datain\[3\] " "Node \"m8650d\|n_t_71x~2sexp\|datain\[3\]\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1699430714953 ""} { "Warning" "WSTA_SCC_NODE" "m8650d\|n_t_70x~4\|\[0\] " "Node \"m8650d\|n_t_70x~4\|\[0\]\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1699430714953 ""} { "Warning" "WSTA_SCC_NODE" "m8650d\|last_unit~9\|\[2\] " "Node \"m8650d\|last_unit~9\|\[2\]\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1699430714953 ""} { "Warning" "WSTA_SCC_NODE" "m8650d\|n_t_27x~1sexp\|datain\[1\] " "Node \"m8650d\|n_t_27x~1sexp\|datain\[1\]\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1699430714953 ""} { "Warning" "WSTA_SCC_NODE" "m8650d\|n_t_75x~9\|\[4\] " "Node \"m8650d\|n_t_75x~9\|\[4\]\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1699430714953 ""} { "Warning" "WSTA_SCC_NODE" "m8650d\|n_t_75x_m~9\|\[4\] " "Node \"m8650d\|n_t_75x_m~9\|\[4\]\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1699430714953 ""} { "Warning" "WSTA_SCC_NODE" "m8650d\|comb~12\|\[5\] " "Node \"m8650d\|comb~12\|\[5\]\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1699430714953 ""} } { { "M8650D.v" "" { Text "//wsl.localhost/Debian/home/vrs/Verilog/projects/32k-Omnibus/M8650D.v" 230 -1 0 } } { "M8650D.v" "" { Text "//wsl.localhost/Debian/home/vrs/Verilog/projects/32k-Omnibus/M8650D.v" 179 -1 0 } } { "M8650D.v" "" { Text "//wsl.localhost/Debian/home/vrs/Verilog/projects/32k-Omnibus/M8650D.v" 225 -1 0 } } { "M8650D.v" "" { Text "//wsl.localhost/Debian/home/vrs/Verilog/projects/32k-Omnibus/M8650D.v" 216 -1 0 } } { "M8650D.v" "" { Text "//wsl.localhost/Debian/home/vrs/Verilog/projects/32k-Omnibus/M8650D.v" 217 -1 0 } } { "M8650D.v" "" { Text "//wsl.localhost/Debian/home/vrs/Verilog/projects/32k-Omnibus/M8650D.v" 224 -1 0 } } { "M8650D.v" "" { Text "//wsl.localhost/Debian/home/vrs/Verilog/projects/32k-Omnibus/M8650D.v" 188 -1 0 } } { "M8650D.v" "" { Text "//wsl.localhost/Debian/home/vrs/Verilog/projects/32k-Omnibus/M8650D.v" 227 -1 0 } } { "M8650D.v" "" { Text "//wsl.localhost/Debian/home/vrs/Verilog/projects/32k-Omnibus/M8650D.v" 189 -1 0 } } { "M8650D.v" "" { Text "//wsl.localhost/Debian/home/vrs/Verilog/projects/32k-Omnibus/M8650D.v" 228 -1 0 } } { "M8650D.v" "" { Text "//wsl.localhost/Debian/home/vrs/Verilog/projects/32k-Omnibus/M8650D.v" 190 -1 0 } } { "M8650D.v" "" { Text "//wsl.localhost/Debian/home/vrs/Verilog/projects/32k-Omnibus/M8650D.v" 229 -1 0 } } { "M8650D.v" "" { Text "//wsl.localhost/Debian/home/vrs/Verilog/projects/32k-Omnibus/M8650D.v" 191 -1 0 } } { "M8650D.v" "" { Text "//wsl.localhost/Debian/home/vrs/Verilog/projects/32k-Omnibus/M8650D.v" 184 -1 0 } } { "M8650D.v" "" { Text "//wsl.localhost/Debian/home/vrs/Verilog/projects/32k-Omnibus/M8650D.v" 141 -1 0 } } { "M8650D.v" "" { Text "//wsl.localhost/Debian/home/vrs/Verilog/projects/32k-Omnibus/M8650D.v" 185 -1 0 } } { "M8650D.v" "" { Text "//wsl.localhost/Debian/home/vrs/Verilog/projects/32k-Omnibus/M8650D.v" 221 -1 0 } } { "M8650D.v" "" { Text "//wsl.localhost/Debian/home/vrs/Verilog/projects/32k-Omnibus/M8650D.v" 187 -1 0 } } { "M8650D.v" "" { Text "//wsl.localhost/Debian/home/vrs/Verilog/projects/32k-Omnibus/M8650D.v" 222 -1 0 } } { "M8650D.v" "" { Text "//wsl.localhost/Debian/home/vrs/Verilog/projects/32k-Omnibus/M8650D.v" 186 -1 0 } } { "M8650D.v" "" { Text "//wsl.localhost/Debian/home/vrs/Verilog/projects/32k-Omnibus/M8650D.v" 223 -1 0 } } { "M8650D.v" "" { Text "//wsl.localhost/Debian/home/vrs/Verilog/projects/32k-Omnibus/M8650D.v" 282 -1 0 } } { "M8650D.v" "" { Text "//wsl.localhost/Debian/home/vrs/Verilog/projects/32k-Omnibus/M8650D.v" 202 -1 0 } } { "M8650D.v" "" { Text "//wsl.localhost/Debian/home/vrs/Verilog/projects/32k-Omnibus/M8650D.v" 226 -1 0 } } { "M8650D.v" "" { Text "//wsl.localhost/Debian/home/vrs/Verilog/projects/32k-Omnibus/M8650D.v" 232 -1 0 } } { "M8650D.v" "" { Text "//wsl.localhost/Debian/home/vrs/Verilog/projects/32k-Omnibus/M8650D.v" 295 -1 0 } } { "M8650D.v" "" { Text "//wsl.localhost/Debian/home/vrs/Verilog/projects/32k-Omnibus/M8650D.v" 157 -1 0 } } { "M8650D.v" "" { Text "//wsl.localhost/Debian/home/vrs/Verilog/projects/32k-Omnibus/M8650D.v" 192 -1 0 } } { "M8650D.v" "" { Text "//wsl.localhost/Debian/home/vrs/Verilog/projects/32k-Omnibus/M8650D.v" 205 -1 0 } } { "M8650D.v" "" { Text "//wsl.localhost/Debian/home/vrs/Verilog/projects/32k-Omnibus/M8650D.v" 207 -1 0 } } { "M8650D.v" "" { Text "//wsl.localhost/Debian/home/vrs/Verilog/projects/32k-Omnibus/M8650D.v" 215 -1 0 } } { "M8650D.v" "" { Text "//wsl.localhost/Debian/home/vrs/Verilog/projects/32k-Omnibus/M8650D.v" 139 -1 0 } } { "M8650D.v" "" { Text "//wsl.localhost/Debian/home/vrs/Verilog/projects/32k-Omnibus/M8650D.v" 201 -1 0 } } { "M8650D.v" "" { Text "//wsl.localhost/Debian/home/vrs/Verilog/projects/32k-Omnibus/M8650D.v" 200 -1 0 } } { "M8650D.v" "" { Text "//wsl.localhost/Debian/home/vrs/Verilog/projects/32k-Omnibus/M8650D.v" 298 -1 0 } } { "M8650D.v" "" { Text "//wsl.localhost/Debian/home/vrs/Verilog/projects/32k-Omnibus/M8650D.v" 171 -1 0 } } { "M8650D.v" "" { Text "//wsl.localhost/Debian/home/vrs/Verilog/projects/32k-Omnibus/M8650D.v" 297 -1 0 } } { "M8650D.v" "" { Text "//wsl.localhost/Debian/home/vrs/Verilog/projects/32k-Omnibus/M8650D.v" 206 -1 0 } } { "M8650D.v" "" { Text "//wsl.localhost/Debian/home/vrs/Verilog/projects/32k-Omnibus/M8650D.v" 214 -1 0 } } } 0 332125 "Found combinational loop of %1!d! nodes" 0 0 "Quartus II" 0 -1 1699430714953 ""} { "Critical Warning" "WSTA_SCC_LOOP_TOO_BIG" "212 " "Design contains combinational loop of 212 nodes. Estimating the delays through the loop." { } { } 1 332081 "Design contains combinational loop of %1!d! nodes. Estimating the delays through the loop." 0 0 "Quartus II" 0 -1 1699430714968 ""} { "Warning" "WSTA_SCC_LOOP" "2 " "Found combinational loop of 2 nodes" { { "Warning" "WSTA_SCC_NODE" "m8650d\|tflg_l~10\|dataout " "Node \"m8650d\|tflg_l~10\|dataout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1699430714968 ""} { "Warning" "WSTA_SCC_NODE" "m8650d\|tflg_l~10\|\[3\] " "Node \"m8650d\|tflg_l~10\|\[3\]\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1699430714968 ""} } { { "M8650D.v" "" { Text "//wsl.localhost/Debian/home/vrs/Verilog/projects/32k-Omnibus/M8650D.v" 252 -1 0 } } } 0 332125 "Found combinational loop of %1!d! nodes" 0 0 "Quartus II" 0 -1 1699430714968 ""} { "Warning" "WSTA_SCC_LOOP" "2 " "Found combinational loop of 2 nodes" { { "Warning" "WSTA_SCC_NODE" "m8650d\|tflg_l_m~10\|dataout " "Node \"m8650d\|tflg_l_m~10\|dataout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1699430714968 ""} { "Warning" "WSTA_SCC_NODE" "m8650d\|tflg_l_m~10\|\[2\] " "Node \"m8650d\|tflg_l_m~10\|\[2\]\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1699430714968 ""} } { { "M8650D.v" "" { Text "//wsl.localhost/Debian/home/vrs/Verilog/projects/32k-Omnibus/M8650D.v" 209 -1 0 } } } 0 332125 "Found combinational loop of %1!d! nodes" 0 0 "Quartus II" 0 -1 1699430714968 ""} { "Warning" "WSTA_SCC_LOOP" "119 " "Found combinational loop of 119 nodes" { { "Warning" "WSTA_SCC_NODE" "m8650d\|n_t_18x~8sexp\|dataout " "Node \"m8650d\|n_t_18x~8sexp\|dataout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1699430714968 ""} { "Warning" "WSTA_SCC_NODE" "m8650d\|n_t_108x~3sexp3\|datain\[1\] " "Node \"m8650d\|n_t_108x~3sexp3\|datain\[1\]\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1699430714968 ""} { "Warning" "WSTA_SCC_NODE" "m8650d\|n_t_108x~3sexp3\|dataout " "Node \"m8650d\|n_t_108x~3sexp3\|dataout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1699430714968 ""} { "Warning" "WSTA_SCC_NODE" "m8650d\|tx_active_l_m~9\|\[5\] " "Node \"m8650d\|tx_active_l_m~9\|\[5\]\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1699430714968 ""} { "Warning" "WSTA_SCC_NODE" "m8650d\|tx_active_l_m~9\|dataout " "Node \"m8650d\|tx_active_l_m~9\|dataout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1699430714968 ""} { "Warning" "WSTA_SCC_NODE" "m8650d\|tx_active_l_m~9\|\[1\] " "Node \"m8650d\|tx_active_l_m~9\|\[1\]\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1699430714968 ""} { "Warning" "WSTA_SCC_NODE" "m8650d\|tx_active_l~9\|\[0\] " "Node \"m8650d\|tx_active_l~9\|\[0\]\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1699430714968 ""} { "Warning" "WSTA_SCC_NODE" "m8650d\|tx_active_l~9\|dataout " "Node \"m8650d\|tx_active_l~9\|dataout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1699430714968 ""} { "Warning" "WSTA_SCC_NODE" "m8650d\|tx_active_l~9\|\[2\] " "Node \"m8650d\|tx_active_l~9\|\[2\]\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1699430714968 ""} { "Warning" "WSTA_SCC_NODE" "m8650d\|n_t_108x~3sexp3\|datain\[0\] " "Node \"m8650d\|n_t_108x~3sexp3\|datain\[0\]\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1699430714968 ""} { "Warning" "WSTA_SCC_NODE" "m8650d\|n_t_146x_m~9\|\[0\] " "Node \"m8650d\|n_t_146x_m~9\|\[0\]\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1699430714968 ""} { "Warning" "WSTA_SCC_NODE" "m8650d\|n_t_146x_m~9\|dataout " "Node \"m8650d\|n_t_146x_m~9\|dataout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1699430714968 ""} { "Warning" "WSTA_SCC_NODE" "m8650d\|n_t_146x_m~9\|\[3\] " "Node \"m8650d\|n_t_146x_m~9\|\[3\]\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1699430714968 ""} { "Warning" "WSTA_SCC_NODE" "m8650d\|n_t_146x~9\|\[0\] " "Node \"m8650d\|n_t_146x~9\|\[0\]\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1699430714968 ""} { "Warning" "WSTA_SCC_NODE" "m8650d\|n_t_146x~9\|dataout " "Node \"m8650d\|n_t_146x~9\|dataout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1699430714968 ""} { "Warning" "WSTA_SCC_NODE" "m8650d\|n_t_146x~9\|\[3\] " "Node \"m8650d\|n_t_146x~9\|\[3\]\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1699430714968 ""} { "Warning" "WSTA_SCC_NODE" "m8650d\|n_t_108x~3sexp1\|datain\[1\] " "Node \"m8650d\|n_t_108x~3sexp1\|datain\[1\]\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1699430714968 ""} { "Warning" "WSTA_SCC_NODE" "m8650d\|n_t_108x~3sexp1\|dataout " "Node \"m8650d\|n_t_108x~3sexp1\|dataout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1699430714968 ""} { "Warning" "WSTA_SCC_NODE" "m8650d\|tx_active_l_m~9\|\[3\] " "Node \"m8650d\|tx_active_l_m~9\|\[3\]\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1699430714968 ""} { "Warning" "WSTA_SCC_NODE" "m8650d\|n_t_94x~1sexp\|datain\[1\] " "Node \"m8650d\|n_t_94x~1sexp\|datain\[1\]\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1699430714968 ""} { "Warning" "WSTA_SCC_NODE" "m8650d\|n_t_94x~1sexp\|dataout " "Node \"m8650d\|n_t_94x~1sexp\|dataout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1699430714968 ""} { "Warning" "WSTA_SCC_NODE" "m8650d\|tx_active_l_m~9\|\[4\] " "Node \"m8650d\|tx_active_l_m~9\|\[4\]\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1699430714968 ""} { "Warning" "WSTA_SCC_NODE" "m8650d\|tx_div_m~9\|\[3\] " "Node \"m8650d\|tx_div_m~9\|\[3\]\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1699430714968 ""} { "Warning" "WSTA_SCC_NODE" "m8650d\|tx_div_m~9\|dataout " "Node \"m8650d\|tx_div_m~9\|dataout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1699430714968 ""} { "Warning" "WSTA_SCC_NODE" "m8650d\|tx_div_m~9\|\[1\] " "Node \"m8650d\|tx_div_m~9\|\[1\]\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1699430714968 ""} { "Warning" "WSTA_SCC_NODE" "m8650d\|tx_div~9\|\[0\] " "Node \"m8650d\|tx_div~9\|\[0\]\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1699430714968 ""} { "Warning" "WSTA_SCC_NODE" "m8650d\|tx_div~9\|dataout " "Node \"m8650d\|tx_div~9\|dataout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1699430714968 ""} { "Warning" "WSTA_SCC_NODE" "m8650d\|tx_div~9\|\[2\] " "Node \"m8650d\|tx_div~9\|\[2\]\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1699430714968 ""} { "Warning" "WSTA_SCC_NODE" "m8650d\|n_t_146x~9\|\[1\] " "Node \"m8650d\|n_t_146x~9\|\[1\]\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1699430714968 ""} { "Warning" "WSTA_SCC_NODE" "m8650d\|n_t_146x_m~9\|\[1\] " "Node \"m8650d\|n_t_146x_m~9\|\[1\]\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1699430714968 ""} { "Warning" "WSTA_SCC_NODE" "m8650d\|n_t_57x~2\|\[2\] " "Node \"m8650d\|n_t_57x~2\|\[2\]\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1699430714968 ""} { "Warning" "WSTA_SCC_NODE" "m8650d\|n_t_57x~2\|dataout " "Node \"m8650d\|n_t_57x~2\|dataout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1699430714968 ""} { "Warning" "WSTA_SCC_NODE" "m8650d\|n_t_66x~9\|\[2\] " "Node \"m8650d\|n_t_66x~9\|\[2\]\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1699430714968 ""} { "Warning" "WSTA_SCC_NODE" "m8650d\|n_t_66x~9\|dataout " "Node \"m8650d\|n_t_66x~9\|dataout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1699430714968 ""} { "Warning" "WSTA_SCC_NODE" "m8650d\|n_t_66x~9\|\[3\] " "Node \"m8650d\|n_t_66x~9\|\[3\]\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1699430714968 ""} { "Warning" "WSTA_SCC_NODE" "m8650d\|n_t_18x~8sexp\|datain\[6\] " "Node \"m8650d\|n_t_18x~8sexp\|datain\[6\]\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1699430714968 ""} { "Warning" "WSTA_SCC_NODE" "m8650d\|n_t_66x_m~16\|\[2\] " "Node \"m8650d\|n_t_66x_m~16\|\[2\]\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1699430714968 ""} { "Warning" "WSTA_SCC_NODE" "m8650d\|n_t_66x_m~16\|dataout " "Node \"m8650d\|n_t_66x_m~16\|dataout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1699430714968 ""} { "Warning" "WSTA_SCC_NODE" "m8650d\|n_t_66x_m~16\|\[3\] " "Node \"m8650d\|n_t_66x_m~16\|\[3\]\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1699430714968 ""} { "Warning" "WSTA_SCC_NODE" "m8650d\|n_t_66x~9\|\[0\] " "Node \"m8650d\|n_t_66x~9\|\[0\]\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1699430714968 ""} { "Warning" "WSTA_SCC_NODE" "m8650d\|n_t_65x~9\|\[2\] " "Node \"m8650d\|n_t_65x~9\|\[2\]\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1699430714968 ""} { "Warning" "WSTA_SCC_NODE" "m8650d\|n_t_65x~9\|dataout " "Node \"m8650d\|n_t_65x~9\|dataout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1699430714968 ""} { "Warning" "WSTA_SCC_NODE" "m8650d\|n_t_66x_m~7\|\[0\] " "Node \"m8650d\|n_t_66x_m~7\|\[0\]\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1699430714968 ""} { "Warning" "WSTA_SCC_NODE" "m8650d\|n_t_66x_m~7\|dataout " "Node \"m8650d\|n_t_66x_m~7\|dataout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1699430714968 ""} { "Warning" "WSTA_SCC_NODE" "m8650d\|n_t_66x_m~16\|\[0\] " "Node \"m8650d\|n_t_66x_m~16\|\[0\]\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1699430714968 ""} { "Warning" "WSTA_SCC_NODE" "m8650d\|n_t_65x~9\|\[3\] " "Node \"m8650d\|n_t_65x~9\|\[3\]\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1699430714968 ""} { "Warning" "WSTA_SCC_NODE" "m8650d\|n_t_18x~8sexp\|datain\[1\] " "Node \"m8650d\|n_t_18x~8sexp\|datain\[1\]\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1699430714968 ""} { "Warning" "WSTA_SCC_NODE" "m8650d\|n_t_65x_m~16\|\[2\] " "Node \"m8650d\|n_t_65x_m~16\|\[2\]\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1699430714968 ""} { "Warning" "WSTA_SCC_NODE" "m8650d\|n_t_65x_m~16\|dataout " "Node \"m8650d\|n_t_65x_m~16\|dataout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1699430714968 ""} { "Warning" "WSTA_SCC_NODE" "m8650d\|n_t_65x_m~16\|\[3\] " "Node \"m8650d\|n_t_65x_m~16\|\[3\]\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1699430714968 ""} { "Warning" "WSTA_SCC_NODE" "m8650d\|n_t_65x~9\|\[0\] " "Node \"m8650d\|n_t_65x~9\|\[0\]\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1699430714968 ""} { "Warning" "WSTA_SCC_NODE" "m8650d\|n_t_63x~9\|\[2\] " "Node \"m8650d\|n_t_63x~9\|\[2\]\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1699430714968 ""} { "Warning" "WSTA_SCC_NODE" "m8650d\|n_t_63x~9\|dataout " "Node \"m8650d\|n_t_63x~9\|dataout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1699430714968 ""} { "Warning" "WSTA_SCC_NODE" "m8650d\|n_t_18x~8sexp\|datain\[2\] " "Node \"m8650d\|n_t_18x~8sexp\|datain\[2\]\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1699430714968 ""} { "Warning" "WSTA_SCC_NODE" "m8650d\|n_t_63x~9\|\[3\] " "Node \"m8650d\|n_t_63x~9\|\[3\]\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1699430714968 ""} { "Warning" "WSTA_SCC_NODE" "m8650d\|n_t_65x_m~7\|\[0\] " "Node \"m8650d\|n_t_65x_m~7\|\[0\]\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1699430714968 ""} { "Warning" "WSTA_SCC_NODE" "m8650d\|n_t_65x_m~7\|dataout " "Node \"m8650d\|n_t_65x_m~7\|dataout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1699430714968 ""} { "Warning" "WSTA_SCC_NODE" "m8650d\|n_t_65x_m~16\|\[0\] " "Node \"m8650d\|n_t_65x_m~16\|\[0\]\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1699430714968 ""} { "Warning" "WSTA_SCC_NODE" "m8650d\|n_t_63x_m~16\|\[2\] " "Node \"m8650d\|n_t_63x_m~16\|\[2\]\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1699430714968 ""} { "Warning" "WSTA_SCC_NODE" "m8650d\|n_t_63x_m~16\|dataout " "Node \"m8650d\|n_t_63x_m~16\|dataout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1699430714968 ""} { "Warning" "WSTA_SCC_NODE" "m8650d\|n_t_63x_m~16\|\[3\] " "Node \"m8650d\|n_t_63x_m~16\|\[3\]\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1699430714968 ""} { "Warning" "WSTA_SCC_NODE" "m8650d\|n_t_63x~9\|\[0\] " "Node \"m8650d\|n_t_63x~9\|\[0\]\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1699430714968 ""} { "Warning" "WSTA_SCC_NODE" "m8650d\|n_t_61x~9\|\[2\] " "Node \"m8650d\|n_t_61x~9\|\[2\]\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1699430714968 ""} { "Warning" "WSTA_SCC_NODE" "m8650d\|n_t_61x~9\|dataout " "Node \"m8650d\|n_t_61x~9\|dataout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1699430714968 ""} { "Warning" "WSTA_SCC_NODE" "m8650d\|n_t_18x~8sexp\|datain\[4\] " "Node \"m8650d\|n_t_18x~8sexp\|datain\[4\]\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1699430714968 ""} { "Warning" "WSTA_SCC_NODE" "m8650d\|n_t_61x~9\|\[3\] " "Node \"m8650d\|n_t_61x~9\|\[3\]\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1699430714968 ""} { "Warning" "WSTA_SCC_NODE" "m8650d\|n_t_63x_m~7\|\[0\] " "Node \"m8650d\|n_t_63x_m~7\|\[0\]\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1699430714968 ""} { "Warning" "WSTA_SCC_NODE" "m8650d\|n_t_63x_m~7\|dataout " "Node \"m8650d\|n_t_63x_m~7\|dataout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1699430714968 ""} { "Warning" "WSTA_SCC_NODE" "m8650d\|n_t_63x_m~16\|\[0\] " "Node \"m8650d\|n_t_63x_m~16\|\[0\]\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1699430714968 ""} { "Warning" "WSTA_SCC_NODE" "m8650d\|n_t_61x_m~16\|\[2\] " "Node \"m8650d\|n_t_61x_m~16\|\[2\]\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1699430714968 ""} { "Warning" "WSTA_SCC_NODE" "m8650d\|n_t_61x_m~16\|dataout " "Node \"m8650d\|n_t_61x_m~16\|dataout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1699430714968 ""} { "Warning" "WSTA_SCC_NODE" "m8650d\|n_t_61x_m~16\|\[3\] " "Node \"m8650d\|n_t_61x_m~16\|\[3\]\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1699430714968 ""} { "Warning" "WSTA_SCC_NODE" "m8650d\|n_t_61x~9\|\[0\] " "Node \"m8650d\|n_t_61x~9\|\[0\]\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1699430714968 ""} { "Warning" "WSTA_SCC_NODE" "m8650d\|n_t_56x~9\|\[2\] " "Node \"m8650d\|n_t_56x~9\|\[2\]\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1699430714968 ""} { "Warning" "WSTA_SCC_NODE" "m8650d\|n_t_56x~9\|dataout " "Node \"m8650d\|n_t_56x~9\|dataout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1699430714968 ""} { "Warning" "WSTA_SCC_NODE" "m8650d\|n_t_18x~8sexp\|datain\[5\] " "Node \"m8650d\|n_t_18x~8sexp\|datain\[5\]\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1699430714968 ""} { "Warning" "WSTA_SCC_NODE" "m8650d\|n_t_56x~9\|\[3\] " "Node \"m8650d\|n_t_56x~9\|\[3\]\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1699430714968 ""} { "Warning" "WSTA_SCC_NODE" "m8650d\|n_t_61x_m~7\|\[0\] " "Node \"m8650d\|n_t_61x_m~7\|\[0\]\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1699430714968 ""} { "Warning" "WSTA_SCC_NODE" "m8650d\|n_t_61x_m~7\|dataout " "Node \"m8650d\|n_t_61x_m~7\|dataout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1699430714968 ""} { "Warning" "WSTA_SCC_NODE" "m8650d\|n_t_61x_m~16\|\[0\] " "Node \"m8650d\|n_t_61x_m~16\|\[0\]\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1699430714968 ""} { "Warning" "WSTA_SCC_NODE" "m8650d\|n_t_56x_m~16\|\[2\] " "Node \"m8650d\|n_t_56x_m~16\|\[2\]\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1699430714968 ""} { "Warning" "WSTA_SCC_NODE" "m8650d\|n_t_56x_m~16\|dataout " "Node \"m8650d\|n_t_56x_m~16\|dataout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1699430714968 ""} { "Warning" "WSTA_SCC_NODE" "m8650d\|n_t_56x_m~16\|\[3\] " "Node \"m8650d\|n_t_56x_m~16\|\[3\]\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1699430714968 ""} { "Warning" "WSTA_SCC_NODE" "m8650d\|n_t_56x~9\|\[0\] " "Node \"m8650d\|n_t_56x~9\|\[0\]\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1699430714968 ""} { "Warning" "WSTA_SCC_NODE" "m8650d\|n_t_62x~9\|\[2\] " "Node \"m8650d\|n_t_62x~9\|\[2\]\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1699430714968 ""} { "Warning" "WSTA_SCC_NODE" "m8650d\|n_t_62x~9\|dataout " "Node \"m8650d\|n_t_62x~9\|dataout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1699430714968 ""} { "Warning" "WSTA_SCC_NODE" "m8650d\|n_t_56x_m~7\|\[0\] " "Node \"m8650d\|n_t_56x_m~7\|\[0\]\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1699430714968 ""} { "Warning" "WSTA_SCC_NODE" "m8650d\|n_t_56x_m~7\|dataout " "Node \"m8650d\|n_t_56x_m~7\|dataout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1699430714968 ""} { "Warning" "WSTA_SCC_NODE" "m8650d\|n_t_56x_m~16\|\[0\] " "Node \"m8650d\|n_t_56x_m~16\|\[0\]\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1699430714968 ""} { "Warning" "WSTA_SCC_NODE" "m8650d\|n_t_62x~9\|\[3\] " "Node \"m8650d\|n_t_62x~9\|\[3\]\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1699430714968 ""} { "Warning" "WSTA_SCC_NODE" "m8650d\|n_t_18x~8sexp\|datain\[0\] " "Node \"m8650d\|n_t_18x~8sexp\|datain\[0\]\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1699430714968 ""} { "Warning" "WSTA_SCC_NODE" "m8650d\|n_t_62x_m~16\|\[2\] " "Node \"m8650d\|n_t_62x_m~16\|\[2\]\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1699430714968 ""} { "Warning" "WSTA_SCC_NODE" "m8650d\|n_t_62x_m~16\|dataout " "Node \"m8650d\|n_t_62x_m~16\|dataout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1699430714968 ""} { "Warning" "WSTA_SCC_NODE" "m8650d\|n_t_62x_m~16\|\[3\] " "Node \"m8650d\|n_t_62x_m~16\|\[3\]\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1699430714968 ""} { "Warning" "WSTA_SCC_NODE" "m8650d\|n_t_62x~9\|\[0\] " "Node \"m8650d\|n_t_62x~9\|\[0\]\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1699430714968 ""} { "Warning" "WSTA_SCC_NODE" "m8650d\|n_t_60x~9\|\[2\] " "Node \"m8650d\|n_t_60x~9\|\[2\]\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1699430714968 ""} { "Warning" "WSTA_SCC_NODE" "m8650d\|n_t_60x~9\|dataout " "Node \"m8650d\|n_t_60x~9\|dataout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1699430714968 ""} { "Warning" "WSTA_SCC_NODE" "m8650d\|n_t_18x~8sexp\|datain\[7\] " "Node \"m8650d\|n_t_18x~8sexp\|datain\[7\]\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1699430714968 ""} { "Warning" "WSTA_SCC_NODE" "m8650d\|n_t_60x~9\|\[3\] " "Node \"m8650d\|n_t_60x~9\|\[3\]\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1699430714968 ""} { "Warning" "WSTA_SCC_NODE" "m8650d\|n_t_62x_m~7\|\[0\] " "Node \"m8650d\|n_t_62x_m~7\|\[0\]\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1699430714968 ""} { "Warning" "WSTA_SCC_NODE" "m8650d\|n_t_62x_m~7\|dataout " "Node \"m8650d\|n_t_62x_m~7\|dataout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1699430714968 ""} { "Warning" "WSTA_SCC_NODE" "m8650d\|n_t_62x_m~16\|\[0\] " "Node \"m8650d\|n_t_62x_m~16\|\[0\]\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1699430714968 ""} { "Warning" "WSTA_SCC_NODE" "m8650d\|n_t_60x_m~16\|\[2\] " "Node \"m8650d\|n_t_60x_m~16\|\[2\]\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1699430714968 ""} { "Warning" "WSTA_SCC_NODE" "m8650d\|n_t_60x_m~16\|dataout " "Node \"m8650d\|n_t_60x_m~16\|dataout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1699430714968 ""} { "Warning" "WSTA_SCC_NODE" "m8650d\|n_t_60x_m~16\|\[3\] " "Node \"m8650d\|n_t_60x_m~16\|\[3\]\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1699430714968 ""} { "Warning" "WSTA_SCC_NODE" "m8650d\|n_t_60x~9\|\[0\] " "Node \"m8650d\|n_t_60x~9\|\[0\]\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1699430714968 ""} { "Warning" "WSTA_SCC_NODE" "m8650d\|enab~9\|\[2\] " "Node \"m8650d\|enab~9\|\[2\]\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1699430714968 ""} { "Warning" "WSTA_SCC_NODE" "m8650d\|enab~9\|dataout " "Node \"m8650d\|enab~9\|dataout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1699430714968 ""} { "Warning" "WSTA_SCC_NODE" "m8650d\|n_t_18x~8sexp\|datain\[3\] " "Node \"m8650d\|n_t_18x~8sexp\|datain\[3\]\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1699430714968 ""} { "Warning" "WSTA_SCC_NODE" "m8650d\|n_t_60x_m~7\|\[0\] " "Node \"m8650d\|n_t_60x_m~7\|\[0\]\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1699430714968 ""} { "Warning" "WSTA_SCC_NODE" "m8650d\|n_t_60x_m~7\|dataout " "Node \"m8650d\|n_t_60x_m~7\|dataout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1699430714968 ""} { "Warning" "WSTA_SCC_NODE" "m8650d\|n_t_60x_m~16\|\[0\] " "Node \"m8650d\|n_t_60x_m~16\|\[0\]\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1699430714968 ""} { "Warning" "WSTA_SCC_NODE" "m8650d\|enab~9\|\[3\] " "Node \"m8650d\|enab~9\|\[3\]\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1699430714968 ""} { "Warning" "WSTA_SCC_NODE" "m8650d\|n_t_108x~3sexp1\|datain\[0\] " "Node \"m8650d\|n_t_108x~3sexp1\|datain\[0\]\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1699430714968 ""} { "Warning" "WSTA_SCC_NODE" "m8650d\|enab_m~9\|\[2\] " "Node \"m8650d\|enab_m~9\|\[2\]\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1699430714968 ""} { "Warning" "WSTA_SCC_NODE" "m8650d\|enab_m~9\|dataout " "Node \"m8650d\|enab_m~9\|dataout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1699430714968 ""} { "Warning" "WSTA_SCC_NODE" "m8650d\|enab_m~9\|\[3\] " "Node \"m8650d\|enab_m~9\|\[3\]\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1699430714968 ""} { "Warning" "WSTA_SCC_NODE" "m8650d\|enab~9\|\[0\] " "Node \"m8650d\|enab~9\|\[0\]\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1699430714968 ""} { "Warning" "WSTA_SCC_NODE" "m8650d\|n_t_94x~1sexp\|datain\[0\] " "Node \"m8650d\|n_t_94x~1sexp\|datain\[0\]\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1699430714968 ""} } { { "M8650D.v" "" { Text "//wsl.localhost/Debian/home/vrs/Verilog/projects/32k-Omnibus/M8650D.v" 274 -1 0 } } { "M8650D.v" "" { Text "//wsl.localhost/Debian/home/vrs/Verilog/projects/32k-Omnibus/M8650D.v" 272 -1 0 } } { "M8650D.v" "" { Text "//wsl.localhost/Debian/home/vrs/Verilog/projects/32k-Omnibus/M8650D.v" 210 -1 0 } } { "M8650D.v" "" { Text "//wsl.localhost/Debian/home/vrs/Verilog/projects/32k-Omnibus/M8650D.v" 235 -1 0 } } { "M8650D.v" "" { Text "//wsl.localhost/Debian/home/vrs/Verilog/projects/32k-Omnibus/M8650D.v" 182 -1 0 } } { "M8650D.v" "" { Text "//wsl.localhost/Debian/home/vrs/Verilog/projects/32k-Omnibus/M8650D.v" 136 -1 0 } } { "M8650D.v" "" { Text "//wsl.localhost/Debian/home/vrs/Verilog/projects/32k-Omnibus/M8650D.v" 302 -1 0 } } { "M8650D.v" "" { Text "//wsl.localhost/Debian/home/vrs/Verilog/projects/32k-Omnibus/M8650D.v" 212 -1 0 } } { "M8650D.v" "" { Text "//wsl.localhost/Debian/home/vrs/Verilog/projects/32k-Omnibus/M8650D.v" 231 -1 0 } } { "M8650D.v" "" { Text "//wsl.localhost/Debian/home/vrs/Verilog/projects/32k-Omnibus/M8650D.v" 292 -1 0 } } { "M8650D.v" "" { Text "//wsl.localhost/Debian/home/vrs/Verilog/projects/32k-Omnibus/M8650D.v" 250 -1 0 } } { "M8650D.v" "" { Text "//wsl.localhost/Debian/home/vrs/Verilog/projects/32k-Omnibus/M8650D.v" 199 -1 0 } } { "M8650D.v" "" { Text "//wsl.localhost/Debian/home/vrs/Verilog/projects/32k-Omnibus/M8650D.v" 249 -1 0 } } { "M8650D.v" "" { Text "//wsl.localhost/Debian/home/vrs/Verilog/projects/32k-Omnibus/M8650D.v" 198 -1 0 } } { "M8650D.v" "" { Text "//wsl.localhost/Debian/home/vrs/Verilog/projects/32k-Omnibus/M8650D.v" 248 -1 0 } } { "M8650D.v" "" { Text "//wsl.localhost/Debian/home/vrs/Verilog/projects/32k-Omnibus/M8650D.v" 197 -1 0 } } { "M8650D.v" "" { Text "//wsl.localhost/Debian/home/vrs/Verilog/projects/32k-Omnibus/M8650D.v" 246 -1 0 } } { "M8650D.v" "" { Text "//wsl.localhost/Debian/home/vrs/Verilog/projects/32k-Omnibus/M8650D.v" 195 -1 0 } } { "M8650D.v" "" { Text "//wsl.localhost/Debian/home/vrs/Verilog/projects/32k-Omnibus/M8650D.v" 245 -1 0 } } { "M8650D.v" "" { Text "//wsl.localhost/Debian/home/vrs/Verilog/projects/32k-Omnibus/M8650D.v" 193 -1 0 } } { "M8650D.v" "" { Text "//wsl.localhost/Debian/home/vrs/Verilog/projects/32k-Omnibus/M8650D.v" 244 -1 0 } } { "M8650D.v" "" { Text "//wsl.localhost/Debian/home/vrs/Verilog/projects/32k-Omnibus/M8650D.v" 196 -1 0 } } { "M8650D.v" "" { Text "//wsl.localhost/Debian/home/vrs/Verilog/projects/32k-Omnibus/M8650D.v" 243 -1 0 } } { "M8650D.v" "" { Text "//wsl.localhost/Debian/home/vrs/Verilog/projects/32k-Omnibus/M8650D.v" 194 -1 0 } } { "M8650D.v" "" { Text "//wsl.localhost/Debian/home/vrs/Verilog/projects/32k-Omnibus/M8650D.v" 247 -1 0 } } { "M8650D.v" "" { Text "//wsl.localhost/Debian/home/vrs/Verilog/projects/32k-Omnibus/M8650D.v" 172 -1 0 } } } 0 332125 "Found combinational loop of %1!d! nodes" 0 0 "Quartus II" 0 -1 1699430714968 ""} { "Critical Warning" "WSTA_SCC_LOOP_TOO_BIG" "119 " "Design contains combinational loop of 119 nodes. Estimating the delays through the loop." { } { } 1 332081 "Design contains combinational loop of %1!d! nodes. Estimating the delays through the loop." 0 0 "Quartus II" 0 -1 1699430714968 ""} { "Warning" "WSTA_SCC_LOOP" "2 " "Found combinational loop of 2 nodes" { { "Warning" "WSTA_SCC_NODE" "m8650d\|int_enab_l~9\|dataout " "Node \"m8650d\|int_enab_l~9\|dataout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1699430714968 ""} { "Warning" "WSTA_SCC_NODE" "m8650d\|int_enab_l~9\|\[2\] " "Node \"m8650d\|int_enab_l~9\|\[2\]\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1699430714968 ""} } { { "M8650D.v" "" { Text "//wsl.localhost/Debian/home/vrs/Verilog/projects/32k-Omnibus/M8650D.v" 253 -1 0 } } } 0 332125 "Found combinational loop of %1!d! nodes" 0 0 "Quartus II" 0 -1 1699430714968 ""} { "Warning" "WSTA_SCC_LOOP" "2 " "Found combinational loop of 2 nodes" { { "Warning" "WSTA_SCC_NODE" "m8650d\|int_enab_l_m~9\|dataout " "Node \"m8650d\|int_enab_l_m~9\|dataout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1699430714968 ""} { "Warning" "WSTA_SCC_NODE" "m8650d\|int_enab_l_m~9\|\[1\] " "Node \"m8650d\|int_enab_l_m~9\|\[1\]\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1699430714968 ""} } { { "M8650D.v" "" { Text "//wsl.localhost/Debian/home/vrs/Verilog/projects/32k-Omnibus/M8650D.v" 178 -1 0 } } } 0 332125 "Found combinational loop of %1!d! nodes" 0 0 "Quartus II" 0 -1 1699430714968 ""} { "Info" "0" "" "Found TIMEQUEST_REPORT_SCRIPT_INCLUDE_DEFAULT_ANALYSIS = ON" { } { } 0 0 "Found TIMEQUEST_REPORT_SCRIPT_INCLUDE_DEFAULT_ANALYSIS = ON" 0 0 "Quartus II" 0 0 1699430714984 ""} { "Critical Warning" "WSTA_TIMING_NOT_MET" "" "Timing requirements not met" { } { } 1 332148 "Timing requirements not met" 0 0 "Quartus II" 0 -1 1699430715044 ""} { "Info" "ISTA_WORST_CASE_SLACK" "setup -10.800 " "Worst-case setup slack is -10.800" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1699430715047 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= ============= ===================== " "========= ============= =====================" { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1699430715047 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -10.800 -48.300 bd1200 " " -10.800 -48.300 bd1200 " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1699430715047 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -10.800 -12.300 bd115200 " " -10.800 -12.300 bd115200 " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1699430715047 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -10.800 -12.300 bd38400 " " -10.800 -12.300 bd38400 " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1699430715047 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -10.800 -12.300 bd9600 " " -10.800 -12.300 bd9600 " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1699430715047 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -10.300 -16.300 clk " " -10.300 -16.300 clk " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1699430715047 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -10.300 -10.300 cf0 " " -10.300 -10.300 cf0 " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1699430715047 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -10.000 -19.000 bd600 " " -10.000 -19.000 bd600 " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1699430715047 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -1.500 -1.500 bd19200 " " -1.500 -1.500 bd19200 " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1699430715047 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -1.500 -1.500 bd2400 " " -1.500 -1.500 bd2400 " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1699430715047 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -1.500 -1.500 bd4800 " " -1.500 -1.500 bd4800 " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1699430715047 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -1.500 -1.500 n_t_1x " " -1.500 -1.500 n_t_1x " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1699430715047 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Quartus II" 0 -1 1699430715047 ""} { "Info" "ISTA_WORST_CASE_SLACK" "hold -3.000 " "Worst-case hold slack is -3.000" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1699430715062 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= ============= ===================== " "========= ============= =====================" { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1699430715062 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -3.000 -3.000 bd115200 " " -3.000 -3.000 bd115200 " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1699430715062 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -3.000 -3.000 bd1200 " " -3.000 -3.000 bd1200 " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1699430715062 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -3.000 -3.000 bd19200 " " -3.000 -3.000 bd19200 " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1699430715062 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -3.000 -3.000 bd2400 " " -3.000 -3.000 bd2400 " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1699430715062 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -3.000 -3.000 bd38400 " " -3.000 -3.000 bd38400 " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1699430715062 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -3.000 -3.000 bd4800 " " -3.000 -3.000 bd4800 " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1699430715062 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -3.000 -3.000 bd9600 " " -3.000 -3.000 bd9600 " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1699430715062 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -3.000 -3.000 n_t_1x " " -3.000 -3.000 n_t_1x " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1699430715062 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 1.500 0.000 clk " " 1.500 0.000 clk " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1699430715062 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 4.200 0.000 bd600 " " 4.200 0.000 bd600 " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1699430715062 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 4.200 0.000 cf0 " " 4.200 0.000 cf0 " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1699430715062 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Quartus II" 0 -1 1699430715062 ""} { "Info" "ISTA_WORST_CASE_SLACK" "recovery -4.500 " "Worst-case recovery slack is -4.500" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1699430715062 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= ============= ===================== " "========= ============= =====================" { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1699430715062 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -4.500 -4.500 bd115200 " " -4.500 -4.500 bd115200 " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1699430715062 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -4.500 -4.500 n_t_1x " " -4.500 -4.500 n_t_1x " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1699430715062 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Quartus II" 0 -1 1699430715062 ""} { "Info" "ISTA_WORST_CASE_SLACK" "removal 0.000 " "Worst-case removal slack is 0.000" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1699430715078 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= ============= ===================== " "========= ============= =====================" { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1699430715078 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 0.000 0.000 bd115200 " " 0.000 0.000 bd115200 " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1699430715078 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 0.000 0.000 n_t_1x " " 0.000 0.000 n_t_1x " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1699430715078 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Quartus II" 0 -1 1699430715078 ""} { "Info" "ISTA_WORST_CASE_SLACK" "minimum pulse width -4.300 " "Worst-case minimum pulse width slack is -4.300" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1699430715094 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= ============= ===================== " "========= ============= =====================" { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1699430715094 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -4.300 -16.800 cf0 " " -4.300 -16.800 cf0 " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1699430715094 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -3.500 -42.000 bd1200 " " -3.500 -42.000 bd1200 " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1699430715094 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -3.500 -14.000 bd115200 " " -3.500 -14.000 bd115200 " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1699430715094 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -3.500 -14.000 bd38400 " " -3.500 -14.000 bd38400 " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1699430715094 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -3.500 -14.000 bd600 " " -3.500 -14.000 bd600 " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1699430715094 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -3.500 -14.000 bd9600 " " -3.500 -14.000 bd9600 " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1699430715094 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -3.500 -14.000 clk " " -3.500 -14.000 clk " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1699430715094 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -3.500 -7.000 bd19200 " " -3.500 -7.000 bd19200 " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1699430715094 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -3.500 -7.000 bd2400 " " -3.500 -7.000 bd2400 " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1699430715094 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -3.500 -7.000 bd4800 " " -3.500 -7.000 bd4800 " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1699430715094 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -3.500 -7.000 n_t_1x " " -3.500 -7.000 n_t_1x " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1699430715094 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Quartus II" 0 -1 1699430715094 ""} { "Info" "ISTA_METASTABILITY_REPORT_DISABLED" "" "The selected device family is not supported by the report_metastability command." { } { } 0 332001 "The selected device family is not supported by the report_metastability command." 0 0 "Quartus II" 0 -1 1699430715470 ""} { "Info" "ISTA_UCP_NOT_CONSTRAINED" "setup " "Design is not fully constrained for setup requirements" { } { } 0 332102 "Design is not fully constrained for %1!s! requirements" 0 0 "Quartus II" 0 -1 1699430715502 ""} { "Info" "ISTA_UCP_NOT_CONSTRAINED" "hold " "Design is not fully constrained for hold requirements" { } { } 0 332102 "Design is not fully constrained for %1!s! requirements" 0 0 "Quartus II" 0 -1 1699430715502 ""} { "Info" "IQEXE_ERROR_COUNT" "TimeQuest Timing Analyzer 0 s 374 s Quartus II 64-Bit " "Quartus II 64-Bit TimeQuest Timing Analyzer was successful. 0 errors, 374 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "4534 " "Peak virtual memory: 4534 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Quartus II" 0 -1 1699430715627 ""} { "Info" "IQEXE_END_BANNER_TIME" "Wed Nov 08 00:05:15 2023 " "Processing ended: Wed Nov 08 00:05:15 2023" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Quartus II" 0 -1 1699430715627 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:01 " "Elapsed time: 00:00:01" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Quartus II" 0 -1 1699430715627 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:00 " "Total CPU time (on all processors): 00:00:00" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Quartus II" 0 -1 1699430715627 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Quartus II" 0 -1 1699430715627 ""} { "Info" "IFLOW_ERROR_COUNT" "Full Compilation 0 s 502 s " "Quartus II Full Compilation was successful. 0 errors, 502 warnings" { } { } 0 293000 "Quartus II %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Quartus II" 0 -1 1699430716632 ""}