Analysis & Synthesis report for cpld Sat Nov 18 05:23:54 2023 Quartus II 64-Bit Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition --------------------- ; Table of Contents ; --------------------- 1. Legal Notice 2. Analysis & Synthesis Summary 3. Analysis & Synthesis Settings 4. Parallel Compilation 5. Analysis & Synthesis Source Files Read 6. Analysis & Synthesis Resource Usage Summary 7. Analysis & Synthesis Resource Utilization by Entity 8. User-Specified and Inferred Latches 9. Port Connectivity Checks: "m8650d:m8650d" 10. Analysis & Synthesis Equations 11. Analysis & Synthesis Messages 12. Analysis & Synthesis Suppressed Messages ---------------- ; Legal Notice ; ---------------- Copyright (C) 1991-2013 Altera Corporation Your use of Altera Corporation's design tools, logic functions and other software and tools, and its AMPP partner logic functions, and any output files from any of the foregoing (including device programming or simulation files), and any associated documentation or information are expressly subject to the terms and conditions of the Altera Program License Subscription Agreement, Altera MegaCore Function License Agreement, or other applicable license agreement, including, without limitation, that your use is for the sole purpose of programming logic devices manufactured by Altera and sold by Altera or its authorized distributors. Please refer to the applicable agreement for further details. +-------------------------------------------------------------------------------+ ; Analysis & Synthesis Summary ; +-----------------------------+-------------------------------------------------+ ; Analysis & Synthesis Status ; Successful - Sat Nov 18 05:23:54 2023 ; ; Quartus II 64-Bit Version ; 13.0.1 Build 232 06/12/2013 SP 1 SJ Web Edition ; ; Revision Name ; cpld ; ; Top-level Entity Name ; cpld ; ; Family ; MAX7000S ; ; Total macrocells ; 86 ; ; Total pins ; 64 ; +-----------------------------+-------------------------------------------------+ +--------------------------------------------------------------------------------------------------------------+ ; Analysis & Synthesis Settings ; +----------------------------------------------------------------------------+-----------------+---------------+ ; Option ; Setting ; Default Value ; +----------------------------------------------------------------------------+-----------------+---------------+ ; Device ; EPM7128SLI84-10 ; ; ; Top-level entity name ; cpld ; cpld ; ; Family name ; MAX7000S ; Cyclone IV GX ; ; Optimization Technique ; Area ; Speed ; ; Use smart compilation ; Off ; Off ; ; Enable parallel Assembler and TimeQuest Timing Analyzer during compilation ; On ; On ; ; Enable compact report table ; Off ; Off ; ; Create Debugging Nodes for IP Cores ; Off ; Off ; ; Preserve fewer node names ; On ; On ; ; Disable OpenCore Plus hardware evaluation ; Off ; Off ; ; Verilog Version ; Verilog_2001 ; Verilog_2001 ; ; VHDL Version ; VHDL_1993 ; VHDL_1993 ; ; State Machine Processing ; Auto ; Auto ; ; Safe State Machine ; Off ; Off ; ; Extract Verilog State Machines ; On ; On ; ; Extract VHDL State Machines ; On ; On ; ; Ignore Verilog initial constructs ; Off ; Off ; ; Iteration limit for constant Verilog loops ; 5000 ; 5000 ; ; Iteration limit for non-constant Verilog loops ; 250 ; 250 ; ; Add Pass-Through Logic to Inferred RAMs ; On ; On ; ; Infer RAMs from Raw Logic ; On ; On ; ; Parallel Synthesis ; On ; On ; ; NOT Gate Push-Back ; On ; On ; ; Power-Up Don't Care ; On ; On ; ; Remove Duplicate Registers ; On ; On ; ; Ignore CARRY Buffers ; Off ; Off ; ; Ignore CASCADE Buffers ; Off ; Off ; ; Ignore GLOBAL Buffers ; Off ; Off ; ; Ignore ROW GLOBAL Buffers ; Off ; Off ; ; Ignore LCELL Buffers ; Auto ; Auto ; ; Ignore SOFT Buffers ; Off ; Off ; ; Limit AHDL Integers to 32 Bits ; Off ; Off ; ; Allow XOR Gate Usage ; On ; On ; ; Auto Logic Cell Insertion ; On ; On ; ; Parallel Expander Chain Length ; 4 ; 4 ; ; Auto Parallel Expanders ; On ; On ; ; Auto Open-Drain Pins ; On ; On ; ; Auto Resource Sharing ; Off ; Off ; ; Maximum Fan-in Per Macrocell ; 100 ; 100 ; ; Use LogicLock Constraints during Resource Balancing ; On ; On ; ; Ignore translate_off and synthesis_off directives ; Off ; Off ; ; Report Parameter Settings ; On ; On ; ; Report Source Assignments ; On ; On ; ; Report Connectivity Checks ; On ; On ; ; HDL message level ; Level2 ; Level2 ; ; Suppress Register Optimization Related Messages ; Off ; Off ; ; Number of Removed Registers Reported in Synthesis Report ; 5000 ; 5000 ; ; Number of Swept Nodes Reported in Synthesis Report ; 5000 ; 5000 ; ; Number of Inverted Registers Reported in Synthesis Report ; 100 ; 100 ; ; Block Design Naming ; Auto ; Auto ; ; Synthesis Effort ; Auto ; Auto ; ; Shift Register Replacement - Allow Asynchronous Clear Signal ; On ; On ; ; Pre-Mapping Resynthesis Optimization ; Off ; Off ; ; Analysis & Synthesis Message Level ; Medium ; Medium ; ; Disable Register Merging Across Hierarchies ; Auto ; Auto ; ; Synthesis Seed ; 1 ; 1 ; +----------------------------------------------------------------------------+-----------------+---------------+ Parallel compilation was disabled, but you have multiple processors available. Enable parallel compilation to reduce compilation time. +-------------------------------------+ ; Parallel Compilation ; +----------------------------+--------+ ; Processors ; Number ; +----------------------------+--------+ ; Number detected on machine ; 8 ; ; Maximum allowed ; 1 ; +----------------------------+--------+ +----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ ; Analysis & Synthesis Source Files Read ; +-----------------------------------------------------------------------+-----------------+------------------------+-----------------------------------------------------------------------+---------+ ; File Name with User-Entered Path ; Used in Netlist ; File Type ; File Name with Absolute Path ; Library ; +-----------------------------------------------------------------------+-----------------+------------------------+-----------------------------------------------------------------------+---------+ ; //wsl.localhost/Debian/home/vrs/Verilog/projects/32k-Omnibus/M8650D.v ; yes ; User Verilog HDL File ; //wsl.localhost/Debian/home/vrs/Verilog/projects/32k-Omnibus/M8650D.v ; ; ; //wsl.localhost/Debian/home/vrs/Verilog/projects/32k-Omnibus/cpld.v ; yes ; User Verilog HDL File ; //wsl.localhost/Debian/home/vrs/Verilog/projects/32k-Omnibus/cpld.v ; ; +-----------------------------------------------------------------------+-----------------+------------------------+-----------------------------------------------------------------------+---------+ +---------------------------------------------+ ; Analysis & Synthesis Resource Usage Summary ; +----------------------+----------------------+ ; Resource ; Usage ; +----------------------+----------------------+ ; Logic cells ; 86 ; ; Total registers ; 18 ; ; I/O pins ; 64 ; ; Shareable expanders ; 7 ; ; Parallel expanders ; 5 ; ; Maximum fan-out node ; initialize ; ; Maximum fan-out ; 26 ; ; Total fan-out ; 430 ; ; Average fan-out ; 2.74 ; +----------------------+----------------------+ +-------------------------------------------------------------------------------------+ ; Analysis & Synthesis Resource Utilization by Entity ; +----------------------------+------------+------+---------------------+--------------+ ; Compilation Hierarchy Node ; Macrocells ; Pins ; Full Hierarchy Name ; Library Name ; +----------------------------+------------+------+---------------------+--------------+ ; |cpld ; 86 ; 64 ; |cpld ; work ; ; |m8650d:m8650d| ; 59 ; 0 ; |cpld|m8650d:m8650d ; work ; +----------------------------+------------+------+---------------------+--------------+ +---------------------------------------------------------------------------------------------------------------+ ; User-Specified and Inferred Latches ; +-----------------------------------------------------+--------------------------------+------------------------+ ; Latch Name ; Latch Enable Signal ; Free of Timing Hazards ; +-----------------------------------------------------+--------------------------------+------------------------+ ; m8650d:m8650d|line ; m8650d:m8650d|tx_div ; yes ; ; m8650d:m8650d|tflg_l ; m8650d:m8650d|tx_div ; yes ; ; m8650d:m8650d|int_enab_l ; m8650d:m8650d|ckkie ; yes ; ; m8650d:m8650d|line_m ; m8650d:m8650d|tx_div ; yes ; ; m8650d:m8650d|tx_div ; m8650d:m8650d|n_t_162x ; yes ; ; m8650d:m8650d|start_l ; m8650d:m8650d|tx_active~direct ; yes ; ; m8650d:m8650d|tflg_l_m ; m8650d:m8650d|tx_div ; yes ; ; m8650d:m8650d|int_enab_l_m ; m8650d:m8650d|ckkie ; yes ; ; m8650d:m8650d|tx_data ; m8650d:m8650d|n_t_57x ; yes ; ; m8650d:m8650d|tx_div_m ; m8650d:m8650d|n_t_162x ; yes ; ; m8650d:m8650d|start_l_m ; m8650d:m8650d|tx_active~direct ; yes ; ; m8650d:m8650d|enab ; m8650d:m8650d|n_t_57x ; yes ; ; m8650d:m8650d|n_t_56x ; m8650d:m8650d|n_t_57x ; yes ; ; m8650d:m8650d|n_t_62x ; m8650d:m8650d|n_t_57x ; yes ; ; m8650d:m8650d|n_t_60x ; m8650d:m8650d|n_t_57x ; yes ; ; m8650d:m8650d|n_t_61x ; m8650d:m8650d|n_t_57x ; yes ; ; m8650d:m8650d|n_t_66x ; m8650d:m8650d|n_t_57x ; yes ; ; m8650d:m8650d|n_t_65x ; m8650d:m8650d|n_t_57x ; yes ; ; m8650d:m8650d|n_t_63x ; m8650d:m8650d|n_t_57x ; yes ; ; m8650d:m8650d|tx_data_m ; m8650d:m8650d|n_t_57x ; yes ; ; m8650d:m8650d|tx_active_l ; m8650d:m8650d|n_t_162x ; yes ; ; m8650d:m8650d|enab_m ; m8650d:m8650d|n_t_57x ; yes ; ; m8650d:m8650d|n_t_56x_m ; m8650d:m8650d|n_t_57x ; yes ; ; m8650d:m8650d|n_t_62x_m ; m8650d:m8650d|n_t_57x ; yes ; ; m8650d:m8650d|n_t_60x_m ; m8650d:m8650d|n_t_57x ; yes ; ; m8650d:m8650d|n_t_61x_m ; m8650d:m8650d|n_t_57x ; yes ; ; m8650d:m8650d|n_t_66x_m ; m8650d:m8650d|n_t_57x ; yes ; ; m8650d:m8650d|n_t_65x_m ; m8650d:m8650d|n_t_57x ; yes ; ; m8650d:m8650d|n_t_63x_m ; m8650d:m8650d|n_t_57x ; yes ; ; m8650d:m8650d|tx_active_l_m ; m8650d:m8650d|n_t_162x ; yes ; ; m8650d:m8650d|n_t_146x ; m8650d:m8650d|n_t_162x ; yes ; ; m8650d:m8650d|n_t_146x_m ; m8650d:m8650d|n_t_162x ; yes ; ; Number of user-specified and inferred latches = 32 ; ; ; +-----------------------------------------------------+--------------------------------+------------------------+ Note: All latches listed above may not be present at the end of synthesis due to various synthesis optimizations. +----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ ; Port Connectivity Checks: "m8650d:m8650d" ; +---------------+--------+----------+----------------------------------------------------------------------------------------------------------------------------------------------+ ; Port ; Type ; Severity ; Details ; +---------------+--------+----------+----------------------------------------------------------------------------------------------------------------------------------------------+ ; n3v3 ; Input ; Info ; Stuck at VCC ; ; n_t_152x ; Input ; Info ; Stuck at VCC ; ; rx_rate ; Output ; Info ; Connected to dangling logic. Logic that only feeds a dangling port will be removed. ; ; n_t_103x ; Input ; Info ; Stuck at VCC ; ; n_t_128x ; Input ; Warning ; Declared by entity but not connected by instance. If a default value exists, it will be used. Otherwise, the port will be connected to GND. ; ; n_t_77x ; Output ; Warning ; Declared by entity but not connected by instance. Logic that only feeds a dangling port will be removed. ; ; bd1200 ; Output ; Warning ; Declared by entity but not connected by instance. Logic that only feeds a dangling port will be removed. ; ; bd150 ; Output ; Warning ; Declared by entity but not connected by instance. Logic that only feeds a dangling port will be removed. ; ; bd2400 ; Output ; Warning ; Declared by entity but not connected by instance. Logic that only feeds a dangling port will be removed. ; ; bd300 ; Output ; Warning ; Declared by entity but not connected by instance. Logic that only feeds a dangling port will be removed. ; ; bd600 ; Output ; Warning ; Declared by entity but not connected by instance. Logic that only feeds a dangling port will be removed. ; ; dotpc_l ; Bidir ; Warning ; Declared by entity but not connected by instance. Logic that only feeds a dangling port will be removed. ; ; eia_in ; Output ; Warning ; Declared by entity but not connected by instance. Logic that only feeds a dangling port will be removed. ; ; eia_out ; Output ; Warning ; Declared by entity but not connected by instance. Logic that only feeds a dangling port will be removed. ; ; int_enab ; Bidir ; Warning ; Declared by entity but not connected by instance. Logic that only feeds a dangling port will be removed. ; ; line_l ; Output ; Warning ; Declared by entity but not connected by instance. Logic that only feeds a dangling port will be removed. ; ; md03 ; Input ; Warning ; Declared by entity but not connected by instance. If a default value exists, it will be used. Otherwise, the port will be connected to GND. ; ; md04 ; Input ; Warning ; Declared by entity but not connected by instance. If a default value exists, it will be used. Otherwise, the port will be connected to GND. ; ; md05 ; Input ; Warning ; Declared by entity but not connected by instance. If a default value exists, it will be used. Otherwise, the port will be connected to GND. ; ; md06 ; Input ; Warning ; Declared by entity but not connected by instance. If a default value exists, it will be used. Otherwise, the port will be connected to GND. ; ; md07 ; Input ; Warning ; Declared by entity but not connected by instance. If a default value exists, it will be used. Otherwise, the port will be connected to GND. ; ; n15v ; Output ; Warning ; Declared by entity but not connected by instance. Logic that only feeds a dangling port will be removed. ; ; n_t_119x ; Output ; Warning ; Declared by entity but not connected by instance. Logic that only feeds a dangling port will be removed. ; ; n_t_161x ; Output ; Warning ; Declared by entity but not connected by instance. Logic that only feeds a dangling port will be removed. ; ; n_t_27x ; Bidir ; Warning ; Declared by entity but not connected by instance. Logic that only feeds a dangling port will be removed. ; ; n_t_30x ; Output ; Warning ; Declared by entity but not connected by instance. Logic that only feeds a dangling port will be removed. ; ; n_t_45x ; Output ; Warning ; Declared by entity but not connected by instance. Logic that only feeds a dangling port will be removed. ; ; n_t_59x ; Output ; Warning ; Declared by entity but not connected by instance. Logic that only feeds a dangling port will be removed. ; ; n_t_83x ; Input ; Warning ; Declared by entity but not connected by instance. If a default value exists, it will be used. Otherwise, the port will be connected to GND. ; ; n_t_89x ; Output ; Warning ; Declared by entity but not connected by instance. Logic that only feeds a dangling port will be removed. ; ; n_t_92x ; Output ; Warning ; Declared by entity but not connected by instance. Logic that only feeds a dangling port will be removed. ; ; n_t_93x ; Output ; Warning ; Declared by entity but not connected by instance. Logic that only feeds a dangling port will be removed. ; ; r_run_l ; Output ; Warning ; Declared by entity but not connected by instance. Logic that only feeds a dangling port will be removed. ; ; reader_run ; Output ; Warning ; Declared by entity but not connected by instance. Logic that only feeds a dangling port will be removed. ; ; reader_run_or ; Output ; Warning ; Declared by entity but not connected by instance. Logic that only feeds a dangling port will be removed. ; ; rtsdtr ; Output ; Warning ; Declared by entity but not connected by instance. Logic that only feeds a dangling port will be removed. ; ; rx20ma_data ; Output ; Warning ; Declared by entity but not connected by instance. Logic that only feeds a dangling port will be removed. ; ; rx_20ma ; Output ; Warning ; Declared by entity but not connected by instance. Logic that only feeds a dangling port will be removed. ; ; rx_20ma_or ; Output ; Warning ; Declared by entity but not connected by instance. Logic that only feeds a dangling port will be removed. ; ; rx_active ; Output ; Warning ; Declared by entity but not connected by instance. Logic that only feeds a dangling port will be removed. ; ; rx_data ; Output ; Warning ; Declared by entity but not connected by instance. Logic that only feeds a dangling port will be removed. ; ; tx_20ma ; Output ; Warning ; Declared by entity but not connected by instance. Logic that only feeds a dangling port will be removed. ; ; tx_20ma_or ; Output ; Warning ; Declared by entity but not connected by instance. Logic that only feeds a dangling port will be removed. ; ; tx_active ; Bidir ; Warning ; Declared by entity but not connected by instance. Logic that only feeds a dangling port will be removed. ; ; tx_div_l ; Bidir ; Warning ; Declared by entity but not connected by instance. Logic that only feeds a dangling port will be removed. ; ; tx_sel_l ; Bidir ; Warning ; Declared by entity but not connected by instance. Logic that only feeds a dangling port will be removed. ; +---------------+--------+----------+----------------------------------------------------------------------------------------------------------------------------------------------+ +--------------------------------+ ; Analysis & Synthesis Equations ; +--------------------------------+ The equations can be found in //wsl.localhost/Debian/home/vrs/Verilog/projects/32k-Omnibus/output_files/cpld.map.eqn. +-------------------------------+ ; Analysis & Synthesis Messages ; +-------------------------------+ Info: ******************************************************************* Info: Running Quartus II 64-Bit Analysis & Synthesis Info: Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition Info: Processing started: Sat Nov 18 05:23:51 2023 Info: Command: quartus_map --read_settings_files=on --write_settings_files=off cpld -c cpld Info (12021): Found 1 design units, including 1 entities, in source file m837cc.v Info (12023): Found entity 1: m837cc Info (12021): Found 1 design units, including 1 entities, in source file m8650d.v Info (12023): Found entity 1: m8650d Warning (10275): Verilog HDL Module Instantiation warning at cpld.v(321): ignored dangling comma in List of Port Connections Info (12021): Found 1 design units, including 1 entities, in source file cpld.v Info (12023): Found entity 1: cpld Warning (10236): Verilog HDL Implicit Net warning at M8650D.v(959): created implicit net for "n_t_60x_d" Info (12127): Elaborating entity "cpld" for the top level hierarchy Info (12128): Elaborating entity "m8650d" for hierarchy "m8650d:m8650d" Warning (10240): Verilog HDL Always Construct warning at M8650D.v(326): inferring latch(es) for variable "rx_div_m", which holds its previous value in one or more paths through the always construct Warning (10240): Verilog HDL Always Construct warning at M8650D.v(336): inferring latch(es) for variable "rx_div", which holds its previous value in one or more paths through the always construct Warning (10240): Verilog HDL Always Construct warning at M8650D.v(346): inferring latch(es) for variable "ck_pulse_m", which holds its previous value in one or more paths through the always construct Warning (10240): Verilog HDL Always Construct warning at M8650D.v(356): inferring latch(es) for variable "ck_pulse", which holds its previous value in one or more paths through the always construct Warning (10240): Verilog HDL Always Construct warning at M8650D.v(367): inferring latch(es) for variable "n_t_43x_m", which holds its previous value in one or more paths through the always construct Warning (10240): Verilog HDL Always Construct warning at M8650D.v(377): inferring latch(es) for variable "n_t_43x", which holds its previous value in one or more paths through the always construct Warning (10240): Verilog HDL Always Construct warning at M8650D.v(387): inferring latch(es) for variable "n_t_75x_m", which holds its previous value in one or more paths through the always construct Warning (10240): Verilog HDL Always Construct warning at M8650D.v(397): inferring latch(es) for variable "n_t_75x", which holds its previous value in one or more paths through the always construct Warning (10240): Verilog HDL Always Construct warning at M8650D.v(425): inferring latch(es) for variable "n_t_30x_m", which holds its previous value in one or more paths through the always construct Warning (10240): Verilog HDL Always Construct warning at M8650D.v(434): inferring latch(es) for variable "n_t_30x", which holds its previous value in one or more paths through the always construct Warning (10240): Verilog HDL Always Construct warning at M8650D.v(441): inferring latch(es) for variable "n_t_34x_m", which holds its previous value in one or more paths through the always construct Warning (10240): Verilog HDL Always Construct warning at M8650D.v(450): inferring latch(es) for variable "n_t_34x", which holds its previous value in one or more paths through the always construct Warning (10240): Verilog HDL Always Construct warning at M8650D.v(457): inferring latch(es) for variable "n_t_36x_m", which holds its previous value in one or more paths through the always construct Warning (10240): Verilog HDL Always Construct warning at M8650D.v(466): inferring latch(es) for variable "n_t_36x", which holds its previous value in one or more paths through the always construct Warning (10240): Verilog HDL Always Construct warning at M8650D.v(473): inferring latch(es) for variable "n_t_35x_m", which holds its previous value in one or more paths through the always construct Warning (10240): Verilog HDL Always Construct warning at M8650D.v(482): inferring latch(es) for variable "n_t_35x", which holds its previous value in one or more paths through the always construct Warning (10240): Verilog HDL Always Construct warning at M8650D.v(490): inferring latch(es) for variable "rx_active_m", which holds its previous value in one or more paths through the always construct Warning (10240): Verilog HDL Always Construct warning at M8650D.v(500): inferring latch(es) for variable "rx_active", which holds its previous value in one or more paths through the always construct Warning (10240): Verilog HDL Always Construct warning at M8650D.v(510): inferring latch(es) for variable "p_pulse_l_m", which holds its previous value in one or more paths through the always construct Warning (10240): Verilog HDL Always Construct warning at M8650D.v(520): inferring latch(es) for variable "p_pulse_l", which holds its previous value in one or more paths through the always construct Warning (10240): Verilog HDL Always Construct warning at M8650D.v(531): inferring latch(es) for variable "last_unit_m", which holds its previous value in one or more paths through the always construct Warning (10240): Verilog HDL Always Construct warning at M8650D.v(541): inferring latch(es) for variable "last_unit", which holds its previous value in one or more paths through the always construct Warning (10240): Verilog HDL Always Construct warning at M8650D.v(551): inferring latch(es) for variable "n_t_88x_m", which holds its previous value in one or more paths through the always construct Warning (10240): Verilog HDL Always Construct warning at M8650D.v(561): inferring latch(es) for variable "n_t_88x", which holds its previous value in one or more paths through the always construct Warning (10240): Verilog HDL Always Construct warning at M8650D.v(580): inferring latch(es) for variable "n_t_37x_m", which holds its previous value in one or more paths through the always construct Warning (10240): Verilog HDL Always Construct warning at M8650D.v(589): inferring latch(es) for variable "n_t_37x", which holds its previous value in one or more paths through the always construct Warning (10240): Verilog HDL Always Construct warning at M8650D.v(596): inferring latch(es) for variable "n_t_38x_m", which holds its previous value in one or more paths through the always construct Warning (10240): Verilog HDL Always Construct warning at M8650D.v(605): inferring latch(es) for variable "n_t_38x", which holds its previous value in one or more paths through the always construct Warning (10240): Verilog HDL Always Construct warning at M8650D.v(612): inferring latch(es) for variable "n_t_39x_m", which holds its previous value in one or more paths through the always construct Warning (10240): Verilog HDL Always Construct warning at M8650D.v(621): inferring latch(es) for variable "n_t_39x", which holds its previous value in one or more paths through the always construct Warning (10240): Verilog HDL Always Construct warning at M8650D.v(628): inferring latch(es) for variable "n_t_40x_m", which holds its previous value in one or more paths through the always construct Warning (10240): Verilog HDL Always Construct warning at M8650D.v(637): inferring latch(es) for variable "n_t_40x", which holds its previous value in one or more paths through the always construct Warning (10240): Verilog HDL Always Construct warning at M8650D.v(681): inferring latch(es) for variable "tx_div_m", which holds its previous value in one or more paths through the always construct Warning (10240): Verilog HDL Always Construct warning at M8650D.v(691): inferring latch(es) for variable "tx_div", which holds its previous value in one or more paths through the always construct Warning (10240): Verilog HDL Always Construct warning at M8650D.v(702): inferring latch(es) for variable "spike_det_l_m", which holds its previous value in one or more paths through the always construct Warning (10240): Verilog HDL Always Construct warning at M8650D.v(712): inferring latch(es) for variable "spike_det_l", which holds its previous value in one or more paths through the always construct Warning (10240): Verilog HDL Always Construct warning at M8650D.v(744): inferring latch(es) for variable "tx_active_l_m", which holds its previous value in one or more paths through the always construct Warning (10240): Verilog HDL Always Construct warning at M8650D.v(754): inferring latch(es) for variable "tx_active_l", which holds its previous value in one or more paths through the always construct Warning (10240): Verilog HDL Always Construct warning at M8650D.v(765): inferring latch(es) for variable "start_l_m", which holds its previous value in one or more paths through the always construct Warning (10240): Verilog HDL Always Construct warning at M8650D.v(775): inferring latch(es) for variable "start_l", which holds its previous value in one or more paths through the always construct Warning (10240): Verilog HDL Always Construct warning at M8650D.v(788): inferring latch(es) for variable "gdollar_4_m", which holds its previous value in one or more paths through the always construct Warning (10240): Verilog HDL Always Construct warning at M8650D.v(796): inferring latch(es) for variable "gdollar_4", which holds its previous value in one or more paths through the always construct Warning (10240): Verilog HDL Always Construct warning at M8650D.v(804): inferring latch(es) for variable "gdollar_5_m", which holds its previous value in one or more paths through the always construct Warning (10240): Verilog HDL Always Construct warning at M8650D.v(812): inferring latch(es) for variable "gdollar_5", which holds its previous value in one or more paths through the always construct Warning (10240): Verilog HDL Always Construct warning at M8650D.v(820): inferring latch(es) for variable "gdollar_6_m", which holds its previous value in one or more paths through the always construct Warning (10240): Verilog HDL Always Construct warning at M8650D.v(828): inferring latch(es) for variable "gdollar_6", which holds its previous value in one or more paths through the always construct Warning (10240): Verilog HDL Always Construct warning at M8650D.v(836): inferring latch(es) for variable "n_t_154x_m", which holds its previous value in one or more paths through the always construct Warning (10240): Verilog HDL Always Construct warning at M8650D.v(844): inferring latch(es) for variable "n_t_154x", which holds its previous value in one or more paths through the always construct Warning (10240): Verilog HDL Always Construct warning at M8650D.v(876): inferring latch(es) for variable "n_t_146x_m", which holds its previous value in one or more paths through the always construct Warning (10240): Verilog HDL Always Construct warning at M8650D.v(885): inferring latch(es) for variable "n_t_146x", which holds its previous value in one or more paths through the always construct Warning (10240): Verilog HDL Always Construct warning at M8650D.v(892): inferring latch(es) for variable "gdollar_7_m", which holds its previous value in one or more paths through the always construct Warning (10240): Verilog HDL Always Construct warning at M8650D.v(901): inferring latch(es) for variable "gdollar_7", which holds its previous value in one or more paths through the always construct Warning (10240): Verilog HDL Always Construct warning at M8650D.v(908): inferring latch(es) for variable "n_t_119x_m", which holds its previous value in one or more paths through the always construct Warning (10240): Verilog HDL Always Construct warning at M8650D.v(917): inferring latch(es) for variable "n_t_119x", which holds its previous value in one or more paths through the always construct Warning (10240): Verilog HDL Always Construct warning at M8650D.v(924): inferring latch(es) for variable "gdollar_8_m", which holds its previous value in one or more paths through the always construct Warning (10240): Verilog HDL Always Construct warning at M8650D.v(933): inferring latch(es) for variable "gdollar_8", which holds its previous value in one or more paths through the always construct Warning (10235): Verilog HDL Always Construct warning at M8650D.v(967): variable "n_t_60x_d" is read inside the Always Construct but isn't in the Always Construct's Event Control Warning (10240): Verilog HDL Always Construct warning at M8650D.v(962): inferring latch(es) for variable "n_t_60x_m", which holds its previous value in one or more paths through the always construct Warning (10240): Verilog HDL Always Construct warning at M8650D.v(968): inferring latch(es) for variable "n_t_60x", which holds its previous value in one or more paths through the always construct Warning (10240): Verilog HDL Always Construct warning at M8650D.v(975): inferring latch(es) for variable "n_t_62x_m", which holds its previous value in one or more paths through the always construct Warning (10240): Verilog HDL Always Construct warning at M8650D.v(984): inferring latch(es) for variable "n_t_62x", which holds its previous value in one or more paths through the always construct Warning (10240): Verilog HDL Always Construct warning at M8650D.v(991): inferring latch(es) for variable "n_t_56x_m", which holds its previous value in one or more paths through the always construct Warning (10240): Verilog HDL Always Construct warning at M8650D.v(1000): inferring latch(es) for variable "n_t_56x", which holds its previous value in one or more paths through the always construct Warning (10240): Verilog HDL Always Construct warning at M8650D.v(1007): inferring latch(es) for variable "n_t_61x_m", which holds its previous value in one or more paths through the always construct Warning (10240): Verilog HDL Always Construct warning at M8650D.v(1016): inferring latch(es) for variable "n_t_61x", which holds its previous value in one or more paths through the always construct Warning (10240): Verilog HDL Always Construct warning at M8650D.v(1024): inferring latch(es) for variable "line_m", which holds its previous value in one or more paths through the always construct Warning (10240): Verilog HDL Always Construct warning at M8650D.v(1034): inferring latch(es) for variable "line", which holds its previous value in one or more paths through the always construct Warning (10240): Verilog HDL Always Construct warning at M8650D.v(1045): inferring latch(es) for variable "enab_m", which holds its previous value in one or more paths through the always construct Warning (10240): Verilog HDL Always Construct warning at M8650D.v(1055): inferring latch(es) for variable "enab", which holds its previous value in one or more paths through the always construct Warning (10240): Verilog HDL Always Construct warning at M8650D.v(1075): inferring latch(es) for variable "n_t_63x_m", which holds its previous value in one or more paths through the always construct Warning (10240): Verilog HDL Always Construct warning at M8650D.v(1084): inferring latch(es) for variable "n_t_63x", which holds its previous value in one or more paths through the always construct Warning (10240): Verilog HDL Always Construct warning at M8650D.v(1091): inferring latch(es) for variable "n_t_65x_m", which holds its previous value in one or more paths through the always construct Warning (10240): Verilog HDL Always Construct warning at M8650D.v(1100): inferring latch(es) for variable "n_t_65x", which holds its previous value in one or more paths through the always construct Warning (10240): Verilog HDL Always Construct warning at M8650D.v(1107): inferring latch(es) for variable "n_t_66x_m", which holds its previous value in one or more paths through the always construct Warning (10240): Verilog HDL Always Construct warning at M8650D.v(1116): inferring latch(es) for variable "n_t_66x", which holds its previous value in one or more paths through the always construct Warning (10240): Verilog HDL Always Construct warning at M8650D.v(1123): inferring latch(es) for variable "tx_data_m", which holds its previous value in one or more paths through the always construct Warning (10240): Verilog HDL Always Construct warning at M8650D.v(1132): inferring latch(es) for variable "tx_data", which holds its previous value in one or more paths through the always construct Warning (10240): Verilog HDL Always Construct warning at M8650D.v(1159): inferring latch(es) for variable "tflg_l_m", which holds its previous value in one or more paths through the always construct Warning (10240): Verilog HDL Always Construct warning at M8650D.v(1169): inferring latch(es) for variable "tflg_l", which holds its previous value in one or more paths through the always construct Warning (10240): Verilog HDL Always Construct warning at M8650D.v(1179): inferring latch(es) for variable "int_enab_l_m", which holds its previous value in one or more paths through the always construct Warning (10240): Verilog HDL Always Construct warning at M8650D.v(1189): inferring latch(es) for variable "int_enab_l", which holds its previous value in one or more paths through the always construct Warning (10240): Verilog HDL Always Construct warning at M8650D.v(1254): inferring latch(es) for variable "rflg_l_m", which holds its previous value in one or more paths through the always construct Warning (10240): Verilog HDL Always Construct warning at M8650D.v(1264): inferring latch(es) for variable "rflg_l", which holds its previous value in one or more paths through the always construct Warning (10240): Verilog HDL Always Construct warning at M8650D.v(1274): inferring latch(es) for variable "r_run_l_m", which holds its previous value in one or more paths through the always construct Warning (10240): Verilog HDL Always Construct warning at M8650D.v(1284): inferring latch(es) for variable "r_run_l", which holds its previous value in one or more paths through the always construct Warning (10034): Output port "n_t_77x" at M8650D.v(88) has no driver Warning (10034): Output port "eia_in" at M8650D.v(114) has no driver Warning (10034): Output port "eia_out" at M8650D.v(115) has no driver Warning (10034): Output port "n15v" at M8650D.v(133) has no driver Warning (10034): Output port "reader_run" at M8650D.v(150) has no driver Warning (10034): Output port "reader_run_or" at M8650D.v(151) has no driver Warning (10034): Output port "rtsdtr" at M8650D.v(152) has no driver Warning (10034): Output port "rx_20ma" at M8650D.v(154) has no driver Warning (10034): Output port "rx_20ma_or" at M8650D.v(155) has no driver Warning (10034): Output port "tx_20ma" at M8650D.v(165) has no driver Warning (10034): Output port "tx_20ma_or" at M8650D.v(166) has no driver Info (10041): Inferred latch for "r_run_l" at M8650D.v(1284) Info (10041): Inferred latch for "r_run_l_m" at M8650D.v(1274) Info (10041): Inferred latch for "rflg_l" at M8650D.v(1264) Info (10041): Inferred latch for "rflg_l_m" at M8650D.v(1254) Info (10041): Inferred latch for "int_enab_l" at M8650D.v(1189) Info (10041): Inferred latch for "int_enab_l_m" at M8650D.v(1179) Info (10041): Inferred latch for "tflg_l" at M8650D.v(1169) Info (10041): Inferred latch for "tflg_l_m" at M8650D.v(1159) Info (10041): Inferred latch for "tx_data" at M8650D.v(1132) Info (10041): Inferred latch for "tx_data_m" at M8650D.v(1123) Info (10041): Inferred latch for "n_t_66x" at M8650D.v(1116) Info (10041): Inferred latch for "n_t_66x_m" at M8650D.v(1107) Info (10041): Inferred latch for "n_t_65x" at M8650D.v(1100) Info (10041): Inferred latch for "n_t_65x_m" at M8650D.v(1091) Info (10041): Inferred latch for "n_t_63x" at M8650D.v(1084) Info (10041): Inferred latch for "n_t_63x_m" at M8650D.v(1075) Info (10041): Inferred latch for "enab" at M8650D.v(1055) Info (10041): Inferred latch for "enab_m" at M8650D.v(1045) Info (10041): Inferred latch for "line" at M8650D.v(1034) Info (10041): Inferred latch for "line_m" at M8650D.v(1024) Info (10041): Inferred latch for "n_t_61x" at M8650D.v(1016) Info (10041): Inferred latch for "n_t_61x_m" at M8650D.v(1007) Info (10041): Inferred latch for "n_t_56x" at M8650D.v(1000) Info (10041): Inferred latch for "n_t_56x_m" at M8650D.v(991) Info (10041): Inferred latch for "n_t_62x" at M8650D.v(984) Info (10041): Inferred latch for "n_t_62x_m" at M8650D.v(975) Info (10041): Inferred latch for "n_t_60x" at M8650D.v(968) Info (10041): Inferred latch for "n_t_60x_m" at M8650D.v(962) Info (10041): Inferred latch for "n_t_119x" at M8650D.v(917) Info (10041): Inferred latch for "n_t_119x_m" at M8650D.v(908) Info (10041): Inferred latch for "gdollar_7" at M8650D.v(901) Info (10041): Inferred latch for "gdollar_7_m" at M8650D.v(892) Info (10041): Inferred latch for "n_t_146x" at M8650D.v(885) Info (10041): Inferred latch for "n_t_146x_m" at M8650D.v(876) Info (10041): Inferred latch for "n_t_154x" at M8650D.v(844) Info (10041): Inferred latch for "n_t_154x_m" at M8650D.v(836) Info (10041): Inferred latch for "gdollar_6" at M8650D.v(828) Info (10041): Inferred latch for "gdollar_6_m" at M8650D.v(820) Info (10041): Inferred latch for "gdollar_5" at M8650D.v(812) Info (10041): Inferred latch for "gdollar_5_m" at M8650D.v(804) Info (10041): Inferred latch for "gdollar_4" at M8650D.v(796) Info (10041): Inferred latch for "gdollar_4_m" at M8650D.v(788) Info (10041): Inferred latch for "start_l" at M8650D.v(775) Info (10041): Inferred latch for "start_l_m" at M8650D.v(765) Info (10041): Inferred latch for "tx_active_l" at M8650D.v(754) Info (10041): Inferred latch for "tx_active_l_m" at M8650D.v(744) Info (10041): Inferred latch for "spike_det_l" at M8650D.v(712) Info (10041): Inferred latch for "spike_det_l_m" at M8650D.v(702) Info (10041): Inferred latch for "tx_div" at M8650D.v(691) Info (10041): Inferred latch for "tx_div_m" at M8650D.v(681) Info (10041): Inferred latch for "n_t_40x" at M8650D.v(637) Info (10041): Inferred latch for "n_t_40x_m" at M8650D.v(628) Info (10041): Inferred latch for "n_t_39x" at M8650D.v(621) Info (10041): Inferred latch for "n_t_39x_m" at M8650D.v(612) Info (10041): Inferred latch for "n_t_38x" at M8650D.v(605) Info (10041): Inferred latch for "n_t_38x_m" at M8650D.v(596) Info (10041): Inferred latch for "n_t_37x" at M8650D.v(589) Info (10041): Inferred latch for "n_t_37x_m" at M8650D.v(580) Info (10041): Inferred latch for "n_t_88x" at M8650D.v(561) Info (10041): Inferred latch for "n_t_88x_m" at M8650D.v(551) Info (10041): Inferred latch for "last_unit" at M8650D.v(541) Info (10041): Inferred latch for "last_unit_m" at M8650D.v(531) Info (10041): Inferred latch for "p_pulse_l" at M8650D.v(520) Info (10041): Inferred latch for "p_pulse_l_m" at M8650D.v(510) Info (10041): Inferred latch for "rx_active" at M8650D.v(500) Info (10041): Inferred latch for "rx_active_m" at M8650D.v(490) Info (10041): Inferred latch for "n_t_35x" at M8650D.v(482) Info (10041): Inferred latch for "n_t_35x_m" at M8650D.v(473) Info (10041): Inferred latch for "n_t_36x" at M8650D.v(466) Info (10041): Inferred latch for "n_t_36x_m" at M8650D.v(457) Info (10041): Inferred latch for "n_t_34x" at M8650D.v(450) Info (10041): Inferred latch for "n_t_34x_m" at M8650D.v(441) Info (10041): Inferred latch for "n_t_30x" at M8650D.v(434) Info (10041): Inferred latch for "n_t_30x_m" at M8650D.v(425) Info (10041): Inferred latch for "n_t_75x" at M8650D.v(397) Info (10041): Inferred latch for "n_t_75x_m" at M8650D.v(387) Info (10041): Inferred latch for "n_t_43x" at M8650D.v(377) Info (10041): Inferred latch for "n_t_43x_m" at M8650D.v(367) Info (10041): Inferred latch for "ck_pulse" at M8650D.v(356) Info (10041): Inferred latch for "ck_pulse_m" at M8650D.v(346) Info (10041): Inferred latch for "rx_div" at M8650D.v(336) Info (10041): Inferred latch for "rx_div_m" at M8650D.v(326) Warning (14025): LATCH primitive "m8650d:m8650d|spike_det_l_m" is permanently disabled Warning (14025): LATCH primitive "m8650d:m8650d|p_pulse_l" is permanently disabled Warning (14025): LATCH primitive "m8650d:m8650d|ck_pulse" is permanently disabled Warning (14025): LATCH primitive "m8650d:m8650d|last_unit" is permanently disabled Warning (14025): LATCH primitive "m8650d:m8650d|rflg_l" is permanently disabled Warning (14026): LATCH primitive "m8650d:m8650d|n_t_40x_m" is permanently enabled Warning (14025): LATCH primitive "m8650d:m8650d|n_t_39x" is permanently disabled Warning (14025): LATCH primitive "m8650d:m8650d|n_t_38x" is permanently disabled Warning (14025): LATCH primitive "m8650d:m8650d|n_t_37x" is permanently disabled Warning (14026): LATCH primitive "m8650d:m8650d|n_t_35x_m" is permanently enabled Warning (14025): LATCH primitive "m8650d:m8650d|n_t_36x" is permanently disabled Warning (12241): 1 hierarchies have connectivity warnings - see the Connectivity Checks report folder Warning (13039): The following bidir pins have no drivers Warning (13040): Bidir "data03_l" has no driver Warning (13040): Bidir "data02_l" has no driver Warning (13040): Bidir "data01_l" has no driver Warning (13040): Bidir "data00_l" has no driver Warning (13024): Output pins are stuck at VCC or GND Warning (13410): Pin "rxdttl" is stuck at GND Info (280013): Promoted pin-driven signal(s) to global signal Info (280014): Promoted clock signal driven by pin "clk" to global clock signal Warning (21074): Design contains 26 input pin(s) that do not drive logic Warning (15610): No output dependent on input pin "pulse_la" Warning (15610): No output dependent on input pin "f_set_l" Warning (15610): No output dependent on input pin "user_mode_l" Warning (15610): No output dependent on input pin "d_l" Warning (15610): No output dependent on input pin "f_l" Warning (15610): No output dependent on input pin "ir01_l" Warning (15610): No output dependent on input pin "ir00_l" Warning (15610): No output dependent on input pin "ind2_l" Warning (15610): No output dependent on input pin "ind1_l" Warning (15610): No output dependent on input pin "cpma_disable_l" Warning (15610): No output dependent on input pin "ts3_l" Warning (15610): No output dependent on input pin "ts1_l" Warning (15610): No output dependent on input pin "tp4" Warning (15610): No output dependent on input pin "tp2" Warning (15610): No output dependent on input pin "df_enable" Warning (15610): No output dependent on input pin "power_ok" Warning (15610): No output dependent on input pin "run_l" Warning (15610): No output dependent on input pin "int_in_prog_l" Warning (15610): No output dependent on input pin "load_cont_l" Warning (15610): No output dependent on input pin "md02_l" Warning (15610): No output dependent on input pin "md01_l" Warning (15610): No output dependent on input pin "md00_l" Warning (15610): No output dependent on input pin "ema2_l" Warning (15610): No output dependent on input pin "ema1_l" Warning (15610): No output dependent on input pin "ema0_l" Warning (15610): No output dependent on input pin "key_ctl_l" Info (21057): Implemented 157 device resources after synthesis - the final resource count might be different Info (21058): Implemented 45 input pins Info (21059): Implemented 7 output pins Info (21060): Implemented 12 bidirectional pins Info (21063): Implemented 86 macrocells Info (21073): Implemented 7 shareable expanders Info (144001): Generated suppressed messages file //wsl.localhost/Debian/home/vrs/Verilog/projects/32k-Omnibus/output_files/cpld.map.smsg Info: Quartus II 64-Bit Analysis & Synthesis was successful. 0 errors, 144 warnings Info: Peak virtual memory: 4577 megabytes Info: Processing ended: Sat Nov 18 05:23:54 2023 Info: Elapsed time: 00:00:03 Info: Total CPU time (on all processors): 00:00:01 +------------------------------------------+ ; Analysis & Synthesis Suppressed Messages ; +------------------------------------------+ The suppressed messages can be found in //wsl.localhost/Debian/home/vrs/Verilog/projects/32k-Omnibus/output_files/cpld.map.smsg.