{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" {  } {  } 3 0 "*******************************************************************" 0 0 "Quartus II" 0 -1 1712870254893 ""}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Analysis & Synthesis Quartus II 64-Bit " "Running Quartus II 64-Bit Analysis & Synthesis" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition " "Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition" {  } {  } 0 0 "%1!s!" 0 0 "Quartus II" 0 -1 1712870254893 ""} { "Info" "IQEXE_START_BANNER_TIME" "Thu Apr 11 14:17:34 2024 " "Processing started: Thu Apr 11 14:17:34 2024" {  } {  } 0 0 "Processing started: %1!s!" 0 0 "Quartus II" 0 -1 1712870254893 ""}  } {  } 4 0 "Running %2!s! %1!s!" 0 0 "Quartus II" 0 -1 1712870254893 ""}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --read_settings_files=on --write_settings_files=off e11 -c e11 " "Command: quartus_map --read_settings_files=on --write_settings_files=off e11 -c e11" {  } {  } 0 0 "Command: %1!s!" 0 0 "Quartus II" 0 -1 1712870254893 ""}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "e11.v 1 1 " "Found 1 design units, including 1 entities, in source file e11.v" { { "Info" "ISGN_ENTITY_NAME" "1 e11 " "Found entity 1: e11" {  } { { "e11.v" "" { Text "//wsl.localhost/Debian/home/vrs/Verilog/projects/pt08/e11.v" 33 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1712870255568 ""}  } {  } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1712870255568 ""}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "m707.v 1 1 " "Found 1 design units, including 1 entities, in source file m707.v" { { "Info" "ISGN_ENTITY_NAME" "1 m707 " "Found entity 1: m707" {  } { { "m707.v" "" { Text "//wsl.localhost/Debian/home/vrs/Verilog/projects/pt08/m707.v" 2 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1712870255614 ""}  } {  } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1712870255614 ""}
{ "Info" "ISGN_START_ELABORATION_TOP" "e11 " "Elaborating entity \"e11\" for the top level hierarchy" {  } {  } 0 12127 "Elaborating entity \"%1!s!\" for the top level hierarchy" 0 0 "Quartus II" 0 -1 1712870255662 ""}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "m707 m707:m707 " "Elaborating entity \"m707\" for hierarchy \"m707:m707\"" {  } { { "e11.v" "m707" { Text "//wsl.localhost/Debian/home/vrs/Verilog/projects/pt08/e11.v" 80 0 0 } }  } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1712870255693 ""}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 3 m707.v(78) " "Verilog HDL assignment warning at m707.v(78): truncated value with size 32 to match size of target (3)" {  } { { "m707.v" "" { Text "//wsl.localhost/Debian/home/vrs/Verilog/projects/pt08/m707.v" 78 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1712870255709 "|e11|m707:m707"}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 9 m707.v(94) " "Verilog HDL assignment warning at m707.v(94): truncated value with size 32 to match size of target (9)" {  } { { "m707.v" "" { Text "//wsl.localhost/Debian/home/vrs/Verilog/projects/pt08/m707.v" 94 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1712870255709 "|e11|m707:m707"}
{ "Info" "IMLS_MLS_PRESET_POWER_UP" "" "Registers with preset signals will power-up high" {  } { { "m707.v" "" { Text "//wsl.localhost/Debian/home/vrs/Verilog/projects/pt08/m707.v" 80 -1 0 } }  } 0 13000 "Registers with preset signals will power-up high" 0 0 "Quartus II" 0 -1 1712870255944 ""}
{ "Info" "IMTM_MTM_PROMOTE_GLOBAL" "" "Promoted pin-driven signal(s) to global signal" { { "Info" "IMTM_MTM_PROMOTE_GLOBAL_CLOCK" "tx_ratei " "Promoted clock signal driven by pin \"tx_ratei\" to global clock signal" {  } {  } 0 280014 "Promoted clock signal driven by pin \"%1!s!\" to global clock signal" 0 0 "Quartus II" 0 -1 1712870255944 ""} { "Info" "IMTM_MTM_PROMOTE_GLOBAL_CLOCK" "rx_rate " "Promoted clock signal driven by pin \"rx_rate\" to global clock signal" {  } {  } 0 280014 "Promoted clock signal driven by pin \"%1!s!\" to global clock signal" 0 0 "Quartus II" 0 -1 1712870255944 ""}  } {  } 0 280013 "Promoted pin-driven signal(s) to global signal" 0 0 "Quartus II" 0 -1 1712870255944 ""}
{ "Warning" "WCUT_CUT_UNNECESSARY_INPUT_PIN_HDR" "5 " "Design contains 5 input pin(s) that do not drive logic" { { "Warning" "WCUT_CUT_UNNECESSARY_INPUT_PIN" "bac3 " "No output dependent on input pin \"bac3\"" {  } { { "e11.v" "" { Text "//wsl.localhost/Debian/home/vrs/Verilog/projects/pt08/e11.v" 35 -1 0 } }  } 0 15610 "No output dependent on input pin \"%1!s!\"" 0 0 "Quartus II" 0 -1 1712870255975 "|e11|bac3"} { "Warning" "WCUT_CUT_UNNECESSARY_INPUT_PIN" "bac2 " "No output dependent on input pin \"bac2\"" {  } { { "e11.v" "" { Text "//wsl.localhost/Debian/home/vrs/Verilog/projects/pt08/e11.v" 35 -1 0 } }  } 0 15610 "No output dependent on input pin \"%1!s!\"" 0 0 "Quartus II" 0 -1 1712870255975 "|e11|bac2"} { "Warning" "WCUT_CUT_UNNECESSARY_INPUT_PIN" "bac1 " "No output dependent on input pin \"bac1\"" {  } { { "e11.v" "" { Text "//wsl.localhost/Debian/home/vrs/Verilog/projects/pt08/e11.v" 35 -1 0 } }  } 0 15610 "No output dependent on input pin \"%1!s!\"" 0 0 "Quartus II" 0 -1 1712870255975 "|e11|bac1"} { "Warning" "WCUT_CUT_UNNECESSARY_INPUT_PIN" "bac0 " "No output dependent on input pin \"bac0\"" {  } { { "e11.v" "" { Text "//wsl.localhost/Debian/home/vrs/Verilog/projects/pt08/e11.v" 35 -1 0 } }  } 0 15610 "No output dependent on input pin \"%1!s!\"" 0 0 "Quartus II" 0 -1 1712870255975 "|e11|bac0"} { "Warning" "WCUT_CUT_UNNECESSARY_INPUT_PIN" "rx_sel " "No output dependent on input pin \"rx_sel\"" {  } { { "e11.v" "" { Text "//wsl.localhost/Debian/home/vrs/Verilog/projects/pt08/e11.v" 34 -1 0 } }  } 0 15610 "No output dependent on input pin \"%1!s!\"" 0 0 "Quartus II" 0 -1 1712870255975 "|e11|rx_sel"}  } {  } 0 21074 "Design contains %1!d! input pin(s) that do not drive logic" 0 0 "Quartus II" 0 -1 1712870255975 ""}
{ "Info" "ICUT_CUT_TM_SUMMARY" "51 " "Implemented 51 device resources after synthesis - the final resource count might be different" { { "Info" "ICUT_CUT_TM_IPINS" "21 " "Implemented 21 input pins" {  } {  } 0 21058 "Implemented %1!d! input pins" 0 0 "Quartus II" 0 -1 1712870255991 ""} { "Info" "ICUT_CUT_TM_OPINS" "7 " "Implemented 7 output pins" {  } {  } 0 21059 "Implemented %1!d! output pins" 0 0 "Quartus II" 0 -1 1712870255991 ""} { "Info" "ICUT_CUT_TM_MCELLS" "21 " "Implemented 21 macrocells" {  } {  } 0 21063 "Implemented %1!d! macrocells" 0 0 "Quartus II" 0 -1 1712870255991 ""} { "Info" "ICUT_CUT_TM_SEXPS" "2 " "Implemented 2 shareable expanders" {  } {  } 0 21073 "Implemented %1!d! shareable expanders" 0 0 "Quartus II" 0 -1 1712870255991 ""}  } {  } 0 21057 "Implemented %1!d! device resources after synthesis - the final resource count might be different" 0 0 "Quartus II" 0 -1 1712870255991 ""}
{ "Info" "IQEXE_ERROR_COUNT" "Analysis & Synthesis 0 s 8 s Quartus II 64-Bit " "Quartus II 64-Bit Analysis & Synthesis was successful. 0 errors, 8 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "4570 " "Peak virtual memory: 4570 megabytes" {  } {  } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Quartus II" 0 -1 1712870256116 ""} { "Info" "IQEXE_END_BANNER_TIME" "Thu Apr 11 14:17:36 2024 " "Processing ended: Thu Apr 11 14:17:36 2024" {  } {  } 0 0 "Processing ended: %1!s!" 0 0 "Quartus II" 0 -1 1712870256116 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:02 " "Elapsed time: 00:00:02" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0 "Quartus II" 0 -1 1712870256116 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:00 " "Total CPU time (on all processors): 00:00:00" {  } {  } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Quartus II" 0 -1 1712870256116 ""}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Quartus II" 0 -1 1712870256116 ""}