{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" {  } {  } 3 0 "*******************************************************************" 0 0 "Quartus II" 0 -1 1712871322776 ""}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Analysis & Synthesis Quartus II 64-Bit " "Running Quartus II 64-Bit Analysis & Synthesis" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition " "Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition" {  } {  } 0 0 "%1!s!" 0 0 "Quartus II" 0 -1 1712871322776 ""} { "Info" "IQEXE_START_BANNER_TIME" "Thu Apr 11 14:35:22 2024 " "Processing started: Thu Apr 11 14:35:22 2024" {  } {  } 0 0 "Processing started: %1!s!" 0 0 "Quartus II" 0 -1 1712871322776 ""}  } {  } 4 0 "Running %2!s! %1!s!" 0 0 "Quartus II" 0 -1 1712871322776 ""}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --read_settings_files=on --write_settings_files=off e2 -c e2 " "Command: quartus_map --read_settings_files=on --write_settings_files=off e2 -c e2" {  } {  } 0 0 "Command: %1!s!" 0 0 "Quartus II" 0 -1 1712871322776 ""}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "e2.v 1 1 " "Found 1 design units, including 1 entities, in source file e2.v" { { "Info" "ISGN_ENTITY_NAME" "1 e2 " "Found entity 1: e2" {  } { { "e2.v" "" { Text "//wsl.localhost/Debian/home/vrs/Verilog/projects/pt08/e2.v" 36 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1712871323467 ""}  } {  } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1712871323467 ""}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "m706.v 1 1 " "Found 1 design units, including 1 entities, in source file m706.v" { { "Info" "ISGN_ENTITY_NAME" "1 m706 " "Found entity 1: m706" {  } { { "m706.v" "" { Text "//wsl.localhost/Debian/home/vrs/Verilog/projects/pt08/m706.v" 2 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1712871323498 ""}  } {  } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1712871323498 ""}
{ "Info" "ISGN_START_ELABORATION_TOP" "e2 " "Elaborating entity \"e2\" for the top level hierarchy" {  } {  } 0 12127 "Elaborating entity \"%1!s!\" for the top level hierarchy" 0 0 "Quartus II" 0 -1 1712871323561 ""}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "m706 m706:m706 " "Elaborating entity \"m706\" for hierarchy \"m706:m706\"" {  } { { "e2.v" "m706" { Text "//wsl.localhost/Debian/home/vrs/Verilog/projects/pt08/e2.v" 92 0 0 } }  } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1712871323592 ""}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 3 m706.v(136) " "Verilog HDL assignment warning at m706.v(136): truncated value with size 32 to match size of target (3)" {  } { { "m706.v" "" { Text "//wsl.localhost/Debian/home/vrs/Verilog/projects/pt08/m706.v" 136 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1712871323592 "|e2|m706:m706"}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 8 m706.v(178) " "Verilog HDL assignment warning at m706.v(178): truncated value with size 32 to match size of target (8)" {  } { { "m706.v" "" { Text "//wsl.localhost/Debian/home/vrs/Verilog/projects/pt08/m706.v" 178 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1712871323592 "|e2|m706:m706"}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 8 m706.v(186) " "Verilog HDL assignment warning at m706.v(186): truncated value with size 32 to match size of target (8)" {  } { { "m706.v" "" { Text "//wsl.localhost/Debian/home/vrs/Verilog/projects/pt08/m706.v" 186 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1712871323592 "|e2|m706:m706"}
{ "Info" "IMLS_MLS_PRESET_POWER_UP" "" "Registers with preset signals will power-up high" {  } { { "m706.v" "" { Text "//wsl.localhost/Debian/home/vrs/Verilog/projects/pt08/m706.v" 80 -1 0 } } { "m706.v" "" { Text "//wsl.localhost/Debian/home/vrs/Verilog/projects/pt08/m706.v" 180 -1 0 } }  } 0 13000 "Registers with preset signals will power-up high" 0 0 "Quartus II" 0 -1 1712871323812 ""}
{ "Info" "IMTM_MTM_PROMOTE_GLOBAL" "" "Promoted pin-driven signal(s) to global signal" { { "Info" "IMTM_MTM_PROMOTE_GLOBAL_CLOCK" "rx_rate " "Promoted clock signal driven by pin \"rx_rate\" to global clock signal" {  } {  } 0 280014 "Promoted clock signal driven by pin \"%1!s!\" to global clock signal" 0 0 "Quartus II" 0 -1 1712871323828 ""} { "Info" "IMTM_MTM_PROMOTE_GLOBAL_CLEAR" "init_l " "Promoted clear signal driven by pin \"init_l\" to global clear signal" {  } {  } 0 280015 "Promoted clear signal driven by pin \"%1!s!\" to global clear signal" 0 0 "Quartus II" 0 -1 1712871323828 ""}  } {  } 0 280013 "Promoted pin-driven signal(s) to global signal" 0 0 "Quartus II" 0 -1 1712871323828 ""}
{ "Warning" "WCUT_CUT_UNNECESSARY_INPUT_PIN_HDR" "1 " "Design contains 1 input pin(s) that do not drive logic" { { "Warning" "WCUT_CUT_UNNECESSARY_INPUT_PIN" "tx_sel " "No output dependent on input pin \"tx_sel\"" {  } { { "e2.v" "" { Text "//wsl.localhost/Debian/home/vrs/Verilog/projects/pt08/e2.v" 40 -1 0 } }  } 0 15610 "No output dependent on input pin \"%1!s!\"" 0 0 "Quartus II" 0 -1 1712871323864 "|e2|tx_sel"}  } {  } 0 21074 "Design contains %1!d! input pin(s) that do not drive logic" 0 0 "Quartus II" 0 -1 1712871323864 ""}
{ "Info" "ICUT_CUT_TM_SUMMARY" "53 " "Implemented 53 device resources after synthesis - the final resource count might be different" { { "Info" "ICUT_CUT_TM_IPINS" "8 " "Implemented 8 input pins" {  } {  } 0 21058 "Implemented %1!d! input pins" 0 0 "Quartus II" 0 -1 1712871323864 ""} { "Info" "ICUT_CUT_TM_OPINS" "13 " "Implemented 13 output pins" {  } {  } 0 21059 "Implemented %1!d! output pins" 0 0 "Quartus II" 0 -1 1712871323864 ""} { "Info" "ICUT_CUT_TM_MCELLS" "29 " "Implemented 29 macrocells" {  } {  } 0 21063 "Implemented %1!d! macrocells" 0 0 "Quartus II" 0 -1 1712871323864 ""} { "Info" "ICUT_CUT_TM_SEXPS" "3 " "Implemented 3 shareable expanders" {  } {  } 0 21073 "Implemented %1!d! shareable expanders" 0 0 "Quartus II" 0 -1 1712871323864 ""}  } {  } 0 21057 "Implemented %1!d! device resources after synthesis - the final resource count might be different" 0 0 "Quartus II" 0 -1 1712871323864 ""}
{ "Info" "IQEXE_ERROR_COUNT" "Analysis & Synthesis 0 s 5 s Quartus II 64-Bit " "Quartus II 64-Bit Analysis & Synthesis was successful. 0 errors, 5 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "4570 " "Peak virtual memory: 4570 megabytes" {  } {  } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Quartus II" 0 -1 1712871324016 ""} { "Info" "IQEXE_END_BANNER_TIME" "Thu Apr 11 14:35:24 2024 " "Processing ended: Thu Apr 11 14:35:24 2024" {  } {  } 0 0 "Processing ended: %1!s!" 0 0 "Quartus II" 0 -1 1712871324016 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:02 " "Elapsed time: 00:00:02" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0 "Quartus II" 0 -1 1712871324016 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:00 " "Total CPU time (on all processors): 00:00:00" {  } {  } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Quartus II" 0 -1 1712871324016 ""}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Quartus II" 0 -1 1712871324016 ""}