{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" {  } {  } 3 0 "*******************************************************************" 0 0 "Quartus II" 0 -1 1712556823259 ""}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Analysis & Synthesis Quartus II 64-Bit " "Running Quartus II 64-Bit Analysis & Synthesis" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition " "Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition" {  } {  } 0 0 "%1!s!" 0 0 "Quartus II" 0 -1 1712556823259 ""} { "Info" "IQEXE_START_BANNER_TIME" "Sun Apr 07 23:13:43 2024 " "Processing started: Sun Apr 07 23:13:43 2024" {  } {  } 0 0 "Processing started: %1!s!" 0 0 "Quartus II" 0 -1 1712556823259 ""}  } {  } 4 0 "Running %2!s! %1!s!" 0 0 "Quartus II" 0 -1 1712556823259 ""}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --read_settings_files=on --write_settings_files=off m707 -c m707 " "Command: quartus_map --read_settings_files=on --write_settings_files=off m707 -c m707" {  } {  } 0 0 "Command: %1!s!" 0 0 "Quartus II" 0 -1 1712556823259 ""}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "m707.v 1 1 " "Found 1 design units, including 1 entities, in source file m707.v" { { "Info" "ISGN_ENTITY_NAME" "1 m707 " "Found entity 1: m707" {  } { { "m707.v" "" { Text "//wsl.localhost/Debian/home/vrs/Verilog/projects/m706kyle/m707.v" 2 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1712556823777 ""}  } {  } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1712556823777 ""}
{ "Error" "EVRFX_VERI_SYNTAX_ERROR" "\"tx_rateo\";  expecting \";\" e11.v(92) " "Verilog HDL syntax error at e11.v(92) near text \"tx_rateo\";  expecting \";\"" {  } { { "e11.v" "" { Text "//wsl.localhost/Debian/home/vrs/Verilog/projects/m706kyle/e11.v" 92 0 0 } }  } 0 10170 "Verilog HDL syntax error at %2!s! near text %1!s!" 0 0 "Quartus II" 0 -1 1712556823822 ""}
{ "Error" "EVRFX_VERI_DESIGN_UNIT_IGNORED" "e11 e11.v(34) " "Ignored design unit \"e11\" at e11.v(34) due to previous errors" {  } { { "e11.v" "" { Text "//wsl.localhost/Debian/home/vrs/Verilog/projects/m706kyle/e11.v" 34 0 0 } }  } 0 10112 "Ignored design unit \"%1!s!\" at %2!s! due to previous errors" 0 0 "Quartus II" 0 -1 1712556823824 ""}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "e11.v 0 0 " "Found 0 design units, including 0 entities, in source file e11.v" {  } {  } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1712556823824 ""}
{ "Error" "EQEXE_ERROR_COUNT" "Analysis & Synthesis 2 s 0 s Quartus II 64-Bit " "Quartus II 64-Bit Analysis & Synthesis was unsuccessful. 2 errors, 0 warnings" { { "Error" "EQEXE_END_PEAK_VSIZE_MEMORY" "4569 " "Peak virtual memory: 4569 megabytes" {  } {  } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Quartus II" 0 -1 1712556823902 ""} { "Error" "EQEXE_END_BANNER_TIME" "Sun Apr 07 23:13:43 2024 " "Processing ended: Sun Apr 07 23:13:43 2024" {  } {  } 0 0 "Processing ended: %1!s!" 0 0 "Quartus II" 0 -1 1712556823902 ""} { "Error" "EQEXE_ELAPSED_TIME" "00:00:00 " "Elapsed time: 00:00:00" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0 "Quartus II" 0 -1 1712556823902 ""} { "Error" "EQEXE_ELAPSED_CPU_TIME" "00:00:00 " "Total CPU time (on all processors): 00:00:00" {  } {  } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Quartus II" 0 -1 1712556823902 ""}  } {  } 0 0 "%6!s! %1!s! was unsuccessful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Quartus II" 0 -1 1712556823902 ""}
{ "Error" "EFLOW_ERROR_COUNT" "Full Compilation 4 s 0 s " "Quartus II Full Compilation was unsuccessful. 4 errors, 0 warnings" {  } {  } 0 293001 "Quartus II %1!s! was unsuccessful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Quartus II" 0 -1 1712556824578 ""}