# -------------------------------------------------------------------------- #
#
# Copyright (C) 1991-2013 Altera Corporation
# Your use of Altera Corporation's design tools, logic functions 
# and other software and tools, and its AMPP partner logic 
# functions, and any output files from any of the foregoing 
# (including device programming or simulation files), and any 
# associated documentation or information are expressly subject 
# to the terms and conditions of the Altera Program License 
# Subscription Agreement, Altera MegaCore Function License 
# Agreement, or other applicable license agreement, including, 
# without limitation, that your use is for the sole purpose of 
# programming logic devices manufactured by Altera and sold by 
# Altera or its authorized distributors.  Please refer to the 
# applicable agreement for further details.
#
# -------------------------------------------------------------------------- #
#
# Quartus II 64-Bit
# Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition
# Date created = 14:41:21  April 02, 2024
#
# -------------------------------------------------------------------------- #
#
# Notes:
#
# 1) The default values for assignments are stored in the file:
#		m707_assignment_defaults.qdf
#    If this file doesn't exist, see file:
#		assignment_defaults.qdf
#
# 2) Altera recommends that you do not modify this file. This
#    file is updated automatically by the Quartus II software
#    and any changes you make may be lost or overwritten.
#
# -------------------------------------------------------------------------- #


set_global_assignment -name FAMILY MAX7000S
set_global_assignment -name DEVICE "EPM7032SLC44-10"
set_global_assignment -name TOP_LEVEL_ENTITY e11
set_global_assignment -name ORIGINAL_QUARTUS_VERSION "13.0 SP1"
set_global_assignment -name PROJECT_CREATION_TIME_DATE "14:41:21  APRIL 02, 2024"
set_global_assignment -name LAST_QUARTUS_VERSION "13.0 SP1"
set_global_assignment -name PROJECT_OUTPUT_DIRECTORY output_files
set_global_assignment -name VERILOG_FILE //wsl.localhost/Debian/home/vrs/Verilog/projects/m706kyle/m707.v
set_global_assignment -name VERILOG_FILE //wsl.localhost/Debian/home/vrs/Verilog/projects/m706kyle/e11.v
set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top
set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -section_id Top
set_global_assignment -name PARTITION_COLOR 16764057 -section_id Top
set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top
set_global_assignment -name DEVICE_FILTER_PIN_COUNT 44
set_global_assignment -name DEVICE_FILTER_PACKAGE PLCC
set_global_assignment -name MAX7000_DEVICE_IO_STANDARD TTL
set_location_assignment PIN_24 -to bac0
set_location_assignment PIN_20 -to bac1
set_location_assignment PIN_19 -to bac2
set_location_assignment PIN_17 -to bac3
set_location_assignment PIN_16 -to bac4
set_location_assignment PIN_11 -to bac5
set_location_assignment PIN_12 -to bac6
set_location_assignment PIN_8 -to bac7
set_location_assignment PIN_5 -to bac8
set_location_assignment PIN_25 -to bac9
set_location_assignment PIN_21 -to bac10
set_location_assignment PIN_18 -to bac11
set_location_assignment PIN_14 -to biop1
set_location_assignment PIN_9 -to biop2
set_location_assignment PIN_6 -to biop4
set_location_assignment PIN_33 -to init_l
set_location_assignment PIN_1 -to initialize
set_location_assignment PIN_29 -to irq_l
set_location_assignment PIN_2 -to rx_rate
set_location_assignment PIN_26 -to rx_sel
set_location_assignment PIN_28 -to skip_l
set_location_assignment PIN_37 -to stop1
set_location_assignment PIN_39 -to stop2
set_location_assignment PIN_44 -to stp_mark
set_location_assignment PIN_43 -to tx_ratei
set_location_assignment PIN_41 -to tx_rateo
set_location_assignment PIN_31 -to tx_sel
set_location_assignment PIN_36 -to txdttl