TimeQuest Timing Analyzer report for m706 Wed Apr 10 18:59:23 2024 Quartus II 64-Bit Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition --------------------- ; Table of Contents ; --------------------- 1. Legal Notice 2. TimeQuest Timing Analyzer Summary 3. Parallel Compilation 4. Clocks 5. Fmax Summary 6. Setup Summary 7. Hold Summary 8. Recovery Summary 9. Removal Summary 10. Minimum Pulse Width Summary 11. Setup: 'm706:m706|clock_scale[2]' 12. Setup: 'm706:m706|in_active' 13. Setup: 'rx_rate' 14. Hold: 'm706:m706|clock_scale[2]' 15. Hold: 'm706:m706|in_active' 16. Hold: 'rx_rate' 17. Recovery: 'm706:m706|in_last_unit' 18. Recovery: 'm706:m706|clock_scale[2]' 19. Recovery: 'm706:m706|in_active' 20. Recovery: 'rx_rate' 21. Recovery: 'rx_data' 22. Removal: 'm706:m706|clock_scale[2]' 23. Removal: 'm706:m706|in_active' 24. Removal: 'm706:m706|in_last_unit' 25. Removal: 'rx_rate' 26. Removal: 'rx_data' 27. Minimum Pulse Width: 'm706:m706|clock_scale[2]' 28. Minimum Pulse Width: 'm706:m706|in_active' 29. Minimum Pulse Width: 'rx_rate' 30. Minimum Pulse Width: 'm706:m706|in_last_unit' 31. Minimum Pulse Width: 'rx_data' 32. Setup Times 33. Hold Times 34. Clock to Output Times 35. Minimum Clock to Output Times 36. Propagation Delay 37. Minimum Propagation Delay 38. Setup Transfers 39. Hold Transfers 40. Recovery Transfers 41. Removal Transfers 42. Report TCCS 43. Report RSKM 44. Unconstrained Paths 45. TimeQuest Timing Analyzer Messages ---------------- ; Legal Notice ; ---------------- Copyright (C) 1991-2013 Altera Corporation Your use of Altera Corporation's design tools, logic functions and other software and tools, and its AMPP partner logic functions, and any output files from any of the foregoing (including device programming or simulation files), and any associated documentation or information are expressly subject to the terms and conditions of the Altera Program License Subscription Agreement, Altera MegaCore Function License Agreement, or other applicable license agreement, including, without limitation, that your use is for the sole purpose of programming logic devices manufactured by Altera and sold by Altera or its authorized distributors. Please refer to the applicable agreement for further details. +----------------------------------------------------------------------------------------+ ; TimeQuest Timing Analyzer Summary ; +--------------------+-------------------------------------------------------------------+ ; Quartus II Version ; Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition ; ; Revision Name ; m706 ; ; Device Family ; MAX7000S ; ; Device Name ; EPM7064SLC44-10 ; ; Timing Models ; Final ; ; Delay Model ; Slow Model ; ; Rise/Fall Delays ; Unavailable ; +--------------------+-------------------------------------------------------------------+ Parallel compilation was disabled, but you have multiple processors available. Enable parallel compilation to reduce compilation time. +-------------------------------------+ ; Parallel Compilation ; +----------------------------+--------+ ; Processors ; Number ; +----------------------------+--------+ ; Number detected on machine ; 8 ; ; Maximum allowed ; 1 ; +----------------------------+--------+ +--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ ; Clocks ; +--------------------------+------+--------+------------+-------+-------+------------+-----------+-------------+-------+--------+-----------+------------+----------+--------+--------+------------------------------+ ; Clock Name ; Type ; Period ; Frequency ; Rise ; Fall ; Duty Cycle ; Divide by ; Multiply by ; Phase ; Offset ; Edge List ; Edge Shift ; Inverted ; Master ; Source ; Targets ; +--------------------------+------+--------+------------+-------+-------+------------+-----------+-------------+-------+--------+-----------+------------+----------+--------+--------+------------------------------+ ; m706:m706|clock_scale[2] ; Base ; 1.000 ; 1000.0 MHz ; 0.000 ; 0.500 ; ; ; ; ; ; ; ; ; ; ; { m706:m706|clock_scale[2] } ; ; m706:m706|in_active ; Base ; 1.000 ; 1000.0 MHz ; 0.000 ; 0.500 ; ; ; ; ; ; ; ; ; ; ; { m706:m706|in_active } ; ; m706:m706|in_last_unit ; Base ; 1.000 ; 1000.0 MHz ; 0.000 ; 0.500 ; ; ; ; ; ; ; ; ; ; ; { m706:m706|in_last_unit } ; ; rx_data ; Base ; 1.000 ; 1000.0 MHz ; 0.000 ; 0.500 ; ; ; ; ; ; ; ; ; ; ; { rx_data } ; ; rx_rate ; Base ; 1.000 ; 1000.0 MHz ; 0.000 ; 0.500 ; ; ; ; ; ; ; ; ; ; ; { rx_rate } ; +--------------------------+------+--------+------------+-------+-------+------------+-----------+-------------+-------+--------+-----------+------------+----------+--------+--------+------------------------------+ +---------------------------------------------------------------+ ; Fmax Summary ; +-----------+-----------------+--------------------------+------+ ; Fmax ; Restricted Fmax ; Clock Name ; Note ; +-----------+-----------------+--------------------------+------+ ; 100.0 MHz ; 100.0 MHz ; m706:m706|clock_scale[2] ; ; ; 100.0 MHz ; 100.0 MHz ; m706:m706|in_active ; ; ; 100.0 MHz ; 100.0 MHz ; rx_rate ; ; +-----------+-----------------+--------------------------+------+ This panel reports FMAX for every clock in the design, regardless of the user-specified clock periods. FMAX is only computed for paths where the source and destination registers or ports are driven by the same clock. Paths of different clocks, including generated clocks, are ignored. For paths between a clock and its inversion, FMAX is computed as if the rising and falling edges are scaled along with FMAX, such that the duty cycle (in terms of a percentage) is maintained. Altera recommends that you always use clock constraints and other slack reports for sign-off analysis. +---------------------------------------------------+ ; Setup Summary ; +--------------------------+--------+---------------+ ; Clock ; Slack ; End Point TNS ; +--------------------------+--------+---------------+ ; m706:m706|clock_scale[2] ; -9.000 ; -93.500 ; ; m706:m706|in_active ; -9.000 ; -83.000 ; ; rx_rate ; -9.000 ; -27.000 ; +--------------------------+--------+---------------+ +---------------------------------------------------+ ; Hold Summary ; +--------------------------+--------+---------------+ ; Clock ; Slack ; End Point TNS ; +--------------------------+--------+---------------+ ; m706:m706|clock_scale[2] ; -3.000 ; -8.500 ; ; m706:m706|in_active ; -3.000 ; -5.500 ; ; rx_rate ; 1.500 ; 0.000 ; +--------------------------+--------+---------------+ +----------------------------------------------------+ ; Recovery Summary ; +--------------------------+---------+---------------+ ; Clock ; Slack ; End Point TNS ; +--------------------------+---------+---------------+ ; m706:m706|in_last_unit ; -27.500 ; -39.500 ; ; m706:m706|clock_scale[2] ; -22.500 ; -84.500 ; ; m706:m706|in_active ; -12.000 ; -64.000 ; ; rx_rate ; -11.500 ; -38.500 ; ; rx_data ; -11.500 ; -11.500 ; +--------------------------+---------+---------------+ +---------------------------------------------------+ ; Removal Summary ; +--------------------------+--------+---------------+ ; Clock ; Slack ; End Point TNS ; +--------------------------+--------+---------------+ ; m706:m706|clock_scale[2] ; -8.000 ; -13.000 ; ; m706:m706|in_active ; -8.000 ; -8.000 ; ; m706:m706|in_last_unit ; 0.000 ; 0.000 ; ; rx_rate ; 4.500 ; 0.000 ; ; rx_data ; 7.500 ; 0.000 ; +--------------------------+--------+---------------+ +---------------------------------------------------+ ; Minimum Pulse Width Summary ; +--------------------------+--------+---------------+ ; Clock ; Slack ; End Point TNS ; +--------------------------+--------+---------------+ ; m706:m706|clock_scale[2] ; -3.500 ; -98.000 ; ; m706:m706|in_active ; -3.500 ; -84.000 ; ; rx_rate ; -3.500 ; -28.000 ; ; m706:m706|in_last_unit ; -3.500 ; -14.000 ; ; rx_data ; -3.500 ; -7.000 ; +--------------------------+--------+---------------+ +-----------------------------------------------------------------------------------------------------------------------------------------------------------+ ; Setup: 'm706:m706|clock_scale[2]' ; +--------+-------------------------+-------------------------+--------------------------+--------------------------+--------------+------------+------------+ ; Slack ; From Node ; To Node ; Launch Clock ; Latch Clock ; Relationship ; Clock Skew ; Data Delay ; +--------+-------------------------+-------------------------+--------------------------+--------------------------+--------------+------------+------------+ ; -9.000 ; m706:m706|tti37[7] ; m706:m706|keyboard_flag ; m706:m706|clock_scale[2] ; m706:m706|clock_scale[2] ; 1.000 ; 0.000 ; 8.000 ; ; -9.000 ; m706:m706|keyboard_flag ; m706:m706|keyboard_flag ; m706:m706|clock_scale[2] ; m706:m706|clock_scale[2] ; 1.000 ; 0.000 ; 8.000 ; ; -9.000 ; m706:m706|tti37[7] ; m706:m706|in_last_unit ; m706:m706|clock_scale[2] ; m706:m706|clock_scale[2] ; 1.000 ; 0.000 ; 8.000 ; ; -9.000 ; m706:m706|in_stop[1] ; m706:m706|in_stop[2] ; m706:m706|clock_scale[2] ; m706:m706|clock_scale[2] ; 1.000 ; 0.000 ; 8.000 ; ; -9.000 ; m706:m706|tti37[6] ; m706:m706|tti37[7] ; m706:m706|clock_scale[2] ; m706:m706|clock_scale[2] ; 1.000 ; 0.000 ; 8.000 ; ; -9.000 ; m706:m706|tti37[5] ; m706:m706|tti37[6] ; m706:m706|clock_scale[2] ; m706:m706|clock_scale[2] ; 1.000 ; 0.000 ; 8.000 ; ; -9.000 ; m706:m706|tti37[4] ; m706:m706|tti37[5] ; m706:m706|clock_scale[2] ; m706:m706|clock_scale[2] ; 1.000 ; 0.000 ; 8.000 ; ; -9.000 ; m706:m706|tti37[3] ; m706:m706|tti37[4] ; m706:m706|clock_scale[2] ; m706:m706|clock_scale[2] ; 1.000 ; 0.000 ; 8.000 ; ; -9.000 ; m706:m706|tti02[2] ; m706:m706|tti37[3] ; m706:m706|clock_scale[2] ; m706:m706|clock_scale[2] ; 1.000 ; 0.000 ; 8.000 ; ; -9.000 ; m706:m706|tti02[1] ; m706:m706|tti02[2] ; m706:m706|clock_scale[2] ; m706:m706|clock_scale[2] ; 1.000 ; 0.000 ; 8.000 ; ; -9.000 ; m706:m706|tti02[0] ; m706:m706|tti02[1] ; m706:m706|clock_scale[2] ; m706:m706|clock_scale[2] ; 1.000 ; 0.000 ; 8.000 ; ; -9.000 ; m706:m706|tti37[7] ; m706:m706|keyboard_flag ; m706:m706|in_active ; m706:m706|clock_scale[2] ; 1.000 ; 0.000 ; 8.000 ; ; -9.000 ; m706:m706|keyboard_flag ; m706:m706|keyboard_flag ; m706:m706|in_active ; m706:m706|clock_scale[2] ; 1.000 ; 0.000 ; 8.000 ; ; -9.000 ; m706:m706|tti37[7] ; m706:m706|in_last_unit ; m706:m706|in_active ; m706:m706|clock_scale[2] ; 1.000 ; 0.000 ; 8.000 ; ; -9.000 ; m706:m706|tti37[6] ; m706:m706|tti37[7] ; m706:m706|in_active ; m706:m706|clock_scale[2] ; 1.000 ; 0.000 ; 8.000 ; ; -9.000 ; m706:m706|tti37[5] ; m706:m706|tti37[6] ; m706:m706|in_active ; m706:m706|clock_scale[2] ; 1.000 ; 0.000 ; 8.000 ; ; -9.000 ; m706:m706|tti37[4] ; m706:m706|tti37[5] ; m706:m706|in_active ; m706:m706|clock_scale[2] ; 1.000 ; 0.000 ; 8.000 ; ; -9.000 ; m706:m706|tti37[3] ; m706:m706|tti37[4] ; m706:m706|in_active ; m706:m706|clock_scale[2] ; 1.000 ; 0.000 ; 8.000 ; ; -9.000 ; m706:m706|tti02[2] ; m706:m706|tti37[3] ; m706:m706|in_active ; m706:m706|clock_scale[2] ; 1.000 ; 0.000 ; 8.000 ; ; -9.000 ; m706:m706|tti02[1] ; m706:m706|tti02[2] ; m706:m706|in_active ; m706:m706|clock_scale[2] ; 1.000 ; 0.000 ; 8.000 ; ; -9.000 ; m706:m706|tti02[0] ; m706:m706|tti02[1] ; m706:m706|in_active ; m706:m706|clock_scale[2] ; 1.000 ; 0.000 ; 8.000 ; ; -2.000 ; rx_rate ; m706:m706|keyboard_flag ; rx_rate ; m706:m706|clock_scale[2] ; 0.500 ; 6.000 ; 6.500 ; ; -2.000 ; rx_data ; m706:m706|keyboard_flag ; rx_data ; m706:m706|clock_scale[2] ; 0.500 ; 6.000 ; 6.500 ; ; -2.000 ; rx_data ; m706:m706|tti02[0] ; rx_data ; m706:m706|clock_scale[2] ; 0.500 ; 6.000 ; 6.500 ; ; -1.500 ; m706:m706|in_last_unit ; m706:m706|keyboard_flag ; m706:m706|in_last_unit ; m706:m706|clock_scale[2] ; 0.500 ; 6.000 ; 8.000 ; ; -1.500 ; rx_rate ; m706:m706|keyboard_flag ; rx_rate ; m706:m706|clock_scale[2] ; 1.000 ; 6.000 ; 6.500 ; ; -1.500 ; m706:m706|in_active ; m706:m706|keyboard_flag ; m706:m706|in_active ; m706:m706|clock_scale[2] ; 0.500 ; 6.000 ; 8.000 ; ; -1.500 ; m706:m706|in_active ; m706:m706|in_stop[1] ; m706:m706|in_active ; m706:m706|clock_scale[2] ; 0.500 ; 6.000 ; 8.000 ; ; -1.500 ; rx_data ; m706:m706|keyboard_flag ; rx_data ; m706:m706|clock_scale[2] ; 1.000 ; 6.000 ; 6.500 ; ; -1.500 ; rx_data ; m706:m706|tti02[0] ; rx_data ; m706:m706|clock_scale[2] ; 1.000 ; 6.000 ; 6.500 ; ; -1.000 ; m706:m706|in_last_unit ; m706:m706|keyboard_flag ; m706:m706|in_last_unit ; m706:m706|clock_scale[2] ; 1.000 ; 6.000 ; 8.000 ; ; -1.000 ; m706:m706|in_active ; m706:m706|keyboard_flag ; m706:m706|in_active ; m706:m706|clock_scale[2] ; 1.000 ; 6.000 ; 8.000 ; ; -1.000 ; m706:m706|in_active ; m706:m706|in_stop[1] ; m706:m706|in_active ; m706:m706|clock_scale[2] ; 1.000 ; 6.000 ; 8.000 ; +--------+-------------------------+-------------------------+--------------------------+--------------------------+--------------+------------+------------+ +------------------------------------------------------------------------------------------------------------------------------------------------------+ ; Setup: 'm706:m706|in_active' ; +--------+-------------------------+-------------------------+--------------------------+---------------------+--------------+------------+------------+ ; Slack ; From Node ; To Node ; Launch Clock ; Latch Clock ; Relationship ; Clock Skew ; Data Delay ; +--------+-------------------------+-------------------------+--------------------------+---------------------+--------------+------------+------------+ ; -9.000 ; m706:m706|tti37[7] ; m706:m706|keyboard_flag ; m706:m706|clock_scale[2] ; m706:m706|in_active ; 1.000 ; 0.000 ; 8.000 ; ; -9.000 ; m706:m706|keyboard_flag ; m706:m706|keyboard_flag ; m706:m706|clock_scale[2] ; m706:m706|in_active ; 1.000 ; 0.000 ; 8.000 ; ; -9.000 ; m706:m706|tti37[7] ; m706:m706|in_last_unit ; m706:m706|clock_scale[2] ; m706:m706|in_active ; 1.000 ; 0.000 ; 8.000 ; ; -9.000 ; m706:m706|tti37[6] ; m706:m706|tti37[7] ; m706:m706|clock_scale[2] ; m706:m706|in_active ; 1.000 ; 0.000 ; 8.000 ; ; -9.000 ; m706:m706|tti37[5] ; m706:m706|tti37[6] ; m706:m706|clock_scale[2] ; m706:m706|in_active ; 1.000 ; 0.000 ; 8.000 ; ; -9.000 ; m706:m706|tti37[4] ; m706:m706|tti37[5] ; m706:m706|clock_scale[2] ; m706:m706|in_active ; 1.000 ; 0.000 ; 8.000 ; ; -9.000 ; m706:m706|tti37[3] ; m706:m706|tti37[4] ; m706:m706|clock_scale[2] ; m706:m706|in_active ; 1.000 ; 0.000 ; 8.000 ; ; -9.000 ; m706:m706|tti02[2] ; m706:m706|tti37[3] ; m706:m706|clock_scale[2] ; m706:m706|in_active ; 1.000 ; 0.000 ; 8.000 ; ; -9.000 ; m706:m706|tti02[1] ; m706:m706|tti02[2] ; m706:m706|clock_scale[2] ; m706:m706|in_active ; 1.000 ; 0.000 ; 8.000 ; ; -9.000 ; m706:m706|tti02[0] ; m706:m706|tti02[1] ; m706:m706|clock_scale[2] ; m706:m706|in_active ; 1.000 ; 0.000 ; 8.000 ; ; -9.000 ; m706:m706|tti37[7] ; m706:m706|keyboard_flag ; m706:m706|in_active ; m706:m706|in_active ; 1.000 ; 0.000 ; 8.000 ; ; -9.000 ; m706:m706|keyboard_flag ; m706:m706|keyboard_flag ; m706:m706|in_active ; m706:m706|in_active ; 1.000 ; 0.000 ; 8.000 ; ; -9.000 ; m706:m706|tti37[7] ; m706:m706|in_last_unit ; m706:m706|in_active ; m706:m706|in_active ; 1.000 ; 0.000 ; 8.000 ; ; -9.000 ; m706:m706|tti37[6] ; m706:m706|tti37[7] ; m706:m706|in_active ; m706:m706|in_active ; 1.000 ; 0.000 ; 8.000 ; ; -9.000 ; m706:m706|tti37[5] ; m706:m706|tti37[6] ; m706:m706|in_active ; m706:m706|in_active ; 1.000 ; 0.000 ; 8.000 ; ; -9.000 ; m706:m706|tti37[4] ; m706:m706|tti37[5] ; m706:m706|in_active ; m706:m706|in_active ; 1.000 ; 0.000 ; 8.000 ; ; -9.000 ; m706:m706|tti37[3] ; m706:m706|tti37[4] ; m706:m706|in_active ; m706:m706|in_active ; 1.000 ; 0.000 ; 8.000 ; ; -9.000 ; m706:m706|tti02[2] ; m706:m706|tti37[3] ; m706:m706|in_active ; m706:m706|in_active ; 1.000 ; 0.000 ; 8.000 ; ; -9.000 ; m706:m706|tti02[1] ; m706:m706|tti02[2] ; m706:m706|in_active ; m706:m706|in_active ; 1.000 ; 0.000 ; 8.000 ; ; -9.000 ; m706:m706|tti02[0] ; m706:m706|tti02[1] ; m706:m706|in_active ; m706:m706|in_active ; 1.000 ; 0.000 ; 8.000 ; ; -2.000 ; rx_rate ; m706:m706|keyboard_flag ; rx_rate ; m706:m706|in_active ; 0.500 ; 6.000 ; 6.500 ; ; -2.000 ; rx_data ; m706:m706|keyboard_flag ; rx_data ; m706:m706|in_active ; 0.500 ; 6.000 ; 6.500 ; ; -2.000 ; rx_data ; m706:m706|tti02[0] ; rx_data ; m706:m706|in_active ; 0.500 ; 6.000 ; 6.500 ; ; -1.500 ; m706:m706|in_last_unit ; m706:m706|keyboard_flag ; m706:m706|in_last_unit ; m706:m706|in_active ; 0.500 ; 6.000 ; 8.000 ; ; -1.500 ; rx_rate ; m706:m706|keyboard_flag ; rx_rate ; m706:m706|in_active ; 1.000 ; 6.000 ; 6.500 ; ; -1.500 ; m706:m706|in_active ; m706:m706|keyboard_flag ; m706:m706|in_active ; m706:m706|in_active ; 0.500 ; 6.000 ; 8.000 ; ; -1.500 ; rx_data ; m706:m706|keyboard_flag ; rx_data ; m706:m706|in_active ; 1.000 ; 6.000 ; 6.500 ; ; -1.500 ; rx_data ; m706:m706|tti02[0] ; rx_data ; m706:m706|in_active ; 1.000 ; 6.000 ; 6.500 ; ; -1.000 ; m706:m706|in_last_unit ; m706:m706|keyboard_flag ; m706:m706|in_last_unit ; m706:m706|in_active ; 1.000 ; 6.000 ; 8.000 ; ; -1.000 ; m706:m706|in_active ; m706:m706|keyboard_flag ; m706:m706|in_active ; m706:m706|in_active ; 1.000 ; 6.000 ; 8.000 ; +--------+-------------------------+-------------------------+--------------------------+---------------------+--------------+------------+------------+ +------------------------------------------------------------------------------------------------------------------------------------------------+ ; Setup: 'rx_rate' ; +--------+--------------------------+--------------------------+--------------------------+-------------+--------------+------------+------------+ ; Slack ; From Node ; To Node ; Launch Clock ; Latch Clock ; Relationship ; Clock Skew ; Data Delay ; +--------+--------------------------+--------------------------+--------------------------+-------------+--------------+------------+------------+ ; -9.000 ; m706:m706|clock_scale[0] ; m706:m706|clock_scale[0] ; rx_rate ; rx_rate ; 1.000 ; 0.000 ; 8.000 ; ; -9.000 ; m706:m706|clock_scale[1] ; m706:m706|clock_scale[1] ; rx_rate ; rx_rate ; 1.000 ; 0.000 ; 8.000 ; ; -9.000 ; m706:m706|clock_scale[0] ; m706:m706|clock_scale[1] ; rx_rate ; rx_rate ; 1.000 ; 0.000 ; 8.000 ; ; -9.000 ; m706:m706|clock_scale[1] ; m706:m706|clock_scale[2] ; rx_rate ; rx_rate ; 1.000 ; 0.000 ; 8.000 ; ; -9.000 ; m706:m706|clock_scale[0] ; m706:m706|clock_scale[2] ; rx_rate ; rx_rate ; 1.000 ; 0.000 ; 8.000 ; ; -6.000 ; m706:m706|clock_scale[2] ; m706:m706|clock_scale[2] ; m706:m706|clock_scale[2] ; rx_rate ; 0.500 ; 1.500 ; 8.000 ; ; -5.500 ; m706:m706|clock_scale[2] ; m706:m706|clock_scale[2] ; m706:m706|clock_scale[2] ; rx_rate ; 1.000 ; 1.500 ; 8.000 ; +--------+--------------------------+--------------------------+--------------------------+-------------+--------------+------------+------------+ +-----------------------------------------------------------------------------------------------------------------------------------------------------------+ ; Hold: 'm706:m706|clock_scale[2]' ; +--------+-------------------------+-------------------------+--------------------------+--------------------------+--------------+------------+------------+ ; Slack ; From Node ; To Node ; Launch Clock ; Latch Clock ; Relationship ; Clock Skew ; Data Delay ; +--------+-------------------------+-------------------------+--------------------------+--------------------------+--------------+------------+------------+ ; -3.000 ; m706:m706|in_last_unit ; m706:m706|keyboard_flag ; m706:m706|in_last_unit ; m706:m706|clock_scale[2] ; 0.000 ; 6.000 ; 8.000 ; ; -3.000 ; m706:m706|in_active ; m706:m706|keyboard_flag ; m706:m706|in_active ; m706:m706|clock_scale[2] ; 0.000 ; 6.000 ; 8.000 ; ; -3.000 ; m706:m706|in_active ; m706:m706|in_stop[1] ; m706:m706|in_active ; m706:m706|clock_scale[2] ; 0.000 ; 6.000 ; 8.000 ; ; -2.500 ; m706:m706|in_last_unit ; m706:m706|keyboard_flag ; m706:m706|in_last_unit ; m706:m706|clock_scale[2] ; -0.500 ; 6.000 ; 8.000 ; ; -2.500 ; rx_rate ; m706:m706|keyboard_flag ; rx_rate ; m706:m706|clock_scale[2] ; 0.000 ; 6.000 ; 6.500 ; ; -2.500 ; m706:m706|in_active ; m706:m706|keyboard_flag ; m706:m706|in_active ; m706:m706|clock_scale[2] ; -0.500 ; 6.000 ; 8.000 ; ; -2.500 ; m706:m706|in_active ; m706:m706|in_stop[1] ; m706:m706|in_active ; m706:m706|clock_scale[2] ; -0.500 ; 6.000 ; 8.000 ; ; -2.500 ; rx_data ; m706:m706|keyboard_flag ; rx_data ; m706:m706|clock_scale[2] ; 0.000 ; 6.000 ; 6.500 ; ; -2.500 ; rx_data ; m706:m706|tti02[0] ; rx_data ; m706:m706|clock_scale[2] ; 0.000 ; 6.000 ; 6.500 ; ; -2.000 ; rx_rate ; m706:m706|keyboard_flag ; rx_rate ; m706:m706|clock_scale[2] ; -0.500 ; 6.000 ; 6.500 ; ; -2.000 ; rx_data ; m706:m706|keyboard_flag ; rx_data ; m706:m706|clock_scale[2] ; -0.500 ; 6.000 ; 6.500 ; ; -2.000 ; rx_data ; m706:m706|tti02[0] ; rx_data ; m706:m706|clock_scale[2] ; -0.500 ; 6.000 ; 6.500 ; ; 5.000 ; m706:m706|tti37[7] ; m706:m706|keyboard_flag ; m706:m706|clock_scale[2] ; m706:m706|clock_scale[2] ; 0.000 ; 0.000 ; 8.000 ; ; 5.000 ; m706:m706|keyboard_flag ; m706:m706|keyboard_flag ; m706:m706|clock_scale[2] ; m706:m706|clock_scale[2] ; 0.000 ; 0.000 ; 8.000 ; ; 5.000 ; m706:m706|tti37[7] ; m706:m706|in_last_unit ; m706:m706|clock_scale[2] ; m706:m706|clock_scale[2] ; 0.000 ; 0.000 ; 8.000 ; ; 5.000 ; m706:m706|in_stop[1] ; m706:m706|in_stop[2] ; m706:m706|clock_scale[2] ; m706:m706|clock_scale[2] ; 0.000 ; 0.000 ; 8.000 ; ; 5.000 ; m706:m706|tti37[6] ; m706:m706|tti37[7] ; m706:m706|clock_scale[2] ; m706:m706|clock_scale[2] ; 0.000 ; 0.000 ; 8.000 ; ; 5.000 ; m706:m706|tti37[5] ; m706:m706|tti37[6] ; m706:m706|clock_scale[2] ; m706:m706|clock_scale[2] ; 0.000 ; 0.000 ; 8.000 ; ; 5.000 ; m706:m706|tti37[4] ; m706:m706|tti37[5] ; m706:m706|clock_scale[2] ; m706:m706|clock_scale[2] ; 0.000 ; 0.000 ; 8.000 ; ; 5.000 ; m706:m706|tti37[3] ; m706:m706|tti37[4] ; m706:m706|clock_scale[2] ; m706:m706|clock_scale[2] ; 0.000 ; 0.000 ; 8.000 ; ; 5.000 ; m706:m706|tti02[2] ; m706:m706|tti37[3] ; m706:m706|clock_scale[2] ; m706:m706|clock_scale[2] ; 0.000 ; 0.000 ; 8.000 ; ; 5.000 ; m706:m706|tti02[1] ; m706:m706|tti02[2] ; m706:m706|clock_scale[2] ; m706:m706|clock_scale[2] ; 0.000 ; 0.000 ; 8.000 ; ; 5.000 ; m706:m706|tti02[0] ; m706:m706|tti02[1] ; m706:m706|clock_scale[2] ; m706:m706|clock_scale[2] ; 0.000 ; 0.000 ; 8.000 ; ; 5.000 ; m706:m706|tti37[7] ; m706:m706|keyboard_flag ; m706:m706|in_active ; m706:m706|clock_scale[2] ; 0.000 ; 0.000 ; 8.000 ; ; 5.000 ; m706:m706|keyboard_flag ; m706:m706|keyboard_flag ; m706:m706|in_active ; m706:m706|clock_scale[2] ; 0.000 ; 0.000 ; 8.000 ; ; 5.000 ; m706:m706|tti37[7] ; m706:m706|in_last_unit ; m706:m706|in_active ; m706:m706|clock_scale[2] ; 0.000 ; 0.000 ; 8.000 ; ; 5.000 ; m706:m706|tti37[6] ; m706:m706|tti37[7] ; m706:m706|in_active ; m706:m706|clock_scale[2] ; 0.000 ; 0.000 ; 8.000 ; ; 5.000 ; m706:m706|tti37[5] ; m706:m706|tti37[6] ; m706:m706|in_active ; m706:m706|clock_scale[2] ; 0.000 ; 0.000 ; 8.000 ; ; 5.000 ; m706:m706|tti37[4] ; m706:m706|tti37[5] ; m706:m706|in_active ; m706:m706|clock_scale[2] ; 0.000 ; 0.000 ; 8.000 ; ; 5.000 ; m706:m706|tti37[3] ; m706:m706|tti37[4] ; m706:m706|in_active ; m706:m706|clock_scale[2] ; 0.000 ; 0.000 ; 8.000 ; ; 5.000 ; m706:m706|tti02[2] ; m706:m706|tti37[3] ; m706:m706|in_active ; m706:m706|clock_scale[2] ; 0.000 ; 0.000 ; 8.000 ; ; 5.000 ; m706:m706|tti02[1] ; m706:m706|tti02[2] ; m706:m706|in_active ; m706:m706|clock_scale[2] ; 0.000 ; 0.000 ; 8.000 ; ; 5.000 ; m706:m706|tti02[0] ; m706:m706|tti02[1] ; m706:m706|in_active ; m706:m706|clock_scale[2] ; 0.000 ; 0.000 ; 8.000 ; +--------+-------------------------+-------------------------+--------------------------+--------------------------+--------------+------------+------------+ +------------------------------------------------------------------------------------------------------------------------------------------------------+ ; Hold: 'm706:m706|in_active' ; +--------+-------------------------+-------------------------+--------------------------+---------------------+--------------+------------+------------+ ; Slack ; From Node ; To Node ; Launch Clock ; Latch Clock ; Relationship ; Clock Skew ; Data Delay ; +--------+-------------------------+-------------------------+--------------------------+---------------------+--------------+------------+------------+ ; -3.000 ; m706:m706|in_last_unit ; m706:m706|keyboard_flag ; m706:m706|in_last_unit ; m706:m706|in_active ; 0.000 ; 6.000 ; 8.000 ; ; -3.000 ; m706:m706|in_active ; m706:m706|keyboard_flag ; m706:m706|in_active ; m706:m706|in_active ; 0.000 ; 6.000 ; 8.000 ; ; -2.500 ; m706:m706|in_last_unit ; m706:m706|keyboard_flag ; m706:m706|in_last_unit ; m706:m706|in_active ; -0.500 ; 6.000 ; 8.000 ; ; -2.500 ; rx_rate ; m706:m706|keyboard_flag ; rx_rate ; m706:m706|in_active ; 0.000 ; 6.000 ; 6.500 ; ; -2.500 ; m706:m706|in_active ; m706:m706|keyboard_flag ; m706:m706|in_active ; m706:m706|in_active ; -0.500 ; 6.000 ; 8.000 ; ; -2.500 ; rx_data ; m706:m706|keyboard_flag ; rx_data ; m706:m706|in_active ; 0.000 ; 6.000 ; 6.500 ; ; -2.500 ; rx_data ; m706:m706|tti02[0] ; rx_data ; m706:m706|in_active ; 0.000 ; 6.000 ; 6.500 ; ; -2.000 ; rx_rate ; m706:m706|keyboard_flag ; rx_rate ; m706:m706|in_active ; -0.500 ; 6.000 ; 6.500 ; ; -2.000 ; rx_data ; m706:m706|keyboard_flag ; rx_data ; m706:m706|in_active ; -0.500 ; 6.000 ; 6.500 ; ; -2.000 ; rx_data ; m706:m706|tti02[0] ; rx_data ; m706:m706|in_active ; -0.500 ; 6.000 ; 6.500 ; ; 5.000 ; m706:m706|tti37[7] ; m706:m706|keyboard_flag ; m706:m706|clock_scale[2] ; m706:m706|in_active ; 0.000 ; 0.000 ; 8.000 ; ; 5.000 ; m706:m706|keyboard_flag ; m706:m706|keyboard_flag ; m706:m706|clock_scale[2] ; m706:m706|in_active ; 0.000 ; 0.000 ; 8.000 ; ; 5.000 ; m706:m706|tti37[7] ; m706:m706|in_last_unit ; m706:m706|clock_scale[2] ; m706:m706|in_active ; 0.000 ; 0.000 ; 8.000 ; ; 5.000 ; m706:m706|tti37[6] ; m706:m706|tti37[7] ; m706:m706|clock_scale[2] ; m706:m706|in_active ; 0.000 ; 0.000 ; 8.000 ; ; 5.000 ; m706:m706|tti37[5] ; m706:m706|tti37[6] ; m706:m706|clock_scale[2] ; m706:m706|in_active ; 0.000 ; 0.000 ; 8.000 ; ; 5.000 ; m706:m706|tti37[4] ; m706:m706|tti37[5] ; m706:m706|clock_scale[2] ; m706:m706|in_active ; 0.000 ; 0.000 ; 8.000 ; ; 5.000 ; m706:m706|tti37[3] ; m706:m706|tti37[4] ; m706:m706|clock_scale[2] ; m706:m706|in_active ; 0.000 ; 0.000 ; 8.000 ; ; 5.000 ; m706:m706|tti02[2] ; m706:m706|tti37[3] ; m706:m706|clock_scale[2] ; m706:m706|in_active ; 0.000 ; 0.000 ; 8.000 ; ; 5.000 ; m706:m706|tti02[1] ; m706:m706|tti02[2] ; m706:m706|clock_scale[2] ; m706:m706|in_active ; 0.000 ; 0.000 ; 8.000 ; ; 5.000 ; m706:m706|tti02[0] ; m706:m706|tti02[1] ; m706:m706|clock_scale[2] ; m706:m706|in_active ; 0.000 ; 0.000 ; 8.000 ; ; 5.000 ; m706:m706|tti37[7] ; m706:m706|keyboard_flag ; m706:m706|in_active ; m706:m706|in_active ; 0.000 ; 0.000 ; 8.000 ; ; 5.000 ; m706:m706|keyboard_flag ; m706:m706|keyboard_flag ; m706:m706|in_active ; m706:m706|in_active ; 0.000 ; 0.000 ; 8.000 ; ; 5.000 ; m706:m706|tti37[7] ; m706:m706|in_last_unit ; m706:m706|in_active ; m706:m706|in_active ; 0.000 ; 0.000 ; 8.000 ; ; 5.000 ; m706:m706|tti37[6] ; m706:m706|tti37[7] ; m706:m706|in_active ; m706:m706|in_active ; 0.000 ; 0.000 ; 8.000 ; ; 5.000 ; m706:m706|tti37[5] ; m706:m706|tti37[6] ; m706:m706|in_active ; m706:m706|in_active ; 0.000 ; 0.000 ; 8.000 ; ; 5.000 ; m706:m706|tti37[4] ; m706:m706|tti37[5] ; m706:m706|in_active ; m706:m706|in_active ; 0.000 ; 0.000 ; 8.000 ; ; 5.000 ; m706:m706|tti37[3] ; m706:m706|tti37[4] ; m706:m706|in_active ; m706:m706|in_active ; 0.000 ; 0.000 ; 8.000 ; ; 5.000 ; m706:m706|tti02[2] ; m706:m706|tti37[3] ; m706:m706|in_active ; m706:m706|in_active ; 0.000 ; 0.000 ; 8.000 ; ; 5.000 ; m706:m706|tti02[1] ; m706:m706|tti02[2] ; m706:m706|in_active ; m706:m706|in_active ; 0.000 ; 0.000 ; 8.000 ; ; 5.000 ; m706:m706|tti02[0] ; m706:m706|tti02[1] ; m706:m706|in_active ; m706:m706|in_active ; 0.000 ; 0.000 ; 8.000 ; +--------+-------------------------+-------------------------+--------------------------+---------------------+--------------+------------+------------+ +-----------------------------------------------------------------------------------------------------------------------------------------------+ ; Hold: 'rx_rate' ; +-------+--------------------------+--------------------------+--------------------------+-------------+--------------+------------+------------+ ; Slack ; From Node ; To Node ; Launch Clock ; Latch Clock ; Relationship ; Clock Skew ; Data Delay ; +-------+--------------------------+--------------------------+--------------------------+-------------+--------------+------------+------------+ ; 1.500 ; m706:m706|clock_scale[2] ; m706:m706|clock_scale[2] ; m706:m706|clock_scale[2] ; rx_rate ; 0.000 ; 1.500 ; 8.000 ; ; 2.000 ; m706:m706|clock_scale[2] ; m706:m706|clock_scale[2] ; m706:m706|clock_scale[2] ; rx_rate ; -0.500 ; 1.500 ; 8.000 ; ; 5.000 ; m706:m706|clock_scale[0] ; m706:m706|clock_scale[0] ; rx_rate ; rx_rate ; 0.000 ; 0.000 ; 8.000 ; ; 5.000 ; m706:m706|clock_scale[1] ; m706:m706|clock_scale[1] ; rx_rate ; rx_rate ; 0.000 ; 0.000 ; 8.000 ; ; 5.000 ; m706:m706|clock_scale[0] ; m706:m706|clock_scale[1] ; rx_rate ; rx_rate ; 0.000 ; 0.000 ; 8.000 ; ; 5.000 ; m706:m706|clock_scale[1] ; m706:m706|clock_scale[2] ; rx_rate ; rx_rate ; 0.000 ; 0.000 ; 8.000 ; ; 5.000 ; m706:m706|clock_scale[0] ; m706:m706|clock_scale[2] ; rx_rate ; rx_rate ; 0.000 ; 0.000 ; 8.000 ; +-------+--------------------------+--------------------------+--------------------------+-------------+--------------+------------+------------+ +--------------------------------------------------------------------------------------------------------------------------------------------------------+ ; Recovery: 'm706:m706|in_last_unit' ; +---------+--------------------------+----------------------+--------------------------+------------------------+--------------+------------+------------+ ; Slack ; From Node ; To Node ; Launch Clock ; Latch Clock ; Relationship ; Clock Skew ; Data Delay ; +---------+--------------------------+----------------------+--------------------------+------------------------+--------------+------------+------------+ ; -27.500 ; m706:m706|spike_detector ; m706:m706|in_active ; m706:m706|clock_scale[2] ; m706:m706|in_last_unit ; 0.500 ; -5.000 ; 21.000 ; ; -27.500 ; m706:m706|spike_detector ; m706:m706|in_active ; m706:m706|in_active ; m706:m706|in_last_unit ; 0.500 ; -5.000 ; 21.000 ; ; -15.000 ; rx_data ; m706:m706|in_active ; rx_data ; m706:m706|in_last_unit ; 0.500 ; 6.000 ; 19.500 ; ; -14.500 ; m706:m706|clock_scale[2] ; m706:m706|in_active ; m706:m706|clock_scale[2] ; m706:m706|in_last_unit ; 0.500 ; 6.000 ; 21.000 ; ; -14.500 ; m706:m706|in_active ; m706:m706|in_active ; m706:m706|in_active ; m706:m706|in_last_unit ; 0.500 ; 6.000 ; 21.000 ; ; -14.500 ; rx_data ; m706:m706|in_active ; rx_data ; m706:m706|in_last_unit ; 1.000 ; 6.000 ; 19.500 ; ; -14.000 ; m706:m706|clock_scale[2] ; m706:m706|in_active ; m706:m706|clock_scale[2] ; m706:m706|in_last_unit ; 1.000 ; 6.000 ; 21.000 ; ; -14.000 ; m706:m706|in_active ; m706:m706|in_active ; m706:m706|in_active ; m706:m706|in_last_unit ; 1.000 ; 6.000 ; 21.000 ; ; -12.000 ; m706:m706|keyboard_flag ; m706:m706|reader_run ; m706:m706|clock_scale[2] ; m706:m706|in_last_unit ; 1.000 ; 0.000 ; 11.000 ; ; -12.000 ; m706:m706|keyboard_flag ; m706:m706|reader_run ; m706:m706|in_active ; m706:m706|in_last_unit ; 1.000 ; 0.000 ; 11.000 ; ; -5.000 ; rx_rate ; m706:m706|in_active ; rx_rate ; m706:m706|in_last_unit ; 0.500 ; 6.000 ; 9.500 ; ; -4.500 ; m706:m706|in_last_unit ; m706:m706|in_active ; m706:m706|in_last_unit ; m706:m706|in_last_unit ; 0.500 ; 6.000 ; 11.000 ; ; -4.500 ; rx_rate ; m706:m706|in_active ; rx_rate ; m706:m706|in_last_unit ; 1.000 ; 6.000 ; 9.500 ; ; -4.000 ; m706:m706|in_last_unit ; m706:m706|in_active ; m706:m706|in_last_unit ; m706:m706|in_last_unit ; 1.000 ; 6.000 ; 11.000 ; +---------+--------------------------+----------------------+--------------------------+------------------------+--------------+------------+------------+ +--------------------------------------------------------------------------------------------------------------------------------------------------------------+ ; Recovery: 'm706:m706|clock_scale[2]' ; +---------+--------------------------+--------------------------+--------------------------+--------------------------+--------------+------------+------------+ ; Slack ; From Node ; To Node ; Launch Clock ; Latch Clock ; Relationship ; Clock Skew ; Data Delay ; +---------+--------------------------+--------------------------+--------------------------+--------------------------+--------------+------------+------------+ ; -22.500 ; m706:m706|spike_detector ; m706:m706|in_active ; m706:m706|clock_scale[2] ; m706:m706|clock_scale[2] ; 0.500 ; 0.000 ; 21.000 ; ; -22.500 ; m706:m706|spike_detector ; m706:m706|in_active ; m706:m706|in_active ; m706:m706|clock_scale[2] ; 0.500 ; 0.000 ; 21.000 ; ; -12.000 ; m706:m706|in_stop[2] ; m706:m706|in_last_unit ; m706:m706|clock_scale[2] ; m706:m706|clock_scale[2] ; 1.000 ; 0.000 ; 11.000 ; ; -10.000 ; rx_data ; m706:m706|in_active ; rx_data ; m706:m706|clock_scale[2] ; 0.500 ; 11.000 ; 19.500 ; ; -9.500 ; m706:m706|clock_scale[2] ; m706:m706|in_active ; m706:m706|clock_scale[2] ; m706:m706|clock_scale[2] ; 0.500 ; 11.000 ; 21.000 ; ; -9.500 ; m706:m706|in_active ; m706:m706|in_active ; m706:m706|in_active ; m706:m706|clock_scale[2] ; 0.500 ; 11.000 ; 21.000 ; ; -9.500 ; rx_data ; m706:m706|in_active ; rx_data ; m706:m706|clock_scale[2] ; 1.000 ; 11.000 ; 19.500 ; ; -9.000 ; m706:m706|clock_scale[2] ; m706:m706|in_active ; m706:m706|clock_scale[2] ; m706:m706|clock_scale[2] ; 1.000 ; 11.000 ; 21.000 ; ; -9.000 ; m706:m706|in_active ; m706:m706|in_active ; m706:m706|in_active ; m706:m706|clock_scale[2] ; 1.000 ; 11.000 ; 21.000 ; ; -5.000 ; rx_rate ; m706:m706|in_stop[1] ; rx_rate ; m706:m706|clock_scale[2] ; 0.500 ; 6.000 ; 9.500 ; ; -5.000 ; rx_rate ; m706:m706|in_stop[2] ; rx_rate ; m706:m706|clock_scale[2] ; 0.500 ; 6.000 ; 9.500 ; ; -5.000 ; rx_rate ; m706:m706|tti37[7] ; rx_rate ; m706:m706|clock_scale[2] ; 0.500 ; 6.000 ; 9.500 ; ; -5.000 ; rx_rate ; m706:m706|tti37[6] ; rx_rate ; m706:m706|clock_scale[2] ; 0.500 ; 6.000 ; 9.500 ; ; -5.000 ; rx_rate ; m706:m706|tti37[5] ; rx_rate ; m706:m706|clock_scale[2] ; 0.500 ; 6.000 ; 9.500 ; ; -5.000 ; rx_rate ; m706:m706|tti37[4] ; rx_rate ; m706:m706|clock_scale[2] ; 0.500 ; 6.000 ; 9.500 ; ; -5.000 ; rx_rate ; m706:m706|tti37[3] ; rx_rate ; m706:m706|clock_scale[2] ; 0.500 ; 6.000 ; 9.500 ; ; -5.000 ; rx_rate ; m706:m706|tti02[2] ; rx_rate ; m706:m706|clock_scale[2] ; 0.500 ; 6.000 ; 9.500 ; ; -5.000 ; rx_rate ; m706:m706|tti02[1] ; rx_rate ; m706:m706|clock_scale[2] ; 0.500 ; 6.000 ; 9.500 ; ; -5.000 ; rx_rate ; m706:m706|tti02[0] ; rx_rate ; m706:m706|clock_scale[2] ; 0.500 ; 6.000 ; 9.500 ; ; -5.000 ; rx_data ; m706:m706|in_stop[1] ; rx_data ; m706:m706|clock_scale[2] ; 0.500 ; 6.000 ; 9.500 ; ; -5.000 ; rx_data ; m706:m706|in_stop[2] ; rx_data ; m706:m706|clock_scale[2] ; 0.500 ; 6.000 ; 9.500 ; ; -5.000 ; rx_data ; m706:m706|tti37[7] ; rx_data ; m706:m706|clock_scale[2] ; 0.500 ; 6.000 ; 9.500 ; ; -5.000 ; rx_data ; m706:m706|tti37[6] ; rx_data ; m706:m706|clock_scale[2] ; 0.500 ; 6.000 ; 9.500 ; ; -5.000 ; rx_data ; m706:m706|tti37[5] ; rx_data ; m706:m706|clock_scale[2] ; 0.500 ; 6.000 ; 9.500 ; ; -5.000 ; rx_data ; m706:m706|tti37[4] ; rx_data ; m706:m706|clock_scale[2] ; 0.500 ; 6.000 ; 9.500 ; ; -5.000 ; rx_data ; m706:m706|tti37[3] ; rx_data ; m706:m706|clock_scale[2] ; 0.500 ; 6.000 ; 9.500 ; ; -5.000 ; rx_data ; m706:m706|tti02[2] ; rx_data ; m706:m706|clock_scale[2] ; 0.500 ; 6.000 ; 9.500 ; ; -5.000 ; rx_data ; m706:m706|tti02[1] ; rx_data ; m706:m706|clock_scale[2] ; 0.500 ; 6.000 ; 9.500 ; ; -5.000 ; rx_data ; m706:m706|tti02[0] ; rx_data ; m706:m706|clock_scale[2] ; 0.500 ; 6.000 ; 9.500 ; ; -4.500 ; m706:m706|in_last_unit ; m706:m706|in_stop[1] ; m706:m706|in_last_unit ; m706:m706|clock_scale[2] ; 0.500 ; 6.000 ; 11.000 ; ; -4.500 ; m706:m706|in_last_unit ; m706:m706|in_stop[2] ; m706:m706|in_last_unit ; m706:m706|clock_scale[2] ; 0.500 ; 6.000 ; 11.000 ; ; -4.500 ; m706:m706|in_last_unit ; m706:m706|tti37[7] ; m706:m706|in_last_unit ; m706:m706|clock_scale[2] ; 0.500 ; 6.000 ; 11.000 ; ; -4.500 ; m706:m706|in_last_unit ; m706:m706|tti37[6] ; m706:m706|in_last_unit ; m706:m706|clock_scale[2] ; 0.500 ; 6.000 ; 11.000 ; ; -4.500 ; m706:m706|in_last_unit ; m706:m706|tti37[5] ; m706:m706|in_last_unit ; m706:m706|clock_scale[2] ; 0.500 ; 6.000 ; 11.000 ; ; -4.500 ; m706:m706|in_last_unit ; m706:m706|tti37[4] ; m706:m706|in_last_unit ; m706:m706|clock_scale[2] ; 0.500 ; 6.000 ; 11.000 ; ; -4.500 ; m706:m706|in_last_unit ; m706:m706|tti37[3] ; m706:m706|in_last_unit ; m706:m706|clock_scale[2] ; 0.500 ; 6.000 ; 11.000 ; ; -4.500 ; m706:m706|in_last_unit ; m706:m706|tti02[2] ; m706:m706|in_last_unit ; m706:m706|clock_scale[2] ; 0.500 ; 6.000 ; 11.000 ; ; -4.500 ; m706:m706|in_last_unit ; m706:m706|tti02[1] ; m706:m706|in_last_unit ; m706:m706|clock_scale[2] ; 0.500 ; 6.000 ; 11.000 ; ; -4.500 ; m706:m706|in_last_unit ; m706:m706|tti02[0] ; m706:m706|in_last_unit ; m706:m706|clock_scale[2] ; 0.500 ; 6.000 ; 11.000 ; ; -4.500 ; rx_rate ; m706:m706|in_stop[1] ; rx_rate ; m706:m706|clock_scale[2] ; 1.000 ; 6.000 ; 9.500 ; ; -4.500 ; rx_rate ; m706:m706|in_stop[2] ; rx_rate ; m706:m706|clock_scale[2] ; 1.000 ; 6.000 ; 9.500 ; ; -4.500 ; rx_rate ; m706:m706|tti37[7] ; rx_rate ; m706:m706|clock_scale[2] ; 1.000 ; 6.000 ; 9.500 ; ; -4.500 ; rx_rate ; m706:m706|tti37[6] ; rx_rate ; m706:m706|clock_scale[2] ; 1.000 ; 6.000 ; 9.500 ; ; -4.500 ; rx_rate ; m706:m706|tti37[5] ; rx_rate ; m706:m706|clock_scale[2] ; 1.000 ; 6.000 ; 9.500 ; ; -4.500 ; rx_rate ; m706:m706|tti37[4] ; rx_rate ; m706:m706|clock_scale[2] ; 1.000 ; 6.000 ; 9.500 ; ; -4.500 ; rx_rate ; m706:m706|tti37[3] ; rx_rate ; m706:m706|clock_scale[2] ; 1.000 ; 6.000 ; 9.500 ; ; -4.500 ; rx_rate ; m706:m706|tti02[2] ; rx_rate ; m706:m706|clock_scale[2] ; 1.000 ; 6.000 ; 9.500 ; ; -4.500 ; rx_rate ; m706:m706|tti02[1] ; rx_rate ; m706:m706|clock_scale[2] ; 1.000 ; 6.000 ; 9.500 ; ; -4.500 ; rx_rate ; m706:m706|tti02[0] ; rx_rate ; m706:m706|clock_scale[2] ; 1.000 ; 6.000 ; 9.500 ; ; -4.500 ; m706:m706|in_active ; m706:m706|in_stop[1] ; m706:m706|in_active ; m706:m706|clock_scale[2] ; 0.500 ; 6.000 ; 11.000 ; ; -4.500 ; m706:m706|in_active ; m706:m706|in_stop[2] ; m706:m706|in_active ; m706:m706|clock_scale[2] ; 0.500 ; 6.000 ; 11.000 ; ; -4.500 ; m706:m706|in_active ; m706:m706|tti37[7] ; m706:m706|in_active ; m706:m706|clock_scale[2] ; 0.500 ; 6.000 ; 11.000 ; ; -4.500 ; m706:m706|in_active ; m706:m706|tti37[6] ; m706:m706|in_active ; m706:m706|clock_scale[2] ; 0.500 ; 6.000 ; 11.000 ; ; -4.500 ; m706:m706|in_active ; m706:m706|tti37[5] ; m706:m706|in_active ; m706:m706|clock_scale[2] ; 0.500 ; 6.000 ; 11.000 ; ; -4.500 ; m706:m706|in_active ; m706:m706|tti37[4] ; m706:m706|in_active ; m706:m706|clock_scale[2] ; 0.500 ; 6.000 ; 11.000 ; ; -4.500 ; m706:m706|in_active ; m706:m706|tti37[3] ; m706:m706|in_active ; m706:m706|clock_scale[2] ; 0.500 ; 6.000 ; 11.000 ; ; -4.500 ; m706:m706|in_active ; m706:m706|tti02[2] ; m706:m706|in_active ; m706:m706|clock_scale[2] ; 0.500 ; 6.000 ; 11.000 ; ; -4.500 ; m706:m706|in_active ; m706:m706|tti02[1] ; m706:m706|in_active ; m706:m706|clock_scale[2] ; 0.500 ; 6.000 ; 11.000 ; ; -4.500 ; m706:m706|in_active ; m706:m706|tti02[0] ; m706:m706|in_active ; m706:m706|clock_scale[2] ; 0.500 ; 6.000 ; 11.000 ; ; -4.500 ; rx_data ; m706:m706|in_stop[1] ; rx_data ; m706:m706|clock_scale[2] ; 1.000 ; 6.000 ; 9.500 ; ; -4.500 ; rx_data ; m706:m706|in_stop[2] ; rx_data ; m706:m706|clock_scale[2] ; 1.000 ; 6.000 ; 9.500 ; ; -4.500 ; rx_data ; m706:m706|tti37[7] ; rx_data ; m706:m706|clock_scale[2] ; 1.000 ; 6.000 ; 9.500 ; ; -4.500 ; rx_data ; m706:m706|tti37[6] ; rx_data ; m706:m706|clock_scale[2] ; 1.000 ; 6.000 ; 9.500 ; ; -4.500 ; rx_data ; m706:m706|tti37[5] ; rx_data ; m706:m706|clock_scale[2] ; 1.000 ; 6.000 ; 9.500 ; ; -4.500 ; rx_data ; m706:m706|tti37[4] ; rx_data ; m706:m706|clock_scale[2] ; 1.000 ; 6.000 ; 9.500 ; ; -4.500 ; rx_data ; m706:m706|tti37[3] ; rx_data ; m706:m706|clock_scale[2] ; 1.000 ; 6.000 ; 9.500 ; ; -4.500 ; rx_data ; m706:m706|tti02[2] ; rx_data ; m706:m706|clock_scale[2] ; 1.000 ; 6.000 ; 9.500 ; ; -4.500 ; rx_data ; m706:m706|tti02[1] ; rx_data ; m706:m706|clock_scale[2] ; 1.000 ; 6.000 ; 9.500 ; ; -4.500 ; rx_data ; m706:m706|tti02[0] ; rx_data ; m706:m706|clock_scale[2] ; 1.000 ; 6.000 ; 9.500 ; ; -4.000 ; m706:m706|in_last_unit ; m706:m706|in_stop[1] ; m706:m706|in_last_unit ; m706:m706|clock_scale[2] ; 1.000 ; 6.000 ; 11.000 ; ; -4.000 ; m706:m706|in_last_unit ; m706:m706|in_stop[2] ; m706:m706|in_last_unit ; m706:m706|clock_scale[2] ; 1.000 ; 6.000 ; 11.000 ; ; -4.000 ; m706:m706|in_last_unit ; m706:m706|tti37[7] ; m706:m706|in_last_unit ; m706:m706|clock_scale[2] ; 1.000 ; 6.000 ; 11.000 ; ; -4.000 ; m706:m706|in_last_unit ; m706:m706|tti37[6] ; m706:m706|in_last_unit ; m706:m706|clock_scale[2] ; 1.000 ; 6.000 ; 11.000 ; ; -4.000 ; m706:m706|in_last_unit ; m706:m706|tti37[5] ; m706:m706|in_last_unit ; m706:m706|clock_scale[2] ; 1.000 ; 6.000 ; 11.000 ; ; -4.000 ; m706:m706|in_last_unit ; m706:m706|tti37[4] ; m706:m706|in_last_unit ; m706:m706|clock_scale[2] ; 1.000 ; 6.000 ; 11.000 ; ; -4.000 ; m706:m706|in_last_unit ; m706:m706|tti37[3] ; m706:m706|in_last_unit ; m706:m706|clock_scale[2] ; 1.000 ; 6.000 ; 11.000 ; ; -4.000 ; m706:m706|in_last_unit ; m706:m706|tti02[2] ; m706:m706|in_last_unit ; m706:m706|clock_scale[2] ; 1.000 ; 6.000 ; 11.000 ; ; -4.000 ; m706:m706|in_last_unit ; m706:m706|tti02[1] ; m706:m706|in_last_unit ; m706:m706|clock_scale[2] ; 1.000 ; 6.000 ; 11.000 ; ; -4.000 ; m706:m706|in_last_unit ; m706:m706|tti02[0] ; m706:m706|in_last_unit ; m706:m706|clock_scale[2] ; 1.000 ; 6.000 ; 11.000 ; ; -4.000 ; m706:m706|in_active ; m706:m706|in_stop[1] ; m706:m706|in_active ; m706:m706|clock_scale[2] ; 1.000 ; 6.000 ; 11.000 ; ; -4.000 ; m706:m706|in_active ; m706:m706|in_stop[2] ; m706:m706|in_active ; m706:m706|clock_scale[2] ; 1.000 ; 6.000 ; 11.000 ; ; -4.000 ; m706:m706|in_active ; m706:m706|tti37[7] ; m706:m706|in_active ; m706:m706|clock_scale[2] ; 1.000 ; 6.000 ; 11.000 ; ; -4.000 ; m706:m706|in_active ; m706:m706|tti37[6] ; m706:m706|in_active ; m706:m706|clock_scale[2] ; 1.000 ; 6.000 ; 11.000 ; ; -4.000 ; m706:m706|in_active ; m706:m706|tti37[5] ; m706:m706|in_active ; m706:m706|clock_scale[2] ; 1.000 ; 6.000 ; 11.000 ; ; -4.000 ; m706:m706|in_active ; m706:m706|tti37[4] ; m706:m706|in_active ; m706:m706|clock_scale[2] ; 1.000 ; 6.000 ; 11.000 ; ; -4.000 ; m706:m706|in_active ; m706:m706|tti37[3] ; m706:m706|in_active ; m706:m706|clock_scale[2] ; 1.000 ; 6.000 ; 11.000 ; ; -4.000 ; m706:m706|in_active ; m706:m706|tti02[2] ; m706:m706|in_active ; m706:m706|clock_scale[2] ; 1.000 ; 6.000 ; 11.000 ; ; -4.000 ; m706:m706|in_active ; m706:m706|tti02[1] ; m706:m706|in_active ; m706:m706|clock_scale[2] ; 1.000 ; 6.000 ; 11.000 ; ; -4.000 ; m706:m706|in_active ; m706:m706|tti02[0] ; m706:m706|in_active ; m706:m706|clock_scale[2] ; 1.000 ; 6.000 ; 11.000 ; ; 0.000 ; rx_rate ; m706:m706|in_active ; rx_rate ; m706:m706|clock_scale[2] ; 0.500 ; 11.000 ; 9.500 ; ; 0.500 ; m706:m706|in_last_unit ; m706:m706|in_active ; m706:m706|in_last_unit ; m706:m706|clock_scale[2] ; 0.500 ; 11.000 ; 11.000 ; ; 0.500 ; rx_rate ; m706:m706|in_active ; rx_rate ; m706:m706|clock_scale[2] ; 1.000 ; 11.000 ; 9.500 ; ; 1.000 ; m706:m706|in_last_unit ; m706:m706|in_active ; m706:m706|in_last_unit ; m706:m706|clock_scale[2] ; 1.000 ; 11.000 ; 11.000 ; ; 3.000 ; rx_rate ; m706:m706|spike_detector ; rx_rate ; m706:m706|clock_scale[2] ; 0.500 ; 11.000 ; 6.500 ; ; 3.000 ; rx_data ; m706:m706|spike_detector ; rx_data ; m706:m706|clock_scale[2] ; 0.500 ; 11.000 ; 6.500 ; ; 3.500 ; m706:m706|in_last_unit ; m706:m706|spike_detector ; m706:m706|in_last_unit ; m706:m706|clock_scale[2] ; 0.500 ; 11.000 ; 8.000 ; ; 3.500 ; rx_rate ; m706:m706|spike_detector ; rx_rate ; m706:m706|clock_scale[2] ; 1.000 ; 11.000 ; 6.500 ; ; 3.500 ; m706:m706|in_active ; m706:m706|spike_detector ; m706:m706|in_active ; m706:m706|clock_scale[2] ; 0.500 ; 11.000 ; 8.000 ; ; 3.500 ; rx_data ; m706:m706|spike_detector ; rx_data ; m706:m706|clock_scale[2] ; 1.000 ; 11.000 ; 6.500 ; ; 4.000 ; m706:m706|in_last_unit ; m706:m706|spike_detector ; m706:m706|in_last_unit ; m706:m706|clock_scale[2] ; 1.000 ; 11.000 ; 8.000 ; +---------+--------------------------+--------------------------+--------------------------+--------------------------+--------------+------------+------------+ +--------------------------------------------------------------------------------------------------------------------------------------------------------+ ; Recovery: 'm706:m706|in_active' ; +---------+-------------------------+--------------------------+--------------------------+---------------------+--------------+------------+------------+ ; Slack ; From Node ; To Node ; Launch Clock ; Latch Clock ; Relationship ; Clock Skew ; Data Delay ; +---------+-------------------------+--------------------------+--------------------------+---------------------+--------------+------------+------------+ ; -12.000 ; m706:m706|keyboard_flag ; m706:m706|reader_run ; m706:m706|clock_scale[2] ; m706:m706|in_active ; 1.000 ; 0.000 ; 11.000 ; ; -12.000 ; m706:m706|in_stop[2] ; m706:m706|in_last_unit ; m706:m706|clock_scale[2] ; m706:m706|in_active ; 1.000 ; 0.000 ; 11.000 ; ; -12.000 ; m706:m706|keyboard_flag ; m706:m706|reader_run ; m706:m706|in_active ; m706:m706|in_active ; 1.000 ; 0.000 ; 11.000 ; ; -5.000 ; rx_rate ; m706:m706|tti37[7] ; rx_rate ; m706:m706|in_active ; 0.500 ; 6.000 ; 9.500 ; ; -5.000 ; rx_rate ; m706:m706|tti37[6] ; rx_rate ; m706:m706|in_active ; 0.500 ; 6.000 ; 9.500 ; ; -5.000 ; rx_rate ; m706:m706|tti37[5] ; rx_rate ; m706:m706|in_active ; 0.500 ; 6.000 ; 9.500 ; ; -5.000 ; rx_rate ; m706:m706|tti37[4] ; rx_rate ; m706:m706|in_active ; 0.500 ; 6.000 ; 9.500 ; ; -5.000 ; rx_rate ; m706:m706|tti37[3] ; rx_rate ; m706:m706|in_active ; 0.500 ; 6.000 ; 9.500 ; ; -5.000 ; rx_rate ; m706:m706|tti02[2] ; rx_rate ; m706:m706|in_active ; 0.500 ; 6.000 ; 9.500 ; ; -5.000 ; rx_rate ; m706:m706|tti02[1] ; rx_rate ; m706:m706|in_active ; 0.500 ; 6.000 ; 9.500 ; ; -5.000 ; rx_rate ; m706:m706|tti02[0] ; rx_rate ; m706:m706|in_active ; 0.500 ; 6.000 ; 9.500 ; ; -5.000 ; rx_data ; m706:m706|tti37[7] ; rx_data ; m706:m706|in_active ; 0.500 ; 6.000 ; 9.500 ; ; -5.000 ; rx_data ; m706:m706|tti37[6] ; rx_data ; m706:m706|in_active ; 0.500 ; 6.000 ; 9.500 ; ; -5.000 ; rx_data ; m706:m706|tti37[5] ; rx_data ; m706:m706|in_active ; 0.500 ; 6.000 ; 9.500 ; ; -5.000 ; rx_data ; m706:m706|tti37[4] ; rx_data ; m706:m706|in_active ; 0.500 ; 6.000 ; 9.500 ; ; -5.000 ; rx_data ; m706:m706|tti37[3] ; rx_data ; m706:m706|in_active ; 0.500 ; 6.000 ; 9.500 ; ; -5.000 ; rx_data ; m706:m706|tti02[2] ; rx_data ; m706:m706|in_active ; 0.500 ; 6.000 ; 9.500 ; ; -5.000 ; rx_data ; m706:m706|tti02[1] ; rx_data ; m706:m706|in_active ; 0.500 ; 6.000 ; 9.500 ; ; -5.000 ; rx_data ; m706:m706|tti02[0] ; rx_data ; m706:m706|in_active ; 0.500 ; 6.000 ; 9.500 ; ; -4.500 ; m706:m706|in_last_unit ; m706:m706|tti37[7] ; m706:m706|in_last_unit ; m706:m706|in_active ; 0.500 ; 6.000 ; 11.000 ; ; -4.500 ; m706:m706|in_last_unit ; m706:m706|tti37[6] ; m706:m706|in_last_unit ; m706:m706|in_active ; 0.500 ; 6.000 ; 11.000 ; ; -4.500 ; m706:m706|in_last_unit ; m706:m706|tti37[5] ; m706:m706|in_last_unit ; m706:m706|in_active ; 0.500 ; 6.000 ; 11.000 ; ; -4.500 ; m706:m706|in_last_unit ; m706:m706|tti37[4] ; m706:m706|in_last_unit ; m706:m706|in_active ; 0.500 ; 6.000 ; 11.000 ; ; -4.500 ; m706:m706|in_last_unit ; m706:m706|tti37[3] ; m706:m706|in_last_unit ; m706:m706|in_active ; 0.500 ; 6.000 ; 11.000 ; ; -4.500 ; m706:m706|in_last_unit ; m706:m706|tti02[2] ; m706:m706|in_last_unit ; m706:m706|in_active ; 0.500 ; 6.000 ; 11.000 ; ; -4.500 ; m706:m706|in_last_unit ; m706:m706|tti02[1] ; m706:m706|in_last_unit ; m706:m706|in_active ; 0.500 ; 6.000 ; 11.000 ; ; -4.500 ; m706:m706|in_last_unit ; m706:m706|tti02[0] ; m706:m706|in_last_unit ; m706:m706|in_active ; 0.500 ; 6.000 ; 11.000 ; ; -4.500 ; rx_rate ; m706:m706|tti37[7] ; rx_rate ; m706:m706|in_active ; 1.000 ; 6.000 ; 9.500 ; ; -4.500 ; rx_rate ; m706:m706|tti37[6] ; rx_rate ; m706:m706|in_active ; 1.000 ; 6.000 ; 9.500 ; ; -4.500 ; rx_rate ; m706:m706|tti37[5] ; rx_rate ; m706:m706|in_active ; 1.000 ; 6.000 ; 9.500 ; ; -4.500 ; rx_rate ; m706:m706|tti37[4] ; rx_rate ; m706:m706|in_active ; 1.000 ; 6.000 ; 9.500 ; ; -4.500 ; rx_rate ; m706:m706|tti37[3] ; rx_rate ; m706:m706|in_active ; 1.000 ; 6.000 ; 9.500 ; ; -4.500 ; rx_rate ; m706:m706|tti02[2] ; rx_rate ; m706:m706|in_active ; 1.000 ; 6.000 ; 9.500 ; ; -4.500 ; rx_rate ; m706:m706|tti02[1] ; rx_rate ; m706:m706|in_active ; 1.000 ; 6.000 ; 9.500 ; ; -4.500 ; rx_rate ; m706:m706|tti02[0] ; rx_rate ; m706:m706|in_active ; 1.000 ; 6.000 ; 9.500 ; ; -4.500 ; m706:m706|in_active ; m706:m706|tti37[7] ; m706:m706|in_active ; m706:m706|in_active ; 0.500 ; 6.000 ; 11.000 ; ; -4.500 ; m706:m706|in_active ; m706:m706|tti37[6] ; m706:m706|in_active ; m706:m706|in_active ; 0.500 ; 6.000 ; 11.000 ; ; -4.500 ; m706:m706|in_active ; m706:m706|tti37[5] ; m706:m706|in_active ; m706:m706|in_active ; 0.500 ; 6.000 ; 11.000 ; ; -4.500 ; m706:m706|in_active ; m706:m706|tti37[4] ; m706:m706|in_active ; m706:m706|in_active ; 0.500 ; 6.000 ; 11.000 ; ; -4.500 ; m706:m706|in_active ; m706:m706|tti37[3] ; m706:m706|in_active ; m706:m706|in_active ; 0.500 ; 6.000 ; 11.000 ; ; -4.500 ; m706:m706|in_active ; m706:m706|tti02[2] ; m706:m706|in_active ; m706:m706|in_active ; 0.500 ; 6.000 ; 11.000 ; ; -4.500 ; m706:m706|in_active ; m706:m706|tti02[1] ; m706:m706|in_active ; m706:m706|in_active ; 0.500 ; 6.000 ; 11.000 ; ; -4.500 ; m706:m706|in_active ; m706:m706|tti02[0] ; m706:m706|in_active ; m706:m706|in_active ; 0.500 ; 6.000 ; 11.000 ; ; -4.500 ; rx_data ; m706:m706|tti37[7] ; rx_data ; m706:m706|in_active ; 1.000 ; 6.000 ; 9.500 ; ; -4.500 ; rx_data ; m706:m706|tti37[6] ; rx_data ; m706:m706|in_active ; 1.000 ; 6.000 ; 9.500 ; ; -4.500 ; rx_data ; m706:m706|tti37[5] ; rx_data ; m706:m706|in_active ; 1.000 ; 6.000 ; 9.500 ; ; -4.500 ; rx_data ; m706:m706|tti37[4] ; rx_data ; m706:m706|in_active ; 1.000 ; 6.000 ; 9.500 ; ; -4.500 ; rx_data ; m706:m706|tti37[3] ; rx_data ; m706:m706|in_active ; 1.000 ; 6.000 ; 9.500 ; ; -4.500 ; rx_data ; m706:m706|tti02[2] ; rx_data ; m706:m706|in_active ; 1.000 ; 6.000 ; 9.500 ; ; -4.500 ; rx_data ; m706:m706|tti02[1] ; rx_data ; m706:m706|in_active ; 1.000 ; 6.000 ; 9.500 ; ; -4.500 ; rx_data ; m706:m706|tti02[0] ; rx_data ; m706:m706|in_active ; 1.000 ; 6.000 ; 9.500 ; ; -4.000 ; m706:m706|in_last_unit ; m706:m706|tti37[7] ; m706:m706|in_last_unit ; m706:m706|in_active ; 1.000 ; 6.000 ; 11.000 ; ; -4.000 ; m706:m706|in_last_unit ; m706:m706|tti37[6] ; m706:m706|in_last_unit ; m706:m706|in_active ; 1.000 ; 6.000 ; 11.000 ; ; -4.000 ; m706:m706|in_last_unit ; m706:m706|tti37[5] ; m706:m706|in_last_unit ; m706:m706|in_active ; 1.000 ; 6.000 ; 11.000 ; ; -4.000 ; m706:m706|in_last_unit ; m706:m706|tti37[4] ; m706:m706|in_last_unit ; m706:m706|in_active ; 1.000 ; 6.000 ; 11.000 ; ; -4.000 ; m706:m706|in_last_unit ; m706:m706|tti37[3] ; m706:m706|in_last_unit ; m706:m706|in_active ; 1.000 ; 6.000 ; 11.000 ; ; -4.000 ; m706:m706|in_last_unit ; m706:m706|tti02[2] ; m706:m706|in_last_unit ; m706:m706|in_active ; 1.000 ; 6.000 ; 11.000 ; ; -4.000 ; m706:m706|in_last_unit ; m706:m706|tti02[1] ; m706:m706|in_last_unit ; m706:m706|in_active ; 1.000 ; 6.000 ; 11.000 ; ; -4.000 ; m706:m706|in_last_unit ; m706:m706|tti02[0] ; m706:m706|in_last_unit ; m706:m706|in_active ; 1.000 ; 6.000 ; 11.000 ; ; -4.000 ; m706:m706|in_active ; m706:m706|tti37[7] ; m706:m706|in_active ; m706:m706|in_active ; 1.000 ; 6.000 ; 11.000 ; ; -4.000 ; m706:m706|in_active ; m706:m706|tti37[6] ; m706:m706|in_active ; m706:m706|in_active ; 1.000 ; 6.000 ; 11.000 ; ; -4.000 ; m706:m706|in_active ; m706:m706|tti37[5] ; m706:m706|in_active ; m706:m706|in_active ; 1.000 ; 6.000 ; 11.000 ; ; -4.000 ; m706:m706|in_active ; m706:m706|tti37[4] ; m706:m706|in_active ; m706:m706|in_active ; 1.000 ; 6.000 ; 11.000 ; ; -4.000 ; m706:m706|in_active ; m706:m706|tti37[3] ; m706:m706|in_active ; m706:m706|in_active ; 1.000 ; 6.000 ; 11.000 ; ; -4.000 ; m706:m706|in_active ; m706:m706|tti02[2] ; m706:m706|in_active ; m706:m706|in_active ; 1.000 ; 6.000 ; 11.000 ; ; -4.000 ; m706:m706|in_active ; m706:m706|tti02[1] ; m706:m706|in_active ; m706:m706|in_active ; 1.000 ; 6.000 ; 11.000 ; ; -4.000 ; m706:m706|in_active ; m706:m706|tti02[0] ; m706:m706|in_active ; m706:m706|in_active ; 1.000 ; 6.000 ; 11.000 ; ; 3.000 ; rx_rate ; m706:m706|spike_detector ; rx_rate ; m706:m706|in_active ; 0.500 ; 11.000 ; 6.500 ; ; 3.000 ; rx_data ; m706:m706|spike_detector ; rx_data ; m706:m706|in_active ; 0.500 ; 11.000 ; 6.500 ; ; 3.500 ; m706:m706|in_last_unit ; m706:m706|spike_detector ; m706:m706|in_last_unit ; m706:m706|in_active ; 0.500 ; 11.000 ; 8.000 ; ; 3.500 ; rx_rate ; m706:m706|spike_detector ; rx_rate ; m706:m706|in_active ; 1.000 ; 11.000 ; 6.500 ; ; 3.500 ; m706:m706|in_active ; m706:m706|spike_detector ; m706:m706|in_active ; m706:m706|in_active ; 0.500 ; 11.000 ; 8.000 ; ; 3.500 ; rx_data ; m706:m706|spike_detector ; rx_data ; m706:m706|in_active ; 1.000 ; 11.000 ; 6.500 ; ; 4.000 ; m706:m706|in_last_unit ; m706:m706|spike_detector ; m706:m706|in_last_unit ; m706:m706|in_active ; 1.000 ; 11.000 ; 8.000 ; ; 4.000 ; m706:m706|in_active ; m706:m706|spike_detector ; m706:m706|in_active ; m706:m706|in_active ; 1.000 ; 11.000 ; 8.000 ; +---------+-------------------------+--------------------------+--------------------------+---------------------+--------------+------------+------------+ +------------------------------------------------------------------------------------------------------------------------------------------------+ ; Recovery: 'rx_rate' ; +---------+-------------------------+--------------------------+--------------------------+-------------+--------------+------------+------------+ ; Slack ; From Node ; To Node ; Launch Clock ; Latch Clock ; Relationship ; Clock Skew ; Data Delay ; +---------+-------------------------+--------------------------+--------------------------+-------------+--------------+------------+------------+ ; -11.500 ; m706:m706|keyboard_flag ; m706:m706|reader_run ; m706:m706|clock_scale[2] ; rx_rate ; 1.000 ; 0.500 ; 11.000 ; ; -11.500 ; m706:m706|keyboard_flag ; m706:m706|reader_run ; m706:m706|in_active ; rx_rate ; 1.000 ; 0.500 ; 11.000 ; ; -9.000 ; m706:m706|in_last_unit ; m706:m706|clock_scale[0] ; m706:m706|in_last_unit ; rx_rate ; 0.500 ; 1.500 ; 11.000 ; ; -9.000 ; m706:m706|in_last_unit ; m706:m706|clock_scale[1] ; m706:m706|in_last_unit ; rx_rate ; 0.500 ; 1.500 ; 11.000 ; ; -9.000 ; m706:m706|in_last_unit ; m706:m706|clock_scale[2] ; m706:m706|in_last_unit ; rx_rate ; 0.500 ; 1.500 ; 11.000 ; ; -9.000 ; m706:m706|in_active ; m706:m706|clock_scale[0] ; m706:m706|in_active ; rx_rate ; 0.500 ; 1.500 ; 11.000 ; ; -9.000 ; m706:m706|in_active ; m706:m706|clock_scale[1] ; m706:m706|in_active ; rx_rate ; 0.500 ; 1.500 ; 11.000 ; ; -9.000 ; m706:m706|in_active ; m706:m706|clock_scale[2] ; m706:m706|in_active ; rx_rate ; 0.500 ; 1.500 ; 11.000 ; ; -8.500 ; m706:m706|in_last_unit ; m706:m706|clock_scale[0] ; m706:m706|in_last_unit ; rx_rate ; 1.000 ; 1.500 ; 11.000 ; ; -8.500 ; m706:m706|in_last_unit ; m706:m706|clock_scale[1] ; m706:m706|in_last_unit ; rx_rate ; 1.000 ; 1.500 ; 11.000 ; ; -8.500 ; m706:m706|in_last_unit ; m706:m706|clock_scale[2] ; m706:m706|in_last_unit ; rx_rate ; 1.000 ; 1.500 ; 11.000 ; ; -8.500 ; m706:m706|in_active ; m706:m706|clock_scale[0] ; m706:m706|in_active ; rx_rate ; 1.000 ; 1.500 ; 11.000 ; ; -8.500 ; m706:m706|in_active ; m706:m706|clock_scale[1] ; m706:m706|in_active ; rx_rate ; 1.000 ; 1.500 ; 11.000 ; ; -8.500 ; m706:m706|in_active ; m706:m706|clock_scale[2] ; m706:m706|in_active ; rx_rate ; 1.000 ; 1.500 ; 11.000 ; +---------+-------------------------+--------------------------+--------------------------+-------------+--------------+------------+------------+ +--------------------------------------------------------------------------------------------------------------------------------------------+ ; Recovery: 'rx_data' ; +---------+-------------------------+----------------------+--------------------------+-------------+--------------+------------+------------+ ; Slack ; From Node ; To Node ; Launch Clock ; Latch Clock ; Relationship ; Clock Skew ; Data Delay ; +---------+-------------------------+----------------------+--------------------------+-------------+--------------+------------+------------+ ; -11.500 ; m706:m706|keyboard_flag ; m706:m706|reader_run ; m706:m706|clock_scale[2] ; rx_data ; 1.000 ; 0.500 ; 11.000 ; ; -11.500 ; m706:m706|keyboard_flag ; m706:m706|reader_run ; m706:m706|in_active ; rx_data ; 1.000 ; 0.500 ; 11.000 ; +---------+-------------------------+----------------------+--------------------------+-------------+--------------+------------+------------+ +-------------------------------------------------------------------------------------------------------------------------------------------------------------+ ; Removal: 'm706:m706|clock_scale[2]' ; +--------+--------------------------+--------------------------+--------------------------+--------------------------+--------------+------------+------------+ ; Slack ; From Node ; To Node ; Launch Clock ; Latch Clock ; Relationship ; Clock Skew ; Data Delay ; +--------+--------------------------+--------------------------+--------------------------+--------------------------+--------------+------------+------------+ ; -8.000 ; m706:m706|in_last_unit ; m706:m706|spike_detector ; m706:m706|in_last_unit ; m706:m706|clock_scale[2] ; 0.000 ; 11.000 ; 8.000 ; ; -8.000 ; m706:m706|in_active ; m706:m706|spike_detector ; m706:m706|in_active ; m706:m706|clock_scale[2] ; 0.000 ; 11.000 ; 8.000 ; ; -7.500 ; m706:m706|in_last_unit ; m706:m706|spike_detector ; m706:m706|in_last_unit ; m706:m706|clock_scale[2] ; -0.500 ; 11.000 ; 8.000 ; ; -7.500 ; rx_rate ; m706:m706|spike_detector ; rx_rate ; m706:m706|clock_scale[2] ; 0.000 ; 11.000 ; 6.500 ; ; -7.500 ; m706:m706|in_active ; m706:m706|spike_detector ; m706:m706|in_active ; m706:m706|clock_scale[2] ; -0.500 ; 11.000 ; 8.000 ; ; -7.500 ; rx_data ; m706:m706|spike_detector ; rx_data ; m706:m706|clock_scale[2] ; 0.000 ; 11.000 ; 6.500 ; ; -7.000 ; rx_rate ; m706:m706|spike_detector ; rx_rate ; m706:m706|clock_scale[2] ; -0.500 ; 11.000 ; 6.500 ; ; -7.000 ; rx_data ; m706:m706|spike_detector ; rx_data ; m706:m706|clock_scale[2] ; -0.500 ; 11.000 ; 6.500 ; ; -5.000 ; m706:m706|in_last_unit ; m706:m706|in_active ; m706:m706|in_last_unit ; m706:m706|clock_scale[2] ; 0.000 ; 11.000 ; 11.000 ; ; -5.000 ; m706:m706|in_active ; m706:m706|in_active ; m706:m706|in_active ; m706:m706|clock_scale[2] ; 0.000 ; 11.000 ; 11.000 ; ; -4.500 ; m706:m706|in_last_unit ; m706:m706|in_active ; m706:m706|in_last_unit ; m706:m706|clock_scale[2] ; -0.500 ; 11.000 ; 11.000 ; ; -4.500 ; rx_rate ; m706:m706|in_active ; rx_rate ; m706:m706|clock_scale[2] ; 0.000 ; 11.000 ; 9.500 ; ; -4.500 ; m706:m706|in_active ; m706:m706|in_active ; m706:m706|in_active ; m706:m706|clock_scale[2] ; -0.500 ; 11.000 ; 11.000 ; ; -4.500 ; rx_data ; m706:m706|in_active ; rx_data ; m706:m706|clock_scale[2] ; 0.000 ; 11.000 ; 9.500 ; ; -4.000 ; rx_rate ; m706:m706|in_active ; rx_rate ; m706:m706|clock_scale[2] ; -0.500 ; 11.000 ; 9.500 ; ; -4.000 ; rx_data ; m706:m706|in_active ; rx_data ; m706:m706|clock_scale[2] ; -0.500 ; 11.000 ; 9.500 ; ; 0.000 ; m706:m706|in_last_unit ; m706:m706|in_stop[1] ; m706:m706|in_last_unit ; m706:m706|clock_scale[2] ; 0.000 ; 6.000 ; 11.000 ; ; 0.000 ; m706:m706|in_last_unit ; m706:m706|in_stop[2] ; m706:m706|in_last_unit ; m706:m706|clock_scale[2] ; 0.000 ; 6.000 ; 11.000 ; ; 0.000 ; m706:m706|in_last_unit ; m706:m706|tti37[7] ; m706:m706|in_last_unit ; m706:m706|clock_scale[2] ; 0.000 ; 6.000 ; 11.000 ; ; 0.000 ; m706:m706|in_last_unit ; m706:m706|tti37[6] ; m706:m706|in_last_unit ; m706:m706|clock_scale[2] ; 0.000 ; 6.000 ; 11.000 ; ; 0.000 ; m706:m706|in_last_unit ; m706:m706|tti37[5] ; m706:m706|in_last_unit ; m706:m706|clock_scale[2] ; 0.000 ; 6.000 ; 11.000 ; ; 0.000 ; m706:m706|in_last_unit ; m706:m706|tti37[4] ; m706:m706|in_last_unit ; m706:m706|clock_scale[2] ; 0.000 ; 6.000 ; 11.000 ; ; 0.000 ; m706:m706|in_last_unit ; m706:m706|tti37[3] ; m706:m706|in_last_unit ; m706:m706|clock_scale[2] ; 0.000 ; 6.000 ; 11.000 ; ; 0.000 ; m706:m706|in_last_unit ; m706:m706|tti02[2] ; m706:m706|in_last_unit ; m706:m706|clock_scale[2] ; 0.000 ; 6.000 ; 11.000 ; ; 0.000 ; m706:m706|in_last_unit ; m706:m706|tti02[1] ; m706:m706|in_last_unit ; m706:m706|clock_scale[2] ; 0.000 ; 6.000 ; 11.000 ; ; 0.000 ; m706:m706|in_last_unit ; m706:m706|tti02[0] ; m706:m706|in_last_unit ; m706:m706|clock_scale[2] ; 0.000 ; 6.000 ; 11.000 ; ; 0.000 ; m706:m706|in_active ; m706:m706|in_stop[1] ; m706:m706|in_active ; m706:m706|clock_scale[2] ; 0.000 ; 6.000 ; 11.000 ; ; 0.000 ; m706:m706|in_active ; m706:m706|in_stop[2] ; m706:m706|in_active ; m706:m706|clock_scale[2] ; 0.000 ; 6.000 ; 11.000 ; ; 0.000 ; m706:m706|in_active ; m706:m706|tti37[7] ; m706:m706|in_active ; m706:m706|clock_scale[2] ; 0.000 ; 6.000 ; 11.000 ; ; 0.000 ; m706:m706|in_active ; m706:m706|tti37[6] ; m706:m706|in_active ; m706:m706|clock_scale[2] ; 0.000 ; 6.000 ; 11.000 ; ; 0.000 ; m706:m706|in_active ; m706:m706|tti37[5] ; m706:m706|in_active ; m706:m706|clock_scale[2] ; 0.000 ; 6.000 ; 11.000 ; ; 0.000 ; m706:m706|in_active ; m706:m706|tti37[4] ; m706:m706|in_active ; m706:m706|clock_scale[2] ; 0.000 ; 6.000 ; 11.000 ; ; 0.000 ; m706:m706|in_active ; m706:m706|tti37[3] ; m706:m706|in_active ; m706:m706|clock_scale[2] ; 0.000 ; 6.000 ; 11.000 ; ; 0.000 ; m706:m706|in_active ; m706:m706|tti02[2] ; m706:m706|in_active ; m706:m706|clock_scale[2] ; 0.000 ; 6.000 ; 11.000 ; ; 0.000 ; m706:m706|in_active ; m706:m706|tti02[1] ; m706:m706|in_active ; m706:m706|clock_scale[2] ; 0.000 ; 6.000 ; 11.000 ; ; 0.000 ; m706:m706|in_active ; m706:m706|tti02[0] ; m706:m706|in_active ; m706:m706|clock_scale[2] ; 0.000 ; 6.000 ; 11.000 ; ; 0.500 ; m706:m706|in_last_unit ; m706:m706|in_stop[1] ; m706:m706|in_last_unit ; m706:m706|clock_scale[2] ; -0.500 ; 6.000 ; 11.000 ; ; 0.500 ; m706:m706|in_last_unit ; m706:m706|in_stop[2] ; m706:m706|in_last_unit ; m706:m706|clock_scale[2] ; -0.500 ; 6.000 ; 11.000 ; ; 0.500 ; m706:m706|in_last_unit ; m706:m706|tti37[7] ; m706:m706|in_last_unit ; m706:m706|clock_scale[2] ; -0.500 ; 6.000 ; 11.000 ; ; 0.500 ; m706:m706|in_last_unit ; m706:m706|tti37[6] ; m706:m706|in_last_unit ; m706:m706|clock_scale[2] ; -0.500 ; 6.000 ; 11.000 ; ; 0.500 ; m706:m706|in_last_unit ; m706:m706|tti37[5] ; m706:m706|in_last_unit ; m706:m706|clock_scale[2] ; -0.500 ; 6.000 ; 11.000 ; ; 0.500 ; m706:m706|in_last_unit ; m706:m706|tti37[4] ; m706:m706|in_last_unit ; m706:m706|clock_scale[2] ; -0.500 ; 6.000 ; 11.000 ; ; 0.500 ; m706:m706|in_last_unit ; m706:m706|tti37[3] ; m706:m706|in_last_unit ; m706:m706|clock_scale[2] ; -0.500 ; 6.000 ; 11.000 ; ; 0.500 ; m706:m706|in_last_unit ; m706:m706|tti02[2] ; m706:m706|in_last_unit ; m706:m706|clock_scale[2] ; -0.500 ; 6.000 ; 11.000 ; ; 0.500 ; m706:m706|in_last_unit ; m706:m706|tti02[1] ; m706:m706|in_last_unit ; m706:m706|clock_scale[2] ; -0.500 ; 6.000 ; 11.000 ; ; 0.500 ; m706:m706|in_last_unit ; m706:m706|tti02[0] ; m706:m706|in_last_unit ; m706:m706|clock_scale[2] ; -0.500 ; 6.000 ; 11.000 ; ; 0.500 ; rx_rate ; m706:m706|in_stop[1] ; rx_rate ; m706:m706|clock_scale[2] ; 0.000 ; 6.000 ; 9.500 ; ; 0.500 ; rx_rate ; m706:m706|in_stop[2] ; rx_rate ; m706:m706|clock_scale[2] ; 0.000 ; 6.000 ; 9.500 ; ; 0.500 ; rx_rate ; m706:m706|tti37[7] ; rx_rate ; m706:m706|clock_scale[2] ; 0.000 ; 6.000 ; 9.500 ; ; 0.500 ; rx_rate ; m706:m706|tti37[6] ; rx_rate ; m706:m706|clock_scale[2] ; 0.000 ; 6.000 ; 9.500 ; ; 0.500 ; rx_rate ; m706:m706|tti37[5] ; rx_rate ; m706:m706|clock_scale[2] ; 0.000 ; 6.000 ; 9.500 ; ; 0.500 ; rx_rate ; m706:m706|tti37[4] ; rx_rate ; m706:m706|clock_scale[2] ; 0.000 ; 6.000 ; 9.500 ; ; 0.500 ; rx_rate ; m706:m706|tti37[3] ; rx_rate ; m706:m706|clock_scale[2] ; 0.000 ; 6.000 ; 9.500 ; ; 0.500 ; rx_rate ; m706:m706|tti02[2] ; rx_rate ; m706:m706|clock_scale[2] ; 0.000 ; 6.000 ; 9.500 ; ; 0.500 ; rx_rate ; m706:m706|tti02[1] ; rx_rate ; m706:m706|clock_scale[2] ; 0.000 ; 6.000 ; 9.500 ; ; 0.500 ; rx_rate ; m706:m706|tti02[0] ; rx_rate ; m706:m706|clock_scale[2] ; 0.000 ; 6.000 ; 9.500 ; ; 0.500 ; m706:m706|in_active ; m706:m706|in_stop[1] ; m706:m706|in_active ; m706:m706|clock_scale[2] ; -0.500 ; 6.000 ; 11.000 ; ; 0.500 ; m706:m706|in_active ; m706:m706|in_stop[2] ; m706:m706|in_active ; m706:m706|clock_scale[2] ; -0.500 ; 6.000 ; 11.000 ; ; 0.500 ; m706:m706|in_active ; m706:m706|tti37[7] ; m706:m706|in_active ; m706:m706|clock_scale[2] ; -0.500 ; 6.000 ; 11.000 ; ; 0.500 ; m706:m706|in_active ; m706:m706|tti37[6] ; m706:m706|in_active ; m706:m706|clock_scale[2] ; -0.500 ; 6.000 ; 11.000 ; ; 0.500 ; m706:m706|in_active ; m706:m706|tti37[5] ; m706:m706|in_active ; m706:m706|clock_scale[2] ; -0.500 ; 6.000 ; 11.000 ; ; 0.500 ; m706:m706|in_active ; m706:m706|tti37[4] ; m706:m706|in_active ; m706:m706|clock_scale[2] ; -0.500 ; 6.000 ; 11.000 ; ; 0.500 ; m706:m706|in_active ; m706:m706|tti37[3] ; m706:m706|in_active ; m706:m706|clock_scale[2] ; -0.500 ; 6.000 ; 11.000 ; ; 0.500 ; m706:m706|in_active ; m706:m706|tti02[2] ; m706:m706|in_active ; m706:m706|clock_scale[2] ; -0.500 ; 6.000 ; 11.000 ; ; 0.500 ; m706:m706|in_active ; m706:m706|tti02[1] ; m706:m706|in_active ; m706:m706|clock_scale[2] ; -0.500 ; 6.000 ; 11.000 ; ; 0.500 ; m706:m706|in_active ; m706:m706|tti02[0] ; m706:m706|in_active ; m706:m706|clock_scale[2] ; -0.500 ; 6.000 ; 11.000 ; ; 0.500 ; rx_data ; m706:m706|in_stop[1] ; rx_data ; m706:m706|clock_scale[2] ; 0.000 ; 6.000 ; 9.500 ; ; 0.500 ; rx_data ; m706:m706|in_stop[2] ; rx_data ; m706:m706|clock_scale[2] ; 0.000 ; 6.000 ; 9.500 ; ; 0.500 ; rx_data ; m706:m706|tti37[7] ; rx_data ; m706:m706|clock_scale[2] ; 0.000 ; 6.000 ; 9.500 ; ; 0.500 ; rx_data ; m706:m706|tti37[6] ; rx_data ; m706:m706|clock_scale[2] ; 0.000 ; 6.000 ; 9.500 ; ; 0.500 ; rx_data ; m706:m706|tti37[5] ; rx_data ; m706:m706|clock_scale[2] ; 0.000 ; 6.000 ; 9.500 ; ; 0.500 ; rx_data ; m706:m706|tti37[4] ; rx_data ; m706:m706|clock_scale[2] ; 0.000 ; 6.000 ; 9.500 ; ; 0.500 ; rx_data ; m706:m706|tti37[3] ; rx_data ; m706:m706|clock_scale[2] ; 0.000 ; 6.000 ; 9.500 ; ; 0.500 ; rx_data ; m706:m706|tti02[2] ; rx_data ; m706:m706|clock_scale[2] ; 0.000 ; 6.000 ; 9.500 ; ; 0.500 ; rx_data ; m706:m706|tti02[1] ; rx_data ; m706:m706|clock_scale[2] ; 0.000 ; 6.000 ; 9.500 ; ; 0.500 ; rx_data ; m706:m706|tti02[0] ; rx_data ; m706:m706|clock_scale[2] ; 0.000 ; 6.000 ; 9.500 ; ; 1.000 ; rx_rate ; m706:m706|in_stop[1] ; rx_rate ; m706:m706|clock_scale[2] ; -0.500 ; 6.000 ; 9.500 ; ; 1.000 ; rx_rate ; m706:m706|in_stop[2] ; rx_rate ; m706:m706|clock_scale[2] ; -0.500 ; 6.000 ; 9.500 ; ; 1.000 ; rx_rate ; m706:m706|tti37[7] ; rx_rate ; m706:m706|clock_scale[2] ; -0.500 ; 6.000 ; 9.500 ; ; 1.000 ; rx_rate ; m706:m706|tti37[6] ; rx_rate ; m706:m706|clock_scale[2] ; -0.500 ; 6.000 ; 9.500 ; ; 1.000 ; rx_rate ; m706:m706|tti37[5] ; rx_rate ; m706:m706|clock_scale[2] ; -0.500 ; 6.000 ; 9.500 ; ; 1.000 ; rx_rate ; m706:m706|tti37[4] ; rx_rate ; m706:m706|clock_scale[2] ; -0.500 ; 6.000 ; 9.500 ; ; 1.000 ; rx_rate ; m706:m706|tti37[3] ; rx_rate ; m706:m706|clock_scale[2] ; -0.500 ; 6.000 ; 9.500 ; ; 1.000 ; rx_rate ; m706:m706|tti02[2] ; rx_rate ; m706:m706|clock_scale[2] ; -0.500 ; 6.000 ; 9.500 ; ; 1.000 ; rx_rate ; m706:m706|tti02[1] ; rx_rate ; m706:m706|clock_scale[2] ; -0.500 ; 6.000 ; 9.500 ; ; 1.000 ; rx_rate ; m706:m706|tti02[0] ; rx_rate ; m706:m706|clock_scale[2] ; -0.500 ; 6.000 ; 9.500 ; ; 1.000 ; rx_data ; m706:m706|in_stop[1] ; rx_data ; m706:m706|clock_scale[2] ; -0.500 ; 6.000 ; 9.500 ; ; 1.000 ; rx_data ; m706:m706|in_stop[2] ; rx_data ; m706:m706|clock_scale[2] ; -0.500 ; 6.000 ; 9.500 ; ; 1.000 ; rx_data ; m706:m706|tti37[7] ; rx_data ; m706:m706|clock_scale[2] ; -0.500 ; 6.000 ; 9.500 ; ; 1.000 ; rx_data ; m706:m706|tti37[6] ; rx_data ; m706:m706|clock_scale[2] ; -0.500 ; 6.000 ; 9.500 ; ; 1.000 ; rx_data ; m706:m706|tti37[5] ; rx_data ; m706:m706|clock_scale[2] ; -0.500 ; 6.000 ; 9.500 ; ; 1.000 ; rx_data ; m706:m706|tti37[4] ; rx_data ; m706:m706|clock_scale[2] ; -0.500 ; 6.000 ; 9.500 ; ; 1.000 ; rx_data ; m706:m706|tti37[3] ; rx_data ; m706:m706|clock_scale[2] ; -0.500 ; 6.000 ; 9.500 ; ; 1.000 ; rx_data ; m706:m706|tti02[2] ; rx_data ; m706:m706|clock_scale[2] ; -0.500 ; 6.000 ; 9.500 ; ; 1.000 ; rx_data ; m706:m706|tti02[1] ; rx_data ; m706:m706|clock_scale[2] ; -0.500 ; 6.000 ; 9.500 ; ; 1.000 ; rx_data ; m706:m706|tti02[0] ; rx_data ; m706:m706|clock_scale[2] ; -0.500 ; 6.000 ; 9.500 ; ; 5.000 ; m706:m706|clock_scale[2] ; m706:m706|in_active ; m706:m706|clock_scale[2] ; m706:m706|clock_scale[2] ; 0.000 ; 11.000 ; 21.000 ; ; 5.500 ; m706:m706|clock_scale[2] ; m706:m706|in_active ; m706:m706|clock_scale[2] ; m706:m706|clock_scale[2] ; -0.500 ; 11.000 ; 21.000 ; ; 8.000 ; m706:m706|in_stop[2] ; m706:m706|in_last_unit ; m706:m706|clock_scale[2] ; m706:m706|clock_scale[2] ; 0.000 ; 0.000 ; 11.000 ; ; 18.500 ; m706:m706|spike_detector ; m706:m706|in_active ; m706:m706|clock_scale[2] ; m706:m706|clock_scale[2] ; -0.500 ; 0.000 ; 21.000 ; +--------+--------------------------+--------------------------+--------------------------+--------------------------+--------------+------------+------------+ +-------------------------------------------------------------------------------------------------------------------------------------------------------+ ; Removal: 'm706:m706|in_active' ; +--------+-------------------------+--------------------------+--------------------------+---------------------+--------------+------------+------------+ ; Slack ; From Node ; To Node ; Launch Clock ; Latch Clock ; Relationship ; Clock Skew ; Data Delay ; +--------+-------------------------+--------------------------+--------------------------+---------------------+--------------+------------+------------+ ; -8.000 ; m706:m706|in_last_unit ; m706:m706|spike_detector ; m706:m706|in_last_unit ; m706:m706|in_active ; 0.000 ; 11.000 ; 8.000 ; ; -8.000 ; m706:m706|in_active ; m706:m706|spike_detector ; m706:m706|in_active ; m706:m706|in_active ; 0.000 ; 11.000 ; 8.000 ; ; -7.500 ; m706:m706|in_last_unit ; m706:m706|spike_detector ; m706:m706|in_last_unit ; m706:m706|in_active ; -0.500 ; 11.000 ; 8.000 ; ; -7.500 ; rx_rate ; m706:m706|spike_detector ; rx_rate ; m706:m706|in_active ; 0.000 ; 11.000 ; 6.500 ; ; -7.500 ; m706:m706|in_active ; m706:m706|spike_detector ; m706:m706|in_active ; m706:m706|in_active ; -0.500 ; 11.000 ; 8.000 ; ; -7.500 ; rx_data ; m706:m706|spike_detector ; rx_data ; m706:m706|in_active ; 0.000 ; 11.000 ; 6.500 ; ; -7.000 ; rx_rate ; m706:m706|spike_detector ; rx_rate ; m706:m706|in_active ; -0.500 ; 11.000 ; 6.500 ; ; -7.000 ; rx_data ; m706:m706|spike_detector ; rx_data ; m706:m706|in_active ; -0.500 ; 11.000 ; 6.500 ; ; 0.000 ; m706:m706|in_last_unit ; m706:m706|tti37[7] ; m706:m706|in_last_unit ; m706:m706|in_active ; 0.000 ; 6.000 ; 11.000 ; ; 0.000 ; m706:m706|in_last_unit ; m706:m706|tti37[6] ; m706:m706|in_last_unit ; m706:m706|in_active ; 0.000 ; 6.000 ; 11.000 ; ; 0.000 ; m706:m706|in_last_unit ; m706:m706|tti37[5] ; m706:m706|in_last_unit ; m706:m706|in_active ; 0.000 ; 6.000 ; 11.000 ; ; 0.000 ; m706:m706|in_last_unit ; m706:m706|tti37[4] ; m706:m706|in_last_unit ; m706:m706|in_active ; 0.000 ; 6.000 ; 11.000 ; ; 0.000 ; m706:m706|in_last_unit ; m706:m706|tti37[3] ; m706:m706|in_last_unit ; m706:m706|in_active ; 0.000 ; 6.000 ; 11.000 ; ; 0.000 ; m706:m706|in_last_unit ; m706:m706|tti02[2] ; m706:m706|in_last_unit ; m706:m706|in_active ; 0.000 ; 6.000 ; 11.000 ; ; 0.000 ; m706:m706|in_last_unit ; m706:m706|tti02[1] ; m706:m706|in_last_unit ; m706:m706|in_active ; 0.000 ; 6.000 ; 11.000 ; ; 0.000 ; m706:m706|in_last_unit ; m706:m706|tti02[0] ; m706:m706|in_last_unit ; m706:m706|in_active ; 0.000 ; 6.000 ; 11.000 ; ; 0.000 ; m706:m706|in_active ; m706:m706|tti37[7] ; m706:m706|in_active ; m706:m706|in_active ; 0.000 ; 6.000 ; 11.000 ; ; 0.000 ; m706:m706|in_active ; m706:m706|tti37[6] ; m706:m706|in_active ; m706:m706|in_active ; 0.000 ; 6.000 ; 11.000 ; ; 0.000 ; m706:m706|in_active ; m706:m706|tti37[5] ; m706:m706|in_active ; m706:m706|in_active ; 0.000 ; 6.000 ; 11.000 ; ; 0.000 ; m706:m706|in_active ; m706:m706|tti37[4] ; m706:m706|in_active ; m706:m706|in_active ; 0.000 ; 6.000 ; 11.000 ; ; 0.000 ; m706:m706|in_active ; m706:m706|tti37[3] ; m706:m706|in_active ; m706:m706|in_active ; 0.000 ; 6.000 ; 11.000 ; ; 0.000 ; m706:m706|in_active ; m706:m706|tti02[2] ; m706:m706|in_active ; m706:m706|in_active ; 0.000 ; 6.000 ; 11.000 ; ; 0.000 ; m706:m706|in_active ; m706:m706|tti02[1] ; m706:m706|in_active ; m706:m706|in_active ; 0.000 ; 6.000 ; 11.000 ; ; 0.000 ; m706:m706|in_active ; m706:m706|tti02[0] ; m706:m706|in_active ; m706:m706|in_active ; 0.000 ; 6.000 ; 11.000 ; ; 0.500 ; m706:m706|in_last_unit ; m706:m706|tti37[7] ; m706:m706|in_last_unit ; m706:m706|in_active ; -0.500 ; 6.000 ; 11.000 ; ; 0.500 ; m706:m706|in_last_unit ; m706:m706|tti37[6] ; m706:m706|in_last_unit ; m706:m706|in_active ; -0.500 ; 6.000 ; 11.000 ; ; 0.500 ; m706:m706|in_last_unit ; m706:m706|tti37[5] ; m706:m706|in_last_unit ; m706:m706|in_active ; -0.500 ; 6.000 ; 11.000 ; ; 0.500 ; m706:m706|in_last_unit ; m706:m706|tti37[4] ; m706:m706|in_last_unit ; m706:m706|in_active ; -0.500 ; 6.000 ; 11.000 ; ; 0.500 ; m706:m706|in_last_unit ; m706:m706|tti37[3] ; m706:m706|in_last_unit ; m706:m706|in_active ; -0.500 ; 6.000 ; 11.000 ; ; 0.500 ; m706:m706|in_last_unit ; m706:m706|tti02[2] ; m706:m706|in_last_unit ; m706:m706|in_active ; -0.500 ; 6.000 ; 11.000 ; ; 0.500 ; m706:m706|in_last_unit ; m706:m706|tti02[1] ; m706:m706|in_last_unit ; m706:m706|in_active ; -0.500 ; 6.000 ; 11.000 ; ; 0.500 ; m706:m706|in_last_unit ; m706:m706|tti02[0] ; m706:m706|in_last_unit ; m706:m706|in_active ; -0.500 ; 6.000 ; 11.000 ; ; 0.500 ; rx_rate ; m706:m706|tti37[7] ; rx_rate ; m706:m706|in_active ; 0.000 ; 6.000 ; 9.500 ; ; 0.500 ; rx_rate ; m706:m706|tti37[6] ; rx_rate ; m706:m706|in_active ; 0.000 ; 6.000 ; 9.500 ; ; 0.500 ; rx_rate ; m706:m706|tti37[5] ; rx_rate ; m706:m706|in_active ; 0.000 ; 6.000 ; 9.500 ; ; 0.500 ; rx_rate ; m706:m706|tti37[4] ; rx_rate ; m706:m706|in_active ; 0.000 ; 6.000 ; 9.500 ; ; 0.500 ; rx_rate ; m706:m706|tti37[3] ; rx_rate ; m706:m706|in_active ; 0.000 ; 6.000 ; 9.500 ; ; 0.500 ; rx_rate ; m706:m706|tti02[2] ; rx_rate ; m706:m706|in_active ; 0.000 ; 6.000 ; 9.500 ; ; 0.500 ; rx_rate ; m706:m706|tti02[1] ; rx_rate ; m706:m706|in_active ; 0.000 ; 6.000 ; 9.500 ; ; 0.500 ; rx_rate ; m706:m706|tti02[0] ; rx_rate ; m706:m706|in_active ; 0.000 ; 6.000 ; 9.500 ; ; 0.500 ; m706:m706|in_active ; m706:m706|tti37[7] ; m706:m706|in_active ; m706:m706|in_active ; -0.500 ; 6.000 ; 11.000 ; ; 0.500 ; m706:m706|in_active ; m706:m706|tti37[6] ; m706:m706|in_active ; m706:m706|in_active ; -0.500 ; 6.000 ; 11.000 ; ; 0.500 ; m706:m706|in_active ; m706:m706|tti37[5] ; m706:m706|in_active ; m706:m706|in_active ; -0.500 ; 6.000 ; 11.000 ; ; 0.500 ; m706:m706|in_active ; m706:m706|tti37[4] ; m706:m706|in_active ; m706:m706|in_active ; -0.500 ; 6.000 ; 11.000 ; ; 0.500 ; m706:m706|in_active ; m706:m706|tti37[3] ; m706:m706|in_active ; m706:m706|in_active ; -0.500 ; 6.000 ; 11.000 ; ; 0.500 ; m706:m706|in_active ; m706:m706|tti02[2] ; m706:m706|in_active ; m706:m706|in_active ; -0.500 ; 6.000 ; 11.000 ; ; 0.500 ; m706:m706|in_active ; m706:m706|tti02[1] ; m706:m706|in_active ; m706:m706|in_active ; -0.500 ; 6.000 ; 11.000 ; ; 0.500 ; m706:m706|in_active ; m706:m706|tti02[0] ; m706:m706|in_active ; m706:m706|in_active ; -0.500 ; 6.000 ; 11.000 ; ; 0.500 ; rx_data ; m706:m706|tti37[7] ; rx_data ; m706:m706|in_active ; 0.000 ; 6.000 ; 9.500 ; ; 0.500 ; rx_data ; m706:m706|tti37[6] ; rx_data ; m706:m706|in_active ; 0.000 ; 6.000 ; 9.500 ; ; 0.500 ; rx_data ; m706:m706|tti37[5] ; rx_data ; m706:m706|in_active ; 0.000 ; 6.000 ; 9.500 ; ; 0.500 ; rx_data ; m706:m706|tti37[4] ; rx_data ; m706:m706|in_active ; 0.000 ; 6.000 ; 9.500 ; ; 0.500 ; rx_data ; m706:m706|tti37[3] ; rx_data ; m706:m706|in_active ; 0.000 ; 6.000 ; 9.500 ; ; 0.500 ; rx_data ; m706:m706|tti02[2] ; rx_data ; m706:m706|in_active ; 0.000 ; 6.000 ; 9.500 ; ; 0.500 ; rx_data ; m706:m706|tti02[1] ; rx_data ; m706:m706|in_active ; 0.000 ; 6.000 ; 9.500 ; ; 0.500 ; rx_data ; m706:m706|tti02[0] ; rx_data ; m706:m706|in_active ; 0.000 ; 6.000 ; 9.500 ; ; 1.000 ; rx_rate ; m706:m706|tti37[7] ; rx_rate ; m706:m706|in_active ; -0.500 ; 6.000 ; 9.500 ; ; 1.000 ; rx_rate ; m706:m706|tti37[6] ; rx_rate ; m706:m706|in_active ; -0.500 ; 6.000 ; 9.500 ; ; 1.000 ; rx_rate ; m706:m706|tti37[5] ; rx_rate ; m706:m706|in_active ; -0.500 ; 6.000 ; 9.500 ; ; 1.000 ; rx_rate ; m706:m706|tti37[4] ; rx_rate ; m706:m706|in_active ; -0.500 ; 6.000 ; 9.500 ; ; 1.000 ; rx_rate ; m706:m706|tti37[3] ; rx_rate ; m706:m706|in_active ; -0.500 ; 6.000 ; 9.500 ; ; 1.000 ; rx_rate ; m706:m706|tti02[2] ; rx_rate ; m706:m706|in_active ; -0.500 ; 6.000 ; 9.500 ; ; 1.000 ; rx_rate ; m706:m706|tti02[1] ; rx_rate ; m706:m706|in_active ; -0.500 ; 6.000 ; 9.500 ; ; 1.000 ; rx_rate ; m706:m706|tti02[0] ; rx_rate ; m706:m706|in_active ; -0.500 ; 6.000 ; 9.500 ; ; 1.000 ; rx_data ; m706:m706|tti37[7] ; rx_data ; m706:m706|in_active ; -0.500 ; 6.000 ; 9.500 ; ; 1.000 ; rx_data ; m706:m706|tti37[6] ; rx_data ; m706:m706|in_active ; -0.500 ; 6.000 ; 9.500 ; ; 1.000 ; rx_data ; m706:m706|tti37[5] ; rx_data ; m706:m706|in_active ; -0.500 ; 6.000 ; 9.500 ; ; 1.000 ; rx_data ; m706:m706|tti37[4] ; rx_data ; m706:m706|in_active ; -0.500 ; 6.000 ; 9.500 ; ; 1.000 ; rx_data ; m706:m706|tti37[3] ; rx_data ; m706:m706|in_active ; -0.500 ; 6.000 ; 9.500 ; ; 1.000 ; rx_data ; m706:m706|tti02[2] ; rx_data ; m706:m706|in_active ; -0.500 ; 6.000 ; 9.500 ; ; 1.000 ; rx_data ; m706:m706|tti02[1] ; rx_data ; m706:m706|in_active ; -0.500 ; 6.000 ; 9.500 ; ; 1.000 ; rx_data ; m706:m706|tti02[0] ; rx_data ; m706:m706|in_active ; -0.500 ; 6.000 ; 9.500 ; ; 8.000 ; m706:m706|keyboard_flag ; m706:m706|reader_run ; m706:m706|clock_scale[2] ; m706:m706|in_active ; 0.000 ; 0.000 ; 11.000 ; ; 8.000 ; m706:m706|in_stop[2] ; m706:m706|in_last_unit ; m706:m706|clock_scale[2] ; m706:m706|in_active ; 0.000 ; 0.000 ; 11.000 ; ; 8.000 ; m706:m706|keyboard_flag ; m706:m706|reader_run ; m706:m706|in_active ; m706:m706|in_active ; 0.000 ; 0.000 ; 11.000 ; +--------+-------------------------+--------------------------+--------------------------+---------------------+--------------+------------+------------+ +-------------------------------------------------------------------------------------------------------------------------------------------------------+ ; Removal: 'm706:m706|in_last_unit' ; +--------+--------------------------+----------------------+--------------------------+------------------------+--------------+------------+------------+ ; Slack ; From Node ; To Node ; Launch Clock ; Latch Clock ; Relationship ; Clock Skew ; Data Delay ; +--------+--------------------------+----------------------+--------------------------+------------------------+--------------+------------+------------+ ; 0.000 ; m706:m706|in_last_unit ; m706:m706|in_active ; m706:m706|in_last_unit ; m706:m706|in_last_unit ; 0.000 ; 6.000 ; 11.000 ; ; 0.000 ; m706:m706|in_active ; m706:m706|in_active ; m706:m706|in_active ; m706:m706|in_last_unit ; 0.000 ; 6.000 ; 11.000 ; ; 0.500 ; m706:m706|in_last_unit ; m706:m706|in_active ; m706:m706|in_last_unit ; m706:m706|in_last_unit ; -0.500 ; 6.000 ; 11.000 ; ; 0.500 ; rx_rate ; m706:m706|in_active ; rx_rate ; m706:m706|in_last_unit ; 0.000 ; 6.000 ; 9.500 ; ; 0.500 ; m706:m706|in_active ; m706:m706|in_active ; m706:m706|in_active ; m706:m706|in_last_unit ; -0.500 ; 6.000 ; 11.000 ; ; 0.500 ; rx_data ; m706:m706|in_active ; rx_data ; m706:m706|in_last_unit ; 0.000 ; 6.000 ; 9.500 ; ; 1.000 ; rx_rate ; m706:m706|in_active ; rx_rate ; m706:m706|in_last_unit ; -0.500 ; 6.000 ; 9.500 ; ; 1.000 ; rx_data ; m706:m706|in_active ; rx_data ; m706:m706|in_last_unit ; -0.500 ; 6.000 ; 9.500 ; ; 8.000 ; m706:m706|keyboard_flag ; m706:m706|reader_run ; m706:m706|clock_scale[2] ; m706:m706|in_last_unit ; 0.000 ; 0.000 ; 11.000 ; ; 8.000 ; m706:m706|keyboard_flag ; m706:m706|reader_run ; m706:m706|in_active ; m706:m706|in_last_unit ; 0.000 ; 0.000 ; 11.000 ; ; 10.000 ; m706:m706|clock_scale[2] ; m706:m706|in_active ; m706:m706|clock_scale[2] ; m706:m706|in_last_unit ; 0.000 ; 6.000 ; 21.000 ; ; 10.500 ; m706:m706|clock_scale[2] ; m706:m706|in_active ; m706:m706|clock_scale[2] ; m706:m706|in_last_unit ; -0.500 ; 6.000 ; 21.000 ; ; 23.500 ; m706:m706|spike_detector ; m706:m706|in_active ; m706:m706|clock_scale[2] ; m706:m706|in_last_unit ; -0.500 ; -5.000 ; 21.000 ; ; 23.500 ; m706:m706|spike_detector ; m706:m706|in_active ; m706:m706|in_active ; m706:m706|in_last_unit ; -0.500 ; -5.000 ; 21.000 ; +--------+--------------------------+----------------------+--------------------------+------------------------+--------------+------------+------------+ +----------------------------------------------------------------------------------------------------------------------------------------------+ ; Removal: 'rx_rate' ; +-------+-------------------------+--------------------------+--------------------------+-------------+--------------+------------+------------+ ; Slack ; From Node ; To Node ; Launch Clock ; Latch Clock ; Relationship ; Clock Skew ; Data Delay ; +-------+-------------------------+--------------------------+--------------------------+-------------+--------------+------------+------------+ ; 4.500 ; m706:m706|in_last_unit ; m706:m706|clock_scale[0] ; m706:m706|in_last_unit ; rx_rate ; 0.000 ; 1.500 ; 11.000 ; ; 4.500 ; m706:m706|in_last_unit ; m706:m706|clock_scale[1] ; m706:m706|in_last_unit ; rx_rate ; 0.000 ; 1.500 ; 11.000 ; ; 4.500 ; m706:m706|in_last_unit ; m706:m706|clock_scale[2] ; m706:m706|in_last_unit ; rx_rate ; 0.000 ; 1.500 ; 11.000 ; ; 4.500 ; m706:m706|in_active ; m706:m706|clock_scale[0] ; m706:m706|in_active ; rx_rate ; 0.000 ; 1.500 ; 11.000 ; ; 4.500 ; m706:m706|in_active ; m706:m706|clock_scale[1] ; m706:m706|in_active ; rx_rate ; 0.000 ; 1.500 ; 11.000 ; ; 4.500 ; m706:m706|in_active ; m706:m706|clock_scale[2] ; m706:m706|in_active ; rx_rate ; 0.000 ; 1.500 ; 11.000 ; ; 5.000 ; m706:m706|in_last_unit ; m706:m706|clock_scale[0] ; m706:m706|in_last_unit ; rx_rate ; -0.500 ; 1.500 ; 11.000 ; ; 5.000 ; m706:m706|in_last_unit ; m706:m706|clock_scale[1] ; m706:m706|in_last_unit ; rx_rate ; -0.500 ; 1.500 ; 11.000 ; ; 5.000 ; m706:m706|in_last_unit ; m706:m706|clock_scale[2] ; m706:m706|in_last_unit ; rx_rate ; -0.500 ; 1.500 ; 11.000 ; ; 5.000 ; m706:m706|in_active ; m706:m706|clock_scale[0] ; m706:m706|in_active ; rx_rate ; -0.500 ; 1.500 ; 11.000 ; ; 5.000 ; m706:m706|in_active ; m706:m706|clock_scale[1] ; m706:m706|in_active ; rx_rate ; -0.500 ; 1.500 ; 11.000 ; ; 5.000 ; m706:m706|in_active ; m706:m706|clock_scale[2] ; m706:m706|in_active ; rx_rate ; -0.500 ; 1.500 ; 11.000 ; ; 7.500 ; m706:m706|keyboard_flag ; m706:m706|reader_run ; m706:m706|clock_scale[2] ; rx_rate ; 0.000 ; 0.500 ; 11.000 ; ; 7.500 ; m706:m706|keyboard_flag ; m706:m706|reader_run ; m706:m706|in_active ; rx_rate ; 0.000 ; 0.500 ; 11.000 ; +-------+-------------------------+--------------------------+--------------------------+-------------+--------------+------------+------------+ +------------------------------------------------------------------------------------------------------------------------------------------+ ; Removal: 'rx_data' ; +-------+-------------------------+----------------------+--------------------------+-------------+--------------+------------+------------+ ; Slack ; From Node ; To Node ; Launch Clock ; Latch Clock ; Relationship ; Clock Skew ; Data Delay ; +-------+-------------------------+----------------------+--------------------------+-------------+--------------+------------+------------+ ; 7.500 ; m706:m706|keyboard_flag ; m706:m706|reader_run ; m706:m706|clock_scale[2] ; rx_data ; 0.000 ; 0.500 ; 11.000 ; ; 7.500 ; m706:m706|keyboard_flag ; m706:m706|reader_run ; m706:m706|in_active ; rx_data ; 0.000 ; 0.500 ; 11.000 ; +-------+-------------------------+----------------------+--------------------------+-------------+--------------+------------+------------+ +---------------------------------------------------------------------------------------------------------------------------------+ ; Minimum Pulse Width: 'm706:m706|clock_scale[2]' ; +--------+--------------+----------------+------------------+--------------------------+------------+-----------------------------+ ; Slack ; Actual Width ; Required Width ; Type ; Clock ; Clock Edge ; Target ; +--------+--------------+----------------+------------------+--------------------------+------------+-----------------------------+ ; -3.500 ; 0.500 ; 4.000 ; High Pulse Width ; m706:m706|clock_scale[2] ; Rise ; m706:m706|in_active ; ; -3.500 ; 0.500 ; 4.000 ; Low Pulse Width ; m706:m706|clock_scale[2] ; Rise ; m706:m706|in_active ; ; -3.500 ; 0.500 ; 4.000 ; High Pulse Width ; m706:m706|clock_scale[2] ; Rise ; m706:m706|in_last_unit ; ; -3.500 ; 0.500 ; 4.000 ; Low Pulse Width ; m706:m706|clock_scale[2] ; Rise ; m706:m706|in_last_unit ; ; -3.500 ; 0.500 ; 4.000 ; High Pulse Width ; m706:m706|clock_scale[2] ; Rise ; m706:m706|in_stop[1] ; ; -3.500 ; 0.500 ; 4.000 ; Low Pulse Width ; m706:m706|clock_scale[2] ; Rise ; m706:m706|in_stop[1] ; ; -3.500 ; 0.500 ; 4.000 ; High Pulse Width ; m706:m706|clock_scale[2] ; Rise ; m706:m706|in_stop[2] ; ; -3.500 ; 0.500 ; 4.000 ; Low Pulse Width ; m706:m706|clock_scale[2] ; Rise ; m706:m706|in_stop[2] ; ; -3.500 ; 0.500 ; 4.000 ; High Pulse Width ; m706:m706|clock_scale[2] ; Rise ; m706:m706|keyboard_flag ; ; -3.500 ; 0.500 ; 4.000 ; Low Pulse Width ; m706:m706|clock_scale[2] ; Rise ; m706:m706|keyboard_flag ; ; -3.500 ; 0.500 ; 4.000 ; High Pulse Width ; m706:m706|clock_scale[2] ; Fall ; m706:m706|spike_detector ; ; -3.500 ; 0.500 ; 4.000 ; Low Pulse Width ; m706:m706|clock_scale[2] ; Fall ; m706:m706|spike_detector ; ; -3.500 ; 0.500 ; 4.000 ; High Pulse Width ; m706:m706|clock_scale[2] ; Rise ; m706:m706|tti02[0] ; ; -3.500 ; 0.500 ; 4.000 ; Low Pulse Width ; m706:m706|clock_scale[2] ; Rise ; m706:m706|tti02[0] ; ; -3.500 ; 0.500 ; 4.000 ; High Pulse Width ; m706:m706|clock_scale[2] ; Rise ; m706:m706|tti02[1] ; ; -3.500 ; 0.500 ; 4.000 ; Low Pulse Width ; m706:m706|clock_scale[2] ; Rise ; m706:m706|tti02[1] ; ; -3.500 ; 0.500 ; 4.000 ; High Pulse Width ; m706:m706|clock_scale[2] ; Rise ; m706:m706|tti02[2] ; ; -3.500 ; 0.500 ; 4.000 ; Low Pulse Width ; m706:m706|clock_scale[2] ; Rise ; m706:m706|tti02[2] ; ; -3.500 ; 0.500 ; 4.000 ; High Pulse Width ; m706:m706|clock_scale[2] ; Rise ; m706:m706|tti37[3] ; ; -3.500 ; 0.500 ; 4.000 ; Low Pulse Width ; m706:m706|clock_scale[2] ; Rise ; m706:m706|tti37[3] ; ; -3.500 ; 0.500 ; 4.000 ; High Pulse Width ; m706:m706|clock_scale[2] ; Rise ; m706:m706|tti37[4] ; ; -3.500 ; 0.500 ; 4.000 ; Low Pulse Width ; m706:m706|clock_scale[2] ; Rise ; m706:m706|tti37[4] ; ; -3.500 ; 0.500 ; 4.000 ; High Pulse Width ; m706:m706|clock_scale[2] ; Rise ; m706:m706|tti37[5] ; ; -3.500 ; 0.500 ; 4.000 ; Low Pulse Width ; m706:m706|clock_scale[2] ; Rise ; m706:m706|tti37[5] ; ; -3.500 ; 0.500 ; 4.000 ; High Pulse Width ; m706:m706|clock_scale[2] ; Rise ; m706:m706|tti37[6] ; ; -3.500 ; 0.500 ; 4.000 ; Low Pulse Width ; m706:m706|clock_scale[2] ; Rise ; m706:m706|tti37[6] ; ; -3.500 ; 0.500 ; 4.000 ; High Pulse Width ; m706:m706|clock_scale[2] ; Rise ; m706:m706|tti37[7] ; ; -3.500 ; 0.500 ; 4.000 ; Low Pulse Width ; m706:m706|clock_scale[2] ; Rise ; m706:m706|tti37[7] ; ; 0.500 ; 0.500 ; 0.000 ; High Pulse Width ; m706:m706|clock_scale[2] ; Rise ; m706|clock_scale[2]|dataout ; ; 0.500 ; 0.500 ; 0.000 ; Low Pulse Width ; m706:m706|clock_scale[2] ; Rise ; m706|clock_scale[2]|dataout ; ; 0.500 ; 0.500 ; 0.000 ; High Pulse Width ; m706:m706|clock_scale[2] ; Rise ; m706|in_active|[0] ; ; 0.500 ; 0.500 ; 0.000 ; Low Pulse Width ; m706:m706|clock_scale[2] ; Rise ; m706|in_active|[0] ; ; 0.500 ; 0.500 ; 0.000 ; High Pulse Width ; m706:m706|clock_scale[2] ; Rise ; m706|in_last_unit|[1] ; ; 0.500 ; 0.500 ; 0.000 ; Low Pulse Width ; m706:m706|clock_scale[2] ; Rise ; m706|in_last_unit|[1] ; ; 0.500 ; 0.500 ; 0.000 ; High Pulse Width ; m706:m706|clock_scale[2] ; Rise ; m706|in_stop[1]|[1] ; ; 0.500 ; 0.500 ; 0.000 ; Low Pulse Width ; m706:m706|clock_scale[2] ; Rise ; m706|in_stop[1]|[1] ; ; 0.500 ; 0.500 ; 0.000 ; High Pulse Width ; m706:m706|clock_scale[2] ; Rise ; m706|in_stop[2]|[1] ; ; 0.500 ; 0.500 ; 0.000 ; Low Pulse Width ; m706:m706|clock_scale[2] ; Rise ; m706|in_stop[2]|[1] ; ; 0.500 ; 0.500 ; 0.000 ; High Pulse Width ; m706:m706|clock_scale[2] ; Rise ; m706|keyboard_flag|[6] ; ; 0.500 ; 0.500 ; 0.000 ; Low Pulse Width ; m706:m706|clock_scale[2] ; Rise ; m706|keyboard_flag|[6] ; ; 0.500 ; 0.500 ; 0.000 ; High Pulse Width ; m706:m706|clock_scale[2] ; Rise ; m706|spike_detector|[0] ; ; 0.500 ; 0.500 ; 0.000 ; Low Pulse Width ; m706:m706|clock_scale[2] ; Rise ; m706|spike_detector|[0] ; ; 0.500 ; 0.500 ; 0.000 ; High Pulse Width ; m706:m706|clock_scale[2] ; Rise ; m706|tti02[0]|[1] ; ; 0.500 ; 0.500 ; 0.000 ; Low Pulse Width ; m706:m706|clock_scale[2] ; Rise ; m706|tti02[0]|[1] ; ; 0.500 ; 0.500 ; 0.000 ; High Pulse Width ; m706:m706|clock_scale[2] ; Rise ; m706|tti02[1]|[1] ; ; 0.500 ; 0.500 ; 0.000 ; Low Pulse Width ; m706:m706|clock_scale[2] ; Rise ; m706|tti02[1]|[1] ; ; 0.500 ; 0.500 ; 0.000 ; High Pulse Width ; m706:m706|clock_scale[2] ; Rise ; m706|tti02[2]|[1] ; ; 0.500 ; 0.500 ; 0.000 ; Low Pulse Width ; m706:m706|clock_scale[2] ; Rise ; m706|tti02[2]|[1] ; ; 0.500 ; 0.500 ; 0.000 ; High Pulse Width ; m706:m706|clock_scale[2] ; Rise ; m706|tti37[3]|[1] ; ; 0.500 ; 0.500 ; 0.000 ; Low Pulse Width ; m706:m706|clock_scale[2] ; Rise ; m706|tti37[3]|[1] ; ; 0.500 ; 0.500 ; 0.000 ; High Pulse Width ; m706:m706|clock_scale[2] ; Rise ; m706|tti37[4]|[1] ; ; 0.500 ; 0.500 ; 0.000 ; Low Pulse Width ; m706:m706|clock_scale[2] ; Rise ; m706|tti37[4]|[1] ; ; 0.500 ; 0.500 ; 0.000 ; High Pulse Width ; m706:m706|clock_scale[2] ; Rise ; m706|tti37[5]|[1] ; ; 0.500 ; 0.500 ; 0.000 ; Low Pulse Width ; m706:m706|clock_scale[2] ; Rise ; m706|tti37[5]|[1] ; ; 0.500 ; 0.500 ; 0.000 ; High Pulse Width ; m706:m706|clock_scale[2] ; Rise ; m706|tti37[6]|[1] ; ; 0.500 ; 0.500 ; 0.000 ; Low Pulse Width ; m706:m706|clock_scale[2] ; Rise ; m706|tti37[6]|[1] ; ; 0.500 ; 0.500 ; 0.000 ; High Pulse Width ; m706:m706|clock_scale[2] ; Rise ; m706|tti37[7]|[1] ; ; 0.500 ; 0.500 ; 0.000 ; Low Pulse Width ; m706:m706|clock_scale[2] ; Rise ; m706|tti37[7]|[1] ; ; 0.500 ; 0.500 ; 0.000 ; High Pulse Width ; m706:m706|clock_scale[2] ; Rise ; m706|tti_shift~11|datain[0] ; ; 0.500 ; 0.500 ; 0.000 ; Low Pulse Width ; m706:m706|clock_scale[2] ; Rise ; m706|tti_shift~11|datain[0] ; ; 0.500 ; 0.500 ; 0.000 ; High Pulse Width ; m706:m706|clock_scale[2] ; Rise ; m706|tti_shift~11|dataout ; ; 0.500 ; 0.500 ; 0.000 ; Low Pulse Width ; m706:m706|clock_scale[2] ; Rise ; m706|tti_shift~11|dataout ; +--------+--------------+----------------+------------------+--------------------------+------------+-----------------------------+ +----------------------------------------------------------------------------------------------------------------------------+ ; Minimum Pulse Width: 'm706:m706|in_active' ; +--------+--------------+----------------+------------------+---------------------+------------+-----------------------------+ ; Slack ; Actual Width ; Required Width ; Type ; Clock ; Clock Edge ; Target ; +--------+--------------+----------------+------------------+---------------------+------------+-----------------------------+ ; -3.500 ; 0.500 ; 4.000 ; High Pulse Width ; m706:m706|in_active ; Rise ; m706:m706|in_last_unit ; ; -3.500 ; 0.500 ; 4.000 ; Low Pulse Width ; m706:m706|in_active ; Rise ; m706:m706|in_last_unit ; ; -3.500 ; 0.500 ; 4.000 ; High Pulse Width ; m706:m706|in_active ; Rise ; m706:m706|keyboard_flag ; ; -3.500 ; 0.500 ; 4.000 ; Low Pulse Width ; m706:m706|in_active ; Rise ; m706:m706|keyboard_flag ; ; -3.500 ; 0.500 ; 4.000 ; High Pulse Width ; m706:m706|in_active ; Rise ; m706:m706|reader_run ; ; -3.500 ; 0.500 ; 4.000 ; Low Pulse Width ; m706:m706|in_active ; Rise ; m706:m706|reader_run ; ; -3.500 ; 0.500 ; 4.000 ; High Pulse Width ; m706:m706|in_active ; Fall ; m706:m706|spike_detector ; ; -3.500 ; 0.500 ; 4.000 ; Low Pulse Width ; m706:m706|in_active ; Fall ; m706:m706|spike_detector ; ; -3.500 ; 0.500 ; 4.000 ; High Pulse Width ; m706:m706|in_active ; Rise ; m706:m706|tti02[0] ; ; -3.500 ; 0.500 ; 4.000 ; Low Pulse Width ; m706:m706|in_active ; Rise ; m706:m706|tti02[0] ; ; -3.500 ; 0.500 ; 4.000 ; High Pulse Width ; m706:m706|in_active ; Rise ; m706:m706|tti02[1] ; ; -3.500 ; 0.500 ; 4.000 ; Low Pulse Width ; m706:m706|in_active ; Rise ; m706:m706|tti02[1] ; ; -3.500 ; 0.500 ; 4.000 ; High Pulse Width ; m706:m706|in_active ; Rise ; m706:m706|tti02[2] ; ; -3.500 ; 0.500 ; 4.000 ; Low Pulse Width ; m706:m706|in_active ; Rise ; m706:m706|tti02[2] ; ; -3.500 ; 0.500 ; 4.000 ; High Pulse Width ; m706:m706|in_active ; Rise ; m706:m706|tti37[3] ; ; -3.500 ; 0.500 ; 4.000 ; Low Pulse Width ; m706:m706|in_active ; Rise ; m706:m706|tti37[3] ; ; -3.500 ; 0.500 ; 4.000 ; High Pulse Width ; m706:m706|in_active ; Rise ; m706:m706|tti37[4] ; ; -3.500 ; 0.500 ; 4.000 ; Low Pulse Width ; m706:m706|in_active ; Rise ; m706:m706|tti37[4] ; ; -3.500 ; 0.500 ; 4.000 ; High Pulse Width ; m706:m706|in_active ; Rise ; m706:m706|tti37[5] ; ; -3.500 ; 0.500 ; 4.000 ; Low Pulse Width ; m706:m706|in_active ; Rise ; m706:m706|tti37[5] ; ; -3.500 ; 0.500 ; 4.000 ; High Pulse Width ; m706:m706|in_active ; Rise ; m706:m706|tti37[6] ; ; -3.500 ; 0.500 ; 4.000 ; Low Pulse Width ; m706:m706|in_active ; Rise ; m706:m706|tti37[6] ; ; -3.500 ; 0.500 ; 4.000 ; High Pulse Width ; m706:m706|in_active ; Rise ; m706:m706|tti37[7] ; ; -3.500 ; 0.500 ; 4.000 ; Low Pulse Width ; m706:m706|in_active ; Rise ; m706:m706|tti37[7] ; ; 0.500 ; 0.500 ; 0.000 ; High Pulse Width ; m706:m706|in_active ; Rise ; m706|in_active|[0] ; ; 0.500 ; 0.500 ; 0.000 ; Low Pulse Width ; m706:m706|in_active ; Rise ; m706|in_active|[0] ; ; 0.500 ; 0.500 ; 0.000 ; High Pulse Width ; m706:m706|in_active ; Rise ; m706|in_active|dataout ; ; 0.500 ; 0.500 ; 0.000 ; Low Pulse Width ; m706:m706|in_active ; Rise ; m706|in_active|dataout ; ; 0.500 ; 0.500 ; 0.000 ; High Pulse Width ; m706:m706|in_active ; Rise ; m706|in_last_unit|[2] ; ; 0.500 ; 0.500 ; 0.000 ; Low Pulse Width ; m706:m706|in_active ; Rise ; m706|in_last_unit|[2] ; ; 0.500 ; 0.500 ; 0.000 ; High Pulse Width ; m706:m706|in_active ; Rise ; m706|keyboard_flag|[3] ; ; 0.500 ; 0.500 ; 0.000 ; Low Pulse Width ; m706:m706|in_active ; Rise ; m706|keyboard_flag|[3] ; ; 0.500 ; 0.500 ; 0.000 ; High Pulse Width ; m706:m706|in_active ; Rise ; m706|reader_run|[2] ; ; 0.500 ; 0.500 ; 0.000 ; Low Pulse Width ; m706:m706|in_active ; Rise ; m706|reader_run|[2] ; ; 0.500 ; 0.500 ; 0.000 ; High Pulse Width ; m706:m706|in_active ; Rise ; m706|spike_detector|[0] ; ; 0.500 ; 0.500 ; 0.000 ; Low Pulse Width ; m706:m706|in_active ; Rise ; m706|spike_detector|[0] ; ; 0.500 ; 0.500 ; 0.000 ; High Pulse Width ; m706:m706|in_active ; Rise ; m706|tti02[0]|[2] ; ; 0.500 ; 0.500 ; 0.000 ; Low Pulse Width ; m706:m706|in_active ; Rise ; m706|tti02[0]|[2] ; ; 0.500 ; 0.500 ; 0.000 ; High Pulse Width ; m706:m706|in_active ; Rise ; m706|tti02[1]|[2] ; ; 0.500 ; 0.500 ; 0.000 ; Low Pulse Width ; m706:m706|in_active ; Rise ; m706|tti02[1]|[2] ; ; 0.500 ; 0.500 ; 0.000 ; High Pulse Width ; m706:m706|in_active ; Rise ; m706|tti02[2]|[2] ; ; 0.500 ; 0.500 ; 0.000 ; Low Pulse Width ; m706:m706|in_active ; Rise ; m706|tti02[2]|[2] ; ; 0.500 ; 0.500 ; 0.000 ; High Pulse Width ; m706:m706|in_active ; Rise ; m706|tti37[3]|[2] ; ; 0.500 ; 0.500 ; 0.000 ; Low Pulse Width ; m706:m706|in_active ; Rise ; m706|tti37[3]|[2] ; ; 0.500 ; 0.500 ; 0.000 ; High Pulse Width ; m706:m706|in_active ; Rise ; m706|tti37[4]|[2] ; ; 0.500 ; 0.500 ; 0.000 ; Low Pulse Width ; m706:m706|in_active ; Rise ; m706|tti37[4]|[2] ; ; 0.500 ; 0.500 ; 0.000 ; High Pulse Width ; m706:m706|in_active ; Rise ; m706|tti37[5]|[2] ; ; 0.500 ; 0.500 ; 0.000 ; Low Pulse Width ; m706:m706|in_active ; Rise ; m706|tti37[5]|[2] ; ; 0.500 ; 0.500 ; 0.000 ; High Pulse Width ; m706:m706|in_active ; Rise ; m706|tti37[6]|[2] ; ; 0.500 ; 0.500 ; 0.000 ; Low Pulse Width ; m706:m706|in_active ; Rise ; m706|tti37[6]|[2] ; ; 0.500 ; 0.500 ; 0.000 ; High Pulse Width ; m706:m706|in_active ; Rise ; m706|tti37[7]|[2] ; ; 0.500 ; 0.500 ; 0.000 ; Low Pulse Width ; m706:m706|in_active ; Rise ; m706|tti37[7]|[2] ; ; 0.500 ; 0.500 ; 0.000 ; High Pulse Width ; m706:m706|in_active ; Rise ; m706|tti_shift~11|datain[1] ; ; 0.500 ; 0.500 ; 0.000 ; Low Pulse Width ; m706:m706|in_active ; Rise ; m706|tti_shift~11|datain[1] ; ; 0.500 ; 0.500 ; 0.000 ; High Pulse Width ; m706:m706|in_active ; Rise ; m706|tti_shift~11|dataout ; ; 0.500 ; 0.500 ; 0.000 ; Low Pulse Width ; m706:m706|in_active ; Rise ; m706|tti_shift~11|dataout ; +--------+--------------+----------------+------------------+---------------------+------------+-----------------------------+ +-------------------------------------------------------------------------------------------------------------+ ; Minimum Pulse Width: 'rx_rate' ; +--------+--------------+----------------+------------------+---------+------------+--------------------------+ ; Slack ; Actual Width ; Required Width ; Type ; Clock ; Clock Edge ; Target ; +--------+--------------+----------------+------------------+---------+------------+--------------------------+ ; -3.500 ; 0.500 ; 4.000 ; High Pulse Width ; rx_rate ; Rise ; m706:m706|clock_scale[0] ; ; -3.500 ; 0.500 ; 4.000 ; Low Pulse Width ; rx_rate ; Rise ; m706:m706|clock_scale[0] ; ; -3.500 ; 0.500 ; 4.000 ; High Pulse Width ; rx_rate ; Rise ; m706:m706|clock_scale[1] ; ; -3.500 ; 0.500 ; 4.000 ; Low Pulse Width ; rx_rate ; Rise ; m706:m706|clock_scale[1] ; ; -3.500 ; 0.500 ; 4.000 ; High Pulse Width ; rx_rate ; Rise ; m706:m706|clock_scale[2] ; ; -3.500 ; 0.500 ; 4.000 ; Low Pulse Width ; rx_rate ; Rise ; m706:m706|clock_scale[2] ; ; -3.500 ; 0.500 ; 4.000 ; High Pulse Width ; rx_rate ; Rise ; m706:m706|reader_run ; ; -3.500 ; 0.500 ; 4.000 ; Low Pulse Width ; rx_rate ; Rise ; m706:m706|reader_run ; ; 0.500 ; 0.500 ; 0.000 ; High Pulse Width ; rx_rate ; Rise ; m706|clock_scale[0]|clk ; ; 0.500 ; 0.500 ; 0.000 ; Low Pulse Width ; rx_rate ; Rise ; m706|clock_scale[0]|clk ; ; 0.500 ; 0.500 ; 0.000 ; High Pulse Width ; rx_rate ; Rise ; m706|clock_scale[1]|clk ; ; 0.500 ; 0.500 ; 0.000 ; Low Pulse Width ; rx_rate ; Rise ; m706|clock_scale[1]|clk ; ; 0.500 ; 0.500 ; 0.000 ; High Pulse Width ; rx_rate ; Rise ; m706|clock_scale[2]|clk ; ; 0.500 ; 0.500 ; 0.000 ; Low Pulse Width ; rx_rate ; Rise ; m706|clock_scale[2]|clk ; ; 0.500 ; 0.500 ; 0.000 ; High Pulse Width ; rx_rate ; Rise ; m706|reader_run|[0] ; ; 0.500 ; 0.500 ; 0.000 ; Low Pulse Width ; rx_rate ; Rise ; m706|reader_run|[0] ; ; 0.500 ; 0.500 ; 0.000 ; High Pulse Width ; rx_rate ; Rise ; rx_rate|dataout ; ; 0.500 ; 0.500 ; 0.000 ; Low Pulse Width ; rx_rate ; Rise ; rx_rate|dataout ; +--------+--------------+----------------+------------------+---------+------------+--------------------------+ +-----------------------------------------------------------------------------------------------------------------------------+ ; Minimum Pulse Width: 'm706:m706|in_last_unit' ; +--------+--------------+----------------+------------------+------------------------+------------+---------------------------+ ; Slack ; Actual Width ; Required Width ; Type ; Clock ; Clock Edge ; Target ; +--------+--------------+----------------+------------------+------------------------+------------+---------------------------+ ; -3.500 ; 0.500 ; 4.000 ; High Pulse Width ; m706:m706|in_last_unit ; Rise ; m706:m706|in_active ; ; -3.500 ; 0.500 ; 4.000 ; Low Pulse Width ; m706:m706|in_last_unit ; Rise ; m706:m706|in_active ; ; -3.500 ; 0.500 ; 4.000 ; High Pulse Width ; m706:m706|in_last_unit ; Rise ; m706:m706|reader_run ; ; -3.500 ; 0.500 ; 4.000 ; Low Pulse Width ; m706:m706|in_last_unit ; Rise ; m706:m706|reader_run ; ; 0.500 ; 0.500 ; 0.000 ; High Pulse Width ; m706:m706|in_last_unit ; Rise ; m706|in_active|[1] ; ; 0.500 ; 0.500 ; 0.000 ; Low Pulse Width ; m706:m706|in_last_unit ; Rise ; m706|in_active|[1] ; ; 0.500 ; 0.500 ; 0.000 ; High Pulse Width ; m706:m706|in_last_unit ; Rise ; m706|in_last_unit|dataout ; ; 0.500 ; 0.500 ; 0.000 ; Low Pulse Width ; m706:m706|in_last_unit ; Rise ; m706|in_last_unit|dataout ; ; 0.500 ; 0.500 ; 0.000 ; High Pulse Width ; m706:m706|in_last_unit ; Rise ; m706|reader_run|[3] ; ; 0.500 ; 0.500 ; 0.000 ; Low Pulse Width ; m706:m706|in_last_unit ; Rise ; m706|reader_run|[3] ; +--------+--------------+----------------+------------------+------------------------+------------+---------------------------+ +---------------------------------------------------------------------------------------------------------+ ; Minimum Pulse Width: 'rx_data' ; +--------+--------------+----------------+------------------+---------+------------+----------------------+ ; Slack ; Actual Width ; Required Width ; Type ; Clock ; Clock Edge ; Target ; +--------+--------------+----------------+------------------+---------+------------+----------------------+ ; -3.500 ; 0.500 ; 4.000 ; High Pulse Width ; rx_data ; Rise ; m706:m706|reader_run ; ; -3.500 ; 0.500 ; 4.000 ; Low Pulse Width ; rx_data ; Rise ; m706:m706|reader_run ; ; 0.500 ; 0.500 ; 0.000 ; High Pulse Width ; rx_data ; Rise ; m706|reader_run|[1] ; ; 0.500 ; 0.500 ; 0.000 ; Low Pulse Width ; rx_data ; Rise ; m706|reader_run|[1] ; ; 0.500 ; 0.500 ; 0.000 ; High Pulse Width ; rx_data ; Rise ; rx_data|dataout ; ; 0.500 ; 0.500 ; 0.000 ; Low Pulse Width ; rx_data ; Rise ; rx_data|dataout ; +--------+--------------+----------------+------------------+---------+------------+----------------------+ +----------------------------------------------------------------------------------------------+ ; Setup Times ; +-----------+--------------------------+-------+-------+------------+--------------------------+ ; Data Port ; Clock Port ; Rise ; Fall ; Clock Edge ; Clock Reference ; +-----------+--------------------------+-------+-------+------------+--------------------------+ ; rx_data ; m706:m706|clock_scale[2] ; 2.500 ; 2.500 ; Rise ; m706:m706|clock_scale[2] ; ; rx_rate ; m706:m706|clock_scale[2] ; 2.500 ; 2.500 ; Rise ; m706:m706|clock_scale[2] ; ; rx_data ; m706:m706|in_active ; 2.500 ; 2.500 ; Rise ; m706:m706|in_active ; ; rx_rate ; m706:m706|in_active ; 2.500 ; 2.500 ; Rise ; m706:m706|in_active ; +-----------+--------------------------+-------+-------+------------+--------------------------+ +----------------------------------------------------------------------------------------------+ ; Hold Times ; +-----------+--------------------------+-------+-------+------------+--------------------------+ ; Data Port ; Clock Port ; Rise ; Fall ; Clock Edge ; Clock Reference ; +-----------+--------------------------+-------+-------+------------+--------------------------+ ; rx_data ; m706:m706|clock_scale[2] ; 2.500 ; 2.500 ; Rise ; m706:m706|clock_scale[2] ; ; rx_rate ; m706:m706|clock_scale[2] ; 2.500 ; 2.500 ; Rise ; m706:m706|clock_scale[2] ; ; rx_data ; m706:m706|in_active ; 2.500 ; 2.500 ; Rise ; m706:m706|in_active ; ; rx_rate ; m706:m706|in_active ; 2.500 ; 2.500 ; Rise ; m706:m706|in_active ; +-----------+--------------------------+-------+-------+------------+--------------------------+ +------------------------------------------------------------------------------------------------+ ; Clock to Output Times ; +-----------+--------------------------+--------+--------+------------+--------------------------+ ; Data Port ; Clock Port ; Rise ; Fall ; Clock Edge ; Clock Reference ; +-----------+--------------------------+--------+--------+------------+--------------------------+ ; iob4_l ; m706:m706|clock_scale[2] ; 17.500 ; 17.500 ; Rise ; m706:m706|clock_scale[2] ; ; iob5_l ; m706:m706|clock_scale[2] ; 17.500 ; 17.500 ; Rise ; m706:m706|clock_scale[2] ; ; iob6_l ; m706:m706|clock_scale[2] ; 17.500 ; 17.500 ; Rise ; m706:m706|clock_scale[2] ; ; iob7_l ; m706:m706|clock_scale[2] ; 17.500 ; 17.500 ; Rise ; m706:m706|clock_scale[2] ; ; iob8_l ; m706:m706|clock_scale[2] ; 17.500 ; 17.500 ; Rise ; m706:m706|clock_scale[2] ; ; iob9_l ; m706:m706|clock_scale[2] ; 17.500 ; 17.500 ; Rise ; m706:m706|clock_scale[2] ; ; iob10_l ; m706:m706|clock_scale[2] ; 17.500 ; 17.500 ; Rise ; m706:m706|clock_scale[2] ; ; iob11_l ; m706:m706|clock_scale[2] ; 17.500 ; 17.500 ; Rise ; m706:m706|clock_scale[2] ; ; irq_l ; m706:m706|clock_scale[2] ; 9.500 ; 9.500 ; Rise ; m706:m706|clock_scale[2] ; ; skip_l ; m706:m706|clock_scale[2] ; 17.500 ; 17.500 ; Rise ; m706:m706|clock_scale[2] ; ; dsrttl ; m706:m706|in_active ; 9.500 ; 9.500 ; Rise ; m706:m706|in_active ; ; iob4_l ; m706:m706|in_active ; 17.500 ; 17.500 ; Rise ; m706:m706|in_active ; ; iob5_l ; m706:m706|in_active ; 17.500 ; 17.500 ; Rise ; m706:m706|in_active ; ; iob6_l ; m706:m706|in_active ; 17.500 ; 17.500 ; Rise ; m706:m706|in_active ; ; iob7_l ; m706:m706|in_active ; 17.500 ; 17.500 ; Rise ; m706:m706|in_active ; ; iob8_l ; m706:m706|in_active ; 17.500 ; 17.500 ; Rise ; m706:m706|in_active ; ; iob9_l ; m706:m706|in_active ; 17.500 ; 17.500 ; Rise ; m706:m706|in_active ; ; iob10_l ; m706:m706|in_active ; 17.500 ; 17.500 ; Rise ; m706:m706|in_active ; ; iob11_l ; m706:m706|in_active ; 17.500 ; 17.500 ; Rise ; m706:m706|in_active ; ; irq_l ; m706:m706|in_active ; 9.500 ; 9.500 ; Rise ; m706:m706|in_active ; ; skip_l ; m706:m706|in_active ; 17.500 ; 17.500 ; Rise ; m706:m706|in_active ; ; dsrttl ; m706:m706|in_last_unit ; 9.500 ; 9.500 ; Rise ; m706:m706|in_last_unit ; ; dsrttl ; rx_data ; 10.000 ; 10.000 ; Rise ; rx_data ; ; dsrttl ; rx_rate ; 10.000 ; 10.000 ; Rise ; rx_rate ; +-----------+--------------------------+--------+--------+------------+--------------------------+ +------------------------------------------------------------------------------------------------+ ; Minimum Clock to Output Times ; +-----------+--------------------------+--------+--------+------------+--------------------------+ ; Data Port ; Clock Port ; Rise ; Fall ; Clock Edge ; Clock Reference ; +-----------+--------------------------+--------+--------+------------+--------------------------+ ; iob4_l ; m706:m706|clock_scale[2] ; 17.500 ; 17.500 ; Rise ; m706:m706|clock_scale[2] ; ; iob5_l ; m706:m706|clock_scale[2] ; 17.500 ; 17.500 ; Rise ; m706:m706|clock_scale[2] ; ; iob6_l ; m706:m706|clock_scale[2] ; 17.500 ; 17.500 ; Rise ; m706:m706|clock_scale[2] ; ; iob7_l ; m706:m706|clock_scale[2] ; 17.500 ; 17.500 ; Rise ; m706:m706|clock_scale[2] ; ; iob8_l ; m706:m706|clock_scale[2] ; 17.500 ; 17.500 ; Rise ; m706:m706|clock_scale[2] ; ; iob9_l ; m706:m706|clock_scale[2] ; 17.500 ; 17.500 ; Rise ; m706:m706|clock_scale[2] ; ; iob10_l ; m706:m706|clock_scale[2] ; 17.500 ; 17.500 ; Rise ; m706:m706|clock_scale[2] ; ; iob11_l ; m706:m706|clock_scale[2] ; 17.500 ; 17.500 ; Rise ; m706:m706|clock_scale[2] ; ; irq_l ; m706:m706|clock_scale[2] ; 9.500 ; 9.500 ; Rise ; m706:m706|clock_scale[2] ; ; skip_l ; m706:m706|clock_scale[2] ; 17.500 ; 17.500 ; Rise ; m706:m706|clock_scale[2] ; ; dsrttl ; m706:m706|in_active ; 9.500 ; 9.500 ; Rise ; m706:m706|in_active ; ; iob4_l ; m706:m706|in_active ; 17.500 ; 17.500 ; Rise ; m706:m706|in_active ; ; iob5_l ; m706:m706|in_active ; 17.500 ; 17.500 ; Rise ; m706:m706|in_active ; ; iob6_l ; m706:m706|in_active ; 17.500 ; 17.500 ; Rise ; m706:m706|in_active ; ; iob7_l ; m706:m706|in_active ; 17.500 ; 17.500 ; Rise ; m706:m706|in_active ; ; iob8_l ; m706:m706|in_active ; 17.500 ; 17.500 ; Rise ; m706:m706|in_active ; ; iob9_l ; m706:m706|in_active ; 17.500 ; 17.500 ; Rise ; m706:m706|in_active ; ; iob10_l ; m706:m706|in_active ; 17.500 ; 17.500 ; Rise ; m706:m706|in_active ; ; iob11_l ; m706:m706|in_active ; 17.500 ; 17.500 ; Rise ; m706:m706|in_active ; ; irq_l ; m706:m706|in_active ; 9.500 ; 9.500 ; Rise ; m706:m706|in_active ; ; skip_l ; m706:m706|in_active ; 17.500 ; 17.500 ; Rise ; m706:m706|in_active ; ; dsrttl ; m706:m706|in_last_unit ; 9.500 ; 9.500 ; Rise ; m706:m706|in_last_unit ; ; dsrttl ; rx_data ; 10.000 ; 10.000 ; Rise ; rx_data ; ; dsrttl ; rx_rate ; 10.000 ; 10.000 ; Rise ; rx_rate ; +-----------+--------------------------+--------+--------+------------+--------------------------+ +------------------------------------------------------+ ; Propagation Delay ; +------------+-------------+--------+----+----+--------+ ; Input Port ; Output Port ; RR ; RF ; FR ; FF ; +------------+-------------+--------+----+----+--------+ ; biop1 ; skip_l ; 10.000 ; ; ; 10.000 ; ; biop2 ; acclr_l ; 10.000 ; ; ; 10.000 ; ; biop4 ; iob4_l ; 10.000 ; ; ; 10.000 ; ; biop4 ; iob5_l ; 10.000 ; ; ; 10.000 ; ; biop4 ; iob6_l ; 10.000 ; ; ; 10.000 ; ; biop4 ; iob7_l ; 10.000 ; ; ; 10.000 ; ; biop4 ; iob8_l ; 10.000 ; ; ; 10.000 ; ; biop4 ; iob9_l ; 10.000 ; ; ; 10.000 ; ; biop4 ; iob10_l ; 10.000 ; ; ; 10.000 ; ; biop4 ; iob11_l ; 10.000 ; ; ; 10.000 ; ; rx_sel ; acclr_l ; 10.000 ; ; ; 10.000 ; ; rx_sel ; iob4_l ; 10.000 ; ; ; 10.000 ; ; rx_sel ; iob5_l ; 10.000 ; ; ; 10.000 ; ; rx_sel ; iob6_l ; 10.000 ; ; ; 10.000 ; ; rx_sel ; iob7_l ; 10.000 ; ; ; 10.000 ; ; rx_sel ; iob8_l ; 10.000 ; ; ; 10.000 ; ; rx_sel ; iob9_l ; 10.000 ; ; ; 10.000 ; ; rx_sel ; iob10_l ; 10.000 ; ; ; 10.000 ; ; rx_sel ; iob11_l ; 10.000 ; ; ; 10.000 ; ; rx_sel ; skip_l ; 10.000 ; ; ; 10.000 ; +------------+-------------+--------+----+----+--------+ +------------------------------------------------------+ ; Minimum Propagation Delay ; +------------+-------------+--------+----+----+--------+ ; Input Port ; Output Port ; RR ; RF ; FR ; FF ; +------------+-------------+--------+----+----+--------+ ; biop1 ; skip_l ; 10.000 ; ; ; 10.000 ; ; biop2 ; acclr_l ; 10.000 ; ; ; 10.000 ; ; biop4 ; iob4_l ; 10.000 ; ; ; 10.000 ; ; biop4 ; iob5_l ; 10.000 ; ; ; 10.000 ; ; biop4 ; iob6_l ; 10.000 ; ; ; 10.000 ; ; biop4 ; iob7_l ; 10.000 ; ; ; 10.000 ; ; biop4 ; iob8_l ; 10.000 ; ; ; 10.000 ; ; biop4 ; iob9_l ; 10.000 ; ; ; 10.000 ; ; biop4 ; iob10_l ; 10.000 ; ; ; 10.000 ; ; biop4 ; iob11_l ; 10.000 ; ; ; 10.000 ; ; rx_sel ; acclr_l ; 10.000 ; ; ; 10.000 ; ; rx_sel ; iob4_l ; 10.000 ; ; ; 10.000 ; ; rx_sel ; iob5_l ; 10.000 ; ; ; 10.000 ; ; rx_sel ; iob6_l ; 10.000 ; ; ; 10.000 ; ; rx_sel ; iob7_l ; 10.000 ; ; ; 10.000 ; ; rx_sel ; iob8_l ; 10.000 ; ; ; 10.000 ; ; rx_sel ; iob9_l ; 10.000 ; ; ; 10.000 ; ; rx_sel ; iob10_l ; 10.000 ; ; ; 10.000 ; ; rx_sel ; iob11_l ; 10.000 ; ; ; 10.000 ; ; rx_sel ; skip_l ; 10.000 ; ; ; 10.000 ; +------------+-------------+--------+----+----+--------+ +-------------------------------------------------------------------------------------------------+ ; Setup Transfers ; +--------------------------+--------------------------+----------+----------+----------+----------+ ; From Clock ; To Clock ; RR Paths ; FR Paths ; RF Paths ; FF Paths ; +--------------------------+--------------------------+----------+----------+----------+----------+ ; m706:m706|clock_scale[2] ; m706:m706|clock_scale[2] ; 14 ; 0 ; 0 ; 0 ; ; m706:m706|in_active ; m706:m706|clock_scale[2] ; 16 ; 3 ; 0 ; 0 ; ; m706:m706|in_last_unit ; m706:m706|clock_scale[2] ; 2 ; 2 ; 0 ; 0 ; ; rx_data ; m706:m706|clock_scale[2] ; 3 ; 3 ; 0 ; 0 ; ; rx_rate ; m706:m706|clock_scale[2] ; 2 ; 2 ; 0 ; 0 ; ; m706:m706|clock_scale[2] ; m706:m706|in_active ; 13 ; 0 ; 0 ; 0 ; ; m706:m706|in_active ; m706:m706|in_active ; 15 ; 2 ; 0 ; 0 ; ; m706:m706|in_last_unit ; m706:m706|in_active ; 2 ; 2 ; 0 ; 0 ; ; rx_data ; m706:m706|in_active ; 3 ; 3 ; 0 ; 0 ; ; rx_rate ; m706:m706|in_active ; 2 ; 2 ; 0 ; 0 ; ; m706:m706|clock_scale[2] ; rx_rate ; 1 ; 1 ; 0 ; 0 ; ; rx_rate ; rx_rate ; 6 ; 0 ; 0 ; 0 ; +--------------------------+--------------------------+----------+----------+----------+----------+ Entries labeled "false path" only account for clock-to-clock false paths and not path-based false paths. As a result, actual path counts may be lower than reported. +-------------------------------------------------------------------------------------------------+ ; Hold Transfers ; +--------------------------+--------------------------+----------+----------+----------+----------+ ; From Clock ; To Clock ; RR Paths ; FR Paths ; RF Paths ; FF Paths ; +--------------------------+--------------------------+----------+----------+----------+----------+ ; m706:m706|clock_scale[2] ; m706:m706|clock_scale[2] ; 14 ; 0 ; 0 ; 0 ; ; m706:m706|in_active ; m706:m706|clock_scale[2] ; 16 ; 3 ; 0 ; 0 ; ; m706:m706|in_last_unit ; m706:m706|clock_scale[2] ; 2 ; 2 ; 0 ; 0 ; ; rx_data ; m706:m706|clock_scale[2] ; 3 ; 3 ; 0 ; 0 ; ; rx_rate ; m706:m706|clock_scale[2] ; 2 ; 2 ; 0 ; 0 ; ; m706:m706|clock_scale[2] ; m706:m706|in_active ; 13 ; 0 ; 0 ; 0 ; ; m706:m706|in_active ; m706:m706|in_active ; 15 ; 2 ; 0 ; 0 ; ; m706:m706|in_last_unit ; m706:m706|in_active ; 2 ; 2 ; 0 ; 0 ; ; rx_data ; m706:m706|in_active ; 3 ; 3 ; 0 ; 0 ; ; rx_rate ; m706:m706|in_active ; 2 ; 2 ; 0 ; 0 ; ; m706:m706|clock_scale[2] ; rx_rate ; 1 ; 1 ; 0 ; 0 ; ; rx_rate ; rx_rate ; 6 ; 0 ; 0 ; 0 ; +--------------------------+--------------------------+----------+----------+----------+----------+ Entries labeled "false path" only account for clock-to-clock false paths and not path-based false paths. As a result, actual path counts may be lower than reported. +-------------------------------------------------------------------------------------------------+ ; Recovery Transfers ; +--------------------------+--------------------------+----------+----------+----------+----------+ ; From Clock ; To Clock ; RR Paths ; FR Paths ; RF Paths ; FF Paths ; +--------------------------+--------------------------+----------+----------+----------+----------+ ; m706:m706|clock_scale[2] ; m706:m706|clock_scale[2] ; 2 ; 2 ; 0 ; 0 ; ; m706:m706|in_active ; m706:m706|clock_scale[2] ; 12 ; 13 ; 1 ; 1 ; ; m706:m706|in_last_unit ; m706:m706|clock_scale[2] ; 11 ; 11 ; 1 ; 1 ; ; rx_data ; m706:m706|clock_scale[2] ; 12 ; 12 ; 1 ; 1 ; ; rx_rate ; m706:m706|clock_scale[2] ; 11 ; 11 ; 1 ; 1 ; ; m706:m706|clock_scale[2] ; m706:m706|in_active ; 2 ; 0 ; 0 ; 0 ; ; m706:m706|in_active ; m706:m706|in_active ; 9 ; 8 ; 1 ; 1 ; ; m706:m706|in_last_unit ; m706:m706|in_active ; 8 ; 8 ; 1 ; 1 ; ; rx_data ; m706:m706|in_active ; 8 ; 8 ; 1 ; 1 ; ; rx_rate ; m706:m706|in_active ; 8 ; 8 ; 1 ; 1 ; ; m706:m706|clock_scale[2] ; m706:m706|in_last_unit ; 2 ; 2 ; 0 ; 0 ; ; m706:m706|in_active ; m706:m706|in_last_unit ; 3 ; 3 ; 0 ; 0 ; ; m706:m706|in_last_unit ; m706:m706|in_last_unit ; 1 ; 1 ; 0 ; 0 ; ; rx_data ; m706:m706|in_last_unit ; 2 ; 2 ; 0 ; 0 ; ; rx_rate ; m706:m706|in_last_unit ; 1 ; 1 ; 0 ; 0 ; ; m706:m706|clock_scale[2] ; rx_data ; 1 ; 0 ; 0 ; 0 ; ; m706:m706|in_active ; rx_data ; 1 ; 0 ; 0 ; 0 ; ; m706:m706|clock_scale[2] ; rx_rate ; 1 ; 0 ; 0 ; 0 ; ; m706:m706|in_active ; rx_rate ; 4 ; 3 ; 0 ; 0 ; ; m706:m706|in_last_unit ; rx_rate ; 3 ; 3 ; 0 ; 0 ; +--------------------------+--------------------------+----------+----------+----------+----------+ Entries labeled "false path" only account for clock-to-clock false paths and not path-based false paths. As a result, actual path counts may be lower than reported. +-------------------------------------------------------------------------------------------------+ ; Removal Transfers ; +--------------------------+--------------------------+----------+----------+----------+----------+ ; From Clock ; To Clock ; RR Paths ; FR Paths ; RF Paths ; FF Paths ; +--------------------------+--------------------------+----------+----------+----------+----------+ ; m706:m706|clock_scale[2] ; m706:m706|clock_scale[2] ; 2 ; 2 ; 0 ; 0 ; ; m706:m706|in_active ; m706:m706|clock_scale[2] ; 12 ; 13 ; 1 ; 1 ; ; m706:m706|in_last_unit ; m706:m706|clock_scale[2] ; 11 ; 11 ; 1 ; 1 ; ; rx_data ; m706:m706|clock_scale[2] ; 12 ; 12 ; 1 ; 1 ; ; rx_rate ; m706:m706|clock_scale[2] ; 11 ; 11 ; 1 ; 1 ; ; m706:m706|clock_scale[2] ; m706:m706|in_active ; 2 ; 0 ; 0 ; 0 ; ; m706:m706|in_active ; m706:m706|in_active ; 9 ; 8 ; 1 ; 1 ; ; m706:m706|in_last_unit ; m706:m706|in_active ; 8 ; 8 ; 1 ; 1 ; ; rx_data ; m706:m706|in_active ; 8 ; 8 ; 1 ; 1 ; ; rx_rate ; m706:m706|in_active ; 8 ; 8 ; 1 ; 1 ; ; m706:m706|clock_scale[2] ; m706:m706|in_last_unit ; 2 ; 2 ; 0 ; 0 ; ; m706:m706|in_active ; m706:m706|in_last_unit ; 3 ; 3 ; 0 ; 0 ; ; m706:m706|in_last_unit ; m706:m706|in_last_unit ; 1 ; 1 ; 0 ; 0 ; ; rx_data ; m706:m706|in_last_unit ; 2 ; 2 ; 0 ; 0 ; ; rx_rate ; m706:m706|in_last_unit ; 1 ; 1 ; 0 ; 0 ; ; m706:m706|clock_scale[2] ; rx_data ; 1 ; 0 ; 0 ; 0 ; ; m706:m706|in_active ; rx_data ; 1 ; 0 ; 0 ; 0 ; ; m706:m706|clock_scale[2] ; rx_rate ; 1 ; 0 ; 0 ; 0 ; ; m706:m706|in_active ; rx_rate ; 4 ; 3 ; 0 ; 0 ; ; m706:m706|in_last_unit ; rx_rate ; 3 ; 3 ; 0 ; 0 ; +--------------------------+--------------------------+----------+----------+----------+----------+ Entries labeled "false path" only account for clock-to-clock false paths and not path-based false paths. As a result, actual path counts may be lower than reported. --------------- ; Report TCCS ; --------------- No dedicated SERDES Transmitter circuitry present in device or used in design --------------- ; Report RSKM ; --------------- No dedicated SERDES Receiver circuitry present in device or used in design +------------------------------------------------+ ; Unconstrained Paths ; +---------------------------------+-------+------+ ; Property ; Setup ; Hold ; +---------------------------------+-------+------+ ; Illegal Clocks ; 0 ; 0 ; ; Unconstrained Clocks ; 0 ; 0 ; ; Unconstrained Input Ports ; 5 ; 5 ; ; Unconstrained Input Port Paths ; 22 ; 22 ; ; Unconstrained Output Ports ; 12 ; 12 ; ; Unconstrained Output Port Paths ; 31 ; 31 ; +---------------------------------+-------+------+ +------------------------------------+ ; TimeQuest Timing Analyzer Messages ; +------------------------------------+ Info: ******************************************************************* Info: Running Quartus II 64-Bit TimeQuest Timing Analyzer Info: Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition Info: Processing started: Wed Apr 10 18:59:21 2024 Info: Command: quartus_sta m706 -c m706 Info: qsta_default_script.tcl version: #1 Info (306004): Started post-fitting delay annotation Info (306005): Delay annotation completed successfully Warning (335095): TimeQuest Timing Analyzer does not support the analysis of latches as synchronous elements for the currently selected device family. Critical Warning (332012): Synopsys Design Constraints File file not found: 'm706.sdc'. A Synopsys Design Constraints File is required by the TimeQuest Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design. Info (332142): No user constrained base clocks found in the design. Calling "derive_clocks -period 1.0" Info (332105): Deriving Clocks Info (332105): create_clock -period 1.000 -name m706:m706|clock_scale[2] m706:m706|clock_scale[2] Info (332105): create_clock -period 1.000 -name m706:m706|in_last_unit m706:m706|in_last_unit Info (332105): create_clock -period 1.000 -name rx_rate rx_rate Info (332105): create_clock -period 1.000 -name m706:m706|in_active m706:m706|in_active Info (332105): create_clock -period 1.000 -name rx_data rx_data Warning (332191): Clock target m706:m706|in_active of clock m706:m706|in_active is fed by another target of the same clock. Info: Found TIMEQUEST_REPORT_SCRIPT_INCLUDE_DEFAULT_ANALYSIS = ON Critical Warning (332148): Timing requirements not met Info (332146): Worst-case setup slack is -9.000 Info (332119): Slack End Point TNS Clock Info (332119): ========= ============= ===================== Info (332119): -9.000 -93.500 m706:m706|clock_scale[2] Info (332119): -9.000 -83.000 m706:m706|in_active Info (332119): -9.000 -27.000 rx_rate Info (332146): Worst-case hold slack is -3.000 Info (332119): Slack End Point TNS Clock Info (332119): ========= ============= ===================== Info (332119): -3.000 -8.500 m706:m706|clock_scale[2] Info (332119): -3.000 -5.500 m706:m706|in_active Info (332119): 1.500 0.000 rx_rate Info (332146): Worst-case recovery slack is -27.500 Info (332119): Slack End Point TNS Clock Info (332119): ========= ============= ===================== Info (332119): -27.500 -39.500 m706:m706|in_last_unit Info (332119): -22.500 -84.500 m706:m706|clock_scale[2] Info (332119): -12.000 -64.000 m706:m706|in_active Info (332119): -11.500 -38.500 rx_rate Info (332119): -11.500 -11.500 rx_data Info (332146): Worst-case removal slack is -8.000 Info (332119): Slack End Point TNS Clock Info (332119): ========= ============= ===================== Info (332119): -8.000 -13.000 m706:m706|clock_scale[2] Info (332119): -8.000 -8.000 m706:m706|in_active Info (332119): 0.000 0.000 m706:m706|in_last_unit Info (332119): 4.500 0.000 rx_rate Info (332119): 7.500 0.000 rx_data Info (332146): Worst-case minimum pulse width slack is -3.500 Info (332119): Slack End Point TNS Clock Info (332119): ========= ============= ===================== Info (332119): -3.500 -98.000 m706:m706|clock_scale[2] Info (332119): -3.500 -84.000 m706:m706|in_active Info (332119): -3.500 -28.000 rx_rate Info (332119): -3.500 -14.000 m706:m706|in_last_unit Info (332119): -3.500 -7.000 rx_data Info (332001): The selected device family is not supported by the report_metastability command. Info (332102): Design is not fully constrained for setup requirements Info (332102): Design is not fully constrained for hold requirements Info: Quartus II 64-Bit TimeQuest Timing Analyzer was successful. 0 errors, 4 warnings Info: Peak virtual memory: 4519 megabytes Info: Processing ended: Wed Apr 10 18:59:23 2024 Info: Elapsed time: 00:00:02 Info: Total CPU time (on all processors): 00:00:00