09/06/93 JMBW Created (from KSDEFS, ucode, and Alan's email) Page tables are pointed to by DBR1-DBR4: ("descriptor base registers") DBR1 user space low 128K DBR2 user space high 128K DBR3 exec space high 128K DBR4 exec space low 128K (not present on all KA10 paging boxes) (identity mapped in ITS anyway) Each DBR contains the physical address of a 64-word block: LH RH +-----+-----+ | 0 | 1 | +-----+-----+ | 2 | 3 | . . . . . . | 174 | 175 | +-----+-----+ | 176 | 177 | +-----+-----+ where halfwords 0-177 contain the entries for pages 0-177 (1K each) in the segment addressed by that DBR. Note that the EPT and UPT have nothing to do with paging. Page table entry (halfword): 1 1 1 1 1 1 1 1 0 1 2 3 4 5 6 7 8 9 0 1 2 3 4 5 6 7 +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+ |ACC|///|A|C|///| PHYSICAL PAGE NO. | +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+ ACC (access) 00 no access allowed 01 read only 10 read/write/first (=01, for software "dirty" bit) 11 read/write A (age bit) cleared on first access (was 3-bit field on KA10, set to 000) C (cacheable) if 1, data from this page may be put in cache The physical page # is the ITS page # (not DEC), i.e. shift the page number left ten bits to get the absolute base address of the 1K page. The DBRs are loaded by the LDBR1-LDBR4 instructions (which usurp the opcodes for WRSPB, WRCSB, WRPUR, and WRCSTM), which also flush the cache and both halves of the TLB (including the half not mapped by the DBR being loaded). These instructions use the immediate operand as the physical address of the page tables, which means they have to be in the first 256K (Alan says in fact they are always in the first 128K). The user DBRs can also be loaded by LPMR (702^9 17,), which also loads the quantum timer (and the JPCs, if supported by this microcode). The DBRs may be retrieved by SDBR1-SDBR4 (which usurp RDSPB, RDCSB, RDPUR, RDCSTM), which each store the DBR at the address given by the EA. Similarly, SPM (702^9 7,) is the reverse of LPMR.