JDF F
// Created by Project Navigator ver 1.0
PROJECT iob_xy
DESIGN iob_xy Normal
DEVFAM spartan2
DEVFAMTIME 0
DEVICE xc2s100
DEVICETIME 1041537174
DEVPKG tq144
DEVPKGTIME 1040136741
DEVSPEED -5
DEVSPEEDTIME 1040136741
FLOW XST VHDL
FLOWTIME 1040136741
STIMULUS iob_tb.vhd Normal
DOCUMENT keyb-doc.txt
MODULE iob.vhd
MODSTYLE iob Normal
MODULE posedge.vhd
MODSTYLE posedge Normal
MODULE XYRam.vhd
MODSTYLE xyram Normal
MODULE KL8JA.vhd
MODSTYLE kl8ja Normal
MODULE vote.vhd
MODSTYLE voter Normal
LIBFILE VT52_cfg.vhd work ***
LIBFILE image_pb.vhd work ***
LIBFILE iob_xy_cfg.vhd work ***
LIBFILE VC8E_cfg.vhd work ***
[Normal]
p_impactConfigFileName=xstvhd, spartan2, Implementation.t_impactProgrammingTool, 1042828422, X:\PDP-8\iob\FPGA\iob1\iob.bit
p_impactConfigMode=xstvhd, spartan2, Implementation.t_impactProgrammingTool, 1042828345, Boundary Scan
p_impactPort=xstvhd, spartan2, Implementation.t_impactProgrammingTool, 1042828345, LPT 2 (PC)
p_ModelSimSimRes=xstvhd, spartan2, Module VHDL Test Bench.t_MSimulatePostMapVhdlModel, 1041083237, 1 ps
p_ModelSimSimRunTime_tb=xstvhd, spartan2, Module VHDL Test Bench.t_MSimulatePostMapVhdlModel, 1041049783, 0ms
p_xstCrossClockAnalysis=xstvhd, spartan2, Schematic.t_synthesize, 1049730292, True
xilxBitgCfg_Rate=xstvhd, spartan2, Implementation.t_bitFile, 1049726450, 5
xilxBitgStart_Clk_Done=xstvhd, spartan2, Implementation.t_bitFile, 1049726450, 1
xilxBitgStart_Clk_DriveDone=xstvhd, spartan2, Implementation.t_bitFile, 1049726450, True
xilxMapReportDetail=xstvhd, spartan2, Implementation.t_map, 1049730413, True
xilxPARdetailedReport=xstvhd, spartan2, Implementation.t_par, 1049730413, True
xilxPAReffortLevel=xstvhd, spartan2, Implementation.t_par, 1049730413, Lowest
xilxXPORTInpFileName=xstvhd, spartan2, Design.t_xport, 1042484710, X:\PDP-8\SBC6120\PLD\IOT1\IOT1.PLD
xilxXPORTInpFileType=xstvhd, spartan2, Design.t_xport, 1042484795, AHDL
[STATUS-ALL]
iob.vhd.jhdFile=WARNINGS,1051373647
XYRam.vhd.jhdFile=WARNINGS,1051373647
[STRATEGY-LIST]
Normal=True