/INSTRUCTION TEST PART I PDP-12 MAINDEC 12-D0BA-L-(D) /COPYRIGHT 1969, DIGITAL EQUIPMENT CORP., MAYNARD MASS. /PDP-12 INSTRUCTION DEFINITIONS (PARTIAL) /MISCELLANEOUS EXPUNGE HLT=0000 /HALT PDP=0002 /CHANGE TO PDP-8 MODE LINC=6141 /CHANGE TO LINC MODE QAC=0005 /ZI TO AI-J(11 BITS) I EQUALS 1 TO 11 CLR=0011 /CLEAR ACCUMULATOR, LINK, AND Z REGISTER ATR=0014 /(A6-A11)>R REGISTER RTA=0015 /R REGISTER>(A6-A11) NOP=0016 /NO OPERATION COM=0017 /C(AC)>C(A) SET=0040 /C(P+1)>BETA REGISTER (OR INDIRECT) XSK=0200 /SKIP ON 1777 /SHIFT ROL=0240 /ROTATE LEFT ROR=0300 /ROTATE RIGHT ALSO SHIFT RIGHT INTO MQ REGISTER SCR=0340 /SCALE RIGHT ALSO SHIFT RIGHT INTO MQ REGISTER /SKIP SXL=0400 /SKIP IF EXTERNAL LEVEL IS -3 KST=0415 /SKIP IF KEY HAS BEEN STRUCK SNS=0440 /SKIP IF SENSE SWITCH IS UP SKP=0456 /SKIP UNCONDITIONALLY AZE=0450 /SKIP IF ACCUMULATOR ZERO APO=0451 /SKIP IF ACCUMULATOR POSITIVE LZE=0452 /SKIP IF LINK ZERO FLO=0454 /SKIP IF ADD OVERFLOW FLAG IS SET QLZ=0455 /SKIP IF BIT 11 OF MQ REGISTER IS 0 /OPERATE IOB=0500 /EXECUTE THE FOLLOWING IOT INSTRUCTION IN PDP-8 MODE LSW=0517 /READ THE CONTENTS OF THHE LEFT SWITCHES INTO THE AC RSW=0516 /READ THE CONTENTS OF THHE RIGHT SWITCHES INTO THE AC /ARITHMETIC LDA=1000 /LOAD ACCUMULATOR STA=1040 /STORE CONTENTS OF ACCUMULATOR ADA=1100 /ADD TO CONTENTS OF ACCUMULATOR ADM=1140 /ADD TO CONTENTS OF MEMORY REGISTER LAM=1200 /ADD CONTENTS OF LINK AND ACCUMULATOR /TO CONTENTS OF MEMORY REGISTER MUL=1240 /MULTIPLY /HALF WORD OPERATIONS LDH=1300 /TRANSFER HALF WORD FROM MEMORY INTO /THE RIGHT HALF OF ACCUMULATOR STH=1340 /TRANSFER THE HALF WORD FROM THE RIGHT /SIDE OF ACCUMULATOR REGISTER INTO THE /DESIGNATED HALF OF A MEMORY REGISTER SHD=1400 /SKIP IF THE HALF WORD IN ACCUMULATOR /REGISTER AND THE MEMORY REGISTER DIFFER /MEMORY REFERENCE OPERATIONS SAE=1440 /SKIP IF THE CONTENTS OF THE ACCUMULATOR /EQUAL THE CONTENTS OF THE DESIGNATED /MEMORY REGISTER SRO=1500 /SKIP IF THE RIGHTMOST BIT IN THE /DESIGNATED MEMORY REGISTER IS 0; /AFTER TESTING, ROTATE THE CONTENTS /ONE PLACE TO THE RIGHT BCL=1540 /FOR EACH BIT POSITION OF MEMORY REGISTER /Y THAT CONTAINS A 1; CLEAR THE /CORRESPONDING BIT POSITION OF THE ACCUMULATOR /(LOGICAL AND) BSE=1600 /FOR EACH BIT POSITION OF MEMORY /REGISTER Y THAT CONTAINS A 1; SET THE /THE CORRESPONDING BIT POSITION OF THE ACCUMULATOR /(INCLUSIVE OR) BCO=1640 /FOR EACH BIT POSITION OF MEMORY /REGISTER Y THAT CONTAINS A 1; COMPLEMENT /THE CORRESPONDING BIT POSITION OF THE /ACCUMULATOR (EXCLUSIVE OR) I=0020 /I BIT ADDRESS REFERENCE /FULL ADDRESS ADD=2000 /ADD THE CONTENTS OF THE DESIGNATED /MEMORY REGISTER TO THE ACCUMULATOR STC=4000 /STORE THE CONTENTS OF THE ACCUMULATOR /IN THE DESIGNATED MEMORY REGISTER /THEN CLEAR ACCUMULATOR JMP=6000 /JUMP TO ANOTHER DESIGNATED MEMORY /REGISTER FOR THE NEXT INSTRUCTION. /INPUT - OUTPUT TLS=6046 /LOAD PRINTER/PUNCH BUFFER, /PRINT, CLEAR FLAG /THIS TEST IS DESIGNED AS A QUICK CONFIDENCE CHECK /OF MOST OF THE PDP-12 L MODE INSTRUCTIONS. /SET LEFT AND RIGHT SWITCHES TO ONE'S, SENSE SWITCHES TO ONE'S, /I/O PRESET L MODE, START 20 /PROGRAM WILL HALT AT REL 0022; AC MUST = 0 /THIS PROGRAM WILL RUN IN ANY 1K SEGMENT *4001 /TAGS AND INITIAL CONSTANTS CALLED 0001 /THIS WAY TO AVOID ADDRESSING PROBLEMS. 0001 0000 0000 /B REG 0000 0000 /B2 REG 0000 0010 /NUM REG 0000 0000 /TEM REG 0000 /CNT REG B=0004 B2=0006 NUM=0010 TEM=0012 CNT=0013 *4020 S1, CLR /MAJOR START L MODE 4020 STC CNT /SET COUNTER = 0 HLT /LEGAL HALT, AC=0'S S2, SET I B /INITIALIZE B NUM /(B)=10 SET I B2 /INITIALIZE B2 TEM /(B2)=0 SET I NUM /NUMBER TO BE TESTED 0001 /(NUM)=1 /MAJOR RESTART FROM END OF PASS LS1, LDA I /TEST MODE OF HLT /INDEX, LDA, LOAD AC SAE I /WITH HLT, DOES AC HLT /CONTAIN HLT? HLT /LDA I OR SAE I FAILED LDA B /SET (AC) = (B) SAE B /SHOULD SKIP HLT /LDA, SAE FAILED SAE B /TRY IT AGAIN HLT /SAE MODIFIED AC STA B2 /STORE IN C(B2); SAE B HLT /STA MODIFIED AC SAE B2 /CHECK STA HLT /STA FAILED LS2, AZE I /AC = B HLT /AZE I FAILED COM /THE NUMBERS + AND - 0 ARE NEVER USED AZE I / HLT /AZE I FAILED OR COM FAILED COM SAE B2 / HLT /AZE, MODIFIED AC OR COM FAILED APO /SHOULD SKIP COM /COMP IF NEG (APO FAILED) APO /SHOULD SKIP HLT /APO FAILED CLR AZE HLT /AZE FAILED COM AZE HLT /AZE FAILED APO I HLT /APO I FAILED LS3, CLR /CLEAR AC, LINK LZE HLT /CLR OR LZE FAILED SAE B LZE /AC - 0, B + 0 HLT /SAE SKIPPED IN ERROR APO I LZE /AC IS POSITIVE HLT /APO SKIPPED IN ERROR LS4, CLR /CLEAR AC, LINK LDA B COM /COMP AC SAE B LZE HLT /COM, SAE FAILED COM SAE B HLT /COM OR SAE FAILED NOP SAE B HLT /NOP SKIPPED IN ERROR OR CHANGED AC LZE HLT /NOP CHANGED LINK SC1, LDA B /NUMBER TO AC ROL /ROTATE NO PLACES SAE B /CHECK THE NUMBER HLT /ROL ROTATED IN ERROR ROL 14 /ROTATE 12 PLACES SAE B /GIVES SAME NUMBER HLT /ROL FAILED SC2, CLR /CLEAR AC AND LINK LDA B /LOAD NUMBER ROR /ROTATE NO PLACES SAE B /NUMBER CHANGED? HLT /ROR ROTATED IN ERROR ROR 14 /ROTATE 12 PLACES SAE B /GIVES SAME NUMBER HLT /ROR FAILED LZE /LINK WAS CLEARED AT SC2 HLT /ROTATE SET LINK IN ERROR SC3, CLR /CLEAR AC COM /COMP AC ROL I 1 /SET THE LINK LDA B /GET NUMBER ROR 17 /GO LEFT AND ROL 17 /RIGHT AN EQUAL SAE B /NUMBER OF PLACES HLT /ROL, ROR FAILED LZE I /TEST LINK HLT /LZE, CLR, ETC SC4, CLR /CLEAR AC AND LINK LDA B /LOAD AC ROR I 15 SAE B /ROTATE 13 DECIMAL HLT /TIMES LZE /LINK MODIFIED? HLT /ROR 13 SET LINK IN ERROR SC5, LDA B /LOAD AC ROL I 15 SAE B /ROTATE 13 GIVES SAME NUMBER HLT /ROL I 13 CHANGED AC SC6, LDA B /LOAD AC SCR 14 /SCALE RIGHT; THIS SHOULD AZE /EXTEND THE SIGN HLT /AC - +/-0 IN ERROR LDA B COM /LOAD COMP SCR 14 /AC SHOULD EQUAL AZE /+/- ZERO HLT /NOT = +/-ZERO SC7, LDA B ROL I 1 /HIGH ORDER BIT TO AC LDA B /SIMULATE SCALE ROR I 1 /VIA ROR, ROL STA B2 /SAVE IN TEMPORARY REGISTER CLR /CLEAR LINK LDA B SCR 1 /SCALE RIGHT SAE B2 /CHECK WITH SIMULATE HLT /SCR FAILED LZE /CONTENTS OF LINK HLT /MODIFIED SC8, LDA B STA B2 /STORE IN TEMPORARY SRO B2 /ROTATE TEMPORARY NOP ROR 1 /ROTATE AC SAE B2 /C(Y) C(AC) SHOULD BE THE SAME HLT /SRO CHANGED C(Y) OR C(AC) SC9, LDA B STA B2 /STORE IN TEMPORARY ROR 1 /ROTATE RIGHT MOST SRO B2 /TO AC SIGN, SRO, COM /SKIP IF SIGN ZERO APO /TEST THE BIT HLT /SRO CHANGED SIGN SCA, LDA B /TEST SCR I 1 STA B2 /WILL THE LAST SCR I 1 /BIT GO TO SRO B2 /THE LINK JMP .+4 /USE SRO TO LZE /FIND THE LAST HLT /BIT & SCR I JMP .+3 LZE I /SRO SAYS BIT A HLT /ONE SCR I AA1, LDA B /ADD VALUES THE COM /RESULT SHOULD EQUAL ZERO ADA / NUM AZE HLT /ADA FAILED AA2, CLR COM /SET TO ALL ONES ADA B SAE B /CHECK END CARRY HLT /END CARRY FAILED AA3, CLR /CLEAR AC AND LINK COM ADA B ADA B /MULTIPLY VIA ADD ROR 1 /DIVIDE BY 2, VIA ROR SAE B HLT /ADDITION FAILED AA4, LDA B ADA I 7777 /AC = -ZERO SAE B HLT /ADDITION OF -0 FAILED AA5, LDA B /USE ADD AND ADA ROR 6 /ADD ALL THE NUMBERS ADD NUM /C(B) = NUM COM ADA B ROL 6 COM SAE B HLT /ADDITION, ADD OR ADA AA6, LZE /LINK SET, SEE HLT /AA3 TO AA6 STC TEM /STORE RESULT IN TEM AZE HLT /STC FAILED TO CLEAR AC LDA B2 /C(B2) = TEM SAE B / HLT /STC FAILED TO STORE AA7, LDA B /PUT NUMBER IN STA B2 /AC AND C(TEM) ADM B2 /ADD TO MEM AND AC ROR 1 SAE B /IS AC CORRECT HLT /ADM FAILED ROL 1 /IS MEMORY SAME AS AC SAE B2 / HLT /ADM FAILED LZE HLT /SEE AA6, AA7 AA8, CLR /CLEAR AC, LINK STA B2 /CLEAR TEMPORARY LDA B /LOAD NUMBER LAM B2 /AC + (-0) = AC SAE B /LINK WAS ZERO HLT /LAM CHANGED AC IN ERROR LZE /LINK SHOULD BE CLEAR HLT /LAR SET LINK CLR STA B2 /CLEAR AC, LINK, TEMPORARY COM /SET AC ROL I 1 /SET LINK =1, AC=7776 LAM B2 /AC = 7777 LZE HLT /0 TO LINK, LAM FAILED AZE HLT /+1 AC, LAM FAILED AA9, CLR /CLEAR LINK STC .+7 LDA B /TEST LAM STC TEM /STORE IN TEMPORARY LAM B2 SAE B2 HLT /AC+C(Y); LAM FAILED LAM I 0 /ADD IN THE LINK NOP SAE B HLT /LAM FAILED BT, LDA B /LOAD AC BCL B /CLEAR SELECTED BITS AZE HLT /BCL FAILED TO CLEAR LDA B COM BCL B COM /BITS OTHER THAN SAE B /SELECTED BITS CLEARED? HLT /BCL CLEARED IN ERROR BT1, LDA B ROR 6 BCO B /COMP BITS BCO B /RE COMP BITS ROL 6 SAE B HLT /BCO FAILED BT2, LDA B BSE I /SET NO BITS 0 SAE B HLT /BSE SET BITS IN ERROR BSE I /SET ALL BITS 7777 ADA B /-0 + C(B) = C(B) SAE B HLT /BSE FAILED TO SET BITS CLR BSE B SAE B HLT /BSE FAILED BT3, CLR BCO B /LOAD VIA COMP COM /COMP BCO B /COMP THE ZERO AZE HLT /BCO FAILED BCO B /ONES TO ZEROS COM /COMP SAE B HLT /BCO FAILED HW1, CLR STA B2 /CLEAR TEMPORARY LDA I TEM-1+4000 STC B2 /FULL ADDRESS STORE LDA B /NUMBER TO AC ROR 6 STH 20 B2 /PUT IN LEFT HALF ROR 6 STH 20 B2 /PUT IN RIGHT HALF SAE B HLT /STH MODIFIED AC SAE B2 HLT /STH, STORED INCORRECTLY HW2, CLR COM LDH B2 /TEST LDH, RIGHT HALF APO HLT /LEFT AC NOT CLEAR SHD B2 APO HLT /SHD, RIGHT HALF COM SHD B2 /LINK SHOULD BE ZERO HLT /SHD, SKIPPED HW3, CLR SHD I /SKP HALF DIFFERENT 7700 HLT /SHD FAILED TO SKIP LDA B STA B2 /C(B) TO C(B2), 1E TEM LDA I TEM-1+4000 STC B2 AZE HLT /STC SCALE: LDA B ROR 6 SHD I B2 /INCREMENT LZE HLT /SHD I SKIPPED IN ERROR SHD B2 /NO INCREMENT LZE HLT /SWD FAILED TO SKIP ROR 6 SHD I B2 LZE HLT /SHD SKIPPED IN ERROR SHD B2 LZE HLT /NO INCREMENT SHD SAE B HLT /GOOD GRIEF, AGAIN! HW4, CLR SHD I 0077 LZE HLT /SHD I LDA B ROR 6 SHD TEM LZE HLT /SHD ST, LDA B /TEST SET COM SET B2 B COM SAE B HLT /SET DIDN'T WORK CLR ADD B /SET MODIFIED AC SAE B2 HLT /SET FAILED LDA B STC .+2 SET I B2 0 AZE HLT /AC MODIFIED, SET LDA B2 SAE B HLT /SET I FAILED XS1, LDA B STC B2 /STORE IN B2 XSK B2 NOP AZE HLT /AAC ALTERED, XSK LDA B2 SAE B HLT /TEST FOR NOT INCREMENT SET I B2 TEM XS2, LDA B STA B2 /CONSTANT+1 ADD 2 XSK I TEM SAE B2 JMP .+2 JMP .+5 ROL 2 SCR 2 AZE HLT /XSK, INCREMENT SET I B2 1777 CLR /CLEAR LINK XSK B2 HLT /XSK SET I B2 1776 XSK I B2 HLT /XSK XSK I B2 LZE HLT /XSK AZE HLT /AC MODIFIED CLR COM STC B2 XSK I B2 NOP ADD B2 SAE I 6000 HLT /XSK I FAILED SET I B2 10 MSA, LDA B ROR 6 BCO B STA /STORE SIGNS TEM /IN TEM BCO B /RESTORE AC APO /STORE OPERAND COM /AS + NUMBER STC B+1 LDA B APO COM /STORE SECOND STC MSB+3 /OPERAND STC B2 /CLEAR AC STC B2+1 LDA I 3777 STC MS /COUNTER CLR MSB, ADD B2 /MULTIPLY SUBROUTINE ROR I 1 /SCALE RIGHT LINK IS ZERO SRO I 0 /SECOND OPERAND ADD B+1 /ADD IV .-1-- STC B2 /STORE TEMPORARY RESULT ADD B2+1 ROR I 1 /BRING IN LINK STC B2+1 SRO I MS, 0 JMP MSB LDA TEM SCR I 14 /SIGN TO LINK +/-1 TO AC ADD B2 LZE COM /IF SIGNS UNLIKE NOP STC B2 ADD B2+1 /TEM HAS SIGNS LZE /ANS IN B2 COM /AND B2+1 ROR 1 STC B2+1 /END OF SIMULATE MSD, LDA B /ORIGINAL NUMBERS ROR 6 /C(B) AND B(B)-6 MUL B /SIMULATE RESULTS SAE /B2 AND B2+1 B2+1 /MUL, INTEGER HLT /LOW ORDER PRODUCT WRONG LZE COM APO HLT /SIGN, LINK, MUL FAILED MSE, LDA B ROR 6 /ORIGINAL NUMBERS MUL /C(B) AND C(B)-6 4000+10 /SIMULATE RESULTS SAE /B2 + B2+1 B2 HLT /MUL, FRACTIONAL FAILED LZE COM APO HLT /SIGN + LINK MUL FAILED JM1, LDA I /JMP 0 RETURN JMP STC 1777 /JMP OUT AND BACK JMP 1777 SET I B NUM SET I B2 NUM-1 LDA B SAE I B2 HLT /INDEX 1, B, MODE SET I B2 TEM QL1, LDA I 7777 ROR 14 /LOAD MQ TO ONE'S QLZ SKP HLT /QLZ MQ11=1 FAILED QLZ I HLT /QLZ I FAILED TO SKIP CLR QLZ HLT /QLZ FAILED MQ11=0 QLZ I SKP HLT /QLZ I SKIPPED IN ERROR QC1, LDA I 7777 ROR 14 /LOAD MQ TO ONE'S LDA I 0 /CLEAR AC QAC /MQ TO AC 1-11 APO HLT /QAC LOADED AC0 CLR /CLEAR MQ LDA I 4000 /SET AC0 QAC /MQ TO AC 1-11 APO HLT /QAC FAILED TO CLEAR AC0 SW1, LSW /READ THE LEFT SWITCHES SAE I /EQUAL TO 7777? 7777 HLT /LSW FAILED SW2, RSW /READ THE RIGHT SWITCHES SAE I /EQUAL TO 7777? 7777 HLT /RSW FAILED SW3, SNS 0 HLT /SW0 FAILED SNS 1 HLT /SW1 FAILED SNS 2 HLT /SW2 FAILED SNS 3 HLT /SW3 FAILED SNS 4 HLT /SW4 FAILED SNS 5 HLT /SW5 FAILED SW4, SNS I 0 SKP HLT /SW0 SKIPPED IN ERROR SNS I 1 SKP HLT /SW1 SKIPPED IN ERROR SNS I 2 SKP HLT /SW2 SKIPPED IN ERROR SNS I 3 SKP HLT /SW3 SKIPPED IN ERROR SNS I 4 SKP HLT /SW4 SKIPPED IN ERROR SNS I 5 SKP HLT /SW5 SKIPPED IN ERROR F1, LDA 1 /END OF TEST ADM B /INCREMENT B LDA B /TEST FOR LAST TEST VAL SAE I 7777 JMP LS1 /KEEP GOING AZE HLT /SAE I SKIPPED IN ERROR SET I NUM /RESET POINTER-DONT USE ZERO 0001 /CYCLE APPROXIMATELY 8 SECONDS LDA I 0207 /BELL CODE IOB TLS /RING IT JMP LS1 $