High Speed Interrupt Executive
| 8-146
|
R. L. Steel r University of Saskatchewan, Saskatoon,
Saskatchewan, Canada
These routines are designed to handle the priority scheduling
of up to 12 interruptable devices. Each I/O device is
assigned a priority level, and upon receipt of an interrupt
from that device, execution of its routine is initiated. If
the priority of an I/O device "x" is less than that of an I/O
device "y" which is currently being serviced, device "X"
will be queued until "y" has been serviced. These routines
allow a user to prohibit interrupts on any (or all) levels.
| Minimum Hardware: | PDP-8 with EAE
|
| Source Language: | MACRO-8
|
| Storage Requirement: | Three memory pages
|
| Catalog:
| November 1969
|