/FFT-R PATCH PAL8 6/10/71 /FFT-R PATCH MQL=DCA MQ MQA=TAD MQ SHL=JMS I SHLOC LSR=JMS I LLOC ASR1=JMS I AS1LOC MUY=JMS I MPLOC *0566 LSR *0761 ASR1 *0765 ASR1 *0770 MQA *1004 MQL *1014 RAR /PART OF PATCH BELOW *1016 MUY *1020 SHL *1023 TAD SIGN /PATCH TO FIX ROUNDING ERROR; SEE SHL /DECUS 8-143 WRITE-UP 0 1217 /TAD ARG2 SPA CLA CLL CMA RAR NOP SZL CIA 5600 SIGN, 0000 *1063 MQL *1074 LSR *1076 SHL *1111 LSR *1113 SHL *1122 LSR *1124 SHL *1142 ASR1 *1146 ASR1 *1151 MQA *1160 MQL MQA *1171 MQA *0110 MQ, 0 AC, 0 T1, 0 T2, 0 CTR, 0 SHLOC, SH LLOC, LS AS1LOC, AA1 MPLOC, MP KM12, -14 *0200 /EAE SHIFT SIMULATORS LS, 0 /LSR DCA AC TAD I LS CMA DCA CTR ISZ LS LR, TAD AC CLL RAR DCA AC TAD MQ RAR DCA MQ ISZ CTR JMP LR TAD AC CLL /THIS OPERATOR ALWAYS CLEARS THE LINK JMP I LS SH, 0 /SHL DCA AC TAD I SH CMA DCA CTR SHR, TAD MQ CLL RAL DCA MQ TAD AC RAL DCA AC ISZ CTR JMP SHR TAD AC ISZ SH JMP I SH AA1, 0 /ASR ONCE CLL SPA STL RAR DCA AC TAD MQ RAR CLL DCA MQ TAD AC SPA STL ISZ AA1 JMP I AA1 SH1, 0 /SHL ONCE DCA AC TAD MQ CLL RAL DCA MQ TAD AC RAL ISZ SH1 JMP I SH1 MP, 0 /MUY SIMULATOR CLA /ENTER WITH ARGS FOLLOWING CALL AND IN MQ DCA AC /EXIT WITH MOST SIGNIFICANT BITS OF PRODUCT TAD I MP /AND LEAST SIGNIFICANT BITS OF PRODUCT DCA T1 /IN THE MQ ISZ MP TAD KM12 DCA CTR CLL MPREP, TAD MQ RAR DCA MQ TAD AC SNL JMP .+3 CLL TAD T1 RAR DCA AC ISZ CTR JMP MPREP TAD MQ RAR CLL DCA MQ TAD AC JMP I MP $