tester- PDP8 card tester via printer port version 0.91 November 27, 2015 mapping[] is verified Main menu Mon Jul 03 18:20:45 2017 test file is: delay is: 0 trigger is: 1 1 read test file 2 set test delay 3 set test trigger 4 run test 5 output loading test 8 diags 9 exit Enter test file name? trying to open test file: tests\m707d.tst reading test file: tests\m707d.tst comment: M707 PCB REV D SCHEMATIC REV c TELETYPE TRANSMITTER comment: comment: ICs are VERTICAL on PCB REV D. comment: comment: Rev D adds AB1 ECHO input. comment: comment: does not test AV2 20MA OUTPUT, use scope and pulldown comment: comment: or use M707D_MA.TST to test 20MA OUTPUT (needs jumper) comment: pins: PINS pins: 1 O BJ1 +3V pins: 2 I BF2 CLEAR FLAG 2-N (NORMALLY 3V) pins: 3 I BE2 I/O CLEAR (NORMALLY INITIALIZE) pins: 4 I BP2 2 X BAUD CLOCK INPUT pins: 5 I AE1 (DEVICE SELECTOR BMB IN) (NAND)->(DEVICE SELECT-N) (NORMALLY MB04-N) pins: 6 I AE2 (DEVICE SELECTOR BMB IN) (NAND)->(DEVICE SELECT-N) (NORMALLY MB03-N) pins: 7 I AF1 (DEVICE SELECTOR BMB IN) (NAND)->(DEVICE SELECT-N) (NORMALLY MB06) pins: 8 I AF2 (DEVICE SELECTOR BMB IN) (NAND)->(DEVICE SELECT-N) (NORMALLY MB05-N) pins: 9 I AH2 (DEVICE SELECTOR BMB IN) (NAND)->(DEVICE SELECT-N) (NORMALLY MB08-N) pins: 10 I AJ2 (DEVICE SELECTOR BMB IN) (NAND)->(DEVICE SELECT-N) (NORMALLY MB07-N) pins: 11 I AN1 (FORCE SELECT-N) (NORMALLY HI) NAND(DEVICE SELECT-N)=(SELECTED) pins: 12 I BH2 I/O SKP. STROBE (NORMALLY IOT 1) pins: 13 O BJ2 I/O SKP.-N (NAND OF I/O SKP. STROBE, FLAG, DEV DECODE) pins: 14 O BK2 P.I.REQ-N (FLAG-N) pins: 15 I BD2 CLEAR FLAG 1 (NORMALLY IOT 2) pins: 16 I AS1 LOAD BUFFER (NORMALLY IOT 4) pins: 17 I AR1 LOAD BUFFER STROBE-N (NAND SELECTED, LOAD BUFFER) pins: 18 I BS2 WAIT-N (PROLONGS STOP BITS) (NORMALLY 3V) pins: 19 O BR2 STOP 1-N pins: 20 O BP1 STOP 1.5-N pins: 21 O BN1 STOP 2-N pins: 22 I BN2 (STOP SELECT) (MUST BE HI TO SET ACTIVE I.E. TX NEXT CHARACTER) pins: 23 O AJ1 (BIT 6) (CONNECTS TO AK1 FOR 5 BIT OUTPUT) pins: 24 O AK2 (ENABLE) (CONNECTS TO AK1 FOR 8 BIT OUTPUT) pins: 25 I AK1 (CHARACTER LOADED) (MUST BE HI TO SET ACTIVE I.E. TX NEXT CHARACTER) pins: 26 O AL1 (ENABLE-N) (NORMALLY CONNECTS TO DECODE INPUT 8) pins: 27 I AH1 (DECODE INPUT 8) (NORMALLY CONNECTS TO (ENABLE-N) pins: 28 I AN2 ENABLE (NORMALLY 3V) pins: 29 I AP2 BIT 8 (NORMALLY AC4) pins: 30 I AR2 BIT 7 (NORMALLY AC5) pins: 31 I AL2 BIT 6 (NORMALLY AC6) pins: 32 I AM2 BIT 5 (NORMALLY AC7) pins: 33 I AU2 BIT 4 (NORMALLY AC8) pins: 34 I AS2 BIT 3 (NORMALLY AC9) pins: 35 I AT2 BIT 2 (NORMALLY AC10) pins: 36 I AU1 BIT 1 (NORMALLY AC11) pins: 37 O AD1 ACTIVE pins: 38 O AD2 LINE pins: 39 O AV2 20MA OUTPUT (PNP TO +) pins: 40 I AB1 ECHO (ORS WITH LINE -> 20MA OUTPUT) pins: direction: OIIIIIIIIIIIOOIIIIOOOIOOIOIIIIIIIIIIOOOI comment: ; set CLEAR FLAG 2-N, I/O CLEAR comment: ; note: STOP FF outputs are unknown. comment: ; note: 20MA output can not test (open emitter) test 1: 111000000010110011XXX00001110000000001X1 comment: ; remove I/O CLEAR test 2: 0 comment: ; clock 2 X BAUD CLOCK INPUT to set STOP FFs test 3: 1 1 test 4: 0 test 5: 1 1 test 6: 0 test 7: 1 1 test 8: 0 comment: ; set (STOP SELECT since all 3 STOP FFs are HI) test 9: 1 comment: ; comment: ; test DEVICE DECODER comment: ; comment: ; turn on LOAD BUFFER (normally IOP4) test 10: 1 comment: ; comment: ; set up to load ENABLE/55h (alternating ones) comment: ; test 11: 101010101 comment: ; turn on DEVICE ADDRESS bits, LOAD BUFFER STROBE-N goes LO comment: ; (ENABLE) will go HI (note: next CLOCK starts TX...) comment: ; (ENABLE-N) will go LO test 12: 111111 0 1 0 comment: ; (ENABLE-N) is LO so change (DECODE INPUT 8) (normally connects to (ENABLE-N) test 13: 0 comment: ; remove DEVICE ADDRESS, LOAD BUFFER STROBE-N goes HI comment: ; since (ENABLE) is HI, set (CHARACTER LOADED) (normal 8 BIT TX) test 14: 000000 1 1 comment: ; toggle (FORCE SELECT-N), LOAD BUFFER STROBE-N goes LO test 15: 0 0 test 16: 1 1 comment: ; test all DEVICE ADDRESS combinations test 17: 000000 1 test 18: 000001 1 test 19: 000010 1 test 20: 000011 1 test 21: 000100 1 test 22: 000101 1 test 23: 000110 1 test 24: 000111 1 test 25: 001000 1 test 26: 001001 1 test 27: 001010 1 test 28: 001011 1 test 29: 001100 1 test 30: 001101 1 test 31: 001110 1 test 32: 001111 1 test 33: 010000 1 test 34: 010001 1 test 35: 010010 1 test 36: 010011 1 test 37: 010100 1 test 38: 010101 1 test 39: 010110 1 test 40: 010111 1 test 41: 011000 1 test 42: 011001 1 test 43: 011010 1 test 44: 011011 1 test 45: 011100 1 test 46: 011101 1 test 47: 011110 1 test 48: 011111 1 test 49: 100000 1 test 50: 100001 1 test 51: 100010 1 test 52: 100011 1 test 53: 100100 1 test 54: 100101 1 test 55: 100110 1 test 56: 100111 1 test 57: 101000 1 test 58: 101001 1 test 59: 101010 1 test 60: 101011 1 test 61: 101100 1 test 62: 101101 1 test 63: 101110 1 test 64: 101111 1 test 65: 110000 1 test 66: 110001 1 test 67: 110010 1 test 68: 110011 1 test 69: 110100 1 test 70: 110101 1 test 71: 110110 1 test 72: 110111 1 test 73: 111000 1 test 74: 111001 1 test 75: 111010 1 test 76: 111011 1 test 77: 111100 1 test 78: 111101 1 test 79: 111110 1 test 80: 111111 0 comment: ; remove LOAD BUFFER (normally IOP4) test 81: 01 comment: ; remove DEVICE ADDRESS test 82: 000000 comment: ; comment: ; comment: ; send the 0x55 character comment: ; comment: ; comment: ; on first 2 X BAUD CLOCK INPUT comment: ; ACTIVE is SET, causes LINE to CLEAR (i.e. START BIT). comment: ; test 83: 1 10 test 84: 0 comment: ; the 2nd 2 X BAUD CLOCK INPUT causes the STOP FFs to PRESET test 85: 1 000 test 86: 0 comment: ; ORGINAL BIT 1 (AC11) goes to LINE comment: ; (BIT 6) shifts comment: ; (ENABLE) goes LO, (ENABLE-N) goes HI test 87: 1 10 1 1 comment: ; since (ENABLE) is LO, change (CHARACTER LOADED) (i.e. 8 not 5) test 88: 0 comment: ; (ENABLE-N) is HI so change (DECODE INPUT 8) (normally connects to (ENABLE-N) test 89: 1 test 90: 0 test 91: 1 test 92: 0 comment: ; ORGINAL BIT 2 (AC10) goes to LINE test 93: 1 0 0 test 94: 0 test 95: 1 test 96: 0 comment: ; ORGINAL BIT 3 (AC9) goes to LINE comment: ; (BIT 6) shifts test 97: 1 1 1 test 98: 0 test 99: 1 test 100: 0 comment: ; ORGINAL BIT 4 (AC8) goes to LINE test 101: 1 0 0 test 102: 0 test 103: 1 test 104: 0 comment: ; ORGINAL BIT 5 (AC7) goes to LINE comment: ; test 105: 1 0 1 test 106: 0 test 107: 1 test 108: 0 comment: ; ORGINAL BIT 6 (AC6) goes to LINE test 109: 1 0 test 110: 0 test 111: 1 test 112: 0 comment: ; ORGINAL BIT 7 (AC5) goes to LINE test 113: 1 1 test 114: 0 test 115: 1 test 116: 0 comment: ; ORGINAL BIT 8 (AC4) goes to LINE test 117: 1 0 test 118: 0 test 119: 1 test 120: 0 comment: ; ORGINAL (ENABLE) goes to LINE (STOP BITS) comment: ; (ACTIVE) goes LO comment: ; P.I.REQ-N (FLAG-N) goes LO...FLAG is ON test 121: 1 0 01 test 122: 0 comment: ; STOP FFs bits start counting... test 123: 1 1 test 124: 0 test 125: 1 1 test 126: 0 test 127: 1 1 comment: ; since STOP 2-N went HI, set (STOP SELECT) (i.e. 2 STOP BITS) test 128: 1 test 129: 0 test 130: 1 test 131: 0 comment: ; comment: ; try the I/O SKIP comment: ; comment: ; turn on DEVICE ADDRESS bits test 132: 111111 comment: ; toggle I/O SKP.STROBE I/O SKP.-N pulses LO (active) test 133: 10 test 134: 01 comment: ; turn off DEVICE ADDRESS bits test 135: 000000 comment: ; toggle I/O SKP.STROBE- I/O SKP.-N stays HI (inactive) test 136: 1 test 137: 0 comment: ; turn on DEVICE ADDRESS bits test 138: 111111 comment: ; set I/O SKP. STROBE, I/O SKP.-N goes LO test 139: 10 comment: ; clear the FLAG- pulse CLEAR FLAG 1, I/O SKP.-n goes HI comment: ; P.I.REQ-N (FLAG-N) goes HI...FLAG is OFF test 140: 111 test 141: 0 comment: ; turn off I/O SKP. STROBE test 142: 0 comment: ; turn off DEVICE ADDRESS bits test 143: 000000 test 144: 11000000001011001111110001110101010101X1 comment: ; comment: ; comment: ; send a 0xAA comment: ; comment: ; comment: ; set up to load ENABLE/0xAA (alternating ones) test 145: 110101010 comment: ; turn on DEVICE ADDRESS bits test 146: 111111 comment: ; turn on LOAD BUFFER (normally IOP4) comment: ; LOAD BUFFER STROBE-N goes LO comment: ; (BIT 6) goes HI comment: ; (ENABLE) goes HI (note: next CLOCK starts TX...) comment: ; (ENABLE-N) goes LO test 147: 10 11 0 comment: ; (ENABLE) is HI, so set (CHARACTER LOADED) (normal 8 BIT TX) test 148: 1 comment: ; (ENABLE-N) is LO, so change (DECODE INPUT 8) (normally connects to (ENABLE-N) test 149: 0 comment: ; remove LOAD BUFFER (normally IOP4) test 150: 01 comment: ; remove DEVICE ADDRESS test 151: 000000 comment: ; comment: ; shift out the 0xAA character comment: ; comment: ; on first 2 X BAUD CLOCK INPUT comment: ; ACTIVE is SET, causes LINE to CLEAR (i.e. START BIT). comment: ; test 152: 1 10 test 153: 0 comment: ; the 2nd 2 X BAUD CLOCK INPUT causes the STOP FFs to PRESET test 154: 1 000 test 155: 0 comment: ; ORGINAL BIT 1 (AC11) goes to LINE comment: ; (BIT 6) shifts comment: ; (ENABLE) goes LO, (ENABLE-N) goes HI test 156: 1 00 1 0 comment: ; since (ENABLE) is LO, change (CHARACTER LOADED) (i.e. 8 not 5) test 157: 0 comment: ; since (ENABLE-N) is HI, change (DECODE INPUT 8) (normally connects to (ENABLE-N) test 158: 1 test 159: 0 test 160: 1 test 161: 0 comment: ; ORGINAL BIT 2 (AC10) goes to LINE test 162: 1 1 1 test 163: 0 test 164: 1 test 165: 0 comment: ; ORGINAL BIT 3 (AC9) goes to LINE comment: ; (BIT 6) becomes original ENABLE test 166: 1 1 0 test 167: 0 test 168: 1 test 169: 0 comment: ; ORGINAL BIT 4 (AC8) goes to LINE comment: ; (BIT 6) goes LO test 170: 1 0 1 test 171: 0 test 172: 1 test 173: 0 comment: ; ORGINAL BIT 5 (AC7) goes to LINE comment: ; test 174: 1 0 0 test 175: 0 test 176: 1 test 177: 0 comment: ; ORGINAL BIT 6 (AC6) goes to LINE test 178: 1 1 test 179: 0 test 180: 1 test 181: 0 comment: ; ORGINAL BIT 7 (AC5) goes to LINE test 182: 1 0 test 183: 0 test 184: 1 test 185: 0 comment: ; ORGINAL BIT 8 (AC4) goes to LINE test 186: 1 1 test 187: 0 test 188: 1 test 189: 0 comment: ; ORGINAL (ENABLE) goes to LINE (STOP BITS) comment: ; (ACTIVE) goes LO comment: ; P.I.REQ-N (FLAG-N) goes LO...FLAG is ON test 190: 1 0 01 test 191: 0 comment: ; STOP FFs bits start counting... test 192: 1 1 test 193: 0 test 194: 1 1 test 195: 0 test 196: 1 1 comment: ; since STOP 2-N went HI, set (STOP SELECT) (i.e. 2 STOP BITS) test 197: 1 test 198: 0 test 199: 1 test 200: 0 comment: ; comment: ; try the I/O SKIP comment: ; comment: ; turn on DEVICE ADDRESS bits test 201: 111111 comment: ; toggle I/O SKP.STROBE I/O SKP.-N pulses LO (active) test 202: 10 test 203: 01 comment: ; turn off DEVICE ADDRESS bits test 204: 000000 comment: ; toggle I/O SKP.STROBE- I/O SKP.-N stays HI (inactive) test 205: 1 test 206: 0 comment: ; turn on DEVICE ADDRESS bits test 207: 111111 comment: ; set I/O SKP. STROBE, I/O SKP.-N goes LO test 208: 10 comment: ; clear the FLAG- pulse CLEAR FLAG 1, I/O SKP.-n goes HI comment: ; P.I.REQ-N (FLAG-N) goes HI...FLAG is OFF test 209: 111 test 210: 0 comment: ; turn off I/O SKP. STROBE test 211: 0 comment: ; turn off DEVICE ADDRESS bits test 212: 000000 test 213: 11000000001011001111110001110101010101X1 comment: ; comment: ; comment: ; send a 0x00 comment: ; comment: ; comment: ; set up to load ENABLE/0x00 (all zeroes) test 214: 100000000 comment: ; turn on DEVICE ADDRESS bits test 215: 111111 comment: ; turn on LOAD BUFFER (normally IOP4) comment: ; LOAD BUFFER STROBE-N goes LO comment: ; (BIT 6) goes LO comment: ; (ENABLE) goes HI (note: next CLOCK starts TX...) comment: ; (ENABLE-N) goes LO test 216: 10 01 0 comment: ; (ENABLE) is HI, so set (CHARACTER LOADED) (normal 8 BIT TX) test 217: 1 comment: ; (ENABLE-N) is LO, so change (DECODE INPUT 8) (normally connects to (ENABLE-N) test 218: 0 comment: ; remove LOAD BUFFER (normally IOP4) test 219: 01 comment: ; remove DEVICE ADDRESS test 220: 000000 comment: ; comment: ; shift out the 0x00 character comment: ; comment: ; on first 2 X BAUD CLOCK INPUT comment: ; ACTIVE is SET, causes LINE to CLEAR (i.e. START BIT). comment: ; test 221: 1 10 test 222: 0 comment: ; the 2nd 2 X BAUD CLOCK INPUT causes the STOP FFs to PRESET test 223: 1 000 test 224: 0 comment: ; ORGINAL BIT 1 (AC11) goes to LINE comment: ; (BIT 6) shifts comment: ; (ENABLE) goes LO, (ENABLE-N) goes HI test 225: 1 00 1 0 comment: ; since (ENABLE) is LO, change (CHARACTER LOADED) (i.e. 8 not 5) test 226: 0 comment: ; since (ENABLE-N) is HI, change (DECODE INPUT 8) (normally connects to (ENABLE-N) test 227: 1 test 228: 0 test 229: 1 test 230: 0 comment: ; ORGINAL BIT 2 (AC10) goes to LINE test 231: 1 0 0 test 232: 0 test 233: 1 test 234: 0 comment: ; ORGINAL BIT 3 (AC9) goes to LINE comment: ; (BIT 6) becomes original ENABLE test 235: 1 1 0 test 236: 0 test 237: 1 test 238: 0 comment: ; ORGINAL BIT 4 (AC8) goes to LINE comment: ; (BIT 6) goes LO test 239: 1 0 0 test 240: 0 test 241: 1 test 242: 0 comment: ; ORGINAL BIT 5 (AC7) goes to LINE comment: ; test 243: 1 0 0 test 244: 0 test 245: 1 test 246: 0 comment: ; ORGINAL BIT 6 (AC6) goes to LINE test 247: 1 0 test 248: 0 test 249: 1 test 250: 0 comment: ; ORGINAL BIT 7 (AC5) goes to LINE test 251: 1 0 test 252: 0 test 253: 1 test 254: 0 comment: ; ORGINAL BIT 8 (AC4) goes to LINE test 255: 1 0 test 256: 0 test 257: 1 test 258: 0 comment: ; ORGINAL (ENABLE) goes to LINE (STOP BITS) comment: ; (ACTIVE) goes LO comment: ; P.I.REQ-N (FLAG-N) goes LO...FLAG is ON test 259: 1 0 01 test 260: 0 comment: ; STOP FFs bits start counting... test 261: 1 1 test 262: 0 test 263: 1 1 test 264: 0 test 265: 1 1 comment: ; since STOP 2-N went HI, set (STOP SELECT) (i.e. 2 STOP BITS) test 266: 1 test 267: 0 test 268: 1 test 269: 0 comment: ; comment: ; try the I/O SKIP comment: ; comment: ; turn on DEVICE ADDRESS bits test 270: 111111 comment: ; toggle I/O SKP.STROBE I/O SKP.-N pulses LO (active) test 271: 10 test 272: 01 comment: ; turn off DEVICE ADDRESS bits test 273: 000000 comment: ; toggle I/O SKP.STROBE- I/O SKP.-N stays HI (inactive) test 274: 1 test 275: 0 comment: ; turn on DEVICE ADDRESS bits test 276: 111111 comment: ; set I/O SKP. STROBE, I/O SKP.-N goes LO test 277: 10 comment: ; clear the FLAG- pulse CLEAR FLAG 1, I/O SKP.-n goes HI comment: ; P.I.REQ-N (FLAG-N) goes HI...FLAG is OFF test 278: 111 test 279: 0 comment: ; turn off I/O SKP. STROBE test 280: 0 comment: ; turn off DEVICE ADDRESS bits test 281: 000000 test 282: 11000000001011001111110001110101010101X1 comment: ; comment: ; comment: ; send a 0xFF comment: ; comment: ; comment: ; set up to load ENABLE/0xFF (all ones) test 283: 111111111 comment: ; turn on DEVICE ADDRESS bits test 284: 111111 comment: ; turn on LOAD BUFFER (normally IOP4) comment: ; LOAD BUFFER STROBE-N goes LO comment: ; (BIT 6) goes HI comment: ; (ENABLE) goes HI (note: next CLOCK starts TX...) comment: ; (ENABLE-N) goes LO test 285: 10 11 0 comment: ; (ENABLE) is HI, so set (CHARACTER LOADED) (normal 8 BIT TX) test 286: 1 comment: ; (ENABLE-N) is LO, so change (DECODE INPUT 8) (normally connects to (ENABLE-N) test 287: 0 comment: ; remove LOAD BUFFER (normally IOP4) test 288: 01 comment: ; remove DEVICE ADDRESS test 289: 000000 comment: ; comment: ; shift out the 0x00 character comment: ; comment: ; on first 2 X BAUD CLOCK INPUT comment: ; ACTIVE is SET, causes LINE to CLEAR (i.e. START BIT). comment: ; test 290: 1 10 test 291: 0 comment: ; the 2nd 2 X BAUD CLOCK INPUT causes the STOP FFs to PRESET test 292: 1 000 test 293: 0 comment: ; ORGINAL BIT 1 (AC11) goes to LINE comment: ; (BIT 6) shifts comment: ; (ENABLE) goes LO, (ENABLE-N) goes HI test 294: 1 10 1 1 comment: ; since (ENABLE) is LO, change (CHARACTER LOADED) (i.e. 8 not 5) test 295: 0 comment: ; since (ENABLE-N) is HI, change (DECODE INPUT 8) (normally connects to (ENABLE-N) test 296: 1 test 297: 0 test 298: 1 test 299: 0 comment: ; ORGINAL BIT 2 (AC10) goes to LINE test 300: 1 1 1 test 301: 0 test 302: 1 test 303: 0 comment: ; ORGINAL BIT 3 (AC9) goes to LINE comment: ; (BIT 6) becomes original ENABLE test 304: 1 1 1 test 305: 0 test 306: 1 test 307: 0 comment: ; ORGINAL BIT 4 (AC8) goes to LINE comment: ; (BIT 6) goes LO test 308: 1 0 1 test 309: 0 test 310: 1 test 311: 0 comment: ; ORGINAL BIT 5 (AC7) goes to LINE comment: ; test 312: 1 1 test 313: 0 test 314: 1 test 315: 0 comment: ; ORGINAL BIT 6 (AC6) goes to LINE test 316: 1 1 test 317: 0 test 318: 1 test 319: 0 comment: ; ORGINAL BIT 7 (AC5) goes to LINE test 320: 1 1 test 321: 0 test 322: 1 test 323: 0 comment: ; ORGINAL BIT 8 (AC4) goes to LINE test 324: 1 1 test 325: 0 test 326: 1 test 327: 0 comment: ; ORGINAL (ENABLE) goes to LINE (STOP BITS) comment: ; (ACTIVE) goes LO comment: ; P.I.REQ-N (FLAG-N) goes LO...FLAG is ON test 328: 1 0 01 test 329: 0 comment: ; STOP FFs bits start counting... test 330: 1 1 test 331: 0 test 332: 1 1 test 333: 0 test 334: 1 1 comment: ; since STOP 2-N went HI, set (STOP SELECT) (i.e. 2 STOP BITS) test 335: 1 test 336: 0 test 337: 1 test 338: 0 comment: ; comment: ; try the I/O SKIP comment: ; comment: ; turn on DEVICE ADDRESS bits test 339: 111111 comment: ; toggle I/O SKP.STROBE I/O SKP.-N pulses LO (active) test 340: 10 test 341: 01 comment: ; turn off DEVICE ADDRESS bits test 342: 000000 comment: ; toggle I/O SKP.STROBE- I/O SKP.-N stays HI (inactive) test 343: 11 test 344: 01 comment: ; turn on DEVICE ADDRESS bits test 345: 111111 comment: ; set I/O SKP. STROBE, I/O SKP.-N goes LO test 346: 10 comment: ; clear the FLAG- pulse CLEAR FLAG 1, I/O SKP.-n goes HI comment: ; P.I.REQ-N (FLAG-N) goes HI...FLAG is OFF test 347: 111 test 348: 0 comment: ; turn off I/O SKP. STROBE test 349: 0 comment: ; turn off DEVICE ADDRESS bits test 350: 000000 test 351: 11000000001011001111110001110101010101X1 comment: ; comment: ; test ECHO input (need to scope AV2 20MA OUTPUT) comment: ; comment: ; set ECHO-N lo, 20MA OUTPUT goes LO test 352: X0 test 353: X1 end: END summary column 1: offset 3, mask 0x4000 column 2: offset 2, mask 0x0080 column 3: offset 2, mask 0x0040 column 4: offset 3, mask 0x0040 column 5: offset 0, mask 0x0800 column 6: offset 0, mask 0x0008 column 7: offset 0, mask 0x0400 column 8: offset 0, mask 0x0004 column 9: offset 0, mask 0x0002 column 10: offset 0, mask 0x0001 column 11: offset 1, mask 0x1000 column 12: offset 3, mask 0x0001 column 13: offset 3, mask 0x0002 column 14: offset 3, mask 0x0004 column 15: offset 2, mask 0x0020 column 16: offset 1, mask 0x0200 column 17: offset 1, mask 0x0400 column 18: offset 4, mask 0x0001 column 19: offset 3, mask 0x0080 column 20: offset 3, mask 0x0200 column 21: offset 3, mask 0x0400 column 22: offset 3, mask 0x0020 column 23: offset 0, mask 0x0100 column 24: offset 1, mask 0x0001 column 25: offset 1, mask 0x8000 column 26: offset 1, mask 0x4000 column 27: offset 0, mask 0x0200 column 28: offset 1, mask 0x0008 column 29: offset 1, mask 0x0010 column 30: offset 1, mask 0x0020 column 31: offset 1, mask 0x0002 column 32: offset 1, mask 0x0004 column 33: offset 2, mask 0x0001 column 34: offset 1, mask 0x0040 column 35: offset 1, mask 0x0080 column 36: offset 2, mask 0x8000 column 37: offset 0, mask 0x1000 column 38: offset 0, mask 0x0010 column 39: offset 2, mask 0x0002 column 40: offset 0, mask 0x4000 direction bits (1=input) 0xB1F0 0x6901 0x7F1A 0xFF9E 0xF0FE pullup bits (1=pullup) 0x0000 0x0000 0x0000 0x0000 0x0000 test step out_data dont care 1: 0x4210 0x5408 0x00C0 0x4006 0x0001 0x0000 0x0000 0x0002 0x0680 0x0000 2: 0x4210 0x5408 0x0080 0x4006 0x0001 0x0000 0x0000 0x0002 0x0680 0x0000 3: 0x4210 0x5408 0x0080 0x40C6 0x0001 0x0000 0x0000 0x0002 0x0600 0x0000 4: 0x4210 0x5408 0x0080 0x4086 0x0001 0x0000 0x0000 0x0002 0x0600 0x0000 5: 0x4210 0x5408 0x0080 0x42C6 0x0001 0x0000 0x0000 0x0002 0x0400 0x0000 6: 0x4210 0x5408 0x0080 0x4286 0x0001 0x0000 0x0000 0x0002 0x0400 0x0000 7: 0x4210 0x5408 0x0080 0x46C6 0x0001 0x0000 0x0000 0x0002 0x0000 0x0000 8: 0x4210 0x5408 0x0080 0x4686 0x0001 0x0000 0x0000 0x0002 0x0000 0x0000 9: 0x4210 0x5408 0x0080 0x46A6 0x0001 0x0000 0x0000 0x0002 0x0000 0x0000 10: 0x4210 0x5608 0x0080 0x46A6 0x0001 0x0000 0x0000 0x0002 0x0000 0x0000 11: 0x4210 0x566C 0x8080 0x46A6 0x0001 0x0000 0x0000 0x0002 0x0000 0x0000 12: 0x4E1F 0x126D 0x8080 0x46A6 0x0001 0x0000 0x0000 0x0002 0x0000 0x0000 13: 0x4C1F 0x126D 0x8080 0x46A6 0x0001 0x0000 0x0000 0x0002 0x0000 0x0000 14: 0x4010 0x966D 0x8080 0x46A6 0x0001 0x0000 0x0000 0x0002 0x0000 0x0000 15: 0x4010 0x826D 0x8080 0x46A6 0x0001 0x0000 0x0000 0x0002 0x0000 0x0000 16: 0x4010 0x966D 0x8080 0x46A6 0x0001 0x0000 0x0000 0x0002 0x0000 0x0000 17: 0x4010 0x966D 0x8080 0x46A6 0x0001 0x0000 0x0000 0x0002 0x0000 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0x5210 0x54FE 0x8081 0x4026 0x0001 0x0000 0x0000 0x0002 0x0000 0x0000 326: 0x5210 0x54FE 0x8081 0x4066 0x0001 0x0000 0x0000 0x0002 0x0000 0x0000 327: 0x5210 0x54FE 0x8081 0x4026 0x0001 0x0000 0x0000 0x0002 0x0000 0x0000 328: 0x4210 0x54FE 0x8081 0x4062 0x0001 0x0000 0x0000 0x0002 0x0000 0x0000 329: 0x4210 0x54FE 0x8081 0x4022 0x0001 0x0000 0x0000 0x0002 0x0000 0x0000 330: 0x4210 0x54FE 0x8081 0x40E2 0x0001 0x0000 0x0000 0x0002 0x0000 0x0000 331: 0x4210 0x54FE 0x8081 0x40A2 0x0001 0x0000 0x0000 0x0002 0x0000 0x0000 332: 0x4210 0x54FE 0x8081 0x42E2 0x0001 0x0000 0x0000 0x0002 0x0000 0x0000 333: 0x4210 0x54FE 0x8081 0x42A2 0x0001 0x0000 0x0000 0x0002 0x0000 0x0000 334: 0x4210 0x54FE 0x8081 0x46E2 0x0001 0x0000 0x0000 0x0002 0x0000 0x0000 335: 0x4210 0x54FE 0x8081 0x46E2 0x0001 0x0000 0x0000 0x0002 0x0000 0x0000 336: 0x4210 0x54FE 0x8081 0x46A2 0x0001 0x0000 0x0000 0x0002 0x0000 0x0000 337: 0x4210 0x54FE 0x8081 0x46E2 0x0001 0x0000 0x0000 0x0002 0x0000 0x0000 338: 0x4210 0x54FE 0x8081 0x46A2 0x0001 0x0000 0x0000 0x0002 0x0000 0x0000 339: 0x4E1F 0x54FE 0x8081 0x46A2 0x0001 0x0000 0x0000 0x0002 0x0000 0x0000 340: 0x4E1F 0x54FE 0x8081 0x46A1 0x0001 0x0000 0x0000 0x0002 0x0000 0x0000 341: 0x4E1F 0x54FE 0x8081 0x46A2 0x0001 0x0000 0x0000 0x0002 0x0000 0x0000 342: 0x4210 0x54FE 0x8081 0x46A2 0x0001 0x0000 0x0000 0x0002 0x0000 0x0000 343: 0x4210 0x54FE 0x8081 0x46A3 0x0001 0x0000 0x0000 0x0002 0x0000 0x0000 344: 0x4210 0x54FE 0x8081 0x46A2 0x0001 0x0000 0x0000 0x0002 0x0000 0x0000 345: 0x4E1F 0x54FE 0x8081 0x46A2 0x0001 0x0000 0x0000 0x0002 0x0000 0x0000 346: 0x4E1F 0x54FE 0x8081 0x46A1 0x0001 0x0000 0x0000 0x0002 0x0000 0x0000 347: 0x4E1F 0x54FE 0x80A1 0x46A7 0x0001 0x0000 0x0000 0x0002 0x0000 0x0000 348: 0x4E1F 0x54FE 0x8081 0x46A7 0x0001 0x0000 0x0000 0x0002 0x0000 0x0000 349: 0x4E1F 0x54FE 0x8081 0x46A6 0x0001 0x0000 0x0000 0x0002 0x0000 0x0000 350: 0x4210 0x54FE 0x8081 0x46A6 0x0001 0x0000 0x0000 0x0002 0x0000 0x0000 351: 0x4210 0x546C 0x8080 0x46A6 0x0001 0x0000 0x0000 0x0002 0x0000 0x0000 352: 0x0210 0x546C 0x8080 0x46A6 0x0001 0x0000 0x0000 0x0002 0x0000 0x0000 353: 0x4210 0x546C 0x8080 0x46A6 0x0001 0x0000 0x0000 0x0002 0x0000 0x0000 PINs used (in edge connector order) (G=ground,P=power) SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBB LETTER ABCDEFHJKLMNPRSTUVABCDEFHJKLMNPRSTUVABCDEFHJKLMNPRSTUVABCDEFHJKLMNPRSTUV SIDE 111111111111111111222222222222222222111111111111111111222222222222222222 USAGE I OIIIOIO I IIGI P GOIIIIOIIIIIIIIO O OO G P GIIIIOO IIOI UUT inputs: 28 UUT outputs: 12 pins used: 40 not used: 26 353 'test steps' 643 lines M707 PCB REV D SCHEMATIC REV c TELETYPE TRANSMITTER ICs are VERTICAL on PCB REV D. Rev D adds AB1 ECHO input. does not test AV2 20MA OUTPUT, use scope and pulldown or use M707D_MA.TST to test 20MA OUTPUT (needs jumper) PINS Main menu Mon Jul 03 18:21:35 2017 test file is: tests\m707d.tst delay is: 0 trigger is: 1 1 read test file 2 set test delay 3 set test trigger 4 run test 5 output loading test 8 diags 9 exit UUT power is okay Mon Jul 03 18:21:37 2017 space single step O run once (one test, all steps) F run, stop on fail G go (run tests N run, stop on fail, no print S scope (run, no print) C turn on comment printout + increase speed (less delay) - decrease speed (more delay)(slower) Q quit test scope (run, no print) pppppppppppppppppppppppppppppp space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn on comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT BBBBAAAAAAABBBBAABBBBBAAAAAAAAAAAAAAAAAA LETTER JFEPEEFFHJNHJKDSRSRPNNJKKLHNPRLMUSTUDDVB SIDE 1222121222122221122112121112222222211221 DIRECTION OIIIIIIIIIIIOOIIIIOOOIOOIOIIIIIIIIIIOOOI all fails was lo 000000000000000 000000000 0000000000 0 falling vvvvvvvvvvvvvvv vvvvvvvvv vvvvvvvvvv v rising ^^^^^^^^^^^^^^^ ^^^^^^^^^ ^^^^^^^^^^ ^ was hi 1111111111111111111111111111111111111111 total fails 0, total passes 30 Main menu Mon Jul 03 18:21:44 2017 test file is: tests\m707d.tst delay is: 0 trigger is: 1 1 read test file 2 set test delay 3 set test trigger 4 run test 5 output loading test 8 diags 9 exit exiting tester- PDP8 card tester via printer port version 0.91 November 27, 2015 mapping[] is verified Main menu Thu Jul 06 09:14:07 2017 test file is: delay is: 0 trigger is: 1 1 read test file 2 set test delay 3 set test trigger 4 run test 5 output loading test 8 diags 9 exit Enter test file name? trying to open test file: tests\m706k.tst reading test file: tests\m706k.tst comment: M706 PCB REV K SCHEMATIC REV L TELETYPE RECEIVER comment: comment: NOTE: 17 PINS not used comment: 1 AA1 PAD, NOT CONNECTED comment: 2 AB1 NOT CONNECTED comment: 3 AC1 NOT CONNECTED comment: 4 AU1 NOT CONNECTED comment: 5 AB2 NOT CONNECTED comment: 6 BA1 NOT CONNECTED comment: 7 BB1 NOT CONNECTED comment: 8 BC1 NOT CONNECTED comment: 9 BE1 NOT CONNECTED comment: 10 BF1 NOT CONNECTED comment: 11 BH1 NOT CONNECTED comment: 12 BJ1 NOT CONNECTED comment: 13 BK1 NOT CONNECTED comment: 14 BL1 PAD, NOT CONNECTED comment: 15 BV1 PAD, NOT CONNECTED comment: 16 BB2 NOT CONNECTED comment: 17 BK2 NOT CONNECTED CPU schematics shows output TT SHIFT-N comment: pins: PINS pins: 1 O AD1 +3V pins: 2 I AL2 READ BUFFER (NORMALLY IOP4) pins: 3 I AD2 (DEVICE SELECTOR BMB INPUTS) (NAND)-> (DEVICE SELECT-N) pins: 4 I AE1 (DEVICE SELECTOR BMB INPUTS) (NAND)-> (DEVICE SELECT-N) pins: 5 I AF1 (DEVICE SELECTOR BMB INPUTS) (NAND)-> (DEVICE SELECT-N) pins: 6 I AH1 (DEVICE SELECTOR BMB INPUTS) (NAND)-> (DEVICE SELECT-N) pins: 7 I AH2 (DEVICE SELECTOR BMB INPUTS) (NAND)-> (DEVICE SELECT-N) pins: 8 I AJ1 (DEVICE SELECTOR BMB INPUTS) (NAND)-> (DEVICE SELECT-N) pins: 9 I AP1 (FORCE SELECT-N) (NORMALLY HI) NAND(DEVICE SELECT-N)=(SELECTED) pins: 10 I BF2 I/O CLEAR (NORMALLY INITIALIZE) pins: 11 I BJ2 CLEAR FLAG 1 (NORMALLY IOP2) pins: 12 O BE2 (SELECTED IOP2-N) = CLEAR FLAG 1 NAND (SELECTED) pins: 13 I BD1 CLEAR FLAG 2 (NORMALLY CONNECTED TO GROUND) pins: 14 O AE2 (KCC-N) = (SELECTED IOP2) NOR I/O CLEAR NOR CLEAR FLAG 2 pins: 15 O AV1 BUFFER STROBE = READ BUFFER AND (SELECTED) pins: 16 I BM1 (EXTRA IN) (NOT USED? ON CPU SCHEMATIC) pins: 17 O BN1 (EXTRA-N) = (EXTRA IN) NAND BUFFER STROBE pins: 18 I BD2 SKP. STROBE (NORMALLY IOP1) pins: 19 O AF2 FLAG-N (AKA P.I. REQUEST) pins: 20 O BH2 I/O SKIP = FLAG NAND SKP. STROBE NAND (SELECTED) (ACTIVE LO) pins: 21 I AV2 (READER RUN SET-N) (NORMALLY CONNECTED TO (KCC-N)) pins: 22 O BL2 READER RUN pins: 23 O AU2 READER ENABLE CANNOT TEST (PNP HI DRIVER; 26MA @1V; OPEN (-15?) pins: 24 O BN2 (ACTIVE-N) (AKA IN ACTIVE ON CPU SCHEMATIC) pins: 25 O BS2 (PRESET-N) = (200NS?) PULSE ON ACTIVE-N FALLING EDGE pins: 26 I AN1 CLOCK 8 BAUD pins: 27 O BS1 CLOCK SCALE 2-N (CLOCK 8 BAUD / 4) NORMALLY DRIVES (STOP CLOCK) pins: 28 O BT2 CLOCK SCALE 2 (CLOCK 8 BAUD DIVIDED BY 4) pins: 29 I BP2 (STOP CLOCK) (<-CLOCK SCALE 2-N FOR 0.5 STOP; -P FOR X.0) pins: 30 I BP1 (STOP SET-N) (NORMALLY +3?) pins: 31 O BU2 STOP 1-N pins: 32 O BV2 STOP 2-N (NORMALLY DRIVES IN LAST UNIT) pins: 33 I BR2 IN LAST UNIT CLEAR-N (<-STOP 1-N FOR 1.X STOP; STOP 2-N FOR 2) pins: 34 I BM2 TELETYPE SERIAL INPUT pins: 35 O AM2 (TELETYPE SERIAL INPUT-N) pins: 36 I BR1 ENABLE (NORMALLY +3V (33)) pins: 37 I AR1 (TT0 DATA) (NORMALLY CONNECTED TO (TELETYPE SERIAL INPUT-N) pins: 38 O AK1 (TT2) (NORMALLY CONNECTED TO AJ2 (TT3 DATA) FOR 8 BIT DATA) pins: 39 I AJ2 (TT3 DATA) =(DATA IN) FOR 5 BIT; = (TT2) FOR 8 BIT pins: 40 I BU1 SHIFT CLOCK (NORMALLY CLOCK SCALE 2) pins: 41 O AS1 TT SHIFT (100NS? PULSE) AKA SHIFT ON CPU SCHEMATIC pins: 42 O AK2 TT0-N (MSB) = TT0 NAND BUFFER STROBE pins: 43 O AR2 TT1-N = TT0 NAND BUFFER STROBE pins: 44 O AS2 TT2-N = TT0 NAND BUFFER STROBE pins: 45 O AL1 TT3-N = TT0 NAND BUFFER STROBE pins: 46 O AM1 TT4-N = TT0 NAND BUFFER STROBE pins: 47 O AP2 TT5-N = TT0 NAND BUFFER STROBE pins: 48 O AT2 TT6-N = TT0 NAND BUFFER STROBE pins: 49 O AN2 TT7-N (LSB) = TT0 NAND BUFFER STROBE pins: direction: OIIIIIIIIIIOIOOIOIOOIOOOOIOOIIOOIIOIIOIIOOOOOOOOO comment: ; note COLUMN 21 PIN AU2 is PNP hi side driver; can not test comment: ; I/O CLEAR hi comment: ; (READER RUN SET-N) low to set READER RUN (not normal powerup) comment: ; (STOP SET-N) low to set STOP 1 and STOP 2 (not normal powerup) comment: ; IN LAST UNIT CLEAR-N low to clear CLOCK SCALE 1 and CLOCK SCALE 2 test 1: 1000000011010000101101X11010000000101X00011111111 comment: ; toggle TELETYPE SERIAL INPUT with I/O CLEAR active -> no change test 2: 10 comment: ; have (TT0 DATA) track (TELETYPE SERIAL INPUT-N) test 3: 0 test 4: 01 comment: ; have (TT0 DATA) track (TELETYPE SERIAL INPUT-N) test 5: 1 comment: ; comment: ; undo the initial setup that is not normal powerup comment: ; comment: ; release I/O CLEAR; (KCC-N) goes hi test 6: 0 1 comment: ; release (STOP SET-N) test 7: 1 comment: ; release (READER RUN SET-N) test 8: 1 comment: ; release IN LAST UNIT CLEAR-N test 9: 1 comment: ; check that STOP 1, STOP 2 do not count when not ACTIVE comment: ; clock (STOP CLOCK). since ACTIVE-N is 1; no count STOP 1; STOP 2 test 10: 1 test 11: 0 comment: ; clock CLOCK 8 BAUD to set (CLOCK SCALE 0) test 12: 1 test 13: 0 comment: ; set/clear CLEAR FLAG 2; (KCC-N) goes lo/hi test 14: 10 test 15: 01 comment: ; comment: ; check 'not selected' does not change comment: ; set/clear READ BUFFER -> no change (not selected) test 16: 1 test 17: 0 comment: ; set/clear (EXTRA IN) -> no change (not selected) test 18: 1 test 19: 0 comment: ; set/clear CLEAR FLAG 1 -> no change (not selected) test 20: 1 test 21: 0 comment: ; set/clear SKP. STROBE -> no change (not selected) test 22: 1 test 23: 0 comment: ; comment: ; forced select tests comment: ; comment: ; (FORCE SELECT-N) test 24: 0 comment: ; set CLEAR FLAG 1 -> (SELECTED IOP2-N) lo; (KCC-N) lo test 25: 10 0 comment: ; clear/set (FORCE SELECT-N) -> (SELECTED IOP2-N) hi/lo; (KCC-N) hi/lo test 26: 1 1 1 test 27: 0 0 0 comment: ; set READ BUFFER -> BUFFFER STROBE goes hi; TTn-N go to ?? test 28: 1 1 XXXXXXXX comment: ; set (EXTRA IN) -. (EXTRA-N) goes lo test 29: 10 comment: ; clear READ BUFFER -> BUFFER STROBE goes lo; (EXTRA-N) goes hi test 30: 0 0 1 11111111 comment: ; set READ BUFFER -> BUFFER STROBE goes hi; (EXTRA-N) goes ho test 31: 1 1 0 XXXXXXXX comment: ; set SKP. STROBE -> no change (flag is off) test 32: 1 comment: ; remove force select -> (SELECTED IOP2-N),(KCC-N),(EXTRA-N) hi; BUFFER STROBE lo test 33: 1 1 10 1 11111111 comment: ; comment: ; check device select comment: ; comment: ; device select -> (SELECTED IOP2-N),(KCC-N),(EXTRA-N) lo; BUFFER STROBE hi test 34: 100000 test 35: 110000 test 36: 111000 test 37: 111100 test 38: 111110 test 39: 111111 0 01 0 XXXXXXXX test 40: 011111 1 10 1 11111111 test 41: 001111 test 42: 000111 test 43: 000011 test 44: 000001 test 45: 000000 test 46: 111111 0 01 0 XXXXXXXX test 47: 011111 1 10 1 11111111 test 48: 111111 0 01 0 XXXXXXXX test 49: 101111 1 10 1 11111111 test 50: 111111 0 01 0 XXXXXXXX test 51: 110111 1 10 1 11111111 test 52: 111111 0 01 0 XXXXXXXX test 53: 111011 1 10 1 11111111 test 54: 111111 0 01 0 XXXXXXXX test 55: 111101 1 10 1 11111111 test 56: 111111 0 01 0 XXXXXXXX test 57: 111110 1 10 1 11111111 test 58: 111111 0 01 0 XXXXXXXX test 59: 000000 1 10 1 11111111 test 60: 000001 test 61: 000010 test 62: 000011 test 63: 000100 test 64: 000101 test 65: 000110 test 66: 000111 test 67: 001000 test 68: 001001 test 69: 001010 test 70: 001011 test 71: 001100 test 72: 001101 test 73: 001110 test 74: 001111 test 75: 010000 test 76: 010001 test 77: 010010 test 78: 010011 test 79: 010100 test 80: 010101 test 81: 010110 test 82: 010111 test 83: 011000 test 84: 011001 test 85: 011010 test 86: 011011 test 87: 011100 test 88: 011101 test 89: 011110 test 90: 011111 test 91: 100000 test 92: 100001 test 93: 100010 test 94: 100011 test 95: 100100 test 96: 100101 test 97: 100110 test 98: 100111 test 99: 101000 test 100: 101001 test 101: 101010 test 102: 101011 test 103: 101100 test 104: 101101 test 105: 101110 test 106: 101111 test 107: 110000 test 108: 110001 test 109: 110010 test 110: 110011 test 111: 110100 test 112: 110101 test 113: 110110 test 114: 110111 test 115: 111000 test 116: 111001 test 117: 111010 test 118: 111011 test 119: 111100 test 120: 111101 test 121: 111110 test 122: 111111 0 01 0 XXXXXXXX comment: ; remove CLEAR FLAG 1 while selected -> (SELECTED IOP2-N) hi; (KCC-N) hi test 123: 01 1 comment: ; remove (EXTRA IN) -> (EXTRA-N) goes hi test 124: 01 comment: ; remove READ BUFFER -> BUFFER STROBE lo; TTn-N go hi test 125: 0 0 11111111 comment: ; deselect test 126: 000000 0 comment: ; comment: ; test the start bit detect gate comment: ; comment: ; verify each signal does not falsely start bit detect with START ENABLE hi comment: ; comment: ; make sure they are off test 127: 0 010 comment: ; set/clear TELETYPE SERIAL INPUT -> no change comment: ; set/clear ENABLE -> no change test 128: 1 test 129: 0 test 130: 10 test 131: 01 comment: ; set/clear CLOCK 8 BAUD -> no change test 132: 1 test 133: 0 comment: ; comment: ; verify each signal inhibits start bit detect with START ENABLE hi comment: ; comment: ; set ENABLE -> no change test 134: 1 comment: ; set/clear TELETYPE SERIAL INPUT -> no change test 135: 10 test 136: 01 comment: ; set/clear CLOCK 8 BAUD -> no change test 137: 1 test 138: 0 comment: ; clear ENABLE test 139: 0 comment: ; set CLOCK 8 BAUD -> no change test 140: 1 comment: ; set/clear TELETYPE SERIAL INPUT -> no change test 141: 10 test 142: 01 comment: ; clear CLOCK 8 BAUD -> no change test 143: 0 comment: ; comment: ; do START BIT detect comment: ; comment: ; set CLOCK 8 BAUD test 144: 1 comment: ; set ENABLE test 145: 1 comment: ; prestage (TT0 DATA) due to clock edge test 146: 0 comment: ; set TELETYPE SERIAL INPUT -> comment: ; READER RUN,ACTIVE-N,STOP 1-N,STOP 2-N go lo test 147: 0 0 11 10 comment: ; select and READ BUFFER -> BUFFER STROBE hi, TTn-N go lo test 148: 1111111 1 1 00000000 comment: ; set (TT5 DATA) to match TT6 test 149: 1 comment: ; CLOCK 8 BAUD to toggle CLOCK SCALE 2-N and CLOCK SCALE 2 test 150: 0 test 151: 1 test 152: 0 test 153: 1 test 154: 0 test 155: 101 test 156: 0 test 157: 1 test 158: 0 test 159: 1 test 160: 0 test 161: 1 test 162: 0 test 163: 110 comment: ; leave CLOCK SCALE 2 set test 164: 0 test 165: 1 test 166: 0 test 167: 1 test 168: 0 test 169: 1 test 170: 0 test 171: 101 comment: ; (STOP CLOCK) does not change STOP 1, STOP 2 since ACTIVE test 172: 1 test 173: 0 test 174: 1 test 175: 0 comment: ; clear TELETYPE SERIAL INPUT (do a short START BT) test 176: 01 comment: ; have (TT0 DATA) track (TELETYPE SERIAL INPUT-N) test 177: 1 comment: ; SHIFT CLOCK to shift 1 (short START BIT sets SPIKE DETECTOR) comment: ; note: ACTIVE-N goes hi AFTER rising edge due to SPIKE DETECTOR comment: ; and CLOCK SCLE 2 gets cleared test 178: 1 10 1 1 00000000 test 179: 0 comment: ; comment: ; receive a '00000000' character comment: ; comment: ; prestage (TT0 DATA) due to clock edge test 180: 0 comment: ; set TELETYPE SERIAL INPUT (START BIT) -> comment: ; READER RUN,ACTIVE-N,TT0-N go lo; STOP 1-N,STOP 2-N go hi comment: ; note: (TT2) is value AFTER rising clock test 181: 0 0 11 10 0 comment: ; CLOCK 8 BAUD to setup CLOCK SCALE 2-N lo; CLOCK SCALE 2 hi test 182: 0 test 183: 1 test 184: 0 test 185: 1 test 186: 0 test 187: 1 test 188: 0 test 189: 101 comment: ; toggle SHIFT CLOCK -> shift in a '00000000' character test 190: 1 10000000 test 191: 0 comment: test 192: 1 11000000 test 193: 0 test 194: 0 1 11100000 comment: ; clear (TT3 DATA) to match TT2 test 195: 0 test 196: 0 test 197: 1 11110000 test 198: 0 test 199: 1 11111000 test 200: 0 test 201: 1 11111100 test 202: 0 test 203: 1 11111110 test 204: 0 test 205: 1 11111111 test 206: 0 comment: ; shift start bit into FLAG -> I/O SKIP lo, FLAG-N (aka P.I. REQUEST) lo test 207: 00 1 comment: ; turn off READ BUFFER -> BUFFER STROBE lo, (TTn-N still hi) test 208: 0 0 test 209: 1 1 comment: ; disable SKP. STROBE -> I/O SKIP goes hi test 210: 0 1 comment: ; on SHIFT CLOCK falling edge, ACTIVE-N hi test 211: 1 0 comment: ; clear TELETYPE SERIAL INPUT (stop bit); set TT0 DATA test 212: 01 comment: ; have (TT0 DATA) track (TELETYPE SERIAL INPUT-N) test 213: 1 test 214: 1 test 215: 0 test 216: 1 test 217: 0 comment: ; IN LAST UNIT CLEAR-N -> CLOCK SCALE 2 lo; CLOCK SCALE 2-N hi test 218: 10 0 comment: ; comment: ; receive a '11111111' character comment: ; comment: ;;;;;;;;;;;;;;;;;;;;;; comment: ; end: END summary column 1: offset 0, mask 0x1000 column 2: offset 1, mask 0x0002 column 3: offset 0, mask 0x0010 column 4: offset 0, mask 0x0800 column 5: offset 0, mask 0x0400 column 6: offset 0, mask 0x0200 column 7: offset 0, mask 0x0002 column 8: offset 0, mask 0x0100 column 9: offset 1, mask 0x0800 column 10: offset 2, mask 0x0080 column 11: offset 3, mask 0x0002 column 12: offset 2, mask 0x0040 column 13: offset 2, mask 0x0400 column 14: offset 0, mask 0x0008 column 15: offset 2, mask 0x4000 column 16: offset 3, mask 0x0800 column 17: offset 3, mask 0x0400 column 18: offset 2, mask 0x0020 column 19: offset 0, mask 0x0004 column 20: offset 3, mask 0x0001 column 21: offset 2, mask 0x0002 column 22: offset 3, mask 0x0008 column 23: offset 2, mask 0x0001 column 24: offset 3, mask 0x0020 column 25: offset 4, mask 0x0001 column 26: offset 1, mask 0x1000 column 27: offset 4, mask 0x8000 column 28: offset 4, mask 0x0002 column 29: offset 3, mask 0x0040 column 30: offset 3, mask 0x0200 column 31: offset 4, mask 0x0004 column 32: offset 4, mask 0x0008 column 33: offset 3, mask 0x0080 column 34: offset 3, mask 0x0010 column 35: offset 1, mask 0x0004 column 36: offset 3, mask 0x0100 column 37: offset 1, mask 0x0400 column 38: offset 1, mask 0x8000 column 39: offset 0, mask 0x0001 column 40: offset 4, mask 0x2000 column 41: offset 1, mask 0x0200 column 42: offset 1, mask 0x0001 column 43: offset 1, mask 0x0020 column 44: offset 1, mask 0x0040 column 45: offset 1, mask 0x4000 column 46: offset 1, mask 0x2000 column 47: offset 1, mask 0x0010 column 48: offset 1, mask 0x0080 column 49: offset 1, mask 0x0008 direction bits (1=input) 0xF0EC 0xE3FD 0xFB59 0xF42D 0xD0FF pullup bits (1=pullup) 0x0000 0x0000 0x0000 0x0000 0x0000 test step out_data dont care 1: 0x1004 0x6CFD 0x00C0 0x0429 0x8001 0x0000 0x8000 0x0001 0x0000 0x0000 2: 0x1004 0x6CF9 0x00C0 0x0439 0x8001 0x0000 0x8000 0x0001 0x0000 0x0000 3: 0x1004 0x68F9 0x00C0 0x0439 0x8001 0x0000 0x8000 0x0001 0x0000 0x0000 4: 0x1004 0x68FD 0x00C0 0x0429 0x8001 0x0000 0x8000 0x0001 0x0000 0x0000 5: 0x1004 0x6CFD 0x00C0 0x0429 0x8001 0x0000 0x8000 0x0001 0x0000 0x0000 6: 0x100C 0x6CFD 0x0040 0x0429 0x8001 0x0000 0x8000 0x0001 0x0000 0x0000 7: 0x100C 0x6CFD 0x0040 0x0629 0x8001 0x0000 0x8000 0x0001 0x0000 0x0000 8: 0x100C 0x6CFD 0x0042 0x0629 0x8001 0x0000 0x8000 0x0001 0x0000 0x0000 9: 0x100C 0x6CFD 0x0042 0x06A9 0x8001 0x0000 0x8000 0x0001 0x0000 0x0000 10: 0x100C 0x6CFD 0x0042 0x06E9 0x8001 0x0000 0x8000 0x0001 0x0000 0x0000 11: 0x100C 0x6CFD 0x0042 0x06A9 0x8001 0x0000 0x8000 0x0001 0x0000 0x0000 12: 0x100C 0x7CFD 0x0042 0x06A9 0x8001 0x0000 0x8000 0x0001 0x0000 0x0000 13: 0x100C 0x6CFD 0x0042 0x06A9 0x8001 0x0000 0x8000 0x0001 0x0000 0x0000 14: 0x1004 0x6CFD 0x0442 0x06A9 0x8001 0x0000 0x8000 0x0001 0x0000 0x0000 15: 0x100C 0x6CFD 0x0042 0x06A9 0x8001 0x0000 0x8000 0x0001 0x0000 0x0000 16: 0x100C 0x6CFF 0x0042 0x06A9 0x8001 0x0000 0x8000 0x0001 0x0000 0x0000 17: 0x100C 0x6CFD 0x0042 0x06A9 0x8001 0x0000 0x8000 0x0001 0x0000 0x0000 18: 0x100C 0x6CFD 0x0042 0x0EA9 0x8001 0x0000 0x8000 0x0001 0x0000 0x0000 19: 0x100C 0x6CFD 0x0042 0x06A9 0x8001 0x0000 0x8000 0x0001 0x0000 0x0000 20: 0x100C 0x6CFD 0x0042 0x06AB 0x8001 0x0000 0x8000 0x0001 0x0000 0x0000 21: 0x100C 0x6CFD 0x0042 0x06A9 0x8001 0x0000 0x8000 0x0001 0x0000 0x0000 22: 0x100C 0x6CFD 0x0062 0x06A9 0x8001 0x0000 0x8000 0x0001 0x0000 0x0000 23: 0x100C 0x6CFD 0x0042 0x06A9 0x8001 0x0000 0x8000 0x0001 0x0000 0x0000 24: 0x100C 0x64FD 0x0042 0x06A9 0x8001 0x0000 0x8000 0x0001 0x0000 0x0000 25: 0x1004 0x64FD 0x0002 0x06AB 0x8001 0x0000 0x8000 0x0001 0x0000 0x0000 26: 0x100C 0x6CFD 0x0042 0x06AB 0x8001 0x0000 0x8000 0x0001 0x0000 0x0000 27: 0x1004 0x64FD 0x0002 0x06AB 0x8001 0x0000 0x8000 0x0001 0x0000 0x0000 28: 0x1004 0x0406 0x4002 0x06AB 0x8001 0x0000 0xE0F9 0x0001 0x0000 0x0000 29: 0x1004 0x0406 0x4002 0x0AAB 0x8001 0x0000 0xE0F9 0x0001 0x0000 0x0000 30: 0x1004 0x64FD 0x0002 0x0EAB 0x8001 0x0000 0x8000 0x0001 0x0000 0x0000 31: 0x1004 0x0406 0x4002 0x0AAB 0x8001 0x0000 0xE0F9 0x0001 0x0000 0x0000 32: 0x1004 0x0406 0x4022 0x0AAB 0x8001 0x0000 0xE0F9 0x0001 0x0000 0x0000 33: 0x100C 0x6CFF 0x0062 0x0EAB 0x8001 0x0000 0x8000 0x0001 0x0000 0x0000 34: 0x101C 0x6CFF 0x0062 0x0EAB 0x8001 0x0000 0x8000 0x0001 0x0000 0x0000 35: 0x181C 0x6CFF 0x0062 0x0EAB 0x8001 0x0000 0x8000 0x0001 0x0000 0x0000 36: 0x1C1C 0x6CFF 0x0062 0x0EAB 0x8001 0x0000 0x8000 0x0001 0x0000 0x0000 37: 0x1E1C 0x6CFF 0x0062 0x0EAB 0x8001 0x0000 0x8000 0x0001 0x0000 0x0000 38: 0x1E1E 0x6CFF 0x0062 0x0EAB 0x8001 0x0000 0x8000 0x0001 0x0000 0x0000 39: 0x1F16 0x0C06 0x4022 0x0AAB 0x8001 0x0000 0xE0F9 0x0001 0x0000 0x0000 40: 0x1F0E 0x6CFF 0x0062 0x0EAB 0x8001 0x0000 0x8000 0x0001 0x0000 0x0000 41: 0x170E 0x6CFF 0x0062 0x0EAB 0x8001 0x0000 0x8000 0x0001 0x0000 0x0000 42: 0x130E 0x6CFF 0x0062 0x0EAB 0x8001 0x0000 0x8000 0x0001 0x0000 0x0000 43: 0x110E 0x6CFF 0x0062 0x0EAB 0x8001 0x0000 0x8000 0x0001 0x0000 0x0000 44: 0x110C 0x6CFF 0x0062 0x0EAB 0x8001 0x0000 0x8000 0x0001 0x0000 0x0000 45: 0x100C 0x6CFF 0x0062 0x0EAB 0x8001 0x0000 0x8000 0x0001 0x0000 0x0000 46: 0x1F16 0x0C06 0x4022 0x0AAB 0x8001 0x0000 0xE0F9 0x0001 0x0000 0x0000 47: 0x1F0E 0x6CFF 0x0062 0x0EAB 0x8001 0x0000 0x8000 0x0001 0x0000 0x0000 48: 0x1F16 0x0C06 0x4022 0x0AAB 0x8001 0x0000 0xE0F9 0x0001 0x0000 0x0000 49: 0x171E 0x6CFF 0x0062 0x0EAB 0x8001 0x0000 0x8000 0x0001 0x0000 0x0000 50: 0x1F16 0x0C06 0x4022 0x0AAB 0x8001 0x0000 0xE0F9 0x0001 0x0000 0x0000 51: 0x1B1E 0x6CFF 0x0062 0x0EAB 0x8001 0x0000 0x8000 0x0001 0x0000 0x0000 52: 0x1F16 0x0C06 0x4022 0x0AAB 0x8001 0x0000 0xE0F9 0x0001 0x0000 0x0000 53: 0x1D1E 0x6CFF 0x0062 0x0EAB 0x8001 0x0000 0x8000 0x0001 0x0000 0x0000 54: 0x1F16 0x0C06 0x4022 0x0AAB 0x8001 0x0000 0xE0F9 0x0001 0x0000 0x0000 55: 0x1F1C 0x6CFF 0x0062 0x0EAB 0x8001 0x0000 0x8000 0x0001 0x0000 0x0000 56: 0x1F16 0x0C06 0x4022 0x0AAB 0x8001 0x0000 0xE0F9 0x0001 0x0000 0x0000 57: 0x1E1E 0x6CFF 0x0062 0x0EAB 0x8001 0x0000 0x8000 0x0001 0x0000 0x0000 58: 0x1F16 0x0C06 0x4022 0x0AAB 0x8001 0x0000 0xE0F9 0x0001 0x0000 0x0000 59: 0x100C 0x6CFF 0x0062 0x0EAB 0x8001 0x0000 0x8000 0x0001 0x0000 0x0000 60: 0x110C 0x6CFF 0x0062 0x0EAB 0x8001 0x0000 0x8000 0x0001 0x0000 0x0000 61: 0x100E 0x6CFF 0x0062 0x0EAB 0x8001 0x0000 0x8000 0x0001 0x0000 0x0000 62: 0x110E 0x6CFF 0x0062 0x0EAB 0x8001 0x0000 0x8000 0x0001 0x0000 0x0000 63: 0x120C 0x6CFF 0x0062 0x0EAB 0x8001 0x0000 0x8000 0x0001 0x0000 0x0000 64: 0x130C 0x6CFF 0x0062 0x0EAB 0x8001 0x0000 0x8000 0x0001 0x0000 0x0000 65: 0x120E 0x6CFF 0x0062 0x0EAB 0x8001 0x0000 0x8000 0x0001 0x0000 0x0000 66: 0x130E 0x6CFF 0x0062 0x0EAB 0x8001 0x0000 0x8000 0x0001 0x0000 0x0000 67: 0x140C 0x6CFF 0x0062 0x0EAB 0x8001 0x0000 0x8000 0x0001 0x0000 0x0000 68: 0x150C 0x6CFF 0x0062 0x0EAB 0x8001 0x0000 0x8000 0x0001 0x0000 0x0000 69: 0x140E 0x6CFF 0x0062 0x0EAB 0x8001 0x0000 0x8000 0x0001 0x0000 0x0000 70: 0x150E 0x6CFF 0x0062 0x0EAB 0x8001 0x0000 0x8000 0x0001 0x0000 0x0000 71: 0x160C 0x6CFF 0x0062 0x0EAB 0x8001 0x0000 0x8000 0x0001 0x0000 0x0000 72: 0x170C 0x6CFF 0x0062 0x0EAB 0x8001 0x0000 0x8000 0x0001 0x0000 0x0000 73: 0x160E 0x6CFF 0x0062 0x0EAB 0x8001 0x0000 0x8000 0x0001 0x0000 0x0000 74: 0x170E 0x6CFF 0x0062 0x0EAB 0x8001 0x0000 0x8000 0x0001 0x0000 0x0000 75: 0x180C 0x6CFF 0x0062 0x0EAB 0x8001 0x0000 0x8000 0x0001 0x0000 0x0000 76: 0x190C 0x6CFF 0x0062 0x0EAB 0x8001 0x0000 0x8000 0x0001 0x0000 0x0000 77: 0x180E 0x6CFF 0x0062 0x0EAB 0x8001 0x0000 0x8000 0x0001 0x0000 0x0000 78: 0x190E 0x6CFF 0x0062 0x0EAB 0x8001 0x0000 0x8000 0x0001 0x0000 0x0000 79: 0x1A0C 0x6CFF 0x0062 0x0EAB 0x8001 0x0000 0x8000 0x0001 0x0000 0x0000 80: 0x1B0C 0x6CFF 0x0062 0x0EAB 0x8001 0x0000 0x8000 0x0001 0x0000 0x0000 81: 0x1A0E 0x6CFF 0x0062 0x0EAB 0x8001 0x0000 0x8000 0x0001 0x0000 0x0000 82: 0x1B0E 0x6CFF 0x0062 0x0EAB 0x8001 0x0000 0x8000 0x0001 0x0000 0x0000 83: 0x1C0C 0x6CFF 0x0062 0x0EAB 0x8001 0x0000 0x8000 0x0001 0x0000 0x0000 84: 0x1D0C 0x6CFF 0x0062 0x0EAB 0x8001 0x0000 0x8000 0x0001 0x0000 0x0000 85: 0x1C0E 0x6CFF 0x0062 0x0EAB 0x8001 0x0000 0x8000 0x0001 0x0000 0x0000 86: 0x1D0E 0x6CFF 0x0062 0x0EAB 0x8001 0x0000 0x8000 0x0001 0x0000 0x0000 87: 0x1E0C 0x6CFF 0x0062 0x0EAB 0x8001 0x0000 0x8000 0x0001 0x0000 0x0000 88: 0x1F0C 0x6CFF 0x0062 0x0EAB 0x8001 0x0000 0x8000 0x0001 0x0000 0x0000 89: 0x1E0E 0x6CFF 0x0062 0x0EAB 0x8001 0x0000 0x8000 0x0001 0x0000 0x0000 90: 0x1F0E 0x6CFF 0x0062 0x0EAB 0x8001 0x0000 0x8000 0x0001 0x0000 0x0000 91: 0x101C 0x6CFF 0x0062 0x0EAB 0x8001 0x0000 0x8000 0x0001 0x0000 0x0000 92: 0x111C 0x6CFF 0x0062 0x0EAB 0x8001 0x0000 0x8000 0x0001 0x0000 0x0000 93: 0x101E 0x6CFF 0x0062 0x0EAB 0x8001 0x0000 0x8000 0x0001 0x0000 0x0000 94: 0x111E 0x6CFF 0x0062 0x0EAB 0x8001 0x0000 0x8000 0x0001 0x0000 0x0000 95: 0x121C 0x6CFF 0x0062 0x0EAB 0x8001 0x0000 0x8000 0x0001 0x0000 0x0000 96: 0x131C 0x6CFF 0x0062 0x0EAB 0x8001 0x0000 0x8000 0x0001 0x0000 0x0000 97: 0x121E 0x6CFF 0x0062 0x0EAB 0x8001 0x0000 0x8000 0x0001 0x0000 0x0000 98: 0x131E 0x6CFF 0x0062 0x0EAB 0x8001 0x0000 0x8000 0x0001 0x0000 0x0000 99: 0x141C 0x6CFF 0x0062 0x0EAB 0x8001 0x0000 0x8000 0x0001 0x0000 0x0000 100: 0x151C 0x6CFF 0x0062 0x0EAB 0x8001 0x0000 0x8000 0x0001 0x0000 0x0000 101: 0x141E 0x6CFF 0x0062 0x0EAB 0x8001 0x0000 0x8000 0x0001 0x0000 0x0000 102: 0x151E 0x6CFF 0x0062 0x0EAB 0x8001 0x0000 0x8000 0x0001 0x0000 0x0000 103: 0x161C 0x6CFF 0x0062 0x0EAB 0x8001 0x0000 0x8000 0x0001 0x0000 0x0000 104: 0x171C 0x6CFF 0x0062 0x0EAB 0x8001 0x0000 0x8000 0x0001 0x0000 0x0000 105: 0x161E 0x6CFF 0x0062 0x0EAB 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0x100C 0x7CFD 0x0062 0x06A9 0x8001 0x0000 0x8000 0x0001 0x0000 0x0000 133: 0x100C 0x6CFD 0x0062 0x06A9 0x8001 0x0000 0x8000 0x0001 0x0000 0x0000 134: 0x100C 0x6CFD 0x0062 0x07A9 0x8001 0x0000 0x8000 0x0001 0x0000 0x0000 135: 0x100C 0x6CF9 0x0062 0x07B9 0x8001 0x0000 0x8000 0x0001 0x0000 0x0000 136: 0x100C 0x6CFD 0x0062 0x07A9 0x8001 0x0000 0x8000 0x0001 0x0000 0x0000 137: 0x100C 0x7CFD 0x0062 0x07A9 0x8001 0x0000 0x8000 0x0001 0x0000 0x0000 138: 0x100C 0x6CFD 0x0062 0x07A9 0x8001 0x0000 0x8000 0x0001 0x0000 0x0000 139: 0x100C 0x6CFD 0x0062 0x06A9 0x8001 0x0000 0x8000 0x0001 0x0000 0x0000 140: 0x100C 0x7CFD 0x0062 0x06A9 0x8001 0x0000 0x8000 0x0001 0x0000 0x0000 141: 0x100C 0x7CF9 0x0062 0x06B9 0x8001 0x0000 0x8000 0x0001 0x0000 0x0000 142: 0x100C 0x7CFD 0x0062 0x06A9 0x8001 0x0000 0x8000 0x0001 0x0000 0x0000 143: 0x100C 0x6CFD 0x0062 0x06A9 0x8001 0x0000 0x8000 0x0001 0x0000 0x0000 144: 0x100C 0x7CFD 0x0062 0x06A9 0x8001 0x0000 0x8000 0x0001 0x0000 0x0000 145: 0x100C 0x7CFD 0x0062 0x07A9 0x8001 0x0000 0x8000 0x0001 0x0000 0x0000 146: 0x100C 0x78FD 0x0062 0x07A9 0x8001 0x0000 0x8000 0x0001 0x0000 0x0000 147: 0x100C 0x78F9 0x0062 0x0791 0x800D 0x0000 0x8000 0x0001 0x0000 0x0000 148: 0x1F1E 0x9802 0x4062 0x0791 0x800D 0x0000 0x0000 0x0001 0x0000 0x0000 149: 0x1F1F 0x9802 0x4062 0x0791 0x800D 0x0000 0x0000 0x0001 0x0000 0x0000 150: 0x1F1F 0x8802 0x4062 0x0791 0x800D 0x0000 0x0000 0x0001 0x0000 0x0000 151: 0x1F1F 0x9802 0x4062 0x0791 0x800D 0x0000 0x0000 0x0001 0x0000 0x0000 152: 0x1F1F 0x8802 0x4062 0x0791 0x800D 0x0000 0x0000 0x0001 0x0000 0x0000 153: 0x1F1F 0x9802 0x4062 0x0791 0x800D 0x0000 0x0000 0x0001 0x0000 0x0000 154: 0x1F1F 0x8802 0x4062 0x0791 0x800D 0x0000 0x0000 0x0001 0x0000 0x0000 155: 0x1F1F 0x9802 0x4062 0x0791 0x000F 0x0000 0x0000 0x0001 0x0000 0x0000 156: 0x1F1F 0x8802 0x4062 0x0791 0x000F 0x0000 0x0000 0x0001 0x0000 0x0000 157: 0x1F1F 0x9802 0x4062 0x0791 0x000F 0x0000 0x0000 0x0001 0x0000 0x0000 158: 0x1F1F 0x8802 0x4062 0x0791 0x000F 0x0000 0x0000 0x0001 0x0000 0x0000 159: 0x1F1F 0x9802 0x4062 0x0791 0x000F 0x0000 0x0000 0x0001 0x0000 0x0000 160: 0x1F1F 0x8802 0x4062 0x0791 0x000F 0x0000 0x0000 0x0001 0x0000 0x0000 161: 0x1F1F 0x9802 0x4062 0x0791 0x000F 0x0000 0x0000 0x0001 0x0000 0x0000 162: 0x1F1F 0x8802 0x4062 0x0791 0x000F 0x0000 0x0000 0x0001 0x0000 0x0000 163: 0x1F1F 0x9802 0x4062 0x0791 0x800D 0x0000 0x0000 0x0001 0x0000 0x0000 164: 0x1F1F 0x8802 0x4062 0x0791 0x800D 0x0000 0x0000 0x0001 0x0000 0x0000 165: 0x1F1F 0x9802 0x4062 0x0791 0x800D 0x0000 0x0000 0x0001 0x0000 0x0000 166: 0x1F1F 0x8802 0x4062 0x0791 0x800D 0x0000 0x0000 0x0001 0x0000 0x0000 167: 0x1F1F 0x9802 0x4062 0x0791 0x800D 0x0000 0x0000 0x0001 0x0000 0x0000 168: 0x1F1F 0x8802 0x4062 0x0791 0x800D 0x0000 0x0000 0x0001 0x0000 0x0000 169: 0x1F1F 0x9802 0x4062 0x0791 0x800D 0x0000 0x0000 0x0001 0x0000 0x0000 170: 0x1F1F 0x8802 0x4062 0x0791 0x800D 0x0000 0x0000 0x0001 0x0000 0x0000 171: 0x1F1F 0x9802 0x4062 0x0791 0x000F 0x0000 0x0000 0x0001 0x0000 0x0000 172: 0x1F1F 0x9802 0x4062 0x07D1 0x000F 0x0000 0x0000 0x0001 0x0000 0x0000 173: 0x1F1F 0x9802 0x4062 0x0791 0x000F 0x0000 0x0000 0x0001 0x0000 0x0000 174: 0x1F1F 0x9802 0x4062 0x07D1 0x000F 0x0000 0x0000 0x0001 0x0000 0x0000 175: 0x1F1F 0x9802 0x4062 0x0791 0x000F 0x0000 0x0000 0x0001 0x0000 0x0000 176: 0x1F1F 0x9806 0x4062 0x0781 0x000F 0x0000 0x0000 0x0001 0x0000 0x0000 177: 0x1F1F 0x9C06 0x4062 0x0781 0x000F 0x0000 0x0000 0x0001 0x0000 0x0000 178: 0x1F1F 0x9C06 0x4062 0x07A1 0xA00D 0x0000 0x0000 0x0001 0x0000 0x0000 179: 0x1F1F 0x9C06 0x4062 0x07A1 0x800D 0x0000 0x0000 0x0001 0x0000 0x0000 180: 0x1F1F 0x9806 0x4062 0x07A1 0x800D 0x0000 0x0000 0x0001 0x0000 0x0000 181: 0x1F1F 0x9802 0x4062 0x0791 0x800D 0x0000 0x0000 0x0001 0x0000 0x0000 182: 0x1F1F 0x8802 0x4062 0x0791 0x800D 0x0000 0x0000 0x0001 0x0000 0x0000 183: 0x1F1F 0x9802 0x4062 0x0791 0x800D 0x0000 0x0000 0x0001 0x0000 0x0000 184: 0x1F1F 0x8802 0x4062 0x0791 0x800D 0x0000 0x0000 0x0001 0x0000 0x0000 185: 0x1F1F 0x9802 0x4062 0x0791 0x800D 0x0000 0x0000 0x0001 0x0000 0x0000 186: 0x1F1F 0x8802 0x4062 0x0791 0x800D 0x0000 0x0000 0x0001 0x0000 0x0000 187: 0x1F1F 0x9802 0x4062 0x0791 0x800D 0x0000 0x0000 0x0001 0x0000 0x0000 188: 0x1F1F 0x8802 0x4062 0x0791 0x800D 0x0000 0x0000 0x0001 0x0000 0x0000 189: 0x1F1F 0x9802 0x4062 0x0791 0x000F 0x0000 0x0000 0x0001 0x0000 0x0000 190: 0x1F1F 0x9803 0x4062 0x0791 0x200F 0x0000 0x0000 0x0001 0x0000 0x0000 191: 0x1F1F 0x9803 0x4062 0x0791 0x000F 0x0000 0x0000 0x0001 0x0000 0x0000 192: 0x1F1F 0x9823 0x4062 0x0791 0x200F 0x0000 0x0000 0x0001 0x0000 0x0000 193: 0x1F1F 0x9823 0x4062 0x0791 0x000F 0x0000 0x0000 0x0001 0x0000 0x0000 194: 0x1F1F 0x1863 0x4062 0x0791 0x200F 0x0000 0x0000 0x0001 0x0000 0x0000 195: 0x1F1E 0x1863 0x4062 0x0791 0x200F 0x0000 0x0000 0x0001 0x0000 0x0000 196: 0x1F1E 0x1863 0x4062 0x0791 0x000F 0x0000 0x0000 0x0001 0x0000 0x0000 197: 0x1F1E 0x5863 0x4062 0x0791 0x200F 0x0000 0x0000 0x0001 0x0000 0x0000 198: 0x1F1E 0x5863 0x4062 0x0791 0x000F 0x0000 0x0000 0x0001 0x0000 0x0000 199: 0x1F1E 0x7863 0x4062 0x0791 0x200F 0x0000 0x0000 0x0001 0x0000 0x0000 200: 0x1F1E 0x7863 0x4062 0x0791 0x000F 0x0000 0x0000 0x0001 0x0000 0x0000 201: 0x1F1E 0x7873 0x4062 0x0791 0x200F 0x0000 0x0000 0x0001 0x0000 0x0000 202: 0x1F1E 0x7873 0x4062 0x0791 0x000F 0x0000 0x0000 0x0001 0x0000 0x0000 203: 0x1F1E 0x78F3 0x4062 0x0791 0x200F 0x0000 0x0000 0x0001 0x0000 0x0000 204: 0x1F1E 0x78F3 0x4062 0x0791 0x000F 0x0000 0x0000 0x0001 0x0000 0x0000 205: 0x1F1E 0x78FB 0x4062 0x0791 0x200F 0x0000 0x0000 0x0001 0x0000 0x0000 206: 0x1F1E 0x78FB 0x4062 0x0791 0x000F 0x0000 0x0000 0x0001 0x0000 0x0000 207: 0x1F1A 0x78FB 0x4062 0x0790 0x200F 0x0000 0x0000 0x0001 0x0000 0x0000 208: 0x1F1A 0x78F9 0x0062 0x0790 0x200F 0x0000 0x0000 0x0001 0x0000 0x0000 209: 0x1F1A 0x78FB 0x4062 0x0790 0x200F 0x0000 0x0000 0x0001 0x0000 0x0000 210: 0x1F1A 0x78FB 0x4042 0x0791 0x200F 0x0000 0x0000 0x0001 0x0000 0x0000 211: 0x1F1A 0x78FB 0x4042 0x07B1 0x000F 0x0000 0x0000 0x0001 0x0000 0x0000 212: 0x1F1A 0x78FF 0x4042 0x07A1 0x000F 0x0000 0x0000 0x0001 0x0000 0x0000 213: 0x1F1A 0x7CFF 0x4042 0x07A1 0x000F 0x0000 0x0000 0x0001 0x0000 0x0000 214: 0x1F1A 0x7CFF 0x4042 0x07A1 0x200F 0x0000 0x0000 0x0001 0x0000 0x0000 215: 0x1F1A 0x7CFF 0x4042 0x07A1 0x000F 0x0000 0x0000 0x0001 0x0000 0x0000 216: 0x1F1A 0x7CFF 0x4042 0x07A1 0x200F 0x0000 0x0000 0x0001 0x0000 0x0000 217: 0x1F1A 0x7CFF 0x4042 0x07A1 0x000F 0x0000 0x0000 0x0001 0x0000 0x0000 218: 0x1F1A 0x7CFF 0x4042 0x0721 0x800D 0x0000 0x0000 0x0001 0x0000 0x0000 PINs used (in edge connector order) (G=ground,P=power) SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBB LETTER ABCDEFHJKLMNPRSTUVABCDEFHJKLMNPRSTUVABCDEFHJKLMNPRSTUVABCDEFHJKLMNPRSTUV SIDE 111111111111111111222222222222222222111111111111111111222222222222222222 USAGE OIIIIOOOIIIOG OP GIOOIIOIOOOOOOOI I IOIIOGI P GIOIOI OIOIIOOOO UUT inputs: 23 UUT outputs: 26 pins used: 49 not used: 17 218 'test steps' 397 lines M706 PCB REV K SCHEMATIC REV L TELETYPE RECEIVER NOTE: 17 PINS not used 1 AA1 PAD, NOT CONNECTED 2 AB1 NOT CONNECTED 3 AC1 NOT CONNECTED 4 AU1 NOT CONNECTED 5 AB2 NOT CONNECTED 6 BA1 NOT CONNECTED 7 BB1 NOT CONNECTED 8 BC1 NOT CONNECTED 9 BE1 NOT CONNECTED 10 BF1 NOT CONNECTED 11 BH1 NOT CONNECTED 12 BJ1 NOT CONNECTED 13 BK1 NOT CONNECTED 14 BL1 PAD, NOT CONNECTED 15 BV1 PAD, NOT CONNECTED 16 BB2 NOT CONNECTED 17 BK2 NOT CONNECTED CPU schematics shows output TT SHIFT-N PINS Main menu Thu Jul 06 09:14:16 2017 test file is: tests\m706k.tst delay is: 0 trigger is: 1 1 read test file 2 set test delay 3 set test trigger 4 run test 5 output loading test 8 diags 9 exit UUT power is okay Thu Jul 06 09:14:21 2017 space single step O run once (one test, all steps) F run, stop on fail G go (run tests N run, stop on fail, no print S scope (run, no print) C turn on comment printout + increase speed (less delay) - decrease speed (more delay)(slower) Q quit test scope (run, no print) pppppppppppppppppppppp space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn on comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAAAAAAAABBBBAABBBABABABBABBBBBBBBABAAABAAAAAAAAA LETTER DLDEFHHJPFJEDEVMNDFHVLUNSNSTPPUVRMMRRKJUSKRSLMPTN SIDE 1221112112221211122222222112212222211121122211222 DIRECTION OIIIIIIIIIIOIOOIOIOOIOOOOIOOIIOOIIOIIOIIOOOOOOOOO all fails was lo 00000000000000000000000 000000000000000000000000 falling vvvvvvvvvvvvvvvvvvvvv v vvvvvvvvvvvvvvv vvvvvvvv rising ^^^^^^^^^^^^^^^^^^^^^ ^ ^^^^^^^^^^^^^^^ ^^^^^^^^ was hi 1111111111111111111111 11111111111111111 11111111 total fails 0, total passes 22 Main menu Thu Jul 06 09:15:23 2017 test file is: tests\m706k.tst delay is: 0 trigger is: 1 1 read test file 2 set test delay 3 set test trigger 4 run test 5 output loading test 8 diags 9 exit UUT power is okay Thu Jul 06 09:15:24 2017 space single step O run once (one test, all steps) F run, stop on fail G go (run tests N run, stop on fail, no print S scope (run, no print) C turn on comment printout + increase speed (less delay) - decrease speed (more delay)(slower) Q quit test scope (run, no print) ppppppppppppppppppp space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn on comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAAAAAAAABBBBAABBBABABABBABBBBBBBBABAAABAAAAAAAAA LETTER DLDEFHHJPFJEDEVMNDFHVLUNSNSTPPUVRMMRRKJUSKRSLMPTN SIDE 1221112112221211122222222112212222211121122211222 DIRECTION OIIIIIIIIIIOIOOIOIOOIOOOOIOOIIOOIIOIIOIIOOOOOOOOO all fails was lo 00000000000000000000000 000000000000000000000000 falling vvvvvvvvvvvvvvvvvvvvv v vvvvvvvvvvvvvvv vvvvvvvv rising ^^^^^^^^^^^^^^^^^^^^^ ^ ^^^^^^^^^^^^^^^ ^^^^^^^^ was hi 1111111111111111111111 11111111111111111 11111111 total fails 0, total passes 19 Main menu Thu Jul 06 09:22:43 2017 test file is: tests\m706k.tst delay is: 0 trigger is: 1 1 read test file 2 set test delay 3 set test trigger 4 run test 5 output loading test 8 diags 9 exit exiting tester- PDP8 card tester via printer port version 0.91 November 27, 2015 mapping[] is verified Main menu Thu Jul 06 09:23:55 2017 test file is: delay is: 0 trigger is: 1 1 read test file 2 set test delay 3 set test trigger 4 run test 5 output loading test 8 diags 9 exit Enter test file name? trying to open test file: tests\m617.tst reading test file: tests\m617.tst comment: M617 REV E 6 4-INPUT NAND BUFFERS (48ma) (7440) comment: pins: PINS pins: 1 I AA1 E1-13 pins: 2 I AB1 E1-12 pins: 3 I AC1 E1-10 pins: 4 I AD1 E1-9 pins: 5 O AE1 E1-8 pins: 6 I AF1 E2-13 pins: 7 I AH1 E2-12 pins: 8 I AJ1 E2-10 pins: 9 I AK1 E2-9 pins: 10 O AL1 E2-8 pins: 11 I AM1 E3-13 pins: 12 I AN1 E3-12 pins: 13 I AP1 E3-10 pins: 14 I AR1 E3-9 pins: 15 O AS1 E3-8 pins: 16 I AD2 E1-5 pins: 17 I AE2 E1-4 pins: 18 I AF2 E1-2 pins: 19 I AH2 E1-1 pins: 20 O AJ2 E1-6 pins: 21 I AK2 E2-5 pins: 22 I AL2 E2-4 pins: 23 I AM2 E2-2 pins: 24 I AN2 E2-1 pins: 25 O AP2 E2-6 pins: 26 I AR2 E3-1 pins: 27 I AS2 E3-2 pins: 28 I AT2 E3-4 pins: 29 I AU2 E3-5 pins: 30 O AV2 E3-6 pins: direction: IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO test 1: 000010000100001000010000100001 test 2: 00001 test 3: 00011 test 4: 00101 test 5: 00111 test 6: 01001 test 7: 01011 test 8: 01101 test 9: 01111 test 10: 10001 test 11: 10011 test 12: 10101 test 13: 10111 test 14: 11001 test 15: 11011 test 16: 11101 test 17: 11110 test 18: 00001 test 19: 00001 test 20: 00011 test 21: 00101 test 22: 00111 test 23: 01001 test 24: 01011 test 25: 01101 test 26: 01111 test 27: 10001 test 28: 10011 test 29: 10101 test 30: 10111 test 31: 11001 test 32: 11011 test 33: 11101 test 34: 11110 test 35: 00001 test 36: 00001 test 37: 00011 test 38: 00101 test 39: 00111 test 40: 01001 test 41: 01011 test 42: 01101 test 43: 01111 test 44: 10001 test 45: 10011 test 46: 10101 test 47: 10111 test 48: 11001 test 49: 11011 test 50: 11101 test 51: 11110 test 52: 00001 test 53: 00001 test 54: 00011 test 55: 00101 test 56: 00111 test 57: 01001 test 58: 01011 test 59: 01101 test 60: 01111 test 61: 10001 test 62: 10011 test 63: 10101 test 64: 10111 test 65: 11001 test 66: 11011 test 67: 11101 test 68: 11110 test 69: 00001 test 70: 00001 test 71: 00011 test 72: 00101 test 73: 00111 test 74: 01001 test 75: 01011 test 76: 01101 test 77: 01111 test 78: 10001 test 79: 10011 test 80: 10101 test 81: 10111 test 82: 11001 test 83: 11011 test 84: 11101 test 85: 11110 test 86: 00001 test 87: 00001 test 88: 00011 test 89: 00101 test 90: 00111 test 91: 01001 test 92: 01011 test 93: 01101 test 94: 01111 test 95: 10001 test 96: 10011 test 97: 10101 test 98: 10111 test 99: 11001 test 100: 11011 test 101: 11101 test 102: 11110 test 103: 00001 test 104: 000010000100001000010000100001 test 105: 111101111011110111101111011110 test 106: 00001 test 107: 00011 test 108: 00101 test 109: 00111 test 110: 01001 test 111: 01011 test 112: 01101 test 113: 01111 test 114: 10001 test 115: 10011 test 116: 10101 test 117: 10111 test 118: 11001 test 119: 11011 test 120: 11101 test 121: 11110 test 122: 00001 test 123: 00011 test 124: 00101 test 125: 00111 test 126: 01001 test 127: 01011 test 128: 01101 test 129: 01111 test 130: 10001 test 131: 10011 test 132: 10101 test 133: 10111 test 134: 11001 test 135: 11011 test 136: 11101 test 137: 11110 test 138: 00001 test 139: 00011 test 140: 00101 test 141: 00111 test 142: 01001 test 143: 01011 test 144: 01101 test 145: 01111 test 146: 10001 test 147: 10011 test 148: 10101 test 149: 10111 test 150: 11001 test 151: 11011 test 152: 11101 test 153: 11110 test 154: 00001 test 155: 00011 test 156: 00101 test 157: 00111 test 158: 01001 test 159: 01011 test 160: 01101 test 161: 01111 test 162: 10001 test 163: 10011 test 164: 10101 test 165: 10111 test 166: 11001 test 167: 11011 test 168: 11101 test 169: 11110 test 170: 00001 test 171: 00011 test 172: 00101 test 173: 00111 test 174: 01001 test 175: 01011 test 176: 01101 test 177: 01111 test 178: 10001 test 179: 10011 test 180: 10101 test 181: 10111 test 182: 11001 test 183: 11011 test 184: 11101 test 185: 11110 test 186: 00001 test 187: 00011 test 188: 00101 test 189: 00111 test 190: 01001 test 191: 01011 test 192: 01101 test 193: 01111 test 194: 10001 test 195: 10011 test 196: 10101 test 197: 10111 test 198: 11001 test 199: 11011 test 200: 11101 test 201: 11110 test 202: 111101111011110111101111011110 end: END summary column 1: offset 0, mask 0x8000 column 2: offset 0, mask 0x4000 column 3: offset 0, mask 0x2000 column 4: offset 0, mask 0x1000 column 5: offset 0, mask 0x0800 column 6: offset 0, mask 0x0400 column 7: offset 0, mask 0x0200 column 8: offset 0, mask 0x0100 column 9: offset 1, mask 0x8000 column 10: offset 1, mask 0x4000 column 11: offset 1, mask 0x2000 column 12: offset 1, mask 0x1000 column 13: offset 1, mask 0x0800 column 14: offset 1, mask 0x0400 column 15: offset 1, mask 0x0200 column 16: offset 0, mask 0x0010 column 17: offset 0, mask 0x0008 column 18: offset 0, mask 0x0004 column 19: offset 0, mask 0x0002 column 20: offset 0, mask 0x0001 column 21: offset 1, mask 0x0001 column 22: offset 1, mask 0x0002 column 23: offset 1, mask 0x0004 column 24: offset 1, mask 0x0008 column 25: offset 1, mask 0x0010 column 26: offset 1, mask 0x0020 column 27: offset 1, mask 0x0040 column 28: offset 1, mask 0x0080 column 29: offset 2, mask 0x0001 column 30: offset 2, mask 0x0002 direction bits (1=input) 0x08E1 0x4310 0xFFFA 0xFFFF 0xF0FF pullup bits (1=pullup) 0x0000 0x0000 0x0000 0x0000 0x0000 test step out_data dont care 1: 0x0801 0x4210 0x0002 0x0000 0x0000 2: 0x0801 0x4210 0x0002 0x0000 0x0000 3: 0x1801 0x4210 0x0002 0x0000 0x0000 4: 0x2801 0x4210 0x0002 0x0000 0x0000 5: 0x3801 0x4210 0x0002 0x0000 0x0000 6: 0x4801 0x4210 0x0002 0x0000 0x0000 7: 0x5801 0x4210 0x0002 0x0000 0x0000 8: 0x6801 0x4210 0x0002 0x0000 0x0000 9: 0x7801 0x4210 0x0002 0x0000 0x0000 10: 0x8801 0x4210 0x0002 0x0000 0x0000 11: 0x9801 0x4210 0x0002 0x0000 0x0000 12: 0xA801 0x4210 0x0002 0x0000 0x0000 13: 0xB801 0x4210 0x0002 0x0000 0x0000 14: 0xC801 0x4210 0x0002 0x0000 0x0000 15: 0xD801 0x4210 0x0002 0x0000 0x0000 16: 0xE801 0x4210 0x0002 0x0000 0x0000 17: 0xF001 0x4210 0x0002 0x0000 0x0000 18: 0x0801 0x4210 0x0002 0x0000 0x0000 19: 0x0801 0x4210 0x0002 0x0000 0x0000 20: 0x0801 0xC210 0x0002 0x0000 0x0000 21: 0x0901 0x4210 0x0002 0x0000 0x0000 22: 0x0901 0xC210 0x0002 0x0000 0x0000 23: 0x0A01 0x4210 0x0002 0x0000 0x0000 24: 0x0A01 0xC210 0x0002 0x0000 0x0000 25: 0x0B01 0x4210 0x0002 0x0000 0x0000 26: 0x0B01 0xC210 0x0002 0x0000 0x0000 27: 0x0C01 0x4210 0x0002 0x0000 0x0000 28: 0x0C01 0xC210 0x0002 0x0000 0x0000 29: 0x0D01 0x4210 0x0002 0x0000 0x0000 30: 0x0D01 0xC210 0x0002 0x0000 0x0000 31: 0x0E01 0x4210 0x0002 0x0000 0x0000 32: 0x0E01 0xC210 0x0002 0x0000 0x0000 33: 0x0F01 0x4210 0x0002 0x0000 0x0000 34: 0x0F01 0x8210 0x0002 0x0000 0x0000 35: 0x0801 0x4210 0x0002 0x0000 0x0000 36: 0x0801 0x4210 0x0002 0x0000 0x0000 37: 0x0801 0x4610 0x0002 0x0000 0x0000 38: 0x0801 0x4A10 0x0002 0x0000 0x0000 39: 0x0801 0x4E10 0x0002 0x0000 0x0000 40: 0x0801 0x5210 0x0002 0x0000 0x0000 41: 0x0801 0x5610 0x0002 0x0000 0x0000 42: 0x0801 0x5A10 0x0002 0x0000 0x0000 43: 0x0801 0x5E10 0x0002 0x0000 0x0000 44: 0x0801 0x6210 0x0002 0x0000 0x0000 45: 0x0801 0x6610 0x0002 0x0000 0x0000 46: 0x0801 0x6A10 0x0002 0x0000 0x0000 47: 0x0801 0x6E10 0x0002 0x0000 0x0000 48: 0x0801 0x7210 0x0002 0x0000 0x0000 49: 0x0801 0x7610 0x0002 0x0000 0x0000 50: 0x0801 0x7A10 0x0002 0x0000 0x0000 51: 0x0801 0x7C10 0x0002 0x0000 0x0000 52: 0x0801 0x4210 0x0002 0x0000 0x0000 53: 0x0801 0x4210 0x0002 0x0000 0x0000 54: 0x0803 0x4210 0x0002 0x0000 0x0000 55: 0x0805 0x4210 0x0002 0x0000 0x0000 56: 0x0807 0x4210 0x0002 0x0000 0x0000 57: 0x0809 0x4210 0x0002 0x0000 0x0000 58: 0x080B 0x4210 0x0002 0x0000 0x0000 59: 0x080D 0x4210 0x0002 0x0000 0x0000 60: 0x080F 0x4210 0x0002 0x0000 0x0000 61: 0x0811 0x4210 0x0002 0x0000 0x0000 62: 0x0813 0x4210 0x0002 0x0000 0x0000 63: 0x0815 0x4210 0x0002 0x0000 0x0000 64: 0x0817 0x4210 0x0002 0x0000 0x0000 65: 0x0819 0x4210 0x0002 0x0000 0x0000 66: 0x081B 0x4210 0x0002 0x0000 0x0000 67: 0x081D 0x4210 0x0002 0x0000 0x0000 68: 0x081E 0x4210 0x0002 0x0000 0x0000 69: 0x0801 0x4210 0x0002 0x0000 0x0000 70: 0x0801 0x4210 0x0002 0x0000 0x0000 71: 0x0801 0x4218 0x0002 0x0000 0x0000 72: 0x0801 0x4214 0x0002 0x0000 0x0000 73: 0x0801 0x421C 0x0002 0x0000 0x0000 74: 0x0801 0x4212 0x0002 0x0000 0x0000 75: 0x0801 0x421A 0x0002 0x0000 0x0000 76: 0x0801 0x4216 0x0002 0x0000 0x0000 77: 0x0801 0x421E 0x0002 0x0000 0x0000 78: 0x0801 0x4211 0x0002 0x0000 0x0000 79: 0x0801 0x4219 0x0002 0x0000 0x0000 80: 0x0801 0x4215 0x0002 0x0000 0x0000 81: 0x0801 0x421D 0x0002 0x0000 0x0000 82: 0x0801 0x4213 0x0002 0x0000 0x0000 83: 0x0801 0x421B 0x0002 0x0000 0x0000 84: 0x0801 0x4217 0x0002 0x0000 0x0000 85: 0x0801 0x420F 0x0002 0x0000 0x0000 86: 0x0801 0x4210 0x0002 0x0000 0x0000 87: 0x0801 0x4210 0x0002 0x0000 0x0000 88: 0x0801 0x4210 0x0003 0x0000 0x0000 89: 0x0801 0x4290 0x0002 0x0000 0x0000 90: 0x0801 0x4290 0x0003 0x0000 0x0000 91: 0x0801 0x4250 0x0002 0x0000 0x0000 92: 0x0801 0x4250 0x0003 0x0000 0x0000 93: 0x0801 0x42D0 0x0002 0x0000 0x0000 94: 0x0801 0x42D0 0x0003 0x0000 0x0000 95: 0x0801 0x4230 0x0002 0x0000 0x0000 96: 0x0801 0x4230 0x0003 0x0000 0x0000 97: 0x0801 0x42B0 0x0002 0x0000 0x0000 98: 0x0801 0x42B0 0x0003 0x0000 0x0000 99: 0x0801 0x4270 0x0002 0x0000 0x0000 100: 0x0801 0x4270 0x0003 0x0000 0x0000 101: 0x0801 0x42F0 0x0002 0x0000 0x0000 102: 0x0801 0x42F0 0x0001 0x0000 0x0000 103: 0x0801 0x4210 0x0002 0x0000 0x0000 104: 0x0801 0x4210 0x0002 0x0000 0x0000 105: 0xF71E 0xBCEF 0x0001 0x0000 0x0000 106: 0x0F1E 0xBCEF 0x0001 0x0000 0x0000 107: 0x1F1E 0xBCEF 0x0001 0x0000 0x0000 108: 0x2F1E 0xBCEF 0x0001 0x0000 0x0000 109: 0x3F1E 0xBCEF 0x0001 0x0000 0x0000 110: 0x4F1E 0xBCEF 0x0001 0x0000 0x0000 111: 0x5F1E 0xBCEF 0x0001 0x0000 0x0000 112: 0x6F1E 0xBCEF 0x0001 0x0000 0x0000 113: 0x7F1E 0xBCEF 0x0001 0x0000 0x0000 114: 0x8F1E 0xBCEF 0x0001 0x0000 0x0000 115: 0x9F1E 0xBCEF 0x0001 0x0000 0x0000 116: 0xAF1E 0xBCEF 0x0001 0x0000 0x0000 117: 0xBF1E 0xBCEF 0x0001 0x0000 0x0000 118: 0xCF1E 0xBCEF 0x0001 0x0000 0x0000 119: 0xDF1E 0xBCEF 0x0001 0x0000 0x0000 120: 0xEF1E 0xBCEF 0x0001 0x0000 0x0000 121: 0xF71E 0xBCEF 0x0001 0x0000 0x0000 122: 0xF01E 0x7CEF 0x0001 0x0000 0x0000 123: 0xF01E 0xFCEF 0x0001 0x0000 0x0000 124: 0xF11E 0x7CEF 0x0001 0x0000 0x0000 125: 0xF11E 0xFCEF 0x0001 0x0000 0x0000 126: 0xF21E 0x7CEF 0x0001 0x0000 0x0000 127: 0xF21E 0xFCEF 0x0001 0x0000 0x0000 128: 0xF31E 0x7CEF 0x0001 0x0000 0x0000 129: 0xF31E 0xFCEF 0x0001 0x0000 0x0000 130: 0xF41E 0x7CEF 0x0001 0x0000 0x0000 131: 0xF41E 0xFCEF 0x0001 0x0000 0x0000 132: 0xF51E 0x7CEF 0x0001 0x0000 0x0000 133: 0xF51E 0xFCEF 0x0001 0x0000 0x0000 134: 0xF61E 0x7CEF 0x0001 0x0000 0x0000 135: 0xF61E 0xFCEF 0x0001 0x0000 0x0000 136: 0xF71E 0x7CEF 0x0001 0x0000 0x0000 137: 0xF71E 0xBCEF 0x0001 0x0000 0x0000 138: 0xF71E 0x82EF 0x0001 0x0000 0x0000 139: 0xF71E 0x86EF 0x0001 0x0000 0x0000 140: 0xF71E 0x8AEF 0x0001 0x0000 0x0000 141: 0xF71E 0x8EEF 0x0001 0x0000 0x0000 142: 0xF71E 0x92EF 0x0001 0x0000 0x0000 143: 0xF71E 0x96EF 0x0001 0x0000 0x0000 144: 0xF71E 0x9AEF 0x0001 0x0000 0x0000 145: 0xF71E 0x9EEF 0x0001 0x0000 0x0000 146: 0xF71E 0xA2EF 0x0001 0x0000 0x0000 147: 0xF71E 0xA6EF 0x0001 0x0000 0x0000 148: 0xF71E 0xAAEF 0x0001 0x0000 0x0000 149: 0xF71E 0xAEEF 0x0001 0x0000 0x0000 150: 0xF71E 0xB2EF 0x0001 0x0000 0x0000 151: 0xF71E 0xB6EF 0x0001 0x0000 0x0000 152: 0xF71E 0xBAEF 0x0001 0x0000 0x0000 153: 0xF71E 0xBCEF 0x0001 0x0000 0x0000 154: 0xF701 0xBCEF 0x0001 0x0000 0x0000 155: 0xF703 0xBCEF 0x0001 0x0000 0x0000 156: 0xF705 0xBCEF 0x0001 0x0000 0x0000 157: 0xF707 0xBCEF 0x0001 0x0000 0x0000 158: 0xF709 0xBCEF 0x0001 0x0000 0x0000 159: 0xF70B 0xBCEF 0x0001 0x0000 0x0000 160: 0xF70D 0xBCEF 0x0001 0x0000 0x0000 161: 0xF70F 0xBCEF 0x0001 0x0000 0x0000 162: 0xF711 0xBCEF 0x0001 0x0000 0x0000 163: 0xF713 0xBCEF 0x0001 0x0000 0x0000 164: 0xF715 0xBCEF 0x0001 0x0000 0x0000 165: 0xF717 0xBCEF 0x0001 0x0000 0x0000 166: 0xF719 0xBCEF 0x0001 0x0000 0x0000 167: 0xF71B 0xBCEF 0x0001 0x0000 0x0000 168: 0xF71D 0xBCEF 0x0001 0x0000 0x0000 169: 0xF71E 0xBCEF 0x0001 0x0000 0x0000 170: 0xF71E 0xBCF0 0x0001 0x0000 0x0000 171: 0xF71E 0xBCF8 0x0001 0x0000 0x0000 172: 0xF71E 0xBCF4 0x0001 0x0000 0x0000 173: 0xF71E 0xBCFC 0x0001 0x0000 0x0000 174: 0xF71E 0xBCF2 0x0001 0x0000 0x0000 175: 0xF71E 0xBCFA 0x0001 0x0000 0x0000 176: 0xF71E 0xBCF6 0x0001 0x0000 0x0000 177: 0xF71E 0xBCFE 0x0001 0x0000 0x0000 178: 0xF71E 0xBCF1 0x0001 0x0000 0x0000 179: 0xF71E 0xBCF9 0x0001 0x0000 0x0000 180: 0xF71E 0xBCF5 0x0001 0x0000 0x0000 181: 0xF71E 0xBCFD 0x0001 0x0000 0x0000 182: 0xF71E 0xBCF3 0x0001 0x0000 0x0000 183: 0xF71E 0xBCFB 0x0001 0x0000 0x0000 184: 0xF71E 0xBCF7 0x0001 0x0000 0x0000 185: 0xF71E 0xBCEF 0x0001 0x0000 0x0000 186: 0xF71E 0xBC0F 0x0002 0x0000 0x0000 187: 0xF71E 0xBC0F 0x0003 0x0000 0x0000 188: 0xF71E 0xBC8F 0x0002 0x0000 0x0000 189: 0xF71E 0xBC8F 0x0003 0x0000 0x0000 190: 0xF71E 0xBC4F 0x0002 0x0000 0x0000 191: 0xF71E 0xBC4F 0x0003 0x0000 0x0000 192: 0xF71E 0xBCCF 0x0002 0x0000 0x0000 193: 0xF71E 0xBCCF 0x0003 0x0000 0x0000 194: 0xF71E 0xBC2F 0x0002 0x0000 0x0000 195: 0xF71E 0xBC2F 0x0003 0x0000 0x0000 196: 0xF71E 0xBCAF 0x0002 0x0000 0x0000 197: 0xF71E 0xBCAF 0x0003 0x0000 0x0000 198: 0xF71E 0xBC6F 0x0002 0x0000 0x0000 199: 0xF71E 0xBC6F 0x0003 0x0000 0x0000 200: 0xF71E 0xBCEF 0x0002 0x0000 0x0000 201: 0xF71E 0xBCEF 0x0001 0x0000 0x0000 202: 0xF71E 0xBCEF 0x0001 0x0000 0x0000 PINs used (in edge connector order) (G=ground,P=power) SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBB LETTER ABCDEFHJKLMNPRSTUVABCDEFHJKLMNPRSTUVABCDEFHJKLMNPRSTUVABCDEFHJKLMNPRSTUV SIDE 111111111111111111222222222222222222111111111111111111222222222222222222 USAGE IIIIOIIIIOIIIIOG P GIIIIOIIIIOIIIIO G P G UUT inputs: 24 UUT outputs: 6 pins used: 30 not used: 36 202 'test steps' 238 lines M617 REV E 6 4-INPUT NAND BUFFERS (48ma) (7440) PINS Main menu Thu Jul 06 09:24:00 2017 test file is: tests\m617.tst delay is: 0 trigger is: 1 1 read test file 2 set test delay 3 set test trigger 4 run test 5 output loading test 8 diags 9 exit UUT power is okay Thu Jul 06 09:24:01 2017 space single step O run once (one test, all steps) F run, stop on fail G go (run tests N run, stop on fail, no print S scope (run, no print) C turn on comment printout + increase speed (less delay) - decrease speed (more delay)(slower) Q quit test scope (run, no print) ppppppppppppppppppp space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn on comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFHJKLMNPRSDEFHJKLMNPRSTUV SIDE 111111111111111222222222222222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO all fails was lo 000000000000000000000000000000 falling vvvvvvvvvvvvvvvvvvvvvvvvvvvvvv rising ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ was hi 111111111111111111111111111111 total fails 0, total passes 19 Main menu Thu Jul 06 09:27:10 2017 test file is: tests\m617.tst delay is: 0 trigger is: 1 1 read test file 2 set test delay 3 set test trigger 4 run test 5 output loading test 8 diags 9 exit exiting tester- PDP8 card tester via printer port version 0.91 November 27, 2015 mapping[] is verified Main menu Sun Jul 09 15:28:49 2017 test file is: delay is: 0 trigger is: 1 1 read test file 2 set test delay 3 set test trigger 4 run test 5 output loading test 8 diags 9 exit Enter test file name? trying to open test file: tests\m706k could not open test file. valid test files are: reverting back to test file: Main menu Sun Jul 09 15:29:07 2017 test file is: delay is: 0 trigger is: 1 1 read test file 2 set test delay 3 set test trigger 4 run test 5 output loading test 8 diags 9 exit there is no test file Main menu Sun Jul 09 15:29:09 2017 test file is: delay is: 0 trigger is: 1 1 read test file 2 set test delay 3 set test trigger 4 run test 5 output loading test 8 diags 9 exit key is 0x0073 Main menu Sun Jul 09 15:29:10 2017 test file is: delay is: 0 trigger is: 1 1 read test file 2 set test delay 3 set test trigger 4 run test 5 output loading test 8 diags 9 exit there is no test file Main menu Sun Jul 09 15:29:13 2017 test file is: delay is: 0 trigger is: 1 1 read test file 2 set test delay 3 set test trigger 4 run test 5 output loading test 8 diags 9 exit Enter test file name? trying to open test file: tests\m706k.tst reading test file: tests\m706k.tst comment: M706 PCB REV K SCHEMATIC REV L TELETYPE RECEIVER comment: comment: NOTE: 17 PINS not used comment: 1 AA1 PAD, NOT CONNECTED comment: 2 AB1 NOT CONNECTED comment: 3 AC1 NOT CONNECTED comment: 4 AU1 NOT CONNECTED comment: 5 AB2 NOT CONNECTED comment: 6 BA1 NOT CONNECTED comment: 7 BB1 NOT CONNECTED comment: 8 BC1 NOT CONNECTED comment: 9 BE1 NOT CONNECTED comment: 10 BF1 NOT CONNECTED comment: 11 BH1 NOT CONNECTED comment: 12 BJ1 NOT CONNECTED comment: 13 BK1 NOT CONNECTED comment: 14 BL1 PAD, NOT CONNECTED comment: 15 BV1 PAD, NOT CONNECTED comment: 16 BB2 NOT CONNECTED comment: 17 BK2 NOT CONNECTED CPU schematics shows output TT SHIFT-N comment: pins: PINS pins: 1 O AD1 +3V pins: 2 I AL2 READ BUFFER (NORMALLY IOP4) pins: 3 I AD2 (DEVICE SELECTOR BMB INPUTS) (NAND)-> (DEVICE SELECT-N) pins: 4 I AE1 (DEVICE SELECTOR BMB INPUTS) (NAND)-> (DEVICE SELECT-N) pins: 5 I AF1 (DEVICE SELECTOR BMB INPUTS) (NAND)-> (DEVICE SELECT-N) pins: 6 I AH1 (DEVICE SELECTOR BMB INPUTS) (NAND)-> (DEVICE SELECT-N) pins: 7 I AH2 (DEVICE SELECTOR BMB INPUTS) (NAND)-> (DEVICE SELECT-N) pins: 8 I AJ1 (DEVICE SELECTOR BMB INPUTS) (NAND)-> (DEVICE SELECT-N) pins: 9 I AP1 (FORCE SELECT-N) (NORMALLY HI) NAND(DEVICE SELECT-N)=(SELECTED) pins: 10 I BF2 I/O CLEAR (NORMALLY INITIALIZE) pins: 11 I BJ2 CLEAR FLAG 1 (NORMALLY IOP2) pins: 12 O BE2 (SELECTED IOP2-N) = CLEAR FLAG 1 NAND (SELECTED) pins: 13 I BD1 CLEAR FLAG 2 (NORMALLY CONNECTED TO GROUND) pins: 14 O AE2 (KCC-N) = (SELECTED IOP2) NOR I/O CLEAR NOR CLEAR FLAG 2 pins: 15 O AV1 BUFFER STROBE = READ BUFFER AND (SELECTED) pins: 16 I BM1 (EXTRA IN) (NOT USED? ON CPU SCHEMATIC) pins: 17 O BN1 (EXTRA-N) = (EXTRA IN) NAND BUFFER STROBE pins: 18 I BD2 SKP. STROBE (NORMALLY IOP1) pins: 19 O AF2 FLAG-N (AKA P.I. REQUEST) pins: 20 O BH2 I/O SKIP = FLAG NAND SKP. STROBE NAND (SELECTED) (ACTIVE LO) pins: 21 I AV2 (READER RUN SET-N) (NORMALLY CONNECTED TO (KCC-N)) pins: 22 O BL2 READER RUN pins: 23 O AU2 READER ENABLE CANNOT TEST (PNP HI DRIVER; 26MA @1V; OPEN (-15?) pins: 24 O BN2 (ACTIVE-N) (AKA IN ACTIVE ON CPU SCHEMATIC) pins: 25 O BS2 (PRESET-N) = (200NS?) PULSE ON ACTIVE-N FALLING EDGE pins: 26 I AN1 CLOCK 8 BAUD pins: 27 O BS1 CLOCK SCALE 2-N (CLOCK 8 BAUD / 4) NORMALLY DRIVES (STOP CLOCK) pins: 28 O BT2 CLOCK SCALE 2 (CLOCK 8 BAUD DIVIDED BY 4) pins: 29 I BP2 (STOP CLOCK) (<-CLOCK SCALE 2-N FOR 0.5 STOP; -P FOR X.0) pins: 30 I BP1 (STOP SET-N) (NORMALLY +3?) pins: 31 O BU2 STOP 1-N pins: 32 O BV2 STOP 2-N (NORMALLY DRIVES IN LAST UNIT) pins: 33 I BR2 IN LAST UNIT CLEAR-N (<-STOP 1-N FOR 1.X STOP; STOP 2-N FOR 2) pins: 34 I BM2 TELETYPE SERIAL INPUT pins: 35 O AM2 (TELETYPE SERIAL INPUT-N) pins: 36 I BR1 ENABLE (NORMALLY +3V (33)) pins: 37 I AR1 (TT0 DATA) (NORMALLY CONNECTED TO (TELETYPE SERIAL INPUT-N) pins: 38 O AK1 (TT2) (NORMALLY CONNECTED TO AJ2 (TT3 DATA) FOR 8 BIT DATA) pins: 39 I AJ2 (TT3 DATA) =(DATA IN) FOR 5 BIT; = (TT2) FOR 8 BIT pins: 40 I BU1 SHIFT CLOCK (NORMALLY CLOCK SCALE 2) pins: 41 O AS1 TT SHIFT (100NS? PULSE) AKA SHIFT ON CPU SCHEMATIC pins: 42 O AK2 TT0-N (MSB) = TT0 NAND BUFFER STROBE pins: 43 O AR2 TT1-N = TT0 NAND BUFFER STROBE pins: 44 O AS2 TT2-N = TT0 NAND BUFFER STROBE pins: 45 O AL1 TT3-N = TT0 NAND BUFFER STROBE pins: 46 O AM1 TT4-N = TT0 NAND BUFFER STROBE pins: 47 O AP2 TT5-N = TT0 NAND BUFFER STROBE pins: 48 O AT2 TT6-N = TT0 NAND BUFFER STROBE pins: 49 O AN2 TT7-N (LSB) = TT0 NAND BUFFER STROBE pins: direction: OIIIIIIIIIIOIOOIOIOOIOOOOIOOIIOOIIOIIOIIOOOOOOOOO comment: ; note COLUMN 21 PIN AU2 is PNP hi side driver; can not test comment: ; I/O CLEAR hi comment: ; (READER RUN SET-N) low to set READER RUN (not normal powerup) comment: ; (STOP SET-N) low to set STOP 1 and STOP 2 (not normal powerup) comment: ; IN LAST UNIT CLEAR-N low to clear CLOCK SCALE 1 and CLOCK SCALE 2 test 1: 1000000011010000101101X11010000000101X00011111111 comment: ; toggle TELETYPE SERIAL INPUT with I/O CLEAR active -> no change test 2: 10 comment: ; have (TT0 DATA) track (TELETYPE SERIAL INPUT-N) test 3: 0 test 4: 01 comment: ; have (TT0 DATA) track (TELETYPE SERIAL INPUT-N) test 5: 1 comment: ; comment: ; undo the initial setup that is not normal powerup comment: ; comment: ; release I/O CLEAR; (KCC-N) goes hi test 6: 0 1 comment: ; release (STOP SET-N) test 7: 1 comment: ; release (READER RUN SET-N) test 8: 1 comment: ; release IN LAST UNIT CLEAR-N test 9: 1 comment: ; check that STOP 1, STOP 2 do not count when not ACTIVE comment: ; clock (STOP CLOCK). since ACTIVE-N is 1; no count STOP 1; STOP 2 test 10: 1 test 11: 0 comment: ; clock CLOCK 8 BAUD to set (CLOCK SCALE 0) test 12: 1 test 13: 0 comment: ; set/clear CLEAR FLAG 2; (KCC-N) goes lo/hi test 14: 10 test 15: 01 comment: ; comment: ; check 'not selected' does not change comment: ; set/clear READ BUFFER -> no change (not selected) test 16: 1 test 17: 0 comment: ; set/clear (EXTRA IN) -> no change (not selected) test 18: 1 test 19: 0 comment: ; set/clear CLEAR FLAG 1 -> no change (not selected) test 20: 1 test 21: 0 comment: ; set/clear SKP. STROBE -> no change (not selected) test 22: 1 test 23: 0 comment: ; comment: ; forced select tests comment: ; comment: ; (FORCE SELECT-N) test 24: 0 comment: ; set CLEAR FLAG 1 -> (SELECTED IOP2-N) lo; (KCC-N) lo test 25: 10 0 comment: ; clear/set (FORCE SELECT-N) -> (SELECTED IOP2-N) hi/lo; (KCC-N) hi/lo test 26: 1 1 1 test 27: 0 0 0 comment: ; set READ BUFFER -> BUFFFER STROBE goes hi; TTn-N go to ?? test 28: 1 1 XXXXXXXX comment: ; set (EXTRA IN) -. (EXTRA-N) goes lo test 29: 10 comment: ; clear READ BUFFER -> BUFFER STROBE goes lo; (EXTRA-N) goes hi test 30: 0 0 1 11111111 comment: ; set READ BUFFER -> BUFFER STROBE goes hi; (EXTRA-N) goes ho test 31: 1 1 0 XXXXXXXX comment: ; set SKP. STROBE -> no change (flag is off) test 32: 1 comment: ; remove force select -> (SELECTED IOP2-N),(KCC-N),(EXTRA-N) hi; BUFFER STROBE lo test 33: 1 1 10 1 11111111 comment: ; comment: ; check device select comment: ; comment: ; device select -> (SELECTED IOP2-N),(KCC-N),(EXTRA-N) lo; BUFFER STROBE hi test 34: 100000 test 35: 110000 test 36: 111000 test 37: 111100 test 38: 111110 test 39: 111111 0 01 0 XXXXXXXX test 40: 011111 1 10 1 11111111 test 41: 001111 test 42: 000111 test 43: 000011 test 44: 000001 test 45: 000000 test 46: 111111 0 01 0 XXXXXXXX test 47: 011111 1 10 1 11111111 test 48: 111111 0 01 0 XXXXXXXX test 49: 101111 1 10 1 11111111 test 50: 111111 0 01 0 XXXXXXXX test 51: 110111 1 10 1 11111111 test 52: 111111 0 01 0 XXXXXXXX test 53: 111011 1 10 1 11111111 test 54: 111111 0 01 0 XXXXXXXX test 55: 111101 1 10 1 11111111 test 56: 111111 0 01 0 XXXXXXXX test 57: 111110 1 10 1 11111111 test 58: 111111 0 01 0 XXXXXXXX test 59: 000000 1 10 1 11111111 test 60: 000001 test 61: 000010 test 62: 000011 test 63: 000100 test 64: 000101 test 65: 000110 test 66: 000111 test 67: 001000 test 68: 001001 test 69: 001010 test 70: 001011 test 71: 001100 test 72: 001101 test 73: 001110 test 74: 001111 test 75: 010000 test 76: 010001 test 77: 010010 test 78: 010011 test 79: 010100 test 80: 010101 test 81: 010110 test 82: 010111 test 83: 011000 test 84: 011001 test 85: 011010 test 86: 011011 test 87: 011100 test 88: 011101 test 89: 011110 test 90: 011111 test 91: 100000 test 92: 100001 test 93: 100010 test 94: 100011 test 95: 100100 test 96: 100101 test 97: 100110 test 98: 100111 test 99: 101000 test 100: 101001 test 101: 101010 test 102: 101011 test 103: 101100 test 104: 101101 test 105: 101110 test 106: 101111 test 107: 110000 test 108: 110001 test 109: 110010 test 110: 110011 test 111: 110100 test 112: 110101 test 113: 110110 test 114: 110111 test 115: 111000 test 116: 111001 test 117: 111010 test 118: 111011 test 119: 111100 test 120: 111101 test 121: 111110 test 122: 111111 0 01 0 XXXXXXXX comment: ; remove CLEAR FLAG 1 while selected -> (SELECTED IOP2-N) hi; (KCC-N) hi test 123: 01 1 comment: ; remove (EXTRA IN) -> (EXTRA-N) goes hi test 124: 01 comment: ; remove READ BUFFER -> BUFFER STROBE lo; TTn-N go hi test 125: 0 0 11111111 comment: ; deselect test 126: 000000 0 comment: ; comment: ; test the start bit detect gate comment: ; comment: ; verify each signal does not falsely start bit detect with START ENABLE hi comment: ; comment: ; make sure they are off test 127: 0 010 comment: ; set/clear TELETYPE SERIAL INPUT -> no change comment: ; set/clear ENABLE -> no change test 128: 1 test 129: 0 test 130: 10 test 131: 01 comment: ; set/clear CLOCK 8 BAUD -> no change test 132: 1 test 133: 0 comment: ; comment: ; verify each signal inhibits start bit detect with START ENABLE hi comment: ; comment: ; set ENABLE -> no change test 134: 1 comment: ; set/clear TELETYPE SERIAL INPUT -> no change test 135: 10 test 136: 01 comment: ; set/clear CLOCK 8 BAUD -> no change test 137: 1 test 138: 0 comment: ; clear ENABLE test 139: 0 comment: ; set CLOCK 8 BAUD -> no change test 140: 1 comment: ; set/clear TELETYPE SERIAL INPUT -> no change test 141: 10 test 142: 01 comment: ; clear CLOCK 8 BAUD -> no change test 143: 0 comment: ; comment: ; do START BIT detect comment: ; comment: ; set CLOCK 8 BAUD test 144: 1 comment: ; set ENABLE test 145: 1 comment: ; prestage (TT0 DATA) due to clock edge test 146: 0 comment: ; set TELETYPE SERIAL INPUT -> comment: ; READER RUN,ACTIVE-N,STOP 1-N,STOP 2-N go lo test 147: 0 0 11 10 comment: ; select and READ BUFFER -> BUFFER STROBE hi, TTn-N go lo test 148: 1111111 1 1 00000000 comment: ; set (TT5 DATA) to match TT6 test 149: 1 comment: ; CLOCK 8 BAUD to toggle CLOCK SCALE 2-N and CLOCK SCALE 2 test 150: 0 test 151: 1 test 152: 0 test 153: 1 test 154: 0 test 155: 101 test 156: 0 test 157: 1 test 158: 0 test 159: 1 test 160: 0 test 161: 1 test 162: 0 test 163: 110 comment: ; leave CLOCK SCALE 2 set test 164: 0 test 165: 1 test 166: 0 test 167: 1 test 168: 0 test 169: 1 test 170: 0 test 171: 101 comment: ; (STOP CLOCK) does not change STOP 1, STOP 2 since ACTIVE test 172: 1 test 173: 0 test 174: 1 test 175: 0 comment: ; clear TELETYPE SERIAL INPUT (do a short START BT) test 176: 01 comment: ; have (TT0 DATA) track (TELETYPE SERIAL INPUT-N) test 177: 1 comment: ; SHIFT CLOCK to shift 1 (short START BIT sets SPIKE DETECTOR) comment: ; note: ACTIVE-N goes hi AFTER rising edge due to SPIKE DETECTOR comment: ; and CLOCK SCLE 2 gets cleared test 178: 1 10 1 1 00000000 test 179: 0 comment: ; comment: ; receive a '00000000' character comment: ; comment: ; prestage (TT0 DATA) due to clock edge test 180: 0 comment: ; set TELETYPE SERIAL INPUT (START BIT) -> comment: ; READER RUN,ACTIVE-N,TT0-N go lo; STOP 1-N,STOP 2-N go hi comment: ; note: (TT2) is value AFTER rising clock test 181: 0 0 11 10 0 comment: ; CLOCK 8 BAUD to setup CLOCK SCALE 2-N lo; CLOCK SCALE 2 hi test 182: 0 test 183: 1 test 184: 0 test 185: 1 test 186: 0 test 187: 1 test 188: 0 test 189: 101 comment: ; toggle SHIFT CLOCK -> shift in a '00000000' character test 190: 1 10000000 test 191: 0 comment: test 192: 1 11000000 test 193: 0 test 194: 0 1 11100000 comment: ; clear (TT3 DATA) to match TT2 test 195: 0 test 196: 0 test 197: 1 11110000 test 198: 0 test 199: 1 11111000 test 200: 0 test 201: 1 11111100 test 202: 0 test 203: 1 11111110 test 204: 0 test 205: 1 11111111 test 206: 0 comment: ; shift start bit into FLAG -> I/O SKIP lo, FLAG-N (aka P.I. REQUEST) lo test 207: 00 1 comment: ; turn off READ BUFFER -> BUFFER STROBE lo, (TTn-N still hi) test 208: 0 0 test 209: 1 1 comment: ; disable SKP. STROBE -> I/O SKIP goes hi test 210: 0 1 comment: ; on SHIFT CLOCK falling edge, ACTIVE-N hi test 211: 1 0 comment: ; clear TELETYPE SERIAL INPUT (stop bit); set TT0 DATA test 212: 01 comment: ; have (TT0 DATA) track (TELETYPE SERIAL INPUT-N) test 213: 1 test 214: 1 test 215: 0 test 216: 1 test 217: 0 comment: ; IN LAST UNIT CLEAR-N -> CLOCK SCALE 2 lo; CLOCK SCALE 2-N hi test 218: 10 0 comment: ; comment: ; receive a '11111111' character comment: ; comment: ;;;;;;;;;;;;;;;;;;;;;; comment: ; end: END summary column 1: offset 0, mask 0x1000 column 2: offset 1, mask 0x0002 column 3: offset 0, mask 0x0010 column 4: offset 0, mask 0x0800 column 5: offset 0, mask 0x0400 column 6: offset 0, mask 0x0200 column 7: offset 0, mask 0x0002 column 8: offset 0, mask 0x0100 column 9: offset 1, mask 0x0800 column 10: offset 2, mask 0x0080 column 11: offset 3, mask 0x0002 column 12: offset 2, mask 0x0040 column 13: offset 2, mask 0x0400 column 14: offset 0, mask 0x0008 column 15: offset 2, mask 0x4000 column 16: offset 3, mask 0x0800 column 17: offset 3, mask 0x0400 column 18: offset 2, mask 0x0020 column 19: offset 0, mask 0x0004 column 20: offset 3, mask 0x0001 column 21: offset 2, mask 0x0002 column 22: offset 3, mask 0x0008 column 23: offset 2, mask 0x0001 column 24: offset 3, mask 0x0020 column 25: offset 4, mask 0x0001 column 26: offset 1, mask 0x1000 column 27: offset 4, mask 0x8000 column 28: offset 4, mask 0x0002 column 29: offset 3, mask 0x0040 column 30: offset 3, mask 0x0200 column 31: offset 4, mask 0x0004 column 32: offset 4, mask 0x0008 column 33: offset 3, mask 0x0080 column 34: offset 3, mask 0x0010 column 35: offset 1, mask 0x0004 column 36: offset 3, mask 0x0100 column 37: offset 1, mask 0x0400 column 38: offset 1, mask 0x8000 column 39: offset 0, mask 0x0001 column 40: offset 4, mask 0x2000 column 41: offset 1, mask 0x0200 column 42: offset 1, mask 0x0001 column 43: offset 1, mask 0x0020 column 44: offset 1, mask 0x0040 column 45: offset 1, mask 0x4000 column 46: offset 1, mask 0x2000 column 47: offset 1, mask 0x0010 column 48: offset 1, mask 0x0080 column 49: offset 1, mask 0x0008 direction bits (1=input) 0xF0EC 0xE3FD 0xFB59 0xF42D 0xD0FF pullup bits (1=pullup) 0x0000 0x0000 0x0000 0x0000 0x0000 test step out_data dont care 1: 0x1004 0x6CFD 0x00C0 0x0429 0x8001 0x0000 0x8000 0x0001 0x0000 0x0000 2: 0x1004 0x6CF9 0x00C0 0x0439 0x8001 0x0000 0x8000 0x0001 0x0000 0x0000 3: 0x1004 0x68F9 0x00C0 0x0439 0x8001 0x0000 0x8000 0x0001 0x0000 0x0000 4: 0x1004 0x68FD 0x00C0 0x0429 0x8001 0x0000 0x8000 0x0001 0x0000 0x0000 5: 0x1004 0x6CFD 0x00C0 0x0429 0x8001 0x0000 0x8000 0x0001 0x0000 0x0000 6: 0x100C 0x6CFD 0x0040 0x0429 0x8001 0x0000 0x8000 0x0001 0x0000 0x0000 7: 0x100C 0x6CFD 0x0040 0x0629 0x8001 0x0000 0x8000 0x0001 0x0000 0x0000 8: 0x100C 0x6CFD 0x0042 0x0629 0x8001 0x0000 0x8000 0x0001 0x0000 0x0000 9: 0x100C 0x6CFD 0x0042 0x06A9 0x8001 0x0000 0x8000 0x0001 0x0000 0x0000 10: 0x100C 0x6CFD 0x0042 0x06E9 0x8001 0x0000 0x8000 0x0001 0x0000 0x0000 11: 0x100C 0x6CFD 0x0042 0x06A9 0x8001 0x0000 0x8000 0x0001 0x0000 0x0000 12: 0x100C 0x7CFD 0x0042 0x06A9 0x8001 0x0000 0x8000 0x0001 0x0000 0x0000 13: 0x100C 0x6CFD 0x0042 0x06A9 0x8001 0x0000 0x8000 0x0001 0x0000 0x0000 14: 0x1004 0x6CFD 0x0442 0x06A9 0x8001 0x0000 0x8000 0x0001 0x0000 0x0000 15: 0x100C 0x6CFD 0x0042 0x06A9 0x8001 0x0000 0x8000 0x0001 0x0000 0x0000 16: 0x100C 0x6CFF 0x0042 0x06A9 0x8001 0x0000 0x8000 0x0001 0x0000 0x0000 17: 0x100C 0x6CFD 0x0042 0x06A9 0x8001 0x0000 0x8000 0x0001 0x0000 0x0000 18: 0x100C 0x6CFD 0x0042 0x0EA9 0x8001 0x0000 0x8000 0x0001 0x0000 0x0000 19: 0x100C 0x6CFD 0x0042 0x06A9 0x8001 0x0000 0x8000 0x0001 0x0000 0x0000 20: 0x100C 0x6CFD 0x0042 0x06AB 0x8001 0x0000 0x8000 0x0001 0x0000 0x0000 21: 0x100C 0x6CFD 0x0042 0x06A9 0x8001 0x0000 0x8000 0x0001 0x0000 0x0000 22: 0x100C 0x6CFD 0x0062 0x06A9 0x8001 0x0000 0x8000 0x0001 0x0000 0x0000 23: 0x100C 0x6CFD 0x0042 0x06A9 0x8001 0x0000 0x8000 0x0001 0x0000 0x0000 24: 0x100C 0x64FD 0x0042 0x06A9 0x8001 0x0000 0x8000 0x0001 0x0000 0x0000 25: 0x1004 0x64FD 0x0002 0x06AB 0x8001 0x0000 0x8000 0x0001 0x0000 0x0000 26: 0x100C 0x6CFD 0x0042 0x06AB 0x8001 0x0000 0x8000 0x0001 0x0000 0x0000 27: 0x1004 0x64FD 0x0002 0x06AB 0x8001 0x0000 0x8000 0x0001 0x0000 0x0000 28: 0x1004 0x0406 0x4002 0x06AB 0x8001 0x0000 0xE0F9 0x0001 0x0000 0x0000 29: 0x1004 0x0406 0x4002 0x0AAB 0x8001 0x0000 0xE0F9 0x0001 0x0000 0x0000 30: 0x1004 0x64FD 0x0002 0x0EAB 0x8001 0x0000 0x8000 0x0001 0x0000 0x0000 31: 0x1004 0x0406 0x4002 0x0AAB 0x8001 0x0000 0xE0F9 0x0001 0x0000 0x0000 32: 0x1004 0x0406 0x4022 0x0AAB 0x8001 0x0000 0xE0F9 0x0001 0x0000 0x0000 33: 0x100C 0x6CFF 0x0062 0x0EAB 0x8001 0x0000 0x8000 0x0001 0x0000 0x0000 34: 0x101C 0x6CFF 0x0062 0x0EAB 0x8001 0x0000 0x8000 0x0001 0x0000 0x0000 35: 0x181C 0x6CFF 0x0062 0x0EAB 0x8001 0x0000 0x8000 0x0001 0x0000 0x0000 36: 0x1C1C 0x6CFF 0x0062 0x0EAB 0x8001 0x0000 0x8000 0x0001 0x0000 0x0000 37: 0x1E1C 0x6CFF 0x0062 0x0EAB 0x8001 0x0000 0x8000 0x0001 0x0000 0x0000 38: 0x1E1E 0x6CFF 0x0062 0x0EAB 0x8001 0x0000 0x8000 0x0001 0x0000 0x0000 39: 0x1F16 0x0C06 0x4022 0x0AAB 0x8001 0x0000 0xE0F9 0x0001 0x0000 0x0000 40: 0x1F0E 0x6CFF 0x0062 0x0EAB 0x8001 0x0000 0x8000 0x0001 0x0000 0x0000 41: 0x170E 0x6CFF 0x0062 0x0EAB 0x8001 0x0000 0x8000 0x0001 0x0000 0x0000 42: 0x130E 0x6CFF 0x0062 0x0EAB 0x8001 0x0000 0x8000 0x0001 0x0000 0x0000 43: 0x110E 0x6CFF 0x0062 0x0EAB 0x8001 0x0000 0x8000 0x0001 0x0000 0x0000 44: 0x110C 0x6CFF 0x0062 0x0EAB 0x8001 0x0000 0x8000 0x0001 0x0000 0x0000 45: 0x100C 0x6CFF 0x0062 0x0EAB 0x8001 0x0000 0x8000 0x0001 0x0000 0x0000 46: 0x1F16 0x0C06 0x4022 0x0AAB 0x8001 0x0000 0xE0F9 0x0001 0x0000 0x0000 47: 0x1F0E 0x6CFF 0x0062 0x0EAB 0x8001 0x0000 0x8000 0x0001 0x0000 0x0000 48: 0x1F16 0x0C06 0x4022 0x0AAB 0x8001 0x0000 0xE0F9 0x0001 0x0000 0x0000 49: 0x171E 0x6CFF 0x0062 0x0EAB 0x8001 0x0000 0x8000 0x0001 0x0000 0x0000 50: 0x1F16 0x0C06 0x4022 0x0AAB 0x8001 0x0000 0xE0F9 0x0001 0x0000 0x0000 51: 0x1B1E 0x6CFF 0x0062 0x0EAB 0x8001 0x0000 0x8000 0x0001 0x0000 0x0000 52: 0x1F16 0x0C06 0x4022 0x0AAB 0x8001 0x0000 0xE0F9 0x0001 0x0000 0x0000 53: 0x1D1E 0x6CFF 0x0062 0x0EAB 0x8001 0x0000 0x8000 0x0001 0x0000 0x0000 54: 0x1F16 0x0C06 0x4022 0x0AAB 0x8001 0x0000 0xE0F9 0x0001 0x0000 0x0000 55: 0x1F1C 0x6CFF 0x0062 0x0EAB 0x8001 0x0000 0x8000 0x0001 0x0000 0x0000 56: 0x1F16 0x0C06 0x4022 0x0AAB 0x8001 0x0000 0xE0F9 0x0001 0x0000 0x0000 57: 0x1E1E 0x6CFF 0x0062 0x0EAB 0x8001 0x0000 0x8000 0x0001 0x0000 0x0000 58: 0x1F16 0x0C06 0x4022 0x0AAB 0x8001 0x0000 0xE0F9 0x0001 0x0000 0x0000 59: 0x100C 0x6CFF 0x0062 0x0EAB 0x8001 0x0000 0x8000 0x0001 0x0000 0x0000 60: 0x110C 0x6CFF 0x0062 0x0EAB 0x8001 0x0000 0x8000 0x0001 0x0000 0x0000 61: 0x100E 0x6CFF 0x0062 0x0EAB 0x8001 0x0000 0x8000 0x0001 0x0000 0x0000 62: 0x110E 0x6CFF 0x0062 0x0EAB 0x8001 0x0000 0x8000 0x0001 0x0000 0x0000 63: 0x120C 0x6CFF 0x0062 0x0EAB 0x8001 0x0000 0x8000 0x0001 0x0000 0x0000 64: 0x130C 0x6CFF 0x0062 0x0EAB 0x8001 0x0000 0x8000 0x0001 0x0000 0x0000 65: 0x120E 0x6CFF 0x0062 0x0EAB 0x8001 0x0000 0x8000 0x0001 0x0000 0x0000 66: 0x130E 0x6CFF 0x0062 0x0EAB 0x8001 0x0000 0x8000 0x0001 0x0000 0x0000 67: 0x140C 0x6CFF 0x0062 0x0EAB 0x8001 0x0000 0x8000 0x0001 0x0000 0x0000 68: 0x150C 0x6CFF 0x0062 0x0EAB 0x8001 0x0000 0x8000 0x0001 0x0000 0x0000 69: 0x140E 0x6CFF 0x0062 0x0EAB 0x8001 0x0000 0x8000 0x0001 0x0000 0x0000 70: 0x150E 0x6CFF 0x0062 0x0EAB 0x8001 0x0000 0x8000 0x0001 0x0000 0x0000 71: 0x160C 0x6CFF 0x0062 0x0EAB 0x8001 0x0000 0x8000 0x0001 0x0000 0x0000 72: 0x170C 0x6CFF 0x0062 0x0EAB 0x8001 0x0000 0x8000 0x0001 0x0000 0x0000 73: 0x160E 0x6CFF 0x0062 0x0EAB 0x8001 0x0000 0x8000 0x0001 0x0000 0x0000 74: 0x170E 0x6CFF 0x0062 0x0EAB 0x8001 0x0000 0x8000 0x0001 0x0000 0x0000 75: 0x180C 0x6CFF 0x0062 0x0EAB 0x8001 0x0000 0x8000 0x0001 0x0000 0x0000 76: 0x190C 0x6CFF 0x0062 0x0EAB 0x8001 0x0000 0x8000 0x0001 0x0000 0x0000 77: 0x180E 0x6CFF 0x0062 0x0EAB 0x8001 0x0000 0x8000 0x0001 0x0000 0x0000 78: 0x190E 0x6CFF 0x0062 0x0EAB 0x8001 0x0000 0x8000 0x0001 0x0000 0x0000 79: 0x1A0C 0x6CFF 0x0062 0x0EAB 0x8001 0x0000 0x8000 0x0001 0x0000 0x0000 80: 0x1B0C 0x6CFF 0x0062 0x0EAB 0x8001 0x0000 0x8000 0x0001 0x0000 0x0000 81: 0x1A0E 0x6CFF 0x0062 0x0EAB 0x8001 0x0000 0x8000 0x0001 0x0000 0x0000 82: 0x1B0E 0x6CFF 0x0062 0x0EAB 0x8001 0x0000 0x8000 0x0001 0x0000 0x0000 83: 0x1C0C 0x6CFF 0x0062 0x0EAB 0x8001 0x0000 0x8000 0x0001 0x0000 0x0000 84: 0x1D0C 0x6CFF 0x0062 0x0EAB 0x8001 0x0000 0x8000 0x0001 0x0000 0x0000 85: 0x1C0E 0x6CFF 0x0062 0x0EAB 0x8001 0x0000 0x8000 0x0001 0x0000 0x0000 86: 0x1D0E 0x6CFF 0x0062 0x0EAB 0x8001 0x0000 0x8000 0x0001 0x0000 0x0000 87: 0x1E0C 0x6CFF 0x0062 0x0EAB 0x8001 0x0000 0x8000 0x0001 0x0000 0x0000 88: 0x1F0C 0x6CFF 0x0062 0x0EAB 0x8001 0x0000 0x8000 0x0001 0x0000 0x0000 89: 0x1E0E 0x6CFF 0x0062 0x0EAB 0x8001 0x0000 0x8000 0x0001 0x0000 0x0000 90: 0x1F0E 0x6CFF 0x0062 0x0EAB 0x8001 0x0000 0x8000 0x0001 0x0000 0x0000 91: 0x101C 0x6CFF 0x0062 0x0EAB 0x8001 0x0000 0x8000 0x0001 0x0000 0x0000 92: 0x111C 0x6CFF 0x0062 0x0EAB 0x8001 0x0000 0x8000 0x0001 0x0000 0x0000 93: 0x101E 0x6CFF 0x0062 0x0EAB 0x8001 0x0000 0x8000 0x0001 0x0000 0x0000 94: 0x111E 0x6CFF 0x0062 0x0EAB 0x8001 0x0000 0x8000 0x0001 0x0000 0x0000 95: 0x121C 0x6CFF 0x0062 0x0EAB 0x8001 0x0000 0x8000 0x0001 0x0000 0x0000 96: 0x131C 0x6CFF 0x0062 0x0EAB 0x8001 0x0000 0x8000 0x0001 0x0000 0x0000 97: 0x121E 0x6CFF 0x0062 0x0EAB 0x8001 0x0000 0x8000 0x0001 0x0000 0x0000 98: 0x131E 0x6CFF 0x0062 0x0EAB 0x8001 0x0000 0x8000 0x0001 0x0000 0x0000 99: 0x141C 0x6CFF 0x0062 0x0EAB 0x8001 0x0000 0x8000 0x0001 0x0000 0x0000 100: 0x151C 0x6CFF 0x0062 0x0EAB 0x8001 0x0000 0x8000 0x0001 0x0000 0x0000 101: 0x141E 0x6CFF 0x0062 0x0EAB 0x8001 0x0000 0x8000 0x0001 0x0000 0x0000 102: 0x151E 0x6CFF 0x0062 0x0EAB 0x8001 0x0000 0x8000 0x0001 0x0000 0x0000 103: 0x161C 0x6CFF 0x0062 0x0EAB 0x8001 0x0000 0x8000 0x0001 0x0000 0x0000 104: 0x171C 0x6CFF 0x0062 0x0EAB 0x8001 0x0000 0x8000 0x0001 0x0000 0x0000 105: 0x161E 0x6CFF 0x0062 0x0EAB 0x8001 0x0000 0x8000 0x0001 0x0000 0x0000 106: 0x171E 0x6CFF 0x0062 0x0EAB 0x8001 0x0000 0x8000 0x0001 0x0000 0x0000 107: 0x181C 0x6CFF 0x0062 0x0EAB 0x8001 0x0000 0x8000 0x0001 0x0000 0x0000 108: 0x191C 0x6CFF 0x0062 0x0EAB 0x8001 0x0000 0x8000 0x0001 0x0000 0x0000 109: 0x181E 0x6CFF 0x0062 0x0EAB 0x8001 0x0000 0x8000 0x0001 0x0000 0x0000 110: 0x191E 0x6CFF 0x0062 0x0EAB 0x8001 0x0000 0x8000 0x0001 0x0000 0x0000 111: 0x1A1C 0x6CFF 0x0062 0x0EAB 0x8001 0x0000 0x8000 0x0001 0x0000 0x0000 112: 0x1B1C 0x6CFF 0x0062 0x0EAB 0x8001 0x0000 0x8000 0x0001 0x0000 0x0000 113: 0x1A1E 0x6CFF 0x0062 0x0EAB 0x8001 0x0000 0x8000 0x0001 0x0000 0x0000 114: 0x1B1E 0x6CFF 0x0062 0x0EAB 0x8001 0x0000 0x8000 0x0001 0x0000 0x0000 115: 0x1C1C 0x6CFF 0x0062 0x0EAB 0x8001 0x0000 0x8000 0x0001 0x0000 0x0000 116: 0x1D1C 0x6CFF 0x0062 0x0EAB 0x8001 0x0000 0x8000 0x0001 0x0000 0x0000 117: 0x1C1E 0x6CFF 0x0062 0x0EAB 0x8001 0x0000 0x8000 0x0001 0x0000 0x0000 118: 0x1D1E 0x6CFF 0x0062 0x0EAB 0x8001 0x0000 0x8000 0x0001 0x0000 0x0000 119: 0x1E1C 0x6CFF 0x0062 0x0EAB 0x8001 0x0000 0x8000 0x0001 0x0000 0x0000 120: 0x1F1C 0x6CFF 0x0062 0x0EAB 0x8001 0x0000 0x8000 0x0001 0x0000 0x0000 121: 0x1E1E 0x6CFF 0x0062 0x0EAB 0x8001 0x0000 0x8000 0x0001 0x0000 0x0000 122: 0x1F16 0x0C06 0x4022 0x0AAB 0x8001 0x0000 0xE0F9 0x0001 0x0000 0x0000 123: 0x1F1E 0x0C06 0x4062 0x0AA9 0x8001 0x0000 0xE0F9 0x0001 0x0000 0x0000 124: 0x1F1E 0x0C06 0x4062 0x06A9 0x8001 0x0000 0xE0F9 0x0001 0x0000 0x0000 125: 0x1F1E 0x6CFD 0x0062 0x06A9 0x8001 0x0000 0x8000 0x0001 0x0000 0x0000 126: 0x100C 0x6CFD 0x0062 0x06A9 0x8001 0x0000 0x8000 0x0001 0x0000 0x0000 127: 0x100C 0x6CFD 0x0062 0x06A9 0x8001 0x0000 0x8000 0x0001 0x0000 0x0000 128: 0x100C 0x6CFD 0x0062 0x07A9 0x8001 0x0000 0x8000 0x0001 0x0000 0x0000 129: 0x100C 0x6CFD 0x0062 0x06A9 0x8001 0x0000 0x8000 0x0001 0x0000 0x0000 130: 0x100C 0x6CF9 0x0062 0x06B9 0x8001 0x0000 0x8000 0x0001 0x0000 0x0000 131: 0x100C 0x6CFD 0x0062 0x06A9 0x8001 0x0000 0x8000 0x0001 0x0000 0x0000 132: 0x100C 0x7CFD 0x0062 0x06A9 0x8001 0x0000 0x8000 0x0001 0x0000 0x0000 133: 0x100C 0x6CFD 0x0062 0x06A9 0x8001 0x0000 0x8000 0x0001 0x0000 0x0000 134: 0x100C 0x6CFD 0x0062 0x07A9 0x8001 0x0000 0x8000 0x0001 0x0000 0x0000 135: 0x100C 0x6CF9 0x0062 0x07B9 0x8001 0x0000 0x8000 0x0001 0x0000 0x0000 136: 0x100C 0x6CFD 0x0062 0x07A9 0x8001 0x0000 0x8000 0x0001 0x0000 0x0000 137: 0x100C 0x7CFD 0x0062 0x07A9 0x8001 0x0000 0x8000 0x0001 0x0000 0x0000 138: 0x100C 0x6CFD 0x0062 0x07A9 0x8001 0x0000 0x8000 0x0001 0x0000 0x0000 139: 0x100C 0x6CFD 0x0062 0x06A9 0x8001 0x0000 0x8000 0x0001 0x0000 0x0000 140: 0x100C 0x7CFD 0x0062 0x06A9 0x8001 0x0000 0x8000 0x0001 0x0000 0x0000 141: 0x100C 0x7CF9 0x0062 0x06B9 0x8001 0x0000 0x8000 0x0001 0x0000 0x0000 142: 0x100C 0x7CFD 0x0062 0x06A9 0x8001 0x0000 0x8000 0x0001 0x0000 0x0000 143: 0x100C 0x6CFD 0x0062 0x06A9 0x8001 0x0000 0x8000 0x0001 0x0000 0x0000 144: 0x100C 0x7CFD 0x0062 0x06A9 0x8001 0x0000 0x8000 0x0001 0x0000 0x0000 145: 0x100C 0x7CFD 0x0062 0x07A9 0x8001 0x0000 0x8000 0x0001 0x0000 0x0000 146: 0x100C 0x78FD 0x0062 0x07A9 0x8001 0x0000 0x8000 0x0001 0x0000 0x0000 147: 0x100C 0x78F9 0x0062 0x0791 0x800D 0x0000 0x8000 0x0001 0x0000 0x0000 148: 0x1F1E 0x9802 0x4062 0x0791 0x800D 0x0000 0x0000 0x0001 0x0000 0x0000 149: 0x1F1F 0x9802 0x4062 0x0791 0x800D 0x0000 0x0000 0x0001 0x0000 0x0000 150: 0x1F1F 0x8802 0x4062 0x0791 0x800D 0x0000 0x0000 0x0001 0x0000 0x0000 151: 0x1F1F 0x9802 0x4062 0x0791 0x800D 0x0000 0x0000 0x0001 0x0000 0x0000 152: 0x1F1F 0x8802 0x4062 0x0791 0x800D 0x0000 0x0000 0x0001 0x0000 0x0000 153: 0x1F1F 0x9802 0x4062 0x0791 0x800D 0x0000 0x0000 0x0001 0x0000 0x0000 154: 0x1F1F 0x8802 0x4062 0x0791 0x800D 0x0000 0x0000 0x0001 0x0000 0x0000 155: 0x1F1F 0x9802 0x4062 0x0791 0x000F 0x0000 0x0000 0x0001 0x0000 0x0000 156: 0x1F1F 0x8802 0x4062 0x0791 0x000F 0x0000 0x0000 0x0001 0x0000 0x0000 157: 0x1F1F 0x9802 0x4062 0x0791 0x000F 0x0000 0x0000 0x0001 0x0000 0x0000 158: 0x1F1F 0x8802 0x4062 0x0791 0x000F 0x0000 0x0000 0x0001 0x0000 0x0000 159: 0x1F1F 0x9802 0x4062 0x0791 0x000F 0x0000 0x0000 0x0001 0x0000 0x0000 160: 0x1F1F 0x8802 0x4062 0x0791 0x000F 0x0000 0x0000 0x0001 0x0000 0x0000 161: 0x1F1F 0x9802 0x4062 0x0791 0x000F 0x0000 0x0000 0x0001 0x0000 0x0000 162: 0x1F1F 0x8802 0x4062 0x0791 0x000F 0x0000 0x0000 0x0001 0x0000 0x0000 163: 0x1F1F 0x9802 0x4062 0x0791 0x800D 0x0000 0x0000 0x0001 0x0000 0x0000 164: 0x1F1F 0x8802 0x4062 0x0791 0x800D 0x0000 0x0000 0x0001 0x0000 0x0000 165: 0x1F1F 0x9802 0x4062 0x0791 0x800D 0x0000 0x0000 0x0001 0x0000 0x0000 166: 0x1F1F 0x8802 0x4062 0x0791 0x800D 0x0000 0x0000 0x0001 0x0000 0x0000 167: 0x1F1F 0x9802 0x4062 0x0791 0x800D 0x0000 0x0000 0x0001 0x0000 0x0000 168: 0x1F1F 0x8802 0x4062 0x0791 0x800D 0x0000 0x0000 0x0001 0x0000 0x0000 169: 0x1F1F 0x9802 0x4062 0x0791 0x800D 0x0000 0x0000 0x0001 0x0000 0x0000 170: 0x1F1F 0x8802 0x4062 0x0791 0x800D 0x0000 0x0000 0x0001 0x0000 0x0000 171: 0x1F1F 0x9802 0x4062 0x0791 0x000F 0x0000 0x0000 0x0001 0x0000 0x0000 172: 0x1F1F 0x9802 0x4062 0x07D1 0x000F 0x0000 0x0000 0x0001 0x0000 0x0000 173: 0x1F1F 0x9802 0x4062 0x0791 0x000F 0x0000 0x0000 0x0001 0x0000 0x0000 174: 0x1F1F 0x9802 0x4062 0x07D1 0x000F 0x0000 0x0000 0x0001 0x0000 0x0000 175: 0x1F1F 0x9802 0x4062 0x0791 0x000F 0x0000 0x0000 0x0001 0x0000 0x0000 176: 0x1F1F 0x9806 0x4062 0x0781 0x000F 0x0000 0x0000 0x0001 0x0000 0x0000 177: 0x1F1F 0x9C06 0x4062 0x0781 0x000F 0x0000 0x0000 0x0001 0x0000 0x0000 178: 0x1F1F 0x9C06 0x4062 0x07A1 0xA00D 0x0000 0x0000 0x0001 0x0000 0x0000 179: 0x1F1F 0x9C06 0x4062 0x07A1 0x800D 0x0000 0x0000 0x0001 0x0000 0x0000 180: 0x1F1F 0x9806 0x4062 0x07A1 0x800D 0x0000 0x0000 0x0001 0x0000 0x0000 181: 0x1F1F 0x9802 0x4062 0x0791 0x800D 0x0000 0x0000 0x0001 0x0000 0x0000 182: 0x1F1F 0x8802 0x4062 0x0791 0x800D 0x0000 0x0000 0x0001 0x0000 0x0000 183: 0x1F1F 0x9802 0x4062 0x0791 0x800D 0x0000 0x0000 0x0001 0x0000 0x0000 184: 0x1F1F 0x8802 0x4062 0x0791 0x800D 0x0000 0x0000 0x0001 0x0000 0x0000 185: 0x1F1F 0x9802 0x4062 0x0791 0x800D 0x0000 0x0000 0x0001 0x0000 0x0000 186: 0x1F1F 0x8802 0x4062 0x0791 0x800D 0x0000 0x0000 0x0001 0x0000 0x0000 187: 0x1F1F 0x9802 0x4062 0x0791 0x800D 0x0000 0x0000 0x0001 0x0000 0x0000 188: 0x1F1F 0x8802 0x4062 0x0791 0x800D 0x0000 0x0000 0x0001 0x0000 0x0000 189: 0x1F1F 0x9802 0x4062 0x0791 0x000F 0x0000 0x0000 0x0001 0x0000 0x0000 190: 0x1F1F 0x9803 0x4062 0x0791 0x200F 0x0000 0x0000 0x0001 0x0000 0x0000 191: 0x1F1F 0x9803 0x4062 0x0791 0x000F 0x0000 0x0000 0x0001 0x0000 0x0000 192: 0x1F1F 0x9823 0x4062 0x0791 0x200F 0x0000 0x0000 0x0001 0x0000 0x0000 193: 0x1F1F 0x9823 0x4062 0x0791 0x000F 0x0000 0x0000 0x0001 0x0000 0x0000 194: 0x1F1F 0x1863 0x4062 0x0791 0x200F 0x0000 0x0000 0x0001 0x0000 0x0000 195: 0x1F1E 0x1863 0x4062 0x0791 0x200F 0x0000 0x0000 0x0001 0x0000 0x0000 196: 0x1F1E 0x1863 0x4062 0x0791 0x000F 0x0000 0x0000 0x0001 0x0000 0x0000 197: 0x1F1E 0x5863 0x4062 0x0791 0x200F 0x0000 0x0000 0x0001 0x0000 0x0000 198: 0x1F1E 0x5863 0x4062 0x0791 0x000F 0x0000 0x0000 0x0001 0x0000 0x0000 199: 0x1F1E 0x7863 0x4062 0x0791 0x200F 0x0000 0x0000 0x0001 0x0000 0x0000 200: 0x1F1E 0x7863 0x4062 0x0791 0x000F 0x0000 0x0000 0x0001 0x0000 0x0000 201: 0x1F1E 0x7873 0x4062 0x0791 0x200F 0x0000 0x0000 0x0001 0x0000 0x0000 202: 0x1F1E 0x7873 0x4062 0x0791 0x000F 0x0000 0x0000 0x0001 0x0000 0x0000 203: 0x1F1E 0x78F3 0x4062 0x0791 0x200F 0x0000 0x0000 0x0001 0x0000 0x0000 204: 0x1F1E 0x78F3 0x4062 0x0791 0x000F 0x0000 0x0000 0x0001 0x0000 0x0000 205: 0x1F1E 0x78FB 0x4062 0x0791 0x200F 0x0000 0x0000 0x0001 0x0000 0x0000 206: 0x1F1E 0x78FB 0x4062 0x0791 0x000F 0x0000 0x0000 0x0001 0x0000 0x0000 207: 0x1F1A 0x78FB 0x4062 0x0790 0x200F 0x0000 0x0000 0x0001 0x0000 0x0000 208: 0x1F1A 0x78F9 0x0062 0x0790 0x200F 0x0000 0x0000 0x0001 0x0000 0x0000 209: 0x1F1A 0x78FB 0x4062 0x0790 0x200F 0x0000 0x0000 0x0001 0x0000 0x0000 210: 0x1F1A 0x78FB 0x4042 0x0791 0x200F 0x0000 0x0000 0x0001 0x0000 0x0000 211: 0x1F1A 0x78FB 0x4042 0x07B1 0x000F 0x0000 0x0000 0x0001 0x0000 0x0000 212: 0x1F1A 0x78FF 0x4042 0x07A1 0x000F 0x0000 0x0000 0x0001 0x0000 0x0000 213: 0x1F1A 0x7CFF 0x4042 0x07A1 0x000F 0x0000 0x0000 0x0001 0x0000 0x0000 214: 0x1F1A 0x7CFF 0x4042 0x07A1 0x200F 0x0000 0x0000 0x0001 0x0000 0x0000 215: 0x1F1A 0x7CFF 0x4042 0x07A1 0x000F 0x0000 0x0000 0x0001 0x0000 0x0000 216: 0x1F1A 0x7CFF 0x4042 0x07A1 0x200F 0x0000 0x0000 0x0001 0x0000 0x0000 217: 0x1F1A 0x7CFF 0x4042 0x07A1 0x000F 0x0000 0x0000 0x0001 0x0000 0x0000 218: 0x1F1A 0x7CFF 0x4042 0x0721 0x800D 0x0000 0x0000 0x0001 0x0000 0x0000 PINs used (in edge connector order) (G=ground,P=power) SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBB LETTER ABCDEFHJKLMNPRSTUVABCDEFHJKLMNPRSTUVABCDEFHJKLMNPRSTUVABCDEFHJKLMNPRSTUV SIDE 111111111111111111222222222222222222111111111111111111222222222222222222 USAGE OIIIIOOOIIIOG OP GIOOIIOIOOOOOOOI I IOIIOGI P GIOIOI OIOIIOOOO UUT inputs: 23 UUT outputs: 26 pins used: 49 not used: 17 218 'test steps' 397 lines M706 PCB REV K SCHEMATIC REV L TELETYPE RECEIVER NOTE: 17 PINS not used 1 AA1 PAD, NOT CONNECTED 2 AB1 NOT CONNECTED 3 AC1 NOT CONNECTED 4 AU1 NOT CONNECTED 5 AB2 NOT CONNECTED 6 BA1 NOT CONNECTED 7 BB1 NOT CONNECTED 8 BC1 NOT CONNECTED 9 BE1 NOT CONNECTED 10 BF1 NOT CONNECTED 11 BH1 NOT CONNECTED 12 BJ1 NOT CONNECTED 13 BK1 NOT CONNECTED 14 BL1 PAD, NOT CONNECTED 15 BV1 PAD, NOT CONNECTED 16 BB2 NOT CONNECTED 17 BK2 NOT CONNECTED CPU schematics shows output TT SHIFT-N PINS Main menu Sun Jul 09 15:29:37 2017 test file is: tests\m706k.tst delay is: 0 trigger is: 1 1 read test file 2 set test delay 3 set test trigger 4 run test 5 output loading test 8 diags 9 exit ***************************** UUT power is OFF * ***************************** Main menu Sun Jul 09 15:29:38 2017 test file is: tests\m706k.tst delay is: 0 trigger is: 1 1 read test file 2 set test delay 3 set test trigger 4 run test 5 output loading test 8 diags 9 exit key is 0x0073 Main menu Sun Jul 09 15:29:39 2017 test file is: tests\m706k.tst delay is: 0 trigger is: 1 1 read test file 2 set test delay 3 set test trigger 4 run test 5 output loading test 8 diags 9 exit UUT power is okay Sun Jul 09 15:29:42 2017 space single step O run once (one test, all steps) F run, stop on fail G go (run tests N run, stop on fail, no print S scope (run, no print) C turn on comment printout + increase speed (less delay) - decrease speed (more delay)(slower) Q quit test scope (run, no print) ppppppppppppppppppppppppppppppppppppppppp space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn on comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAAAAAAAABBBBAABBBABABABBABBBBBBBBABAAABAAAAAAAAA LETTER DLDEFHHJPFJEDEVMNDFHVLUNSNSTPPUVRMMRRKJUSKRSLMPTN SIDE 1221112112221211122222222112212222211121122211222 DIRECTION OIIIIIIIIIIOIOOIOIOOIOOOOIOOIIOOIIOIIOIIOOOOOOOOO all fails was lo 00000000000000000000000 000000000000000000000000 falling vvvvvvvvvvvvvvvvvvvvv v vvvvvvvvvvvvvvv vvvvvvvv rising ^^^^^^^^^^^^^^^^^^^^^ ^ ^^^^^^^^^^^^^^^ ^^^^^^^^ was hi 1111111111111111111111 11111111111111111 11111111 total fails 0, total passes 41 Main menu Sun Jul 09 15:29:48 2017 test file is: tests\m706k.tst delay is: 0 trigger is: 1 1 read test file 2 set test delay 3 set test trigger 4 run test 5 output loading test 8 diags 9 exit Enter test file name? trying to open test file: tests\m707d could not open test file. valid test files are: reverting back to test file: tests\m706k.tst Main menu Sun Jul 09 15:30:30 2017 test file is: tests\m706k.tst delay is: 0 trigger is: 1 1 read test file 2 set test delay 3 set test trigger 4 run test 5 output loading test 8 diags 9 exit Enter test file name? trying to open test file: tests\m707d.tst reading test file: tests\m707d.tst comment: M707 PCB REV D SCHEMATIC REV c TELETYPE TRANSMITTER comment: comment: ICs are VERTICAL on PCB REV D. comment: comment: Rev D adds AB1 ECHO input. comment: comment: does not test AV2 20MA OUTPUT, use scope and pulldown comment: comment: or use M707D_MA.TST to test 20MA OUTPUT (needs jumper) comment: pins: PINS pins: 1 O BJ1 +3V pins: 2 I BF2 CLEAR FLAG 2-N (NORMALLY 3V) pins: 3 I BE2 I/O CLEAR (NORMALLY INITIALIZE) pins: 4 I BP2 2 X BAUD CLOCK INPUT pins: 5 I AE1 (DEVICE SELECTOR BMB IN) (NAND)->(DEVICE SELECT-N) (NORMALLY MB04-N) pins: 6 I AE2 (DEVICE SELECTOR BMB IN) (NAND)->(DEVICE SELECT-N) (NORMALLY MB03-N) pins: 7 I AF1 (DEVICE SELECTOR BMB IN) (NAND)->(DEVICE SELECT-N) (NORMALLY MB06) pins: 8 I AF2 (DEVICE SELECTOR BMB IN) (NAND)->(DEVICE SELECT-N) (NORMALLY MB05-N) pins: 9 I AH2 (DEVICE SELECTOR BMB IN) (NAND)->(DEVICE SELECT-N) (NORMALLY MB08-N) pins: 10 I AJ2 (DEVICE SELECTOR BMB IN) (NAND)->(DEVICE SELECT-N) (NORMALLY MB07-N) pins: 11 I AN1 (FORCE SELECT-N) (NORMALLY HI) NAND(DEVICE SELECT-N)=(SELECTED) pins: 12 I BH2 I/O SKP. STROBE (NORMALLY IOT 1) pins: 13 O BJ2 I/O SKP.-N (NAND OF I/O SKP. STROBE, FLAG, DEV DECODE) pins: 14 O BK2 P.I.REQ-N (FLAG-N) pins: 15 I BD2 CLEAR FLAG 1 (NORMALLY IOT 2) pins: 16 I AS1 LOAD BUFFER (NORMALLY IOT 4) pins: 17 I AR1 LOAD BUFFER STROBE-N (NAND SELECTED, LOAD BUFFER) pins: 18 I BS2 WAIT-N (PROLONGS STOP BITS) (NORMALLY 3V) pins: 19 O BR2 STOP 1-N pins: 20 O BP1 STOP 1.5-N pins: 21 O BN1 STOP 2-N pins: 22 I BN2 (STOP SELECT) (MUST BE HI TO SET ACTIVE I.E. TX NEXT CHARACTER) pins: 23 O AJ1 (BIT 6) (CONNECTS TO AK1 FOR 5 BIT OUTPUT) pins: 24 O AK2 (ENABLE) (CONNECTS TO AK1 FOR 8 BIT OUTPUT) pins: 25 I AK1 (CHARACTER LOADED) (MUST BE HI TO SET ACTIVE I.E. TX NEXT CHARACTER) pins: 26 O AL1 (ENABLE-N) (NORMALLY CONNECTS TO DECODE INPUT 8) pins: 27 I AH1 (DECODE INPUT 8) (NORMALLY CONNECTS TO (ENABLE-N) pins: 28 I AN2 ENABLE (NORMALLY 3V) pins: 29 I AP2 BIT 8 (NORMALLY AC4) pins: 30 I AR2 BIT 7 (NORMALLY AC5) pins: 31 I AL2 BIT 6 (NORMALLY AC6) pins: 32 I AM2 BIT 5 (NORMALLY AC7) pins: 33 I AU2 BIT 4 (NORMALLY AC8) pins: 34 I AS2 BIT 3 (NORMALLY AC9) pins: 35 I AT2 BIT 2 (NORMALLY AC10) pins: 36 I AU1 BIT 1 (NORMALLY AC11) pins: 37 O AD1 ACTIVE pins: 38 O AD2 LINE pins: 39 O AV2 20MA OUTPUT (PNP TO +) pins: 40 I AB1 ECHO (ORS WITH LINE -> 20MA OUTPUT) pins: direction: OIIIIIIIIIIIOOIIIIOOOIOOIOIIIIIIIIIIOOOI comment: ; set CLEAR FLAG 2-N, I/O CLEAR comment: ; note: STOP FF outputs are unknown. comment: ; note: 20MA output can not test (open emitter) test 1: 111000000010110011XXX00001110000000001X1 comment: ; remove I/O CLEAR test 2: 0 comment: ; clock 2 X BAUD CLOCK INPUT to set STOP FFs test 3: 1 1 test 4: 0 test 5: 1 1 test 6: 0 test 7: 1 1 test 8: 0 comment: ; set (STOP SELECT since all 3 STOP FFs are HI) test 9: 1 comment: ; comment: ; test DEVICE DECODER comment: ; comment: ; turn on LOAD BUFFER (normally IOP4) test 10: 1 comment: ; comment: ; set up to load ENABLE/55h (alternating ones) comment: ; test 11: 101010101 comment: ; turn on DEVICE ADDRESS bits, LOAD BUFFER STROBE-N goes LO comment: ; (ENABLE) will go HI (note: next CLOCK starts TX...) comment: ; (ENABLE-N) will go LO test 12: 111111 0 1 0 comment: ; (ENABLE-N) is LO so change (DECODE INPUT 8) (normally connects to (ENABLE-N) test 13: 0 comment: ; remove DEVICE ADDRESS, LOAD BUFFER STROBE-N goes HI comment: ; since (ENABLE) is HI, set (CHARACTER LOADED) (normal 8 BIT TX) test 14: 000000 1 1 comment: ; toggle (FORCE SELECT-N), LOAD BUFFER STROBE-N goes LO test 15: 0 0 test 16: 1 1 comment: ; test all DEVICE ADDRESS combinations test 17: 000000 1 test 18: 000001 1 test 19: 000010 1 test 20: 000011 1 test 21: 000100 1 test 22: 000101 1 test 23: 000110 1 test 24: 000111 1 test 25: 001000 1 test 26: 001001 1 test 27: 001010 1 test 28: 001011 1 test 29: 001100 1 test 30: 001101 1 test 31: 001110 1 test 32: 001111 1 test 33: 010000 1 test 34: 010001 1 test 35: 010010 1 test 36: 010011 1 test 37: 010100 1 test 38: 010101 1 test 39: 010110 1 test 40: 010111 1 test 41: 011000 1 test 42: 011001 1 test 43: 011010 1 test 44: 011011 1 test 45: 011100 1 test 46: 011101 1 test 47: 011110 1 test 48: 011111 1 test 49: 100000 1 test 50: 100001 1 test 51: 100010 1 test 52: 100011 1 test 53: 100100 1 test 54: 100101 1 test 55: 100110 1 test 56: 100111 1 test 57: 101000 1 test 58: 101001 1 test 59: 101010 1 test 60: 101011 1 test 61: 101100 1 test 62: 101101 1 test 63: 101110 1 test 64: 101111 1 test 65: 110000 1 test 66: 110001 1 test 67: 110010 1 test 68: 110011 1 test 69: 110100 1 test 70: 110101 1 test 71: 110110 1 test 72: 110111 1 test 73: 111000 1 test 74: 111001 1 test 75: 111010 1 test 76: 111011 1 test 77: 111100 1 test 78: 111101 1 test 79: 111110 1 test 80: 111111 0 comment: ; remove LOAD BUFFER (normally IOP4) test 81: 01 comment: ; remove DEVICE ADDRESS test 82: 000000 comment: ; comment: ; comment: ; send the 0x55 character comment: ; comment: ; comment: ; on first 2 X BAUD CLOCK INPUT comment: ; ACTIVE is SET, causes LINE to CLEAR (i.e. START BIT). comment: ; test 83: 1 10 test 84: 0 comment: ; the 2nd 2 X BAUD CLOCK INPUT causes the STOP FFs to PRESET test 85: 1 000 test 86: 0 comment: ; ORGINAL BIT 1 (AC11) goes to LINE comment: ; (BIT 6) shifts comment: ; (ENABLE) goes LO, (ENABLE-N) goes HI test 87: 1 10 1 1 comment: ; since (ENABLE) is LO, change (CHARACTER LOADED) (i.e. 8 not 5) test 88: 0 comment: ; (ENABLE-N) is HI so change (DECODE INPUT 8) (normally connects to (ENABLE-N) test 89: 1 test 90: 0 test 91: 1 test 92: 0 comment: ; ORGINAL BIT 2 (AC10) goes to LINE test 93: 1 0 0 test 94: 0 test 95: 1 test 96: 0 comment: ; ORGINAL BIT 3 (AC9) goes to LINE comment: ; (BIT 6) shifts test 97: 1 1 1 test 98: 0 test 99: 1 test 100: 0 comment: ; ORGINAL BIT 4 (AC8) goes to LINE test 101: 1 0 0 test 102: 0 test 103: 1 test 104: 0 comment: ; ORGINAL BIT 5 (AC7) goes to LINE comment: ; test 105: 1 0 1 test 106: 0 test 107: 1 test 108: 0 comment: ; ORGINAL BIT 6 (AC6) goes to LINE test 109: 1 0 test 110: 0 test 111: 1 test 112: 0 comment: ; ORGINAL BIT 7 (AC5) goes to LINE test 113: 1 1 test 114: 0 test 115: 1 test 116: 0 comment: ; ORGINAL BIT 8 (AC4) goes to LINE test 117: 1 0 test 118: 0 test 119: 1 test 120: 0 comment: ; ORGINAL (ENABLE) goes to LINE (STOP BITS) comment: ; (ACTIVE) goes LO comment: ; P.I.REQ-N (FLAG-N) goes LO...FLAG is ON test 121: 1 0 01 test 122: 0 comment: ; STOP FFs bits start counting... test 123: 1 1 test 124: 0 test 125: 1 1 test 126: 0 test 127: 1 1 comment: ; since STOP 2-N went HI, set (STOP SELECT) (i.e. 2 STOP BITS) test 128: 1 test 129: 0 test 130: 1 test 131: 0 comment: ; comment: ; try the I/O SKIP comment: ; comment: ; turn on DEVICE ADDRESS bits test 132: 111111 comment: ; toggle I/O SKP.STROBE I/O SKP.-N pulses LO (active) test 133: 10 test 134: 01 comment: ; turn off DEVICE ADDRESS bits test 135: 000000 comment: ; toggle I/O SKP.STROBE- I/O SKP.-N stays HI (inactive) test 136: 1 test 137: 0 comment: ; turn on DEVICE ADDRESS bits test 138: 111111 comment: ; set I/O SKP. STROBE, I/O SKP.-N goes LO test 139: 10 comment: ; clear the FLAG- pulse CLEAR FLAG 1, I/O SKP.-n goes HI comment: ; P.I.REQ-N (FLAG-N) goes HI...FLAG is OFF test 140: 111 test 141: 0 comment: ; turn off I/O SKP. STROBE test 142: 0 comment: ; turn off DEVICE ADDRESS bits test 143: 000000 test 144: 11000000001011001111110001110101010101X1 comment: ; comment: ; comment: ; send a 0xAA comment: ; comment: ; comment: ; set up to load ENABLE/0xAA (alternating ones) test 145: 110101010 comment: ; turn on DEVICE ADDRESS bits test 146: 111111 comment: ; turn on LOAD BUFFER (normally IOP4) comment: ; LOAD BUFFER STROBE-N goes LO comment: ; (BIT 6) goes HI comment: ; (ENABLE) goes HI (note: next CLOCK starts TX...) comment: ; (ENABLE-N) goes LO test 147: 10 11 0 comment: ; (ENABLE) is HI, so set (CHARACTER LOADED) (normal 8 BIT TX) test 148: 1 comment: ; (ENABLE-N) is LO, so change (DECODE INPUT 8) (normally connects to (ENABLE-N) test 149: 0 comment: ; remove LOAD BUFFER (normally IOP4) test 150: 01 comment: ; remove DEVICE ADDRESS test 151: 000000 comment: ; comment: ; shift out the 0xAA character comment: ; comment: ; on first 2 X BAUD CLOCK INPUT comment: ; ACTIVE is SET, causes LINE to CLEAR (i.e. START BIT). comment: ; test 152: 1 10 test 153: 0 comment: ; the 2nd 2 X BAUD CLOCK INPUT causes the STOP FFs to PRESET test 154: 1 000 test 155: 0 comment: ; ORGINAL BIT 1 (AC11) goes to LINE comment: ; (BIT 6) shifts comment: ; (ENABLE) goes LO, (ENABLE-N) goes HI test 156: 1 00 1 0 comment: ; since (ENABLE) is LO, change (CHARACTER LOADED) (i.e. 8 not 5) test 157: 0 comment: ; since (ENABLE-N) is HI, change (DECODE INPUT 8) (normally connects to (ENABLE-N) test 158: 1 test 159: 0 test 160: 1 test 161: 0 comment: ; ORGINAL BIT 2 (AC10) goes to LINE test 162: 1 1 1 test 163: 0 test 164: 1 test 165: 0 comment: ; ORGINAL BIT 3 (AC9) goes to LINE comment: ; (BIT 6) becomes original ENABLE test 166: 1 1 0 test 167: 0 test 168: 1 test 169: 0 comment: ; ORGINAL BIT 4 (AC8) goes to LINE comment: ; (BIT 6) goes LO test 170: 1 0 1 test 171: 0 test 172: 1 test 173: 0 comment: ; ORGINAL BIT 5 (AC7) goes to LINE comment: ; test 174: 1 0 0 test 175: 0 test 176: 1 test 177: 0 comment: ; ORGINAL BIT 6 (AC6) goes to LINE test 178: 1 1 test 179: 0 test 180: 1 test 181: 0 comment: ; ORGINAL BIT 7 (AC5) goes to LINE test 182: 1 0 test 183: 0 test 184: 1 test 185: 0 comment: ; ORGINAL BIT 8 (AC4) goes to LINE test 186: 1 1 test 187: 0 test 188: 1 test 189: 0 comment: ; ORGINAL (ENABLE) goes to LINE (STOP BITS) comment: ; (ACTIVE) goes LO comment: ; P.I.REQ-N (FLAG-N) goes LO...FLAG is ON test 190: 1 0 01 test 191: 0 comment: ; STOP FFs bits start counting... test 192: 1 1 test 193: 0 test 194: 1 1 test 195: 0 test 196: 1 1 comment: ; since STOP 2-N went HI, set (STOP SELECT) (i.e. 2 STOP BITS) test 197: 1 test 198: 0 test 199: 1 test 200: 0 comment: ; comment: ; try the I/O SKIP comment: ; comment: ; turn on DEVICE ADDRESS bits test 201: 111111 comment: ; toggle I/O SKP.STROBE I/O SKP.-N pulses LO (active) test 202: 10 test 203: 01 comment: ; turn off DEVICE ADDRESS bits test 204: 000000 comment: ; toggle I/O SKP.STROBE- I/O SKP.-N stays HI (inactive) test 205: 1 test 206: 0 comment: ; turn on DEVICE ADDRESS bits test 207: 111111 comment: ; set I/O SKP. STROBE, I/O SKP.-N goes LO test 208: 10 comment: ; clear the FLAG- pulse CLEAR FLAG 1, I/O SKP.-n goes HI comment: ; P.I.REQ-N (FLAG-N) goes HI...FLAG is OFF test 209: 111 test 210: 0 comment: ; turn off I/O SKP. STROBE test 211: 0 comment: ; turn off DEVICE ADDRESS bits test 212: 000000 test 213: 11000000001011001111110001110101010101X1 comment: ; comment: ; comment: ; send a 0x00 comment: ; comment: ; comment: ; set up to load ENABLE/0x00 (all zeroes) test 214: 100000000 comment: ; turn on DEVICE ADDRESS bits test 215: 111111 comment: ; turn on LOAD BUFFER (normally IOP4) comment: ; LOAD BUFFER STROBE-N goes LO comment: ; (BIT 6) goes LO comment: ; (ENABLE) goes HI (note: next CLOCK starts TX...) comment: ; (ENABLE-N) goes LO test 216: 10 01 0 comment: ; (ENABLE) is HI, so set (CHARACTER LOADED) (normal 8 BIT TX) test 217: 1 comment: ; (ENABLE-N) is LO, so change (DECODE INPUT 8) (normally connects to (ENABLE-N) test 218: 0 comment: ; remove LOAD BUFFER (normally IOP4) test 219: 01 comment: ; remove DEVICE ADDRESS test 220: 000000 comment: ; comment: ; shift out the 0x00 character comment: ; comment: ; on first 2 X BAUD CLOCK INPUT comment: ; ACTIVE is SET, causes LINE to CLEAR (i.e. START BIT). comment: ; test 221: 1 10 test 222: 0 comment: ; the 2nd 2 X BAUD CLOCK INPUT causes the STOP FFs to PRESET test 223: 1 000 test 224: 0 comment: ; ORGINAL BIT 1 (AC11) goes to LINE comment: ; (BIT 6) shifts comment: ; (ENABLE) goes LO, (ENABLE-N) goes HI test 225: 1 00 1 0 comment: ; since (ENABLE) is LO, change (CHARACTER LOADED) (i.e. 8 not 5) test 226: 0 comment: ; since (ENABLE-N) is HI, change (DECODE INPUT 8) (normally connects to (ENABLE-N) test 227: 1 test 228: 0 test 229: 1 test 230: 0 comment: ; ORGINAL BIT 2 (AC10) goes to LINE test 231: 1 0 0 test 232: 0 test 233: 1 test 234: 0 comment: ; ORGINAL BIT 3 (AC9) goes to LINE comment: ; (BIT 6) becomes original ENABLE test 235: 1 1 0 test 236: 0 test 237: 1 test 238: 0 comment: ; ORGINAL BIT 4 (AC8) goes to LINE comment: ; (BIT 6) goes LO test 239: 1 0 0 test 240: 0 test 241: 1 test 242: 0 comment: ; ORGINAL BIT 5 (AC7) goes to LINE comment: ; test 243: 1 0 0 test 244: 0 test 245: 1 test 246: 0 comment: ; ORGINAL BIT 6 (AC6) goes to LINE test 247: 1 0 test 248: 0 test 249: 1 test 250: 0 comment: ; ORGINAL BIT 7 (AC5) goes to LINE test 251: 1 0 test 252: 0 test 253: 1 test 254: 0 comment: ; ORGINAL BIT 8 (AC4) goes to LINE test 255: 1 0 test 256: 0 test 257: 1 test 258: 0 comment: ; ORGINAL (ENABLE) goes to LINE (STOP BITS) comment: ; (ACTIVE) goes LO comment: ; P.I.REQ-N (FLAG-N) goes LO...FLAG is ON test 259: 1 0 01 test 260: 0 comment: ; STOP FFs bits start counting... test 261: 1 1 test 262: 0 test 263: 1 1 test 264: 0 test 265: 1 1 comment: ; since STOP 2-N went HI, set (STOP SELECT) (i.e. 2 STOP BITS) test 266: 1 test 267: 0 test 268: 1 test 269: 0 comment: ; comment: ; try the I/O SKIP comment: ; comment: ; turn on DEVICE ADDRESS bits test 270: 111111 comment: ; toggle I/O SKP.STROBE I/O SKP.-N pulses LO (active) test 271: 10 test 272: 01 comment: ; turn off DEVICE ADDRESS bits test 273: 000000 comment: ; toggle I/O SKP.STROBE- I/O SKP.-N stays HI (inactive) test 274: 1 test 275: 0 comment: ; turn on DEVICE ADDRESS bits test 276: 111111 comment: ; set I/O SKP. STROBE, I/O SKP.-N goes LO test 277: 10 comment: ; clear the FLAG- pulse CLEAR FLAG 1, I/O SKP.-n goes HI comment: ; P.I.REQ-N (FLAG-N) goes HI...FLAG is OFF test 278: 111 test 279: 0 comment: ; turn off I/O SKP. STROBE test 280: 0 comment: ; turn off DEVICE ADDRESS bits test 281: 000000 test 282: 11000000001011001111110001110101010101X1 comment: ; comment: ; comment: ; send a 0xFF comment: ; comment: ; comment: ; set up to load ENABLE/0xFF (all ones) test 283: 111111111 comment: ; turn on DEVICE ADDRESS bits test 284: 111111 comment: ; turn on LOAD BUFFER (normally IOP4) comment: ; LOAD BUFFER STROBE-N goes LO comment: ; (BIT 6) goes HI comment: ; (ENABLE) goes HI (note: next CLOCK starts TX...) comment: ; (ENABLE-N) goes LO test 285: 10 11 0 comment: ; (ENABLE) is HI, so set (CHARACTER LOADED) (normal 8 BIT TX) test 286: 1 comment: ; (ENABLE-N) is LO, so change (DECODE INPUT 8) (normally connects to (ENABLE-N) test 287: 0 comment: ; remove LOAD BUFFER (normally IOP4) test 288: 01 comment: ; remove DEVICE ADDRESS test 289: 000000 comment: ; comment: ; shift out the 0x00 character comment: ; comment: ; on first 2 X BAUD CLOCK INPUT comment: ; ACTIVE is SET, causes LINE to CLEAR (i.e. START BIT). comment: ; test 290: 1 10 test 291: 0 comment: ; the 2nd 2 X BAUD CLOCK INPUT causes the STOP FFs to PRESET test 292: 1 000 test 293: 0 comment: ; ORGINAL BIT 1 (AC11) goes to LINE comment: ; (BIT 6) shifts comment: ; (ENABLE) goes LO, (ENABLE-N) goes HI test 294: 1 10 1 1 comment: ; since (ENABLE) is LO, change (CHARACTER LOADED) (i.e. 8 not 5) test 295: 0 comment: ; since (ENABLE-N) is HI, change (DECODE INPUT 8) (normally connects to (ENABLE-N) test 296: 1 test 297: 0 test 298: 1 test 299: 0 comment: ; ORGINAL BIT 2 (AC10) goes to LINE test 300: 1 1 1 test 301: 0 test 302: 1 test 303: 0 comment: ; ORGINAL BIT 3 (AC9) goes to LINE comment: ; (BIT 6) becomes original ENABLE test 304: 1 1 1 test 305: 0 test 306: 1 test 307: 0 comment: ; ORGINAL BIT 4 (AC8) goes to LINE comment: ; (BIT 6) goes LO test 308: 1 0 1 test 309: 0 test 310: 1 test 311: 0 comment: ; ORGINAL BIT 5 (AC7) goes to LINE comment: ; test 312: 1 1 test 313: 0 test 314: 1 test 315: 0 comment: ; ORGINAL BIT 6 (AC6) goes to LINE test 316: 1 1 test 317: 0 test 318: 1 test 319: 0 comment: ; ORGINAL BIT 7 (AC5) goes to LINE test 320: 1 1 test 321: 0 test 322: 1 test 323: 0 comment: ; ORGINAL BIT 8 (AC4) goes to LINE test 324: 1 1 test 325: 0 test 326: 1 test 327: 0 comment: ; ORGINAL (ENABLE) goes to LINE (STOP BITS) comment: ; (ACTIVE) goes LO comment: ; P.I.REQ-N (FLAG-N) goes LO...FLAG is ON test 328: 1 0 01 test 329: 0 comment: ; STOP FFs bits start counting... test 330: 1 1 test 331: 0 test 332: 1 1 test 333: 0 test 334: 1 1 comment: ; since STOP 2-N went HI, set (STOP SELECT) (i.e. 2 STOP BITS) test 335: 1 test 336: 0 test 337: 1 test 338: 0 comment: ; comment: ; try the I/O SKIP comment: ; comment: ; turn on DEVICE ADDRESS bits test 339: 111111 comment: ; toggle I/O SKP.STROBE I/O SKP.-N pulses LO (active) test 340: 10 test 341: 01 comment: ; turn off DEVICE ADDRESS bits test 342: 000000 comment: ; toggle I/O SKP.STROBE- I/O SKP.-N stays HI (inactive) test 343: 11 test 344: 01 comment: ; turn on DEVICE ADDRESS bits test 345: 111111 comment: ; set I/O SKP. STROBE, I/O SKP.-N goes LO test 346: 10 comment: ; clear the FLAG- pulse CLEAR FLAG 1, I/O SKP.-n goes HI comment: ; P.I.REQ-N (FLAG-N) goes HI...FLAG is OFF test 347: 111 test 348: 0 comment: ; turn off I/O SKP. STROBE test 349: 0 comment: ; turn off DEVICE ADDRESS bits test 350: 000000 test 351: 11000000001011001111110001110101010101X1 comment: ; comment: ; test ECHO input (need to scope AV2 20MA OUTPUT) comment: ; comment: ; set ECHO-N lo, 20MA OUTPUT goes LO test 352: X0 test 353: X1 end: END summary column 1: offset 3, mask 0x4000 column 2: offset 2, mask 0x0080 column 3: offset 2, mask 0x0040 column 4: offset 3, mask 0x0040 column 5: offset 0, mask 0x0800 column 6: offset 0, mask 0x0008 column 7: offset 0, mask 0x0400 column 8: offset 0, mask 0x0004 column 9: offset 0, mask 0x0002 column 10: offset 0, mask 0x0001 column 11: offset 1, mask 0x1000 column 12: offset 3, mask 0x0001 column 13: offset 3, mask 0x0002 column 14: offset 3, mask 0x0004 column 15: offset 2, mask 0x0020 column 16: offset 1, mask 0x0200 column 17: offset 1, mask 0x0400 column 18: offset 4, mask 0x0001 column 19: offset 3, mask 0x0080 column 20: offset 3, mask 0x0200 column 21: offset 3, mask 0x0400 column 22: offset 3, mask 0x0020 column 23: offset 0, mask 0x0100 column 24: offset 1, mask 0x0001 column 25: offset 1, mask 0x8000 column 26: offset 1, mask 0x4000 column 27: offset 0, mask 0x0200 column 28: offset 1, mask 0x0008 column 29: offset 1, mask 0x0010 column 30: offset 1, mask 0x0020 column 31: offset 1, mask 0x0002 column 32: offset 1, mask 0x0004 column 33: offset 2, mask 0x0001 column 34: offset 1, mask 0x0040 column 35: offset 1, mask 0x0080 column 36: offset 2, mask 0x8000 column 37: offset 0, mask 0x1000 column 38: offset 0, mask 0x0010 column 39: offset 2, mask 0x0002 column 40: offset 0, mask 0x4000 direction bits (1=input) 0xB1F0 0x6901 0x7F1A 0xFF9E 0xF0FE pullup bits (1=pullup) 0x0000 0x0000 0x0000 0x0000 0x0000 test step out_data dont care 1: 0x4210 0x5408 0x00C0 0x4006 0x0001 0x0000 0x0000 0x0002 0x0680 0x0000 2: 0x4210 0x5408 0x0080 0x4006 0x0001 0x0000 0x0000 0x0002 0x0680 0x0000 3: 0x4210 0x5408 0x0080 0x40C6 0x0001 0x0000 0x0000 0x0002 0x0600 0x0000 4: 0x4210 0x5408 0x0080 0x4086 0x0001 0x0000 0x0000 0x0002 0x0600 0x0000 5: 0x4210 0x5408 0x0080 0x42C6 0x0001 0x0000 0x0000 0x0002 0x0400 0x0000 6: 0x4210 0x5408 0x0080 0x4286 0x0001 0x0000 0x0000 0x0002 0x0400 0x0000 7: 0x4210 0x5408 0x0080 0x46C6 0x0001 0x0000 0x0000 0x0002 0x0000 0x0000 8: 0x4210 0x5408 0x0080 0x4686 0x0001 0x0000 0x0000 0x0002 0x0000 0x0000 9: 0x4210 0x5408 0x0080 0x46A6 0x0001 0x0000 0x0000 0x0002 0x0000 0x0000 10: 0x4210 0x5608 0x0080 0x46A6 0x0001 0x0000 0x0000 0x0002 0x0000 0x0000 11: 0x4210 0x566C 0x8080 0x46A6 0x0001 0x0000 0x0000 0x0002 0x0000 0x0000 12: 0x4E1F 0x126D 0x8080 0x46A6 0x0001 0x0000 0x0000 0x0002 0x0000 0x0000 13: 0x4C1F 0x126D 0x8080 0x46A6 0x0001 0x0000 0x0000 0x0002 0x0000 0x0000 14: 0x4010 0x966D 0x8080 0x46A6 0x0001 0x0000 0x0000 0x0002 0x0000 0x0000 15: 0x4010 0x826D 0x8080 0x46A6 0x0001 0x0000 0x0000 0x0002 0x0000 0x0000 16: 0x4010 0x966D 0x8080 0x46A6 0x0001 0x0000 0x0000 0x0002 0x0000 0x0000 17: 0x4010 0x966D 0x8080 0x46A6 0x0001 0x0000 0x0000 0x0002 0x0000 0x0000 18: 0x4011 0x966D 0x8080 0x46A6 0x0001 0x0000 0x0000 0x0002 0x0000 0x0000 19: 0x4012 0x966D 0x8080 0x46A6 0x0001 0x0000 0x0000 0x0002 0x0000 0x0000 20: 0x4013 0x966D 0x8080 0x46A6 0x0001 0x0000 0x0000 0x0002 0x0000 0x0000 21: 0x4014 0x966D 0x8080 0x46A6 0x0001 0x0000 0x0000 0x0002 0x0000 0x0000 22: 0x4015 0x966D 0x8080 0x46A6 0x0001 0x0000 0x0000 0x0002 0x0000 0x0000 23: 0x4016 0x966D 0x8080 0x46A6 0x0001 0x0000 0x0000 0x0002 0x0000 0x0000 24: 0x4017 0x966D 0x8080 0x46A6 0x0001 0x0000 0x0000 0x0002 0x0000 0x0000 25: 0x4410 0x966D 0x8080 0x46A6 0x0001 0x0000 0x0000 0x0002 0x0000 0x0000 26: 0x4411 0x966D 0x8080 0x46A6 0x0001 0x0000 0x0000 0x0002 0x0000 0x0000 27: 0x4412 0x966D 0x8080 0x46A6 0x0001 0x0000 0x0000 0x0002 0x0000 0x0000 28: 0x4413 0x966D 0x8080 0x46A6 0x0001 0x0000 0x0000 0x0002 0x0000 0x0000 29: 0x4414 0x966D 0x8080 0x46A6 0x0001 0x0000 0x0000 0x0002 0x0000 0x0000 30: 0x4415 0x966D 0x8080 0x46A6 0x0001 0x0000 0x0000 0x0002 0x0000 0x0000 31: 0x4416 0x966D 0x8080 0x46A6 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0x0000 0x0000 0x0002 0x0000 0x0000 259: 0x4210 0x5408 0x0080 0x4062 0x0001 0x0000 0x0000 0x0002 0x0000 0x0000 260: 0x4210 0x5408 0x0080 0x4022 0x0001 0x0000 0x0000 0x0002 0x0000 0x0000 261: 0x4210 0x5408 0x0080 0x40E2 0x0001 0x0000 0x0000 0x0002 0x0000 0x0000 262: 0x4210 0x5408 0x0080 0x40A2 0x0001 0x0000 0x0000 0x0002 0x0000 0x0000 263: 0x4210 0x5408 0x0080 0x42E2 0x0001 0x0000 0x0000 0x0002 0x0000 0x0000 264: 0x4210 0x5408 0x0080 0x42A2 0x0001 0x0000 0x0000 0x0002 0x0000 0x0000 265: 0x4210 0x5408 0x0080 0x46E2 0x0001 0x0000 0x0000 0x0002 0x0000 0x0000 266: 0x4210 0x5408 0x0080 0x46E2 0x0001 0x0000 0x0000 0x0002 0x0000 0x0000 267: 0x4210 0x5408 0x0080 0x46A2 0x0001 0x0000 0x0000 0x0002 0x0000 0x0000 268: 0x4210 0x5408 0x0080 0x46E2 0x0001 0x0000 0x0000 0x0002 0x0000 0x0000 269: 0x4210 0x5408 0x0080 0x46A2 0x0001 0x0000 0x0000 0x0002 0x0000 0x0000 270: 0x4E1F 0x5408 0x0080 0x46A2 0x0001 0x0000 0x0000 0x0002 0x0000 0x0000 271: 0x4E1F 0x5408 0x0080 0x46A1 0x0001 0x0000 0x0000 0x0002 0x0000 0x0000 272: 0x4E1F 0x5408 0x0080 0x46A2 0x0001 0x0000 0x0000 0x0002 0x0000 0x0000 273: 0x4210 0x5408 0x0080 0x46A2 0x0001 0x0000 0x0000 0x0002 0x0000 0x0000 274: 0x4210 0x5408 0x0080 0x46A3 0x0001 0x0000 0x0000 0x0002 0x0000 0x0000 275: 0x4210 0x5408 0x0080 0x46A2 0x0001 0x0000 0x0000 0x0002 0x0000 0x0000 276: 0x4E1F 0x5408 0x0080 0x46A2 0x0001 0x0000 0x0000 0x0002 0x0000 0x0000 277: 0x4E1F 0x5408 0x0080 0x46A1 0x0001 0x0000 0x0000 0x0002 0x0000 0x0000 278: 0x4E1F 0x5408 0x00A0 0x46A7 0x0001 0x0000 0x0000 0x0002 0x0000 0x0000 279: 0x4E1F 0x5408 0x0080 0x46A7 0x0001 0x0000 0x0000 0x0002 0x0000 0x0000 280: 0x4E1F 0x5408 0x0080 0x46A6 0x0001 0x0000 0x0000 0x0002 0x0000 0x0000 281: 0x4210 0x5408 0x0080 0x46A6 0x0001 0x0000 0x0000 0x0002 0x0000 0x0000 282: 0x4210 0x546C 0x8080 0x46A6 0x0001 0x0000 0x0000 0x0002 0x0000 0x0000 283: 0x4210 0x54FE 0x8081 0x46A6 0x0001 0x0000 0x0000 0x0002 0x0000 0x0000 284: 0x4E1F 0x54FE 0x8081 0x46A6 0x0001 0x0000 0x0000 0x0002 0x0000 0x0000 285: 0x4F1F 0x12FF 0x8081 0x46A6 0x0001 0x0000 0x0000 0x0002 0x0000 0x0000 286: 0x4F1F 0x92FF 0x8081 0x46A6 0x0001 0x0000 0x0000 0x0002 0x0000 0x0000 287: 0x4D1F 0x92FF 0x8081 0x46A6 0x0001 0x0000 0x0000 0x0002 0x0000 0x0000 288: 0x4D1F 0x94FF 0x8081 0x46A6 0x0001 0x0000 0x0000 0x0002 0x0000 0x0000 289: 0x4110 0x94FF 0x8081 0x46A6 0x0001 0x0000 0x0000 0x0002 0x0000 0x0000 290: 0x5100 0x94FF 0x8081 0x46E6 0x0001 0x0000 0x0000 0x0002 0x0000 0x0000 291: 0x5100 0x94FF 0x8081 0x46A6 0x0001 0x0000 0x0000 0x0002 0x0000 0x0000 292: 0x5100 0x94FF 0x8081 0x4066 0x0001 0x0000 0x0000 0x0002 0x0000 0x0000 293: 0x5100 0x94FF 0x8081 0x4026 0x0001 0x0000 0x0000 0x0002 0x0000 0x0000 294: 0x5110 0xD4FE 0x8081 0x4066 0x0001 0x0000 0x0000 0x0002 0x0000 0x0000 295: 0x5110 0x54FE 0x8081 0x4066 0x0001 0x0000 0x0000 0x0002 0x0000 0x0000 296: 0x5310 0x54FE 0x8081 0x4066 0x0001 0x0000 0x0000 0x0002 0x0000 0x0000 297: 0x5310 0x54FE 0x8081 0x4026 0x0001 0x0000 0x0000 0x0002 0x0000 0x0000 298: 0x5310 0x54FE 0x8081 0x4066 0x0001 0x0000 0x0000 0x0002 0x0000 0x0000 299: 0x5310 0x54FE 0x8081 0x4026 0x0001 0x0000 0x0000 0x0002 0x0000 0x0000 300: 0x5310 0x54FE 0x8081 0x4066 0x0001 0x0000 0x0000 0x0002 0x0000 0x0000 301: 0x5310 0x54FE 0x8081 0x4026 0x0001 0x0000 0x0000 0x0002 0x0000 0x0000 302: 0x5310 0x54FE 0x8081 0x4066 0x0001 0x0000 0x0000 0x0002 0x0000 0x0000 303: 0x5310 0x54FE 0x8081 0x4026 0x0001 0x0000 0x0000 0x0002 0x0000 0x0000 304: 0x5310 0x54FE 0x8081 0x4066 0x0001 0x0000 0x0000 0x0002 0x0000 0x0000 305: 0x5310 0x54FE 0x8081 0x4026 0x0001 0x0000 0x0000 0x0002 0x0000 0x0000 306: 0x5310 0x54FE 0x8081 0x4066 0x0001 0x0000 0x0000 0x0002 0x0000 0x0000 307: 0x5310 0x54FE 0x8081 0x4026 0x0001 0x0000 0x0000 0x0002 0x0000 0x0000 308: 0x5210 0x54FE 0x8081 0x4066 0x0001 0x0000 0x0000 0x0002 0x0000 0x0000 309: 0x5210 0x54FE 0x8081 0x4026 0x0001 0x0000 0x0000 0x0002 0x0000 0x0000 310: 0x5210 0x54FE 0x8081 0x4066 0x0001 0x0000 0x0000 0x0002 0x0000 0x0000 311: 0x5210 0x54FE 0x8081 0x4026 0x0001 0x0000 0x0000 0x0002 0x0000 0x0000 312: 0x5210 0x54FE 0x8081 0x4066 0x0001 0x0000 0x0000 0x0002 0x0000 0x0000 313: 0x5210 0x54FE 0x8081 0x4026 0x0001 0x0000 0x0000 0x0002 0x0000 0x0000 314: 0x5210 0x54FE 0x8081 0x4066 0x0001 0x0000 0x0000 0x0002 0x0000 0x0000 315: 0x5210 0x54FE 0x8081 0x4026 0x0001 0x0000 0x0000 0x0002 0x0000 0x0000 316: 0x5210 0x54FE 0x8081 0x4066 0x0001 0x0000 0x0000 0x0002 0x0000 0x0000 317: 0x5210 0x54FE 0x8081 0x4026 0x0001 0x0000 0x0000 0x0002 0x0000 0x0000 318: 0x5210 0x54FE 0x8081 0x4066 0x0001 0x0000 0x0000 0x0002 0x0000 0x0000 319: 0x5210 0x54FE 0x8081 0x4026 0x0001 0x0000 0x0000 0x0002 0x0000 0x0000 320: 0x5210 0x54FE 0x8081 0x4066 0x0001 0x0000 0x0000 0x0002 0x0000 0x0000 321: 0x5210 0x54FE 0x8081 0x4026 0x0001 0x0000 0x0000 0x0002 0x0000 0x0000 322: 0x5210 0x54FE 0x8081 0x4066 0x0001 0x0000 0x0000 0x0002 0x0000 0x0000 323: 0x5210 0x54FE 0x8081 0x4026 0x0001 0x0000 0x0000 0x0002 0x0000 0x0000 324: 0x5210 0x54FE 0x8081 0x4066 0x0001 0x0000 0x0000 0x0002 0x0000 0x0000 325: 0x5210 0x54FE 0x8081 0x4026 0x0001 0x0000 0x0000 0x0002 0x0000 0x0000 326: 0x5210 0x54FE 0x8081 0x4066 0x0001 0x0000 0x0000 0x0002 0x0000 0x0000 327: 0x5210 0x54FE 0x8081 0x4026 0x0001 0x0000 0x0000 0x0002 0x0000 0x0000 328: 0x4210 0x54FE 0x8081 0x4062 0x0001 0x0000 0x0000 0x0002 0x0000 0x0000 329: 0x4210 0x54FE 0x8081 0x4022 0x0001 0x0000 0x0000 0x0002 0x0000 0x0000 330: 0x4210 0x54FE 0x8081 0x40E2 0x0001 0x0000 0x0000 0x0002 0x0000 0x0000 331: 0x4210 0x54FE 0x8081 0x40A2 0x0001 0x0000 0x0000 0x0002 0x0000 0x0000 332: 0x4210 0x54FE 0x8081 0x42E2 0x0001 0x0000 0x0000 0x0002 0x0000 0x0000 333: 0x4210 0x54FE 0x8081 0x42A2 0x0001 0x0000 0x0000 0x0002 0x0000 0x0000 334: 0x4210 0x54FE 0x8081 0x46E2 0x0001 0x0000 0x0000 0x0002 0x0000 0x0000 335: 0x4210 0x54FE 0x8081 0x46E2 0x0001 0x0000 0x0000 0x0002 0x0000 0x0000 336: 0x4210 0x54FE 0x8081 0x46A2 0x0001 0x0000 0x0000 0x0002 0x0000 0x0000 337: 0x4210 0x54FE 0x8081 0x46E2 0x0001 0x0000 0x0000 0x0002 0x0000 0x0000 338: 0x4210 0x54FE 0x8081 0x46A2 0x0001 0x0000 0x0000 0x0002 0x0000 0x0000 339: 0x4E1F 0x54FE 0x8081 0x46A2 0x0001 0x0000 0x0000 0x0002 0x0000 0x0000 340: 0x4E1F 0x54FE 0x8081 0x46A1 0x0001 0x0000 0x0000 0x0002 0x0000 0x0000 341: 0x4E1F 0x54FE 0x8081 0x46A2 0x0001 0x0000 0x0000 0x0002 0x0000 0x0000 342: 0x4210 0x54FE 0x8081 0x46A2 0x0001 0x0000 0x0000 0x0002 0x0000 0x0000 343: 0x4210 0x54FE 0x8081 0x46A3 0x0001 0x0000 0x0000 0x0002 0x0000 0x0000 344: 0x4210 0x54FE 0x8081 0x46A2 0x0001 0x0000 0x0000 0x0002 0x0000 0x0000 345: 0x4E1F 0x54FE 0x8081 0x46A2 0x0001 0x0000 0x0000 0x0002 0x0000 0x0000 346: 0x4E1F 0x54FE 0x8081 0x46A1 0x0001 0x0000 0x0000 0x0002 0x0000 0x0000 347: 0x4E1F 0x54FE 0x80A1 0x46A7 0x0001 0x0000 0x0000 0x0002 0x0000 0x0000 348: 0x4E1F 0x54FE 0x8081 0x46A7 0x0001 0x0000 0x0000 0x0002 0x0000 0x0000 349: 0x4E1F 0x54FE 0x8081 0x46A6 0x0001 0x0000 0x0000 0x0002 0x0000 0x0000 350: 0x4210 0x54FE 0x8081 0x46A6 0x0001 0x0000 0x0000 0x0002 0x0000 0x0000 351: 0x4210 0x546C 0x8080 0x46A6 0x0001 0x0000 0x0000 0x0002 0x0000 0x0000 352: 0x0210 0x546C 0x8080 0x46A6 0x0001 0x0000 0x0000 0x0002 0x0000 0x0000 353: 0x4210 0x546C 0x8080 0x46A6 0x0001 0x0000 0x0000 0x0002 0x0000 0x0000 PINs used (in edge connector order) (G=ground,P=power) SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBB LETTER ABCDEFHJKLMNPRSTUVABCDEFHJKLMNPRSTUVABCDEFHJKLMNPRSTUVABCDEFHJKLMNPRSTUV SIDE 111111111111111111222222222222222222111111111111111111222222222222222222 USAGE I OIIIOIO I IIGI P GOIIIIOIIIIIIIIO O OO G P GIIIIOO IIOI UUT inputs: 28 UUT outputs: 12 pins used: 40 not used: 26 353 'test steps' 643 lines M707 PCB REV D SCHEMATIC REV c TELETYPE TRANSMITTER ICs are VERTICAL on PCB REV D. Rev D adds AB1 ECHO input. does not test AV2 20MA OUTPUT, use scope and pulldown or use M707D_MA.TST to test 20MA OUTPUT (needs jumper) PINS Main menu Sun Jul 09 15:30:54 2017 test file is: tests\m707d.tst delay is: 0 trigger is: 1 1 read test file 2 set test delay 3 set test trigger 4 run test 5 output loading test 8 diags 9 exit UUT power is okay Sun Jul 09 15:30:56 2017 space single step O run once (one test, all steps) F run, stop on fail G go (run tests N run, stop on fail, no print S scope (run, no print) C turn on comment printout + increase speed (less delay) - decrease speed (more delay)(slower) Q quit test scope (run, no print) ppppppppppppppp space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn on comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT BBBBAAAAAAABBBBAABBBBBAAAAAAAAAAAAAAAAAA LETTER JFEPEEFFHJNHJKDSRSRPNNJKKLHNPRLMUSTUDDVB SIDE 1222121222122221122112121112222222211221 DIRECTION OIIIIIIIIIIIOOIIIIOOOIOOIOIIIIIIIIIIOOOI all fails was lo 000000000000000 000000000 0000000000 0 falling vvvvvvvvvvvvvvv vvvvvvvvv vvvvvvvvvv v rising ^^^^^^^^^^^^^^^ ^^^^^^^^^ ^^^^^^^^^^ ^ was hi 1111111111111111111111111111111111111111 total fails 0, total passes 15 Main menu Sun Jul 09 15:31:00 2017 test file is: tests\m707d.tst delay is: 0 trigger is: 1 1 read test file 2 set test delay 3 set test trigger 4 run test 5 output loading test 8 diags 9 exit exiting tester- PDP8 card tester via printer port version 0.91 November 27, 2015 mapping[] is verified Main menu Sun Jul 09 16:04:09 2017 test file is: delay is: 0 trigger is: 1 1 read test file 2 set test delay 3 set test trigger 4 run test 5 output loading test 8 diags 9 exit Enter test file name? trying to open test file: tests\m516.tst could not open test file. valid test files are: reverting back to test file: Main menu Sun Jul 09 16:04:16 2017 test file is: delay is: 0 trigger is: 1 1 read test file 2 set test delay 3 set test trigger 4 run test 5 output loading test 8 diags 9 exit there is no test file Main menu Sun Jul 09 16:04:41 2017 test file is: delay is: 0 trigger is: 1 1 read test file 2 set test delay 3 set test trigger 4 run test 5 output loading test 8 diags 9 exit key is 0x0073 Main menu Sun Jul 09 16:04:41 2017 test file is: delay is: 0 trigger is: 1 1 read test file 2 set test delay 3 set test trigger 4 run test 5 output loading test 8 diags 9 exit there is no test file Main menu Sun Jul 09 16:04:45 2017 test file is: delay is: 0 trigger is: 1 1 read test file 2 set test delay 3 set test trigger 4 run test 5 output loading test 8 diags 9 exit Enter test file name? trying to open test file: tests\m516.tst could not open test file. valid test files are: reverting back to test file: Main menu Sun Jul 09 16:04:50 2017 test file is: delay is: 0 trigger is: 1 1 read test file 2 set test delay 3 set test trigger 4 run test 5 output loading test 8 diags 9 exit Enter test file name? trying to open test file: tests\m516.tst reading test file: tests\m516.tst comment: M516 POSITIVE BUS RECEIVER (6 4-input NAND) (3 7420) PCB REV A SCHEMATIC REV (blank) comment: pins: PINS pins: 1 I AA1 E1-2 INPUT 1A pins: 2 I AB1 E1-1 INPUT 1B pins: 3 I AC1 E1-4 INPUT 1C pins: 4 I AD1 E1-5 INPUT 1D pins: 5 O AE1 E1-6 OUTPUT 1 = (1A NAND 1B NAND 1C NAND 1D) pins: 6 I AD2 E1-13 INPUT 2A pins: 7 I AE2 E1-12 INPUT 2B pins: 8 I AF2 E1-10 INPUT 2C pins: 9 I AH2 E1-9 INPUT 2D pins: 10 O AJ2 E1-8 OUTPUT 2 = (2A NAND 2B NAND 2C NAND 2D) pins: 11 I AF1 E2-2 INPUT 3A pins: 12 I AH1 E2-1 INPUT 3B pins: 13 I AJ1 E2-4 INPUT 3C pins: 14 I AK1 E2-5 INPUT 3D pins: 15 O AL1 E2-6 OUTPUT 3 = (3A NAND 3B NAND 3C NAND 3D) pins: 16 I AK2 E2-13 INPUT 4A pins: 17 I AL2 E2-12 INPUT 4B pins: 18 I AM2 E2-10 INPUT 4C pins: 19 I AN2 E2-9 INPUT 4D pins: 20 O AP2 E2-8 OUTPUT 4 = (4A NAND 4B NAND 4C NAND 4D) pins: 21 I AM1 E3-1 INPUT 5A pins: 22 I AN1 E3-2 INPUT 5B pins: 23 I AP1 E3-4 INPUT 5C pins: 24 I AR1 E3-5 INPUT 5D pins: 25 O AS1 E3-6 OUTPUT 5 = (5A NAND 5B NAND 5C NAND 5D) pins: 26 I AR2 E3-13 INPUT 6A pins: 27 I AS2 E3-12 INPUT 6B pins: 28 I AT2 E3-10 INPUT 6C pins: 29 I AU2 E3-9 INPUT 6D pins: 30 O AV2 E3-8 OUTPUT 6 = (6A NAND 6B NAND 6C NAND 6D) pins: direction: IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO test 1: 000010000100001000010000100001 test 2: 00001 test 3: 00011 test 4: 00101 test 5: 00111 test 6: 01001 test 7: 01011 test 8: 01101 test 9: 01111 test 10: 10001 test 11: 10011 test 12: 10101 test 13: 10111 test 14: 11001 test 15: 11011 test 16: 11101 test 17: 11110 test 18: 00001 test 19: 00001 test 20: 00011 test 21: 00101 test 22: 00111 test 23: 01001 test 24: 01011 test 25: 01101 test 26: 01111 test 27: 10001 test 28: 10011 test 29: 10101 test 30: 10111 test 31: 11001 test 32: 11011 test 33: 11101 test 34: 11110 test 35: 00001 test 36: 00001 test 37: 00011 test 38: 00101 test 39: 00111 test 40: 01001 test 41: 01011 test 42: 01101 test 43: 01111 test 44: 10001 test 45: 10011 test 46: 10101 test 47: 10111 test 48: 11001 test 49: 11011 test 50: 11101 test 51: 11110 test 52: 00001 test 53: 00001 test 54: 00011 test 55: 00101 test 56: 00111 test 57: 01001 test 58: 01011 test 59: 01101 test 60: 01111 test 61: 10001 test 62: 10011 test 63: 10101 test 64: 10111 test 65: 11001 test 66: 11011 test 67: 11101 test 68: 11110 test 69: 00001 test 70: 00001 test 71: 00011 test 72: 00101 test 73: 00111 test 74: 01001 test 75: 01011 test 76: 01101 test 77: 01111 test 78: 10001 test 79: 10011 test 80: 10101 test 81: 10111 test 82: 11001 test 83: 11011 test 84: 11101 test 85: 11110 test 86: 00001 test 87: 00001 test 88: 00011 test 89: 00101 test 90: 00111 test 91: 01001 test 92: 01011 test 93: 01101 test 94: 01111 test 95: 10001 test 96: 10011 test 97: 10101 test 98: 10111 test 99: 11001 test 100: 11011 test 101: 11101 test 102: 11110 test 103: 00001 test 104: 000010000100001000010000100001 test 105: 111101111011110111101111011110 test 106: 00001 test 107: 00011 test 108: 00101 test 109: 00111 test 110: 01001 test 111: 01011 test 112: 01101 test 113: 01111 test 114: 10001 test 115: 10011 test 116: 10101 test 117: 10111 test 118: 11001 test 119: 11011 test 120: 11101 test 121: 11110 test 122: 00001 test 123: 00011 test 124: 00101 test 125: 00111 test 126: 01001 test 127: 01011 test 128: 01101 test 129: 01111 test 130: 10001 test 131: 10011 test 132: 10101 test 133: 10111 test 134: 11001 test 135: 11011 test 136: 11101 test 137: 11110 test 138: 00001 test 139: 00011 test 140: 00101 test 141: 00111 test 142: 01001 test 143: 01011 test 144: 01101 test 145: 01111 test 146: 10001 test 147: 10011 test 148: 10101 test 149: 10111 test 150: 11001 test 151: 11011 test 152: 11101 test 153: 11110 test 154: 00001 test 155: 00011 test 156: 00101 test 157: 00111 test 158: 01001 test 159: 01011 test 160: 01101 test 161: 01111 test 162: 10001 test 163: 10011 test 164: 10101 test 165: 10111 test 166: 11001 test 167: 11011 test 168: 11101 test 169: 11110 test 170: 00001 test 171: 00011 test 172: 00101 test 173: 00111 test 174: 01001 test 175: 01011 test 176: 01101 test 177: 01111 test 178: 10001 test 179: 10011 test 180: 10101 test 181: 10111 test 182: 11001 test 183: 11011 test 184: 11101 test 185: 11110 test 186: 00001 test 187: 00011 test 188: 00101 test 189: 00111 test 190: 01001 test 191: 01011 test 192: 01101 test 193: 01111 test 194: 10001 test 195: 10011 test 196: 10101 test 197: 10111 test 198: 11001 test 199: 11011 test 200: 11101 test 201: 11110 test 202: 111101111011110111101111011110 end: END summary column 1: offset 0, mask 0x8000 column 2: offset 0, mask 0x4000 column 3: offset 0, mask 0x2000 column 4: offset 0, mask 0x1000 column 5: offset 0, mask 0x0800 column 6: offset 0, mask 0x0010 column 7: offset 0, mask 0x0008 column 8: offset 0, mask 0x0004 column 9: offset 0, mask 0x0002 column 10: offset 0, mask 0x0001 column 11: offset 0, mask 0x0400 column 12: offset 0, mask 0x0200 column 13: offset 0, mask 0x0100 column 14: offset 1, mask 0x8000 column 15: offset 1, mask 0x4000 column 16: offset 1, mask 0x0001 column 17: offset 1, mask 0x0002 column 18: offset 1, mask 0x0004 column 19: offset 1, mask 0x0008 column 20: offset 1, mask 0x0010 column 21: offset 1, mask 0x2000 column 22: offset 1, mask 0x1000 column 23: offset 1, mask 0x0800 column 24: offset 1, mask 0x0400 column 25: offset 1, mask 0x0200 column 26: offset 1, mask 0x0020 column 27: offset 1, mask 0x0040 column 28: offset 1, mask 0x0080 column 29: offset 2, mask 0x0001 column 30: offset 2, mask 0x0002 direction bits (1=input) 0x08E1 0x4310 0xFFFA 0xFFFF 0xF0FF pullup bits (1=pullup) 0x0000 0x0000 0x0000 0x0000 0x0000 test step out_data dont care 1: 0x0801 0x4210 0x0002 0x0000 0x0000 2: 0x0801 0x4210 0x0002 0x0000 0x0000 3: 0x1801 0x4210 0x0002 0x0000 0x0000 4: 0x2801 0x4210 0x0002 0x0000 0x0000 5: 0x3801 0x4210 0x0002 0x0000 0x0000 6: 0x4801 0x4210 0x0002 0x0000 0x0000 7: 0x5801 0x4210 0x0002 0x0000 0x0000 8: 0x6801 0x4210 0x0002 0x0000 0x0000 9: 0x7801 0x4210 0x0002 0x0000 0x0000 10: 0x8801 0x4210 0x0002 0x0000 0x0000 11: 0x9801 0x4210 0x0002 0x0000 0x0000 12: 0xA801 0x4210 0x0002 0x0000 0x0000 13: 0xB801 0x4210 0x0002 0x0000 0x0000 14: 0xC801 0x4210 0x0002 0x0000 0x0000 15: 0xD801 0x4210 0x0002 0x0000 0x0000 16: 0xE801 0x4210 0x0002 0x0000 0x0000 17: 0xF001 0x4210 0x0002 0x0000 0x0000 18: 0x0801 0x4210 0x0002 0x0000 0x0000 19: 0x0801 0x4210 0x0002 0x0000 0x0000 20: 0x0803 0x4210 0x0002 0x0000 0x0000 21: 0x0805 0x4210 0x0002 0x0000 0x0000 22: 0x0807 0x4210 0x0002 0x0000 0x0000 23: 0x0809 0x4210 0x0002 0x0000 0x0000 24: 0x080B 0x4210 0x0002 0x0000 0x0000 25: 0x080D 0x4210 0x0002 0x0000 0x0000 26: 0x080F 0x4210 0x0002 0x0000 0x0000 27: 0x0811 0x4210 0x0002 0x0000 0x0000 28: 0x0813 0x4210 0x0002 0x0000 0x0000 29: 0x0815 0x4210 0x0002 0x0000 0x0000 30: 0x0817 0x4210 0x0002 0x0000 0x0000 31: 0x0819 0x4210 0x0002 0x0000 0x0000 32: 0x081B 0x4210 0x0002 0x0000 0x0000 33: 0x081D 0x4210 0x0002 0x0000 0x0000 34: 0x081E 0x4210 0x0002 0x0000 0x0000 35: 0x0801 0x4210 0x0002 0x0000 0x0000 36: 0x0801 0x4210 0x0002 0x0000 0x0000 37: 0x0801 0xC210 0x0002 0x0000 0x0000 38: 0x0901 0x4210 0x0002 0x0000 0x0000 39: 0x0901 0xC210 0x0002 0x0000 0x0000 40: 0x0A01 0x4210 0x0002 0x0000 0x0000 41: 0x0A01 0xC210 0x0002 0x0000 0x0000 42: 0x0B01 0x4210 0x0002 0x0000 0x0000 43: 0x0B01 0xC210 0x0002 0x0000 0x0000 44: 0x0C01 0x4210 0x0002 0x0000 0x0000 45: 0x0C01 0xC210 0x0002 0x0000 0x0000 46: 0x0D01 0x4210 0x0002 0x0000 0x0000 47: 0x0D01 0xC210 0x0002 0x0000 0x0000 48: 0x0E01 0x4210 0x0002 0x0000 0x0000 49: 0x0E01 0xC210 0x0002 0x0000 0x0000 50: 0x0F01 0x4210 0x0002 0x0000 0x0000 51: 0x0F01 0x8210 0x0002 0x0000 0x0000 52: 0x0801 0x4210 0x0002 0x0000 0x0000 53: 0x0801 0x4210 0x0002 0x0000 0x0000 54: 0x0801 0x4218 0x0002 0x0000 0x0000 55: 0x0801 0x4214 0x0002 0x0000 0x0000 56: 0x0801 0x421C 0x0002 0x0000 0x0000 57: 0x0801 0x4212 0x0002 0x0000 0x0000 58: 0x0801 0x421A 0x0002 0x0000 0x0000 59: 0x0801 0x4216 0x0002 0x0000 0x0000 60: 0x0801 0x421E 0x0002 0x0000 0x0000 61: 0x0801 0x4211 0x0002 0x0000 0x0000 62: 0x0801 0x4219 0x0002 0x0000 0x0000 63: 0x0801 0x4215 0x0002 0x0000 0x0000 64: 0x0801 0x421D 0x0002 0x0000 0x0000 65: 0x0801 0x4213 0x0002 0x0000 0x0000 66: 0x0801 0x421B 0x0002 0x0000 0x0000 67: 0x0801 0x4217 0x0002 0x0000 0x0000 68: 0x0801 0x420F 0x0002 0x0000 0x0000 69: 0x0801 0x4210 0x0002 0x0000 0x0000 70: 0x0801 0x4210 0x0002 0x0000 0x0000 71: 0x0801 0x4610 0x0002 0x0000 0x0000 72: 0x0801 0x4A10 0x0002 0x0000 0x0000 73: 0x0801 0x4E10 0x0002 0x0000 0x0000 74: 0x0801 0x5210 0x0002 0x0000 0x0000 75: 0x0801 0x5610 0x0002 0x0000 0x0000 76: 0x0801 0x5A10 0x0002 0x0000 0x0000 77: 0x0801 0x5E10 0x0002 0x0000 0x0000 78: 0x0801 0x6210 0x0002 0x0000 0x0000 79: 0x0801 0x6610 0x0002 0x0000 0x0000 80: 0x0801 0x6A10 0x0002 0x0000 0x0000 81: 0x0801 0x6E10 0x0002 0x0000 0x0000 82: 0x0801 0x7210 0x0002 0x0000 0x0000 83: 0x0801 0x7610 0x0002 0x0000 0x0000 84: 0x0801 0x7A10 0x0002 0x0000 0x0000 85: 0x0801 0x7C10 0x0002 0x0000 0x0000 86: 0x0801 0x4210 0x0002 0x0000 0x0000 87: 0x0801 0x4210 0x0002 0x0000 0x0000 88: 0x0801 0x4210 0x0003 0x0000 0x0000 89: 0x0801 0x4290 0x0002 0x0000 0x0000 90: 0x0801 0x4290 0x0003 0x0000 0x0000 91: 0x0801 0x4250 0x0002 0x0000 0x0000 92: 0x0801 0x4250 0x0003 0x0000 0x0000 93: 0x0801 0x42D0 0x0002 0x0000 0x0000 94: 0x0801 0x42D0 0x0003 0x0000 0x0000 95: 0x0801 0x4230 0x0002 0x0000 0x0000 96: 0x0801 0x4230 0x0003 0x0000 0x0000 97: 0x0801 0x42B0 0x0002 0x0000 0x0000 98: 0x0801 0x42B0 0x0003 0x0000 0x0000 99: 0x0801 0x4270 0x0002 0x0000 0x0000 100: 0x0801 0x4270 0x0003 0x0000 0x0000 101: 0x0801 0x42F0 0x0002 0x0000 0x0000 102: 0x0801 0x42F0 0x0001 0x0000 0x0000 103: 0x0801 0x4210 0x0002 0x0000 0x0000 104: 0x0801 0x4210 0x0002 0x0000 0x0000 105: 0xF71E 0xBCEF 0x0001 0x0000 0x0000 106: 0x0F1E 0xBCEF 0x0001 0x0000 0x0000 107: 0x1F1E 0xBCEF 0x0001 0x0000 0x0000 108: 0x2F1E 0xBCEF 0x0001 0x0000 0x0000 109: 0x3F1E 0xBCEF 0x0001 0x0000 0x0000 110: 0x4F1E 0xBCEF 0x0001 0x0000 0x0000 111: 0x5F1E 0xBCEF 0x0001 0x0000 0x0000 112: 0x6F1E 0xBCEF 0x0001 0x0000 0x0000 113: 0x7F1E 0xBCEF 0x0001 0x0000 0x0000 114: 0x8F1E 0xBCEF 0x0001 0x0000 0x0000 115: 0x9F1E 0xBCEF 0x0001 0x0000 0x0000 116: 0xAF1E 0xBCEF 0x0001 0x0000 0x0000 117: 0xBF1E 0xBCEF 0x0001 0x0000 0x0000 118: 0xCF1E 0xBCEF 0x0001 0x0000 0x0000 119: 0xDF1E 0xBCEF 0x0001 0x0000 0x0000 120: 0xEF1E 0xBCEF 0x0001 0x0000 0x0000 121: 0xF71E 0xBCEF 0x0001 0x0000 0x0000 122: 0xF701 0xBCEF 0x0001 0x0000 0x0000 123: 0xF703 0xBCEF 0x0001 0x0000 0x0000 124: 0xF705 0xBCEF 0x0001 0x0000 0x0000 125: 0xF707 0xBCEF 0x0001 0x0000 0x0000 126: 0xF709 0xBCEF 0x0001 0x0000 0x0000 127: 0xF70B 0xBCEF 0x0001 0x0000 0x0000 128: 0xF70D 0xBCEF 0x0001 0x0000 0x0000 129: 0xF70F 0xBCEF 0x0001 0x0000 0x0000 130: 0xF711 0xBCEF 0x0001 0x0000 0x0000 131: 0xF713 0xBCEF 0x0001 0x0000 0x0000 132: 0xF715 0xBCEF 0x0001 0x0000 0x0000 133: 0xF717 0xBCEF 0x0001 0x0000 0x0000 134: 0xF719 0xBCEF 0x0001 0x0000 0x0000 135: 0xF71B 0xBCEF 0x0001 0x0000 0x0000 136: 0xF71D 0xBCEF 0x0001 0x0000 0x0000 137: 0xF71E 0xBCEF 0x0001 0x0000 0x0000 138: 0xF01E 0x7CEF 0x0001 0x0000 0x0000 139: 0xF01E 0xFCEF 0x0001 0x0000 0x0000 140: 0xF11E 0x7CEF 0x0001 0x0000 0x0000 141: 0xF11E 0xFCEF 0x0001 0x0000 0x0000 142: 0xF21E 0x7CEF 0x0001 0x0000 0x0000 143: 0xF21E 0xFCEF 0x0001 0x0000 0x0000 144: 0xF31E 0x7CEF 0x0001 0x0000 0x0000 145: 0xF31E 0xFCEF 0x0001 0x0000 0x0000 146: 0xF41E 0x7CEF 0x0001 0x0000 0x0000 147: 0xF41E 0xFCEF 0x0001 0x0000 0x0000 148: 0xF51E 0x7CEF 0x0001 0x0000 0x0000 149: 0xF51E 0xFCEF 0x0001 0x0000 0x0000 150: 0xF61E 0x7CEF 0x0001 0x0000 0x0000 151: 0xF61E 0xFCEF 0x0001 0x0000 0x0000 152: 0xF71E 0x7CEF 0x0001 0x0000 0x0000 153: 0xF71E 0xBCEF 0x0001 0x0000 0x0000 154: 0xF71E 0xBCF0 0x0001 0x0000 0x0000 155: 0xF71E 0xBCF8 0x0001 0x0000 0x0000 156: 0xF71E 0xBCF4 0x0001 0x0000 0x0000 157: 0xF71E 0xBCFC 0x0001 0x0000 0x0000 158: 0xF71E 0xBCF2 0x0001 0x0000 0x0000 159: 0xF71E 0xBCFA 0x0001 0x0000 0x0000 160: 0xF71E 0xBCF6 0x0001 0x0000 0x0000 161: 0xF71E 0xBCFE 0x0001 0x0000 0x0000 162: 0xF71E 0xBCF1 0x0001 0x0000 0x0000 163: 0xF71E 0xBCF9 0x0001 0x0000 0x0000 164: 0xF71E 0xBCF5 0x0001 0x0000 0x0000 165: 0xF71E 0xBCFD 0x0001 0x0000 0x0000 166: 0xF71E 0xBCF3 0x0001 0x0000 0x0000 167: 0xF71E 0xBCFB 0x0001 0x0000 0x0000 168: 0xF71E 0xBCF7 0x0001 0x0000 0x0000 169: 0xF71E 0xBCEF 0x0001 0x0000 0x0000 170: 0xF71E 0x82EF 0x0001 0x0000 0x0000 171: 0xF71E 0x86EF 0x0001 0x0000 0x0000 172: 0xF71E 0x8AEF 0x0001 0x0000 0x0000 173: 0xF71E 0x8EEF 0x0001 0x0000 0x0000 174: 0xF71E 0x92EF 0x0001 0x0000 0x0000 175: 0xF71E 0x96EF 0x0001 0x0000 0x0000 176: 0xF71E 0x9AEF 0x0001 0x0000 0x0000 177: 0xF71E 0x9EEF 0x0001 0x0000 0x0000 178: 0xF71E 0xA2EF 0x0001 0x0000 0x0000 179: 0xF71E 0xA6EF 0x0001 0x0000 0x0000 180: 0xF71E 0xAAEF 0x0001 0x0000 0x0000 181: 0xF71E 0xAEEF 0x0001 0x0000 0x0000 182: 0xF71E 0xB2EF 0x0001 0x0000 0x0000 183: 0xF71E 0xB6EF 0x0001 0x0000 0x0000 184: 0xF71E 0xBAEF 0x0001 0x0000 0x0000 185: 0xF71E 0xBCEF 0x0001 0x0000 0x0000 186: 0xF71E 0xBC0F 0x0002 0x0000 0x0000 187: 0xF71E 0xBC0F 0x0003 0x0000 0x0000 188: 0xF71E 0xBC8F 0x0002 0x0000 0x0000 189: 0xF71E 0xBC8F 0x0003 0x0000 0x0000 190: 0xF71E 0xBC4F 0x0002 0x0000 0x0000 191: 0xF71E 0xBC4F 0x0003 0x0000 0x0000 192: 0xF71E 0xBCCF 0x0002 0x0000 0x0000 193: 0xF71E 0xBCCF 0x0003 0x0000 0x0000 194: 0xF71E 0xBC2F 0x0002 0x0000 0x0000 195: 0xF71E 0xBC2F 0x0003 0x0000 0x0000 196: 0xF71E 0xBCAF 0x0002 0x0000 0x0000 197: 0xF71E 0xBCAF 0x0003 0x0000 0x0000 198: 0xF71E 0xBC6F 0x0002 0x0000 0x0000 199: 0xF71E 0xBC6F 0x0003 0x0000 0x0000 200: 0xF71E 0xBCEF 0x0002 0x0000 0x0000 201: 0xF71E 0xBCEF 0x0001 0x0000 0x0000 202: 0xF71E 0xBCEF 0x0001 0x0000 0x0000 PINs used (in edge connector order) (G=ground,P=power) SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBB LETTER ABCDEFHJKLMNPRSTUVABCDEFHJKLMNPRSTUVABCDEFHJKLMNPRSTUVABCDEFHJKLMNPRSTUV SIDE 111111111111111111222222222222222222111111111111111111222222222222222222 USAGE IIIIOIIIIOIIIIOG P GIIIIOIIIIOIIIIO G P G UUT inputs: 24 UUT outputs: 6 pins used: 30 not used: 36 202 'test steps' 238 lines M516 POSITIVE BUS RECEIVER (6 4-input NAND) (3 7420) PCB REV A SCHEMATIC REV (blank) PINS Main menu Sun Jul 09 16:55:36 2017 test file is: tests\m516.tst delay is: 0 trigger is: 1 1 read test file 2 set test delay 3 set test trigger 4 run test 5 output loading test 8 diags 9 exit UUT power is okay Sun Jul 09 16:55:42 2017 space single step O run once (one test, all steps) F run, stop on fail G go (run tests N run, stop on fail, no print S scope (run, no print) C turn on comment printout + increase speed (less delay) - decrease speed (more delay)(slower) Q quit test scope (run, no print) ppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppp space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn on comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEDEFHJFHJKLKLMNPMNPRSRSTUV SIDE 111112222211111222221111122222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO all fails was lo 000000000000000000000000000000 falling vvvvvvvvvvvvvvvvvvvvvvvvvvvvvv rising ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ was hi 111111111111111111111111111111 total fails 0, total passes 75 Main menu Sun Jul 09 16:55:51 2017 test file is: tests\m516.tst delay is: 0 trigger is: 1 1 read test file 2 set test delay 3 set test trigger 4 run test 5 output loading test 8 diags 9 exit UUT power is okay Sun Jul 09 16:58:31 2017 space single step O run once (one test, all steps) F run, stop on fail G go (run tests N run, stop on fail, no print S scope (run, no print) C turn on comment printout + increase speed (less delay) - decrease speed (more delay)(slower) Q quit test scope (run, no print) ppppppppppppppp space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn on comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEDEFHJFHJKLKLMNPMNPRSRSTUV SIDE 111112222211111222221111122222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO all fails was lo 000000000000000000000000000000 falling vvvvvvvvvvvvvvvvvvvvvvvvvvvvvv rising ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ was hi 111111111111111111111111111111 total fails 0, total passes 15 Main menu Sun Jul 09 16:58:34 2017 test file is: tests\m516.tst delay is: 0 trigger is: 1 1 read test file 2 set test delay 3 set test trigger 4 run test 5 output loading test 8 diags 9 exit UUT power is okay Sun Jul 09 16:59:22 2017 space single step O run once (one test, all steps) F run, stop on fail G go (run tests N run, stop on fail, no print S scope (run, no print) C turn on comment printout + increase speed (less delay) - decrease speed (more delay)(slower) Q quit test scope (run, no print) ppppppppppppp space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn on comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEDEFHJFHJKLKLMNPMNPRSRSTUV SIDE 111112222211111222221111122222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO all fails was lo 000000000000000000000000000000 falling vvvvvvvvvvvvvvvvvvvvvvvvvvvvvv rising ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ was hi 111111111111111111111111111111 total fails 0, total passes 13 Main menu Sun Jul 09 16:59:24 2017 test file is: tests\m516.tst delay is: 0 trigger is: 1 1 read test file 2 set test delay 3 set test trigger 4 run test 5 output loading test 8 diags 9 exit Enter test file name? trying to open test file: tests\m216.tst reading test file: tests\m216.tst comment: M216 6 FLIP FLOPS comment: pins: PINS pins: 1 I AA1 E1-1 CLEAR-N E1-5/6 E1-8/9 E2-5/6 pins: 2 I AB1 E1-3 CLOCK E1-5/6 pins: 3 I AC1 E1-2 DATA E1-5/6 pins: 4 I AD1 E1-4 SET-N E1-5/6 pins: 5 O AE1 E1-5 Q E1-5/6 pins: 6 O AF1 E1-5 Q-N E1-5/6 pins: 7 I AD2 E1-11 CLOCK E1-8/9 pins: 8 I AE2 E1-12 DATA E1-8/9 pins: 9 I AF2 E1-10 SET-N E1-8/9 pins: 10 O AH2 E1-9 Q E1-8/9 pins: 11 O AJ2 E1-8 Q-N E1-8/9 pins: 12 I AH1 E2-3 CLOCK E2-5/6 pins: 13 I AJ1 E2-2 DATA E2-5/6 pins: 14 I AK1 E2-4 SET-N E2-5/6 pins: 15 O AL1 E2-5 Q E2-5/6 pins: 16 O AM1 E2-6 Q-N E2-5/6 pins: 17 I AK2 E3-13 CLEAR-N E3-8/9 E3-5/6 E2-8/9 pins: 18 I AL2 E3-11 CLOCK E3-8/9 pins: 19 I AM2 E3-12 DATA E3-8/9 pins: 20 I AN2 E3-10 SET-N E3-8/9 pins: 21 O AP2 E3-9 Q E3-8/9 pins: 22 O AR2 E3-8 Q-N E3-8/9 pins: 23 I AN1 E3-3 CLOCK E3-5/6 pins: 24 I AP1 E3-2 DATA E3-5/6 pins: 25 I AR1 E3-4 SET-N E3-5/6 pins: 26 O AS1 E3-5 Q E3-5/6 pins: 27 O AU1 E3-6 Q-N E3-5/6 pins: 28 I AS2 E2-11 CLOCK E2-8/9 pins: 29 I AT2 E2-12 DATA E2-8/9 pins: 30 I AU2 E2-10 SET-N E2-8/9 pins: 31 O AV2 E2-9 Q E2-8/9 pins: 32 O AV1 E2-8 Q-N E2-8/9 pins: direction: IIIIOOIIIOOIIIOOIIIIOOIIIOOIIIOO test 1: 00001100011000110000110001100011 test 2: 100010 10 10 test 3: 100110 test 4: 110101 test 5: 111101 test 6: 101101 test 7: 111110 test 8: 110110 test 9: 100110 test 10: 000101 11 11 test 11: 100101 10 10 test 12: 100010 test 13: 00001100011000110000110001100011 test 14: 1 1000010 10 test 15: 1 00110 test 16: 1 10101 test 17: 1 11101 test 18: 1 01101 test 19: 1 11110 test 20: 1 10110 test 21: 1 00110 test 22: 0 1100101 11 test 23: 1 1000101 10 test 24: 1 00010 test 25: 00001100011000110000110001100011 test 26: 1 10 1000010 test 27: 1 00110 test 28: 1 10101 test 29: 1 11101 test 30: 1 01101 test 31: 1 11110 test 32: 1 10110 test 33: 1 00110 test 34: 0 11 1100101 test 35: 1 10 1000101 test 36: 1 00010 test 37: 00001100011000110000110001100011 test 38: 100010 10 10 test 39: 100110 test 40: 110101 test 41: 111101 test 42: 101101 test 43: 111110 test 44: 110110 test 45: 100110 test 46: 000101 11 11 test 47: 100101 10 10 test 48: 100010 test 49: 00001100011000110000110001100011 test 50: 1 1000010 10 test 51: 1 00110 test 52: 1 10101 test 53: 1 11101 test 54: 1 01101 test 55: 1 11110 test 56: 1 10110 test 57: 1 00110 test 58: 0 1100101 11 test 59: 1 1000101 10 test 60: 1 00010 test 61: 00001100011000110000110001100011 test 62: 1 10 1000010 test 63: 1 00110 test 64: 1 10101 test 65: 1 11101 test 66: 1 01101 test 67: 1 11110 test 68: 1 10110 test 69: 1 00110 test 70: 0 11 1100101 test 71: 1 10 1000101 test 72: 1 00010 test 73: 00001100011000110000110001100011 end: END summary column 1: offset 0, mask 0x8000 column 2: offset 0, mask 0x4000 column 3: offset 0, mask 0x2000 column 4: offset 0, mask 0x1000 column 5: offset 0, mask 0x0800 column 6: offset 0, mask 0x0400 column 7: offset 0, mask 0x0010 column 8: offset 0, mask 0x0008 column 9: offset 0, mask 0x0004 column 10: offset 0, mask 0x0002 column 11: offset 0, mask 0x0001 column 12: offset 0, mask 0x0200 column 13: offset 0, mask 0x0100 column 14: offset 1, mask 0x8000 column 15: offset 1, mask 0x4000 column 16: offset 1, mask 0x2000 column 17: offset 1, mask 0x0001 column 18: offset 1, mask 0x0002 column 19: offset 1, mask 0x0004 column 20: offset 1, mask 0x0008 column 21: offset 1, mask 0x0010 column 22: offset 1, mask 0x0020 column 23: offset 1, mask 0x1000 column 24: offset 1, mask 0x0800 column 25: offset 1, mask 0x0400 column 26: offset 1, mask 0x0200 column 27: offset 2, mask 0x8000 column 28: offset 1, mask 0x0040 column 29: offset 1, mask 0x0080 column 30: offset 2, mask 0x0001 column 31: offset 2, mask 0x0002 column 32: offset 2, mask 0x4000 direction bits (1=input) 0x0CE3 0x6330 0xFFFA 0xFFFF 0xF0FF pullup bits (1=pullup) 0x0000 0x0000 0x0000 0x0000 0x0000 test step out_data dont care 1: 0x0C03 0x6230 0xC002 0x0000 0x0000 2: 0x8802 0x4230 0xC002 0x0000 0x0000 3: 0x9802 0x4230 0xC002 0x0000 0x0000 4: 0xD402 0x4230 0xC002 0x0000 0x0000 5: 0xF402 0x4230 0xC002 0x0000 0x0000 6: 0xB402 0x4230 0xC002 0x0000 0x0000 7: 0xF802 0x4230 0xC002 0x0000 0x0000 8: 0xD802 0x4230 0xC002 0x0000 0x0000 9: 0x9802 0x4230 0xC002 0x0000 0x0000 10: 0x1403 0x6230 0xC002 0x0000 0x0000 11: 0x9402 0x4230 0xC002 0x0000 0x0000 12: 0x8802 0x4230 0xC002 0x0000 0x0000 13: 0x0C03 0x6230 0xC002 0x0000 0x0000 14: 0x8802 0x4230 0xC002 0x0000 0x0000 15: 0x8806 0x4230 0xC002 0x0000 0x0000 16: 0x8815 0x4230 0xC002 0x0000 0x0000 17: 0x881D 0x4230 0xC002 0x0000 0x0000 18: 0x880D 0x4230 0xC002 0x0000 0x0000 19: 0x881E 0x4230 0xC002 0x0000 0x0000 20: 0x8816 0x4230 0xC002 0x0000 0x0000 21: 0x8806 0x4230 0xC002 0x0000 0x0000 22: 0x0C05 0x6230 0xC002 0x0000 0x0000 23: 0x8805 0x4230 0xC002 0x0000 0x0000 24: 0x8802 0x4230 0xC002 0x0000 0x0000 25: 0x0C03 0x6230 0xC002 0x0000 0x0000 26: 0x8802 0x4230 0xC002 0x0000 0x0000 27: 0x8802 0xC230 0xC002 0x0000 0x0000 28: 0x8A02 0xA230 0xC002 0x0000 0x0000 29: 0x8B02 0xA230 0xC002 0x0000 0x0000 30: 0x8902 0xA230 0xC002 0x0000 0x0000 31: 0x8B02 0xC230 0xC002 0x0000 0x0000 32: 0x8A02 0xC230 0xC002 0x0000 0x0000 33: 0x8802 0xC230 0xC002 0x0000 0x0000 34: 0x0C03 0xA230 0xC002 0x0000 0x0000 35: 0x8802 0xA230 0xC002 0x0000 0x0000 36: 0x8802 0x4230 0xC002 0x0000 0x0000 37: 0x0C03 0x6230 0xC002 0x0000 0x0000 38: 0x0C03 0x6211 0x0002 0x0000 0x0000 39: 0x0C03 0x6219 0x0002 0x0000 0x0000 40: 0x0C03 0x622B 0x0002 0x0000 0x0000 41: 0x0C03 0x622F 0x0002 0x0000 0x0000 42: 0x0C03 0x622D 0x0002 0x0000 0x0000 43: 0x0C03 0x621F 0x0002 0x0000 0x0000 44: 0x0C03 0x621B 0x0002 0x0000 0x0000 45: 0x0C03 0x6219 0x0002 0x0000 0x0000 46: 0x0C03 0x6228 0xC002 0x0000 0x0000 47: 0x0C03 0x6229 0x0002 0x0000 0x0000 48: 0x0C03 0x6211 0x0002 0x0000 0x0000 49: 0x0C03 0x6230 0xC002 0x0000 0x0000 50: 0x0C03 0x6211 0x0002 0x0000 0x0000 51: 0x0C03 0x6611 0x0002 0x0000 0x0000 52: 0x0C03 0x7411 0x8002 0x0000 0x0000 53: 0x0C03 0x7C11 0x8002 0x0000 0x0000 54: 0x0C03 0x6C11 0x8002 0x0000 0x0000 55: 0x0C03 0x7E11 0x0002 0x0000 0x0000 56: 0x0C03 0x7611 0x0002 0x0000 0x0000 57: 0x0C03 0x6611 0x0002 0x0000 0x0000 58: 0x0C03 0x6430 0xC002 0x0000 0x0000 59: 0x0C03 0x6411 0x8002 0x0000 0x0000 60: 0x0C03 0x6211 0x0002 0x0000 0x0000 61: 0x0C03 0x6230 0xC002 0x0000 0x0000 62: 0x0C03 0x6211 0x0002 0x0000 0x0000 63: 0x0C03 0x6211 0x0003 0x0000 0x0000 64: 0x0C03 0x6251 0x4001 0x0000 0x0000 65: 0x0C03 0x62D1 0x4001 0x0000 0x0000 66: 0x0C03 0x6291 0x4001 0x0000 0x0000 67: 0x0C03 0x62D1 0x0003 0x0000 0x0000 68: 0x0C03 0x6251 0x0003 0x0000 0x0000 69: 0x0C03 0x6211 0x0003 0x0000 0x0000 70: 0x0C03 0x6230 0xC001 0x0000 0x0000 71: 0x0C03 0x6211 0x4001 0x0000 0x0000 72: 0x0C03 0x6211 0x0002 0x0000 0x0000 73: 0x0C03 0x6230 0xC002 0x0000 0x0000 PINs used (in edge connector order) (G=ground,P=power) SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBB LETTER ABCDEFHJKLMNPRSTUVABCDEFHJKLMNPRSTUVABCDEFHJKLMNPRSTUVABCDEFHJKLMNPRSTUV SIDE 111111111111111111222222222222222222111111111111111111222222222222222222 USAGE IIIIOOIIIOOIIIOGOOP GIIIOOIIIIOOIIIO G P G UUT inputs: 20 UUT outputs: 12 pins used: 32 not used: 34 73 'test steps' 111 lines M216 6 FLIP FLOPS PINS Main menu Sun Jul 09 17:20:46 2017 test file is: tests\m216.tst delay is: 0 trigger is: 1 1 read test file 2 set test delay 3 set test trigger 4 run test 5 output loading test 8 diags 9 exit UUT power is okay Sun Jul 09 17:20:47 2017 space single step O run once (one test, all steps) F run, stop on fail G go (run tests N run, stop on fail, no print S scope (run, no print) C turn on comment printout + increase speed (less delay) - decrease speed (more delay)(slower) Q quit test scope (run, no print) pppppppppppppppppppppppppppppppppppppppppppppppppppppppppppp space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn on comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFDEFHJHJKLMKLMNPRNPRSUSTUVV SIDE 11111122222111112222221111122221 DIRECTION IIIIOOIIIOOIIIOOIIIIOOIIIOOIIIOO all fails was lo 00000000000000000000000000000000 falling vvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvv rising ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ was hi 11111111111111111111111111111111 total fails 0, total passes 60 Main menu Sun Jul 09 17:21:29 2017 test file is: tests\m216.tst delay is: 0 trigger is: 1 1 read test file 2 set test delay 3 set test trigger 4 run test 5 output loading test 8 diags 9 exit Enter test file name? trying to open test file: tests\m160.tst reading test file: tests\m160.tst comment: M160 3 AND-OR TREES (4-2-2-2-3;4-2-2-4;2-2) comment: pins: PINS pins: 1 I AA1 E2-1 4-X-X-X-X pins: 2 I AB1 E2-2 4-X-X-X-X pins: 3 I AC1 E2-3 4-X-X-X-X pins: 4 I AD1 E2-13 4-X-X-X-X pins: 5 I AE1 E1-13 X-2-X-X-X pins: 6 I AF1 E1-1 X-2-X-X-X pins: 7 I AH1 E1-2 X-X-2-X-X pins: 8 I AJ1 E1-3 X-X-2-X-X pins: 9 I AK1 E1-5 X-X-X-2-X pins: 10 I AL1 E1-4 X-X-X-2-X pins: 11 I AM1 E2-6 X-X-X-X-3 pins: 12 I AN1 E2-5 X-X-X-X-3 pins: 13 I AP1 E2-4 X-X-X-X-3 pins: 14 O AR1 E1-8 OUPUT pins: 15 I AD2 E4-3 4-X-X-X pins: 16 I AE2 E4-2 4-X-X-X pins: 17 I AF2 E4-1 4-X-X-X pins: 18 I AH2 E4-13 4-X-X-X pins: 19 I AJ2 E3-1 X-2-X-X pins: 20 I AK2 E3-13 X-2-X-X pins: 21 I AL2 E3-10 X-X-2-X pins: 22 I AM2 E3-9 X-X-2-X pins: 23 I AN2 E4-8 X-X-X-4 pins: 24 I AP2 E4-5 X-X-X-4 pins: 25 I AR2 E4-6 X-X-X-4 pins: 26 I AS2 E4-4 X-X-X-4 pins: 27 O AT2 E3-8 OUTPUT pins: 28 I AS1 E3-5 2-X pins: 29 I AU1 E3-4 2-X pins: 30 I AV1 E3-2 X-2 pins: 31 I AU2 E3-3 X-2 pins: 32 O AV2 E3-6 OUTPUT pins: direction: IIIIIIIIIIIIIOIIIIIIIIIIIIOIIIIO test 1: 00000000000001000000000000100001 test 2: 0001 1 test 3: 0011 1 test 4: 0010 1 test 5: 0110 1 test 6: 0111 1 test 7: 0101 1 test 8: 0100 1 test 9: 1100 1 test 10: 1101 1 test 11: 1111 0 test 12: 1110 1 test 13: 1010 1 test 14: 1011 1 test 15: 1001 1 test 16: 1000 1 test 17: 00000000000001000000000000100001 test 18: 01 1 test 19: 10 1 test 20: 11 0 test 21: 01 1 test 22: 00000000000001000000000000100001 test 23: 01 1 test 24: 10 1 test 25: 11 0 test 26: 01 1 test 27: 00000000000001000000000000100001 test 28: 01 1 test 29: 10 1 test 30: 11 0 test 31: 01 1 test 32: 00000000000001000000000000100001 test 33: 0011 test 34: 0111 test 35: 0101 test 36: 0101 test 37: 1110 test 38: 1011 test 39: 1001 test 40: 00000000000001000000000000100001 test 41: 0001 1 test 42: 0011 1 test 43: 0010 1 test 44: 0110 1 test 45: 0111 1 test 46: 0101 1 test 47: 0100 1 test 48: 1100 1 test 49: 1101 1 test 50: 1111 0 test 51: 1110 1 test 52: 1010 1 test 53: 1011 1 test 54: 1001 1 test 55: 1000 1 test 56: 00000000000001000000000000100001 test 57: 01 1 test 58: 10 1 test 59: 11 0 test 60: 01 1 test 61: 00000000000001000000000000100001 test 62: 01 1 test 63: 10 1 test 64: 11 0 test 65: 01 1 test 66: 00000000000001000000000000100001 test 67: 00011 test 68: 00111 test 69: 00101 test 70: 01101 test 71: 01111 test 72: 01011 test 73: 01001 test 74: 11001 test 75: 11011 test 76: 11110 test 77: 11101 test 78: 10101 test 79: 10111 test 80: 10011 test 81: 10001 test 82: 00000000000001000000000000100001 test 83: 01 1 test 84: 10 1 test 85: 11 0 test 86: 01 1 test 87: 00000000000001000000000000100001 test 88: 011 test 89: 101 test 90: 110 test 91: 011 test 92: 00000000000001000000000000100001 end: END summary column 1: offset 0, mask 0x8000 column 2: offset 0, mask 0x4000 column 3: offset 0, mask 0x2000 column 4: offset 0, mask 0x1000 column 5: offset 0, mask 0x0800 column 6: offset 0, mask 0x0400 column 7: offset 0, mask 0x0200 column 8: offset 0, mask 0x0100 column 9: offset 1, mask 0x8000 column 10: offset 1, mask 0x4000 column 11: offset 1, mask 0x2000 column 12: offset 1, mask 0x1000 column 13: offset 1, mask 0x0800 column 14: offset 1, mask 0x0400 column 15: offset 0, mask 0x0010 column 16: offset 0, mask 0x0008 column 17: offset 0, mask 0x0004 column 18: offset 0, mask 0x0002 column 19: offset 0, mask 0x0001 column 20: offset 1, mask 0x0001 column 21: offset 1, mask 0x0002 column 22: offset 1, mask 0x0004 column 23: offset 1, mask 0x0008 column 24: offset 1, mask 0x0010 column 25: offset 1, mask 0x0020 column 26: offset 1, mask 0x0040 column 27: offset 1, mask 0x0080 column 28: offset 1, mask 0x0200 column 29: offset 2, mask 0x8000 column 30: offset 2, mask 0x4000 column 31: offset 2, mask 0x0001 column 32: offset 2, mask 0x0002 direction bits (1=input) 0x00E0 0x0580 0x3FFA 0xFFFF 0xF0FF pullup bits (1=pullup) 0x0000 0x0000 0x0000 0x0000 0x0000 test step out_data dont care 1: 0x0000 0x0480 0x0002 0x0000 0x0000 2: 0x1000 0x0480 0x0002 0x0000 0x0000 3: 0x3000 0x0480 0x0002 0x0000 0x0000 4: 0x2000 0x0480 0x0002 0x0000 0x0000 5: 0x6000 0x0480 0x0002 0x0000 0x0000 6: 0x7000 0x0480 0x0002 0x0000 0x0000 7: 0x5000 0x0480 0x0002 0x0000 0x0000 8: 0x4000 0x0480 0x0002 0x0000 0x0000 9: 0xC000 0x0480 0x0002 0x0000 0x0000 10: 0xD000 0x0480 0x0002 0x0000 0x0000 11: 0xF000 0x0080 0x0002 0x0000 0x0000 12: 0xE000 0x0480 0x0002 0x0000 0x0000 13: 0xA000 0x0480 0x0002 0x0000 0x0000 14: 0xB000 0x0480 0x0002 0x0000 0x0000 15: 0x9000 0x0480 0x0002 0x0000 0x0000 16: 0x8000 0x0480 0x0002 0x0000 0x0000 17: 0x0000 0x0480 0x0002 0x0000 0x0000 18: 0x0400 0x0480 0x0002 0x0000 0x0000 19: 0x0800 0x0480 0x0002 0x0000 0x0000 20: 0x0C00 0x0080 0x0002 0x0000 0x0000 21: 0x0400 0x0480 0x0002 0x0000 0x0000 22: 0x0000 0x0480 0x0002 0x0000 0x0000 23: 0x0100 0x0480 0x0002 0x0000 0x0000 24: 0x0200 0x0480 0x0002 0x0000 0x0000 25: 0x0300 0x0080 0x0002 0x0000 0x0000 26: 0x0100 0x0480 0x0002 0x0000 0x0000 27: 0x0000 0x0480 0x0002 0x0000 0x0000 28: 0x0000 0x4480 0x0002 0x0000 0x0000 29: 0x0000 0x8480 0x0002 0x0000 0x0000 30: 0x0000 0xC080 0x0002 0x0000 0x0000 31: 0x0000 0x4480 0x0002 0x0000 0x0000 32: 0x0000 0x0480 0x0002 0x0000 0x0000 33: 0x0000 0x0C80 0x0002 0x0000 0x0000 34: 0x0000 0x1C80 0x0002 0x0000 0x0000 35: 0x0000 0x1480 0x0002 0x0000 0x0000 36: 0x0000 0x1480 0x0002 0x0000 0x0000 37: 0x0000 0x3880 0x0002 0x0000 0x0000 38: 0x0000 0x2C80 0x0002 0x0000 0x0000 39: 0x0000 0x2480 0x0002 0x0000 0x0000 40: 0x0000 0x0480 0x0002 0x0000 0x0000 41: 0x0002 0x0480 0x0002 0x0000 0x0000 42: 0x0006 0x0480 0x0002 0x0000 0x0000 43: 0x0004 0x0480 0x0002 0x0000 0x0000 44: 0x000C 0x0480 0x0002 0x0000 0x0000 45: 0x000E 0x0480 0x0002 0x0000 0x0000 46: 0x000A 0x0480 0x0002 0x0000 0x0000 47: 0x0008 0x0480 0x0002 0x0000 0x0000 48: 0x0018 0x0480 0x0002 0x0000 0x0000 49: 0x001A 0x0480 0x0002 0x0000 0x0000 50: 0x001E 0x0400 0x0002 0x0000 0x0000 51: 0x001C 0x0480 0x0002 0x0000 0x0000 52: 0x0014 0x0480 0x0002 0x0000 0x0000 53: 0x0016 0x0480 0x0002 0x0000 0x0000 54: 0x0012 0x0480 0x0002 0x0000 0x0000 55: 0x0010 0x0480 0x0002 0x0000 0x0000 56: 0x0000 0x0480 0x0002 0x0000 0x0000 57: 0x0000 0x0481 0x0002 0x0000 0x0000 58: 0x0001 0x0480 0x0002 0x0000 0x0000 59: 0x0001 0x0401 0x0002 0x0000 0x0000 60: 0x0000 0x0481 0x0002 0x0000 0x0000 61: 0x0000 0x0480 0x0002 0x0000 0x0000 62: 0x0000 0x0484 0x0002 0x0000 0x0000 63: 0x0000 0x0482 0x0002 0x0000 0x0000 64: 0x0000 0x0406 0x0002 0x0000 0x0000 65: 0x0000 0x0484 0x0002 0x0000 0x0000 66: 0x0000 0x0480 0x0002 0x0000 0x0000 67: 0x0000 0x04C0 0x0002 0x0000 0x0000 68: 0x0000 0x04E0 0x0002 0x0000 0x0000 69: 0x0000 0x04A0 0x0002 0x0000 0x0000 70: 0x0000 0x04B0 0x0002 0x0000 0x0000 71: 0x0000 0x04F0 0x0002 0x0000 0x0000 72: 0x0000 0x04D0 0x0002 0x0000 0x0000 73: 0x0000 0x0490 0x0002 0x0000 0x0000 74: 0x0000 0x0498 0x0002 0x0000 0x0000 75: 0x0000 0x04D8 0x0002 0x0000 0x0000 76: 0x0000 0x0478 0x0002 0x0000 0x0000 77: 0x0000 0x04B8 0x0002 0x0000 0x0000 78: 0x0000 0x04A8 0x0002 0x0000 0x0000 79: 0x0000 0x04E8 0x0002 0x0000 0x0000 80: 0x0000 0x04C8 0x0002 0x0000 0x0000 81: 0x0000 0x0488 0x0002 0x0000 0x0000 82: 0x0000 0x0480 0x0002 0x0000 0x0000 83: 0x0000 0x0480 0x8002 0x0000 0x0000 84: 0x0000 0x0680 0x0002 0x0000 0x0000 85: 0x0000 0x0680 0x8000 0x0000 0x0000 86: 0x0000 0x0480 0x8002 0x0000 0x0000 87: 0x0000 0x0480 0x0002 0x0000 0x0000 88: 0x0000 0x0480 0x0003 0x0000 0x0000 89: 0x0000 0x0480 0x4002 0x0000 0x0000 90: 0x0000 0x0480 0x4001 0x0000 0x0000 91: 0x0000 0x0480 0x0003 0x0000 0x0000 92: 0x0000 0x0480 0x0002 0x0000 0x0000 PINs used (in edge connector order) (G=ground,P=power) SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBB LETTER ABCDEFHJKLMNPRSTUVABCDEFHJKLMNPRSTUVABCDEFHJKLMNPRSTUVABCDEFHJKLMNPRSTUV SIDE 111111111111111111222222222222222222111111111111111111222222222222222222 USAGE IIIIIIIIIIIIIOIGIIP GIIIIIIIIIIIIOIO G P G UUT inputs: 29 UUT outputs: 3 pins used: 32 not used: 34 92 'test steps' 130 lines M160 3 AND-OR TREES (4-2-2-2-3;4-2-2-4;2-2) PINS Main menu Sun Jul 09 17:25:53 2017 test file is: tests\m160.tst delay is: 0 trigger is: 1 1 read test file 2 set test delay 3 set test trigger 4 run test 5 output loading test 8 diags 9 exit UUT power is okay Sun Jul 09 17:27:44 2017 space single step O run once (one test, all steps) F run, stop on fail G go (run tests N run, stop on fail, no print S scope (run, no print) C turn on comment printout + increase speed (less delay) - decrease speed (more delay)(slower) Q quit test scope (run, no print) pppppppppppppppppppppppppppppppppppppppppppppppp space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn on comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit scope (run, no print) ppppppppppppppppppppppppppppppp pppppppppppppp space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn on comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFHJKLMNPRDEFHJKLMNPRSTSUVUV SIDE 11111111111111222222222222211122 DIRECTION IIIIIIIIIIIIIOIIIIIIIIIIIIOIIIIO all fails was lo 00000000000000000000000000000000 falling vvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvv rising ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ was hi 11111111111111111111111111111111 total fails 0, total passes 93 Main menu Sun Jul 09 17:29:23 2017 test file is: tests\m160.tst delay is: 0 trigger is: 1 1 read test file 2 set test delay 3 set test trigger 4 run test 5 output loading test 8 diags 9 exit exiting tester- PDP8 card tester via printer port version 0.91 November 27, 2015 mapping[] is verified Main menu Mon Jul 10 10:57:00 2017 test file is: delay is: 0 trigger is: 1 1 read test file 2 set test delay 3 set test trigger 4 run test 5 output loading test 8 diags 9 exit Enter test file name? trying to open test file: tests\m113.tst reading test file: tests\m113.tst comment: M113 10 2-input NAND comment: pins: PINS pins: 1 I AA1 E1-1 pins: 2 I AB1 E1-2 pins: 3 O AC1 E1-3 pins: 4 I AD1 E1-4 pins: 5 I AE1 E1-5 pins: 6 O AF1 E1-6 pins: 7 I AD2 E1-13 pins: 8 I AE2 E1-12 pins: 9 O AF2 E1-11 pins: 10 I AH1 E3-4 pins: 11 I AJ1 E3-5 pins: 12 O AK1 E3-6 pins: 13 I AH2 E3-10 pins: 14 I AJ2 E3-9 pins: 15 O AK2 E3-8 pins: 16 I AL1 E2-1 pins: 17 I AM1 E2-2 pins: 18 O AN1 E2-3 pins: 19 I AL2 E3-10 pins: 20 I AM2 E3-9 pins: 21 O AN2 E3-8 pins: 22 I AP1 E2-4 pins: 23 I AR1 E2-5 pins: 24 O AS1 E2-6 pins: 25 I AP2 E2-13 pins: 26 I AR2 E2-12 pins: 27 O AS2 E2-11 pins: 28 I AT2 E2-10 pins: 29 I AU2 E2-9 pins: 30 O AV2 E2-8 pins: direction: IIOIIOIIOIIOIIOIIOIIOIIOIIOIIO test 1: 001001001001001001001001001001 test 2: 110110110110110110110110110110 test 3: 011 test 4: 001 test 5: 101 test 6: 110 test 7: 011 test 8: 001 test 9: 101 test 10: 110 test 11: 011 test 12: 001 test 13: 101 test 14: 110 test 15: 011 test 16: 001 test 17: 101 test 18: 110 test 19: 011 test 20: 001 test 21: 101 test 22: 110 test 23: 011 test 24: 001 test 25: 101 test 26: 110 test 27: 011 test 28: 001 test 29: 101 test 30: 110 test 31: 011 test 32: 001 test 33: 101 test 34: 110 test 35: 011 test 36: 001 test 37: 101 test 38: 110 test 39: 011 test 40: 001 test 41: 101 test 42: 110 test 43: 001001001001001001001001001001 test 44: 011 test 45: 110 test 46: 101 test 47: 001 test 48: 011 test 49: 110 test 50: 101 test 51: 001 test 52: 011 test 53: 110 test 54: 101 test 55: 001 test 56: 011 test 57: 110 test 58: 101 test 59: 001 test 60: 011 test 61: 110 test 62: 101 test 63: 001 test 64: 011 test 65: 110 test 66: 101 test 67: 001 test 68: 011 test 69: 110 test 70: 101 test 71: 001 test 72: 011 test 73: 110 test 74: 101 test 75: 001 test 76: 011 test 77: 110 test 78: 101 test 79: 001 test 80: 011 test 81: 110 test 82: 101 test 83: 001 end: END summary column 1: offset 0, mask 0x8000 column 2: offset 0, mask 0x4000 column 3: offset 0, mask 0x2000 column 4: offset 0, mask 0x1000 column 5: offset 0, mask 0x0800 column 6: offset 0, mask 0x0400 column 7: offset 0, mask 0x0010 column 8: offset 0, mask 0x0008 column 9: offset 0, mask 0x0004 column 10: offset 0, mask 0x0200 column 11: offset 0, mask 0x0100 column 12: offset 1, mask 0x8000 column 13: offset 0, mask 0x0002 column 14: offset 0, mask 0x0001 column 15: offset 1, mask 0x0001 column 16: offset 1, mask 0x4000 column 17: offset 1, mask 0x2000 column 18: offset 1, mask 0x1000 column 19: offset 1, mask 0x0002 column 20: offset 1, mask 0x0004 column 21: offset 1, mask 0x0008 column 22: offset 1, mask 0x0800 column 23: offset 1, mask 0x0400 column 24: offset 1, mask 0x0200 column 25: offset 1, mask 0x0010 column 26: offset 1, mask 0x0020 column 27: offset 1, mask 0x0040 column 28: offset 1, mask 0x0080 column 29: offset 2, mask 0x0001 column 30: offset 2, mask 0x0002 direction bits (1=input) 0x24E4 0x9349 0xFFFA 0xFFFF 0xF0FF pullup bits (1=pullup) 0x0000 0x0000 0x0000 0x0000 0x0000 test step out_data dont care 1: 0x2404 0x9249 0x0002 0x0000 0x0000 2: 0xDB1B 0x6CB6 0x0001 0x0000 0x0000 3: 0x7B1B 0x6CB6 0x0001 0x0000 0x0000 4: 0x3B1B 0x6CB6 0x0001 0x0000 0x0000 5: 0xBB1B 0x6CB6 0x0001 0x0000 0x0000 6: 0xDB1B 0x6CB6 0x0001 0x0000 0x0000 7: 0xCF1B 0x6CB6 0x0001 0x0000 0x0000 8: 0xC71B 0x6CB6 0x0001 0x0000 0x0000 9: 0xD71B 0x6CB6 0x0001 0x0000 0x0000 10: 0xDB1B 0x6CB6 0x0001 0x0000 0x0000 11: 0xDB0F 0x6CB6 0x0001 0x0000 0x0000 12: 0xDB07 0x6CB6 0x0001 0x0000 0x0000 13: 0xDB17 0x6CB6 0x0001 0x0000 0x0000 14: 0xDB1B 0x6CB6 0x0001 0x0000 0x0000 15: 0xD91B 0xECB6 0x0001 0x0000 0x0000 16: 0xD81B 0xECB6 0x0001 0x0000 0x0000 17: 0xDA1B 0xECB6 0x0001 0x0000 0x0000 18: 0xDB1B 0x6CB6 0x0001 0x0000 0x0000 19: 0xDB19 0x6CB7 0x0001 0x0000 0x0000 20: 0xDB18 0x6CB7 0x0001 0x0000 0x0000 21: 0xDB1A 0x6CB7 0x0001 0x0000 0x0000 22: 0xDB1B 0x6CB6 0x0001 0x0000 0x0000 23: 0xDB1B 0x3CB6 0x0001 0x0000 0x0000 24: 0xDB1B 0x1CB6 0x0001 0x0000 0x0000 25: 0xDB1B 0x5CB6 0x0001 0x0000 0x0000 26: 0xDB1B 0x6CB6 0x0001 0x0000 0x0000 27: 0xDB1B 0x6CBC 0x0001 0x0000 0x0000 28: 0xDB1B 0x6CB8 0x0001 0x0000 0x0000 29: 0xDB1B 0x6CBA 0x0001 0x0000 0x0000 30: 0xDB1B 0x6CB6 0x0001 0x0000 0x0000 31: 0xDB1B 0x66B6 0x0001 0x0000 0x0000 32: 0xDB1B 0x62B6 0x0001 0x0000 0x0000 33: 0xDB1B 0x6AB6 0x0001 0x0000 0x0000 34: 0xDB1B 0x6CB6 0x0001 0x0000 0x0000 35: 0xDB1B 0x6CE6 0x0001 0x0000 0x0000 36: 0xDB1B 0x6CC6 0x0001 0x0000 0x0000 37: 0xDB1B 0x6CD6 0x0001 0x0000 0x0000 38: 0xDB1B 0x6CB6 0x0001 0x0000 0x0000 39: 0xDB1B 0x6C36 0x0003 0x0000 0x0000 40: 0xDB1B 0x6C36 0x0002 0x0000 0x0000 41: 0xDB1B 0x6CB6 0x0002 0x0000 0x0000 42: 0xDB1B 0x6CB6 0x0001 0x0000 0x0000 43: 0x2404 0x9249 0x0002 0x0000 0x0000 44: 0x6404 0x9249 0x0002 0x0000 0x0000 45: 0xC404 0x9249 0x0002 0x0000 0x0000 46: 0xA404 0x9249 0x0002 0x0000 0x0000 47: 0x2404 0x9249 0x0002 0x0000 0x0000 48: 0x2C04 0x9249 0x0002 0x0000 0x0000 49: 0x3804 0x9249 0x0002 0x0000 0x0000 50: 0x3404 0x9249 0x0002 0x0000 0x0000 51: 0x2404 0x9249 0x0002 0x0000 0x0000 52: 0x240C 0x9249 0x0002 0x0000 0x0000 53: 0x2418 0x9249 0x0002 0x0000 0x0000 54: 0x2414 0x9249 0x0002 0x0000 0x0000 55: 0x2404 0x9249 0x0002 0x0000 0x0000 56: 0x2504 0x9249 0x0002 0x0000 0x0000 57: 0x2704 0x1249 0x0002 0x0000 0x0000 58: 0x2604 0x9249 0x0002 0x0000 0x0000 59: 0x2404 0x9249 0x0002 0x0000 0x0000 60: 0x2405 0x9249 0x0002 0x0000 0x0000 61: 0x2407 0x9248 0x0002 0x0000 0x0000 62: 0x2406 0x9249 0x0002 0x0000 0x0000 63: 0x2404 0x9249 0x0002 0x0000 0x0000 64: 0x2404 0xB249 0x0002 0x0000 0x0000 65: 0x2404 0xE249 0x0002 0x0000 0x0000 66: 0x2404 0xD249 0x0002 0x0000 0x0000 67: 0x2404 0x9249 0x0002 0x0000 0x0000 68: 0x2404 0x924D 0x0002 0x0000 0x0000 69: 0x2404 0x9247 0x0002 0x0000 0x0000 70: 0x2404 0x924B 0x0002 0x0000 0x0000 71: 0x2404 0x9249 0x0002 0x0000 0x0000 72: 0x2404 0x9649 0x0002 0x0000 0x0000 73: 0x2404 0x9C49 0x0002 0x0000 0x0000 74: 0x2404 0x9A49 0x0002 0x0000 0x0000 75: 0x2404 0x9249 0x0002 0x0000 0x0000 76: 0x2404 0x9269 0x0002 0x0000 0x0000 77: 0x2404 0x9239 0x0002 0x0000 0x0000 78: 0x2404 0x9259 0x0002 0x0000 0x0000 79: 0x2404 0x9249 0x0002 0x0000 0x0000 80: 0x2404 0x9249 0x0003 0x0000 0x0000 81: 0x2404 0x92C9 0x0001 0x0000 0x0000 82: 0x2404 0x92C9 0x0002 0x0000 0x0000 83: 0x2404 0x9249 0x0002 0x0000 0x0000 PINs used (in edge connector order) (G=ground,P=power) SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBB LETTER ABCDEFHJKLMNPRSTUVABCDEFHJKLMNPRSTUVABCDEFHJKLMNPRSTUVABCDEFHJKLMNPRSTUV SIDE 111111111111111111222222222222222222111111111111111111222222222222222222 USAGE IIOIIOIIOIIOIIOG P GIIOIIOIIOIIOIIO G P G UUT inputs: 20 UUT outputs: 10 pins used: 30 not used: 36 83 'test steps' 119 lines M113 10 2-input NAND PINS Main menu Mon Jul 10 10:57:08 2017 test file is: tests\m113.tst delay is: 0 trigger is: 1 1 read test file 2 set test delay 3 set test trigger 4 run test 5 output loading test 8 diags 9 exit UUT power is okay Mon Jul 10 10:57:10 2017 space single step O run once (one test, all steps) F run, stop on fail G go (run tests N run, stop on fail, no print S scope (run, no print) C turn on comment printout + increase speed (less delay) - decrease speed (more delay)(slower) Q quit test scope (run, no print) FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn on comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFDEFHJKHJKLMNLMNPRSPRSTUV SIDE 111111222111222111222111222222 DIRECTION IIOIIOIIOIIOIIOIIOIIOIIOIIOIIO all fails O was lo 000000000000000000000000000000 falling vvvvvvvvvvvvvvvvvvvvvvvvvvvvvv rising ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ was hi 111111111111111111111111111111 total fails 61, total passes 0 Main menu Mon Jul 10 10:57:29 2017 test file is: tests\m113.tst delay is: 0 trigger is: 1 1 read test file 2 set test delay 3 set test trigger 4 run test 5 output loading test 8 diags 9 exit ***************************** UUT power is OFF * ***************************** Main menu Mon Jul 10 10:57:32 2017 test file is: tests\m113.tst delay is: 0 trigger is: 1 1 read test file 2 set test delay 3 set test trigger 4 run test 5 output loading test 8 diags 9 exit UUT power is okay Mon Jul 10 10:57:35 2017 space single step O run once (one test, all steps) F run, stop on fail G go (run tests N run, stop on fail, no print S scope (run, no print) C turn on comment printout + increase speed (less delay) - decrease speed (more delay)(slower) Q quit test scope (run, no print) FFFFFFFFFFFFFFFFFFF space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn on comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit step 19 110110110110011110110110110110 step 20 110110110110001110110110110110 step 21 110110110110101110110110110110 step 22 110110110110110110110110110110 step 23 110110110110110011110110110110 step 24 110110110110110001110110110110 step 25 110110110110110101110110110110 step 26 110110110110110110110110110110 step 27 110110110110110110011110110110 step 28 110110110110110110001110110110 step 29 110110110110110110101110110110 step 30 110110110110110110110110110110 step 31 110110110110110110110011110110 step 32 110110110110110110110001110110 step 33 110110110110110110110101110110 step 34 110110110110110110110110110110 step 35 110110110110110110110110011110 step 36 110110110110110110110110001110 step 37 110110110110110110110110101110 step 38 110110110110110110110110110110 step 39 110110110110110110110110110011 step 40 110110110110110110110110110001 step 41 110110110110110110110110110101 step 42 110110110110110110110110110110 step 43 001001001001001001001001001001 step 44 011001001001001001001001001001 step 45 110001001001001001001001001001 SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFDEFHJKHJKLMNLMNPRSPRSTUV SIDE 111111222111222111222111222222 DIRECTION IIOIIOIIOIIOIIOIIOIIOIIOIIOIIO changed: 0 step 46 100001001001001001001001001001 fail ^ step 47 001001001001001001001001001001 step 48 001011001001001001001001001001 step 49 001110001001001001001001001001 step 50 001101001001001001001001001001 step 51 001001001001001001001001001001 step 52 001001011001001001001001001001 step 53 001001110001001001001001001001 step 54 001001101001001001001001001001 step 55 001001001001001001001001001001 step 56 001001001011001001001001001001 step 57 001001001110001001001001001001 step 58 001001001101001001001001001001 step 59 001001001001001001001001001001 step 60 001001001001011001001001001001 step 61 001001001001110001001001001001 step 62 001001001001101001001001001001 step 63 001001001001001001001001001001 step 64 001001001001001011001001001001 step 65 001001001001001110001001001001 step 66 001001001001001101001001001001 step 67 001001001001001001001001001001 step 68 001001001001001001011001001001 step 69 001001001001001001110001001001 step 70 001001001001001001101001001001 step 71 001001001001001001001001001001 step 72 001001001001001001001011001001 step 73 001001001001001001001110001001 step 74 001001001001001001001101001001 step 75 001001001001001001001001001001 step 76 001001001001001001001001011001 step 77 001001001001001001001001110001 step 78 001001001001001001001001101001 step 79 001001001001001001001001001001 step 80 001001001001001001001001001011 step 81 001001001001001001001001001110 step 82 001001001001001001001001001101 step 83 001001001001001001001001001001 test 20: *** FAIL *************************** 2 steps failed SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFDEFHJKHJKLMNLMNPRSPRSTUV SIDE 111111222111222111222111222222 DIRECTION IIOIIOIIOIIOIIOIIOIIOIIOIIOIIO this fail O all fails O was hi 111111111111111111111111111111 rising ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ falling vvvvvvvvvvvvvvvvvvvvvvvvvvvvvv was lo 000000000000000000000000000000 total fails 20, total passes 0 space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn on comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit step 1 001001001001001001001001001001 step 2 110110110110110110110110110110 step 3 011110110110110110110110110110 step 4 001110110110110110110110110110 SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFDEFHJKHJKLMNLMNPRSPRSTUV SIDE 111111222111222111222111222222 DIRECTION IIOIIOIIOIIOIIOIIOIIOIIOIIOIIO changed: 1 0 step 5 100110110110110110110110110110 fail ^ step 6 110110110110110110110110110110 step 7 110011110110110110110110110110 step 8 110001110110110110110110110110 step 9 110101110110110110110110110110 step 10 110110110110110110110110110110 step 11 110110011110110110110110110110 step 12 110110001110110110110110110110 step 13 110110101110110110110110110110 step 14 110110110110110110110110110110 step 15 110110110011110110110110110110 step 16 110110110001110110110110110110 step 17 110110110101110110110110110110 step 18 110110110110110110110110110110 step 19 110110110110011110110110110110 step 20 110110110110001110110110110110 step 21 110110110110101110110110110110 step 22 110110110110110110110110110110 step 23 110110110110110011110110110110 step 24 110110110110110001110110110110 step 25 110110110110110101110110110110 step 26 110110110110110110110110110110 step 27 110110110110110110011110110110 step 28 110110110110110110001110110110 step 29 110110110110110110101110110110 step 30 110110110110110110110110110110 step 31 110110110110110110110011110110 step 32 110110110110110110110001110110 step 33 110110110110110110110101110110 step 34 110110110110110110110110110110 step 35 110110110110110110110110011110 step 36 110110110110110110110110001110 step 37 110110110110110110110110101110 step 38 110110110110110110110110110110 step 39 110110110110110110110110110011 step 40 110110110110110110110110110001 step 41 110110110110110110110110110101 step 42 110110110110110110110110110110 step 43 001001001001001001001001001001 step 44 011001001001001001001001001001 step 45 110001001001001001001001001001 SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFDEFHJKHJKLMNLMNPRSPRSTUV SIDE 111111222111222111222111222222 DIRECTION IIOIIOIIOIIOIIOIIOIIOIIOIIOIIO changed: 0 step 46 100001001001001001001001001001 fail ^ step 47 001001001001001001001001001001 step 48 001011001001001001001001001001 step 49 001110001001001001001001001001 step 50 001101001001001001001001001001 step 51 001001001001001001001001001001 step 52 001001011001001001001001001001 step 53 001001110001001001001001001001 step 54 001001101001001001001001001001 step 55 001001001001001001001001001001 step 56 001001001011001001001001001001 step 57 001001001110001001001001001001 step 58 001001001101001001001001001001 step 59 001001001001001001001001001001 step 60 001001001001011001001001001001 step 61 001001001001110001001001001001 step 62 001001001001101001001001001001 step 63 001001001001001001001001001001 step 64 001001001001001011001001001001 step 65 001001001001001110001001001001 step 66 001001001001001101001001001001 step 67 001001001001001001001001001001 step 68 001001001001001001011001001001 step 69 001001001001001001110001001001 step 70 001001001001001001101001001001 step 71 001001001001001001001001001001 step 72 001001001001001001001011001001 step 73 001001001001001001001110001001 step 74 001001001001001001001101001001 step 75 001001001001001001001001001001 step 76 001001001001001001001001011001 step 77 001001001001001001001001110001 step 78 001001001001001001001001101001 step 79 001001001001001001001001001001 step 80 001001001001001001001001001011 step 81 001001001001001001001001001110 step 82 001001001001001001001001001101 step 83 001001001001001001001001001001 test 21: *** FAIL *************************** 2 steps failed SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFDEFHJKHJKLMNLMNPRSPRSTUV SIDE 111111222111222111222111222222 DIRECTION IIOIIOIIOIIOIIOIIOIIOIIOIIOIIO this fail O all fails O was hi 111111111111111111111111111111 rising ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ falling vvvvvvvvvvvvvvvvvvvvvvvvvvvvvv was lo 000000000000000000000000000000 total fails 21, total passes 0 space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn on comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit step 1 001001001001001001001001001001 step 2 110110110110110110110110110110 step 3 011110110110110110110110110110 step 4 001110110110110110110110110110 SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFDEFHJKHJKLMNLMNPRSPRSTUV SIDE 111111222111222111222111222222 DIRECTION IIOIIOIIOIIOIIOIIOIIOIIOIIOIIO changed: 1 0 step 5 100110110110110110110110110110 fail ^ step 6 110110110110110110110110110110 step 7 110011110110110110110110110110 step 8 110001110110110110110110110110 step 9 110101110110110110110110110110 step 10 110110110110110110110110110110 step 11 110110011110110110110110110110 step 12 110110001110110110110110110110 step 13 110110101110110110110110110110 step 14 110110110110110110110110110110 step 15 110110110011110110110110110110 step 16 110110110001110110110110110110 step 17 110110110101110110110110110110 step 18 110110110110110110110110110110 step 19 110110110110011110110110110110 step 20 110110110110001110110110110110 step 21 110110110110101110110110110110 step 22 110110110110110110110110110110 step 23 110110110110110011110110110110 step 24 110110110110110001110110110110 step 25 110110110110110101110110110110 step 26 110110110110110110110110110110 step 27 110110110110110110011110110110 step 28 110110110110110110001110110110 step 29 110110110110110110101110110110 step 30 110110110110110110110110110110 step 31 110110110110110110110011110110 step 32 110110110110110110110001110110 step 33 110110110110110110110101110110 step 34 110110110110110110110110110110 step 35 110110110110110110110110011110 step 36 110110110110110110110110001110 step 37 110110110110110110110110101110 step 38 110110110110110110110110110110 step 39 110110110110110110110110110011 step 40 110110110110110110110110110001 step 41 110110110110110110110110110101 step 42 110110110110110110110110110110 step 43 001001001001001001001001001001 step 44 011001001001001001001001001001 step 45 110001001001001001001001001001 SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFDEFHJKHJKLMNLMNPRSPRSTUV SIDE 111111222111222111222111222222 DIRECTION IIOIIOIIOIIOIIOIIOIIOIIOIIOIIO changed: 0 step 46 100001001001001001001001001001 fail ^ step 47 001001001001001001001001001001 step 48 001011001001001001001001001001 step 49 001110001001001001001001001001 step 50 001101001001001001001001001001 step 51 001001001001001001001001001001 step 52 001001011001001001001001001001 step 53 001001110001001001001001001001 step 54 001001101001001001001001001001 step 55 001001001001001001001001001001 step 56 001001001011001001001001001001 step 57 001001001110001001001001001001 step 58 001001001101001001001001001001 step 59 001001001001001001001001001001 step 60 001001001001011001001001001001 step 61 001001001001110001001001001001 step 62 001001001001101001001001001001 step 63 001001001001001001001001001001 step 64 001001001001001011001001001001 step 65 001001001001001110001001001001 step 66 001001001001001101001001001001 step 67 001001001001001001001001001001 step 68 001001001001001001011001001001 step 69 001001001001001001110001001001 step 70 001001001001001001101001001001 step 71 001001001001001001001001001001 step 72 001001001001001001001011001001 step 73 001001001001001001001110001001 step 74 001001001001001001001101001001 step 75 001001001001001001001001001001 step 76 001001001001001001001001011001 step 77 001001001001001001001001110001 step 78 001001001001001001001001101001 step 79 001001001001001001001001001001 step 80 001001001001001001001001001011 step 81 001001001001001001001001001110 step 82 001001001001001001001001001101 step 83 001001001001001001001001001001 test 22: *** FAIL *************************** 2 steps failed SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFDEFHJKHJKLMNLMNPRSPRSTUV SIDE 111111222111222111222111222222 DIRECTION IIOIIOIIOIIOIIOIIOIIOIIOIIOIIO this fail O all fails O was hi 111111111111111111111111111111 rising ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ falling vvvvvvvvvvvvvvvvvvvvvvvvvvvvvv was lo 000000000000000000000000000000 total fails 22, total passes 0 space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn on comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit step 1 001001001001001001001001001001 step 2 110110110110110110110110110110 step 3 011110110110110110110110110110 step 4 001110110110110110110110110110 SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFDEFHJKHJKLMNLMNPRSPRSTUV SIDE 111111222111222111222111222222 DIRECTION IIOIIOIIOIIOIIOIIOIIOIIOIIOIIO changed: 1 0 step 5 100110110110110110110110110110 fail ^ space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn on comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit step 6 110110110110110110110110110110 step 7 110011110110110110110110110110 step 8 110001110110110110110110110110 step 9 110101110110110110110110110110 step 10 110110110110110110110110110110 step 11 110110011110110110110110110110 step 12 110110001110110110110110110110 step 13 110110101110110110110110110110 step 14 110110110110110110110110110110 step 15 110110110011110110110110110110 step 16 110110110001110110110110110110 step 17 110110110101110110110110110110 step 18 110110110110110110110110110110 step 19 110110110110011110110110110110 step 20 110110110110001110110110110110 step 21 110110110110101110110110110110 step 22 110110110110110110110110110110 step 23 110110110110110011110110110110 step 24 110110110110110001110110110110 step 25 110110110110110101110110110110 step 26 110110110110110110110110110110 step 27 110110110110110110011110110110 step 28 110110110110110110001110110110 step 29 110110110110110110101110110110 step 30 110110110110110110110110110110 step 31 110110110110110110110011110110 step 32 110110110110110110110001110110 step 33 110110110110110110110101110110 step 34 110110110110110110110110110110 step 35 110110110110110110110110011110 step 36 110110110110110110110110001110 step 37 110110110110110110110110101110 step 38 110110110110110110110110110110 step 39 110110110110110110110110110011 step 40 110110110110110110110110110001 step 41 110110110110110110110110110101 step 42 110110110110110110110110110110 step 43 001001001001001001001001001001 step 44 011001001001001001001001001001 step 45 110001001001001001001001001001 SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFDEFHJKHJKLMNLMNPRSPRSTUV SIDE 111111222111222111222111222222 DIRECTION IIOIIOIIOIIOIIOIIOIIOIIOIIOIIO changed: 0 step 46 100001001001001001001001001001 fail ^ step 47 001001001001001001001001001001 step 48 001011001001001001001001001001 step 49 001110001001001001001001001001 step 50 001101001001001001001001001001 step 51 001001001001001001001001001001 step 52 001001011001001001001001001001 step 53 001001110001001001001001001001 step 54 001001101001001001001001001001 step 55 001001001001001001001001001001 step 56 001001001011001001001001001001 step 57 001001001110001001001001001001 step 58 001001001101001001001001001001 step 59 001001001001001001001001001001 step 60 001001001001011001001001001001 step 61 001001001001110001001001001001 step 62 001001001001101001001001001001 step 63 001001001001001001001001001001 step 64 001001001001001011001001001001 step 65 001001001001001110001001001001 step 66 001001001001001101001001001001 step 67 001001001001001001001001001001 step 68 001001001001001001011001001001 step 69 001001001001001001110001001001 step 70 001001001001001001101001001001 step 71 001001001001001001001001001001 step 72 001001001001001001001011001001 step 73 001001001001001001001110001001 step 74 001001001001001001001101001001 step 75 001001001001001001001001001001 step 76 001001001001001001001001011001 step 77 001001001001001001001001110001 step 78 001001001001001001001001101001 step 79 001001001001001001001001001001 step 80 001001001001001001001001001011 step 81 001001001001001001001001001110 step 82 001001001001001001001001001101 step 83 001001001001001001001001001001 test 23: *** FAIL *************************** 2 steps failed SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFDEFHJKHJKLMNLMNPRSPRSTUV SIDE 111111222111222111222111222222 DIRECTION IIOIIOIIOIIOIIOIIOIIOIIOIIOIIO this fail O all fails O was hi 111111111111111111111111111111 rising ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ falling vvvvvvvvvvvvvvvvvvvvvvvvvvvvvv was lo 000000000000000000000000000000 total fails 23, total passes 0 space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn on comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit step 1 001001001001001001001001001001 step 2 110110110110110110110110110110 step 3 011110110110110110110110110110 step 4 001110110110110110110110110110 SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFDEFHJKHJKLMNLMNPRSPRSTUV SIDE 111111222111222111222111222222 DIRECTION IIOIIOIIOIIOIIOIIOIIOIIOIIOIIO changed: 1 0 step 5 100110110110110110110110110110 fail ^ step 6 110110110110110110110110110110 step 7 110011110110110110110110110110 step 8 110001110110110110110110110110 step 9 110101110110110110110110110110 step 10 110110110110110110110110110110 step 11 110110011110110110110110110110 step 12 110110001110110110110110110110 step 13 110110101110110110110110110110 step 14 110110110110110110110110110110 step 15 110110110011110110110110110110 step 16 110110110001110110110110110110 step 17 110110110101110110110110110110 step 18 110110110110110110110110110110 step 19 110110110110011110110110110110 step 20 110110110110001110110110110110 step 21 110110110110101110110110110110 step 22 110110110110110110110110110110 step 23 110110110110110011110110110110 step 24 110110110110110001110110110110 step 25 110110110110110101110110110110 step 26 110110110110110110110110110110 step 27 110110110110110110011110110110 step 28 110110110110110110001110110110 step 29 110110110110110110101110110110 step 30 110110110110110110110110110110 step 31 110110110110110110110011110110 step 32 110110110110110110110001110110 step 33 110110110110110110110101110110 step 34 110110110110110110110110110110 step 35 110110110110110110110110011110 step 36 110110110110110110110110001110 step 37 110110110110110110110110101110 step 38 110110110110110110110110110110 step 39 110110110110110110110110110011 step 40 110110110110110110110110110001 step 41 110110110110110110110110110101 step 42 110110110110110110110110110110 step 43 001001001001001001001001001001 step 44 011001001001001001001001001001 step 45 110001001001001001001001001001 SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFDEFHJKHJKLMNLMNPRSPRSTUV SIDE 111111222111222111222111222222 DIRECTION IIOIIOIIOIIOIIOIIOIIOIIOIIOIIO changed: 0 step 46 100001001001001001001001001001 fail ^ step 47 001001001001001001001001001001 step 48 001011001001001001001001001001 step 49 001110001001001001001001001001 step 50 001101001001001001001001001001 step 51 001001001001001001001001001001 step 52 001001011001001001001001001001 step 53 001001110001001001001001001001 step 54 001001101001001001001001001001 step 55 001001001001001001001001001001 step 56 001001001011001001001001001001 step 57 001001001110001001001001001001 step 58 001001001101001001001001001001 step 59 001001001001001001001001001001 step 60 001001001001011001001001001001 step 61 001001001001110001001001001001 step 62 001001001001101001001001001001 step 63 001001001001001001001001001001 step 64 001001001001001011001001001001 step 65 001001001001001110001001001001 step 66 001001001001001101001001001001 step 67 001001001001001001001001001001 step 68 001001001001001001011001001001 step 69 001001001001001001110001001001 step 70 001001001001001001101001001001 step 71 001001001001001001001001001001 step 72 001001001001001001001011001001 step 73 001001001001001001001110001001 step 74 001001001001001001001101001001 step 75 001001001001001001001001001001 step 76 001001001001001001001001011001 step 77 001001001001001001001001110001 step 78 001001001001001001001001101001 step 79 001001001001001001001001001001 step 80 001001001001001001001001001011 step 81 001001001001001001001001001110 step 82 001001001001001001001001001101 step 83 001001001001001001001001001001 test 24: *** FAIL *************************** 2 steps failed SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFDEFHJKHJKLMNLMNPRSPRSTUV SIDE 111111222111222111222111222222 DIRECTION IIOIIOIIOIIOIIOIIOIIOIIOIIOIIO this fail O all fails O was hi 111111111111111111111111111111 rising ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ falling vvvvvvvvvvvvvvvvvvvvvvvvvvvvvv was lo 000000000000000000000000000000 total fails 24, total passes 0 space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn on comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFDEFHJKHJKLMNLMNPRSPRSTUV SIDE 111111222111222111222111222222 DIRECTION IIOIIOIIOIIOIIOIIOIIOIIOIIOIIO all fails O was lo 000000000000000000000000000000 falling vvvvvvvvvvvvvvvvvvvvvvvvvvvvvv rising ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ was hi 111111111111111111111111111111 total fails 24, total passes 0 Main menu Mon Jul 10 11:00:11 2017 test file is: tests\m113.tst delay is: 0 trigger is: 1 1 read test file 2 set test delay 3 set test trigger 4 run test 5 output loading test 8 diags 9 exit Enter test file name? trying to open test file: tests\m220.tst reading test file: tests\m220.tst comment: M220 PCB REV ? SCHEMATIC REV C MAJOR REGISTERS comment: pins: PINS pins: 1 I BE2 E12-13 (ADD 01) BE2 TO ADDER3 A1 pins: 2 I BH2 E16-3 E12-3 AC ENABLE AC2 TO ADDER2 A2 AC3 TO ADDER3 A1 pins: 3 I BJ2 E16-5 E12-5 AC-N ENABLE AC2-N TO ADDER2 A2 AC3-N TO ADDER3 A1 pins: 4 I BF1 E16-10 E12-10 MQ ENABLE MQ2 TO ADDER2 A2 MQ3 TO ADDER3 A1 pins: 5 I BH1 E16-9 MQ2 (AND) ADDER2 A2 ADDER3 A1 pins: 6 I BN2 E12-9 MQ3 ADDER2 A2 ADDER3 A1 pins: 7 I BC1 E14-1 E15-1 SR ENABLE SR2 TO ADDER2 A2 SR3 TO ADDER3 A1 pins: 8 I BE1 E14-13 SR2 (AND) ADDER2 A2 pins: 9 I BD2 E15-13 SR3 (AND) ADDER3 A1 pins: 10 I BF2 SC ENABLE SC2 TO ADDER2 A2 SC3 TO ADDER3 A1 pins: 11 I BD1 E14-2 SC2 (AND) ADDER2 A2 pins: 12 I BN1 E15-2 SC3 (AND) ADDER3 A1 pins: 13 I BL1 E14-5 E15-5 DATA ENABLE DATA2 TO ADDER2 A2 DATA3 TO ADDER3 A1 pins: 14 I BM2 E14-4 DATA2 (AND) ADDER2 A2 pins: 15 I BP2 E15-4 DATA3 (AND) ADDER3 A1 pins: 16 I BL2 E14-10 E15-10 IO ENABLE IO2 TO ADDER2 A2 IO3 TO ADDER3 A1 pins: 17 I BK1 E14-9 IO2 (AND) ADDER2 A2 pins: 18 I BM1 E15-9 IO3 (AND) ADDER3 A1 pins: 19 I BP1 E17-13 MA ENABLE MA2 TO ADDER2 B2 pins: 20 I BR2 E18-13 (MA3 ENABLE) MA3 TO ADDER3 B1 pins: 21 I BS2 E17-3 E18-3 PC ENABLE PC2 TO ADDER2 B2 PC3 TO ADDER3 B1 pins: 22 I BU2 E17-5 MEM ENABLE MEM2 TO ADDER2 B2 pins: 23 I BR1 E17-4 MEM2 (AND) ADDER2 B2 pins: 24 I BV1 E18-5 (MEM3 ENABLE) MA3 TO ADDER3 B1 pins: 25 I BV2 E18-4 MEM3 (AND) ADDER3 B1 pins: 26 I BT2 E17-10 E18-10 DATA ADDR EN DADDR2 TO ADDER2 B2 DADDR3 TO ADDER3 B1 pins: 27 I BS1 E17-9 DADDR2 (AND) ADDER2 B2 pins: 28 I BU1 E18-9 DADDR3 (AND) ADDER3 B1 pins: 29 I BJ1 E13-5 CO ADDER3 C0 pins: 30 O BK2 E13-10 C2 ADDER2 C2 pins: 31 O AE2 E13-12 ADDER2 ADDER2 SUM2 pins: 32 O AF1 E13-1 ADDER3 ADDER3 SUM1 pins: 33 I AA1 E3-13 E5-13 AND MB2 TO BUS2 MB3 TO BUS3 pins: 34 I AD2 E1-1 E2-5 SHIFT RIGHT ADDER1 TO BUS2 ADDER2 TO BUS3 pins: 35 I AD1 E1-9 E2-9 SHIFT RIGHT TWICE ADDER0 TO BUS2 ADDER1 TO BUS3 pins: 36 I AB1 E1-10 ADDER0 (AND) BUS2 pins: 37 I AC1 E1-13 E2-10 ADDER1 (AND) BUS2 (AND) BUS3 pins: 38 I AH2 E3-8 E1-1 ADDER4 (AND) BUS2 (AND) BUS3 pins: 39 I AJ2 E3-6 ADDER5 (AND) BUS3 pins: 40 I AE1 E1-2 E2-3 NO SHIFT ADDER2 TO BUS2 ADDER3 TO BUS3 pins: 41 I AF2 E1-5 E2-13 SHIFT LEFT ADDER3 TO BUS2 ADDER4 TO BUS3 pins: 42 I AH1 E3-8 E5-8 SHIFT LEFT TWICE ADDER4 TO BUS2 ADDER5 TO BUS3 pins: 43 I AB2 R,Q TT LINE SHIFT-N TTLINE TO BUS2 ADDER3 TO BUS3 pins: 44 I BB2 E6-1 (TTLINE) (AND) BUS2 pins: 45 O AJ1 E1-8 (BUS 2) pins: 46 O AK2 E2-8 (BUS 3) pins: 47 I AK1 E4-3 E4-11 (MA LOAD) pins: 48 O AM1 E4-6 (MA2 Q-N) pins: 49 O AM2 E4-5 (MA2 Q) pins: 50 O AL1 E4-8 (MA3 Q-N) pins: 51 O AL2 E4-9 (MA3 Q) pins: 52 I AN2 E4-3 E4-11 (PC LOAD) pins: 53 O AR2 E9-6 (PC2 Q-N) pins: 54 O AP1 E9-5 (PC2 Q) pins: 55 O AP2 E9-8 (PC3 Q-N) pins: 56 O AN1 E9-9 (PC3 Q) pins: 57 I AR1 E8-3 E8-11 (MB LOAD) pins: 58 O AU2 E11-6 (BUFFERED MB2 Q-N) pins: 59 O AT2 E11-8 (BUFFERED MB2 Q) pins: 60 O AS1 E7-8 (BUFFERED MB3 Q-N) pins: 61 O AS2 E7-6 (BUFFERED MB3 Q) pins: 62 I AU1 E10-3 E10-11 (AC LOAD) pins: 63 O BB1 E10-6 (AC2 Q-N) pins: 64 O BA1 E10-5 (AC2 Q) pins: 65 O AV2 E10-8 (AC3 Q-N) pins: 66 O AV1 E10-9 (AC3 Q) pins: direction: IIIIIIIIIIIIIIIIIIIIIIIIIIIIIOOOIIIIIIIIIIIIOOIOOOOIOOOOIOOOOIOOOO comment: ; all registers are unknown comment: ; turn on C0, TT LINE SHIFT-N (C2,ADDER2,ADDER3 to 111) comment: ; with no ENABLES, BUS2,BUS3 is 11 test 1: 00000000000000000000000000001111000000000010110XXXX0XXXX0XXXX0XXXX comment: ; comment: ; test all registers using SHIFT RIGHT TWICE path comment: ; comment: ; use SHIFT RIGHT TWICE, ADDER0, ADDER1 to setup BUS2,BUS3 test 2: 111 00 comment: ; set all registers to 00 test 3: 11010110101101011010 test 4: 0 0 0 0 comment: ; set all registers to 01 test 5: 110 01 test 6: 1 011 011 011 01 test 7: 0 0 0 0 comment: ; set all registers to 11 test 8: 100 11 test 9: 10101101011010110101 test 10: 0 0 0 0 comment: ; set all registers to 01 test 11: 110 01 test 12: 110 110 110 110 test 13: 0 0 0 0 comment: ; set all registers to 00 test 14: 111 00 test 15: 11010110101101011010 test 16: 0 0 0 0 comment: ; remove SHIFT RIGHT TWICE, ADDER0, ADDER1 test 17: 000 11 test 18: 000000000000000000000000000011110000000000101101010010100101001010 comment: ; comment: ; same tests, but use SHIFT LEFT TWICE path comment: ; comment: ; use SHIFT LEFT TWICE, ADDER4, ADDER5 to setup BUS2,BUS3 test 19: 11 1 00 comment: ; set all registers to 00 test 20: 11010110101101011010 test 21: 0 0 0 0 comment: ; set all registers to 01 test 22: 10 1 01 test 23: 1 011 011 011 01 test 24: 0 0 0 0 comment: ; set all registers to 11 test 25: 00 1 11 test 26: 10101101011010110101 test 27: 0 0 0 0 comment: ; set all registers to 01 test 28: 10 1 01 test 29: 110 110 110 110 test 30: 0 0 0 0 comment: ; set all registers to 00 test 31: 11 1 00 test 32: 11010110101101011010 test 33: 0 0 0 0 comment: ; remove SHIFT LEFT TWICE, ADDER4, ADDER5 test 34: 00 0 11 test 35: 000000000000000000000000000011110000000000101101010010100101001010 comment: ; comment: ; change each register individually (only one bit changes per strobe) comment: ; comment: ; use SHIFT RIGHT TWICE, ADDER0, ADDER1 to setup BUS2,BUS3 comment: ; set each register to 00 test 36: 111 00 test 37: 1 test 38: 0 test 39: 1 test 40: 0 test 41: 1 test 42: 0 test 43: 1 test 44: 0 comment: ; set each register to 01 test 45: 110 01 test 46: 1 01 test 47: 0 test 48: 1 01 test 49: 0 test 50: 1 01 test 51: 0 test 52: 1 01 test 53: 0 comment: ; set each register to 11 test 54: 100 11 test 55: 101 test 56: 0 test 57: 101 test 58: 0 test 59: 101 test 60: 0 test 61: 101 test 62: 0 comment: ; set each register to 10 test 63: 101 10 test 64: 1 10 test 65: 0 test 66: 1 10 test 67: 0 test 68: 1 10 test 69: 0 test 70: 1 10 test 71: 0 comment: ; set each register to 00 test 72: 111 00 test 73: 110 test 74: 0 test 75: 110 test 76: 0 test 77: 110 test 78: 0 test 79: 110 test 80: 0 comment: ; all registers are 00 test 81: 000000000000000000000000000011110011100000100001010010100101001010 comment: ; comment: ; with all registers 00; change each register individually to 00,01,10,11 comment: ; comment: ; use SHIFT RIGHT TWICE, ADDER0, ADDER1 to setup BUS2,BUS3 comment: ; change each regster to 00 and back to 00 test 82: 111 1 test 83: 0 test 84: 111 1 test 85: 0 test 86: 111 1 test 87: 0 test 88: 111 1 test 89: 0 comment: ; change each register to 01 and back to 00 test 90: 110 01 test 91: 1 01 test 92: 0 test 93: 111 00 test 94: 1 10 test 95: 0 test 96: 110 01 test 97: 1 01 test 98: 0 test 99: 111 00 test 100: 1 10 test 101: 0 test 102: 110 01 test 103: 1 01 test 104: 0 test 105: 111 00 test 106: 1 10 test 107: 0 test 108: 110 01 test 109: 1 01 test 110: 0 test 111: 111 00 test 112: 1 10 test 113: 0 comment: ; change each register to 10 and back to 00 test 114: 101 10 test 115: 101 test 116: 0 test 117: 111 00 test 118: 110 test 119: 0 test 120: 101 10 test 121: 101 test 122: 0 test 123: 111 00 test 124: 110 test 125: 0 test 126: 101 10 test 127: 101 test 128: 0 test 129: 111 00 test 130: 110 test 131: 0 test 132: 101 10 test 133: 101 test 134: 0 test 135: 111 00 test 136: 110 test 137: 0 comment: ; change each register to 11 and back to 00 test 138: 100 11 test 139: 1110101 test 140: 0 test 141: 111 00 test 142: 11010 test 143: 0 test 144: 100 11 test 145: 10101 test 146: 0 test 147: 111 00 test 148: 11010 test 149: 0 test 150: 100 11 test 151: 10101 test 152: 0 test 153: 111 00 test 154: 11010 test 155: 0 test 156: 100 11 test 157: 10101 test 158: 0 test 159: 111 00 test 160: 11010 test 161: 0 comment: ; all registers are 00 test 162: 000000000000000000000000000011110011100000100001010010100101001010 comment: ; comment: ; with all registers 01; change each register individually to 00,01,10,11 comment: ; comment: ; use SHIFT RIGHT TWICE, ADDER0, ADDER1 to setup BUS2,BUS3 comment: ; set all registers to 01 test 163: 110 01 test 164: 11001110011100111001 test 165: 0 0 0 0 comment: ; all registers are 01 test 166: 000000000000000000000000000011110011000000100101001010010100101001 comment: ; use SHIFT RIGHT TWICE, ADDER0, ADDER1 to setup BUS2,BUS3 comment: ; set each register to 00 and back to 01 test 167: 111 00 test 168: 1 10 test 169: 0 test 170: 110 01 test 171: 1 01 test 172: 0 test 173: 111 00 test 174: 1 10 test 175: 0 test 176: 110 01 test 177: 1 01 test 178: 0 test 179: 111 00 test 180: 1 10 test 181: 0 test 182: 110 01 test 183: 1 01 test 184: 0 test 185: 111 00 test 186: 1 10 test 187: 0 test 188: 110 01 test 189: 1 01 test 190: 0 comment: ; set each register to 01 and back to 01 test 191: 1 test 192: 0 test 193: 1 test 194: 0 test 195: 1 test 196: 0 test 197: 1 test 198: 0 comment: ; set each register to 10 and back to 01 test 199: 101 10 test 200: 10110 test 201: 0 test 202: 110 01 test 203: 11001 test 204: 0 test 205: 101 10 test 206: 10110 test 207: 0 test 208: 110 01 test 209: 11001 test 210: 0 test 211: 101 10 test 212: 10110 test 213: 0 test 214: 110 01 test 215: 11001 test 216: 0 test 217: 101 10 test 218: 10110 test 219: 0 test 220: 110 01 test 221: 11001 test 222: 0 comment: ; set each register to 11 and back to 01 test 223: 100 11 test 224: 101 test 225: 0 test 226: 110 01 test 227: 110 test 228: 0 test 229: 100 11 test 230: 101 test 231: 0 test 232: 110 01 test 233: 110 test 234: 0 test 235: 100 11 test 236: 101 test 237: 0 test 238: 110 01 test 239: 110 test 240: 0 test 241: 100 11 test 242: 101 test 243: 0 test 244: 110 01 test 245: 110 test 246: 0 comment: ; all registers are 01 test 247: 000000000000000000000000000011110011000000100101001010010100101001 comment: ; comment: ; with all registers 10; change each register individually to 00,01,10,11 comment: ; comment: ; use SHIFT RIGHT TWICE, ADDER0, ADDER1 to setup BUS2,BUS3 comment: ; set all registers to 10 test 248: 101 10 test 249: 10110101101011010110 test 250: 0 0 0 0 comment: ; all registers are 10 test 251: 000000000000000000000000000011110010100000101000110001100011000110 comment: ; use SHIFT RIGHT TWICE, ADDER0, ADDER1 to setup BUS2,BUS3 comment: ; set each register to 00 and back to 10 test 252: 111 00 test 253: 110 test 254: 0 test 255: 101 10 test 256: 101 test 257: 0 test 258: 111 00 test 259: 110 test 260: 0 test 261: 101 10 test 262: 101 test 263: 0 test 264: 111 00 test 265: 110 test 266: 0 test 267: 101 10 test 268: 101 test 269: 0 test 270: 111 00 test 271: 110 test 272: 0 test 273: 101 10 test 274: 101 test 275: 0 comment: ; set each register to 01 and back to 10 test 276: 110 01 test 277: 11001 test 278: 0 test 279: 101 10 test 280: 10110 test 281: 0 test 282: 110 01 test 283: 11001 test 284: 0 test 285: 101 10 test 286: 10110 test 287: 0 test 288: 110 01 test 289: 11001 test 290: 0 test 291: 101 10 test 292: 10110 test 293: 0 test 294: 110 01 test 295: 11001 test 296: 0 test 297: 101 10 test 298: 10110 test 299: 0 comment: ; set each register to 10 and back to 10 test 300: 101 10 test 301: 1 test 302: 0 test 303: 1 test 304: 0 test 305: 1 test 306: 0 test 307: 1 test 308: 0 comment: ; set each register to 11 and back to 10 test 309: 100 11 test 310: 1 01 test 311: 0 test 312: 101 10 test 313: 1 10 test 314: 0 test 315: 100 11 test 316: 1 01 test 317: 0 test 318: 101 10 test 319: 1 10 test 320: 0 test 321: 100 11 test 322: 1 01 test 323: 0 test 324: 101 10 test 325: 1 10 test 326: 0 test 327: 100 11 test 328: 1 01 test 329: 0 test 330: 101 10 test 331: 1 10 test 332: 0 comment: ; all registers are 10 test 333: 000000000000000000000000000011110010000000101100110001100011000110 comment: ; comment: ; with all registers 11; change each register individually to 00,01,10,11 comment: ; comment: ; use SHIFT RIGHT TWICE, ADDER0, ADDER1 to setup BUS2,BUS3 comment: ; set all registers to 11 test 334: 100 11 test 335: 10101101011010110101 test 336: 0 0 0 0 comment: ; all registers are 11 test 337: 000000000000000000000000000011110010000000101100101001010010100101 comment: ; use SHIFT RIGHT TWICE, ADDER0, ADDER1 to setup BUS2,BUS3 comment: ; set each register to 00 and back to 11 test 338: 111 00 test 339: 11010 test 340: 0 test 341: 100 11 test 342: 10101 test 343: 0 test 344: 111 00 test 345: 11010 test 346: 0 test 347: 100 11 test 348: 10101 test 349: 0 test 350: 111 00 test 351: 11010 test 352: 0 test 353: 100 11 test 354: 10101 test 355: 0 test 356: 111 00 test 357: 11010 test 358: 0 test 359: 100 11 test 360: 10101 test 361: 0 comment: ; set each register to 01 and back to 11 test 362: 110 01 test 363: 110 test 364: 0 test 365: 100 11 test 366: 101 test 367: 0 test 368: 110 01 test 369: 110 test 370: 0 test 371: 100 11 test 372: 101 test 373: 0 test 374: 110 01 test 375: 110 test 376: 0 test 377: 100 11 test 378: 101 test 379: 0 test 380: 110 01 test 381: 110 test 382: 0 test 383: 100 11 test 384: 101 test 385: 0 comment: ; set each register to 10 and back to 11 test 386: 101 10 test 387: 1 10 test 388: 0 test 389: 100 11 test 390: 1 01 test 391: 0 test 392: 101 10 test 393: 1 10 test 394: 0 test 395: 100 11 test 396: 1 01 test 397: 0 test 398: 101 10 test 399: 1 10 test 400: 0 test 401: 100 11 test 402: 1 01 test 403: 0 test 404: 101 10 test 405: 1 10 test 406: 0 test 407: 100 11 test 408: 1 01 test 409: 0 comment: ; set each register to 11 and back to 11 test 410: 100 11 test 411: 1 test 412: 0 test 413: 100 1 test 414: 0 test 415: 100 1 test 416: 0 test 417: 100 1 test 418: 0 comment: ; all registers are 11 test 419: 000000000000000000000000000011110010000000101100101001010010100101 comment: ; use SHIFT RIGHT TWICE, ADDER0, ADDER1 to setup BUS2,BUS3 comment: ; set registers to 00 test 420: 111 00 test 421: 11010110101101011010 test 422: 0 0 0 0 comment: ; all registers are 00 test 423: 000000000000000000000000000011110011100000100001010010100101001010 comment: ; comment: ; now test each register using SHIFT LEFT TWICE/ADDER4/ADDER5 comment: comment: ; disable SHIFT RIGHT TWICE, ADDER0, ADDER1 test 424: 000 11 comment: ; use SHIFT LEFT TWICE, ADDER4, ADDER5 to set BUS2,BUS3 to 00 test 425: 11 1 00 comment: ; all registers are 00 test 426: 000000000000000000000000000011110000011001100001010010100101001010 comment: ; use SHIFT LEFT TWICE, ADDER4, ADDER5 to set BUS2,BUS3 to 00 comment: ; set each register to 00 test 427: 11 1 001 test 428: 0 test 429: 00 1 test 430: 0 test 431: 00 1 test 432: 0 test 433: 00 1 test 434: 0 test 435: 00 comment: ; set each register to 01 test 436: 10 1 01 test 437: 011 01 test 438: 0 test 439: 01 1 01 test 440: 0 test 441: 01 1 01 test 442: 0 test 443: 01 1 01 test 444: 0 comment: ; set each register to 11 test 445: 00 1 11 test 446: 11101 test 447: 0 test 448: 11 101 test 449: 0 test 450: 11 101 test 451: 0 test 452: 11 101 test 453: 0 comment: ; set each register to 10 test 454: 01 1 10 test 455: 101 10 test 456: 0 test 457: 10 1 10 test 458: 0 test 459: 10 1 10 test 460: 0 test 461: 10 1 10 test 462: 0 comment: ; set each register to 00 test 463: 11 1 00110 test 464: 0 test 465: 00 110 test 466: 0 test 467: 00 110 test 468: 0 test 469: 00 110 test 470: 0 test 471: 00 comment: ; all registers are 00 test 472: 000000000000000000000000000011110000011001100001010010100101001010 comment: ; comment: ; test AND/MB path comment: ; comment: ; set registers MA,PC,MB,AC to 00,00,11,00 comment: ; use SHIFT LEFT TWICE, ADDER4, ADDER5 to set BUS2,BUS3 to 00 test 473: 00 1 11 test 474: 10101 test 475: 0 test 476: 11 1 00 test 477: 1101011010 11010 test 478: 0 0 0 comment: ; use AND enable to setup BUS2,BUS3 to 11 comment: ; set MA,PC,xx,AC to 11 and back to 00 test 479: 11 0 11 test 480: 1 11 test 481: 10101 test 482: 0 test 483: 0 11 test 484: 11 1 00 test 485: 11010 test 486: 0 test 487: 11 0 11 test 488: 1 11 test 489: 10101 test 490: 0 test 491: 0 test 492: 11 1 00 test 493: 11010 test 494: 0 test 495: 11 0 11 test 496: 1 11 test 497: 1 test 498: 0 test 499: 10101 test 500: 0 test 501: 0 test 502: 11 1 00 test 503: 11010 test 504: 0 test 505: 11 0 11 comment: ; set registers MA,PC,MB,AC to 01,01,10,01 comment: ; use SHIFT LEFT TWICE, ADDER4, ADDER5 to set BUS2,BUS3 to 01 test 506: 01 1 10 test 507: 10110 test 508: 0 test 509: 10 1 01 test 510: 1100111001 11001 test 511: 0 0 0 comment: ; use AND enable to setup BUS2,BUS3 to 10 comment: ; set MA,PC,xx,AC to 10 and back to 01 test 512: 01 0 11 test 513: 1 10 test 514: 10110 test 515: 0 test 516: 0 11 test 517: 10 1 01 test 518: 11001 test 519: 0 test 520: 10 0 11 test 521: 1 10 test 522: 10110 test 523: 0 test 524: 0 11 test 525: 10 1 01 test 526: 11001 test 527: 0 test 528: 10 0 11 test 529: 1 10 test 530: 1 test 531: 0 test 532: 10110 test 533: 0 test 534: 0 11 test 535: 10 1 01 test 536: 11001 test 537: 0 test 538: 10 0 11 comment: ; set registers MA,PC,MB,AC to 10,10,01,10 comment: ; use SHIFT LEFT TWICE, ADDER4, ADDER5 to set BUS2,BUS3 to 01 test 539: 10 1 01 test 540: 11001 test 541: 0 test 542: 01 1 10 test 543: 1011010110 10110 test 544: 0 0 0 comment: ; use AND enable to setup BUS2,BUS3 to 01 comment: ; set MA,PC,xx,AC to 01 and back to 10 test 545: 01 0 11 test 546: 1 01 test 547: 11001 test 548: 0 test 549: 0 11 test 550: 01 1 10 test 551: 10110 test 552: 0 test 553: 01 0 11 test 554: 1 01 test 555: 11001 test 556: 0 test 557: 0 11 test 558: 01 1 10 test 559: 10110 test 560: 0 test 561: 01 0 11 test 562: 1 01 test 563: 1 test 564: 0 test 565: 11001 test 566: 0 test 567: 0 11 test 568: 01 1 10 test 569: 10110 test 570: 0 test 571: 01 0 11 comment: ; set registers MA,PC,MB,AC to 11,11,00,11 comment: ; use SHIFT LEFT TWICE, ADDER4, ADDER5 to set BUS2,BUS3 to 01 test 572: 11 1 00 test 573: 11010 test 574: 0 test 575: 00 1 11 test 576: 1010110101 10101 test 577: 0 0 0 comment: ; use AND enable to setup BUS2,BUS3 to 00 comment: ; set MA,PC,xx,AC to 00 and back to 11 test 578: 00 0 11 test 579: 1 00 test 580: 11010 test 581: 0 test 582: 0 11 test 583: 00 1 11 test 584: 10101 test 585: 0 test 586: 00 0 11 test 587: 1 00 test 588: 11010 test 589: 0 test 590: 0 11 test 591: 00 1 11 test 592: 10101 test 593: 0 test 594: 00 0 11 test 595: 1 00 test 596: 1 test 597: 0 test 598: 11010 test 599: 0 test 600: 0 11 test 601: 00 1 11 test 602: 10101 test 603: 0 test 604: 00 0 11 comment: comment: ; using SHIFT LEFT TWICE,ADDER4,ADDER5; set all registers to 00 test 605: 11 1 00 test 606: 11010110101101011010 test 607: 0 0 0 0 comment: ; disable SHIFT LEFT TWICE, ADDER4, ADDER5 test 608: 00 0 11 comment: ; all registers are 00 test 609: 000000000000000000000000000011110000000000101101010010100101001010 comment: ; comment: ; initial ADDER tests comment: ; comment: ; with no ENABLES, C0 HI, should have ADDER2,ADDER3,C2 test 610: 1111 comment: ; enable MQ ENABLE; toggle MQ2, MQ3 to ADDER2, ADDER3 test 611: 100 1111 test 612: 101 1110 test 613: 111 1100 test 614: 110 1101 test 615: 100 1111 comment: ; disable MQ ENABLE test 616: 0 1111 comment: ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; comment: ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; comment: ; need more ENABLE tests to isolate AND/OR errors comment: ; (should set all regsters to 11) comment: ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; comment: ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; comment: ; enable NO SHIFT to connect ADDER2,ADDER3 to BUS2,BUS3 test 617: 111 1100 1 11 test 618: 110 1101 1 10 test 619: 101 1110 1 01 test 620: 100 1111 1 00 comment: ; disable NO SHIFT test 621: 100 1111 0 11 comment: ; enable SHIFT RIGHT to connect ADDER1,ADDER2 to BUS2,BUS3 test 622: 100 1111 1 1 00 test 623: 101 1110 1 test 624: 110 1101 1 1 01 test 625: 111 1100 1 test 626: 111 1100 1 0 11 test 627: 110 1101 1 test 628: 101 1110 1 0 10 test 629: 100 1111 1 comment: ; disable SHIFT RIGHT test 630: 100 1111 0 11 comment: ; enable SHIFT RIGHT TWICE to connect ADDER0, ADDER1 to BUS2,BUS3 test 631: 111 00 test 632: 110 01 test 633: 101 10 test 634: 100 11 comment: ; disable SHIFT RIGHT TWICE test 635: 0 11 comment: ;enable SHIFT LEFT TWICE to connect ADDER4,ADDER5 to BUS2,BUS3 test 636: 11 1 00 test 637: 10 1 01 test 638: 01 1 10 test 639: 00 1 11 comment: ; disable SHIFT LEFT TWICE test 640: 0 11 comment: ; enable SHIFT LEFT to connect ADDER3,ADDER4 to BUS2,BUS3 test 641: 100 1111 1 1 00 test 642: 110 1101 1 test 643: 111 1100 1 1 10 test 644: 101 1110 1 test 645: 101 1110 0 1 11 test 646: 111 1100 1 test 647: 110 1101 0 1 01 test 648: 100 1111 1 comment: ; disable SHIFT LEFT test 649: 100 1111 0 11 test 650: 100 1111 1 comment: ; enable TT LINE SHIFT-N to connect TTLINE,ADDER3 to BUS2,BUS3 test 651: 100 1111 0100 test 652: 110 1101 0 test 653: 111 1100 0101 test 654: 101 1110 0 test 655: 101 1110 0011 test 656: 111 1100 0 test 657: 110 1101 0010 test 658: 100 1111 0 comment: ; disable TT LINE SHIFT-N test 659: 1111 1 11 comment: ; disable MQ ENABLE test 660: 0 test 661: 000000000000000000000000000011110000000000101101010010100101001010 comment: ; using SHIFT LEFT TWICE,ADDER4,ADDER5; set all registers to 00 test 662: 11 1 00 test 663: 11010110101101011010 test 664: 0 0 0 0 comment: ; disable SHIFT LEFT TWICE, ADDER4, ADDER5 test 665: 00 0 11 comment: ; all registers are 00 test 666: 000000000000000000000000000011110000000000101101010010100101001010 comment: ; set all registers to 00 test 667: 11 1 00 test 668: 11010110101101011010 test 669: 0 0 0 0 comment: ; disable SHIFT LEFT TWICE, ADDER4, ADDER5 test 670: 00 0 11 comment: ; all registers are 00 test 671: 000000000000000000000000000011110000000000101101010010100101001010 comment: ; use NO SHIFT to route ADDER2,ADDER3 to BUS2,BUS3 comment: ; toggle C0 test 672: 1111 1 00 test 673: 0110 1 01 test 674: 1111 1 00 comment: ; enable (add 01); toggle C0 test 675: 1 1110 1 01 test 676: 1 0101 1 10 test 677: 1 1110 1 01 test 678: 0 1111 1 00 comment: ; enable MQ ENABLE; toggle C0, MQ2, MQ3 test 679: 100 1111 1 00 test 680: 100 0110 1 01 test 681: 100 1111 1 00 test 682: 101 1110 1 01 test 683: 101 0101 1 10 test 684: 101 1110 1 01 test 685: 110 1101 1 10 test 686: 110 0100 1 11 test 687: 110 1101 1 10 test 688: 111 1100 1 11 test 689: 111 0011 1 00 test 690: 111 1100 1 11 test 691: 000 1111 1 00 comment: ; enable SR ENABLE; toggle C0, SR2, SR3 test 692: 100 1111 1 00 test 693: 100 0110 1 01 test 694: 100 1111 1 00 test 695: 101 1110 1 01 test 696: 101 0101 1 10 test 697: 101 1110 1 01 test 698: 110 1101 1 10 test 699: 110 0100 1 11 test 700: 110 1101 1 10 test 701: 111 1100 1 11 test 702: 111 0011 1 00 test 703: 111 1100 1 11 test 704: 000 1111 1 00 comment: ; enable SC ENABLE; toggel C0, SC2, SC3 test 705: 100 1111 1 00 test 706: 100 0110 1 01 test 707: 100 1111 1 00 test 708: 101 1110 1 01 test 709: 101 0101 1 10 test 710: 101 1110 1 01 test 711: 110 1101 1 10 test 712: 110 0100 1 11 test 713: 110 1101 1 10 test 714: 111 1100 1 11 test 715: 111 0011 1 00 test 716: 111 1100 1 11 test 717: 000 1111 1 00 comment: ; enable DATA ENABLE; toggle C0, DATA2, DATA3 test 718: 100 1111 1 00 test 719: 100 0110 1 01 test 720: 100 1111 1 00 test 721: 101 1110 1 01 test 722: 101 0101 1 10 test 723: 101 1110 1 01 test 724: 110 1101 1 10 test 725: 110 0100 1 11 test 726: 110 1101 1 10 test 727: 111 1100 1 11 test 728: 111 0011 1 00 test 729: 111 1100 1 11 test 730: 000 1111 1 00 comment: ; enable IO ENABLE; toggle C0, IO2, IO3 test 731: 100 1111 1 00 test 732: 100 0110 1 01 test 733: 100 1111 1 00 test 734: 101 1110 1 01 test 735: 101 0101 1 10 test 736: 101 1110 1 01 test 737: 110 1101 1 10 test 738: 110 0100 1 11 test 739: 110 1101 1 10 test 740: 111 1100 1 11 test 741: 111 0011 1 00 test 742: 111 1100 1 11 test 743: 000 1111 1 00 comment: ; enable MEM ENABLE; toggle C0, MEM2 test 744: 10 1111 1 00 test 745: 10 0110 1 01 test 746: 10 1111 1 00 test 747: 11 1101 1 10 test 748: 11 0100 1 11 test 749: 11 1101 1 10 test 750: 00 1111 1 00 comment: ; enable (MEM3 ENABLE); toggle C0, MEM3 test 751: 10 1111 1 00 test 752: 10 0110 1 01 test 753: 10 1111 1 00 test 754: 11 1110 1 01 test 755: 11 0101 1 10 test 756: 11 1110 1 01 test 757: 00 1111 1 00 comment: ; enable MEM ENABLE, (MEM3 ENABLE); toggle C0, MEM2, MEM3 test 758: 1010 1111 1 00 test 759: 1010 0110 1 01 test 760: 1010 1111 1 00 test 761: 1011 1110 1 01 test 762: 1011 0101 1 10 test 763: 1011 1110 1 01 test 764: 1110 1101 1 10 test 765: 1110 0100 1 11 test 766: 1110 1101 1 10 test 767: 1111 1100 1 11 test 768: 1111 0011 1 00 test 769: 1111 1100 1 11 test 770: 0000 1111 1 00 comment: ; enable DATA ADDR EN; toggle C0, DADDR2, DADDR3 test 771: 1001111 1 00 test 772: 1000110 1 01 test 773: 1001111 1 00 test 774: 1011110 1 01 test 775: 1010101 1 10 test 776: 1011110 1 01 test 777: 1101101 1 10 test 778: 1100100 1 11 test 779: 1101101 1 10 test 780: 1111100 1 11 test 781: 1110011 1 00 test 782: 1111100 1 11 test 783: 0001111 1 00 test 784: 000000000000000000000000000011110000000100100001010010100101001010 comment: ; turn on MQ2 (not enabled) test 785: 1 1111 1 00 comment: ; turn on MQ3 (not enabled) test 786: 1 1111 1 00 comment: ; turn on SR2 (not enabled) test 787: 1 1111 1 00 comment: ; turn on SR3 (not enabled) test 788: 1 1111 1 00 comment: ; turn on SC2 (not enabled) test 789: 1 1111 1 00 comment: ; turn on SC3 (not enabled) test 790: 1 1111 1 00 comment: ; turn on DATA2 (not enabled) test 791: 1 1111 1 00 comment: ; turn on DATA3 (not enabled) test 792: 1 1111 1 00 comment: ; turn on IO2 (not enabled) test 793: 1 1111 1 00 comment: ; turn on IO3 (not enabled) test 794: 1 1111 1 00 comment: ; turn on MEM2 (not enabled) test 795: 1 1111 1 00 comment: ; turn on MEM3 (not enabled) test 796: 1 1111 1 00 comment: ; turn on DADDR2 (not enabled) test 797: 1 1111 1 00 comment: ; turn on DADDR3 (not enabled) test 798: 11111 1 00 comment: ; turn on ADDER0 (not enabled) test 799: 1111 1 1 00 comment: ; turn on ADDER1 (not enabled) test 800: 1111 1 1 00 comment: ; turn on ADDER4 (not enabled) test 801: 1111 1 1 00 comment: ; turn on ADDER5 (not enabled) test 802: 1111 11 00 comment: ; turn on (TTLINE) (not enabled) test 803: 1111 1 100 comment: ; not enabled, signals hi test 804: 000011011011011011000010101111110001111100110001010010100101001010 comment: ; toggle C0 test 805: 1111 1 00 test 806: 0110 1 01 test 807: 1111 1 00 comment: ; enable (add 01); toggle C0 test 808: 1 1110 1 01 test 809: 1 0101 1 10 test 810: 1 1110 1 01 test 811: 0 1111 1 00 comment: ; enable MQ ENABLE; toggle C0, MQ2, MQ3 test 812: 100 1111 1 00 test 813: 100 0110 1 01 test 814: 100 1111 1 00 test 815: 101 1110 1 01 test 816: 101 0101 1 10 test 817: 101 1110 1 01 test 818: 110 1101 1 10 test 819: 110 0100 1 11 test 820: 110 1101 1 10 test 821: 111 1100 1 11 test 822: 111 0011 1 00 test 823: 111 1100 1 11 test 824: 0 1111 1 00 comment: ; enable SR ENABLE; toggle C0, SR2, SR3 test 825: 100 1111 1 00 test 826: 100 0110 1 01 test 827: 100 1111 1 00 test 828: 101 1110 1 01 test 829: 101 0101 1 10 test 830: 101 1110 1 01 test 831: 110 1101 1 10 test 832: 110 0100 1 11 test 833: 110 1101 1 10 test 834: 111 1100 1 11 test 835: 111 0011 1 00 test 836: 111 1100 1 11 test 837: 0 1111 1 00 comment: ; enable SC ENABLE; toggel C0, SC2, SC3 test 838: 100 1111 1 00 test 839: 100 0110 1 01 test 840: 100 1111 1 00 test 841: 101 1110 1 01 test 842: 101 0101 1 10 test 843: 101 1110 1 01 test 844: 110 1101 1 10 test 845: 110 0100 1 11 test 846: 110 1101 1 10 test 847: 111 1100 1 11 test 848: 111 0011 1 00 test 849: 111 1100 1 11 test 850: 0 1111 1 00 comment: ; enable DATA ENABLE; toggle C0, DATA2, DATA3 test 851: 100 1111 1 00 test 852: 100 0110 1 01 test 853: 100 1111 1 00 test 854: 101 1110 1 01 test 855: 101 0101 1 10 test 856: 101 1110 1 01 test 857: 110 1101 1 10 test 858: 110 0100 1 11 test 859: 110 1101 1 10 test 860: 111 1100 1 11 test 861: 111 0011 1 00 test 862: 111 1100 1 11 test 863: 0 1111 1 00 comment: ; enable IO ENABLE; toggle C0, IO2, IO3 test 864: 100 1111 1 00 test 865: 100 0110 1 01 test 866: 100 1111 1 00 test 867: 101 1110 1 01 test 868: 101 0101 1 10 test 869: 101 1110 1 01 test 870: 110 1101 1 10 test 871: 110 0100 1 11 test 872: 110 1101 1 10 test 873: 111 1100 1 11 test 874: 111 0011 1 00 test 875: 111 1100 1 11 test 876: 0 1111 1 00 comment: ; enable MEM ENABLE; toggle C0, MEM2 test 877: 10 1111 1 00 test 878: 10 0110 1 01 test 879: 10 1111 1 00 test 880: 11 1101 1 10 test 881: 11 0100 1 11 test 882: 11 1101 1 10 test 883: 0 1111 1 00 comment: ; enable (MEM3 ENABLE); toggle C0, MEM3 test 884: 10 1111 1 00 test 885: 10 0110 1 01 test 886: 10 1111 1 00 test 887: 11 1110 1 01 test 888: 11 0101 1 10 test 889: 11 1110 1 01 test 890: 0 1111 1 00 comment: ; enable MEM ENABLE, (MEM3 ENABLE); toggle C0, MEM2, MEM3 test 891: 1010 1111 1 00 test 892: 1010 0110 1 01 test 893: 1010 1111 1 00 test 894: 1011 1110 1 01 test 895: 1011 0101 1 10 test 896: 1011 1110 1 01 test 897: 1110 1101 1 10 test 898: 1110 0100 1 11 test 899: 1110 1101 1 10 test 900: 1111 1100 1 11 test 901: 1111 0011 1 00 test 902: 1111 1100 1 11 test 903: 0 0 1111 1 00 comment: ; enable DATA ADDR EN; toggle C0, DADDR2, DADDR3 test 904: 1001111 1 00 test 905: 1000110 1 01 test 906: 1001111 1 00 test 907: 1011110 1 01 test 908: 1010101 1 10 test 909: 1011110 1 01 test 910: 1101101 1 10 test 911: 1100100 1 11 test 912: 1101101 1 10 test 913: 1111100 1 11 test 914: 1110011 1 00 test 915: 1111100 1 11 test 916: 0 1111 1 00 comment: ; not enabled, signals hi test 917: 000011011011011011000010101111110011100100100001010010100101001010 comment: ; all registers are 00 test 918: 000000000000000000000000000011110000000000101101010010100101001010 comment: ; use SHIFT RIGHT TWICE, ADDER0, ADDER1 to setup BUS2,BUS3 comment: ; set registers MA,PC,MB,AC to 11,11,11,00 test 919: 100 11 test 920: 101011010110101 test 921: 0 0 0 test 922: 111 00 test 923: 11010 test 924: 0 test 925: 000 11 comment: ; use NO SHIFT to route ADDER2,ADDER3 to BUS2,BUS3 test 926: 1111 1 00 comment: ; enable AC ENABLE to ADDER2,ADDER3 test 927: 1 1111 1 00 test 928: 11010 test 929: 0 test 930: 11010 test 931: 0 test 932: 11010 test 933: 0 test 934: 1 test 935: 0 comment: ; disable AC ENABLE test 936: 0 1111 1 00 comment: ; enable AC ENABLE-N to ADDER2,ADDER3 test 937: 1 1100 1 11 test 938: 10101 test 939: 0 test 940: 10101 test 941: 0 test 942: 10101 test 943: 0 test 944: 1100 1 11 comment: ; note that ADDER2,ADDER3 and BUS2,BUS3 are the NEW values test 945: 1111 1 00 10101 test 946: 0 test 947: 1111 1 00 comment: ; note that ADDER2,ADDER3 and BUS2,BUS3 are the NEW values test 948: 1100 1 11 11010 test 949: 0 test 950: 1100 1 11 comment: ; note that ADDER2,ADDER3 and BUS2,BUS3 are the NEW values test 951: 1111 1 00 10101 test 952: 0 comment: ; disable AC ENABLE-N test 953: 0 1111 1 00 comment: ; disable NO SHIFT 0 11 comment: ; all registers are 11 test 954: 000000000000000000000000000011110000000000101100101001010010100101 comment: ; use SHIFT RIGHT TWICE, ADDER0, ADDER1 to setup BUS2,BUS3 comment: ; set registers MA,PC,MB,AC to 10,10,10,01 test 955: 101 10 test 956: 101101011010110 test 957: 0 0 0 test 958: 110 01 test 959: 11001 test 960: 0 test 961: 000 11 comment: ; use NO SHIFT to route ADDER2,ADDER3 to BUS2,BUS3 test 962: 1111 1 00 comment: ; enable AC ENABLE to ADDER2,ADDER3 test 963: 1 1110 1 01 test 964: 11001 test 965: 0 test 966: 11001 test 967: 0 test 968: 11001 test 969: 0 test 970: 1 test 971: 0 comment: ; disable AC ENABLE test 972: 0 1111 1 00 comment: ; enable AC ENABLE-N to ADDER2,ADDER3 test 973: 1 1101 1 10 test 974: 10110 test 975: 0 test 976: 10110 test 977: 0 test 978: 10110 test 979: 0 test 980: 1101 1 10 comment: ; note that ADDER2,ADDER3 and BUS2,BUS3 are the NEW values test 981: 1110 1 01 10110 test 982: 0 test 983: 1110 1 01 comment: ; note that ADDER2,ADDER3 and BUS2,BUS3 are the NEW values test 984: 1101 1 10 11001 test 985: 0 test 986: 1101 1 10 comment: ; note that ADDER2,ADDER3 and BUS2,BUS3 are the NEW values test 987: 1110 1 01 10110 comment: ; disable AC ENABLE-N test 988: 0 1111 1 00 comment: ; disable NO SHIFT 0 11 comment: ; all registers are 10 test 989: 000000000000000000000000000011110000000000101100110001100011000110 comment: ; use SHIFT RIGHT TWICE, ADDER0, ADDER1 to setup BUS2,BUS3 comment: ; set registers MA,PC,MB,AC to 01,01,01,10 test 990: 110 01 test 991: 110011100111001 test 992: 0 0 0 test 993: 101 10 test 994: 10110 test 995: 0 test 996: 000 11 comment: ; use NO SHIFT to route ADDER2,ADDER3 to BUS2,BUS3 test 997: 1111 1 00 comment: ; enable AC ENABLE to ADDER2,ADDER3 test 998: 1 1101 1 10 test 999: 10110 test 1000: 0 test 1001: 10110 test 1002: 0 test 1003: 10110 test 1004: 0 test 1005: 1 test 1006: 0 comment: ; disable AC ENABLE test 1007: 0 1111 1 00 comment: ; enable AC ENABLE-N to ADDER2,ADDER3 test 1008: 1 1110 1 01 test 1009: 11001 test 1010: 0 test 1011: 11001 test 1012: 0 test 1013: 11001 test 1014: 0 test 1015: 1110 1 01 comment: ; note that ADDER2,ADDER3 and BUS2,BUS3 are the NEW values test 1016: 1101 1 10 11001 test 1017: 0 test 1018: 1101 1 10 comment: ; note that ADDER2,ADDER3 and BUS2,BUS3 are the NEW values test 1019: 1110 1 01 10110 test 1020: 0 test 1021: 1110 1 01 comment: ; note that ADDER2,ADDER3 and BUS2,BUS3 are the NEW values test 1022: 1101 1 10 11001 comment: ; disable AC ENABLE-N test 1023: 0 1111 1 00 comment: ; disable NO SHIFT 0 11 comment: ; all registers are 01 test 1024: 000000000000000000000000000011110000000000101101001010010100101001 comment: ; use SHIFT RIGHT TWICE, ADDER0, ADDER1 to setup BUS2,BUS3 comment: ; set registers MA,PC,MB,AC to 00,00,00,11 test 1025: 111 00 test 1026: 110101101011010 test 1027: 0 0 0 test 1028: 100 11 test 1029: 10101 test 1030: 0 test 1031: 000 11 comment: ; use NO SHIFT to route ADDER2,ADDER3 to BUS2,BUS3 test 1032: 1111 1 00 comment: ; enable AC ENABLE to ADDER2,ADDER3 test 1033: 1 1100 1 11 test 1034: 10101 test 1035: 0 test 1036: 10101 test 1037: 0 test 1038: 10101 test 1039: 0 test 1040: 1 test 1041: 0 comment: ; disable AC ENABLE test 1042: 0 1111 1 00 comment: ; enable AC ENABLE-N to ADDER2,ADDER3 test 1043: 1 1111 1 00 test 1044: 11010 test 1045: 0 test 1046: 11010 test 1047: 0 test 1048: 11010 test 1049: 0 test 1050: 1111 1 00 comment: ; note that ADDER2,ADDER3 and BUS2,BUS3 are the NEW values test 1051: 1100 1 11 11010 test 1052: 0 test 1053: 1100 1 11 comment: ; note that ADDER2,ADDER3 and BUS2,BUS3 are the NEW values test 1054: 1111 1 00 10101 test 1055: 0 test 1056: 1111 1 00 comment: ; note that ADDER2,ADDER3 and BUS2,BUS3 are the NEW values test 1057: 1100 1 11 11010 test 1058: 0 comment: ; disable AC ENABLE-N test 1059: 0 1111 1 00 comment: ; disable NO SHIFT 0 11 comment: ; all registers are 00 test 1060: 000000000000000000000000000011110000000000101101010010100101001010 comment: ; comment: ; test MA ENABLES (they are separate) comment: ; comment: ; use SHIFT RIGHT TWICE, ADDER0, ADDER1 to setup BUS2,BUS3 comment: ; set registers MA,PC,MB,AC to 11,00,00,00 test 1061: 111 00 test 1062: 110101101011010 test 1063: 0 0 0 test 1064: 100 11 test 1065: 10101 test 1066: 0 comment: ; enable MA ENABLE/(MA3 ENABLE) to ADDER2/ADDER3 test 1067: 10 01 test 1068: 11 00 test 1069: 01 10 test 1070: 00 11 comment: ; set registers MA,PC,MB,AC to 01,10,10,10 test 1071: 101 10 test 1072: 101101011010110 test 1073: 0 0 0 test 1074: 110 01 test 1075: 11001 test 1076: 0 comment: ; enable MA ENABLE/(MA3 ENABLE) to ADDER2/ADDER3 test 1077: 10 11 test 1078: 11 10 test 1079: 01 10 test 1080: 00 11 comment: ; set registers MA,PC,MB,AC to 00,11,11,11 test 1081: 100 11 test 1082: 101011010110101 test 1083: 0 0 0 test 1084: 111 00 test 1085: 11010 test 1086: 0 comment: ; enable MA ENABLE/(MA3 ENABLE) to ADDER2/ADDER3 test 1087: 10 11 test 1088: 11 11 test 1089: 01 11 test 1090: 00 11 comment: ; set registers MA,PC,MB,AC to 10,01,01,01 test 1091: 110 01 test 1092: 110011100111001 test 1093: 0 0 0 test 1094: 101 10 test 1095: 10110 test 1096: 0 comment: ; enable MA ENABLE/(MA3 ENABLE) to ADDER2/ADDER3 test 1097: 10 01 test 1098: 11 01 test 1099: 01 11 test 1100: 00 11 comment: ; set registers MA,PC,MB,AC to 00,00,00,00 test 1101: 111 00 test 1102: 11010110101101011010 test 1103: 0 0 0 0 comment: ; disable SHIFT RIGHT TWICE/ADDER0/ADDER1 test 1104: 000 11 comment: ; all registers are 00 test 1105: 000000000000000000000000000011110000000000101101010010100101001010 comment: ; comment: ; test PC ENABLE comment: ; comment: ; use SHIFT RIGHT TWICE, ADDER0, ADDER1 to setup BUS2,BUS3 comment: ; set registers MA,PC,MB,AC to 00,11,00,00 test 1106: 111 00 test 1107: 11010 1101011010 test 1108: 0 0 0 test 1109: 100 11 test 1110: 10101 test 1111: 0 comment: ; enable PC ENABLE to ADDER2/ADDER3 test 1112: 1 00 test 1113: 0 11 comment: ; set registers MA,PC,MB,AC to 10,01,10,10 test 1114: 101 10 test 1115: 10110 1011010110 test 1116: 0 0 0 test 1117: 110 01 test 1118: 11001 test 1119: 0 comment: ; enable PC ENABLE to ADDER2/ADDER3 test 1120: 1 10 test 1121: 0 11 comment: ; set registers MA,PC,MB,AC to 11,00,11,11 test 1122: 100 11 test 1123: 10101 1010110101 test 1124: 0 0 0 test 1125: 111 00 test 1126: 11010 test 1127: 0 comment: ; enable PC ENABLE to ADDER2/ADDER3 test 1128: 1 11 test 1129: 0 11 comment: ; set registers MA,PC,MB,AC to 01,10,01,01 test 1130: 110 01 test 1131: 11001 1100111001 test 1132: 0 0 0 test 1133: 101 10 test 1134: 10110 test 1135: 0 comment: ; enable PC ENABLE to ADDER2/ADDER3 test 1136: 1 01 test 1137: 0 11 comment: ; set registers MA,PC,MB,AC to 00,00,00,00 test 1138: 111 00 test 1139: 11010110101101011010 test 1140: 0 0 0 0 comment: ; disable SHIFT RIGHT TWICE/ADDER0/ADDER1 test 1141: 000 11 comment: ; all registers are 00 test 1142: 000000000000000000000000000011110000000000101101010010100101001010 comment: ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; comment: ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; comment: ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; comment: ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; comment: ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; comment: ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; comment: ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; comment: ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; comment: ; comment: ; still need comment: ; comment: ; more adder tests comment: ; comment: ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; comment: ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; comment: ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; comment: ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; comment: ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; comment: ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; comment: ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; comment: ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; end: END summary column 1: offset 2, mask 0x0040 column 2: offset 3, mask 0x0001 column 3: offset 3, mask 0x0002 column 4: offset 2, mask 0x0100 column 5: offset 3, mask 0x8000 column 6: offset 3, mask 0x0020 column 7: offset 2, mask 0x0800 column 8: offset 2, mask 0x0200 column 9: offset 2, mask 0x0020 column 10: offset 2, mask 0x0080 column 11: offset 2, mask 0x0400 column 12: offset 3, mask 0x0400 column 13: offset 3, mask 0x1000 column 14: offset 3, mask 0x0010 column 15: offset 3, mask 0x0040 column 16: offset 3, mask 0x0008 column 17: offset 3, mask 0x2000 column 18: offset 3, mask 0x0800 column 19: offset 3, mask 0x0200 column 20: offset 3, mask 0x0080 column 21: offset 4, mask 0x0001 column 22: offset 4, mask 0x0004 column 23: offset 3, mask 0x0100 column 24: offset 4, mask 0x1000 column 25: offset 4, mask 0x0008 column 26: offset 4, mask 0x0002 column 27: offset 4, mask 0x8000 column 28: offset 4, mask 0x2000 column 29: offset 3, mask 0x4000 column 30: offset 3, mask 0x0004 column 31: offset 0, mask 0x0008 column 32: offset 0, mask 0x0400 column 33: offset 0, mask 0x8000 column 34: offset 0, mask 0x0010 column 35: offset 0, mask 0x1000 column 36: offset 0, mask 0x4000 column 37: offset 0, mask 0x2000 column 38: offset 0, mask 0x0002 column 39: offset 0, mask 0x0001 column 40: offset 0, mask 0x0800 column 41: offset 0, mask 0x0004 column 42: offset 0, mask 0x0200 column 43: offset 0, mask 0x0040 column 44: offset 2, mask 0x0008 column 45: offset 0, mask 0x0100 column 46: offset 1, mask 0x0001 column 47: offset 1, mask 0x8000 column 48: offset 1, mask 0x2000 column 49: offset 1, mask 0x0004 column 50: offset 1, mask 0x4000 column 51: offset 1, mask 0x0002 column 52: offset 1, mask 0x0008 column 53: offset 1, mask 0x0020 column 54: offset 1, mask 0x0800 column 55: offset 1, mask 0x0010 column 56: offset 1, mask 0x1000 column 57: offset 1, mask 0x0400 column 58: offset 2, mask 0x0001 column 59: offset 1, mask 0x0080 column 60: offset 1, mask 0x0200 column 61: offset 1, mask 0x0040 column 62: offset 2, mask 0x8000 column 63: offset 2, mask 0x1000 column 64: offset 2, mask 0x2000 column 65: offset 2, mask 0x0002 column 66: offset 2, mask 0x4000 direction bits (1=input) 0x05A8 0x7BF7 0x7013 0x0004 0x40F0 pullup bits (1=pullup) 0x0000 0x0000 0x0000 0x0000 0x0000 test step out_data dont care 1: 0x0548 0x0001 0x0000 0x4004 0x0000 0x0000 0x7AF6 0x7003 0x0000 0x0000 2: 0x7448 0x0000 0x0000 0x4004 0x0000 0x0000 0x7AF6 0x7003 0x0000 0x0000 3: 0x7448 0xE638 0x9003 0x4004 0x0000 4: 0x7448 0x6230 0x1003 0x4004 0x0000 5: 0x5448 0x6231 0x1003 0x4004 0x0000 6: 0x5448 0xB46B 0xD001 0x4004 0x0000 7: 0x5448 0x3063 0x5001 0x4004 0x0000 8: 0x1548 0x3063 0x5001 0x4004 0x0000 9: 0x1548 0x9CCF 0xE000 0x4004 0x0000 10: 0x1548 0x18C7 0x6000 0x4004 0x0000 11: 0x5448 0x18C7 0x6000 0x4004 0x0000 12: 0x5448 0xB46B 0xD001 0x4004 0x0000 13: 0x5448 0x3063 0x5001 0x4004 0x0000 14: 0x7448 0x3062 0x5001 0x4004 0x0000 15: 0x7448 0xE638 0x9003 0x4004 0x0000 16: 0x7448 0x6230 0x1003 0x4004 0x0000 17: 0x0548 0x6231 0x1003 0x4004 0x0000 18: 0x0548 0x6231 0x1003 0x4004 0x0000 19: 0x064B 0x6230 0x1003 0x4004 0x0000 20: 0x064B 0xE638 0x9003 0x4004 0x0000 21: 0x064B 0x6230 0x1003 0x4004 0x0000 22: 0x064A 0x6231 0x1003 0x4004 0x0000 23: 0x064A 0xB46B 0xD001 0x4004 0x0000 24: 0x064A 0x3063 0x5001 0x4004 0x0000 25: 0x0748 0x3063 0x5001 0x4004 0x0000 26: 0x0748 0x9CCF 0xE000 0x4004 0x0000 27: 0x0748 0x18C7 0x6000 0x4004 0x0000 28: 0x064A 0x18C7 0x6000 0x4004 0x0000 29: 0x064A 0xB46B 0xD001 0x4004 0x0000 30: 0x064A 0x3063 0x5001 0x4004 0x0000 31: 0x064B 0x3062 0x5001 0x4004 0x0000 32: 0x064B 0xE638 0x9003 0x4004 0x0000 33: 0x064B 0x6230 0x1003 0x4004 0x0000 34: 0x0548 0x6231 0x1003 0x4004 0x0000 35: 0x0548 0x6231 0x1003 0x4004 0x0000 36: 0x7448 0x6230 0x1003 0x4004 0x0000 37: 0x7448 0xE230 0x1003 0x4004 0x0000 38: 0x7448 0x6230 0x1003 0x4004 0x0000 39: 0x7448 0x6238 0x1003 0x4004 0x0000 40: 0x7448 0x6230 0x1003 0x4004 0x0000 41: 0x7448 0x6630 0x1003 0x4004 0x0000 42: 0x7448 0x6230 0x1003 0x4004 0x0000 43: 0x7448 0x6230 0x9003 0x4004 0x0000 44: 0x7448 0x6230 0x1003 0x4004 0x0000 45: 0x5448 0x6231 0x1003 0x4004 0x0000 46: 0x5448 0xA233 0x1003 0x4004 0x0000 47: 0x5448 0x2233 0x1003 0x4004 0x0000 48: 0x5448 0x322B 0x1003 0x4004 0x0000 49: 0x5448 0x3223 0x1003 0x4004 0x0000 50: 0x5448 0x3463 0x1003 0x4004 0x0000 51: 0x5448 0x3063 0x1003 0x4004 0x0000 52: 0x5448 0x3063 0xD001 0x4004 0x0000 53: 0x5448 0x3063 0x5001 0x4004 0x0000 54: 0x1548 0x3063 0x5001 0x4004 0x0000 55: 0x1548 0x9067 0x5001 0x4004 0x0000 56: 0x1548 0x1067 0x5001 0x4004 0x0000 57: 0x1548 0x184F 0x5001 0x4004 0x0000 58: 0x1548 0x1847 0x5001 0x4004 0x0000 59: 0x1548 0x1CC7 0x5000 0x4004 0x0000 60: 0x1548 0x18C7 0x5000 0x4004 0x0000 61: 0x1548 0x18C7 0xE000 0x4004 0x0000 62: 0x1548 0x18C7 0x6000 0x4004 0x0000 63: 0x3548 0x18C6 0x6000 0x4004 0x0000 64: 0x3548 0xD8C4 0x6000 0x4004 0x0000 65: 0x3548 0x58C4 0x6000 0x4004 0x0000 66: 0x3548 0x48DC 0x6000 0x4004 0x0000 67: 0x3548 0x48D4 0x6000 0x4004 0x0000 68: 0x3548 0x4E94 0x6000 0x4004 0x0000 69: 0x3548 0x4A94 0x6000 0x4004 0x0000 70: 0x3548 0x4A94 0xA002 0x4004 0x0000 71: 0x3548 0x4A94 0x2002 0x4004 0x0000 72: 0x7448 0x4A94 0x2002 0x4004 0x0000 73: 0x7448 0xEA90 0x2002 0x4004 0x0000 74: 0x7448 0x6A90 0x2002 0x4004 0x0000 75: 0x7448 0x62B8 0x2002 0x4004 0x0000 76: 0x7448 0x62B0 0x2002 0x4004 0x0000 77: 0x7448 0x6630 0x2003 0x4004 0x0000 78: 0x7448 0x6230 0x2003 0x4004 0x0000 79: 0x7448 0x6230 0x9003 0x4004 0x0000 80: 0x7448 0x6230 0x1003 0x4004 0x0000 81: 0x7448 0x6230 0x1003 0x4004 0x0000 82: 0x7448 0xE230 0x1003 0x4004 0x0000 83: 0x7448 0x6230 0x1003 0x4004 0x0000 84: 0x7448 0x6238 0x1003 0x4004 0x0000 85: 0x7448 0x6230 0x1003 0x4004 0x0000 86: 0x7448 0x6630 0x1003 0x4004 0x0000 87: 0x7448 0x6230 0x1003 0x4004 0x0000 88: 0x7448 0x6230 0x9003 0x4004 0x0000 89: 0x7448 0x6230 0x1003 0x4004 0x0000 90: 0x5448 0x6231 0x1003 0x4004 0x0000 91: 0x5448 0xA233 0x1003 0x4004 0x0000 92: 0x5448 0x2233 0x1003 0x4004 0x0000 93: 0x7448 0x2232 0x1003 0x4004 0x0000 94: 0x7448 0xE230 0x1003 0x4004 0x0000 95: 0x7448 0x6230 0x1003 0x4004 0x0000 96: 0x5448 0x6231 0x1003 0x4004 0x0000 97: 0x5448 0x7229 0x1003 0x4004 0x0000 98: 0x5448 0x7221 0x1003 0x4004 0x0000 99: 0x7448 0x7220 0x1003 0x4004 0x0000 100: 0x7448 0x6238 0x1003 0x4004 0x0000 101: 0x7448 0x6230 0x1003 0x4004 0x0000 102: 0x5448 0x6231 0x1003 0x4004 0x0000 103: 0x5448 0x6471 0x1003 0x4004 0x0000 104: 0x5448 0x6071 0x1003 0x4004 0x0000 105: 0x7448 0x6070 0x1003 0x4004 0x0000 106: 0x7448 0x6630 0x1003 0x4004 0x0000 107: 0x7448 0x6230 0x1003 0x4004 0x0000 108: 0x5448 0x6231 0x1003 0x4004 0x0000 109: 0x5448 0x6231 0xD001 0x4004 0x0000 110: 0x5448 0x6231 0x5001 0x4004 0x0000 111: 0x7448 0x6230 0x5001 0x4004 0x0000 112: 0x7448 0x6230 0x9003 0x4004 0x0000 113: 0x7448 0x6230 0x1003 0x4004 0x0000 114: 0x3548 0x6230 0x1003 0x4004 0x0000 115: 0x3548 0xC234 0x1003 0x4004 0x0000 116: 0x3548 0x4234 0x1003 0x4004 0x0000 117: 0x7448 0x4234 0x1003 0x4004 0x0000 118: 0x7448 0xE230 0x1003 0x4004 0x0000 119: 0x7448 0x6230 0x1003 0x4004 0x0000 120: 0x3548 0x6230 0x1003 0x4004 0x0000 121: 0x3548 0x6A18 0x1003 0x4004 0x0000 122: 0x3548 0x6A10 0x1003 0x4004 0x0000 123: 0x7448 0x6A10 0x1003 0x4004 0x0000 124: 0x7448 0x6238 0x1003 0x4004 0x0000 125: 0x7448 0x6230 0x1003 0x4004 0x0000 126: 0x3548 0x6230 0x1003 0x4004 0x0000 127: 0x3548 0x66B0 0x1002 0x4004 0x0000 128: 0x3548 0x62B0 0x1002 0x4004 0x0000 129: 0x7448 0x62B0 0x1002 0x4004 0x0000 130: 0x7448 0x6630 0x1003 0x4004 0x0000 131: 0x7448 0x6230 0x1003 0x4004 0x0000 132: 0x3548 0x6230 0x1003 0x4004 0x0000 133: 0x3548 0x6230 0xA003 0x4004 0x0000 134: 0x3548 0x6230 0x2003 0x4004 0x0000 135: 0x7448 0x6230 0x2003 0x4004 0x0000 136: 0x7448 0x6230 0x9003 0x4004 0x0000 137: 0x7448 0x6230 0x1003 0x4004 0x0000 138: 0x1548 0x6231 0x1003 0x4004 0x0000 139: 0x1548 0x8237 0x1003 0x4004 0x0000 140: 0x1548 0x0237 0x1003 0x4004 0x0000 141: 0x7448 0x0236 0x1003 0x4004 0x0000 142: 0x7448 0xE230 0x1003 0x4004 0x0000 143: 0x7448 0x6230 0x1003 0x4004 0x0000 144: 0x1548 0x6231 0x1003 0x4004 0x0000 145: 0x1548 0x7A09 0x1003 0x4004 0x0000 146: 0x1548 0x7A01 0x1003 0x4004 0x0000 147: 0x7448 0x7A00 0x1003 0x4004 0x0000 148: 0x7448 0x6238 0x1003 0x4004 0x0000 149: 0x7448 0x6230 0x1003 0x4004 0x0000 150: 0x1548 0x6231 0x1003 0x4004 0x0000 151: 0x1548 0x64F1 0x1002 0x4004 0x0000 152: 0x1548 0x60F1 0x1002 0x4004 0x0000 153: 0x7448 0x60F0 0x1002 0x4004 0x0000 154: 0x7448 0x6630 0x1003 0x4004 0x0000 155: 0x7448 0x6230 0x1003 0x4004 0x0000 156: 0x1548 0x6231 0x1003 0x4004 0x0000 157: 0x1548 0x6231 0xE001 0x4004 0x0000 158: 0x1548 0x6231 0x6001 0x4004 0x0000 159: 0x7448 0x6230 0x6001 0x4004 0x0000 160: 0x7448 0x6230 0x9003 0x4004 0x0000 161: 0x7448 0x6230 0x1003 0x4004 0x0000 162: 0x7448 0x6230 0x1003 0x4004 0x0000 163: 0x5448 0x6231 0x1003 0x4004 0x0000 164: 0x5448 0xB46B 0xD001 0x4004 0x0000 165: 0x5448 0x3063 0x5001 0x4004 0x0000 166: 0x5448 0x3063 0x5001 0x4004 0x0000 167: 0x7448 0x3062 0x5001 0x4004 0x0000 168: 0x7448 0xF060 0x5001 0x4004 0x0000 169: 0x7448 0x7060 0x5001 0x4004 0x0000 170: 0x5448 0x7061 0x5001 0x4004 0x0000 171: 0x5448 0xB063 0x5001 0x4004 0x0000 172: 0x5448 0x3063 0x5001 0x4004 0x0000 173: 0x7448 0x3062 0x5001 0x4004 0x0000 174: 0x7448 0x207A 0x5001 0x4004 0x0000 175: 0x7448 0x2072 0x5001 0x4004 0x0000 176: 0x5448 0x2073 0x5001 0x4004 0x0000 177: 0x5448 0x306B 0x5001 0x4004 0x0000 178: 0x5448 0x3063 0x5001 0x4004 0x0000 179: 0x7448 0x3062 0x5001 0x4004 0x0000 180: 0x7448 0x3622 0x5001 0x4004 0x0000 181: 0x7448 0x3222 0x5001 0x4004 0x0000 182: 0x5448 0x3223 0x5001 0x4004 0x0000 183: 0x5448 0x3463 0x5001 0x4004 0x0000 184: 0x5448 0x3063 0x5001 0x4004 0x0000 185: 0x7448 0x3062 0x5001 0x4004 0x0000 186: 0x7448 0x3062 0x9003 0x4004 0x0000 187: 0x7448 0x3062 0x1003 0x4004 0x0000 188: 0x5448 0x3063 0x1003 0x4004 0x0000 189: 0x5448 0x3063 0xD001 0x4004 0x0000 190: 0x5448 0x3063 0x5001 0x4004 0x0000 191: 0x5448 0xB063 0x5001 0x4004 0x0000 192: 0x5448 0x3063 0x5001 0x4004 0x0000 193: 0x5448 0x306B 0x5001 0x4004 0x0000 194: 0x5448 0x3063 0x5001 0x4004 0x0000 195: 0x5448 0x3463 0x5001 0x4004 0x0000 196: 0x5448 0x3063 0x5001 0x4004 0x0000 197: 0x5448 0x3063 0xD001 0x4004 0x0000 198: 0x5448 0x3063 0x5001 0x4004 0x0000 199: 0x3548 0x3062 0x5001 0x4004 0x0000 200: 0x3548 0xD064 0x5001 0x4004 0x0000 201: 0x3548 0x5064 0x5001 0x4004 0x0000 202: 0x5448 0x5065 0x5001 0x4004 0x0000 203: 0x5448 0xB063 0x5001 0x4004 0x0000 204: 0x5448 0x3063 0x5001 0x4004 0x0000 205: 0x3548 0x3062 0x5001 0x4004 0x0000 206: 0x3548 0x285A 0x5001 0x4004 0x0000 207: 0x3548 0x2852 0x5001 0x4004 0x0000 208: 0x5448 0x2853 0x5001 0x4004 0x0000 209: 0x5448 0x306B 0x5001 0x4004 0x0000 210: 0x5448 0x3063 0x5001 0x4004 0x0000 211: 0x3548 0x3062 0x5001 0x4004 0x0000 212: 0x3548 0x36A2 0x5000 0x4004 0x0000 213: 0x3548 0x32A2 0x5000 0x4004 0x0000 214: 0x5448 0x32A3 0x5000 0x4004 0x0000 215: 0x5448 0x3463 0x5001 0x4004 0x0000 216: 0x5448 0x3063 0x5001 0x4004 0x0000 217: 0x3548 0x3062 0x5001 0x4004 0x0000 218: 0x3548 0x3062 0xA003 0x4004 0x0000 219: 0x3548 0x3062 0x2003 0x4004 0x0000 220: 0x5448 0x3063 0x2003 0x4004 0x0000 221: 0x5448 0x3063 0xD001 0x4004 0x0000 222: 0x5448 0x3063 0x5001 0x4004 0x0000 223: 0x1548 0x3063 0x5001 0x4004 0x0000 224: 0x1548 0x9067 0x5001 0x4004 0x0000 225: 0x1548 0x1067 0x5001 0x4004 0x0000 226: 0x5448 0x1067 0x5001 0x4004 0x0000 227: 0x5448 0xB063 0x5001 0x4004 0x0000 228: 0x5448 0x3063 0x5001 0x4004 0x0000 229: 0x1548 0x3063 0x5001 0x4004 0x0000 230: 0x1548 0x384B 0x5001 0x4004 0x0000 231: 0x1548 0x3843 0x5001 0x4004 0x0000 232: 0x5448 0x3843 0x5001 0x4004 0x0000 233: 0x5448 0x306B 0x5001 0x4004 0x0000 234: 0x5448 0x3063 0x5001 0x4004 0x0000 235: 0x1548 0x3063 0x5001 0x4004 0x0000 236: 0x1548 0x34E3 0x5000 0x4004 0x0000 237: 0x1548 0x30E3 0x5000 0x4004 0x0000 238: 0x5448 0x30E3 0x5000 0x4004 0x0000 239: 0x5448 0x3463 0x5001 0x4004 0x0000 240: 0x5448 0x3063 0x5001 0x4004 0x0000 241: 0x1548 0x3063 0x5001 0x4004 0x0000 242: 0x1548 0x3063 0xE001 0x4004 0x0000 243: 0x1548 0x3063 0x6001 0x4004 0x0000 244: 0x5448 0x3063 0x6001 0x4004 0x0000 245: 0x5448 0x3063 0xD001 0x4004 0x0000 246: 0x5448 0x3063 0x5001 0x4004 0x0000 247: 0x5448 0x3063 0x5001 0x4004 0x0000 248: 0x3548 0x3062 0x5001 0x4004 0x0000 249: 0x3548 0xCE9C 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0x5448 0x52A5 0x2002 0x4004 0x0000 1122: 0x1548 0x52A5 0x2002 0x4004 0x0000 1123: 0x1548 0x94E7 0xE000 0x4004 0x0000 1124: 0x1548 0x10E7 0x6000 0x4004 0x0000 1125: 0x7448 0x10E6 0x6000 0x4004 0x0000 1126: 0x7448 0x00FE 0x6000 0x4004 0x0000 1127: 0x7448 0x00F6 0x6000 0x4004 0x0000 1128: 0x7448 0x00F6 0x6000 0x4004 0x0001 1129: 0x7448 0x00F6 0x6000 0x4004 0x0000 1130: 0x5448 0x00F7 0x6000 0x4004 0x0000 1131: 0x5448 0xA473 0xD001 0x4004 0x0000 1132: 0x5448 0x2073 0x5001 0x4004 0x0000 1133: 0x3548 0x2072 0x5001 0x4004 0x0000 1134: 0x3548 0x285A 0x5001 0x4004 0x0000 1135: 0x3548 0x2852 0x5001 0x4004 0x0000 1136: 0x3540 0x2852 0x5001 0x4004 0x0001 1137: 0x3548 0x2852 0x5001 0x4004 0x0000 1138: 0x7448 0x2852 0x5001 0x4004 0x0000 1139: 0x7448 0xE638 0x9003 0x4004 0x0000 1140: 0x7448 0x6230 0x1003 0x4004 0x0000 1141: 0x0548 0x6231 0x1003 0x4004 0x0000 1142: 0x0548 0x6231 0x1003 0x4004 0x0000 PINs used (in edge connector order) (G=ground,P=power) SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBB LETTER ABCDEFHJKLMNPRSTUVABCDEFHJKLMNPRSTUVABCDEFHJKLMNPRSTUVABCDEFHJKLMNPRSTUV SIDE 111111111111111111222222222222222222111111111111111111222222222222222222 USAGE IIIIIOIOIOOOOIOGIOPIGIOIIIOOOIOOOOOOOOIIIIIIIIIIIIIGIIPIGIIIIIOIIIIIIIII UUT inputs: 45 UUT outputs: 21 pins used: 66 not used: 0 1142 'test steps' 1506 lines M220 PCB REV ? SCHEMATIC REV C MAJOR REGISTERS PINS Main menu Mon Jul 10 11:00:18 2017 test file is: tests\m220.tst delay is: 0 trigger is: 1 1 read test file 2 set test delay 3 set test trigger 4 run test 5 output loading test 8 diags 9 exit UUT power is okay Mon Jul 10 11:00:21 2017 space single step O run once (one test, all steps) F run, stop on fail G go (run tests N run, stop on fail, no print S scope (run, no print) C turn on comment printout + increase speed (less delay) - decrease speed (more delay)(slower) Q quit test scope (run, no print) FFFFFFF space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn on comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit step 124 000000000000000000000000000011110011100000100001010110100101001010 step 125 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000000000000000000000000000011110000011001100001010010100010101010 step 477 000000000000000000000000000011110000011001100011010110100010111010 step 478 000000000000000000000000000011110000011001100001010010100010101010 step 479 000000000000000000000000000011110000011000101101010010100010101010 SLOT BBBBBBBBBBBBBBBBBBBBBBBBBBBBBBAAAAAAAAAAAAABAAAAAAAAAAAAAAAAAABBAA LETTER EHJFHNCEDFDNLMPLKMPRSURVVTSUJKEFADDBCHJEFHBBJKKMMLLNRPPNRUTSSUBAVV SIDE 222112112211122211122211221112211211122121221211212221211221211121 DIRECTION IIIIIIIIIIIIIIIIIIIIIIIIIIIIIOOOIIIIIIIIIIIIOOIOOOOIOOOOIOOOOIOOOO changed: 1 00 step 480 000000000000000000000000000011111000011000100001010010100010101010 fail ^^ SLOT BBBBBBBBBBBBBBBBBBBBBBBBBBBBBBAAAAAAAAAAAAABAAAAAAAAAAAAAAAAAABBAA LETTER EHJFHNCEDFDNLMPLKMPRSURVVTSUJKEFADDBCHJEFHBBJKKMMLLNRPPNRUTSSUBAVV SIDE 222112112211122211122211221112211211122121221211212221211221211121 DIRECTION IIIIIIIIIIIIIIIIIIIIIIIIIIIIIOOOIIIIIIIIIIIIOOIOOOOIOOOOIOOOOIOOOO changed: 1 step 481 000000000000000000000000000011111000011000100011010010100010101010 fail ^^ ^^^^ SLOT BBBBBBBBBBBBBBBBBBBBBBBBBBBBBBAAAAAAAAAAAAABAAAAAAAAAAAAAAAAAABBAA LETTER EHJFHNCEDFDNLMPLKMPRSURVVTSUJKEFADDBCHJEFHBBJKKMMLLNRPPNRUTSSUBAVV SIDE 222112112211122211122211221112211211122121221211212221211221211121 DIRECTION IIIIIIIIIIIIIIIIIIIIIIIIIIIIIOOOIIIIIIIIIIIIOOIOOOOIOOOOIOOOOIOOOO changed: 0 step 482 000000000000000000000000000011111000011000100001010010100010101010 fail ^^ ^^^^ SLOT BBBBBBBBBBBBBBBBBBBBBBBBBBBBBBAAAAAAAAAAAAABAAAAAAAAAAAAAAAAAABBAA LETTER EHJFHNCEDFDNLMPLKMPRSURVVTSUJKEFADDBCHJEFHBBJKKMMLLNRPPNRUTSSUBAVV SIDE 222112112211122211122211221112211211122121221211212221211221211121 DIRECTION IIIIIIIIIIIIIIIIIIIIIIIIIIIIIOOOIIIIIIIIIIIIOOIOOOOIOOOOIOOOOIOOOO changed: 0 11 step 483 000000000000000000000000000011110000011000101101010010100010101010 fail ^^^^ SLOT BBBBBBBBBBBBBBBBBBBBBBBBBBBBBBAAAAAAAAAAAAABAAAAAAAAAAAAAAAAAABBAA LETTER EHJFHNCEDFDNLMPLKMPRSURVVTSUJKEFADDBCHJEFHBBJKKMMLLNRPPNRUTSSUBAVV SIDE 222112112211122211122211221112211211122121221211212221211221211121 DIRECTION IIIIIIIIIIIIIIIIIIIIIIIIIIIIIOOOIIIIIIIIIIIIOOIOOOOIOOOOIOOOOIOOOO changed: 1 00 step 484 000000000000000000000000000011110000011001100001010010100010101010 fail ^^^^ step 485 000000000000000000000000000011110000011001100011010010100010101010 step 486 000000000000000000000000000011110000011001100001010010100010101010 step 487 000000000000000000000000000011110000011000101101010010100010101010 SLOT BBBBBBBBBBBBBBBBBBBBBBBBBBBBBBAAAAAAAAAAAAABAAAAAAAAAAAAAAAAAABBAA LETTER EHJFHNCEDFDNLMPLKMPRSURVVTSUJKEFADDBCHJEFHBBJKKMMLLNRPPNRUTSSUBAVV SIDE 222112112211122211122211221112211211122121221211212221211221211121 DIRECTION IIIIIIIIIIIIIIIIIIIIIIIIIIIIIOOOIIIIIIIIIIIIOOIOOOOIOOOOIOOOOIOOOO changed: 1 00 step 488 000000000000000000000000000011111000011000100001010010100010101010 fail ^^ SLOT BBBBBBBBBBBBBBBBBBBBBBBBBBBBBBAAAAAAAAAAAAABAAAAAAAAAAAAAAAAAABBAA LETTER EHJFHNCEDFDNLMPLKMPRSURVVTSUJKEFADDBCHJEFHBBJKKMMLLNRPPNRUTSSUBAVV SIDE 222112112211122211122211221112211211122121221211212221211221211121 DIRECTION IIIIIIIIIIIIIIIIIIIIIIIIIIIIIOOOIIIIIIIIIIIIOOIOOOOIOOOOIOOOOIOOOO changed: 1 step 489 000000000000000000000000000011111000011000100001010110100010101010 fail ^^ ^^^^ SLOT BBBBBBBBBBBBBBBBBBBBBBBBBBBBBBAAAAAAAAAAAAABAAAAAAAAAAAAAAAAAABBAA LETTER EHJFHNCEDFDNLMPLKMPRSURVVTSUJKEFADDBCHJEFHBBJKKMMLLNRPPNRUTSSUBAVV SIDE 222112112211122211122211221112211211122121221211212221211221211121 DIRECTION IIIIIIIIIIIIIIIIIIIIIIIIIIIIIOOOIIIIIIIIIIIIOOIOOOOIOOOOIOOOOIOOOO changed: 0 step 490 000000000000000000000000000011111000011000100001010010100010101010 fail ^^ ^^^^ SLOT BBBBBBBBBBBBBBBBBBBBBBBBBBBBBBAAAAAAAAAAAAABAAAAAAAAAAAAAAAAAABBAA LETTER EHJFHNCEDFDNLMPLKMPRSURVVTSUJKEFADDBCHJEFHBBJKKMMLLNRPPNRUTSSUBAVV SIDE 222112112211122211122211221112211211122121221211212221211221211121 DIRECTION IIIIIIIIIIIIIIIIIIIIIIIIIIIIIOOOIIIIIIIIIIIIOOIOOOOIOOOOIOOOOIOOOO changed: 0 11 step 491 000000000000000000000000000011110000011000101101010010100010101010 fail ^^^^ SLOT BBBBBBBBBBBBBBBBBBBBBBBBBBBBBBAAAAAAAAAAAAABAAAAAAAAAAAAAAAAAABBAA LETTER EHJFHNCEDFDNLMPLKMPRSURVVTSUJKEFADDBCHJEFHBBJKKMMLLNRPPNRUTSSUBAVV SIDE 222112112211122211122211221112211211122121221211212221211221211121 DIRECTION IIIIIIIIIIIIIIIIIIIIIIIIIIIIIOOOIIIIIIIIIIIIOOIOOOOIOOOOIOOOOIOOOO changed: 1 00 step 492 000000000000000000000000000011110000011001100001010010100010101010 fail ^^^^ step 493 000000000000000000000000000011110000011001100001010110100010101010 step 494 000000000000000000000000000011110000011001100001010010100010101010 step 495 000000000000000000000000000011110000011000101101010010100010101010 SLOT BBBBBBBBBBBBBBBBBBBBBBBBBBBBBBAAAAAAAAAAAAABAAAAAAAAAAAAAAAAAABBAA LETTER EHJFHNCEDFDNLMPLKMPRSURVVTSUJKEFADDBCHJEFHBBJKKMMLLNRPPNRUTSSUBAVV SIDE 222112112211122211122211221112211211122121221211212221211221211121 DIRECTION IIIIIIIIIIIIIIIIIIIIIIIIIIIIIOOOIIIIIIIIIIIIOOIOOOOIOOOOIOOOOIOOOO changed: 1 00 step 496 000000000000000000000000000011111000011000100001010010100010101010 fail ^^ SLOT BBBBBBBBBBBBBBBBBBBBBBBBBBBBBBAAAAAAAAAAAAABAAAAAAAAAAAAAAAAAABBAA LETTER EHJFHNCEDFDNLMPLKMPRSURVVTSUJKEFADDBCHJEFHBBJKKMMLLNRPPNRUTSSUBAVV SIDE 222112112211122211122211221112211211122121221211212221211221211121 DIRECTION IIIIIIIIIIIIIIIIIIIIIIIIIIIIIOOOIIIIIIIIIIIIOOIOOOOIOOOOIOOOOIOOOO changed: 11010 step 497 000000000000000000000000000011111000011000100001010010101101001010 fail ^^ ^^^^ SLOT BBBBBBBBBBBBBBBBBBBBBBBBBBBBBBAAAAAAAAAAAAABAAAAAAAAAAAAAAAAAABBAA LETTER EHJFHNCEDFDNLMPLKMPRSURVVTSUJKEFADDBCHJEFHBBJKKMMLLNRPPNRUTSSUBAVV SIDE 222112112211122211122211221112211211122121221211212221211221211121 DIRECTION IIIIIIIIIIIIIIIIIIIIIIIIIIIIIOOOIIIIIIIIIIIIOOIOOOOIOOOOIOOOOIOOOO changed: 0 step 498 000000000000000000000000000011111000011000100001010010100101001010 fail ^^ ^^^^ SLOT BBBBBBBBBBBBBBBBBBBBBBBBBBBBBBAAAAAAAAAAAAABAAAAAAAAAAAAAAAAAABBAA LETTER EHJFHNCEDFDNLMPLKMPRSURVVTSUJKEFADDBCHJEFHBBJKKMMLLNRPPNRUTSSUBAVV SIDE 222112112211122211122211221112211211122121221211212221211221211121 DIRECTION IIIIIIIIIIIIIIIIIIIIIIIIIIIIIOOOIIIIIIIIIIIIOOIOOOOIOOOOIOOOOIOOOO changed: 1 step 499 000000000000000000000000000011111000011000100001010010100101011010 fail ^^ ^^^^ ^^^^ SLOT BBBBBBBBBBBBBBBBBBBBBBBBBBBBBBAAAAAAAAAAAAABAAAAAAAAAAAAAAAAAABBAA LETTER EHJFHNCEDFDNLMPLKMPRSURVVTSUJKEFADDBCHJEFHBBJKKMMLLNRPPNRUTSSUBAVV SIDE 222112112211122211122211221112211211122121221211212221211221211121 DIRECTION IIIIIIIIIIIIIIIIIIIIIIIIIIIIIOOOIIIIIIIIIIIIOOIOOOOIOOOOIOOOOIOOOO changed: 0 step 500 000000000000000000000000000011111000011000100001010010100101001010 fail ^^ ^^^^ ^^^^ SLOT BBBBBBBBBBBBBBBBBBBBBBBBBBBBBBAAAAAAAAAAAAABAAAAAAAAAAAAAAAAAABBAA LETTER EHJFHNCEDFDNLMPLKMPRSURVVTSUJKEFADDBCHJEFHBBJKKMMLLNRPPNRUTSSUBAVV SIDE 222112112211122211122211221112211211122121221211212221211221211121 DIRECTION IIIIIIIIIIIIIIIIIIIIIIIIIIIIIOOOIIIIIIIIIIIIOOIOOOOIOOOOIOOOOIOOOO changed: 0 11 step 501 000000000000000000000000000011110000011000101101010010100101001010 fail ^^^^ ^^^^ SLOT BBBBBBBBBBBBBBBBBBBBBBBBBBBBBBAAAAAAAAAAAAABAAAAAAAAAAAAAAAAAABBAA LETTER EHJFHNCEDFDNLMPLKMPRSURVVTSUJKEFADDBCHJEFHBBJKKMMLLNRPPNRUTSSUBAVV SIDE 222112112211122211122211221112211211122121221211212221211221211121 DIRECTION IIIIIIIIIIIIIIIIIIIIIIIIIIIIIOOOIIIIIIIIIIIIOOIOOOOIOOOOIOOOOIOOOO changed: 1 00 step 502 000000000000000000000000000011110000011001100001010010100101001010 fail ^^^^ ^^^^ SLOT BBBBBBBBBBBBBBBBBBBBBBBBBBBBBBAAAAAAAAAAAAABAAAAAAAAAAAAAAAAAABBAA LETTER EHJFHNCEDFDNLMPLKMPRSURVVTSUJKEFADDBCHJEFHBBJKKMMLLNRPPNRUTSSUBAVV SIDE 222112112211122211122211221112211211122121221211212221211221211121 DIRECTION IIIIIIIIIIIIIIIIIIIIIIIIIIIIIOOOIIIIIIIIIIIIOOIOOOOIOOOOIOOOOIOOOO changed: 1 step 503 000000000000000000000000000011110000011001100001010010100101011010 fail ^^^^ SLOT BBBBBBBBBBBBBBBBBBBBBBBBBBBBBBAAAAAAAAAAAAABAAAAAAAAAAAAAAAAAABBAA LETTER EHJFHNCEDFDNLMPLKMPRSURVVTSUJKEFADDBCHJEFHBBJKKMMLLNRPPNRUTSSUBAVV SIDE 222112112211122211122211221112211211122121221211212221211221211121 DIRECTION IIIIIIIIIIIIIIIIIIIIIIIIIIIIIOOOIIIIIIIIIIIIOOIOOOOIOOOOIOOOOIOOOO changed: 0 step 504 000000000000000000000000000011110000011001100001010010100101001010 fail ^^^^ SLOT BBBBBBBBBBBBBBBBBBBBBBBBBBBBBBAAAAAAAAAAAAABAAAAAAAAAAAAAAAAAABBAA LETTER EHJFHNCEDFDNLMPLKMPRSURVVTSUJKEFADDBCHJEFHBBJKKMMLLNRPPNRUTSSUBAVV SIDE 222112112211122211122211221112211211122121221211212221211221211121 DIRECTION IIIIIIIIIIIIIIIIIIIIIIIIIIIIIOOOIIIIIIIIIIIIOOIOOOOIOOOOIOOOOIOOOO changed: 0 11 step 505 000000000000000000000000000011110000011000101101010010100101001010 fail ^^^^ SLOT BBBBBBBBBBBBBBBBBBBBBBBBBBBBBBAAAAAAAAAAAAABAAAAAAAAAAAAAAAAAABBAA LETTER EHJFHNCEDFDNLMPLKMPRSURVVTSUJKEFADDBCHJEFHBBJKKMMLLNRPPNRUTSSUBAVV SIDE 222112112211122211122211221112211211122121221211212221211221211121 DIRECTION IIIIIIIIIIIIIIIIIIIIIIIIIIIIIOOOIIIIIIIIIIIIOOIOOOOIOOOOIOOOOIOOOO changed: 0 1 0 step 506 000000000000000000000000000011110000001001101001010010100101001010 fail ^^^^ step 507 000000000000000000000000000011110000001001101001010010101011001010 step 508 000000000000000000000000000011110000001001101001010010100011001010 step 509 000000000000000000000000000011110000010001100101010010100011001010 step 510 000000000000000000000000000011110000010001100111001110010011011001 step 511 000000000000000000000000000011110000010001100101001010010011001001 step 512 000000000000000000000000000011110000001000101101001010010011001001 SLOT BBBBBBBBBBBBBBBBBBBBBBBBBBBBBBAAAAAAAAAAAAABAAAAAAAAAAAAAAAAAABBAA LETTER EHJFHNCEDFDNLMPLKMPRSURVVTSUJKEFADDBCHJEFHBBJKKMMLLNRPPNRUTSSUBAVV SIDE 222112112211122211122211221112211211122121221211212221211221211121 DIRECTION IIIIIIIIIIIIIIIIIIIIIIIIIIIIIOOOIIIIIIIIIIIIOOIOOOOIOOOOIOOOOIOOOO changed: 1 00 step 513 000000000000000000000000000011111000001000100001001010010011001001 fail ^ SLOT BBBBBBBBBBBBBBBBBBBBBBBBBBBBBBAAAAAAAAAAAAABAAAAAAAAAAAAAAAAAABBAA LETTER EHJFHNCEDFDNLMPLKMPRSURVVTSUJKEFADDBCHJEFHBBJKKMMLLNRPPNRUTSSUBAVV SIDE 222112112211122211122211221112211211122121221211212221211221211121 DIRECTION IIIIIIIIIIIIIIIIIIIIIIIIIIIIIOOOIIIIIIIIIIIIOOIOOOOIOOOOIOOOOIOOOO changed: 1 10 step 514 000000000000000000000000000011111000001000100011010010010011001001 fail ^ ^^ SLOT BBBBBBBBBBBBBBBBBBBBBBBBBBBBBBAAAAAAAAAAAAABAAAAAAAAAAAAAAAAAABBAA LETTER EHJFHNCEDFDNLMPLKMPRSURVVTSUJKEFADDBCHJEFHBBJKKMMLLNRPPNRUTSSUBAVV SIDE 222112112211122211122211221112211211122121221211212221211221211121 DIRECTION IIIIIIIIIIIIIIIIIIIIIIIIIIIIIOOOIIIIIIIIIIIIOOIOOOOIOOOOIOOOOIOOOO changed: 0 step 515 000000000000000000000000000011111000001000100001010010010011001001 fail ^ ^^ SLOT BBBBBBBBBBBBBBBBBBBBBBBBBBBBBBAAAAAAAAAAAAABAAAAAAAAAAAAAAAAAABBAA LETTER EHJFHNCEDFDNLMPLKMPRSURVVTSUJKEFADDBCHJEFHBBJKKMMLLNRPPNRUTSSUBAVV SIDE 222112112211122211122211221112211211122121221211212221211221211121 DIRECTION IIIIIIIIIIIIIIIIIIIIIIIIIIIIIOOOIIIIIIIIIIIIOOIOOOOIOOOOIOOOOIOOOO changed: 0 11 step 516 000000000000000000000000000011110000001000101101010010010011001001 fail ^^ SLOT BBBBBBBBBBBBBBBBBBBBBBBBBBBBBBAAAAAAAAAAAAABAAAAAAAAAAAAAAAAAABBAA LETTER EHJFHNCEDFDNLMPLKMPRSURVVTSUJKEFADDBCHJEFHBBJKKMMLLNRPPNRUTSSUBAVV SIDE 222112112211122211122211221112211211122121221211212221211221211121 DIRECTION IIIIIIIIIIIIIIIIIIIIIIIIIIIIIOOOIIIIIIIIIIIIOOIOOOOIOOOOIOOOOIOOOO changed: 10 1 0 step 517 000000000000000000000000000011110000010001100101010010010011001001 fail ^^ step 518 000000000000000000000000000011110000010001100111001010010011001001 step 519 000000000000000000000000000011110000010001100101001010010011001001 step 520 000000000000000000000000000011110000010000101101001010010011001001 SLOT BBBBBBBBBBBBBBBBBBBBBBBBBBBBBBAAAAAAAAAAAAABAAAAAAAAAAAAAAAAAABBAA LETTER EHJFHNCEDFDNLMPLKMPRSURVVTSUJKEFADDBCHJEFHBBJKKMMLLNRPPNRUTSSUBAVV SIDE 222112112211122211122211221112211211122121221211212221211221211121 DIRECTION IIIIIIIIIIIIIIIIIIIIIIIIIIIIIOOOIIIIIIIIIIIIOOIOOOOIOOOOIOOOOIOOOO changed: 1 00 step 521 000000000000000000000000000011111000010000100001001010010011001001 fail ^ SLOT BBBBBBBBBBBBBBBBBBBBBBBBBBBBBBAAAAAAAAAAAAABAAAAAAAAAAAAAAAAAABBAA LETTER EHJFHNCEDFDNLMPLKMPRSURVVTSUJKEFADDBCHJEFHBBJKKMMLLNRPPNRUTSSUBAVV SIDE 222112112211122211122211221112211211122121221211212221211221211121 DIRECTION IIIIIIIIIIIIIIIIIIIIIIIIIIIIIOOOIIIIIIIIIIIIOOIOOOOIOOOOIOOOOIOOOO changed: 1 10 step 522 000000000000000000000000000011111000010000100001001110100011001001 fail ^ ^^ SLOT BBBBBBBBBBBBBBBBBBBBBBBBBBBBBBAAAAAAAAAAAAABAAAAAAAAAAAAAAAAAABBAA LETTER EHJFHNCEDFDNLMPLKMPRSURVVTSUJKEFADDBCHJEFHBBJKKMMLLNRPPNRUTSSUBAVV SIDE 222112112211122211122211221112211211122121221211212221211221211121 DIRECTION IIIIIIIIIIIIIIIIIIIIIIIIIIIIIOOOIIIIIIIIIIIIOOIOOOOIOOOOIOOOOIOOOO changed: 0 step 523 000000000000000000000000000011111000010000100001001010100011001001 fail ^ ^^ SLOT BBBBBBBBBBBBBBBBBBBBBBBBBBBBBBAAAAAAAAAAAAABAAAAAAAAAAAAAAAAAABBAA LETTER EHJFHNCEDFDNLMPLKMPRSURVVTSUJKEFADDBCHJEFHBBJKKMMLLNRPPNRUTSSUBAVV SIDE 222112112211122211122211221112211211122121221211212221211221211121 DIRECTION IIIIIIIIIIIIIIIIIIIIIIIIIIIIIOOOIIIIIIIIIIIIOOIOOOOIOOOOIOOOOIOOOO changed: 0 11 step 524 000000000000000000000000000011110000010000101101001010100011001001 fail ^^ SLOT BBBBBBBBBBBBBBBBBBBBBBBBBBBBBBAAAAAAAAAAAAABAAAAAAAAAAAAAAAAAABBAA LETTER EHJFHNCEDFDNLMPLKMPRSURVVTSUJKEFADDBCHJEFHBBJKKMMLLNRPPNRUTSSUBAVV SIDE 222112112211122211122211221112211211122121221211212221211221211121 DIRECTION IIIIIIIIIIIIIIIIIIIIIIIIIIIIIOOOIIIIIIIIIIIIOOIOOOOIOOOOIOOOOIOOOO changed: 1 0 step 525 000000000000000000000000000011110000010001100101001010100011001001 fail ^^ step 526 000000000000000000000000000011110000010001100101001110010011001001 step 527 000000000000000000000000000011110000010001100101001010010011001001 step 528 000000000000000000000000000011110000010000101101001010010011001001 SLOT BBBBBBBBBBBBBBBBBBBBBBBBBBBBBBAAAAAAAAAAAAABAAAAAAAAAAAAAAAAAABBAA LETTER EHJFHNCEDFDNLMPLKMPRSURVVTSUJKEFADDBCHJEFHBBJKKMMLLNRPPNRUTSSUBAVV SIDE 222112112211122211122211221112211211122121221211212221211221211121 DIRECTION IIIIIIIIIIIIIIIIIIIIIIIIIIIIIOOOIIIIIIIIIIIIOOIOOOOIOOOOIOOOOIOOOO changed: 1 00 step 529 000000000000000000000000000011111000010000100001001010010011001001 fail ^ SLOT BBBBBBBBBBBBBBBBBBBBBBBBBBBBBBAAAAAAAAAAAAABAAAAAAAAAAAAAAAAAABBAA LETTER EHJFHNCEDFDNLMPLKMPRSURVVTSUJKEFADDBCHJEFHBBJKKMMLLNRPPNRUTSSUBAVV SIDE 222112112211122211122211221112211211122121221211212221211221211121 DIRECTION IIIIIIIIIIIIIIIIIIIIIIIIIIIIIOOOIIIIIIIIIIIIOOIOOOOIOOOOIOOOOIOOOO changed: 110 step 530 000000000000000000000000000011111000010000100001001010011101001001 fail ^ ^^ SLOT BBBBBBBBBBBBBBBBBBBBBBBBBBBBBBAAAAAAAAAAAAABAAAAAAAAAAAAAAAAAABBAA LETTER EHJFHNCEDFDNLMPLKMPRSURVVTSUJKEFADDBCHJEFHBBJKKMMLLNRPPNRUTSSUBAVV SIDE 222112112211122211122211221112211211122121221211212221211221211121 DIRECTION IIIIIIIIIIIIIIIIIIIIIIIIIIIIIOOOIIIIIIIIIIIIOOIOOOOIOOOOIOOOOIOOOO changed: 0 step 531 000000000000000000000000000011111000010000100001001010010101001001 fail ^ ^^ SLOT BBBBBBBBBBBBBBBBBBBBBBBBBBBBBBAAAAAAAAAAAAABAAAAAAAAAAAAAAAAAABBAA LETTER EHJFHNCEDFDNLMPLKMPRSURVVTSUJKEFADDBCHJEFHBBJKKMMLLNRPPNRUTSSUBAVV SIDE 222112112211122211122211221112211211122121221211212221211221211121 DIRECTION IIIIIIIIIIIIIIIIIIIIIIIIIIIIIOOOIIIIIIIIIIIIOOIOOOOIOOOOIOOOOIOOOO changed: 1 10 step 532 000000000000000000000000000011111000010000100001001010010101011010 fail ^ ^^ ^^ SLOT BBBBBBBBBBBBBBBBBBBBBBBBBBBBBBAAAAAAAAAAAAABAAAAAAAAAAAAAAAAAABBAA LETTER EHJFHNCEDFDNLMPLKMPRSURVVTSUJKEFADDBCHJEFHBBJKKMMLLNRPPNRUTSSUBAVV SIDE 222112112211122211122211221112211211122121221211212221211221211121 DIRECTION IIIIIIIIIIIIIIIIIIIIIIIIIIIIIOOOIIIIIIIIIIIIOOIOOOOIOOOOIOOOOIOOOO changed: 0 step 533 000000000000000000000000000011111000010000100001001010010101001010 fail ^ ^^ ^^ SLOT BBBBBBBBBBBBBBBBBBBBBBBBBBBBBBAAAAAAAAAAAAABAAAAAAAAAAAAAAAAAABBAA LETTER EHJFHNCEDFDNLMPLKMPRSURVVTSUJKEFADDBCHJEFHBBJKKMMLLNRPPNRUTSSUBAVV SIDE 222112112211122211122211221112211211122121221211212221211221211121 DIRECTION IIIIIIIIIIIIIIIIIIIIIIIIIIIIIOOOIIIIIIIIIIIIOOIOOOOIOOOOIOOOOIOOOO changed: 0 11 step 534 000000000000000000000000000011110000010000101101001010010101001010 fail ^^ ^^ SLOT BBBBBBBBBBBBBBBBBBBBBBBBBBBBBBAAAAAAAAAAAAABAAAAAAAAAAAAAAAAAABBAA LETTER EHJFHNCEDFDNLMPLKMPRSURVVTSUJKEFADDBCHJEFHBBJKKMMLLNRPPNRUTSSUBAVV SIDE 222112112211122211122211221112211211122121221211212221211221211121 DIRECTION IIIIIIIIIIIIIIIIIIIIIIIIIIIIIOOOIIIIIIIIIIIIOOIOOOOIOOOOIOOOOIOOOO changed: 1 0 step 535 000000000000000000000000000011110000010001100101001010010101001010 fail ^^ ^^ SLOT BBBBBBBBBBBBBBBBBBBBBBBBBBBBBBAAAAAAAAAAAAABAAAAAAAAAAAAAAAAAABBAA LETTER EHJFHNCEDFDNLMPLKMPRSURVVTSUJKEFADDBCHJEFHBBJKKMMLLNRPPNRUTSSUBAVV SIDE 222112112211122211122211221112211211122121221211212221211221211121 DIRECTION IIIIIIIIIIIIIIIIIIIIIIIIIIIIIOOOIIIIIIIIIIIIOOIOOOOIOOOOIOOOOIOOOO changed: 1 01 step 536 000000000000000000000000000011110000010001100101001010010101011001 fail ^^ SLOT BBBBBBBBBBBBBBBBBBBBBBBBBBBBBBAAAAAAAAAAAAABAAAAAAAAAAAAAAAAAABBAA LETTER EHJFHNCEDFDNLMPLKMPRSURVVTSUJKEFADDBCHJEFHBBJKKMMLLNRPPNRUTSSUBAVV SIDE 222112112211122211122211221112211211122121221211212221211221211121 DIRECTION IIIIIIIIIIIIIIIIIIIIIIIIIIIIIOOOIIIIIIIIIIIIOOIOOOOIOOOOIOOOOIOOOO changed: 0 step 537 000000000000000000000000000011110000010001100101001010010101001001 fail ^^ SLOT BBBBBBBBBBBBBBBBBBBBBBBBBBBBBBAAAAAAAAAAAAABAAAAAAAAAAAAAAAAAABBAA LETTER EHJFHNCEDFDNLMPLKMPRSURVVTSUJKEFADDBCHJEFHBBJKKMMLLNRPPNRUTSSUBAVV SIDE 222112112211122211122211221112211211122121221211212221211221211121 DIRECTION IIIIIIIIIIIIIIIIIIIIIIIIIIIIIOOOIIIIIIIIIIIIOOIOOOOIOOOOIOOOOIOOOO changed: 0 1 step 538 000000000000000000000000000011110000010000101101001010010101001001 fail ^^ SLOT BBBBBBBBBBBBBBBBBBBBBBBBBBBBBBAAAAAAAAAAAAABAAAAAAAAAAAAAAAAAABBAA LETTER EHJFHNCEDFDNLMPLKMPRSURVVTSUJKEFADDBCHJEFHBBJKKMMLLNRPPNRUTSSUBAVV SIDE 222112112211122211122211221112211211122121221211212221211221211121 DIRECTION IIIIIIIIIIIIIIIIIIIIIIIIIIIIIOOOIIIIIIIIIIIIOOIOOOOIOOOOIOOOOIOOOO changed: 1 0 step 539 000000000000000000000000000011110000010001100101001010010101001001 fail ^^ step 540 000000000000000000000000000011110000010001100101001010011100101001 step 541 000000000000000000000000000011110000010001100101001010010100101001 step 542 000000000000000000000000000011110000001001101001001010010100101001 step 543 000000000000000000000000000011110000001001101010110101100100110110 step 544 000000000000000000000000000011110000001001101000110001100100100110 step 545 000000000000000000000000000011110000001000101100110001100100100110 SLOT BBBBBBBBBBBBBBBBBBBBBBBBBBBBBBAAAAAAAAAAAAABAAAAAAAAAAAAAAAAAABBAA LETTER EHJFHNCEDFDNLMPLKMPRSURVVTSUJKEFADDBCHJEFHBBJKKMMLLNRPPNRUTSSUBAVV SIDE 222112112211122211122211221112211211122121221211212221211221211121 DIRECTION IIIIIIIIIIIIIIIIIIIIIIIIIIIIIOOOIIIIIIIIIIIIOOIOOOOIOOOOIOOOOIOOOO changed: 1 00 step 546 000000000000000000000000000011111000001000100000110001100100100110 fail ^ SLOT BBBBBBBBBBBBBBBBBBBBBBBBBBBBBBAAAAAAAAAAAAABAAAAAAAAAAAAAAAAAABBAA LETTER EHJFHNCEDFDNLMPLKMPRSURVVTSUJKEFADDBCHJEFHBBJKKMMLLNRPPNRUTSSUBAVV SIDE 222112112211122211122211221112211211122121221211212221211221211121 DIRECTION IIIIIIIIIIIIIIIIIIIIIIIIIIIIIOOOIIIIIIIIIIIIOOIOOOOIOOOOIOOOOIOOOO changed: 110 step 547 000000000000000000000000000011111000001000100011010001100100100110 fail ^ ^^ SLOT BBBBBBBBBBBBBBBBBBBBBBBBBBBBBBAAAAAAAAAAAAABAAAAAAAAAAAAAAAAAABBAA LETTER EHJFHNCEDFDNLMPLKMPRSURVVTSUJKEFADDBCHJEFHBBJKKMMLLNRPPNRUTSSUBAVV SIDE 222112112211122211122211221112211211122121221211212221211221211121 DIRECTION IIIIIIIIIIIIIIIIIIIIIIIIIIIIIOOOIIIIIIIIIIIIOOIOOOOIOOOOIOOOOIOOOO changed: 0 step 548 000000000000000000000000000011111000001000100001010001100100100110 fail ^ ^^ SLOT BBBBBBBBBBBBBBBBBBBBBBBBBBBBBBAAAAAAAAAAAAABAAAAAAAAAAAAAAAAAABBAA LETTER EHJFHNCEDFDNLMPLKMPRSURVVTSUJKEFADDBCHJEFHBBJKKMMLLNRPPNRUTSSUBAVV SIDE 222112112211122211122211221112211211122121221211212221211221211121 DIRECTION IIIIIIIIIIIIIIIIIIIIIIIIIIIIIOOOIIIIIIIIIIIIOOIOOOOIOOOOIOOOOIOOOO changed: 0 11 step 549 000000000000000000000000000011110000001000101101010001100100100110 fail ^^ SLOT BBBBBBBBBBBBBBBBBBBBBBBBBBBBBBAAAAAAAAAAAAABAAAAAAAAAAAAAAAAAABBAA LETTER EHJFHNCEDFDNLMPLKMPRSURVVTSUJKEFADDBCHJEFHBBJKKMMLLNRPPNRUTSSUBAVV SIDE 222112112211122211122211221112211211122121221211212221211221211121 DIRECTION IIIIIIIIIIIIIIIIIIIIIIIIIIIIIOOOIIIIIIIIIIIIOOIOOOOIOOOOIOOOOIOOOO changed: 1 0 step 550 000000000000000000000000000011110000001001101001010001100100100110 fail ^^ step 551 000000000000000000000000000011110000001001101010110001100100100110 step 552 000000000000000000000000000011110000001001101000110001100100100110 step 553 000000000000000000000000000011110000001000101100110001100100100110 SLOT BBBBBBBBBBBBBBBBBBBBBBBBBBBBBBAAAAAAAAAAAAABAAAAAAAAAAAAAAAAAABBAA LETTER EHJFHNCEDFDNLMPLKMPRSURVVTSUJKEFADDBCHJEFHBBJKKMMLLNRPPNRUTSSUBAVV SIDE 222112112211122211122211221112211211122121221211212221211221211121 DIRECTION IIIIIIIIIIIIIIIIIIIIIIIIIIIIIOOOIIIIIIIIIIIIOOIOOOOIOOOOIOOOOIOOOO changed: 1 00 step 554 000000000000000000000000000011111000001000100000110001100100100110 fail ^ SLOT BBBBBBBBBBBBBBBBBBBBBBBBBBBBBBAAAAAAAAAAAAABAAAAAAAAAAAAAAAAAABBAA LETTER EHJFHNCEDFDNLMPLKMPRSURVVTSUJKEFADDBCHJEFHBBJKKMMLLNRPPNRUTSSUBAVV SIDE 222112112211122211122211221112211211122121221211212221211221211121 DIRECTION IIIIIIIIIIIIIIIIIIIIIIIIIIIIIOOOIIIIIIIIIIIIOOIOOOOIOOOOIOOOOIOOOO changed: 110 step 555 000000000000000000000000000011111000001000100000110110100100100110 fail ^ ^^ SLOT BBBBBBBBBBBBBBBBBBBBBBBBBBBBBBAAAAAAAAAAAAABAAAAAAAAAAAAAAAAAABBAA LETTER EHJFHNCEDFDNLMPLKMPRSURVVTSUJKEFADDBCHJEFHBBJKKMMLLNRPPNRUTSSUBAVV SIDE 222112112211122211122211221112211211122121221211212221211221211121 DIRECTION IIIIIIIIIIIIIIIIIIIIIIIIIIIIIOOOIIIIIIIIIIIIOOIOOOOIOOOOIOOOOIOOOO changed: 0 step 556 000000000000000000000000000011111000001000100000110010100100100110 fail ^ ^^ SLOT BBBBBBBBBBBBBBBBBBBBBBBBBBBBBBAAAAAAAAAAAAABAAAAAAAAAAAAAAAAAABBAA LETTER EHJFHNCEDFDNLMPLKMPRSURVVTSUJKEFADDBCHJEFHBBJKKMMLLNRPPNRUTSSUBAVV SIDE 222112112211122211122211221112211211122121221211212221211221211121 DIRECTION IIIIIIIIIIIIIIIIIIIIIIIIIIIIIOOOIIIIIIIIIIIIOOIOOOOIOOOOIOOOOIOOOO changed: 0 11 step 557 000000000000000000000000000011110000001000101100110010100100100110 fail ^^ SLOT BBBBBBBBBBBBBBBBBBBBBBBBBBBBBBAAAAAAAAAAAAABAAAAAAAAAAAAAAAAAABBAA LETTER EHJFHNCEDFDNLMPLKMPRSURVVTSUJKEFADDBCHJEFHBBJKKMMLLNRPPNRUTSSUBAVV SIDE 222112112211122211122211221112211211122121221211212221211221211121 DIRECTION IIIIIIIIIIIIIIIIIIIIIIIIIIIIIOOOIIIIIIIIIIIIOOIOOOOIOOOOIOOOOIOOOO changed: 1 0 step 558 000000000000000000000000000011110000001001101000110010100100100110 fail ^^ step 559 000000000000000000000000000011110000001001101000110101100100100110 step 560 000000000000000000000000000011110000001001101000110001100100100110 step 561 000000000000000000000000000011110000001000101100110001100100100110 SLOT BBBBBBBBBBBBBBBBBBBBBBBBBBBBBBAAAAAAAAAAAAABAAAAAAAAAAAAAAAAAABBAA LETTER EHJFHNCEDFDNLMPLKMPRSURVVTSUJKEFADDBCHJEFHBBJKKMMLLNRPPNRUTSSUBAVV SIDE 222112112211122211122211221112211211122121221211212221211221211121 DIRECTION IIIIIIIIIIIIIIIIIIIIIIIIIIIIIOOOIIIIIIIIIIIIOOIOOOOIOOOOIOOOOIOOOO changed: 1 00 step 562 000000000000000000000000000011111000001000100000110001100100100110 fail ^ SLOT BBBBBBBBBBBBBBBBBBBBBBBBBBBBBBAAAAAAAAAAAAABAAAAAAAAAAAAAAAAAABBAA LETTER EHJFHNCEDFDNLMPLKMPRSURVVTSUJKEFADDBCHJEFHBBJKKMMLLNRPPNRUTSSUBAVV SIDE 222112112211122211122211221112211211122121221211212221211221211121 DIRECTION IIIIIIIIIIIIIIIIIIIIIIIIIIIIIOOOIIIIIIIIIIIIOOIOOOOIOOOOIOOOOIOOOO changed: 1 10 step 563 000000000000000000000000000011111000001000100000110001101101000110 fail ^ ^^ SLOT BBBBBBBBBBBBBBBBBBBBBBBBBBBBBBAAAAAAAAAAAAABAAAAAAAAAAAAAAAAAABBAA LETTER EHJFHNCEDFDNLMPLKMPRSURVVTSUJKEFADDBCHJEFHBBJKKMMLLNRPPNRUTSSUBAVV SIDE 222112112211122211122211221112211211122121221211212221211221211121 DIRECTION IIIIIIIIIIIIIIIIIIIIIIIIIIIIIOOOIIIIIIIIIIIIOOIOOOOIOOOOIOOOOIOOOO changed: 0 step 564 000000000000000000000000000011111000001000100000110001100101000110 fail ^ ^^ SLOT BBBBBBBBBBBBBBBBBBBBBBBBBBBBBBAAAAAAAAAAAAABAAAAAAAAAAAAAAAAAABBAA LETTER EHJFHNCEDFDNLMPLKMPRSURVVTSUJKEFADDBCHJEFHBBJKKMMLLNRPPNRUTSSUBAVV SIDE 222112112211122211122211221112211211122121221211212221211221211121 DIRECTION IIIIIIIIIIIIIIIIIIIIIIIIIIIIIOOOIIIIIIIIIIIIOOIOOOOIOOOOIOOOOIOOOO changed: 110 step 565 000000000000000000000000000011111000001000100000110001100101011010 fail ^ ^^ ^^ SLOT BBBBBBBBBBBBBBBBBBBBBBBBBBBBBBAAAAAAAAAAAAABAAAAAAAAAAAAAAAAAABBAA LETTER EHJFHNCEDFDNLMPLKMPRSURVVTSUJKEFADDBCHJEFHBBJKKMMLLNRPPNRUTSSUBAVV SIDE 222112112211122211122211221112211211122121221211212221211221211121 DIRECTION IIIIIIIIIIIIIIIIIIIIIIIIIIIIIOOOIIIIIIIIIIIIOOIOOOOIOOOOIOOOOIOOOO changed: 0 step 566 000000000000000000000000000011111000001000100000110001100101001010 fail ^ ^^ ^^ SLOT BBBBBBBBBBBBBBBBBBBBBBBBBBBBBBAAAAAAAAAAAAABAAAAAAAAAAAAAAAAAABBAA LETTER EHJFHNCEDFDNLMPLKMPRSURVVTSUJKEFADDBCHJEFHBBJKKMMLLNRPPNRUTSSUBAVV SIDE 222112112211122211122211221112211211122121221211212221211221211121 DIRECTION IIIIIIIIIIIIIIIIIIIIIIIIIIIIIOOOIIIIIIIIIIIIOOIOOOOIOOOOIOOOOIOOOO changed: 0 11 step 567 000000000000000000000000000011110000001000101100110001100101001010 fail ^^ ^^ SLOT BBBBBBBBBBBBBBBBBBBBBBBBBBBBBBAAAAAAAAAAAAABAAAAAAAAAAAAAAAAAABBAA LETTER EHJFHNCEDFDNLMPLKMPRSURVVTSUJKEFADDBCHJEFHBBJKKMMLLNRPPNRUTSSUBAVV SIDE 222112112211122211122211221112211211122121221211212221211221211121 DIRECTION IIIIIIIIIIIIIIIIIIIIIIIIIIIIIOOOIIIIIIIIIIIIOOIOOOOIOOOOIOOOOIOOOO changed: 1 0 step 568 000000000000000000000000000011110000001001101000110001100101001010 fail ^^ ^^ SLOT BBBBBBBBBBBBBBBBBBBBBBBBBBBBBBAAAAAAAAAAAAABAAAAAAAAAAAAAAAAAABBAA LETTER EHJFHNCEDFDNLMPLKMPRSURVVTSUJKEFADDBCHJEFHBBJKKMMLLNRPPNRUTSSUBAVV SIDE 222112112211122211122211221112211211122121221211212221211221211121 DIRECTION IIIIIIIIIIIIIIIIIIIIIIIIIIIIIOOOIIIIIIIIIIIIOOIOOOOIOOOOIOOOOIOOOO changed: 101 step 569 000000000000000000000000000011110000001001101000110001100101010110 fail ^^ SLOT BBBBBBBBBBBBBBBBBBBBBBBBBBBBBBAAAAAAAAAAAAABAAAAAAAAAAAAAAAAAABBAA LETTER EHJFHNCEDFDNLMPLKMPRSURVVTSUJKEFADDBCHJEFHBBJKKMMLLNRPPNRUTSSUBAVV SIDE 222112112211122211122211221112211211122121221211212221211221211121 DIRECTION IIIIIIIIIIIIIIIIIIIIIIIIIIIIIOOOIIIIIIIIIIIIOOIOOOOIOOOOIOOOOIOOOO changed: 0 step 570 000000000000000000000000000011110000001001101000110001100101000110 fail ^^ SLOT BBBBBBBBBBBBBBBBBBBBBBBBBBBBBBAAAAAAAAAAAAABAAAAAAAAAAAAAAAAAABBAA LETTER EHJFHNCEDFDNLMPLKMPRSURVVTSUJKEFADDBCHJEFHBBJKKMMLLNRPPNRUTSSUBAVV SIDE 222112112211122211122211221112211211122121221211212221211221211121 DIRECTION IIIIIIIIIIIIIIIIIIIIIIIIIIIIIOOOIIIIIIIIIIIIOOIOOOOIOOOOIOOOOIOOOO changed: 0 1 step 571 000000000000000000000000000011110000001000101100110001100101000110 fail ^^ SLOT BBBBBBBBBBBBBBBBBBBBBBBBBBBBBBAAAAAAAAAAAAABAAAAAAAAAAAAAAAAAABBAA LETTER EHJFHNCEDFDNLMPLKMPRSURVVTSUJKEFADDBCHJEFHBBJKKMMLLNRPPNRUTSSUBAVV SIDE 222112112211122211122211221112211211122121221211212221211221211121 DIRECTION IIIIIIIIIIIIIIIIIIIIIIIIIIIIIOOOIIIIIIIIIIIIOOIOOOOIOOOOIOOOOIOOOO changed: 1 1 00 step 572 000000000000000000000000000011110000011001100000110001100101000110 fail ^^ step 573 000000000000000000000000000011110000011001100000110001101101000110 step 574 000000000000000000000000000011110000011001100000110001100101000110 step 575 000000000000000000000000000011110000000001101100110001100101000110 step 576 000000000000000000000000000011110000000001101110101101010101010101 step 577 000000000000000000000000000011110000000001101100101001010101000101 step 578 000000000000000000000000000011110000000000101100101001010101000101 step 579 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EHJFHNCEDFDNLMPLKMPRSURVVTSUJKEFADDBCHJEFHBBJKKMMLLNRPPNRUTSSUBAVV SIDE 222112112211122211122211221112211211122121221211212221211221211121 DIRECTION IIIIIIIIIIIIIIIIIIIIIIIIIIIIIOOOIIIIIIIIIIIIOOIOOOOIOOOOIOOOOIOOOO changed: 1 0 step 652 000110000000000000000000000011010000010000011101010010100101001010 fail ^^ SLOT BBBBBBBBBBBBBBBBBBBBBBBBBBBBBBAAAAAAAAAAAAABAAAAAAAAAAAAAAAAAABBAA LETTER EHJFHNCEDFDNLMPLKMPRSURVVTSUJKEFADDBCHJEFHBBJKKMMLLNRPPNRUTSSUBAVV SIDE 222112112211122211122211221112211211122121221211212221211221211121 DIRECTION IIIIIIIIIIIIIIIIIIIIIIIIIIIIIOOOIIIIIIIIIIIIOOIOOOOIOOOOIOOOOIOOOO changed: 1 0 step 653 000111000000000000000000000011000000010000011101010010100101001010 fail ^ SLOT BBBBBBBBBBBBBBBBBBBBBBBBBBBBBBAAAAAAAAAAAAABAAAAAAAAAAAAAAAAAABBAA LETTER EHJFHNCEDFDNLMPLKMPRSURVVTSUJKEFADDBCHJEFHBBJKKMMLLNRPPNRUTSSUBAVV SIDE 222112112211122211122211221112211211122121221211212221211221211121 DIRECTION IIIIIIIIIIIIIIIIIIIIIIIIIIIIIOOOIIIIIIIIIIIIOOIOOOOIOOOOIOOOOIOOOO changed: 0 1 step 654 000101000000000000000000000011100000010000011101010010100101001010 fail ^ step 655 000101000000000000000000000011100000010000001101010010100101001010 step 656 000111000000000000000000000011000000010000001101010010100101001010 SLOT BBBBBBBBBBBBBBBBBBBBBBBBBBBBBBAAAAAAAAAAAAABAAAAAAAAAAAAAAAAAABBAA LETTER EHJFHNCEDFDNLMPLKMPRSURVVTSUJKEFADDBCHJEFHBBJKKMMLLNRPPNRUTSSUBAVV SIDE 222112112211122211122211221112211211122121221211212221211221211121 DIRECTION IIIIIIIIIIIIIIIIIIIIIIIIIIIIIOOOIIIIIIIIIIIIOOIOOOOIOOOOIOOOOIOOOO changed: 0 1 step 657 000110000000000000000000000011010000010000001101010010100101001010 fail ^ SLOT BBBBBBBBBBBBBBBBBBBBBBBBBBBBBBAAAAAAAAAAAAABAAAAAAAAAAAAAAAAAABBAA LETTER EHJFHNCEDFDNLMPLKMPRSURVVTSUJKEFADDBCHJEFHBBJKKMMLLNRPPNRUTSSUBAVV SIDE 222112112211122211122211221112211211122121221211212221211221211121 DIRECTION IIIIIIIIIIIIIIIIIIIIIIIIIIIIIOOOIIIIIIIIIIIIOOIOOOOIOOOOIOOOOIOOOO changed: 0 1 step 658 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000000000000000000000000000000000000000000000000000000000000000000 total fails 8, total passes 0 space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn on comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit step 1 000000000000000000000000000011110000000000101101010010100101001010 step 2 000000000000000000000000000011110011100000100001010010100101001010 step 3 000000000000000000000000000011110011100000100011010110101101011010 step 4 000000000000000000000000000011110011100000100001010010100101001010 step 5 000000000000000000000000000011110011000000100101010010100101001010 step 6 000000000000000000000000000011110011000000100111001110011100111001 step 7 000000000000000000000000000011110011000000100101001010010100101001 step 8 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481 000000000000000000000000000011111000011000100011010010100010101010 fail ^^ ^^^^ SLOT BBBBBBBBBBBBBBBBBBBBBBBBBBBBBBAAAAAAAAAAAAABAAAAAAAAAAAAAAAAAABBAA LETTER EHJFHNCEDFDNLMPLKMPRSURVVTSUJKEFADDBCHJEFHBBJKKMMLLNRPPNRUTSSUBAVV SIDE 222112112211122211122211221112211211122121221211212221211221211121 DIRECTION IIIIIIIIIIIIIIIIIIIIIIIIIIIIIOOOIIIIIIIIIIIIOOIOOOOIOOOOIOOOOIOOOO changed: 0 step 482 000000000000000000000000000011111000011000100001010010100010101010 fail ^^ ^^^^ SLOT BBBBBBBBBBBBBBBBBBBBBBBBBBBBBBAAAAAAAAAAAAABAAAAAAAAAAAAAAAAAABBAA LETTER EHJFHNCEDFDNLMPLKMPRSURVVTSUJKEFADDBCHJEFHBBJKKMMLLNRPPNRUTSSUBAVV SIDE 222112112211122211122211221112211211122121221211212221211221211121 DIRECTION IIIIIIIIIIIIIIIIIIIIIIIIIIIIIOOOIIIIIIIIIIIIOOIOOOOIOOOOIOOOOIOOOO changed: 0 11 step 483 000000000000000000000000000011110000011000101101010010100010101010 fail ^^^^ SLOT BBBBBBBBBBBBBBBBBBBBBBBBBBBBBBAAAAAAAAAAAAABAAAAAAAAAAAAAAAAAABBAA LETTER EHJFHNCEDFDNLMPLKMPRSURVVTSUJKEFADDBCHJEFHBBJKKMMLLNRPPNRUTSSUBAVV SIDE 222112112211122211122211221112211211122121221211212221211221211121 DIRECTION IIIIIIIIIIIIIIIIIIIIIIIIIIIIIOOOIIIIIIIIIIIIOOIOOOOIOOOOIOOOOIOOOO changed: 1 00 step 484 000000000000000000000000000011110000011001100001010010100010101010 fail ^^^^ step 485 000000000000000000000000000011110000011001100011010010100010101010 step 486 000000000000000000000000000011110000011001100001010010100010101010 step 487 000000000000000000000000000011110000011000101101010010100010101010 SLOT BBBBBBBBBBBBBBBBBBBBBBBBBBBBBBAAAAAAAAAAAAABAAAAAAAAAAAAAAAAAABBAA LETTER EHJFHNCEDFDNLMPLKMPRSURVVTSUJKEFADDBCHJEFHBBJKKMMLLNRPPNRUTSSUBAVV SIDE 222112112211122211122211221112211211122121221211212221211221211121 DIRECTION IIIIIIIIIIIIIIIIIIIIIIIIIIIIIOOOIIIIIIIIIIIIOOIOOOOIOOOOIOOOOIOOOO changed: 1 00 step 488 000000000000000000000000000011111000011000100001010010100010101010 fail ^^ SLOT BBBBBBBBBBBBBBBBBBBBBBBBBBBBBBAAAAAAAAAAAAABAAAAAAAAAAAAAAAAAABBAA LETTER EHJFHNCEDFDNLMPLKMPRSURVVTSUJKEFADDBCHJEFHBBJKKMMLLNRPPNRUTSSUBAVV SIDE 222112112211122211122211221112211211122121221211212221211221211121 DIRECTION IIIIIIIIIIIIIIIIIIIIIIIIIIIIIOOOIIIIIIIIIIIIOOIOOOOIOOOOIOOOOIOOOO changed: 1 step 489 000000000000000000000000000011111000011000100001010110100010101010 fail ^^ ^^^^ SLOT BBBBBBBBBBBBBBBBBBBBBBBBBBBBBBAAAAAAAAAAAAABAAAAAAAAAAAAAAAAAABBAA LETTER EHJFHNCEDFDNLMPLKMPRSURVVTSUJKEFADDBCHJEFHBBJKKMMLLNRPPNRUTSSUBAVV SIDE 222112112211122211122211221112211211122121221211212221211221211121 DIRECTION IIIIIIIIIIIIIIIIIIIIIIIIIIIIIOOOIIIIIIIIIIIIOOIOOOOIOOOOIOOOOIOOOO changed: 0 step 490 000000000000000000000000000011111000011000100001010010100010101010 fail ^^ ^^^^ SLOT BBBBBBBBBBBBBBBBBBBBBBBBBBBBBBAAAAAAAAAAAAABAAAAAAAAAAAAAAAAAABBAA LETTER EHJFHNCEDFDNLMPLKMPRSURVVTSUJKEFADDBCHJEFHBBJKKMMLLNRPPNRUTSSUBAVV SIDE 222112112211122211122211221112211211122121221211212221211221211121 DIRECTION IIIIIIIIIIIIIIIIIIIIIIIIIIIIIOOOIIIIIIIIIIIIOOIOOOOIOOOOIOOOOIOOOO changed: 0 11 step 491 000000000000000000000000000011110000011000101101010010100010101010 fail ^^^^ SLOT BBBBBBBBBBBBBBBBBBBBBBBBBBBBBBAAAAAAAAAAAAABAAAAAAAAAAAAAAAAAABBAA LETTER EHJFHNCEDFDNLMPLKMPRSURVVTSUJKEFADDBCHJEFHBBJKKMMLLNRPPNRUTSSUBAVV SIDE 222112112211122211122211221112211211122121221211212221211221211121 DIRECTION IIIIIIIIIIIIIIIIIIIIIIIIIIIIIOOOIIIIIIIIIIIIOOIOOOOIOOOOIOOOOIOOOO changed: 1 00 step 492 000000000000000000000000000011110000011001100001010010100010101010 fail ^^^^ step 493 000000000000000000000000000011110000011001100001010110100010101010 step 494 000000000000000000000000000011110000011001100001010010100010101010 step 495 000000000000000000000000000011110000011000101101010010100010101010 SLOT BBBBBBBBBBBBBBBBBBBBBBBBBBBBBBAAAAAAAAAAAAABAAAAAAAAAAAAAAAAAABBAA LETTER EHJFHNCEDFDNLMPLKMPRSURVVTSUJKEFADDBCHJEFHBBJKKMMLLNRPPNRUTSSUBAVV SIDE 222112112211122211122211221112211211122121221211212221211221211121 DIRECTION IIIIIIIIIIIIIIIIIIIIIIIIIIIIIOOOIIIIIIIIIIIIOOIOOOOIOOOOIOOOOIOOOO changed: 1 00 step 496 000000000000000000000000000011111000011000100001010010100010101010 fail ^^ SLOT BBBBBBBBBBBBBBBBBBBBBBBBBBBBBBAAAAAAAAAAAAABAAAAAAAAAAAAAAAAAABBAA LETTER EHJFHNCEDFDNLMPLKMPRSURVVTSUJKEFADDBCHJEFHBBJKKMMLLNRPPNRUTSSUBAVV SIDE 222112112211122211122211221112211211122121221211212221211221211121 DIRECTION IIIIIIIIIIIIIIIIIIIIIIIIIIIIIOOOIIIIIIIIIIIIOOIOOOOIOOOOIOOOOIOOOO changed: 11010 step 497 000000000000000000000000000011111000011000100001010010101101001010 fail ^^ ^^^^ SLOT BBBBBBBBBBBBBBBBBBBBBBBBBBBBBBAAAAAAAAAAAAABAAAAAAAAAAAAAAAAAABBAA LETTER EHJFHNCEDFDNLMPLKMPRSURVVTSUJKEFADDBCHJEFHBBJKKMMLLNRPPNRUTSSUBAVV SIDE 222112112211122211122211221112211211122121221211212221211221211121 DIRECTION IIIIIIIIIIIIIIIIIIIIIIIIIIIIIOOOIIIIIIIIIIIIOOIOOOOIOOOOIOOOOIOOOO changed: 0 step 498 000000000000000000000000000011111000011000100001010010100101001010 fail ^^ ^^^^ SLOT BBBBBBBBBBBBBBBBBBBBBBBBBBBBBBAAAAAAAAAAAAABAAAAAAAAAAAAAAAAAABBAA LETTER EHJFHNCEDFDNLMPLKMPRSURVVTSUJKEFADDBCHJEFHBBJKKMMLLNRPPNRUTSSUBAVV SIDE 222112112211122211122211221112211211122121221211212221211221211121 DIRECTION IIIIIIIIIIIIIIIIIIIIIIIIIIIIIOOOIIIIIIIIIIIIOOIOOOOIOOOOIOOOOIOOOO changed: 1 step 499 000000000000000000000000000011111000011000100001010010100101011010 fail ^^ ^^^^ ^^^^ SLOT BBBBBBBBBBBBBBBBBBBBBBBBBBBBBBAAAAAAAAAAAAABAAAAAAAAAAAAAAAAAABBAA LETTER EHJFHNCEDFDNLMPLKMPRSURVVTSUJKEFADDBCHJEFHBBJKKMMLLNRPPNRUTSSUBAVV SIDE 222112112211122211122211221112211211122121221211212221211221211121 DIRECTION IIIIIIIIIIIIIIIIIIIIIIIIIIIIIOOOIIIIIIIIIIIIOOIOOOOIOOOOIOOOOIOOOO changed: 0 step 500 000000000000000000000000000011111000011000100001010010100101001010 fail ^^ ^^^^ ^^^^ SLOT BBBBBBBBBBBBBBBBBBBBBBBBBBBBBBAAAAAAAAAAAAABAAAAAAAAAAAAAAAAAABBAA LETTER EHJFHNCEDFDNLMPLKMPRSURVVTSUJKEFADDBCHJEFHBBJKKMMLLNRPPNRUTSSUBAVV SIDE 222112112211122211122211221112211211122121221211212221211221211121 DIRECTION IIIIIIIIIIIIIIIIIIIIIIIIIIIIIOOOIIIIIIIIIIIIOOIOOOOIOOOOIOOOOIOOOO changed: 0 11 step 501 000000000000000000000000000011110000011000101101010010100101001010 fail ^^^^ ^^^^ SLOT BBBBBBBBBBBBBBBBBBBBBBBBBBBBBBAAAAAAAAAAAAABAAAAAAAAAAAAAAAAAABBAA LETTER EHJFHNCEDFDNLMPLKMPRSURVVTSUJKEFADDBCHJEFHBBJKKMMLLNRPPNRUTSSUBAVV SIDE 222112112211122211122211221112211211122121221211212221211221211121 DIRECTION IIIIIIIIIIIIIIIIIIIIIIIIIIIIIOOOIIIIIIIIIIIIOOIOOOOIOOOOIOOOOIOOOO changed: 1 00 step 502 000000000000000000000000000011110000011001100001010010100101001010 fail ^^^^ ^^^^ SLOT BBBBBBBBBBBBBBBBBBBBBBBBBBBBBBAAAAAAAAAAAAABAAAAAAAAAAAAAAAAAABBAA LETTER EHJFHNCEDFDNLMPLKMPRSURVVTSUJKEFADDBCHJEFHBBJKKMMLLNRPPNRUTSSUBAVV SIDE 222112112211122211122211221112211211122121221211212221211221211121 DIRECTION IIIIIIIIIIIIIIIIIIIIIIIIIIIIIOOOIIIIIIIIIIIIOOIOOOOIOOOOIOOOOIOOOO changed: 1 step 503 000000000000000000000000000011110000011001100001010010100101011010 fail ^^^^ SLOT BBBBBBBBBBBBBBBBBBBBBBBBBBBBBBAAAAAAAAAAAAABAAAAAAAAAAAAAAAAAABBAA LETTER EHJFHNCEDFDNLMPLKMPRSURVVTSUJKEFADDBCHJEFHBBJKKMMLLNRPPNRUTSSUBAVV SIDE 222112112211122211122211221112211211122121221211212221211221211121 DIRECTION IIIIIIIIIIIIIIIIIIIIIIIIIIIIIOOOIIIIIIIIIIIIOOIOOOOIOOOOIOOOOIOOOO changed: 0 step 504 000000000000000000000000000011110000011001100001010010100101001010 fail ^^^^ SLOT BBBBBBBBBBBBBBBBBBBBBBBBBBBBBBAAAAAAAAAAAAABAAAAAAAAAAAAAAAAAABBAA LETTER EHJFHNCEDFDNLMPLKMPRSURVVTSUJKEFADDBCHJEFHBBJKKMMLLNRPPNRUTSSUBAVV SIDE 222112112211122211122211221112211211122121221211212221211221211121 DIRECTION IIIIIIIIIIIIIIIIIIIIIIIIIIIIIOOOIIIIIIIIIIIIOOIOOOOIOOOOIOOOOIOOOO changed: 0 11 step 505 000000000000000000000000000011110000011000101101010010100101001010 fail ^^^^ SLOT BBBBBBBBBBBBBBBBBBBBBBBBBBBBBBAAAAAAAAAAAAABAAAAAAAAAAAAAAAAAABBAA LETTER EHJFHNCEDFDNLMPLKMPRSURVVTSUJKEFADDBCHJEFHBBJKKMMLLNRPPNRUTSSUBAVV SIDE 222112112211122211122211221112211211122121221211212221211221211121 DIRECTION IIIIIIIIIIIIIIIIIIIIIIIIIIIIIOOOIIIIIIIIIIIIOOIOOOOIOOOOIOOOOIOOOO changed: 0 1 0 step 506 000000000000000000000000000011110000001001101001010010100101001010 fail ^^^^ step 507 000000000000000000000000000011110000001001101001010010101011001010 step 508 000000000000000000000000000011110000001001101001010010100011001010 step 509 000000000000000000000000000011110000010001100101010010100011001010 step 510 000000000000000000000000000011110000010001100111001110010011011001 step 511 000000000000000000000000000011110000010001100101001010010011001001 step 512 000000000000000000000000000011110000001000101101001010010011001001 SLOT BBBBBBBBBBBBBBBBBBBBBBBBBBBBBBAAAAAAAAAAAAABAAAAAAAAAAAAAAAAAABBAA LETTER EHJFHNCEDFDNLMPLKMPRSURVVTSUJKEFADDBCHJEFHBBJKKMMLLNRPPNRUTSSUBAVV SIDE 222112112211122211122211221112211211122121221211212221211221211121 DIRECTION IIIIIIIIIIIIIIIIIIIIIIIIIIIIIOOOIIIIIIIIIIIIOOIOOOOIOOOOIOOOOIOOOO changed: 1 00 step 513 000000000000000000000000000011111000001000100001001010010011001001 fail ^ SLOT BBBBBBBBBBBBBBBBBBBBBBBBBBBBBBAAAAAAAAAAAAABAAAAAAAAAAAAAAAAAABBAA LETTER EHJFHNCEDFDNLMPLKMPRSURVVTSUJKEFADDBCHJEFHBBJKKMMLLNRPPNRUTSSUBAVV SIDE 222112112211122211122211221112211211122121221211212221211221211121 DIRECTION IIIIIIIIIIIIIIIIIIIIIIIIIIIIIOOOIIIIIIIIIIIIOOIOOOOIOOOOIOOOOIOOOO changed: 1 10 step 514 000000000000000000000000000011111000001000100011010010010011001001 fail ^ ^^ SLOT BBBBBBBBBBBBBBBBBBBBBBBBBBBBBBAAAAAAAAAAAAABAAAAAAAAAAAAAAAAAABBAA LETTER EHJFHNCEDFDNLMPLKMPRSURVVTSUJKEFADDBCHJEFHBBJKKMMLLNRPPNRUTSSUBAVV SIDE 222112112211122211122211221112211211122121221211212221211221211121 DIRECTION IIIIIIIIIIIIIIIIIIIIIIIIIIIIIOOOIIIIIIIIIIIIOOIOOOOIOOOOIOOOOIOOOO changed: 0 step 515 000000000000000000000000000011111000001000100001010010010011001001 fail ^ ^^ SLOT BBBBBBBBBBBBBBBBBBBBBBBBBBBBBBAAAAAAAAAAAAABAAAAAAAAAAAAAAAAAABBAA LETTER EHJFHNCEDFDNLMPLKMPRSURVVTSUJKEFADDBCHJEFHBBJKKMMLLNRPPNRUTSSUBAVV SIDE 222112112211122211122211221112211211122121221211212221211221211121 DIRECTION IIIIIIIIIIIIIIIIIIIIIIIIIIIIIOOOIIIIIIIIIIIIOOIOOOOIOOOOIOOOOIOOOO changed: 0 11 step 516 000000000000000000000000000011110000001000101101010010010011001001 fail ^^ SLOT BBBBBBBBBBBBBBBBBBBBBBBBBBBBBBAAAAAAAAAAAAABAAAAAAAAAAAAAAAAAABBAA LETTER EHJFHNCEDFDNLMPLKMPRSURVVTSUJKEFADDBCHJEFHBBJKKMMLLNRPPNRUTSSUBAVV SIDE 222112112211122211122211221112211211122121221211212221211221211121 DIRECTION IIIIIIIIIIIIIIIIIIIIIIIIIIIIIOOOIIIIIIIIIIIIOOIOOOOIOOOOIOOOOIOOOO changed: 10 1 0 step 517 000000000000000000000000000011110000010001100101010010010011001001 fail ^^ step 518 000000000000000000000000000011110000010001100111001010010011001001 step 519 000000000000000000000000000011110000010001100101001010010011001001 step 520 000000000000000000000000000011110000010000101101001010010011001001 SLOT BBBBBBBBBBBBBBBBBBBBBBBBBBBBBBAAAAAAAAAAAAABAAAAAAAAAAAAAAAAAABBAA LETTER EHJFHNCEDFDNLMPLKMPRSURVVTSUJKEFADDBCHJEFHBBJKKMMLLNRPPNRUTSSUBAVV SIDE 222112112211122211122211221112211211122121221211212221211221211121 DIRECTION IIIIIIIIIIIIIIIIIIIIIIIIIIIIIOOOIIIIIIIIIIIIOOIOOOOIOOOOIOOOOIOOOO changed: 1 00 step 521 000000000000000000000000000011111000010000100001001010010011001001 fail ^ SLOT BBBBBBBBBBBBBBBBBBBBBBBBBBBBBBAAAAAAAAAAAAABAAAAAAAAAAAAAAAAAABBAA LETTER EHJFHNCEDFDNLMPLKMPRSURVVTSUJKEFADDBCHJEFHBBJKKMMLLNRPPNRUTSSUBAVV SIDE 222112112211122211122211221112211211122121221211212221211221211121 DIRECTION IIIIIIIIIIIIIIIIIIIIIIIIIIIIIOOOIIIIIIIIIIIIOOIOOOOIOOOOIOOOOIOOOO changed: 1 10 step 522 000000000000000000000000000011111000010000100001001110100011001001 fail ^ ^^ SLOT BBBBBBBBBBBBBBBBBBBBBBBBBBBBBBAAAAAAAAAAAAABAAAAAAAAAAAAAAAAAABBAA LETTER EHJFHNCEDFDNLMPLKMPRSURVVTSUJKEFADDBCHJEFHBBJKKMMLLNRPPNRUTSSUBAVV SIDE 222112112211122211122211221112211211122121221211212221211221211121 DIRECTION IIIIIIIIIIIIIIIIIIIIIIIIIIIIIOOOIIIIIIIIIIIIOOIOOOOIOOOOIOOOOIOOOO changed: 0 step 523 000000000000000000000000000011111000010000100001001010100011001001 fail ^ ^^ SLOT BBBBBBBBBBBBBBBBBBBBBBBBBBBBBBAAAAAAAAAAAAABAAAAAAAAAAAAAAAAAABBAA LETTER EHJFHNCEDFDNLMPLKMPRSURVVTSUJKEFADDBCHJEFHBBJKKMMLLNRPPNRUTSSUBAVV SIDE 222112112211122211122211221112211211122121221211212221211221211121 DIRECTION IIIIIIIIIIIIIIIIIIIIIIIIIIIIIOOOIIIIIIIIIIIIOOIOOOOIOOOOIOOOOIOOOO changed: 0 11 step 524 000000000000000000000000000011110000010000101101001010100011001001 fail ^^ SLOT BBBBBBBBBBBBBBBBBBBBBBBBBBBBBBAAAAAAAAAAAAABAAAAAAAAAAAAAAAAAABBAA LETTER EHJFHNCEDFDNLMPLKMPRSURVVTSUJKEFADDBCHJEFHBBJKKMMLLNRPPNRUTSSUBAVV SIDE 222112112211122211122211221112211211122121221211212221211221211121 DIRECTION IIIIIIIIIIIIIIIIIIIIIIIIIIIIIOOOIIIIIIIIIIIIOOIOOOOIOOOOIOOOOIOOOO changed: 1 0 step 525 000000000000000000000000000011110000010001100101001010100011001001 fail ^^ step 526 000000000000000000000000000011110000010001100101001110010011001001 step 527 000000000000000000000000000011110000010001100101001010010011001001 step 528 000000000000000000000000000011110000010000101101001010010011001001 SLOT BBBBBBBBBBBBBBBBBBBBBBBBBBBBBBAAAAAAAAAAAAABAAAAAAAAAAAAAAAAAABBAA LETTER EHJFHNCEDFDNLMPLKMPRSURVVTSUJKEFADDBCHJEFHBBJKKMMLLNRPPNRUTSSUBAVV SIDE 222112112211122211122211221112211211122121221211212221211221211121 DIRECTION IIIIIIIIIIIIIIIIIIIIIIIIIIIIIOOOIIIIIIIIIIIIOOIOOOOIOOOOIOOOOIOOOO changed: 1 00 step 529 000000000000000000000000000011111000010000100001001010010011001001 fail ^ SLOT BBBBBBBBBBBBBBBBBBBBBBBBBBBBBBAAAAAAAAAAAAABAAAAAAAAAAAAAAAAAABBAA LETTER EHJFHNCEDFDNLMPLKMPRSURVVTSUJKEFADDBCHJEFHBBJKKMMLLNRPPNRUTSSUBAVV SIDE 222112112211122211122211221112211211122121221211212221211221211121 DIRECTION IIIIIIIIIIIIIIIIIIIIIIIIIIIIIOOOIIIIIIIIIIIIOOIOOOOIOOOOIOOOOIOOOO changed: 110 step 530 000000000000000000000000000011111000010000100001001010011101001001 fail ^ ^^ SLOT BBBBBBBBBBBBBBBBBBBBBBBBBBBBBBAAAAAAAAAAAAABAAAAAAAAAAAAAAAAAABBAA LETTER EHJFHNCEDFDNLMPLKMPRSURVVTSUJKEFADDBCHJEFHBBJKKMMLLNRPPNRUTSSUBAVV SIDE 222112112211122211122211221112211211122121221211212221211221211121 DIRECTION IIIIIIIIIIIIIIIIIIIIIIIIIIIIIOOOIIIIIIIIIIIIOOIOOOOIOOOOIOOOOIOOOO changed: 0 step 531 000000000000000000000000000011111000010000100001001010010101001001 fail ^ ^^ SLOT BBBBBBBBBBBBBBBBBBBBBBBBBBBBBBAAAAAAAAAAAAABAAAAAAAAAAAAAAAAAABBAA LETTER EHJFHNCEDFDNLMPLKMPRSURVVTSUJKEFADDBCHJEFHBBJKKMMLLNRPPNRUTSSUBAVV SIDE 222112112211122211122211221112211211122121221211212221211221211121 DIRECTION IIIIIIIIIIIIIIIIIIIIIIIIIIIIIOOOIIIIIIIIIIIIOOIOOOOIOOOOIOOOOIOOOO changed: 1 10 step 532 000000000000000000000000000011111000010000100001001010010101011010 fail ^ ^^ ^^ SLOT BBBBBBBBBBBBBBBBBBBBBBBBBBBBBBAAAAAAAAAAAAABAAAAAAAAAAAAAAAAAABBAA LETTER EHJFHNCEDFDNLMPLKMPRSURVVTSUJKEFADDBCHJEFHBBJKKMMLLNRPPNRUTSSUBAVV SIDE 222112112211122211122211221112211211122121221211212221211221211121 DIRECTION IIIIIIIIIIIIIIIIIIIIIIIIIIIIIOOOIIIIIIIIIIIIOOIOOOOIOOOOIOOOOIOOOO changed: 0 step 533 000000000000000000000000000011111000010000100001001010010101001010 fail ^ ^^ ^^ SLOT BBBBBBBBBBBBBBBBBBBBBBBBBBBBBBAAAAAAAAAAAAABAAAAAAAAAAAAAAAAAABBAA LETTER EHJFHNCEDFDNLMPLKMPRSURVVTSUJKEFADDBCHJEFHBBJKKMMLLNRPPNRUTSSUBAVV SIDE 222112112211122211122211221112211211122121221211212221211221211121 DIRECTION IIIIIIIIIIIIIIIIIIIIIIIIIIIIIOOOIIIIIIIIIIIIOOIOOOOIOOOOIOOOOIOOOO changed: 0 11 step 534 000000000000000000000000000011110000010000101101001010010101001010 fail ^^ ^^ SLOT BBBBBBBBBBBBBBBBBBBBBBBBBBBBBBAAAAAAAAAAAAABAAAAAAAAAAAAAAAAAABBAA LETTER EHJFHNCEDFDNLMPLKMPRSURVVTSUJKEFADDBCHJEFHBBJKKMMLLNRPPNRUTSSUBAVV SIDE 222112112211122211122211221112211211122121221211212221211221211121 DIRECTION IIIIIIIIIIIIIIIIIIIIIIIIIIIIIOOOIIIIIIIIIIIIOOIOOOOIOOOOIOOOOIOOOO changed: 1 0 step 535 000000000000000000000000000011110000010001100101001010010101001010 fail ^^ ^^ SLOT BBBBBBBBBBBBBBBBBBBBBBBBBBBBBBAAAAAAAAAAAAABAAAAAAAAAAAAAAAAAABBAA LETTER EHJFHNCEDFDNLMPLKMPRSURVVTSUJKEFADDBCHJEFHBBJKKMMLLNRPPNRUTSSUBAVV SIDE 222112112211122211122211221112211211122121221211212221211221211121 DIRECTION IIIIIIIIIIIIIIIIIIIIIIIIIIIIIOOOIIIIIIIIIIIIOOIOOOOIOOOOIOOOOIOOOO changed: 1 01 step 536 000000000000000000000000000011110000010001100101001010010101011001 fail ^^ SLOT BBBBBBBBBBBBBBBBBBBBBBBBBBBBBBAAAAAAAAAAAAABAAAAAAAAAAAAAAAAAABBAA LETTER EHJFHNCEDFDNLMPLKMPRSURVVTSUJKEFADDBCHJEFHBBJKKMMLLNRPPNRUTSSUBAVV SIDE 222112112211122211122211221112211211122121221211212221211221211121 DIRECTION IIIIIIIIIIIIIIIIIIIIIIIIIIIIIOOOIIIIIIIIIIIIOOIOOOOIOOOOIOOOOIOOOO changed: 0 step 537 000000000000000000000000000011110000010001100101001010010101001001 fail ^^ SLOT BBBBBBBBBBBBBBBBBBBBBBBBBBBBBBAAAAAAAAAAAAABAAAAAAAAAAAAAAAAAABBAA LETTER EHJFHNCEDFDNLMPLKMPRSURVVTSUJKEFADDBCHJEFHBBJKKMMLLNRPPNRUTSSUBAVV SIDE 222112112211122211122211221112211211122121221211212221211221211121 DIRECTION IIIIIIIIIIIIIIIIIIIIIIIIIIIIIOOOIIIIIIIIIIIIOOIOOOOIOOOOIOOOOIOOOO changed: 0 1 step 538 000000000000000000000000000011110000010000101101001010010101001001 fail ^^ SLOT BBBBBBBBBBBBBBBBBBBBBBBBBBBBBBAAAAAAAAAAAAABAAAAAAAAAAAAAAAAAABBAA LETTER EHJFHNCEDFDNLMPLKMPRSURVVTSUJKEFADDBCHJEFHBBJKKMMLLNRPPNRUTSSUBAVV SIDE 222112112211122211122211221112211211122121221211212221211221211121 DIRECTION IIIIIIIIIIIIIIIIIIIIIIIIIIIIIOOOIIIIIIIIIIIIOOIOOOOIOOOOIOOOOIOOOO changed: 1 0 step 539 000000000000000000000000000011110000010001100101001010010101001001 fail ^^ step 540 000000000000000000000000000011110000010001100101001010011100101001 step 541 000000000000000000000000000011110000010001100101001010010100101001 step 542 000000000000000000000000000011110000001001101001001010010100101001 step 543 000000000000000000000000000011110000001001101010110101100100110110 step 544 000000000000000000000000000011110000001001101000110001100100100110 step 545 000000000000000000000000000011110000001000101100110001100100100110 SLOT BBBBBBBBBBBBBBBBBBBBBBBBBBBBBBAAAAAAAAAAAAABAAAAAAAAAAAAAAAAAABBAA LETTER EHJFHNCEDFDNLMPLKMPRSURVVTSUJKEFADDBCHJEFHBBJKKMMLLNRPPNRUTSSUBAVV SIDE 222112112211122211122211221112211211122121221211212221211221211121 DIRECTION IIIIIIIIIIIIIIIIIIIIIIIIIIIIIOOOIIIIIIIIIIIIOOIOOOOIOOOOIOOOOIOOOO changed: 1 00 step 546 000000000000000000000000000011111000001000100000110001100100100110 fail ^ SLOT BBBBBBBBBBBBBBBBBBBBBBBBBBBBBBAAAAAAAAAAAAABAAAAAAAAAAAAAAAAAABBAA LETTER EHJFHNCEDFDNLMPLKMPRSURVVTSUJKEFADDBCHJEFHBBJKKMMLLNRPPNRUTSSUBAVV SIDE 222112112211122211122211221112211211122121221211212221211221211121 DIRECTION IIIIIIIIIIIIIIIIIIIIIIIIIIIIIOOOIIIIIIIIIIIIOOIOOOOIOOOOIOOOOIOOOO changed: 110 step 547 000000000000000000000000000011111000001000100011010001100100100110 fail ^ ^^ SLOT BBBBBBBBBBBBBBBBBBBBBBBBBBBBBBAAAAAAAAAAAAABAAAAAAAAAAAAAAAAAABBAA LETTER EHJFHNCEDFDNLMPLKMPRSURVVTSUJKEFADDBCHJEFHBBJKKMMLLNRPPNRUTSSUBAVV SIDE 222112112211122211122211221112211211122121221211212221211221211121 DIRECTION IIIIIIIIIIIIIIIIIIIIIIIIIIIIIOOOIIIIIIIIIIIIOOIOOOOIOOOOIOOOOIOOOO changed: 0 step 548 000000000000000000000000000011111000001000100001010001100100100110 fail ^ ^^ SLOT BBBBBBBBBBBBBBBBBBBBBBBBBBBBBBAAAAAAAAAAAAABAAAAAAAAAAAAAAAAAABBAA LETTER EHJFHNCEDFDNLMPLKMPRSURVVTSUJKEFADDBCHJEFHBBJKKMMLLNRPPNRUTSSUBAVV SIDE 222112112211122211122211221112211211122121221211212221211221211121 DIRECTION IIIIIIIIIIIIIIIIIIIIIIIIIIIIIOOOIIIIIIIIIIIIOOIOOOOIOOOOIOOOOIOOOO changed: 0 11 step 549 000000000000000000000000000011110000001000101101010001100100100110 fail ^^ SLOT BBBBBBBBBBBBBBBBBBBBBBBBBBBBBBAAAAAAAAAAAAABAAAAAAAAAAAAAAAAAABBAA LETTER EHJFHNCEDFDNLMPLKMPRSURVVTSUJKEFADDBCHJEFHBBJKKMMLLNRPPNRUTSSUBAVV SIDE 222112112211122211122211221112211211122121221211212221211221211121 DIRECTION IIIIIIIIIIIIIIIIIIIIIIIIIIIIIOOOIIIIIIIIIIIIOOIOOOOIOOOOIOOOOIOOOO changed: 1 0 step 550 000000000000000000000000000011110000001001101001010001100100100110 fail ^^ step 551 000000000000000000000000000011110000001001101010110001100100100110 step 552 000000000000000000000000000011110000001001101000110001100100100110 step 553 000000000000000000000000000011110000001000101100110001100100100110 SLOT BBBBBBBBBBBBBBBBBBBBBBBBBBBBBBAAAAAAAAAAAAABAAAAAAAAAAAAAAAAAABBAA LETTER EHJFHNCEDFDNLMPLKMPRSURVVTSUJKEFADDBCHJEFHBBJKKMMLLNRPPNRUTSSUBAVV SIDE 222112112211122211122211221112211211122121221211212221211221211121 DIRECTION IIIIIIIIIIIIIIIIIIIIIIIIIIIIIOOOIIIIIIIIIIIIOOIOOOOIOOOOIOOOOIOOOO changed: 1 00 step 554 000000000000000000000000000011111000001000100000110001100100100110 fail ^ SLOT BBBBBBBBBBBBBBBBBBBBBBBBBBBBBBAAAAAAAAAAAAABAAAAAAAAAAAAAAAAAABBAA LETTER EHJFHNCEDFDNLMPLKMPRSURVVTSUJKEFADDBCHJEFHBBJKKMMLLNRPPNRUTSSUBAVV SIDE 222112112211122211122211221112211211122121221211212221211221211121 DIRECTION IIIIIIIIIIIIIIIIIIIIIIIIIIIIIOOOIIIIIIIIIIIIOOIOOOOIOOOOIOOOOIOOOO changed: 110 step 555 000000000000000000000000000011111000001000100000110110100100100110 fail ^ ^^ SLOT BBBBBBBBBBBBBBBBBBBBBBBBBBBBBBAAAAAAAAAAAAABAAAAAAAAAAAAAAAAAABBAA LETTER EHJFHNCEDFDNLMPLKMPRSURVVTSUJKEFADDBCHJEFHBBJKKMMLLNRPPNRUTSSUBAVV SIDE 222112112211122211122211221112211211122121221211212221211221211121 DIRECTION IIIIIIIIIIIIIIIIIIIIIIIIIIIIIOOOIIIIIIIIIIIIOOIOOOOIOOOOIOOOOIOOOO changed: 0 step 556 000000000000000000000000000011111000001000100000110010100100100110 fail ^ ^^ SLOT BBBBBBBBBBBBBBBBBBBBBBBBBBBBBBAAAAAAAAAAAAABAAAAAAAAAAAAAAAAAABBAA LETTER EHJFHNCEDFDNLMPLKMPRSURVVTSUJKEFADDBCHJEFHBBJKKMMLLNRPPNRUTSSUBAVV SIDE 222112112211122211122211221112211211122121221211212221211221211121 DIRECTION IIIIIIIIIIIIIIIIIIIIIIIIIIIIIOOOIIIIIIIIIIIIOOIOOOOIOOOOIOOOOIOOOO changed: 0 11 step 557 000000000000000000000000000011110000001000101100110010100100100110 fail ^^ SLOT BBBBBBBBBBBBBBBBBBBBBBBBBBBBBBAAAAAAAAAAAAABAAAAAAAAAAAAAAAAAABBAA LETTER EHJFHNCEDFDNLMPLKMPRSURVVTSUJKEFADDBCHJEFHBBJKKMMLLNRPPNRUTSSUBAVV SIDE 222112112211122211122211221112211211122121221211212221211221211121 DIRECTION IIIIIIIIIIIIIIIIIIIIIIIIIIIIIOOOIIIIIIIIIIIIOOIOOOOIOOOOIOOOOIOOOO changed: 1 0 step 558 000000000000000000000000000011110000001001101000110010100100100110 fail ^^ step 559 000000000000000000000000000011110000001001101000110101100100100110 step 560 000000000000000000000000000011110000001001101000110001100100100110 step 561 000000000000000000000000000011110000001000101100110001100100100110 SLOT BBBBBBBBBBBBBBBBBBBBBBBBBBBBBBAAAAAAAAAAAAABAAAAAAAAAAAAAAAAAABBAA LETTER EHJFHNCEDFDNLMPLKMPRSURVVTSUJKEFADDBCHJEFHBBJKKMMLLNRPPNRUTSSUBAVV SIDE 222112112211122211122211221112211211122121221211212221211221211121 DIRECTION IIIIIIIIIIIIIIIIIIIIIIIIIIIIIOOOIIIIIIIIIIIIOOIOOOOIOOOOIOOOOIOOOO changed: 1 00 step 562 000000000000000000000000000011111000001000100000110001100100100110 fail ^ SLOT BBBBBBBBBBBBBBBBBBBBBBBBBBBBBBAAAAAAAAAAAAABAAAAAAAAAAAAAAAAAABBAA LETTER EHJFHNCEDFDNLMPLKMPRSURVVTSUJKEFADDBCHJEFHBBJKKMMLLNRPPNRUTSSUBAVV SIDE 222112112211122211122211221112211211122121221211212221211221211121 DIRECTION IIIIIIIIIIIIIIIIIIIIIIIIIIIIIOOOIIIIIIIIIIIIOOIOOOOIOOOOIOOOOIOOOO changed: 1 10 step 563 000000000000000000000000000011111000001000100000110001101101000110 fail ^ ^^ SLOT BBBBBBBBBBBBBBBBBBBBBBBBBBBBBBAAAAAAAAAAAAABAAAAAAAAAAAAAAAAAABBAA LETTER EHJFHNCEDFDNLMPLKMPRSURVVTSUJKEFADDBCHJEFHBBJKKMMLLNRPPNRUTSSUBAVV SIDE 222112112211122211122211221112211211122121221211212221211221211121 DIRECTION IIIIIIIIIIIIIIIIIIIIIIIIIIIIIOOOIIIIIIIIIIIIOOIOOOOIOOOOIOOOOIOOOO changed: 0 step 564 000000000000000000000000000011111000001000100000110001100101000110 fail ^ ^^ SLOT BBBBBBBBBBBBBBBBBBBBBBBBBBBBBBAAAAAAAAAAAAABAAAAAAAAAAAAAAAAAABBAA LETTER EHJFHNCEDFDNLMPLKMPRSURVVTSUJKEFADDBCHJEFHBBJKKMMLLNRPPNRUTSSUBAVV SIDE 222112112211122211122211221112211211122121221211212221211221211121 DIRECTION IIIIIIIIIIIIIIIIIIIIIIIIIIIIIOOOIIIIIIIIIIIIOOIOOOOIOOOOIOOOOIOOOO changed: 110 step 565 000000000000000000000000000011111000001000100000110001100101011010 fail ^ ^^ ^^ SLOT BBBBBBBBBBBBBBBBBBBBBBBBBBBBBBAAAAAAAAAAAAABAAAAAAAAAAAAAAAAAABBAA LETTER EHJFHNCEDFDNLMPLKMPRSURVVTSUJKEFADDBCHJEFHBBJKKMMLLNRPPNRUTSSUBAVV SIDE 222112112211122211122211221112211211122121221211212221211221211121 DIRECTION IIIIIIIIIIIIIIIIIIIIIIIIIIIIIOOOIIIIIIIIIIIIOOIOOOOIOOOOIOOOOIOOOO changed: 0 step 566 000000000000000000000000000011111000001000100000110001100101001010 fail ^ ^^ ^^ SLOT BBBBBBBBBBBBBBBBBBBBBBBBBBBBBBAAAAAAAAAAAAABAAAAAAAAAAAAAAAAAABBAA LETTER EHJFHNCEDFDNLMPLKMPRSURVVTSUJKEFADDBCHJEFHBBJKKMMLLNRPPNRUTSSUBAVV SIDE 222112112211122211122211221112211211122121221211212221211221211121 DIRECTION IIIIIIIIIIIIIIIIIIIIIIIIIIIIIOOOIIIIIIIIIIIIOOIOOOOIOOOOIOOOOIOOOO changed: 0 11 step 567 000000000000000000000000000011110000001000101100110001100101001010 fail ^^ ^^ SLOT BBBBBBBBBBBBBBBBBBBBBBBBBBBBBBAAAAAAAAAAAAABAAAAAAAAAAAAAAAAAABBAA LETTER EHJFHNCEDFDNLMPLKMPRSURVVTSUJKEFADDBCHJEFHBBJKKMMLLNRPPNRUTSSUBAVV SIDE 222112112211122211122211221112211211122121221211212221211221211121 DIRECTION IIIIIIIIIIIIIIIIIIIIIIIIIIIIIOOOIIIIIIIIIIIIOOIOOOOIOOOOIOOOOIOOOO changed: 1 0 step 568 000000000000000000000000000011110000001001101000110001100101001010 fail ^^ ^^ SLOT BBBBBBBBBBBBBBBBBBBBBBBBBBBBBBAAAAAAAAAAAAABAAAAAAAAAAAAAAAAAABBAA LETTER EHJFHNCEDFDNLMPLKMPRSURVVTSUJKEFADDBCHJEFHBBJKKMMLLNRPPNRUTSSUBAVV SIDE 222112112211122211122211221112211211122121221211212221211221211121 DIRECTION IIIIIIIIIIIIIIIIIIIIIIIIIIIIIOOOIIIIIIIIIIIIOOIOOOOIOOOOIOOOOIOOOO changed: 101 step 569 000000000000000000000000000011110000001001101000110001100101010110 fail ^^ SLOT BBBBBBBBBBBBBBBBBBBBBBBBBBBBBBAAAAAAAAAAAAABAAAAAAAAAAAAAAAAAABBAA LETTER EHJFHNCEDFDNLMPLKMPRSURVVTSUJKEFADDBCHJEFHBBJKKMMLLNRPPNRUTSSUBAVV SIDE 222112112211122211122211221112211211122121221211212221211221211121 DIRECTION IIIIIIIIIIIIIIIIIIIIIIIIIIIIIOOOIIIIIIIIIIIIOOIOOOOIOOOOIOOOOIOOOO changed: 0 step 570 000000000000000000000000000011110000001001101000110001100101000110 fail ^^ SLOT BBBBBBBBBBBBBBBBBBBBBBBBBBBBBBAAAAAAAAAAAAABAAAAAAAAAAAAAAAAAABBAA LETTER EHJFHNCEDFDNLMPLKMPRSURVVTSUJKEFADDBCHJEFHBBJKKMMLLNRPPNRUTSSUBAVV SIDE 222112112211122211122211221112211211122121221211212221211221211121 DIRECTION IIIIIIIIIIIIIIIIIIIIIIIIIIIIIOOOIIIIIIIIIIIIOOIOOOOIOOOOIOOOOIOOOO changed: 0 1 step 571 000000000000000000000000000011110000001000101100110001100101000110 fail ^^ SLOT BBBBBBBBBBBBBBBBBBBBBBBBBBBBBBAAAAAAAAAAAAABAAAAAAAAAAAAAAAAAABBAA LETTER EHJFHNCEDFDNLMPLKMPRSURVVTSUJKEFADDBCHJEFHBBJKKMMLLNRPPNRUTSSUBAVV SIDE 222112112211122211122211221112211211122121221211212221211221211121 DIRECTION IIIIIIIIIIIIIIIIIIIIIIIIIIIIIOOOIIIIIIIIIIIIOOIOOOOIOOOOIOOOOIOOOO changed: 1 1 00 step 572 000000000000000000000000000011110000011001100000110001100101000110 fail ^^ step 573 000000000000000000000000000011110000011001100000110001101101000110 step 574 000000000000000000000000000011110000011001100000110001100101000110 step 575 000000000000000000000000000011110000000001101100110001100101000110 step 576 000000000000000000000000000011110000000001101110101101010101010101 step 577 000000000000000000000000000011110000000001101100101001010101000101 step 578 000000000000000000000000000011110000000000101100101001010101000101 step 579 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000100000000000000000000000011110011100000100001010010100101001010 step 632 000100000000000000000000000011110011000000100101010010100101001010 step 633 000100000000000000000000000011110010100000101001010010100101001010 step 634 000100000000000000000000000011110010000000101101010010100101001010 step 635 000100000000000000000000000011110000000000101101010010100101001010 step 636 000100000000000000000000000011110000011001100001010010100101001010 step 637 000100000000000000000000000011110000010001100101010010100101001010 step 638 000100000000000000000000000011110000001001101001010010100101001010 step 639 000100000000000000000000000011110000000001101101010010100101001010 step 640 000100000000000000000000000011110000000000101101010010100101001010 step 641 000100000000000000000000000011110000010010100001010010100101001010 step 642 000110000000000000000000000011010000010010100001010010100101001010 step 643 000111000000000000000000000011000000010010101001010010100101001010 step 644 000101000000000000000000000011100000010010101001010010100101001010 step 645 000101000000000000000000000011100000000010101101010010100101001010 step 646 000111000000000000000000000011000000000010101101010010100101001010 step 647 000110000000000000000000000011010000000010100101010010100101001010 step 648 000100000000000000000000000011110000000010100101010010100101001010 step 649 000100000000000000000000000011110000000000101101010010100101001010 step 650 000100000000000000000000000011110000010000101101010010100101001010 SLOT BBBBBBBBBBBBBBBBBBBBBBBBBBBBBBAAAAAAAAAAAAABAAAAAAAAAAAAAAAAAABBAA LETTER EHJFHNCEDFDNLMPLKMPRSURVVTSUJKEFADDBCHJEFHBBJKKMMLLNRPPNRUTSSUBAVV SIDE 222112112211122211122211221112211211122121221211212221211221211121 DIRECTION IIIIIIIIIIIIIIIIIIIIIIIIIIIIIOOOIIIIIIIIIIIIOOIOOOOIOOOOIOOOOIOOOO changed: 01 step 651 000100000000000000000000000011110000010000011101010010100101001010 fail ^^ SLOT BBBBBBBBBBBBBBBBBBBBBBBBBBBBBBAAAAAAAAAAAAABAAAAAAAAAAAAAAAAAABBAA LETTER EHJFHNCEDFDNLMPLKMPRSURVVTSUJKEFADDBCHJEFHBBJKKMMLLNRPPNRUTSSUBAVV SIDE 222112112211122211122211221112211211122121221211212221211221211121 DIRECTION IIIIIIIIIIIIIIIIIIIIIIIIIIIIIOOOIIIIIIIIIIIIOOIOOOOIOOOOIOOOOIOOOO changed: 1 0 step 652 000110000000000000000000000011010000010000011101010010100101001010 fail ^^ SLOT BBBBBBBBBBBBBBBBBBBBBBBBBBBBBBAAAAAAAAAAAAABAAAAAAAAAAAAAAAAAABBAA LETTER EHJFHNCEDFDNLMPLKMPRSURVVTSUJKEFADDBCHJEFHBBJKKMMLLNRPPNRUTSSUBAVV SIDE 222112112211122211122211221112211211122121221211212221211221211121 DIRECTION IIIIIIIIIIIIIIIIIIIIIIIIIIIIIOOOIIIIIIIIIIIIOOIOOOOIOOOOIOOOOIOOOO changed: 1 0 step 653 000111000000000000000000000011000000010000011101010010100101001010 fail ^ SLOT BBBBBBBBBBBBBBBBBBBBBBBBBBBBBBAAAAAAAAAAAAABAAAAAAAAAAAAAAAAAABBAA LETTER EHJFHNCEDFDNLMPLKMPRSURVVTSUJKEFADDBCHJEFHBBJKKMMLLNRPPNRUTSSUBAVV SIDE 222112112211122211122211221112211211122121221211212221211221211121 DIRECTION IIIIIIIIIIIIIIIIIIIIIIIIIIIIIOOOIIIIIIIIIIIIOOIOOOOIOOOOIOOOOIOOOO changed: 0 1 step 654 000101000000000000000000000011100000010000011101010010100101001010 fail ^ step 655 000101000000000000000000000011100000010000001101010010100101001010 step 656 000111000000000000000000000011000000010000001101010010100101001010 SLOT BBBBBBBBBBBBBBBBBBBBBBBBBBBBBBAAAAAAAAAAAAABAAAAAAAAAAAAAAAAAABBAA LETTER EHJFHNCEDFDNLMPLKMPRSURVVTSUJKEFADDBCHJEFHBBJKKMMLLNRPPNRUTSSUBAVV SIDE 222112112211122211122211221112211211122121221211212221211221211121 DIRECTION IIIIIIIIIIIIIIIIIIIIIIIIIIIIIOOOIIIIIIIIIIIIOOIOOOOIOOOOIOOOOIOOOO changed: 0 1 step 657 000110000000000000000000000011010000010000001101010010100101001010 fail ^ SLOT BBBBBBBBBBBBBBBBBBBBBBBBBBBBBBAAAAAAAAAAAAABAAAAAAAAAAAAAAAAAABBAA LETTER EHJFHNCEDFDNLMPLKMPRSURVVTSUJKEFADDBCHJEFHBBJKKMMLLNRPPNRUTSSUBAVV SIDE 222112112211122211122211221112211211122121221211212221211221211121 DIRECTION IIIIIIIIIIIIIIIIIIIIIIIIIIIIIOOOIIIIIIIIIIIIOOIOOOOIOOOOIOOOOIOOOO changed: 0 1 step 658 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000000000000000000000000000011110011100000100011010110101101011010 step 1140 000000000000000000000000000011110011100000100001010010100101001010 step 1141 000000000000000000000000000011110000000000101101010010100101001010 step 1142 000000000000000000000000000011110000000000101101010010100101001010 test 9: *** FAIL *************************** 69 steps failed SLOT BBBBBBBBBBBBBBBBBBBBBBBBBBBBBBAAAAAAAAAAAAABAAAAAAAAAAAAAAAAAABBAA LETTER EHJFHNCEDFDNLMPLKMPRSURVVTSUJKEFADDBCHJEFHBBJKKMMLLNRPPNRUTSSUBAVV SIDE 222112112211122211122211221112211211122121221211212221211221211121 DIRECTION IIIIIIIIIIIIIIIIIIIIIIIIIIIIIOOOIIIIIIIIIIIIOOIOOOOIOOOOIOOOOIOOOO this fail OO OOOO OOOO OOOO OOOO all fails OO OOOO OOOO OOOO OOOO was hi 111111111111111111111111111111111111111111111111111111111111111111 rising ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ falling vvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvv was lo 000000000000000000000000000000000000000000000000000000000000000000 total fails 9, total passes 0 space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn on comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit comment_flag is 1 space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn off comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit source: ; all registers are unknown source: ; turn on C0, TT LINE SHIFT-N (C2,ADDER2,ADDER3 to 111) source: ; with no ENABLES, BUS2,BUS3 is 11 source: 00000000000000000000000000001111000000000010110XXXX0XXXX0XXXX0XXXX changed: step 1 000000000000000000000000000011110000000000101101010010100101001010 source: ; source: ; test all registers using SHIFT RIGHT TWICE path source: ; source: ; use SHIFT RIGHT TWICE, ADDER0, ADDER1 to setup BUS2,BUS3 source: 111 00 changed: 111 00 step 2 000000000000000000000000000011110011100000100001010010100101001010 source: ; set all registers to 00 source: 11010110101101011010 changed: 1 1 1 1 step 3 000000000000000000000000000011110011100000100011010110101101011010 source: 0 0 0 0 changed: 0 0 0 0 step 4 000000000000000000000000000011110011100000100001010010100101001010 source: ; set all registers to 01 source: 110 01 changed: 0 1 step 5 000000000000000000000000000011110011000000100101010010100101001010 source: 1 011 011 011 01 changed: 1 011 011 011 01 step 6 000000000000000000000000000011110011000000100111001110011100111001 source: 0 0 0 0 changed: 0 0 0 0 step 7 000000000000000000000000000011110011000000100101001010010100101001 source: ; set all registers to 11 source: 100 11 changed: 0 1 step 8 000000000000000000000000000011110010000000101101001010010100101001 source: 10101101011010110101 changed: 101 101 101 101 step 9 000000000000000000000000000011110010000000101110101101011010110101 source: 0 0 0 0 changed: 0 0 0 0 step 10 000000000000000000000000000011110010000000101100101001010010100101 source: ; set all registers to 01 source: 110 01 changed: 1 0 step 11 000000000000000000000000000011110011000000100100101001010010100101 source: 110 110 110 110 changed: 110 110 110 110 step 12 000000000000000000000000000011110011000000100111001110011100111001 source: 0 0 0 0 changed: 0 0 0 0 step 13 000000000000000000000000000011110011000000100101001010010100101001 source: ; set all registers to 00 source: 111 00 changed: 1 0 step 14 000000000000000000000000000011110011100000100001001010010100101001 source: 11010110101101011010 changed: 1 101 101 101 10 step 15 000000000000000000000000000011110011100000100011010110101101011010 source: 0 0 0 0 changed: 0 0 0 0 step 16 000000000000000000000000000011110011100000100001010010100101001010 source: ; remove SHIFT RIGHT TWICE, ADDER0, ADDER1 source: 000 11 changed: 000 11 step 17 000000000000000000000000000011110000000000101101010010100101001010 source: 000000000000000000000000000011110000000000101101010010100101001010 changed: step 18 000000000000000000000000000011110000000000101101010010100101001010 source: ; source: ; same tests, but use SHIFT LEFT TWICE path source: ; source: ; use SHIFT LEFT TWICE, ADDER4, ADDER5 to setup BUS2,BUS3 source: 11 1 00 changed: 11 1 00 step 19 000000000000000000000000000011110000011001100001010010100101001010 source: ; set all registers to 00 source: 11010110101101011010 changed: 1 1 1 1 step 20 000000000000000000000000000011110000011001100011010110101101011010 source: 0 0 0 0 changed: 0 0 0 0 step 21 000000000000000000000000000011110000011001100001010010100101001010 source: ; set all registers to 01 source: 10 1 01 changed: 0 1 step 22 000000000000000000000000000011110000010001100101010010100101001010 source: 1 011 011 011 01 changed: 1 011 011 011 01 step 23 000000000000000000000000000011110000010001100111001110011100111001 source: 0 0 0 0 changed: 0 0 0 0 step 24 000000000000000000000000000011110000010001100101001010010100101001 source: ; set all registers to 11 source: 00 1 11 changed: 0 1 step 25 000000000000000000000000000011110000000001101101001010010100101001 source: 10101101011010110101 changed: 101 101 101 101 step 26 000000000000000000000000000011110000000001101110101101011010110101 source: 0 0 0 0 changed: 0 0 0 0 step 27 000000000000000000000000000011110000000001101100101001010010100101 source: ; set all registers to 01 source: 10 1 01 changed: 1 0 step 28 000000000000000000000000000011110000010001100100101001010010100101 source: 110 110 110 110 changed: 110 110 110 110 step 29 000000000000000000000000000011110000010001100111001110011100111001 source: 0 0 0 0 changed: 0 0 0 0 step 30 000000000000000000000000000011110000010001100101001010010100101001 source: ; set all registers to 00 source: 11 1 00 changed: 1 0 step 31 000000000000000000000000000011110000011001100001001010010100101001 source: 11010110101101011010 changed: 1 101 101 101 10 step 32 000000000000000000000000000011110000011001100011010110101101011010 source: 0 0 0 0 changed: 0 0 0 0 step 33 000000000000000000000000000011110000011001100001010010100101001010 source: ; remove SHIFT LEFT TWICE, ADDER4, ADDER5 source: 00 0 11 changed: 00 0 11 step 34 000000000000000000000000000011110000000000101101010010100101001010 source: 000000000000000000000000000011110000000000101101010010100101001010 changed: step 35 000000000000000000000000000011110000000000101101010010100101001010 source: ; source: ; change each register individually (only one bit changes per strobe) source: ; source: ; use SHIFT RIGHT TWICE, ADDER0, ADDER1 to setup BUS2,BUS3 source: ; set each register to 00 source: 111 00 changed: 111 00 step 36 000000000000000000000000000011110011100000100001010010100101001010 source: 1 changed: 1 step 37 000000000000000000000000000011110011100000100011010010100101001010 source: 0 changed: 0 step 38 000000000000000000000000000011110011100000100001010010100101001010 source: 1 changed: 1 step 39 000000000000000000000000000011110011100000100001010110100101001010 source: 0 changed: 0 step 40 000000000000000000000000000011110011100000100001010010100101001010 source: 1 changed: 1 step 41 000000000000000000000000000011110011100000100001010010101101001010 source: 0 changed: 0 step 42 000000000000000000000000000011110011100000100001010010100101001010 source: 1 changed: 1 step 43 000000000000000000000000000011110011100000100001010010100101011010 source: 0 changed: 0 step 44 000000000000000000000000000011110011100000100001010010100101001010 source: ; set each register to 01 source: 110 01 changed: 0 1 step 45 000000000000000000000000000011110011000000100101010010100101001010 source: 1 01 changed: 1 01 step 46 000000000000000000000000000011110011000000100111001010100101001010 source: 0 changed: 0 step 47 000000000000000000000000000011110011000000100101001010100101001010 source: 1 01 changed: 1 01 step 48 000000000000000000000000000011110011000000100101001110010101001010 source: 0 changed: 0 step 49 000000000000000000000000000011110011000000100101001010010101001010 source: 1 01 changed: 1 01 step 50 000000000000000000000000000011110011000000100101001010011100101010 source: 0 changed: 0 step 51 000000000000000000000000000011110011000000100101001010010100101010 source: 1 01 changed: 1 01 step 52 000000000000000000000000000011110011000000100101001010010100111001 source: 0 changed: 0 step 53 000000000000000000000000000011110011000000100101001010010100101001 source: ; set each register to 11 source: 100 11 changed: 0 1 step 54 000000000000000000000000000011110010000000101101001010010100101001 source: 101 changed: 101 step 55 000000000000000000000000000011110010000000101110101010010100101001 source: 0 changed: 0 step 56 000000000000000000000000000011110010000000101100101010010100101001 source: 101 changed: 101 step 57 000000000000000000000000000011110010000000101100101101010100101001 source: 0 changed: 0 step 58 000000000000000000000000000011110010000000101100101001010100101001 source: 101 changed: 101 step 59 000000000000000000000000000011110010000000101100101001011010101001 source: 0 changed: 0 step 60 000000000000000000000000000011110010000000101100101001010010101001 source: 101 changed: 101 step 61 000000000000000000000000000011110010000000101100101001010010110101 source: 0 changed: 0 step 62 000000000000000000000000000011110010000000101100101001010010100101 source: ; set each register to 10 source: 101 10 changed: 1 0 step 63 000000000000000000000000000011110010100000101000101001010010100101 source: 1 10 changed: 1 10 step 64 000000000000000000000000000011110010100000101010110001010010100101 source: 0 changed: 0 step 65 000000000000000000000000000011110010100000101000110001010010100101 source: 1 10 changed: 1 10 step 66 000000000000000000000000000011110010100000101000110101100010100101 source: 0 changed: 0 step 67 000000000000000000000000000011110010100000101000110001100010100101 source: 1 10 changed: 1 10 step 68 000000000000000000000000000011110010100000101000110001101011000101 source: 0 changed: 0 step 69 000000000000000000000000000011110010100000101000110001100011000101 source: 1 10 changed: 1 10 step 70 000000000000000000000000000011110010100000101000110001100011010110 source: 0 changed: 0 step 71 000000000000000000000000000011110010100000101000110001100011000110 source: ; set each register to 00 source: 111 00 changed: 1 0 step 72 000000000000000000000000000011110011100000100000110001100011000110 source: 110 changed: 110 step 73 000000000000000000000000000011110011100000100011010001100011000110 source: 0 changed: 0 step 74 000000000000000000000000000011110011100000100001010001100011000110 source: 110 changed: 110 step 75 000000000000000000000000000011110011100000100001010110100011000110 source: 0 changed: 0 step 76 000000000000000000000000000011110011100000100001010010100011000110 source: 110 changed: 110 step 77 000000000000000000000000000011110011100000100001010010101101000110 source: 0 changed: 0 step 78 000000000000000000000000000011110011100000100001010010100101000110 source: 110 changed: 110 step 79 000000000000000000000000000011110011100000100001010010100101011010 source: 0 changed: 0 step 80 000000000000000000000000000011110011100000100001010010100101001010 source: ; all registers are 00 source: 000000000000000000000000000011110011100000100001010010100101001010 changed: step 81 000000000000000000000000000011110011100000100001010010100101001010 source: ; source: ; with all registers 00; change each register individually to 00,01,10,11 source: ; source: ; use SHIFT RIGHT TWICE, ADDER0, ADDER1 to setup BUS2,BUS3 source: ; change each regster to 00 and back to 00 source: 111 1 changed: 1 step 82 000000000000000000000000000011110011100000100011010010100101001010 source: 0 changed: 0 step 83 000000000000000000000000000011110011100000100001010010100101001010 source: 111 1 changed: 1 step 84 000000000000000000000000000011110011100000100001010110100101001010 source: 0 changed: 0 step 85 000000000000000000000000000011110011100000100001010010100101001010 source: 111 1 changed: 1 step 86 000000000000000000000000000011110011100000100001010010101101001010 source: 0 changed: 0 step 87 000000000000000000000000000011110011100000100001010010100101001010 source: 111 1 changed: 1 step 88 000000000000000000000000000011110011100000100001010010100101011010 source: 0 changed: 0 step 89 000000000000000000000000000011110011100000100001010010100101001010 source: ; change each register to 01 and back to 00 source: 110 01 changed: 0 1 step 90 000000000000000000000000000011110011000000100101010010100101001010 source: 1 01 changed: 1 01 step 91 000000000000000000000000000011110011000000100111001010100101001010 source: 0 changed: 0 step 92 000000000000000000000000000011110011000000100101001010100101001010 source: 111 00 changed: 1 0 step 93 000000000000000000000000000011110011100000100001001010100101001010 source: 1 10 changed: 1 10 step 94 000000000000000000000000000011110011100000100011010010100101001010 source: 0 changed: 0 step 95 000000000000000000000000000011110011100000100001010010100101001010 source: 110 01 changed: 0 1 step 96 000000000000000000000000000011110011000000100101010010100101001010 source: 1 01 changed: 1 01 step 97 000000000000000000000000000011110011000000100101010110010101001010 source: 0 changed: 0 step 98 000000000000000000000000000011110011000000100101010010010101001010 source: 111 00 changed: 1 0 step 99 000000000000000000000000000011110011100000100001010010010101001010 source: 1 10 changed: 1 10 step 100 000000000000000000000000000011110011100000100001010110100101001010 source: 0 changed: 0 step 101 000000000000000000000000000011110011100000100001010010100101001010 source: 110 01 changed: 0 1 step 102 000000000000000000000000000011110011000000100101010010100101001010 source: 1 01 changed: 1 01 step 103 000000000000000000000000000011110011000000100101010010101100101010 source: 0 changed: 0 step 104 000000000000000000000000000011110011000000100101010010100100101010 source: 111 00 changed: 1 0 step 105 000000000000000000000000000011110011100000100001010010100100101010 source: 1 10 changed: 1 10 step 106 000000000000000000000000000011110011100000100001010010101101001010 source: 0 changed: 0 step 107 000000000000000000000000000011110011100000100001010010100101001010 source: 110 01 changed: 0 1 step 108 000000000000000000000000000011110011000000100101010010100101001010 source: 1 01 changed: 1 01 step 109 000000000000000000000000000011110011000000100101010010100101011001 source: 0 changed: 0 step 110 000000000000000000000000000011110011000000100101010010100101001001 source: 111 00 changed: 1 0 step 111 000000000000000000000000000011110011100000100001010010100101001001 source: 1 10 changed: 1 10 step 112 000000000000000000000000000011110011100000100001010010100101011010 source: 0 changed: 0 step 113 000000000000000000000000000011110011100000100001010010100101001010 source: ; change each register to 10 and back to 00 source: 101 10 changed: 0 1 step 114 000000000000000000000000000011110010100000101001010010100101001010 source: 101 changed: 101 step 115 000000000000000000000000000011110010100000101010110010100101001010 source: 0 changed: 0 step 116 000000000000000000000000000011110010100000101000110010100101001010 source: 111 00 changed: 1 0 step 117 000000000000000000000000000011110011100000100000110010100101001010 source: 110 changed: 110 step 118 000000000000000000000000000011110011100000100011010010100101001010 source: 0 changed: 0 step 119 000000000000000000000000000011110011100000100001010010100101001010 source: 101 10 changed: 0 1 step 120 000000000000000000000000000011110010100000101001010010100101001010 source: 101 changed: 101 step 121 000000000000000000000000000011110010100000101001010101100101001010 source: 0 changed: 0 step 122 000000000000000000000000000011110010100000101001010001100101001010 source: 111 00 changed: 1 0 step 123 000000000000000000000000000011110011100000100001010001100101001010 source: 110 changed: 110 step 124 000000000000000000000000000011110011100000100001010110100101001010 source: 0 changed: 0 step 125 000000000000000000000000000011110011100000100001010010100101001010 source: 101 10 changed: 0 1 step 126 000000000000000000000000000011110010100000101001010010100101001010 source: 101 changed: 101 step 127 000000000000000000000000000011110010100000101001010010101011001010 source: 0 changed: 0 step 128 000000000000000000000000000011110010100000101001010010100011001010 source: 111 00 changed: 1 0 step 129 000000000000000000000000000011110011100000100001010010100011001010 source: 110 changed: 110 step 130 000000000000000000000000000011110011100000100001010010101101001010 source: 0 changed: 0 step 131 000000000000000000000000000011110011100000100001010010100101001010 source: 101 10 changed: 0 1 step 132 000000000000000000000000000011110010100000101001010010100101001010 source: 101 changed: 101 step 133 000000000000000000000000000011110010100000101001010010100101010110 source: 0 changed: 0 step 134 000000000000000000000000000011110010100000101001010010100101000110 source: 111 00 changed: 1 0 step 135 000000000000000000000000000011110011100000100001010010100101000110 source: 110 changed: 110 step 136 000000000000000000000000000011110011100000100001010010100101011010 source: 0 changed: 0 step 137 000000000000000000000000000011110011100000100001010010100101001010 source: ; change each register to 11 and back to 00 source: 100 11 changed: 00 11 step 138 000000000000000000000000000011110010000000101101010010100101001010 source: 1110101 changed: 10101 step 139 000000000000000000000000000011110010000000101110101010100101001010 source: 0 changed: 0 step 140 000000000000000000000000000011110010000000101100101010100101001010 source: 111 00 changed: 11 00 step 141 000000000000000000000000000011110011100000100000101010100101001010 source: 11010 changed: 11010 step 142 000000000000000000000000000011110011100000100011010010100101001010 source: 0 changed: 0 step 143 000000000000000000000000000011110011100000100001010010100101001010 source: 100 11 changed: 00 11 step 144 000000000000000000000000000011110010000000101101010010100101001010 source: 10101 changed: 10101 step 145 000000000000000000000000000011110010000000101101010101010101001010 source: 0 changed: 0 step 146 000000000000000000000000000011110010000000101101010001010101001010 source: 111 00 changed: 11 00 step 147 000000000000000000000000000011110011100000100001010001010101001010 source: 11010 changed: 11010 step 148 000000000000000000000000000011110011100000100001010110100101001010 source: 0 changed: 0 step 149 000000000000000000000000000011110011100000100001010010100101001010 source: 100 11 changed: 00 11 step 150 000000000000000000000000000011110010000000101101010010100101001010 source: 10101 changed: 10101 step 151 000000000000000000000000000011110010000000101101010010101010101010 source: 0 changed: 0 step 152 000000000000000000000000000011110010000000101101010010100010101010 source: 111 00 changed: 11 00 step 153 000000000000000000000000000011110011100000100001010010100010101010 source: 11010 changed: 11010 step 154 000000000000000000000000000011110011100000100001010010101101001010 source: 0 changed: 0 step 155 000000000000000000000000000011110011100000100001010010100101001010 source: 100 11 changed: 00 11 step 156 000000000000000000000000000011110010000000101101010010100101001010 source: 10101 changed: 10101 step 157 000000000000000000000000000011110010000000101101010010100101010101 source: 0 changed: 0 step 158 000000000000000000000000000011110010000000101101010010100101000101 source: 111 00 changed: 11 00 step 159 000000000000000000000000000011110011100000100001010010100101000101 source: 11010 changed: 11010 step 160 000000000000000000000000000011110011100000100001010010100101011010 source: 0 changed: 0 step 161 000000000000000000000000000011110011100000100001010010100101001010 source: ; all registers are 00 source: 000000000000000000000000000011110011100000100001010010100101001010 changed: step 162 000000000000000000000000000011110011100000100001010010100101001010 source: ; source: ; with all registers 01; change each register individually to 00,01,10,11 source: ; source: ; use SHIFT RIGHT TWICE, ADDER0, ADDER1 to setup BUS2,BUS3 source: ; set all registers to 01 source: 110 01 changed: 0 1 step 163 000000000000000000000000000011110011000000100101010010100101001010 source: 11001110011100111001 changed: 1 011 011 011 01 step 164 000000000000000000000000000011110011000000100111001110011100111001 source: 0 0 0 0 changed: 0 0 0 0 step 165 000000000000000000000000000011110011000000100101001010010100101001 source: ; all registers are 01 source: 000000000000000000000000000011110011000000100101001010010100101001 changed: step 166 000000000000000000000000000011110011000000100101001010010100101001 source: ; use SHIFT RIGHT TWICE, ADDER0, ADDER1 to setup BUS2,BUS3 source: ; set each register to 00 and back to 01 source: 111 00 changed: 1 0 step 167 000000000000000000000000000011110011100000100001001010010100101001 source: 1 10 changed: 1 10 step 168 000000000000000000000000000011110011100000100011010010010100101001 source: 0 changed: 0 step 169 000000000000000000000000000011110011100000100001010010010100101001 source: 110 01 changed: 0 1 step 170 000000000000000000000000000011110011000000100101010010010100101001 source: 1 01 changed: 1 01 step 171 000000000000000000000000000011110011000000100111001010010100101001 source: 0 changed: 0 step 172 000000000000000000000000000011110011000000100101001010010100101001 source: 111 00 changed: 1 0 step 173 000000000000000000000000000011110011100000100001001010010100101001 source: 1 10 changed: 1 10 step 174 000000000000000000000000000011110011100000100001001110100100101001 source: 0 changed: 0 step 175 000000000000000000000000000011110011100000100001001010100100101001 source: 110 01 changed: 0 1 step 176 000000000000000000000000000011110011000000100101001010100100101001 source: 1 01 changed: 1 01 step 177 000000000000000000000000000011110011000000100101001110010100101001 source: 0 changed: 0 step 178 000000000000000000000000000011110011000000100101001010010100101001 source: 111 00 changed: 1 0 step 179 000000000000000000000000000011110011100000100001001010010100101001 source: 1 10 changed: 1 10 step 180 000000000000000000000000000011110011100000100001001010011101001001 source: 0 changed: 0 step 181 000000000000000000000000000011110011100000100001001010010101001001 source: 110 01 changed: 0 1 step 182 000000000000000000000000000011110011000000100101001010010101001001 source: 1 01 changed: 1 01 step 183 000000000000000000000000000011110011000000100101001010011100101001 source: 0 changed: 0 step 184 000000000000000000000000000011110011000000100101001010010100101001 source: 111 00 changed: 1 0 step 185 000000000000000000000000000011110011100000100001001010010100101001 source: 1 10 changed: 1 10 step 186 000000000000000000000000000011110011100000100001001010010100111010 source: 0 changed: 0 step 187 000000000000000000000000000011110011100000100001001010010100101010 source: 110 01 changed: 0 1 step 188 000000000000000000000000000011110011000000100101001010010100101010 source: 1 01 changed: 1 01 step 189 000000000000000000000000000011110011000000100101001010010100111001 source: 0 changed: 0 step 190 000000000000000000000000000011110011000000100101001010010100101001 source: ; set each register to 01 and back to 01 source: 1 changed: 1 step 191 000000000000000000000000000011110011000000100111001010010100101001 source: 0 changed: 0 step 192 000000000000000000000000000011110011000000100101001010010100101001 source: 1 changed: 1 step 193 000000000000000000000000000011110011000000100101001110010100101001 source: 0 changed: 0 step 194 000000000000000000000000000011110011000000100101001010010100101001 source: 1 changed: 1 step 195 000000000000000000000000000011110011000000100101001010011100101001 source: 0 changed: 0 step 196 000000000000000000000000000011110011000000100101001010010100101001 source: 1 changed: 1 step 197 000000000000000000000000000011110011000000100101001010010100111001 source: 0 changed: 0 step 198 000000000000000000000000000011110011000000100101001010010100101001 source: ; set each register to 10 and back to 01 source: 101 10 changed: 01 10 step 199 000000000000000000000000000011110010100000101001001010010100101001 source: 10110 changed: 10110 step 200 000000000000000000000000000011110010100000101010110010010100101001 source: 0 changed: 0 step 201 000000000000000000000000000011110010100000101000110010010100101001 source: 110 01 changed: 10 01 step 202 000000000000000000000000000011110011000000100100110010010100101001 source: 11001 changed: 11001 step 203 000000000000000000000000000011110011000000100111001010010100101001 source: 0 changed: 0 step 204 000000000000000000000000000011110011000000100101001010010100101001 source: 101 10 changed: 01 10 step 205 000000000000000000000000000011110010100000101001001010010100101001 source: 10110 changed: 10110 step 206 000000000000000000000000000011110010100000101001001101100100101001 source: 0 changed: 0 step 207 000000000000000000000000000011110010100000101001001001100100101001 source: 110 01 changed: 10 01 step 208 000000000000000000000000000011110011000000100101001001100100101001 source: 11001 changed: 11001 step 209 000000000000000000000000000011110011000000100101001110010100101001 source: 0 changed: 0 step 210 000000000000000000000000000011110011000000100101001010010100101001 source: 101 10 changed: 01 10 step 211 000000000000000000000000000011110010100000101001001010010100101001 source: 10110 changed: 10110 step 212 000000000000000000000000000011110010100000101001001010011011001001 source: 0 changed: 0 step 213 000000000000000000000000000011110010100000101001001010010011001001 source: 110 01 changed: 10 01 step 214 000000000000000000000000000011110011000000100101001010010011001001 source: 11001 changed: 11001 step 215 000000000000000000000000000011110011000000100101001010011100101001 source: 0 changed: 0 step 216 000000000000000000000000000011110011000000100101001010010100101001 source: 101 10 changed: 01 10 step 217 000000000000000000000000000011110010100000101001001010010100101001 source: 10110 changed: 10110 step 218 000000000000000000000000000011110010100000101001001010010100110110 source: 0 changed: 0 step 219 000000000000000000000000000011110010100000101001001010010100100110 source: 110 01 changed: 10 01 step 220 000000000000000000000000000011110011000000100101001010010100100110 source: 11001 changed: 11001 step 221 000000000000000000000000000011110011000000100101001010010100111001 source: 0 changed: 0 step 222 000000000000000000000000000011110011000000100101001010010100101001 source: ; set each register to 11 and back to 01 source: 100 11 changed: 0 1 step 223 000000000000000000000000000011110010000000101101001010010100101001 source: 101 changed: 101 step 224 000000000000000000000000000011110010000000101110101010010100101001 source: 0 changed: 0 step 225 000000000000000000000000000011110010000000101100101010010100101001 source: 110 01 changed: 1 0 step 226 000000000000000000000000000011110011000000100100101010010100101001 source: 110 changed: 110 step 227 000000000000000000000000000011110011000000100111001010010100101001 source: 0 changed: 0 step 228 000000000000000000000000000011110011000000100101001010010100101001 source: 100 11 changed: 0 1 step 229 000000000000000000000000000011110010000000101101001010010100101001 source: 101 changed: 101 step 230 000000000000000000000000000011110010000000101101001101010100101001 source: 0 changed: 0 step 231 000000000000000000000000000011110010000000101101001001010100101001 source: 110 01 changed: 1 0 step 232 000000000000000000000000000011110011000000100101001001010100101001 source: 110 changed: 110 step 233 000000000000000000000000000011110011000000100101001110010100101001 source: 0 changed: 0 step 234 000000000000000000000000000011110011000000100101001010010100101001 source: 100 11 changed: 0 1 step 235 000000000000000000000000000011110010000000101101001010010100101001 source: 101 changed: 101 step 236 000000000000000000000000000011110010000000101101001010011010101001 source: 0 changed: 0 step 237 000000000000000000000000000011110010000000101101001010010010101001 source: 110 01 changed: 1 0 step 238 000000000000000000000000000011110011000000100101001010010010101001 source: 110 changed: 110 step 239 000000000000000000000000000011110011000000100101001010011100101001 source: 0 changed: 0 step 240 000000000000000000000000000011110011000000100101001010010100101001 source: 100 11 changed: 0 1 step 241 000000000000000000000000000011110010000000101101001010010100101001 source: 101 changed: 101 step 242 000000000000000000000000000011110010000000101101001010010100110101 source: 0 changed: 0 step 243 000000000000000000000000000011110010000000101101001010010100100101 source: 110 01 changed: 1 0 step 244 000000000000000000000000000011110011000000100101001010010100100101 source: 110 changed: 110 step 245 000000000000000000000000000011110011000000100101001010010100111001 source: 0 changed: 0 step 246 000000000000000000000000000011110011000000100101001010010100101001 source: ; all registers are 01 source: 000000000000000000000000000011110011000000100101001010010100101001 changed: step 247 000000000000000000000000000011110011000000100101001010010100101001 source: ; source: ; with all registers 10; change each register individually to 00,01,10,11 source: ; source: ; use SHIFT RIGHT TWICE, ADDER0, ADDER1 to setup BUS2,BUS3 source: ; set all registers to 10 source: 101 10 changed: 01 10 step 248 000000000000000000000000000011110010100000101001001010010100101001 source: 10110101101011010110 changed: 10110101101011010110 step 249 000000000000000000000000000011110010100000101010110101101011010110 source: 0 0 0 0 changed: 0 0 0 0 step 250 000000000000000000000000000011110010100000101000110001100011000110 source: ; all registers are 10 source: 000000000000000000000000000011110010100000101000110001100011000110 changed: step 251 000000000000000000000000000011110010100000101000110001100011000110 source: ; use SHIFT RIGHT TWICE, ADDER0, ADDER1 to setup BUS2,BUS3 source: ; set each register to 00 and back to 10 source: 111 00 changed: 1 0 step 252 000000000000000000000000000011110011100000100000110001100011000110 source: 110 changed: 110 step 253 000000000000000000000000000011110011100000100011010001100011000110 source: 0 changed: 0 step 254 000000000000000000000000000011110011100000100001010001100011000110 source: 101 10 changed: 0 1 step 255 000000000000000000000000000011110010100000101001010001100011000110 source: 101 changed: 101 step 256 000000000000000000000000000011110010100000101010110001100011000110 source: 0 changed: 0 step 257 000000000000000000000000000011110010100000101000110001100011000110 source: 111 00 changed: 1 0 step 258 000000000000000000000000000011110011100000100000110001100011000110 source: 110 changed: 110 step 259 000000000000000000000000000011110011100000100000110110100011000110 source: 0 changed: 0 step 260 000000000000000000000000000011110011100000100000110010100011000110 source: 101 10 changed: 0 1 step 261 000000000000000000000000000011110010100000101000110010100011000110 source: 101 changed: 101 step 262 000000000000000000000000000011110010100000101000110101100011000110 source: 0 changed: 0 step 263 000000000000000000000000000011110010100000101000110001100011000110 source: 111 00 changed: 1 0 step 264 000000000000000000000000000011110011100000100000110001100011000110 source: 110 changed: 110 step 265 000000000000000000000000000011110011100000100000110001101101000110 source: 0 changed: 0 step 266 000000000000000000000000000011110011100000100000110001100101000110 source: 101 10 changed: 0 1 step 267 000000000000000000000000000011110010100000101000110001100101000110 source: 101 changed: 101 step 268 000000000000000000000000000011110010100000101000110001101011000110 source: 0 changed: 0 step 269 000000000000000000000000000011110010100000101000110001100011000110 source: 111 00 changed: 1 0 step 270 000000000000000000000000000011110011100000100000110001100011000110 source: 110 changed: 110 step 271 000000000000000000000000000011110011100000100000110001100011011010 source: 0 changed: 0 step 272 000000000000000000000000000011110011100000100000110001100011001010 source: 101 10 changed: 0 1 step 273 000000000000000000000000000011110010100000101000110001100011001010 source: 101 changed: 101 step 274 000000000000000000000000000011110010100000101000110001100011010110 source: 0 changed: 0 step 275 000000000000000000000000000011110010100000101000110001100011000110 source: ; set each register to 01 and back to 10 source: 110 01 changed: 10 01 step 276 000000000000000000000000000011110011000000100100110001100011000110 source: 11001 changed: 11001 step 277 000000000000000000000000000011110011000000100111001001100011000110 source: 0 changed: 0 step 278 000000000000000000000000000011110011000000100101001001100011000110 source: 101 10 changed: 01 10 step 279 000000000000000000000000000011110010100000101001001001100011000110 source: 10110 changed: 10110 step 280 000000000000000000000000000011110010100000101010110001100011000110 source: 0 changed: 0 step 281 000000000000000000000000000011110010100000101000110001100011000110 source: 110 01 changed: 10 01 step 282 000000000000000000000000000011110011000000100100110001100011000110 source: 11001 changed: 11001 step 283 000000000000000000000000000011110011000000100100110110010011000110 source: 0 changed: 0 step 284 000000000000000000000000000011110011000000100100110010010011000110 source: 101 10 changed: 01 10 step 285 000000000000000000000000000011110010100000101000110010010011000110 source: 10110 changed: 10110 step 286 000000000000000000000000000011110010100000101000110101100011000110 source: 0 changed: 0 step 287 000000000000000000000000000011110010100000101000110001100011000110 source: 110 01 changed: 10 01 step 288 000000000000000000000000000011110011000000100100110001100011000110 source: 11001 changed: 11001 step 289 000000000000000000000000000011110011000000100100110001101100100110 source: 0 changed: 0 step 290 000000000000000000000000000011110011000000100100110001100100100110 source: 101 10 changed: 01 10 step 291 000000000000000000000000000011110010100000101000110001100100100110 source: 10110 changed: 10110 step 292 000000000000000000000000000011110010100000101000110001101011000110 source: 0 changed: 0 step 293 000000000000000000000000000011110010100000101000110001100011000110 source: 110 01 changed: 10 01 step 294 000000000000000000000000000011110011000000100100110001100011000110 source: 11001 changed: 11001 step 295 000000000000000000000000000011110011000000100100110001100011011001 source: 0 changed: 0 step 296 000000000000000000000000000011110011000000100100110001100011001001 source: 101 10 changed: 01 10 step 297 000000000000000000000000000011110010100000101000110001100011001001 source: 10110 changed: 10110 step 298 000000000000000000000000000011110010100000101000110001100011010110 source: 0 changed: 0 step 299 000000000000000000000000000011110010100000101000110001100011000110 source: ; set each register to 10 and back to 10 source: 101 10 changed: step 300 000000000000000000000000000011110010100000101000110001100011000110 source: 1 changed: 1 step 301 000000000000000000000000000011110010100000101010110001100011000110 source: 0 changed: 0 step 302 000000000000000000000000000011110010100000101000110001100011000110 source: 1 changed: 1 step 303 000000000000000000000000000011110010100000101000110101100011000110 source: 0 changed: 0 step 304 000000000000000000000000000011110010100000101000110001100011000110 source: 1 changed: 1 step 305 000000000000000000000000000011110010100000101000110001101011000110 source: 0 changed: 0 step 306 000000000000000000000000000011110010100000101000110001100011000110 source: 1 changed: 1 step 307 000000000000000000000000000011110010100000101000110001100011010110 source: 0 changed: 0 step 308 000000000000000000000000000011110010100000101000110001100011000110 source: ; set each register to 11 and back to 10 source: 100 11 changed: 0 1 step 309 000000000000000000000000000011110010000000101100110001100011000110 source: 1 01 changed: 1 01 step 310 000000000000000000000000000011110010000000101110101001100011000110 source: 0 changed: 0 step 311 000000000000000000000000000011110010000000101100101001100011000110 source: 101 10 changed: 1 0 step 312 000000000000000000000000000011110010100000101000101001100011000110 source: 1 10 changed: 1 10 step 313 000000000000000000000000000011110010100000101010110001100011000110 source: 0 changed: 0 step 314 000000000000000000000000000011110010100000101000110001100011000110 source: 100 11 changed: 0 1 step 315 000000000000000000000000000011110010000000101100110001100011000110 source: 1 01 changed: 1 01 step 316 000000000000000000000000000011110010000000101100110101010011000110 source: 0 changed: 0 step 317 000000000000000000000000000011110010000000101100110001010011000110 source: 101 10 changed: 1 0 step 318 000000000000000000000000000011110010100000101000110001010011000110 source: 1 10 changed: 1 10 step 319 000000000000000000000000000011110010100000101000110101100011000110 source: 0 changed: 0 step 320 000000000000000000000000000011110010100000101000110001100011000110 source: 100 11 changed: 0 1 step 321 000000000000000000000000000011110010000000101100110001100011000110 source: 1 01 changed: 1 01 step 322 000000000000000000000000000011110010000000101100110001101010100110 source: 0 changed: 0 step 323 000000000000000000000000000011110010000000101100110001100010100110 source: 101 10 changed: 1 0 step 324 000000000000000000000000000011110010100000101000110001100010100110 source: 1 10 changed: 1 10 step 325 000000000000000000000000000011110010100000101000110001101011000110 source: 0 changed: 0 step 326 000000000000000000000000000011110010100000101000110001100011000110 source: 100 11 changed: 0 1 step 327 000000000000000000000000000011110010000000101100110001100011000110 source: 1 01 changed: 1 01 step 328 000000000000000000000000000011110010000000101100110001100011010101 source: 0 changed: 0 step 329 000000000000000000000000000011110010000000101100110001100011000101 source: 101 10 changed: 1 0 step 330 000000000000000000000000000011110010100000101000110001100011000101 source: 1 10 changed: 1 10 step 331 000000000000000000000000000011110010100000101000110001100011010110 source: 0 changed: 0 step 332 000000000000000000000000000011110010100000101000110001100011000110 source: ; all registers are 10 source: 000000000000000000000000000011110010000000101100110001100011000110 changed: 0 1 step 333 000000000000000000000000000011110010000000101100110001100011000110 source: ; source: ; with all registers 11; change each register individually to 00,01,10,11 source: ; source: ; use SHIFT RIGHT TWICE, ADDER0, ADDER1 to setup BUS2,BUS3 source: ; set all registers to 11 source: 100 11 changed: step 334 000000000000000000000000000011110010000000101100110001100011000110 source: 10101101011010110101 changed: 1 011 011 011 01 step 335 000000000000000000000000000011110010000000101110101101011010110101 source: 0 0 0 0 changed: 0 0 0 0 step 336 000000000000000000000000000011110010000000101100101001010010100101 source: ; all registers are 11 source: 000000000000000000000000000011110010000000101100101001010010100101 changed: step 337 000000000000000000000000000011110010000000101100101001010010100101 source: ; use SHIFT RIGHT TWICE, ADDER0, ADDER1 to setup BUS2,BUS3 source: ; set each register to 00 and back to 11 source: 111 00 changed: 11 00 step 338 000000000000000000000000000011110011100000100000101001010010100101 source: 11010 changed: 11010 step 339 000000000000000000000000000011110011100000100011010001010010100101 source: 0 changed: 0 step 340 000000000000000000000000000011110011100000100001010001010010100101 source: 100 11 changed: 00 11 step 341 000000000000000000000000000011110010000000101101010001010010100101 source: 10101 changed: 10101 step 342 000000000000000000000000000011110010000000101110101001010010100101 source: 0 changed: 0 step 343 000000000000000000000000000011110010000000101100101001010010100101 source: 111 00 changed: 11 00 step 344 000000000000000000000000000011110011100000100000101001010010100101 source: 11010 changed: 11010 step 345 000000000000000000000000000011110011100000100000101110100010100101 source: 0 changed: 0 step 346 000000000000000000000000000011110011100000100000101010100010100101 source: 100 11 changed: 00 11 step 347 000000000000000000000000000011110010000000101100101010100010100101 source: 10101 changed: 10101 step 348 000000000000000000000000000011110010000000101100101101010010100101 source: 0 changed: 0 step 349 000000000000000000000000000011110010000000101100101001010010100101 source: 111 00 changed: 11 00 step 350 000000000000000000000000000011110011100000100000101001010010100101 source: 11010 changed: 11010 step 351 000000000000000000000000000011110011100000100000101001011101000101 source: 0 changed: 0 step 352 000000000000000000000000000011110011100000100000101001010101000101 source: 100 11 changed: 00 11 step 353 000000000000000000000000000011110010000000101100101001010101000101 source: 10101 changed: 10101 step 354 000000000000000000000000000011110010000000101100101001011010100101 source: 0 changed: 0 step 355 000000000000000000000000000011110010000000101100101001010010100101 source: 111 00 changed: 11 00 step 356 000000000000000000000000000011110011100000100000101001010010100101 source: 11010 changed: 11010 step 357 000000000000000000000000000011110011100000100000101001010010111010 source: 0 changed: 0 step 358 000000000000000000000000000011110011100000100000101001010010101010 source: 100 11 changed: 00 11 step 359 000000000000000000000000000011110010000000101100101001010010101010 source: 10101 changed: 10101 step 360 000000000000000000000000000011110010000000101100101001010010110101 source: 0 changed: 0 step 361 000000000000000000000000000011110010000000101100101001010010100101 source: ; set each register to 01 and back to 11 source: 110 01 changed: 1 0 step 362 000000000000000000000000000011110011000000100100101001010010100101 source: 110 changed: 110 step 363 000000000000000000000000000011110011000000100111001001010010100101 source: 0 changed: 0 step 364 000000000000000000000000000011110011000000100101001001010010100101 source: 100 11 changed: 0 1 step 365 000000000000000000000000000011110010000000101101001001010010100101 source: 101 changed: 101 step 366 000000000000000000000000000011110010000000101110101001010010100101 source: 0 changed: 0 step 367 000000000000000000000000000011110010000000101100101001010010100101 source: 110 01 changed: 1 0 step 368 000000000000000000000000000011110011000000100100101001010010100101 source: 110 changed: 110 step 369 000000000000000000000000000011110011000000100100101110010010100101 source: 0 changed: 0 step 370 000000000000000000000000000011110011000000100100101010010010100101 source: 100 11 changed: 0 1 step 371 000000000000000000000000000011110010000000101100101010010010100101 source: 101 changed: 101 step 372 000000000000000000000000000011110010000000101100101101010010100101 source: 0 changed: 0 step 373 000000000000000000000000000011110010000000101100101001010010100101 source: 110 01 changed: 1 0 step 374 000000000000000000000000000011110011000000100100101001010010100101 source: 110 changed: 110 step 375 000000000000000000000000000011110011000000100100101001011100100101 source: 0 changed: 0 step 376 000000000000000000000000000011110011000000100100101001010100100101 source: 100 11 changed: 0 1 step 377 000000000000000000000000000011110010000000101100101001010100100101 source: 101 changed: 101 step 378 000000000000000000000000000011110010000000101100101001011010100101 source: 0 changed: 0 step 379 000000000000000000000000000011110010000000101100101001010010100101 source: 110 01 changed: 1 0 step 380 000000000000000000000000000011110011000000100100101001010010100101 source: 110 changed: 110 step 381 000000000000000000000000000011110011000000100100101001010010111001 source: 0 changed: 0 step 382 000000000000000000000000000011110011000000100100101001010010101001 source: 100 11 changed: 0 1 step 383 000000000000000000000000000011110010000000101100101001010010101001 source: 101 changed: 101 step 384 000000000000000000000000000011110010000000101100101001010010110101 source: 0 changed: 0 step 385 000000000000000000000000000011110010000000101100101001010010100101 source: ; set each register to 10 and back to 11 source: 101 10 changed: 1 0 step 386 000000000000000000000000000011110010100000101000101001010010100101 source: 1 10 changed: 1 10 step 387 000000000000000000000000000011110010100000101010110001010010100101 source: 0 changed: 0 step 388 000000000000000000000000000011110010100000101000110001010010100101 source: 100 11 changed: 0 1 step 389 000000000000000000000000000011110010000000101100110001010010100101 source: 1 01 changed: 1 01 step 390 000000000000000000000000000011110010000000101110101001010010100101 source: 0 changed: 0 step 391 000000000000000000000000000011110010000000101100101001010010100101 source: 101 10 changed: 1 0 step 392 000000000000000000000000000011110010100000101000101001010010100101 source: 1 10 changed: 1 10 step 393 000000000000000000000000000011110010100000101000101101100010100101 source: 0 changed: 0 step 394 000000000000000000000000000011110010100000101000101001100010100101 source: 100 11 changed: 0 1 step 395 000000000000000000000000000011110010000000101100101001100010100101 source: 1 01 changed: 1 01 step 396 000000000000000000000000000011110010000000101100101101010010100101 source: 0 changed: 0 step 397 000000000000000000000000000011110010000000101100101001010010100101 source: 101 10 changed: 1 0 step 398 000000000000000000000000000011110010100000101000101001010010100101 source: 1 10 changed: 1 10 step 399 000000000000000000000000000011110010100000101000101001011011000101 source: 0 changed: 0 step 400 000000000000000000000000000011110010100000101000101001010011000101 source: 100 11 changed: 0 1 step 401 000000000000000000000000000011110010000000101100101001010011000101 source: 1 01 changed: 1 01 step 402 000000000000000000000000000011110010000000101100101001011010100101 source: 0 changed: 0 step 403 000000000000000000000000000011110010000000101100101001010010100101 source: 101 10 changed: 1 0 step 404 000000000000000000000000000011110010100000101000101001010010100101 source: 1 10 changed: 1 10 step 405 000000000000000000000000000011110010100000101000101001010010110110 source: 0 changed: 0 step 406 000000000000000000000000000011110010100000101000101001010010100110 source: 100 11 changed: 0 1 step 407 000000000000000000000000000011110010000000101100101001010010100110 source: 1 01 changed: 1 01 step 408 000000000000000000000000000011110010000000101100101001010010110101 source: 0 changed: 0 step 409 000000000000000000000000000011110010000000101100101001010010100101 source: ; set each register to 11 and back to 11 source: 100 11 changed: step 410 000000000000000000000000000011110010000000101100101001010010100101 source: 1 changed: 1 step 411 000000000000000000000000000011110010000000101110101001010010100101 source: 0 changed: 0 step 412 000000000000000000000000000011110010000000101100101001010010100101 source: 100 1 changed: 1 step 413 000000000000000000000000000011110010000000101100101101010010100101 source: 0 changed: 0 step 414 000000000000000000000000000011110010000000101100101001010010100101 source: 100 1 changed: 1 step 415 000000000000000000000000000011110010000000101100101001011010100101 source: 0 changed: 0 step 416 000000000000000000000000000011110010000000101100101001010010100101 source: 100 1 changed: 1 step 417 000000000000000000000000000011110010000000101100101001010010110101 source: 0 changed: 0 step 418 000000000000000000000000000011110010000000101100101001010010100101 source: ; all registers are 11 source: 000000000000000000000000000011110010000000101100101001010010100101 changed: step 419 000000000000000000000000000011110010000000101100101001010010100101 source: ; use SHIFT RIGHT TWICE, ADDER0, ADDER1 to setup BUS2,BUS3 source: ; set registers to 00 source: 111 00 changed: 11 00 step 420 000000000000000000000000000011110011100000100000101001010010100101 source: 11010110101101011010 changed: 11010110101101011010 step 421 000000000000000000000000000011110011100000100011010110101101011010 source: 0 0 0 0 changed: 0 0 0 0 step 422 000000000000000000000000000011110011100000100001010010100101001010 source: ; all registers are 00 source: 000000000000000000000000000011110011100000100001010010100101001010 changed: step 423 000000000000000000000000000011110011100000100001010010100101001010 source: ; source: ; now test each register using SHIFT LEFT TWICE/ADDER4/ADDER5 source: source: ; disable SHIFT RIGHT TWICE, ADDER0, ADDER1 source: 000 11 changed: 000 11 step 424 000000000000000000000000000011110000000000101101010010100101001010 source: ; use SHIFT LEFT TWICE, ADDER4, ADDER5 to set BUS2,BUS3 to 00 source: 11 1 00 changed: 11 1 00 step 425 000000000000000000000000000011110000011001100001010010100101001010 source: ; all registers are 00 source: 000000000000000000000000000011110000011001100001010010100101001010 changed: step 426 000000000000000000000000000011110000011001100001010010100101001010 source: ; use SHIFT LEFT TWICE, ADDER4, ADDER5 to set BUS2,BUS3 to 00 source: ; set each register to 00 source: 11 1 001 changed: 1 step 427 000000000000000000000000000011110000011001100011010010100101001010 source: 0 changed: 0 step 428 000000000000000000000000000011110000011001100001010010100101001010 source: 00 1 changed: 1 step 429 000000000000000000000000000011110000011001100001010110100101001010 source: 0 changed: 0 step 430 000000000000000000000000000011110000011001100001010010100101001010 source: 00 1 changed: 1 step 431 000000000000000000000000000011110000011001100001010010101101001010 source: 0 changed: 0 step 432 000000000000000000000000000011110000011001100001010010100101001010 source: 00 1 changed: 1 step 433 000000000000000000000000000011110000011001100001010010100101011010 source: 0 changed: 0 step 434 000000000000000000000000000011110000011001100001010010100101001010 source: 00 changed: step 435 000000000000000000000000000011110000011001100001010010100101001010 source: ; set each register to 01 source: 10 1 01 changed: 0 1 step 436 000000000000000000000000000011110000010001100101010010100101001010 source: 011 01 changed: 1 01 step 437 000000000000000000000000000011110000010001100111001010100101001010 source: 0 changed: 0 step 438 000000000000000000000000000011110000010001100101001010100101001010 source: 01 1 01 changed: 1 01 step 439 000000000000000000000000000011110000010001100101001110010101001010 source: 0 changed: 0 step 440 000000000000000000000000000011110000010001100101001010010101001010 source: 01 1 01 changed: 1 01 step 441 000000000000000000000000000011110000010001100101001010011100101010 source: 0 changed: 0 step 442 000000000000000000000000000011110000010001100101001010010100101010 source: 01 1 01 changed: 1 01 step 443 000000000000000000000000000011110000010001100101001010010100111001 source: 0 changed: 0 step 444 000000000000000000000000000011110000010001100101001010010100101001 source: ; set each register to 11 source: 00 1 11 changed: 0 1 step 445 000000000000000000000000000011110000000001101101001010010100101001 source: 11101 changed: 101 step 446 000000000000000000000000000011110000000001101110101010010100101001 source: 0 changed: 0 step 447 000000000000000000000000000011110000000001101100101010010100101001 source: 11 101 changed: 101 step 448 000000000000000000000000000011110000000001101100101101010100101001 source: 0 changed: 0 step 449 000000000000000000000000000011110000000001101100101001010100101001 source: 11 101 changed: 101 step 450 000000000000000000000000000011110000000001101100101001011010101001 source: 0 changed: 0 step 451 000000000000000000000000000011110000000001101100101001010010101001 source: 11 101 changed: 101 step 452 000000000000000000000000000011110000000001101100101001010010110101 source: 0 changed: 0 step 453 000000000000000000000000000011110000000001101100101001010010100101 source: ; set each register to 10 source: 01 1 10 changed: 1 0 step 454 000000000000000000000000000011110000001001101000101001010010100101 source: 101 10 changed: 1 10 step 455 000000000000000000000000000011110000001001101010110001010010100101 source: 0 changed: 0 step 456 000000000000000000000000000011110000001001101000110001010010100101 source: 10 1 10 changed: 1 10 step 457 000000000000000000000000000011110000001001101000110101100010100101 source: 0 changed: 0 step 458 000000000000000000000000000011110000001001101000110001100010100101 source: 10 1 10 changed: 1 10 step 459 000000000000000000000000000011110000001001101000110001101011000101 source: 0 changed: 0 step 460 000000000000000000000000000011110000001001101000110001100011000101 source: 10 1 10 changed: 1 10 step 461 000000000000000000000000000011110000001001101000110001100011010110 source: 0 changed: 0 step 462 000000000000000000000000000011110000001001101000110001100011000110 source: ; set each register to 00 source: 11 1 00110 changed: 1 0 110 step 463 000000000000000000000000000011110000011001100011010001100011000110 source: 0 changed: 0 step 464 000000000000000000000000000011110000011001100001010001100011000110 source: 00 110 changed: 110 step 465 000000000000000000000000000011110000011001100001010110100011000110 source: 0 changed: 0 step 466 000000000000000000000000000011110000011001100001010010100011000110 source: 00 110 changed: 110 step 467 000000000000000000000000000011110000011001100001010010101101000110 source: 0 changed: 0 step 468 000000000000000000000000000011110000011001100001010010100101000110 source: 00 110 changed: 110 step 469 000000000000000000000000000011110000011001100001010010100101011010 source: 0 changed: 0 step 470 000000000000000000000000000011110000011001100001010010100101001010 source: 00 changed: step 471 000000000000000000000000000011110000011001100001010010100101001010 source: ; all registers are 00 source: 000000000000000000000000000011110000011001100001010010100101001010 changed: step 472 000000000000000000000000000011110000011001100001010010100101001010 source: ; source: ; test AND/MB path source: ; source: ; set registers MA,PC,MB,AC to 00,00,11,00 source: ; use SHIFT LEFT TWICE, ADDER4, ADDER5 to set BUS2,BUS3 to 00 source: 00 1 11 changed: 00 11 step 473 000000000000000000000000000011110000000001101101010010100101001010 source: 10101 changed: 10101 step 474 000000000000000000000000000011110000000001101101010010101010101010 source: 0 changed: 0 step 475 000000000000000000000000000011110000000001101101010010100010101010 source: 11 1 00 changed: 11 00 step 476 000000000000000000000000000011110000011001100001010010100010101010 source: 1101011010 11010 changed: 1 1 1 step 477 000000000000000000000000000011110000011001100011010110100010111010 source: 0 0 0 changed: 0 0 0 step 478 000000000000000000000000000011110000011001100001010010100010101010 source: ; use AND enable to setup BUS2,BUS3 to 11 source: ; set MA,PC,xx,AC to 11 and back to 00 source: 11 0 11 changed: 0 11 step 479 000000000000000000000000000011110000011000101101010010100010101010 SLOT BBBBBBBBBBBBBBBBBBBBBBBBBBBBBBAAAAAAAAAAAAABAAAAAAAAAAAAAAAAAABBAA LETTER EHJFHNCEDFDNLMPLKMPRSURVVTSUJKEFADDBCHJEFHBBJKKMMLLNRPPNRUTSSUBAVV SIDE 222112112211122211122211221112211211122121221211212221211221211121 DIRECTION IIIIIIIIIIIIIIIIIIIIIIIIIIIIIOOOIIIIIIIIIIIIOOIOOOOIOOOOIOOOOIOOOO source: 1 11 changed: 1 00 step 480 000000000000000000000000000011111000011000100001010010100010101010 fail ^^ space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn off comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT BBBBBBBBBBBBBBBBBBBBBBBBBBBBBBAAAAAAAAAAAAABAAAAAAAAAAAAAAAAAABBAA LETTER EHJFHNCEDFDNLMPLKMPRSURVVTSUJKEFADDBCHJEFHBBJKKMMLLNRPPNRUTSSUBAVV SIDE 222112112211122211122211221112211211122121221211212221211221211121 DIRECTION IIIIIIIIIIIIIIIIIIIIIIIIIIIIIOOOIIIIIIIIIIIIOOIOOOOIOOOOIOOOOIOOOO all fails OO OOOO OOOO OOOO OOOO was lo 000000000000000000000000000000000000000000000000000000000000000000 falling vvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvv rising ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ was hi 111111111111111111111111111111111111111111111111111111111111111111 total fails 9, total passes 0 Main menu Mon Jul 10 12:32:49 2017 test file is: tests\m220.tst delay is: 0 trigger is: 1 1 read test file 2 set test delay 3 set test trigger 4 run test 5 output loading test 8 diags 9 exit Enter test file name? trying to open test file: tests\m113.tst reading test file: tests\m113.tst comment: M113 10 2-input NAND comment: pins: PINS pins: 1 I AA1 E1-1 pins: 2 I AB1 E1-2 pins: 3 O AC1 E1-3 pins: 4 I AD1 E1-4 pins: 5 I AE1 E1-5 pins: 6 O AF1 E1-6 pins: 7 I AD2 E1-13 pins: 8 I AE2 E1-12 pins: 9 O AF2 E1-11 pins: 10 I AH1 E3-4 pins: 11 I AJ1 E3-5 pins: 12 O AK1 E3-6 pins: 13 I AH2 E3-10 pins: 14 I AJ2 E3-9 pins: 15 O AK2 E3-8 pins: 16 I AL1 E2-1 pins: 17 I AM1 E2-2 pins: 18 O AN1 E2-3 pins: 19 I AL2 E3-10 pins: 20 I AM2 E3-9 pins: 21 O AN2 E3-8 pins: 22 I AP1 E2-4 pins: 23 I AR1 E2-5 pins: 24 O AS1 E2-6 pins: 25 I AP2 E2-13 pins: 26 I AR2 E2-12 pins: 27 O AS2 E2-11 pins: 28 I AT2 E2-10 pins: 29 I AU2 E2-9 pins: 30 O AV2 E2-8 pins: direction: IIOIIOIIOIIOIIOIIOIIOIIOIIOIIO test 1: 001001001001001001001001001001 test 2: 110110110110110110110110110110 test 3: 011 test 4: 001 test 5: 101 test 6: 110 test 7: 011 test 8: 001 test 9: 101 test 10: 110 test 11: 011 test 12: 001 test 13: 101 test 14: 110 test 15: 011 test 16: 001 test 17: 101 test 18: 110 test 19: 011 test 20: 001 test 21: 101 test 22: 110 test 23: 011 test 24: 001 test 25: 101 test 26: 110 test 27: 011 test 28: 001 test 29: 101 test 30: 110 test 31: 011 test 32: 001 test 33: 101 test 34: 110 test 35: 011 test 36: 001 test 37: 101 test 38: 110 test 39: 011 test 40: 001 test 41: 101 test 42: 110 test 43: 001001001001001001001001001001 test 44: 011 test 45: 110 test 46: 101 test 47: 001 test 48: 011 test 49: 110 test 50: 101 test 51: 001 test 52: 011 test 53: 110 test 54: 101 test 55: 001 test 56: 011 test 57: 110 test 58: 101 test 59: 001 test 60: 011 test 61: 110 test 62: 101 test 63: 001 test 64: 011 test 65: 110 test 66: 101 test 67: 001 test 68: 011 test 69: 110 test 70: 101 test 71: 001 test 72: 011 test 73: 110 test 74: 101 test 75: 001 test 76: 011 test 77: 110 test 78: 101 test 79: 001 test 80: 011 test 81: 110 test 82: 101 test 83: 001 end: END summary column 1: offset 0, mask 0x8000 column 2: offset 0, mask 0x4000 column 3: offset 0, mask 0x2000 column 4: offset 0, mask 0x1000 column 5: offset 0, mask 0x0800 column 6: offset 0, mask 0x0400 column 7: offset 0, mask 0x0010 column 8: offset 0, mask 0x0008 column 9: offset 0, mask 0x0004 column 10: offset 0, mask 0x0200 column 11: offset 0, mask 0x0100 column 12: offset 1, mask 0x8000 column 13: offset 0, mask 0x0002 column 14: offset 0, mask 0x0001 column 15: offset 1, mask 0x0001 column 16: offset 1, mask 0x4000 column 17: offset 1, mask 0x2000 column 18: offset 1, mask 0x1000 column 19: offset 1, mask 0x0002 column 20: offset 1, mask 0x0004 column 21: offset 1, mask 0x0008 column 22: offset 1, mask 0x0800 column 23: offset 1, mask 0x0400 column 24: offset 1, mask 0x0200 column 25: offset 1, mask 0x0010 column 26: offset 1, mask 0x0020 column 27: offset 1, mask 0x0040 column 28: offset 1, mask 0x0080 column 29: offset 2, mask 0x0001 column 30: offset 2, mask 0x0002 direction bits (1=input) 0x24E4 0x9349 0xFFFA 0xFFFF 0xF0FF pullup bits (1=pullup) 0x0000 0x0000 0x0000 0x0000 0x0000 test step out_data dont care 1: 0x2404 0x9249 0x0002 0x0000 0x0000 2: 0xDB1B 0x6CB6 0x0001 0x0000 0x0000 3: 0x7B1B 0x6CB6 0x0001 0x0000 0x0000 4: 0x3B1B 0x6CB6 0x0001 0x0000 0x0000 5: 0xBB1B 0x6CB6 0x0001 0x0000 0x0000 6: 0xDB1B 0x6CB6 0x0001 0x0000 0x0000 7: 0xCF1B 0x6CB6 0x0001 0x0000 0x0000 8: 0xC71B 0x6CB6 0x0001 0x0000 0x0000 9: 0xD71B 0x6CB6 0x0001 0x0000 0x0000 10: 0xDB1B 0x6CB6 0x0001 0x0000 0x0000 11: 0xDB0F 0x6CB6 0x0001 0x0000 0x0000 12: 0xDB07 0x6CB6 0x0001 0x0000 0x0000 13: 0xDB17 0x6CB6 0x0001 0x0000 0x0000 14: 0xDB1B 0x6CB6 0x0001 0x0000 0x0000 15: 0xD91B 0xECB6 0x0001 0x0000 0x0000 16: 0xD81B 0xECB6 0x0001 0x0000 0x0000 17: 0xDA1B 0xECB6 0x0001 0x0000 0x0000 18: 0xDB1B 0x6CB6 0x0001 0x0000 0x0000 19: 0xDB19 0x6CB7 0x0001 0x0000 0x0000 20: 0xDB18 0x6CB7 0x0001 0x0000 0x0000 21: 0xDB1A 0x6CB7 0x0001 0x0000 0x0000 22: 0xDB1B 0x6CB6 0x0001 0x0000 0x0000 23: 0xDB1B 0x3CB6 0x0001 0x0000 0x0000 24: 0xDB1B 0x1CB6 0x0001 0x0000 0x0000 25: 0xDB1B 0x5CB6 0x0001 0x0000 0x0000 26: 0xDB1B 0x6CB6 0x0001 0x0000 0x0000 27: 0xDB1B 0x6CBC 0x0001 0x0000 0x0000 28: 0xDB1B 0x6CB8 0x0001 0x0000 0x0000 29: 0xDB1B 0x6CBA 0x0001 0x0000 0x0000 30: 0xDB1B 0x6CB6 0x0001 0x0000 0x0000 31: 0xDB1B 0x66B6 0x0001 0x0000 0x0000 32: 0xDB1B 0x62B6 0x0001 0x0000 0x0000 33: 0xDB1B 0x6AB6 0x0001 0x0000 0x0000 34: 0xDB1B 0x6CB6 0x0001 0x0000 0x0000 35: 0xDB1B 0x6CE6 0x0001 0x0000 0x0000 36: 0xDB1B 0x6CC6 0x0001 0x0000 0x0000 37: 0xDB1B 0x6CD6 0x0001 0x0000 0x0000 38: 0xDB1B 0x6CB6 0x0001 0x0000 0x0000 39: 0xDB1B 0x6C36 0x0003 0x0000 0x0000 40: 0xDB1B 0x6C36 0x0002 0x0000 0x0000 41: 0xDB1B 0x6CB6 0x0002 0x0000 0x0000 42: 0xDB1B 0x6CB6 0x0001 0x0000 0x0000 43: 0x2404 0x9249 0x0002 0x0000 0x0000 44: 0x6404 0x9249 0x0002 0x0000 0x0000 45: 0xC404 0x9249 0x0002 0x0000 0x0000 46: 0xA404 0x9249 0x0002 0x0000 0x0000 47: 0x2404 0x9249 0x0002 0x0000 0x0000 48: 0x2C04 0x9249 0x0002 0x0000 0x0000 49: 0x3804 0x9249 0x0002 0x0000 0x0000 50: 0x3404 0x9249 0x0002 0x0000 0x0000 51: 0x2404 0x9249 0x0002 0x0000 0x0000 52: 0x240C 0x9249 0x0002 0x0000 0x0000 53: 0x2418 0x9249 0x0002 0x0000 0x0000 54: 0x2414 0x9249 0x0002 0x0000 0x0000 55: 0x2404 0x9249 0x0002 0x0000 0x0000 56: 0x2504 0x9249 0x0002 0x0000 0x0000 57: 0x2704 0x1249 0x0002 0x0000 0x0000 58: 0x2604 0x9249 0x0002 0x0000 0x0000 59: 0x2404 0x9249 0x0002 0x0000 0x0000 60: 0x2405 0x9249 0x0002 0x0000 0x0000 61: 0x2407 0x9248 0x0002 0x0000 0x0000 62: 0x2406 0x9249 0x0002 0x0000 0x0000 63: 0x2404 0x9249 0x0002 0x0000 0x0000 64: 0x2404 0xB249 0x0002 0x0000 0x0000 65: 0x2404 0xE249 0x0002 0x0000 0x0000 66: 0x2404 0xD249 0x0002 0x0000 0x0000 67: 0x2404 0x9249 0x0002 0x0000 0x0000 68: 0x2404 0x924D 0x0002 0x0000 0x0000 69: 0x2404 0x9247 0x0002 0x0000 0x0000 70: 0x2404 0x924B 0x0002 0x0000 0x0000 71: 0x2404 0x9249 0x0002 0x0000 0x0000 72: 0x2404 0x9649 0x0002 0x0000 0x0000 73: 0x2404 0x9C49 0x0002 0x0000 0x0000 74: 0x2404 0x9A49 0x0002 0x0000 0x0000 75: 0x2404 0x9249 0x0002 0x0000 0x0000 76: 0x2404 0x9269 0x0002 0x0000 0x0000 77: 0x2404 0x9239 0x0002 0x0000 0x0000 78: 0x2404 0x9259 0x0002 0x0000 0x0000 79: 0x2404 0x9249 0x0002 0x0000 0x0000 80: 0x2404 0x9249 0x0003 0x0000 0x0000 81: 0x2404 0x92C9 0x0001 0x0000 0x0000 82: 0x2404 0x92C9 0x0002 0x0000 0x0000 83: 0x2404 0x9249 0x0002 0x0000 0x0000 PINs used (in edge connector order) (G=ground,P=power) SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBB LETTER ABCDEFHJKLMNPRSTUVABCDEFHJKLMNPRSTUVABCDEFHJKLMNPRSTUVABCDEFHJKLMNPRSTUV SIDE 111111111111111111222222222222222222111111111111111111222222222222222222 USAGE IIOIIOIIOIIOIIOG P GIIOIIOIIOIIOIIO G P G UUT inputs: 20 UUT outputs: 10 pins used: 30 not used: 36 83 'test steps' 119 lines M113 10 2-input NAND PINS Main menu Mon Jul 10 12:32:54 2017 test file is: tests\m113.tst delay is: 0 trigger is: 1 1 read test file 2 set test delay 3 set test trigger 4 run test 5 output loading test 8 diags 9 exit UUT power is okay Mon Jul 10 12:33:00 2017 space single step O run once (one test, all steps) F run, stop on fail G go (run tests N run, stop on fail, no print S scope (run, no print) C turn on comment printout + increase speed (less delay) - decrease speed (more delay)(slower) Q quit test scope (run, no print) pppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppp space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn on comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFDEFHJKHJKLMNLMNPRSPRSTUV SIDE 111111222111222111222111222222 DIRECTION IIOIIOIIOIIOIIOIIOIIOIIOIIOIIO all fails was lo 000000000000000000000000000000 falling vvvvvvvvvvvvvvvvvvvvvvvvvvvvvv rising ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ was hi 111111111111111111111111111111 total fails 0, total passes 68 Main menu Mon Jul 10 12:33:04 2017 test file is: tests\m113.tst delay is: 0 trigger is: 1 1 read test file 2 set test delay 3 set test trigger 4 run test 5 output loading test 8 diags 9 exit UUT power is okay Mon Jul 10 12:33:50 2017 space single step O run once (one test, all steps) F run, stop on fail G go (run tests N run, stop on fail, no print S scope (run, no print) C turn on comment printout + increase speed (less delay) - decrease speed (more delay)(slower) Q quit test scope (run, no print) ppppppppppppppppppppppp space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn on comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFDEFHJKHJKLMNLMNPRSPRSTUV SIDE 111111222111222111222111222222 DIRECTION IIOIIOIIOIIOIIOIIOIIOIIOIIOIIO all fails was lo 000000000000000000000000000000 falling vvvvvvvvvvvvvvvvvvvvvvvvvvvvvv rising ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ was hi 111111111111111111111111111111 total fails 0, total passes 23 Main menu Mon Jul 10 12:33:52 2017 test file is: tests\m113.tst delay is: 0 trigger is: 1 1 read test file 2 set test delay 3 set test trigger 4 run test 5 output loading test 8 diags 9 exit UUT power is okay Mon Jul 10 12:34:14 2017 space single step O run once (one test, all steps) F run, stop on fail G go (run tests N run, stop on fail, no print S scope (run, no print) C turn on comment printout + increase speed (less delay) - decrease speed (more delay)(slower) Q quit test scope (run, no print) pppppppppppppppppppppppppppp space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn on comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFDEFHJKHJKLMNLMNPRSPRSTUV SIDE 111111222111222111222111222222 DIRECTION IIOIIOIIOIIOIIOIIOIIOIIOIIOIIO all fails was lo 000000000000000000000000000000 falling vvvvvvvvvvvvvvvvvvvvvvvvvvvvvv rising ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ was hi 111111111111111111111111111111 total fails 0, total passes 28 Main menu Mon Jul 10 12:34:15 2017 test file is: tests\m113.tst delay is: 0 trigger is: 1 1 read test file 2 set test delay 3 set test trigger 4 run test 5 output loading test 8 diags 9 exit UUT power is okay Mon Jul 10 12:34:47 2017 space single step O run once (one test, all steps) F run, stop on fail G go (run tests N run, stop on fail, no print S scope (run, no print) C turn on comment printout + increase speed (less delay) - decrease speed (more delay)(slower) Q quit test scope (run, no print) ppppppppppppppppppppppppppppppp space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn on comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFDEFHJKHJKLMNLMNPRSPRSTUV SIDE 111111222111222111222111222222 DIRECTION IIOIIOIIOIIOIIOIIOIIOIIOIIOIIO all fails was lo 000000000000000000000000000000 falling vvvvvvvvvvvvvvvvvvvvvvvvvvvvvv rising ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ was hi 111111111111111111111111111111 total fails 0, total passes 31 Main menu Mon Jul 10 12:34:49 2017 test file is: tests\m113.tst delay is: 0 trigger is: 1 1 read test file 2 set test delay 3 set test trigger 4 run test 5 output loading test 8 diags 9 exit UUT power is okay Mon Jul 10 12:35:11 2017 space single step O run once (one test, all steps) F run, stop on fail G go (run tests N run, stop on fail, no print S scope (run, no print) C turn on comment printout + increase speed (less delay) - decrease speed (more delay)(slower) Q quit test scope (run, no print) ppppppppppppppppppppppppppp space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn on comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFDEFHJKHJKLMNLMNPRSPRSTUV SIDE 111111222111222111222111222222 DIRECTION IIOIIOIIOIIOIIOIIOIIOIIOIIOIIO all fails was lo 000000000000000000000000000000 falling vvvvvvvvvvvvvvvvvvvvvvvvvvvvvv rising ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ was hi 111111111111111111111111111111 total fails 0, total passes 27 Main menu Mon Jul 10 12:35:13 2017 test file is: tests\m113.tst delay is: 0 trigger is: 1 1 read test file 2 set test delay 3 set test trigger 4 run test 5 output loading test 8 diags 9 exit UUT power is okay Mon Jul 10 12:35:29 2017 space single step O run once (one test, all steps) F run, stop on fail G go (run tests N run, stop on fail, no print S scope (run, no print) C turn on comment printout + increase speed (less delay) - decrease speed (more delay)(slower) Q quit test scope (run, no print) pppppppppppppppppppppppp space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn on comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFDEFHJKHJKLMNLMNPRSPRSTUV SIDE 111111222111222111222111222222 DIRECTION IIOIIOIIOIIOIIOIIOIIOIIOIIOIIO all fails was lo 000000000000000000000000000000 falling vvvvvvvvvvvvvvvvvvvvvvvvvvvvvv rising ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ was hi 111111111111111111111111111111 total fails 0, total passes 24 Main menu Mon Jul 10 12:35:31 2017 test file is: tests\m113.tst delay is: 0 trigger is: 1 1 read test file 2 set test delay 3 set test trigger 4 run test 5 output loading test 8 diags 9 exit UUT power is okay Mon Jul 10 12:35:44 2017 space single step O run once (one test, all steps) F run, stop on fail G go (run tests N run, stop on fail, no print S scope (run, no print) C turn on comment printout + increase speed (less delay) - decrease speed (more delay)(slower) Q quit test scope (run, no print) pppppppppppppppppppppppppppp space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn on comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFDEFHJKHJKLMNLMNPRSPRSTUV SIDE 111111222111222111222111222222 DIRECTION IIOIIOIIOIIOIIOIIOIIOIIOIIOIIO all fails was lo 000000000000000000000000000000 falling vvvvvvvvvvvvvvvvvvvvvvvvvvvvvv rising ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ was hi 111111111111111111111111111111 total fails 0, total passes 28 Main menu Mon Jul 10 12:35:46 2017 test file is: tests\m113.tst delay is: 0 trigger is: 1 1 read test file 2 set test delay 3 set test trigger 4 run test 5 output loading test 8 diags 9 exit Enter test file name? trying to open test file: tests\m117.tst reading test file: tests\m117.tst comment: M117 REV 3 6 4-input NAND comment: pins: PINS pins: 1 I AA1 E1-13 pins: 2 I AB1 E1-12 pins: 3 I AC1 E1-10 pins: 4 I AD1 E1-9 pins: 5 O AE1 E1-8 pins: 6 I AF1 E2-13 pins: 7 I AH1 E2-12 pins: 8 I AJ1 E2-10 pins: 9 I AK1 E2-9 pins: 10 O AL1 E2-8 pins: 11 I AM1 E3-13 pins: 12 I AN1 E3-12 pins: 13 I AP1 E3-10 pins: 14 I AR1 E3-9 pins: 15 O AS1 E3-8 pins: 16 I AD2 E1-5 pins: 17 I AE2 E1-4 pins: 18 I AF2 E1-2 pins: 19 I AH2 E1-1 pins: 20 O AJ2 E1-6 pins: 21 I AK2 E2-5 pins: 22 I AL2 E2-4 pins: 23 I AM2 E2-2 pins: 24 I AN2 E2-1 pins: 25 O AP2 E2-6 pins: 26 I AR2 E3-1 pins: 27 I AS2 E3-2 pins: 28 I AT2 E3-4 pins: 29 I AU2 E3-5 pins: 30 O AV2 E3-6 pins: direction: IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO test 1: 000010000100001000010000100001 test 2: 00001 test 3: 00011 test 4: 00101 test 5: 00111 test 6: 01001 test 7: 01011 test 8: 01101 test 9: 01111 test 10: 10001 test 11: 10011 test 12: 10101 test 13: 10111 test 14: 11001 test 15: 11011 test 16: 11101 test 17: 11110 test 18: 00001 test 19: 00001 test 20: 00011 test 21: 00101 test 22: 00111 test 23: 01001 test 24: 01011 test 25: 01101 test 26: 01111 test 27: 10001 test 28: 10011 test 29: 10101 test 30: 10111 test 31: 11001 test 32: 11011 test 33: 11101 test 34: 11110 test 35: 00001 test 36: 00001 test 37: 00011 test 38: 00101 test 39: 00111 test 40: 01001 test 41: 01011 test 42: 01101 test 43: 01111 test 44: 10001 test 45: 10011 test 46: 10101 test 47: 10111 test 48: 11001 test 49: 11011 test 50: 11101 test 51: 11110 test 52: 00001 test 53: 00001 test 54: 00011 test 55: 00101 test 56: 00111 test 57: 01001 test 58: 01011 test 59: 01101 test 60: 01111 test 61: 10001 test 62: 10011 test 63: 10101 test 64: 10111 test 65: 11001 test 66: 11011 test 67: 11101 test 68: 11110 test 69: 00001 test 70: 00001 test 71: 00011 test 72: 00101 test 73: 00111 test 74: 01001 test 75: 01011 test 76: 01101 test 77: 01111 test 78: 10001 test 79: 10011 test 80: 10101 test 81: 10111 test 82: 11001 test 83: 11011 test 84: 11101 test 85: 11110 test 86: 00001 test 87: 00001 test 88: 00011 test 89: 00101 test 90: 00111 test 91: 01001 test 92: 01011 test 93: 01101 test 94: 01111 test 95: 10001 test 96: 10011 test 97: 10101 test 98: 10111 test 99: 11001 test 100: 11011 test 101: 11101 test 102: 11110 test 103: 00001 test 104: 000010000100001000010000100001 test 105: 111101111011110111101111011110 test 106: 00001 test 107: 00011 test 108: 00101 test 109: 00111 test 110: 01001 test 111: 01011 test 112: 01101 test 113: 01111 test 114: 10001 test 115: 10011 test 116: 10101 test 117: 10111 test 118: 11001 test 119: 11011 test 120: 11101 test 121: 11110 test 122: 00001 test 123: 00011 test 124: 00101 test 125: 00111 test 126: 01001 test 127: 01011 test 128: 01101 test 129: 01111 test 130: 10001 test 131: 10011 test 132: 10101 test 133: 10111 test 134: 11001 test 135: 11011 test 136: 11101 test 137: 11110 test 138: 00001 test 139: 00011 test 140: 00101 test 141: 00111 test 142: 01001 test 143: 01011 test 144: 01101 test 145: 01111 test 146: 10001 test 147: 10011 test 148: 10101 test 149: 10111 test 150: 11001 test 151: 11011 test 152: 11101 test 153: 11110 test 154: 00001 test 155: 00011 test 156: 00101 test 157: 00111 test 158: 01001 test 159: 01011 test 160: 01101 test 161: 01111 test 162: 10001 test 163: 10011 test 164: 10101 test 165: 10111 test 166: 11001 test 167: 11011 test 168: 11101 test 169: 11110 test 170: 00001 test 171: 00011 test 172: 00101 test 173: 00111 test 174: 01001 test 175: 01011 test 176: 01101 test 177: 01111 test 178: 10001 test 179: 10011 test 180: 10101 test 181: 10111 test 182: 11001 test 183: 11011 test 184: 11101 test 185: 11110 test 186: 00001 test 187: 00011 test 188: 00101 test 189: 00111 test 190: 01001 test 191: 01011 test 192: 01101 test 193: 01111 test 194: 10001 test 195: 10011 test 196: 10101 test 197: 10111 test 198: 11001 test 199: 11011 test 200: 11101 test 201: 11110 test 202: 111101111011110111101111011110 end: END summary column 1: offset 0, mask 0x8000 column 2: offset 0, mask 0x4000 column 3: offset 0, mask 0x2000 column 4: offset 0, mask 0x1000 column 5: offset 0, mask 0x0800 column 6: offset 0, mask 0x0400 column 7: offset 0, mask 0x0200 column 8: offset 0, mask 0x0100 column 9: offset 1, mask 0x8000 column 10: offset 1, mask 0x4000 column 11: offset 1, mask 0x2000 column 12: offset 1, mask 0x1000 column 13: offset 1, mask 0x0800 column 14: offset 1, mask 0x0400 column 15: offset 1, mask 0x0200 column 16: offset 0, mask 0x0010 column 17: offset 0, mask 0x0008 column 18: offset 0, mask 0x0004 column 19: offset 0, mask 0x0002 column 20: offset 0, mask 0x0001 column 21: offset 1, mask 0x0001 column 22: offset 1, mask 0x0002 column 23: offset 1, mask 0x0004 column 24: offset 1, mask 0x0008 column 25: offset 1, mask 0x0010 column 26: offset 1, mask 0x0020 column 27: offset 1, mask 0x0040 column 28: offset 1, mask 0x0080 column 29: offset 2, mask 0x0001 column 30: offset 2, mask 0x0002 direction bits (1=input) 0x08E1 0x4310 0xFFFA 0xFFFF 0xF0FF pullup bits (1=pullup) 0x0000 0x0000 0x0000 0x0000 0x0000 test step out_data dont care 1: 0x0801 0x4210 0x0002 0x0000 0x0000 2: 0x0801 0x4210 0x0002 0x0000 0x0000 3: 0x1801 0x4210 0x0002 0x0000 0x0000 4: 0x2801 0x4210 0x0002 0x0000 0x0000 5: 0x3801 0x4210 0x0002 0x0000 0x0000 6: 0x4801 0x4210 0x0002 0x0000 0x0000 7: 0x5801 0x4210 0x0002 0x0000 0x0000 8: 0x6801 0x4210 0x0002 0x0000 0x0000 9: 0x7801 0x4210 0x0002 0x0000 0x0000 10: 0x8801 0x4210 0x0002 0x0000 0x0000 11: 0x9801 0x4210 0x0002 0x0000 0x0000 12: 0xA801 0x4210 0x0002 0x0000 0x0000 13: 0xB801 0x4210 0x0002 0x0000 0x0000 14: 0xC801 0x4210 0x0002 0x0000 0x0000 15: 0xD801 0x4210 0x0002 0x0000 0x0000 16: 0xE801 0x4210 0x0002 0x0000 0x0000 17: 0xF001 0x4210 0x0002 0x0000 0x0000 18: 0x0801 0x4210 0x0002 0x0000 0x0000 19: 0x0801 0x4210 0x0002 0x0000 0x0000 20: 0x0801 0xC210 0x0002 0x0000 0x0000 21: 0x0901 0x4210 0x0002 0x0000 0x0000 22: 0x0901 0xC210 0x0002 0x0000 0x0000 23: 0x0A01 0x4210 0x0002 0x0000 0x0000 24: 0x0A01 0xC210 0x0002 0x0000 0x0000 25: 0x0B01 0x4210 0x0002 0x0000 0x0000 26: 0x0B01 0xC210 0x0002 0x0000 0x0000 27: 0x0C01 0x4210 0x0002 0x0000 0x0000 28: 0x0C01 0xC210 0x0002 0x0000 0x0000 29: 0x0D01 0x4210 0x0002 0x0000 0x0000 30: 0x0D01 0xC210 0x0002 0x0000 0x0000 31: 0x0E01 0x4210 0x0002 0x0000 0x0000 32: 0x0E01 0xC210 0x0002 0x0000 0x0000 33: 0x0F01 0x4210 0x0002 0x0000 0x0000 34: 0x0F01 0x8210 0x0002 0x0000 0x0000 35: 0x0801 0x4210 0x0002 0x0000 0x0000 36: 0x0801 0x4210 0x0002 0x0000 0x0000 37: 0x0801 0x4610 0x0002 0x0000 0x0000 38: 0x0801 0x4A10 0x0002 0x0000 0x0000 39: 0x0801 0x4E10 0x0002 0x0000 0x0000 40: 0x0801 0x5210 0x0002 0x0000 0x0000 41: 0x0801 0x5610 0x0002 0x0000 0x0000 42: 0x0801 0x5A10 0x0002 0x0000 0x0000 43: 0x0801 0x5E10 0x0002 0x0000 0x0000 44: 0x0801 0x6210 0x0002 0x0000 0x0000 45: 0x0801 0x6610 0x0002 0x0000 0x0000 46: 0x0801 0x6A10 0x0002 0x0000 0x0000 47: 0x0801 0x6E10 0x0002 0x0000 0x0000 48: 0x0801 0x7210 0x0002 0x0000 0x0000 49: 0x0801 0x7610 0x0002 0x0000 0x0000 50: 0x0801 0x7A10 0x0002 0x0000 0x0000 51: 0x0801 0x7C10 0x0002 0x0000 0x0000 52: 0x0801 0x4210 0x0002 0x0000 0x0000 53: 0x0801 0x4210 0x0002 0x0000 0x0000 54: 0x0803 0x4210 0x0002 0x0000 0x0000 55: 0x0805 0x4210 0x0002 0x0000 0x0000 56: 0x0807 0x4210 0x0002 0x0000 0x0000 57: 0x0809 0x4210 0x0002 0x0000 0x0000 58: 0x080B 0x4210 0x0002 0x0000 0x0000 59: 0x080D 0x4210 0x0002 0x0000 0x0000 60: 0x080F 0x4210 0x0002 0x0000 0x0000 61: 0x0811 0x4210 0x0002 0x0000 0x0000 62: 0x0813 0x4210 0x0002 0x0000 0x0000 63: 0x0815 0x4210 0x0002 0x0000 0x0000 64: 0x0817 0x4210 0x0002 0x0000 0x0000 65: 0x0819 0x4210 0x0002 0x0000 0x0000 66: 0x081B 0x4210 0x0002 0x0000 0x0000 67: 0x081D 0x4210 0x0002 0x0000 0x0000 68: 0x081E 0x4210 0x0002 0x0000 0x0000 69: 0x0801 0x4210 0x0002 0x0000 0x0000 70: 0x0801 0x4210 0x0002 0x0000 0x0000 71: 0x0801 0x4218 0x0002 0x0000 0x0000 72: 0x0801 0x4214 0x0002 0x0000 0x0000 73: 0x0801 0x421C 0x0002 0x0000 0x0000 74: 0x0801 0x4212 0x0002 0x0000 0x0000 75: 0x0801 0x421A 0x0002 0x0000 0x0000 76: 0x0801 0x4216 0x0002 0x0000 0x0000 77: 0x0801 0x421E 0x0002 0x0000 0x0000 78: 0x0801 0x4211 0x0002 0x0000 0x0000 79: 0x0801 0x4219 0x0002 0x0000 0x0000 80: 0x0801 0x4215 0x0002 0x0000 0x0000 81: 0x0801 0x421D 0x0002 0x0000 0x0000 82: 0x0801 0x4213 0x0002 0x0000 0x0000 83: 0x0801 0x421B 0x0002 0x0000 0x0000 84: 0x0801 0x4217 0x0002 0x0000 0x0000 85: 0x0801 0x420F 0x0002 0x0000 0x0000 86: 0x0801 0x4210 0x0002 0x0000 0x0000 87: 0x0801 0x4210 0x0002 0x0000 0x0000 88: 0x0801 0x4210 0x0003 0x0000 0x0000 89: 0x0801 0x4290 0x0002 0x0000 0x0000 90: 0x0801 0x4290 0x0003 0x0000 0x0000 91: 0x0801 0x4250 0x0002 0x0000 0x0000 92: 0x0801 0x4250 0x0003 0x0000 0x0000 93: 0x0801 0x42D0 0x0002 0x0000 0x0000 94: 0x0801 0x42D0 0x0003 0x0000 0x0000 95: 0x0801 0x4230 0x0002 0x0000 0x0000 96: 0x0801 0x4230 0x0003 0x0000 0x0000 97: 0x0801 0x42B0 0x0002 0x0000 0x0000 98: 0x0801 0x42B0 0x0003 0x0000 0x0000 99: 0x0801 0x4270 0x0002 0x0000 0x0000 100: 0x0801 0x4270 0x0003 0x0000 0x0000 101: 0x0801 0x42F0 0x0002 0x0000 0x0000 102: 0x0801 0x42F0 0x0001 0x0000 0x0000 103: 0x0801 0x4210 0x0002 0x0000 0x0000 104: 0x0801 0x4210 0x0002 0x0000 0x0000 105: 0xF71E 0xBCEF 0x0001 0x0000 0x0000 106: 0x0F1E 0xBCEF 0x0001 0x0000 0x0000 107: 0x1F1E 0xBCEF 0x0001 0x0000 0x0000 108: 0x2F1E 0xBCEF 0x0001 0x0000 0x0000 109: 0x3F1E 0xBCEF 0x0001 0x0000 0x0000 110: 0x4F1E 0xBCEF 0x0001 0x0000 0x0000 111: 0x5F1E 0xBCEF 0x0001 0x0000 0x0000 112: 0x6F1E 0xBCEF 0x0001 0x0000 0x0000 113: 0x7F1E 0xBCEF 0x0001 0x0000 0x0000 114: 0x8F1E 0xBCEF 0x0001 0x0000 0x0000 115: 0x9F1E 0xBCEF 0x0001 0x0000 0x0000 116: 0xAF1E 0xBCEF 0x0001 0x0000 0x0000 117: 0xBF1E 0xBCEF 0x0001 0x0000 0x0000 118: 0xCF1E 0xBCEF 0x0001 0x0000 0x0000 119: 0xDF1E 0xBCEF 0x0001 0x0000 0x0000 120: 0xEF1E 0xBCEF 0x0001 0x0000 0x0000 121: 0xF71E 0xBCEF 0x0001 0x0000 0x0000 122: 0xF01E 0x7CEF 0x0001 0x0000 0x0000 123: 0xF01E 0xFCEF 0x0001 0x0000 0x0000 124: 0xF11E 0x7CEF 0x0001 0x0000 0x0000 125: 0xF11E 0xFCEF 0x0001 0x0000 0x0000 126: 0xF21E 0x7CEF 0x0001 0x0000 0x0000 127: 0xF21E 0xFCEF 0x0001 0x0000 0x0000 128: 0xF31E 0x7CEF 0x0001 0x0000 0x0000 129: 0xF31E 0xFCEF 0x0001 0x0000 0x0000 130: 0xF41E 0x7CEF 0x0001 0x0000 0x0000 131: 0xF41E 0xFCEF 0x0001 0x0000 0x0000 132: 0xF51E 0x7CEF 0x0001 0x0000 0x0000 133: 0xF51E 0xFCEF 0x0001 0x0000 0x0000 134: 0xF61E 0x7CEF 0x0001 0x0000 0x0000 135: 0xF61E 0xFCEF 0x0001 0x0000 0x0000 136: 0xF71E 0x7CEF 0x0001 0x0000 0x0000 137: 0xF71E 0xBCEF 0x0001 0x0000 0x0000 138: 0xF71E 0x82EF 0x0001 0x0000 0x0000 139: 0xF71E 0x86EF 0x0001 0x0000 0x0000 140: 0xF71E 0x8AEF 0x0001 0x0000 0x0000 141: 0xF71E 0x8EEF 0x0001 0x0000 0x0000 142: 0xF71E 0x92EF 0x0001 0x0000 0x0000 143: 0xF71E 0x96EF 0x0001 0x0000 0x0000 144: 0xF71E 0x9AEF 0x0001 0x0000 0x0000 145: 0xF71E 0x9EEF 0x0001 0x0000 0x0000 146: 0xF71E 0xA2EF 0x0001 0x0000 0x0000 147: 0xF71E 0xA6EF 0x0001 0x0000 0x0000 148: 0xF71E 0xAAEF 0x0001 0x0000 0x0000 149: 0xF71E 0xAEEF 0x0001 0x0000 0x0000 150: 0xF71E 0xB2EF 0x0001 0x0000 0x0000 151: 0xF71E 0xB6EF 0x0001 0x0000 0x0000 152: 0xF71E 0xBAEF 0x0001 0x0000 0x0000 153: 0xF71E 0xBCEF 0x0001 0x0000 0x0000 154: 0xF701 0xBCEF 0x0001 0x0000 0x0000 155: 0xF703 0xBCEF 0x0001 0x0000 0x0000 156: 0xF705 0xBCEF 0x0001 0x0000 0x0000 157: 0xF707 0xBCEF 0x0001 0x0000 0x0000 158: 0xF709 0xBCEF 0x0001 0x0000 0x0000 159: 0xF70B 0xBCEF 0x0001 0x0000 0x0000 160: 0xF70D 0xBCEF 0x0001 0x0000 0x0000 161: 0xF70F 0xBCEF 0x0001 0x0000 0x0000 162: 0xF711 0xBCEF 0x0001 0x0000 0x0000 163: 0xF713 0xBCEF 0x0001 0x0000 0x0000 164: 0xF715 0xBCEF 0x0001 0x0000 0x0000 165: 0xF717 0xBCEF 0x0001 0x0000 0x0000 166: 0xF719 0xBCEF 0x0001 0x0000 0x0000 167: 0xF71B 0xBCEF 0x0001 0x0000 0x0000 168: 0xF71D 0xBCEF 0x0001 0x0000 0x0000 169: 0xF71E 0xBCEF 0x0001 0x0000 0x0000 170: 0xF71E 0xBCF0 0x0001 0x0000 0x0000 171: 0xF71E 0xBCF8 0x0001 0x0000 0x0000 172: 0xF71E 0xBCF4 0x0001 0x0000 0x0000 173: 0xF71E 0xBCFC 0x0001 0x0000 0x0000 174: 0xF71E 0xBCF2 0x0001 0x0000 0x0000 175: 0xF71E 0xBCFA 0x0001 0x0000 0x0000 176: 0xF71E 0xBCF6 0x0001 0x0000 0x0000 177: 0xF71E 0xBCFE 0x0001 0x0000 0x0000 178: 0xF71E 0xBCF1 0x0001 0x0000 0x0000 179: 0xF71E 0xBCF9 0x0001 0x0000 0x0000 180: 0xF71E 0xBCF5 0x0001 0x0000 0x0000 181: 0xF71E 0xBCFD 0x0001 0x0000 0x0000 182: 0xF71E 0xBCF3 0x0001 0x0000 0x0000 183: 0xF71E 0xBCFB 0x0001 0x0000 0x0000 184: 0xF71E 0xBCF7 0x0001 0x0000 0x0000 185: 0xF71E 0xBCEF 0x0001 0x0000 0x0000 186: 0xF71E 0xBC0F 0x0002 0x0000 0x0000 187: 0xF71E 0xBC0F 0x0003 0x0000 0x0000 188: 0xF71E 0xBC8F 0x0002 0x0000 0x0000 189: 0xF71E 0xBC8F 0x0003 0x0000 0x0000 190: 0xF71E 0xBC4F 0x0002 0x0000 0x0000 191: 0xF71E 0xBC4F 0x0003 0x0000 0x0000 192: 0xF71E 0xBCCF 0x0002 0x0000 0x0000 193: 0xF71E 0xBCCF 0x0003 0x0000 0x0000 194: 0xF71E 0xBC2F 0x0002 0x0000 0x0000 195: 0xF71E 0xBC2F 0x0003 0x0000 0x0000 196: 0xF71E 0xBCAF 0x0002 0x0000 0x0000 197: 0xF71E 0xBCAF 0x0003 0x0000 0x0000 198: 0xF71E 0xBC6F 0x0002 0x0000 0x0000 199: 0xF71E 0xBC6F 0x0003 0x0000 0x0000 200: 0xF71E 0xBCEF 0x0002 0x0000 0x0000 201: 0xF71E 0xBCEF 0x0001 0x0000 0x0000 202: 0xF71E 0xBCEF 0x0001 0x0000 0x0000 PINs used (in edge connector order) (G=ground,P=power) SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBB LETTER ABCDEFHJKLMNPRSTUVABCDEFHJKLMNPRSTUVABCDEFHJKLMNPRSTUVABCDEFHJKLMNPRSTUV SIDE 111111111111111111222222222222222222111111111111111111222222222222222222 USAGE IIIIOIIIIOIIIIOG P GIIIIOIIIIOIIIIO G P G UUT inputs: 24 UUT outputs: 6 pins used: 30 not used: 36 202 'test steps' 238 lines M117 REV 3 6 4-input NAND PINS Main menu Mon Jul 10 12:36:04 2017 test file is: tests\m117.tst delay is: 0 trigger is: 1 1 read test file 2 set test delay 3 set test trigger 4 run test 5 output loading test 8 diags 9 exit UUT power is okay Mon Jul 10 12:36:07 2017 space single step O run once (one test, all steps) F run, stop on fail G go (run tests N run, stop on fail, no print S scope (run, no print) C turn on comment printout + increase speed (less delay) - decrease speed (more delay)(slower) Q quit test scope (run, no print) pppppppppppppppp space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn on comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFHJKLMNPRSDEFHJKLMNPRSTUV SIDE 111111111111111222222222222222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO all fails was lo 000000000000000000000000000000 falling vvvvvvvvvvvvvvvvvvvvvvvvvvvvvv rising ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ was hi 111111111111111111111111111111 total fails 0, total passes 16 Main menu Mon Jul 10 12:36:10 2017 test file is: tests\m117.tst delay is: 0 trigger is: 1 1 read test file 2 set test delay 3 set test trigger 4 run test 5 output loading test 8 diags 9 exit Enter test file name? trying to open test file: tests\m617.tst reading test file: tests\m617.tst comment: M617 REV E 6 4-INPUT NAND BUFFERS (48ma) (7440) comment: pins: PINS pins: 1 I AA1 E1-13 pins: 2 I AB1 E1-12 pins: 3 I AC1 E1-10 pins: 4 I AD1 E1-9 pins: 5 O AE1 E1-8 pins: 6 I AF1 E2-13 pins: 7 I AH1 E2-12 pins: 8 I AJ1 E2-10 pins: 9 I AK1 E2-9 pins: 10 O AL1 E2-8 pins: 11 I AM1 E3-13 pins: 12 I AN1 E3-12 pins: 13 I AP1 E3-10 pins: 14 I AR1 E3-9 pins: 15 O AS1 E3-8 pins: 16 I AD2 E1-5 pins: 17 I AE2 E1-4 pins: 18 I AF2 E1-2 pins: 19 I AH2 E1-1 pins: 20 O AJ2 E1-6 pins: 21 I AK2 E2-5 pins: 22 I AL2 E2-4 pins: 23 I AM2 E2-2 pins: 24 I AN2 E2-1 pins: 25 O AP2 E2-6 pins: 26 I AR2 E3-1 pins: 27 I AS2 E3-2 pins: 28 I AT2 E3-4 pins: 29 I AU2 E3-5 pins: 30 O AV2 E3-6 pins: direction: IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO test 1: 000010000100001000010000100001 test 2: 00001 test 3: 00011 test 4: 00101 test 5: 00111 test 6: 01001 test 7: 01011 test 8: 01101 test 9: 01111 test 10: 10001 test 11: 10011 test 12: 10101 test 13: 10111 test 14: 11001 test 15: 11011 test 16: 11101 test 17: 11110 test 18: 00001 test 19: 00001 test 20: 00011 test 21: 00101 test 22: 00111 test 23: 01001 test 24: 01011 test 25: 01101 test 26: 01111 test 27: 10001 test 28: 10011 test 29: 10101 test 30: 10111 test 31: 11001 test 32: 11011 test 33: 11101 test 34: 11110 test 35: 00001 test 36: 00001 test 37: 00011 test 38: 00101 test 39: 00111 test 40: 01001 test 41: 01011 test 42: 01101 test 43: 01111 test 44: 10001 test 45: 10011 test 46: 10101 test 47: 10111 test 48: 11001 test 49: 11011 test 50: 11101 test 51: 11110 test 52: 00001 test 53: 00001 test 54: 00011 test 55: 00101 test 56: 00111 test 57: 01001 test 58: 01011 test 59: 01101 test 60: 01111 test 61: 10001 test 62: 10011 test 63: 10101 test 64: 10111 test 65: 11001 test 66: 11011 test 67: 11101 test 68: 11110 test 69: 00001 test 70: 00001 test 71: 00011 test 72: 00101 test 73: 00111 test 74: 01001 test 75: 01011 test 76: 01101 test 77: 01111 test 78: 10001 test 79: 10011 test 80: 10101 test 81: 10111 test 82: 11001 test 83: 11011 test 84: 11101 test 85: 11110 test 86: 00001 test 87: 00001 test 88: 00011 test 89: 00101 test 90: 00111 test 91: 01001 test 92: 01011 test 93: 01101 test 94: 01111 test 95: 10001 test 96: 10011 test 97: 10101 test 98: 10111 test 99: 11001 test 100: 11011 test 101: 11101 test 102: 11110 test 103: 00001 test 104: 000010000100001000010000100001 test 105: 111101111011110111101111011110 test 106: 00001 test 107: 00011 test 108: 00101 test 109: 00111 test 110: 01001 test 111: 01011 test 112: 01101 test 113: 01111 test 114: 10001 test 115: 10011 test 116: 10101 test 117: 10111 test 118: 11001 test 119: 11011 test 120: 11101 test 121: 11110 test 122: 00001 test 123: 00011 test 124: 00101 test 125: 00111 test 126: 01001 test 127: 01011 test 128: 01101 test 129: 01111 test 130: 10001 test 131: 10011 test 132: 10101 test 133: 10111 test 134: 11001 test 135: 11011 test 136: 11101 test 137: 11110 test 138: 00001 test 139: 00011 test 140: 00101 test 141: 00111 test 142: 01001 test 143: 01011 test 144: 01101 test 145: 01111 test 146: 10001 test 147: 10011 test 148: 10101 test 149: 10111 test 150: 11001 test 151: 11011 test 152: 11101 test 153: 11110 test 154: 00001 test 155: 00011 test 156: 00101 test 157: 00111 test 158: 01001 test 159: 01011 test 160: 01101 test 161: 01111 test 162: 10001 test 163: 10011 test 164: 10101 test 165: 10111 test 166: 11001 test 167: 11011 test 168: 11101 test 169: 11110 test 170: 00001 test 171: 00011 test 172: 00101 test 173: 00111 test 174: 01001 test 175: 01011 test 176: 01101 test 177: 01111 test 178: 10001 test 179: 10011 test 180: 10101 test 181: 10111 test 182: 11001 test 183: 11011 test 184: 11101 test 185: 11110 test 186: 00001 test 187: 00011 test 188: 00101 test 189: 00111 test 190: 01001 test 191: 01011 test 192: 01101 test 193: 01111 test 194: 10001 test 195: 10011 test 196: 10101 test 197: 10111 test 198: 11001 test 199: 11011 test 200: 11101 test 201: 11110 test 202: 111101111011110111101111011110 end: END summary column 1: offset 0, mask 0x8000 column 2: offset 0, mask 0x4000 column 3: offset 0, mask 0x2000 column 4: offset 0, mask 0x1000 column 5: offset 0, mask 0x0800 column 6: offset 0, mask 0x0400 column 7: offset 0, mask 0x0200 column 8: offset 0, mask 0x0100 column 9: offset 1, mask 0x8000 column 10: offset 1, mask 0x4000 column 11: offset 1, mask 0x2000 column 12: offset 1, mask 0x1000 column 13: offset 1, mask 0x0800 column 14: offset 1, mask 0x0400 column 15: offset 1, mask 0x0200 column 16: offset 0, mask 0x0010 column 17: offset 0, mask 0x0008 column 18: offset 0, mask 0x0004 column 19: offset 0, mask 0x0002 column 20: offset 0, mask 0x0001 column 21: offset 1, mask 0x0001 column 22: offset 1, mask 0x0002 column 23: offset 1, mask 0x0004 column 24: offset 1, mask 0x0008 column 25: offset 1, mask 0x0010 column 26: offset 1, mask 0x0020 column 27: offset 1, mask 0x0040 column 28: offset 1, mask 0x0080 column 29: offset 2, mask 0x0001 column 30: offset 2, mask 0x0002 direction bits (1=input) 0x08E1 0x4310 0xFFFA 0xFFFF 0xF0FF pullup bits (1=pullup) 0x0000 0x0000 0x0000 0x0000 0x0000 test step out_data dont care 1: 0x0801 0x4210 0x0002 0x0000 0x0000 2: 0x0801 0x4210 0x0002 0x0000 0x0000 3: 0x1801 0x4210 0x0002 0x0000 0x0000 4: 0x2801 0x4210 0x0002 0x0000 0x0000 5: 0x3801 0x4210 0x0002 0x0000 0x0000 6: 0x4801 0x4210 0x0002 0x0000 0x0000 7: 0x5801 0x4210 0x0002 0x0000 0x0000 8: 0x6801 0x4210 0x0002 0x0000 0x0000 9: 0x7801 0x4210 0x0002 0x0000 0x0000 10: 0x8801 0x4210 0x0002 0x0000 0x0000 11: 0x9801 0x4210 0x0002 0x0000 0x0000 12: 0xA801 0x4210 0x0002 0x0000 0x0000 13: 0xB801 0x4210 0x0002 0x0000 0x0000 14: 0xC801 0x4210 0x0002 0x0000 0x0000 15: 0xD801 0x4210 0x0002 0x0000 0x0000 16: 0xE801 0x4210 0x0002 0x0000 0x0000 17: 0xF001 0x4210 0x0002 0x0000 0x0000 18: 0x0801 0x4210 0x0002 0x0000 0x0000 19: 0x0801 0x4210 0x0002 0x0000 0x0000 20: 0x0801 0xC210 0x0002 0x0000 0x0000 21: 0x0901 0x4210 0x0002 0x0000 0x0000 22: 0x0901 0xC210 0x0002 0x0000 0x0000 23: 0x0A01 0x4210 0x0002 0x0000 0x0000 24: 0x0A01 0xC210 0x0002 0x0000 0x0000 25: 0x0B01 0x4210 0x0002 0x0000 0x0000 26: 0x0B01 0xC210 0x0002 0x0000 0x0000 27: 0x0C01 0x4210 0x0002 0x0000 0x0000 28: 0x0C01 0xC210 0x0002 0x0000 0x0000 29: 0x0D01 0x4210 0x0002 0x0000 0x0000 30: 0x0D01 0xC210 0x0002 0x0000 0x0000 31: 0x0E01 0x4210 0x0002 0x0000 0x0000 32: 0x0E01 0xC210 0x0002 0x0000 0x0000 33: 0x0F01 0x4210 0x0002 0x0000 0x0000 34: 0x0F01 0x8210 0x0002 0x0000 0x0000 35: 0x0801 0x4210 0x0002 0x0000 0x0000 36: 0x0801 0x4210 0x0002 0x0000 0x0000 37: 0x0801 0x4610 0x0002 0x0000 0x0000 38: 0x0801 0x4A10 0x0002 0x0000 0x0000 39: 0x0801 0x4E10 0x0002 0x0000 0x0000 40: 0x0801 0x5210 0x0002 0x0000 0x0000 41: 0x0801 0x5610 0x0002 0x0000 0x0000 42: 0x0801 0x5A10 0x0002 0x0000 0x0000 43: 0x0801 0x5E10 0x0002 0x0000 0x0000 44: 0x0801 0x6210 0x0002 0x0000 0x0000 45: 0x0801 0x6610 0x0002 0x0000 0x0000 46: 0x0801 0x6A10 0x0002 0x0000 0x0000 47: 0x0801 0x6E10 0x0002 0x0000 0x0000 48: 0x0801 0x7210 0x0002 0x0000 0x0000 49: 0x0801 0x7610 0x0002 0x0000 0x0000 50: 0x0801 0x7A10 0x0002 0x0000 0x0000 51: 0x0801 0x7C10 0x0002 0x0000 0x0000 52: 0x0801 0x4210 0x0002 0x0000 0x0000 53: 0x0801 0x4210 0x0002 0x0000 0x0000 54: 0x0803 0x4210 0x0002 0x0000 0x0000 55: 0x0805 0x4210 0x0002 0x0000 0x0000 56: 0x0807 0x4210 0x0002 0x0000 0x0000 57: 0x0809 0x4210 0x0002 0x0000 0x0000 58: 0x080B 0x4210 0x0002 0x0000 0x0000 59: 0x080D 0x4210 0x0002 0x0000 0x0000 60: 0x080F 0x4210 0x0002 0x0000 0x0000 61: 0x0811 0x4210 0x0002 0x0000 0x0000 62: 0x0813 0x4210 0x0002 0x0000 0x0000 63: 0x0815 0x4210 0x0002 0x0000 0x0000 64: 0x0817 0x4210 0x0002 0x0000 0x0000 65: 0x0819 0x4210 0x0002 0x0000 0x0000 66: 0x081B 0x4210 0x0002 0x0000 0x0000 67: 0x081D 0x4210 0x0002 0x0000 0x0000 68: 0x081E 0x4210 0x0002 0x0000 0x0000 69: 0x0801 0x4210 0x0002 0x0000 0x0000 70: 0x0801 0x4210 0x0002 0x0000 0x0000 71: 0x0801 0x4218 0x0002 0x0000 0x0000 72: 0x0801 0x4214 0x0002 0x0000 0x0000 73: 0x0801 0x421C 0x0002 0x0000 0x0000 74: 0x0801 0x4212 0x0002 0x0000 0x0000 75: 0x0801 0x421A 0x0002 0x0000 0x0000 76: 0x0801 0x4216 0x0002 0x0000 0x0000 77: 0x0801 0x421E 0x0002 0x0000 0x0000 78: 0x0801 0x4211 0x0002 0x0000 0x0000 79: 0x0801 0x4219 0x0002 0x0000 0x0000 80: 0x0801 0x4215 0x0002 0x0000 0x0000 81: 0x0801 0x421D 0x0002 0x0000 0x0000 82: 0x0801 0x4213 0x0002 0x0000 0x0000 83: 0x0801 0x421B 0x0002 0x0000 0x0000 84: 0x0801 0x4217 0x0002 0x0000 0x0000 85: 0x0801 0x420F 0x0002 0x0000 0x0000 86: 0x0801 0x4210 0x0002 0x0000 0x0000 87: 0x0801 0x4210 0x0002 0x0000 0x0000 88: 0x0801 0x4210 0x0003 0x0000 0x0000 89: 0x0801 0x4290 0x0002 0x0000 0x0000 90: 0x0801 0x4290 0x0003 0x0000 0x0000 91: 0x0801 0x4250 0x0002 0x0000 0x0000 92: 0x0801 0x4250 0x0003 0x0000 0x0000 93: 0x0801 0x42D0 0x0002 0x0000 0x0000 94: 0x0801 0x42D0 0x0003 0x0000 0x0000 95: 0x0801 0x4230 0x0002 0x0000 0x0000 96: 0x0801 0x4230 0x0003 0x0000 0x0000 97: 0x0801 0x42B0 0x0002 0x0000 0x0000 98: 0x0801 0x42B0 0x0003 0x0000 0x0000 99: 0x0801 0x4270 0x0002 0x0000 0x0000 100: 0x0801 0x4270 0x0003 0x0000 0x0000 101: 0x0801 0x42F0 0x0002 0x0000 0x0000 102: 0x0801 0x42F0 0x0001 0x0000 0x0000 103: 0x0801 0x4210 0x0002 0x0000 0x0000 104: 0x0801 0x4210 0x0002 0x0000 0x0000 105: 0xF71E 0xBCEF 0x0001 0x0000 0x0000 106: 0x0F1E 0xBCEF 0x0001 0x0000 0x0000 107: 0x1F1E 0xBCEF 0x0001 0x0000 0x0000 108: 0x2F1E 0xBCEF 0x0001 0x0000 0x0000 109: 0x3F1E 0xBCEF 0x0001 0x0000 0x0000 110: 0x4F1E 0xBCEF 0x0001 0x0000 0x0000 111: 0x5F1E 0xBCEF 0x0001 0x0000 0x0000 112: 0x6F1E 0xBCEF 0x0001 0x0000 0x0000 113: 0x7F1E 0xBCEF 0x0001 0x0000 0x0000 114: 0x8F1E 0xBCEF 0x0001 0x0000 0x0000 115: 0x9F1E 0xBCEF 0x0001 0x0000 0x0000 116: 0xAF1E 0xBCEF 0x0001 0x0000 0x0000 117: 0xBF1E 0xBCEF 0x0001 0x0000 0x0000 118: 0xCF1E 0xBCEF 0x0001 0x0000 0x0000 119: 0xDF1E 0xBCEF 0x0001 0x0000 0x0000 120: 0xEF1E 0xBCEF 0x0001 0x0000 0x0000 121: 0xF71E 0xBCEF 0x0001 0x0000 0x0000 122: 0xF01E 0x7CEF 0x0001 0x0000 0x0000 123: 0xF01E 0xFCEF 0x0001 0x0000 0x0000 124: 0xF11E 0x7CEF 0x0001 0x0000 0x0000 125: 0xF11E 0xFCEF 0x0001 0x0000 0x0000 126: 0xF21E 0x7CEF 0x0001 0x0000 0x0000 127: 0xF21E 0xFCEF 0x0001 0x0000 0x0000 128: 0xF31E 0x7CEF 0x0001 0x0000 0x0000 129: 0xF31E 0xFCEF 0x0001 0x0000 0x0000 130: 0xF41E 0x7CEF 0x0001 0x0000 0x0000 131: 0xF41E 0xFCEF 0x0001 0x0000 0x0000 132: 0xF51E 0x7CEF 0x0001 0x0000 0x0000 133: 0xF51E 0xFCEF 0x0001 0x0000 0x0000 134: 0xF61E 0x7CEF 0x0001 0x0000 0x0000 135: 0xF61E 0xFCEF 0x0001 0x0000 0x0000 136: 0xF71E 0x7CEF 0x0001 0x0000 0x0000 137: 0xF71E 0xBCEF 0x0001 0x0000 0x0000 138: 0xF71E 0x82EF 0x0001 0x0000 0x0000 139: 0xF71E 0x86EF 0x0001 0x0000 0x0000 140: 0xF71E 0x8AEF 0x0001 0x0000 0x0000 141: 0xF71E 0x8EEF 0x0001 0x0000 0x0000 142: 0xF71E 0x92EF 0x0001 0x0000 0x0000 143: 0xF71E 0x96EF 0x0001 0x0000 0x0000 144: 0xF71E 0x9AEF 0x0001 0x0000 0x0000 145: 0xF71E 0x9EEF 0x0001 0x0000 0x0000 146: 0xF71E 0xA2EF 0x0001 0x0000 0x0000 147: 0xF71E 0xA6EF 0x0001 0x0000 0x0000 148: 0xF71E 0xAAEF 0x0001 0x0000 0x0000 149: 0xF71E 0xAEEF 0x0001 0x0000 0x0000 150: 0xF71E 0xB2EF 0x0001 0x0000 0x0000 151: 0xF71E 0xB6EF 0x0001 0x0000 0x0000 152: 0xF71E 0xBAEF 0x0001 0x0000 0x0000 153: 0xF71E 0xBCEF 0x0001 0x0000 0x0000 154: 0xF701 0xBCEF 0x0001 0x0000 0x0000 155: 0xF703 0xBCEF 0x0001 0x0000 0x0000 156: 0xF705 0xBCEF 0x0001 0x0000 0x0000 157: 0xF707 0xBCEF 0x0001 0x0000 0x0000 158: 0xF709 0xBCEF 0x0001 0x0000 0x0000 159: 0xF70B 0xBCEF 0x0001 0x0000 0x0000 160: 0xF70D 0xBCEF 0x0001 0x0000 0x0000 161: 0xF70F 0xBCEF 0x0001 0x0000 0x0000 162: 0xF711 0xBCEF 0x0001 0x0000 0x0000 163: 0xF713 0xBCEF 0x0001 0x0000 0x0000 164: 0xF715 0xBCEF 0x0001 0x0000 0x0000 165: 0xF717 0xBCEF 0x0001 0x0000 0x0000 166: 0xF719 0xBCEF 0x0001 0x0000 0x0000 167: 0xF71B 0xBCEF 0x0001 0x0000 0x0000 168: 0xF71D 0xBCEF 0x0001 0x0000 0x0000 169: 0xF71E 0xBCEF 0x0001 0x0000 0x0000 170: 0xF71E 0xBCF0 0x0001 0x0000 0x0000 171: 0xF71E 0xBCF8 0x0001 0x0000 0x0000 172: 0xF71E 0xBCF4 0x0001 0x0000 0x0000 173: 0xF71E 0xBCFC 0x0001 0x0000 0x0000 174: 0xF71E 0xBCF2 0x0001 0x0000 0x0000 175: 0xF71E 0xBCFA 0x0001 0x0000 0x0000 176: 0xF71E 0xBCF6 0x0001 0x0000 0x0000 177: 0xF71E 0xBCFE 0x0001 0x0000 0x0000 178: 0xF71E 0xBCF1 0x0001 0x0000 0x0000 179: 0xF71E 0xBCF9 0x0001 0x0000 0x0000 180: 0xF71E 0xBCF5 0x0001 0x0000 0x0000 181: 0xF71E 0xBCFD 0x0001 0x0000 0x0000 182: 0xF71E 0xBCF3 0x0001 0x0000 0x0000 183: 0xF71E 0xBCFB 0x0001 0x0000 0x0000 184: 0xF71E 0xBCF7 0x0001 0x0000 0x0000 185: 0xF71E 0xBCEF 0x0001 0x0000 0x0000 186: 0xF71E 0xBC0F 0x0002 0x0000 0x0000 187: 0xF71E 0xBC0F 0x0003 0x0000 0x0000 188: 0xF71E 0xBC8F 0x0002 0x0000 0x0000 189: 0xF71E 0xBC8F 0x0003 0x0000 0x0000 190: 0xF71E 0xBC4F 0x0002 0x0000 0x0000 191: 0xF71E 0xBC4F 0x0003 0x0000 0x0000 192: 0xF71E 0xBCCF 0x0002 0x0000 0x0000 193: 0xF71E 0xBCCF 0x0003 0x0000 0x0000 194: 0xF71E 0xBC2F 0x0002 0x0000 0x0000 195: 0xF71E 0xBC2F 0x0003 0x0000 0x0000 196: 0xF71E 0xBCAF 0x0002 0x0000 0x0000 197: 0xF71E 0xBCAF 0x0003 0x0000 0x0000 198: 0xF71E 0xBC6F 0x0002 0x0000 0x0000 199: 0xF71E 0xBC6F 0x0003 0x0000 0x0000 200: 0xF71E 0xBCEF 0x0002 0x0000 0x0000 201: 0xF71E 0xBCEF 0x0001 0x0000 0x0000 202: 0xF71E 0xBCEF 0x0001 0x0000 0x0000 PINs used (in edge connector order) (G=ground,P=power) SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBB LETTER ABCDEFHJKLMNPRSTUVABCDEFHJKLMNPRSTUVABCDEFHJKLMNPRSTUVABCDEFHJKLMNPRSTUV SIDE 111111111111111111222222222222222222111111111111111111222222222222222222 USAGE IIIIOIIIIOIIIIOG P GIIIIOIIIIOIIIIO G P G UUT inputs: 24 UUT outputs: 6 pins used: 30 not used: 36 202 'test steps' 238 lines M617 REV E 6 4-INPUT NAND BUFFERS (48ma) (7440) PINS Main menu Mon Jul 10 12:36:37 2017 test file is: tests\m617.tst delay is: 0 trigger is: 1 1 read test file 2 set test delay 3 set test trigger 4 run test 5 output loading test 8 diags 9 exit UUT power is okay Mon Jul 10 12:36:38 2017 space single step O run once (one test, all steps) F run, stop on fail G go (run tests N run, stop on fail, no print S scope (run, no print) C turn on comment printout + increase speed (less delay) - decrease speed (more delay)(slower) Q quit test scope (run, no print) pppppppppppppp space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn on comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFHJKLMNPRSDEFHJKLMNPRSTUV SIDE 111111111111111222222222222222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO all fails was lo 000000000000000000000000000000 falling vvvvvvvvvvvvvvvvvvvvvvvvvvvvvv rising ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ was hi 111111111111111111111111111111 total fails 0, total passes 14 Main menu Mon Jul 10 12:36:40 2017 test file is: tests\m617.tst delay is: 0 trigger is: 1 1 read test file 2 set test delay 3 set test trigger 4 run test 5 output loading test 8 diags 9 exit Enter test file name? trying to open test file: tests\m310.tst reading test file: tests\m310.tst comment: M310 REV D DELAY LINE comment: comment: USE SINGLE STEP AND DMM. comment: USE OSCILLOSCOPE TO SEE PULSES. comment: comment: AE1 IS THE INPUT FOR THE AF1 OUTPUT. comment: AH1 IS THE INPUT FOR THE AJ1 OUTPUT. comment: CONNECT AE1 TO EACH TAP: comment: pins: PINS pins: 1 I AH2 PULSE INPUT (EDGE?) pins: 2 O AJ2 0 NS DELAY TAP pins: 3 O AK2 50 NS DELAY TAP pins: 4 O AL2 100 NS DELAY TAP pins: 5 O AM2 150 NS DELAY TAP pins: 6 O AN2 200 NS DELAY TAP pins: 7 O AP2 250 NS DELAY TAP pins: 8 O AR2 300 NS DELAY TAP pins: 9 O AS2 350 NS DELAY TAP pins: 10 O AT2 400 NS DELAY TAP pins: 11 O AU2 450 NS DELAY TAP pins: 12 O AV2 500 NS DELAY TAP pins: 13 I AE1 INPUT 1 (NORMALLY CONNECTED TO A DELAY TAP) pins: 14 O AF1 OUTPUT 1 7440 BUFFER 48MA DRIVE PULSES HI (100 NS) pins: 15 I AH1 INPUT 2 (NORMALLY CONNECTED TO A DELAY TAP) pins: 16 O AJ1 OUTPUT 2 7440 BUFFER 48MA DRIVE PULSES HI (100 NS) pins: direction: IOOOOOOOOOOOIOIO test 1: 0111111111110000 test 2: 100000000000 test 3: 011111111111001X test 4: 100000000000 test 5: 0111111111111X00 test 6: 100000000000 test 7: 0111111111110X0X test 8: 100000000000 end: END summary column 1: offset 0, mask 0x0002 column 2: offset 0, mask 0x0001 column 3: offset 1, mask 0x0001 column 4: offset 1, mask 0x0002 column 5: offset 1, mask 0x0004 column 6: offset 1, mask 0x0008 column 7: offset 1, mask 0x0010 column 8: offset 1, mask 0x0020 column 9: offset 1, mask 0x0040 column 10: offset 1, mask 0x0080 column 11: offset 2, mask 0x0001 column 12: offset 2, mask 0x0002 column 13: offset 0, mask 0x0800 column 14: offset 0, mask 0x0400 column 15: offset 0, mask 0x0200 column 16: offset 0, mask 0x0100 direction bits (1=input) 0xF5FD 0xFFFF 0xFFFB 0xFFFF 0xF0FF pullup bits (1=pullup) 0x0000 0x0000 0x0000 0x0000 0x0000 test step out_data dont care 1: 0x0001 0x00FF 0x0003 0x0000 0x0000 2: 0x0002 0x0000 0x0000 0x0000 0x0000 3: 0x0201 0x00FF 0x0003 0x0000 0x0000 0x0100 0x0000 0x0000 0x0000 0x0000 4: 0x0202 0x0000 0x0000 0x0000 0x0000 0x0100 0x0000 0x0000 0x0000 0x0000 5: 0x0801 0x00FF 0x0003 0x0000 0x0000 0x0400 0x0000 0x0000 0x0000 0x0000 6: 0x0802 0x0000 0x0000 0x0000 0x0000 0x0400 0x0000 0x0000 0x0000 0x0000 7: 0x0001 0x00FF 0x0003 0x0000 0x0000 0x0500 0x0000 0x0000 0x0000 0x0000 8: 0x0002 0x0000 0x0000 0x0000 0x0000 0x0500 0x0000 0x0000 0x0000 0x0000 PINs used (in edge connector order) (G=ground,P=power) SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBB LETTER ABCDEFHJKLMNPRSTUVABCDEFHJKLMNPRSTUVABCDEFHJKLMNPRSTUVABCDEFHJKLMNPRSTUV SIDE 111111111111111111222222222222222222111111111111111111222222222222222222 USAGE IOIO G P G IOOOOOOOOOOO G P G UUT inputs: 3 UUT outputs: 13 pins used: 16 not used: 50 8 'test steps' 37 lines M310 REV D DELAY LINE USE SINGLE STEP AND DMM. USE OSCILLOSCOPE TO SEE PULSES. AE1 IS THE INPUT FOR THE AF1 OUTPUT. AH1 IS THE INPUT FOR THE AJ1 OUTPUT. CONNECT AE1 TO EACH TAP: PINS Main menu Mon Jul 10 12:37:15 2017 test file is: tests\m310.tst delay is: 0 trigger is: 1 1 read test file 2 set test delay 3 set test trigger 4 run test 5 output loading test 8 diags 9 exit UUT power is okay Mon Jul 10 12:37:19 2017 space single step O run once (one test, all steps) F run, stop on fail G go (run tests N run, stop on fail, no print S scope (run, no print) C turn on comment printout + increase speed (less delay) - decrease speed (more delay)(slower) Q quit test scope (run, no print) ppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppp ppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppp ppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppp pppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppp space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn on comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit comment_flag is 1 space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn off comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAAAAAAAAAAAAAAA LETTER HJKLMNPRSTUVEFHJ SIDE 2222222222221111 DIRECTION IOOOOOOOOOOOIOIO source: 100000000000 changed: 100000000000 step 2 1000000000000000 okay space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn off comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAAAAAAAAAAAAAAA LETTER HJKLMNPRSTUVEFHJ SIDE 2222222222221111 DIRECTION IOOOOOOOOOOOIOIO source: 011111111111001X changed: 011111111111 1 step 3 0111111111110010 okay space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn off comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAAAAAAAAAAAAAAA LETTER HJKLMNPRSTUVEFHJ SIDE 2222222222221111 DIRECTION IOOOOOOOOOOOIOIO source: 100000000000 changed: 100000000000 step 4 1000000000000010 okay space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn off comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAAAAAAAAAAAAAAA LETTER HJKLMNPRSTUVEFHJ SIDE 2222222222221111 DIRECTION IOOOOOOOOOOOIOIO source: 0111111111111X00 changed: 0111111111111 0 step 5 0111111111111000 okay space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn off comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAAAAAAAAAAAAAAA LETTER HJKLMNPRSTUVEFHJ SIDE 2222222222221111 DIRECTION IOOOOOOOOOOOIOIO source: 100000000000 changed: 100000000000 step 6 1000000000001000 okay space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn off comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAAAAAAAAAAAAAAA LETTER HJKLMNPRSTUVEFHJ SIDE 2222222222221111 DIRECTION IOOOOOOOOOOOIOIO source: 0111111111110X0X changed: 0111111111110 step 7 0111111111110000 okay space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn off comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAAAAAAAAAAAAAAA LETTER HJKLMNPRSTUVEFHJ SIDE 2222222222221111 DIRECTION IOOOOOOOOOOOIOIO source: 100000000000 changed: 100000000000 step 8 1000000000000000 okay test 302: pass SLOT AAAAAAAAAAAAAAAA LETTER HJKLMNPRSTUVEFHJ SIDE 2222222222221111 DIRECTION IOOOOOOOOOOOIOIO this fail all fails was hi 1111111111111 1 rising ^^^^^^^^^^^^^ ^ falling vvvvvvvvvvvvv v was lo 0000000000000000 total fails 0, total passes 302 space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn off comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAAAAAAAAAAAAAAA LETTER HJKLMNPRSTUVEFHJ SIDE 2222222222221111 DIRECTION IOOOOOOOOOOOIOIO source: 0111111111110000 changed: 011111111111 step 1 0111111111110000 okay space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn off comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAAAAAAAAAAAAAAA LETTER HJKLMNPRSTUVEFHJ SIDE 2222222222221111 DIRECTION IOOOOOOOOOOOIOIO source: 100000000000 changed: 100000000000 step 2 1000000000000000 okay space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn off comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAAAAAAAAAAAAAAA LETTER HJKLMNPRSTUVEFHJ SIDE 2222222222221111 DIRECTION IOOOOOOOOOOOIOIO source: 011111111111001X changed: 011111111111 1 step 3 0111111111110010 okay space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn off comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAAAAAAAAAAAAAAA LETTER HJKLMNPRSTUVEFHJ SIDE 2222222222221111 DIRECTION IOOOOOOOOOOOIOIO source: 100000000000 changed: 100000000000 step 4 1000000000000010 okay space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn off comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAAAAAAAAAAAAAAA LETTER HJKLMNPRSTUVEFHJ SIDE 2222222222221111 DIRECTION IOOOOOOOOOOOIOIO source: 0111111111111X00 changed: 0111111111111 0 step 5 0111111111111000 okay space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn off comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit source: 100000000000 changed: 100000000000 step 6 1000000000001000 source: 0111111111110X0X changed: 0111111111110 step 7 0111111111110000 source: 100000000000 changed: 100000000000 step 8 1000000000000000 test 303: pass SLOT AAAAAAAAAAAAAAAA LETTER HJKLMNPRSTUVEFHJ SIDE 2222222222221111 DIRECTION IOOOOOOOOOOOIOIO this fail all fails was hi 1111111111111 1 rising ^^^^^^^^^^^^^ ^ falling vvvvvvvvvvvvv v was lo 0000000000000000 total fails 0, total passes 303 space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn off comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit source: 0111111111110000 changed: 011111111111 step 1 0111111111110000 source: 100000000000 changed: 100000000000 step 2 1000000000000000 source: 011111111111001X changed: 011111111111 1 step 3 0111111111110010 source: 100000000000 changed: 100000000000 step 4 1000000000000010 source: 0111111111111X00 changed: 0111111111111 0 step 5 0111111111111000 source: 100000000000 changed: 100000000000 step 6 1000000000001000 source: 0111111111110X0X changed: 0111111111110 step 7 0111111111110000 source: 100000000000 changed: 100000000000 step 8 1000000000000000 test 304: pass SLOT AAAAAAAAAAAAAAAA LETTER HJKLMNPRSTUVEFHJ SIDE 2222222222221111 DIRECTION IOOOOOOOOOOOIOIO this fail all fails was hi 1111111111111 1 rising ^^^^^^^^^^^^^ ^ falling vvvvvvvvvvvvv v was lo 0000000000000000 total fails 0, total passes 304 space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn off comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit source: 0111111111110000 changed: 011111111111 step 1 0111111111110000 source: 100000000000 changed: 100000000000 step 2 1000000000000000 source: 011111111111001X changed: 011111111111 1 step 3 0111111111110010 source: 100000000000 changed: 100000000000 step 4 1000000000000010 source: 0111111111111X00 changed: 0111111111111 0 step 5 0111111111111000 source: 100000000000 changed: 100000000000 step 6 1000000000001000 source: 0111111111110X0X changed: 0111111111110 step 7 0111111111110000 source: 100000000000 changed: 100000000000 step 8 1000000000000000 test 305: pass SLOT AAAAAAAAAAAAAAAA LETTER HJKLMNPRSTUVEFHJ SIDE 2222222222221111 DIRECTION IOOOOOOOOOOOIOIO this fail all fails was hi 1111111111111 1 rising ^^^^^^^^^^^^^ ^ falling vvvvvvvvvvvvv v was lo 0000000000000000 total fails 0, total passes 305 space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn off comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAAAAAAAAAAAAAAA LETTER HJKLMNPRSTUVEFHJ SIDE 2222222222221111 DIRECTION IOOOOOOOOOOOIOIO all fails was lo 0000000000000000 falling vvvvvvvvvvvvv v rising ^^^^^^^^^^^^^ ^ was hi 1111111111111 1 total fails 0, total passes 305 Main menu Mon Jul 10 12:37:49 2017 test file is: tests\m310.tst delay is: 0 trigger is: 1 1 read test file 2 set test delay 3 set test trigger 4 run test 5 output loading test 8 diags 9 exit Enter test file name? trying to open test file: tests\m310.tst reading test file: tests\m310.tst comment: M310 REV D DELAY LINE comment: comment: USE SINGLE STEP AND DMM. comment: USE OSCILLOSCOPE TO SEE PULSES. comment: comment: AE1 IS THE INPUT FOR THE AF1 OUTPUT. comment: AH1 IS THE INPUT FOR THE AJ1 OUTPUT. comment: CONNECT AE1 TO EACH TAP: comment: pins: PINS pins: 1 I AH2 PULSE INPUT (EDGE?) pins: 2 O AJ2 0 NS DELAY TAP pins: 3 O AK2 50 NS DELAY TAP pins: 4 O AL2 100 NS DELAY TAP pins: 5 O AM2 150 NS DELAY TAP pins: 6 O AN2 200 NS DELAY TAP pins: 7 O AP2 250 NS DELAY TAP pins: 8 O AR2 300 NS DELAY TAP pins: 9 O AS2 350 NS DELAY TAP pins: 10 O AT2 400 NS DELAY TAP pins: 11 O AU2 450 NS DELAY TAP pins: 12 O AV2 500 NS DELAY TAP pins: 13 I AE1 INPUT 1 (NORMALLY CONNECTED TO A DELAY TAP) pins: 14 O AF1 OUTPUT 1 7440 BUFFER 48MA DRIVE PULSES HI (100 NS) pins: 15 I AH1 INPUT 2 (NORMALLY CONNECTED TO A DELAY TAP) pins: 16 O AJ1 OUTPUT 2 7440 BUFFER 48MA DRIVE PULSES HI (100 NS) pins: direction: IOOOOOOOOOOOIOIO test 1: 0111111111110000 test 2: 100000000000 test 3: 011111111111001X test 4: 100000000000 test 5: 0111111111111X00 test 6: 100000000000 test 7: 0111111111110X0X test 8: 100000000000 end: END summary column 1: offset 0, mask 0x0002 column 2: offset 0, mask 0x0001 column 3: offset 1, mask 0x0001 column 4: offset 1, mask 0x0002 column 5: offset 1, mask 0x0004 column 6: offset 1, mask 0x0008 column 7: offset 1, mask 0x0010 column 8: offset 1, mask 0x0020 column 9: offset 1, mask 0x0040 column 10: offset 1, mask 0x0080 column 11: offset 2, mask 0x0001 column 12: offset 2, mask 0x0002 column 13: offset 0, mask 0x0800 column 14: offset 0, mask 0x0400 column 15: offset 0, mask 0x0200 column 16: offset 0, mask 0x0100 direction bits (1=input) 0xF5FD 0xFFFF 0xFFFB 0xFFFF 0xF0FF pullup bits (1=pullup) 0x0000 0x0000 0x0000 0x0000 0x0000 test step out_data dont care 1: 0x0001 0x00FF 0x0003 0x0000 0x0000 2: 0x0002 0x0000 0x0000 0x0000 0x0000 3: 0x0201 0x00FF 0x0003 0x0000 0x0000 0x0100 0x0000 0x0000 0x0000 0x0000 4: 0x0202 0x0000 0x0000 0x0000 0x0000 0x0100 0x0000 0x0000 0x0000 0x0000 5: 0x0801 0x00FF 0x0003 0x0000 0x0000 0x0400 0x0000 0x0000 0x0000 0x0000 6: 0x0802 0x0000 0x0000 0x0000 0x0000 0x0400 0x0000 0x0000 0x0000 0x0000 7: 0x0001 0x00FF 0x0003 0x0000 0x0000 0x0500 0x0000 0x0000 0x0000 0x0000 8: 0x0002 0x0000 0x0000 0x0000 0x0000 0x0500 0x0000 0x0000 0x0000 0x0000 PINs used (in edge connector order) (G=ground,P=power) SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBB LETTER ABCDEFHJKLMNPRSTUVABCDEFHJKLMNPRSTUVABCDEFHJKLMNPRSTUVABCDEFHJKLMNPRSTUV SIDE 111111111111111111222222222222222222111111111111111111222222222222222222 USAGE IOIO G P G IOOOOOOOOOOO G P G UUT inputs: 3 UUT outputs: 13 pins used: 16 not used: 50 8 'test steps' 37 lines M310 REV D DELAY LINE USE SINGLE STEP AND DMM. USE OSCILLOSCOPE TO SEE PULSES. AE1 IS THE INPUT FOR THE AF1 OUTPUT. AH1 IS THE INPUT FOR THE AJ1 OUTPUT. CONNECT AE1 TO EACH TAP: PINS Main menu Mon Jul 10 12:37:52 2017 test file is: tests\m310.tst delay is: 0 trigger is: 1 1 read test file 2 set test delay 3 set test trigger 4 run test 5 output loading test 8 diags 9 exit key is 0x0020 Main menu Mon Jul 10 12:38:41 2017 test file is: tests\m310.tst delay is: 0 trigger is: 1 1 read test file 2 set test delay 3 set test trigger 4 run test 5 output loading test 8 diags 9 exit UUT power is okay Mon Jul 10 12:38:43 2017 space single step O run once (one test, all steps) F run, stop on fail G go (run tests N run, stop on fail, no print S scope (run, no print) C turn on comment printout + increase speed (less delay) - decrease speed (more delay)(slower) Q quit test scope (run, no print) ppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppp ppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppp ppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppp ppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppp ppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppp ppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppp ppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppp ppppppppppppppppppppppppppppppppppppppppppppppppppppp space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn on comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit step 7 0111111111110000 step 8 1000000000000000 test 607: pass SLOT AAAAAAAAAAAAAAAA LETTER HJKLMNPRSTUVEFHJ SIDE 2222222222221111 DIRECTION IOOOOOOOOOOOIOIO this fail all fails was hi 1111111111111 1 rising ^^^^^^^^^^^^^ ^ falling vvvvvvvvvvvvv v was lo 0000000000000000 total fails 0, total passes 607 space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn on comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit step 1 0111111111110000 step 2 1000000000000000 step 3 0111111111110010 step 4 1000000000000010 step 5 0111111111111000 step 6 1000000000001000 step 7 0111111111110000 step 8 1000000000000000 test 608: pass SLOT AAAAAAAAAAAAAAAA LETTER HJKLMNPRSTUVEFHJ SIDE 2222222222221111 DIRECTION IOOOOOOOOOOOIOIO this fail all fails was hi 1111111111111 1 rising ^^^^^^^^^^^^^ ^ falling vvvvvvvvvvvvv v was lo 0000000000000000 total fails 0, total passes 608 space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn on comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAAAAAAAAAAAAAAA LETTER HJKLMNPRSTUVEFHJ SIDE 2222222222221111 DIRECTION IOOOOOOOOOOOIOIO all fails was lo 0000000000000000 falling vvvvvvvvvvvvv v rising ^^^^^^^^^^^^^ ^ was hi 1111111111111 1 total fails 0, total passes 608 Main menu Mon Jul 10 12:38:51 2017 test file is: tests\m310.tst delay is: 0 trigger is: 1 1 read test file 2 set test delay 3 set test trigger 4 run test 5 output loading test 8 diags 9 exit UUT power is okay Mon Jul 10 12:39:07 2017 space single step O run once (one test, all steps) F run, stop on fail G go (run tests N run, stop on fail, no print S scope (run, no print) C turn on comment printout + increase speed (less delay) - decrease speed (more delay)(slower) Q quit test scope (run, no print) ppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppp ppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppp ppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppp ppppppp space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn on comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAAAAAAAAAAAAAAA LETTER HJKLMNPRSTUVEFHJ SIDE 2222222222221111 DIRECTION IOOOOOOOOOOOIOIO all fails was lo 0000000000000000 falling vvvvvvvvvvvvv v rising ^^^^^^^^^^^^^ ^ was hi 1111111111111 1 total fails 0, total passes 244 Main menu Mon Jul 10 12:39:09 2017 test file is: tests\m310.tst delay is: 0 trigger is: 1 1 read test file 2 set test delay 3 set test trigger 4 run test 5 output loading test 8 diags 9 exit Enter test file name? trying to open test file: tests\m360.tst reading test file: tests\m360.tst comment: M360 SCHEMATIC REV B, PCB REV B VARIABLE DELAY LINE comment: comment: USE SINGLE STEP AND DMM. comment: USE OSCILLOSCOPE TO SEE PULSES. comment: TRIGGER ON STEP 5, OBSERVE AS2 POSITIVE PULSE, AT2 NEGATIVE PULSE comment: TRIGGER ON STEP 10, OBSERVE AS2 POSITIVE PULSE, AT2 NEGATIVE PULSE comment: MANUALLY CHANGE DELAY ADJUSTMENT, OBSERVE WITH OSCILLOSCOPE. comment: pins: PINS pins: 1 I AP2 INPUT 1 pins: 2 I AR2 INPUT 2 pins: 3 O AS2 POSITIVE 100 NS PULSE OUTPUT WHEN (INPUT 1 AND INPUT 2) RISING EDGE pins: 4 P AT2 NEGATIVE OF AS2, NEGATIVE 5 US PULSE OUTPUT (FAST DOWN, RC UP) (OPEN DRAIN) pins: 5 I AU2 INVERTER INPUT pins: 6 P AV2 INVERTER OUTPUT (OPEN DRAIN) pins: direction: IIOPIP comment: ; INITAL OFF test 1: 000101 comment: ; NO PULSES test 2: 01 test 3: 00 test 4: 10 comment: ; PULSE (SO FAST, IT WLL BE OVER BEFORE TESTED) test 5: 1101 comment: ;AGAIN WITH INVERTER ON comment: ; INITAL OFF test 6: 000110 comment: ; NO PULSES test 7: 01 test 8: 00 test 9: 10 comment: ; PULSE (SO FAST, IT WLL BE OVER BEFORE TESTED) test 10: 1101 comment: ; BACK TO INITAL CONDITIONS test 11: 000101 end: END summary column 1: offset 1, mask 0x0010 column 2: offset 1, mask 0x0020 column 3: offset 1, mask 0x0040 column 4: offset 1, mask 0x0080 column 5: offset 2, mask 0x0001 column 6: offset 2, mask 0x0002 direction bits (1=input) 0xFFFF 0xFFCF 0xFFFA 0xFFFF 0xF0FF pullup bits (1=pullup) 0x0000 0x0080 0x0002 0x0000 0x0000 test step out_data dont care 1: 0x0000 0x0080 0x0002 0x0000 0x0000 2: 0x0000 0x00A0 0x0002 0x0000 0x0000 3: 0x0000 0x0080 0x0002 0x0000 0x0000 4: 0x0000 0x0090 0x0002 0x0000 0x0000 5: 0x0000 0x00B0 0x0002 0x0000 0x0000 6: 0x0000 0x0080 0x0001 0x0000 0x0000 7: 0x0000 0x00A0 0x0001 0x0000 0x0000 8: 0x0000 0x0080 0x0001 0x0000 0x0000 9: 0x0000 0x0090 0x0001 0x0000 0x0000 10: 0x0000 0x00B0 0x0001 0x0000 0x0000 11: 0x0000 0x0080 0x0002 0x0000 0x0000 PINs used (in edge connector order) (G=ground,P=power) SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBB LETTER ABCDEFHJKLMNPRSTUVABCDEFHJKLMNPRSTUVABCDEFHJKLMNPRSTUVABCDEFHJKLMNPRSTUV SIDE 111111111111111111222222222222222222111111111111111111222222222222222222 USAGE G P G IIOPIP G P G UUT inputs: 3 UUT outputs: 3 pins used: 6 not used: 60 11 'test steps' 37 lines M360 SCHEMATIC REV B, PCB REV B VARIABLE DELAY LINE USE SINGLE STEP AND DMM. USE OSCILLOSCOPE TO SEE PULSES. TRIGGER ON STEP 5, OBSERVE AS2 POSITIVE PULSE, AT2 NEGATIVE PULSE TRIGGER ON STEP 10, OBSERVE AS2 POSITIVE PULSE, AT2 NEGATIVE PULSE MANUALLY CHANGE DELAY ADJUSTMENT, OBSERVE WITH OSCILLOSCOPE. PINS Main menu Mon Jul 10 12:39:33 2017 test file is: tests\m360.tst delay is: 0 trigger is: 1 1 read test file 2 set test delay 3 set test trigger 4 run test 5 output loading test 8 diags 9 exit UUT power is okay Mon Jul 10 12:39:35 2017 space single step O run once (one test, all steps) F run, stop on fail G go (run tests N run, stop on fail, no print S scope (run, no print) C turn on comment printout + increase speed (less delay) - decrease speed (more delay)(slower) Q quit test scope (run, no print) ppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppp ppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppp ppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppp space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn on comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit step 11 000101 test 236: pass SLOT AAAAAA LETTER PRSTUV SIDE 222222 DIRECTION IIOPIP this fail all fails was hi 11 111 rising ^^ ^^ falling vv vv was lo 000 00 total fails 0, total passes 236 space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn on comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit comment_flag is 1 space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn off comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAAAAA LETTER PRSTUV SIDE 222222 DIRECTION IIOPIP source: ; INITAL OFF source: 000101 changed: step 1 000101 okay space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn off comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAAAAA LETTER PRSTUV SIDE 222222 DIRECTION IIOPIP source: ; NO PULSES source: 01 changed: 1 step 2 010101 okay space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn off comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAAAAA LETTER PRSTUV SIDE 222222 DIRECTION IIOPIP source: 00 changed: 0 step 3 000101 okay space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn off comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAAAAA LETTER PRSTUV SIDE 222222 DIRECTION IIOPIP source: 10 changed: 1 step 4 100101 okay space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn off comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAAAAA LETTER PRSTUV SIDE 222222 DIRECTION IIOPIP source: ; PULSE (SO FAST, IT WLL BE OVER BEFORE TESTED) source: 1101 changed: 1 step 5 110101 okay space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn off comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAAAAA LETTER PRSTUV SIDE 222222 DIRECTION IIOPIP source: ;AGAIN WITH INVERTER ON source: ; INITAL OFF source: 000110 changed: 00 10 step 6 000110 okay space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn off comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAAAAA LETTER PRSTUV SIDE 222222 DIRECTION IIOPIP source: ; NO PULSES source: 01 changed: 1 step 7 010110 okay space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn off comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAAAAA LETTER PRSTUV SIDE 222222 DIRECTION IIOPIP source: 00 changed: 0 step 8 000110 okay space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn off comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAAAAA LETTER PRSTUV SIDE 222222 DIRECTION IIOPIP source: 10 changed: 1 step 9 100110 okay space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn off comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAAAAA LETTER PRSTUV SIDE 222222 DIRECTION IIOPIP source: ; PULSE (SO FAST, IT WLL BE OVER BEFORE TESTED) source: 1101 changed: 1 step 10 110110 okay space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn off comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit source: ; BACK TO INITAL CONDITIONS source: 000101 changed: 00 01 step 11 000101 test 237: pass SLOT AAAAAA LETTER PRSTUV SIDE 222222 DIRECTION IIOPIP this fail all fails was hi 11 111 rising ^^ ^^ falling vv vv was lo 000 00 total fails 0, total passes 237 space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn off comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit source: ; INITAL OFF source: 000101 changed: step 1 000101 source: ; NO PULSES source: 01 changed: 1 step 2 010101 source: 00 changed: 0 step 3 000101 source: 10 changed: 1 step 4 100101 source: ; PULSE (SO FAST, IT WLL BE OVER BEFORE TESTED) source: 1101 changed: 1 step 5 110101 source: ;AGAIN WITH INVERTER ON source: ; INITAL OFF source: 000110 changed: 00 10 step 6 000110 source: ; NO PULSES source: 01 changed: 1 step 7 010110 source: 00 changed: 0 step 8 000110 source: 10 changed: 1 step 9 100110 source: ; PULSE (SO FAST, IT WLL BE OVER BEFORE TESTED) source: 1101 changed: 1 step 10 110110 source: ; BACK TO INITAL CONDITIONS source: 000101 changed: 00 01 step 11 000101 test 238: pass SLOT AAAAAA LETTER PRSTUV SIDE 222222 DIRECTION IIOPIP this fail all fails was hi 11 111 rising ^^ ^^ falling vv vv was lo 000 00 total fails 0, total passes 238 space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn off comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAAAAA LETTER PRSTUV SIDE 222222 DIRECTION IIOPIP all fails was lo 000 00 falling vv vv rising ^^ ^^ was hi 11 111 total fails 0, total passes 238 Main menu Mon Jul 10 12:39:54 2017 test file is: tests\m360.tst delay is: 0 trigger is: 1 1 read test file 2 set test delay 3 set test trigger 4 run test 5 output loading test 8 diags 9 exit exiting tester- PDP8 card tester via printer port version 0.91 November 27, 2015 mapping[] is verified Main menu Mon Jul 10 15:08:03 2017 test file is: delay is: 0 trigger is: 1 1 read test file 2 set test delay 3 set test trigger 4 run test 5 output loading test 8 diags 9 exit Enter test file name? trying to open test file: tests\m516.tst reading test file: tests\m516.tst comment: M516 POSITIVE BUS RECEIVER (6 4-input NAND) (3 7420) PCB REV A SCHEMATIC REV (blank) comment: pins: PINS pins: 1 I AA1 E1-2 INPUT 1A pins: 2 I AB1 E1-1 INPUT 1B pins: 3 I AC1 E1-4 INPUT 1C pins: 4 I AD1 E1-5 INPUT 1D pins: 5 O AE1 E1-6 OUTPUT 1 = (1A NAND 1B NAND 1C NAND 1D) pins: 6 I AD2 E1-13 INPUT 2A pins: 7 I AE2 E1-12 INPUT 2B pins: 8 I AF2 E1-10 INPUT 2C pins: 9 I AH2 E1-9 INPUT 2D pins: 10 O AJ2 E1-8 OUTPUT 2 = (2A NAND 2B NAND 2C NAND 2D) pins: 11 I AF1 E2-2 INPUT 3A pins: 12 I AH1 E2-1 INPUT 3B pins: 13 I AJ1 E2-4 INPUT 3C pins: 14 I AK1 E2-5 INPUT 3D pins: 15 O AL1 E2-6 OUTPUT 3 = (3A NAND 3B NAND 3C NAND 3D) pins: 16 I AK2 E2-13 INPUT 4A pins: 17 I AL2 E2-12 INPUT 4B pins: 18 I AM2 E2-10 INPUT 4C pins: 19 I AN2 E2-9 INPUT 4D pins: 20 O AP2 E2-8 OUTPUT 4 = (4A NAND 4B NAND 4C NAND 4D) pins: 21 I AM1 E3-1 INPUT 5A pins: 22 I AN1 E3-2 INPUT 5B pins: 23 I AP1 E3-4 INPUT 5C pins: 24 I AR1 E3-5 INPUT 5D pins: 25 O AS1 E3-6 OUTPUT 5 = (5A NAND 5B NAND 5C NAND 5D) pins: 26 I AR2 E3-13 INPUT 6A pins: 27 I AS2 E3-12 INPUT 6B pins: 28 I AT2 E3-10 INPUT 6C pins: 29 I AU2 E3-9 INPUT 6D pins: 30 O AV2 E3-8 OUTPUT 6 = (6A NAND 6B NAND 6C NAND 6D) pins: direction: IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO test 1: 000010000100001000010000100001 test 2: 00001 test 3: 00011 test 4: 00101 test 5: 00111 test 6: 01001 test 7: 01011 test 8: 01101 test 9: 01111 test 10: 10001 test 11: 10011 test 12: 10101 test 13: 10111 test 14: 11001 test 15: 11011 test 16: 11101 test 17: 11110 test 18: 00001 test 19: 00001 test 20: 00011 test 21: 00101 test 22: 00111 test 23: 01001 test 24: 01011 test 25: 01101 test 26: 01111 test 27: 10001 test 28: 10011 test 29: 10101 test 30: 10111 test 31: 11001 test 32: 11011 test 33: 11101 test 34: 11110 test 35: 00001 test 36: 00001 test 37: 00011 test 38: 00101 test 39: 00111 test 40: 01001 test 41: 01011 test 42: 01101 test 43: 01111 test 44: 10001 test 45: 10011 test 46: 10101 test 47: 10111 test 48: 11001 test 49: 11011 test 50: 11101 test 51: 11110 test 52: 00001 test 53: 00001 test 54: 00011 test 55: 00101 test 56: 00111 test 57: 01001 test 58: 01011 test 59: 01101 test 60: 01111 test 61: 10001 test 62: 10011 test 63: 10101 test 64: 10111 test 65: 11001 test 66: 11011 test 67: 11101 test 68: 11110 test 69: 00001 test 70: 00001 test 71: 00011 test 72: 00101 test 73: 00111 test 74: 01001 test 75: 01011 test 76: 01101 test 77: 01111 test 78: 10001 test 79: 10011 test 80: 10101 test 81: 10111 test 82: 11001 test 83: 11011 test 84: 11101 test 85: 11110 test 86: 00001 test 87: 00001 test 88: 00011 test 89: 00101 test 90: 00111 test 91: 01001 test 92: 01011 test 93: 01101 test 94: 01111 test 95: 10001 test 96: 10011 test 97: 10101 test 98: 10111 test 99: 11001 test 100: 11011 test 101: 11101 test 102: 11110 test 103: 00001 test 104: 000010000100001000010000100001 test 105: 111101111011110111101111011110 test 106: 00001 test 107: 00011 test 108: 00101 test 109: 00111 test 110: 01001 test 111: 01011 test 112: 01101 test 113: 01111 test 114: 10001 test 115: 10011 test 116: 10101 test 117: 10111 test 118: 11001 test 119: 11011 test 120: 11101 test 121: 11110 test 122: 00001 test 123: 00011 test 124: 00101 test 125: 00111 test 126: 01001 test 127: 01011 test 128: 01101 test 129: 01111 test 130: 10001 test 131: 10011 test 132: 10101 test 133: 10111 test 134: 11001 test 135: 11011 test 136: 11101 test 137: 11110 test 138: 00001 test 139: 00011 test 140: 00101 test 141: 00111 test 142: 01001 test 143: 01011 test 144: 01101 test 145: 01111 test 146: 10001 test 147: 10011 test 148: 10101 test 149: 10111 test 150: 11001 test 151: 11011 test 152: 11101 test 153: 11110 test 154: 00001 test 155: 00011 test 156: 00101 test 157: 00111 test 158: 01001 test 159: 01011 test 160: 01101 test 161: 01111 test 162: 10001 test 163: 10011 test 164: 10101 test 165: 10111 test 166: 11001 test 167: 11011 test 168: 11101 test 169: 11110 test 170: 00001 test 171: 00011 test 172: 00101 test 173: 00111 test 174: 01001 test 175: 01011 test 176: 01101 test 177: 01111 test 178: 10001 test 179: 10011 test 180: 10101 test 181: 10111 test 182: 11001 test 183: 11011 test 184: 11101 test 185: 11110 test 186: 00001 test 187: 00011 test 188: 00101 test 189: 00111 test 190: 01001 test 191: 01011 test 192: 01101 test 193: 01111 test 194: 10001 test 195: 10011 test 196: 10101 test 197: 10111 test 198: 11001 test 199: 11011 test 200: 11101 test 201: 11110 test 202: 111101111011110111101111011110 end: END summary column 1: offset 0, mask 0x8000 column 2: offset 0, mask 0x4000 column 3: offset 0, mask 0x2000 column 4: offset 0, mask 0x1000 column 5: offset 0, mask 0x0800 column 6: offset 0, mask 0x0010 column 7: offset 0, mask 0x0008 column 8: offset 0, mask 0x0004 column 9: offset 0, mask 0x0002 column 10: offset 0, mask 0x0001 column 11: offset 0, mask 0x0400 column 12: offset 0, mask 0x0200 column 13: offset 0, mask 0x0100 column 14: offset 1, mask 0x8000 column 15: offset 1, mask 0x4000 column 16: offset 1, mask 0x0001 column 17: offset 1, mask 0x0002 column 18: offset 1, mask 0x0004 column 19: offset 1, mask 0x0008 column 20: offset 1, mask 0x0010 column 21: offset 1, mask 0x2000 column 22: offset 1, mask 0x1000 column 23: offset 1, mask 0x0800 column 24: offset 1, mask 0x0400 column 25: offset 1, mask 0x0200 column 26: offset 1, mask 0x0020 column 27: offset 1, mask 0x0040 column 28: offset 1, mask 0x0080 column 29: offset 2, mask 0x0001 column 30: offset 2, mask 0x0002 direction bits (1=input) 0x08E1 0x4310 0xFFFA 0xFFFF 0xF0FF pullup bits (1=pullup) 0x0000 0x0000 0x0000 0x0000 0x0000 test step out_data dont care 1: 0x0801 0x4210 0x0002 0x0000 0x0000 2: 0x0801 0x4210 0x0002 0x0000 0x0000 3: 0x1801 0x4210 0x0002 0x0000 0x0000 4: 0x2801 0x4210 0x0002 0x0000 0x0000 5: 0x3801 0x4210 0x0002 0x0000 0x0000 6: 0x4801 0x4210 0x0002 0x0000 0x0000 7: 0x5801 0x4210 0x0002 0x0000 0x0000 8: 0x6801 0x4210 0x0002 0x0000 0x0000 9: 0x7801 0x4210 0x0002 0x0000 0x0000 10: 0x8801 0x4210 0x0002 0x0000 0x0000 11: 0x9801 0x4210 0x0002 0x0000 0x0000 12: 0xA801 0x4210 0x0002 0x0000 0x0000 13: 0xB801 0x4210 0x0002 0x0000 0x0000 14: 0xC801 0x4210 0x0002 0x0000 0x0000 15: 0xD801 0x4210 0x0002 0x0000 0x0000 16: 0xE801 0x4210 0x0002 0x0000 0x0000 17: 0xF001 0x4210 0x0002 0x0000 0x0000 18: 0x0801 0x4210 0x0002 0x0000 0x0000 19: 0x0801 0x4210 0x0002 0x0000 0x0000 20: 0x0803 0x4210 0x0002 0x0000 0x0000 21: 0x0805 0x4210 0x0002 0x0000 0x0000 22: 0x0807 0x4210 0x0002 0x0000 0x0000 23: 0x0809 0x4210 0x0002 0x0000 0x0000 24: 0x080B 0x4210 0x0002 0x0000 0x0000 25: 0x080D 0x4210 0x0002 0x0000 0x0000 26: 0x080F 0x4210 0x0002 0x0000 0x0000 27: 0x0811 0x4210 0x0002 0x0000 0x0000 28: 0x0813 0x4210 0x0002 0x0000 0x0000 29: 0x0815 0x4210 0x0002 0x0000 0x0000 30: 0x0817 0x4210 0x0002 0x0000 0x0000 31: 0x0819 0x4210 0x0002 0x0000 0x0000 32: 0x081B 0x4210 0x0002 0x0000 0x0000 33: 0x081D 0x4210 0x0002 0x0000 0x0000 34: 0x081E 0x4210 0x0002 0x0000 0x0000 35: 0x0801 0x4210 0x0002 0x0000 0x0000 36: 0x0801 0x4210 0x0002 0x0000 0x0000 37: 0x0801 0xC210 0x0002 0x0000 0x0000 38: 0x0901 0x4210 0x0002 0x0000 0x0000 39: 0x0901 0xC210 0x0002 0x0000 0x0000 40: 0x0A01 0x4210 0x0002 0x0000 0x0000 41: 0x0A01 0xC210 0x0002 0x0000 0x0000 42: 0x0B01 0x4210 0x0002 0x0000 0x0000 43: 0x0B01 0xC210 0x0002 0x0000 0x0000 44: 0x0C01 0x4210 0x0002 0x0000 0x0000 45: 0x0C01 0xC210 0x0002 0x0000 0x0000 46: 0x0D01 0x4210 0x0002 0x0000 0x0000 47: 0x0D01 0xC210 0x0002 0x0000 0x0000 48: 0x0E01 0x4210 0x0002 0x0000 0x0000 49: 0x0E01 0xC210 0x0002 0x0000 0x0000 50: 0x0F01 0x4210 0x0002 0x0000 0x0000 51: 0x0F01 0x8210 0x0002 0x0000 0x0000 52: 0x0801 0x4210 0x0002 0x0000 0x0000 53: 0x0801 0x4210 0x0002 0x0000 0x0000 54: 0x0801 0x4218 0x0002 0x0000 0x0000 55: 0x0801 0x4214 0x0002 0x0000 0x0000 56: 0x0801 0x421C 0x0002 0x0000 0x0000 57: 0x0801 0x4212 0x0002 0x0000 0x0000 58: 0x0801 0x421A 0x0002 0x0000 0x0000 59: 0x0801 0x4216 0x0002 0x0000 0x0000 60: 0x0801 0x421E 0x0002 0x0000 0x0000 61: 0x0801 0x4211 0x0002 0x0000 0x0000 62: 0x0801 0x4219 0x0002 0x0000 0x0000 63: 0x0801 0x4215 0x0002 0x0000 0x0000 64: 0x0801 0x421D 0x0002 0x0000 0x0000 65: 0x0801 0x4213 0x0002 0x0000 0x0000 66: 0x0801 0x421B 0x0002 0x0000 0x0000 67: 0x0801 0x4217 0x0002 0x0000 0x0000 68: 0x0801 0x420F 0x0002 0x0000 0x0000 69: 0x0801 0x4210 0x0002 0x0000 0x0000 70: 0x0801 0x4210 0x0002 0x0000 0x0000 71: 0x0801 0x4610 0x0002 0x0000 0x0000 72: 0x0801 0x4A10 0x0002 0x0000 0x0000 73: 0x0801 0x4E10 0x0002 0x0000 0x0000 74: 0x0801 0x5210 0x0002 0x0000 0x0000 75: 0x0801 0x5610 0x0002 0x0000 0x0000 76: 0x0801 0x5A10 0x0002 0x0000 0x0000 77: 0x0801 0x5E10 0x0002 0x0000 0x0000 78: 0x0801 0x6210 0x0002 0x0000 0x0000 79: 0x0801 0x6610 0x0002 0x0000 0x0000 80: 0x0801 0x6A10 0x0002 0x0000 0x0000 81: 0x0801 0x6E10 0x0002 0x0000 0x0000 82: 0x0801 0x7210 0x0002 0x0000 0x0000 83: 0x0801 0x7610 0x0002 0x0000 0x0000 84: 0x0801 0x7A10 0x0002 0x0000 0x0000 85: 0x0801 0x7C10 0x0002 0x0000 0x0000 86: 0x0801 0x4210 0x0002 0x0000 0x0000 87: 0x0801 0x4210 0x0002 0x0000 0x0000 88: 0x0801 0x4210 0x0003 0x0000 0x0000 89: 0x0801 0x4290 0x0002 0x0000 0x0000 90: 0x0801 0x4290 0x0003 0x0000 0x0000 91: 0x0801 0x4250 0x0002 0x0000 0x0000 92: 0x0801 0x4250 0x0003 0x0000 0x0000 93: 0x0801 0x42D0 0x0002 0x0000 0x0000 94: 0x0801 0x42D0 0x0003 0x0000 0x0000 95: 0x0801 0x4230 0x0002 0x0000 0x0000 96: 0x0801 0x4230 0x0003 0x0000 0x0000 97: 0x0801 0x42B0 0x0002 0x0000 0x0000 98: 0x0801 0x42B0 0x0003 0x0000 0x0000 99: 0x0801 0x4270 0x0002 0x0000 0x0000 100: 0x0801 0x4270 0x0003 0x0000 0x0000 101: 0x0801 0x42F0 0x0002 0x0000 0x0000 102: 0x0801 0x42F0 0x0001 0x0000 0x0000 103: 0x0801 0x4210 0x0002 0x0000 0x0000 104: 0x0801 0x4210 0x0002 0x0000 0x0000 105: 0xF71E 0xBCEF 0x0001 0x0000 0x0000 106: 0x0F1E 0xBCEF 0x0001 0x0000 0x0000 107: 0x1F1E 0xBCEF 0x0001 0x0000 0x0000 108: 0x2F1E 0xBCEF 0x0001 0x0000 0x0000 109: 0x3F1E 0xBCEF 0x0001 0x0000 0x0000 110: 0x4F1E 0xBCEF 0x0001 0x0000 0x0000 111: 0x5F1E 0xBCEF 0x0001 0x0000 0x0000 112: 0x6F1E 0xBCEF 0x0001 0x0000 0x0000 113: 0x7F1E 0xBCEF 0x0001 0x0000 0x0000 114: 0x8F1E 0xBCEF 0x0001 0x0000 0x0000 115: 0x9F1E 0xBCEF 0x0001 0x0000 0x0000 116: 0xAF1E 0xBCEF 0x0001 0x0000 0x0000 117: 0xBF1E 0xBCEF 0x0001 0x0000 0x0000 118: 0xCF1E 0xBCEF 0x0001 0x0000 0x0000 119: 0xDF1E 0xBCEF 0x0001 0x0000 0x0000 120: 0xEF1E 0xBCEF 0x0001 0x0000 0x0000 121: 0xF71E 0xBCEF 0x0001 0x0000 0x0000 122: 0xF701 0xBCEF 0x0001 0x0000 0x0000 123: 0xF703 0xBCEF 0x0001 0x0000 0x0000 124: 0xF705 0xBCEF 0x0001 0x0000 0x0000 125: 0xF707 0xBCEF 0x0001 0x0000 0x0000 126: 0xF709 0xBCEF 0x0001 0x0000 0x0000 127: 0xF70B 0xBCEF 0x0001 0x0000 0x0000 128: 0xF70D 0xBCEF 0x0001 0x0000 0x0000 129: 0xF70F 0xBCEF 0x0001 0x0000 0x0000 130: 0xF711 0xBCEF 0x0001 0x0000 0x0000 131: 0xF713 0xBCEF 0x0001 0x0000 0x0000 132: 0xF715 0xBCEF 0x0001 0x0000 0x0000 133: 0xF717 0xBCEF 0x0001 0x0000 0x0000 134: 0xF719 0xBCEF 0x0001 0x0000 0x0000 135: 0xF71B 0xBCEF 0x0001 0x0000 0x0000 136: 0xF71D 0xBCEF 0x0001 0x0000 0x0000 137: 0xF71E 0xBCEF 0x0001 0x0000 0x0000 138: 0xF01E 0x7CEF 0x0001 0x0000 0x0000 139: 0xF01E 0xFCEF 0x0001 0x0000 0x0000 140: 0xF11E 0x7CEF 0x0001 0x0000 0x0000 141: 0xF11E 0xFCEF 0x0001 0x0000 0x0000 142: 0xF21E 0x7CEF 0x0001 0x0000 0x0000 143: 0xF21E 0xFCEF 0x0001 0x0000 0x0000 144: 0xF31E 0x7CEF 0x0001 0x0000 0x0000 145: 0xF31E 0xFCEF 0x0001 0x0000 0x0000 146: 0xF41E 0x7CEF 0x0001 0x0000 0x0000 147: 0xF41E 0xFCEF 0x0001 0x0000 0x0000 148: 0xF51E 0x7CEF 0x0001 0x0000 0x0000 149: 0xF51E 0xFCEF 0x0001 0x0000 0x0000 150: 0xF61E 0x7CEF 0x0001 0x0000 0x0000 151: 0xF61E 0xFCEF 0x0001 0x0000 0x0000 152: 0xF71E 0x7CEF 0x0001 0x0000 0x0000 153: 0xF71E 0xBCEF 0x0001 0x0000 0x0000 154: 0xF71E 0xBCF0 0x0001 0x0000 0x0000 155: 0xF71E 0xBCF8 0x0001 0x0000 0x0000 156: 0xF71E 0xBCF4 0x0001 0x0000 0x0000 157: 0xF71E 0xBCFC 0x0001 0x0000 0x0000 158: 0xF71E 0xBCF2 0x0001 0x0000 0x0000 159: 0xF71E 0xBCFA 0x0001 0x0000 0x0000 160: 0xF71E 0xBCF6 0x0001 0x0000 0x0000 161: 0xF71E 0xBCFE 0x0001 0x0000 0x0000 162: 0xF71E 0xBCF1 0x0001 0x0000 0x0000 163: 0xF71E 0xBCF9 0x0001 0x0000 0x0000 164: 0xF71E 0xBCF5 0x0001 0x0000 0x0000 165: 0xF71E 0xBCFD 0x0001 0x0000 0x0000 166: 0xF71E 0xBCF3 0x0001 0x0000 0x0000 167: 0xF71E 0xBCFB 0x0001 0x0000 0x0000 168: 0xF71E 0xBCF7 0x0001 0x0000 0x0000 169: 0xF71E 0xBCEF 0x0001 0x0000 0x0000 170: 0xF71E 0x82EF 0x0001 0x0000 0x0000 171: 0xF71E 0x86EF 0x0001 0x0000 0x0000 172: 0xF71E 0x8AEF 0x0001 0x0000 0x0000 173: 0xF71E 0x8EEF 0x0001 0x0000 0x0000 174: 0xF71E 0x92EF 0x0001 0x0000 0x0000 175: 0xF71E 0x96EF 0x0001 0x0000 0x0000 176: 0xF71E 0x9AEF 0x0001 0x0000 0x0000 177: 0xF71E 0x9EEF 0x0001 0x0000 0x0000 178: 0xF71E 0xA2EF 0x0001 0x0000 0x0000 179: 0xF71E 0xA6EF 0x0001 0x0000 0x0000 180: 0xF71E 0xAAEF 0x0001 0x0000 0x0000 181: 0xF71E 0xAEEF 0x0001 0x0000 0x0000 182: 0xF71E 0xB2EF 0x0001 0x0000 0x0000 183: 0xF71E 0xB6EF 0x0001 0x0000 0x0000 184: 0xF71E 0xBAEF 0x0001 0x0000 0x0000 185: 0xF71E 0xBCEF 0x0001 0x0000 0x0000 186: 0xF71E 0xBC0F 0x0002 0x0000 0x0000 187: 0xF71E 0xBC0F 0x0003 0x0000 0x0000 188: 0xF71E 0xBC8F 0x0002 0x0000 0x0000 189: 0xF71E 0xBC8F 0x0003 0x0000 0x0000 190: 0xF71E 0xBC4F 0x0002 0x0000 0x0000 191: 0xF71E 0xBC4F 0x0003 0x0000 0x0000 192: 0xF71E 0xBCCF 0x0002 0x0000 0x0000 193: 0xF71E 0xBCCF 0x0003 0x0000 0x0000 194: 0xF71E 0xBC2F 0x0002 0x0000 0x0000 195: 0xF71E 0xBC2F 0x0003 0x0000 0x0000 196: 0xF71E 0xBCAF 0x0002 0x0000 0x0000 197: 0xF71E 0xBCAF 0x0003 0x0000 0x0000 198: 0xF71E 0xBC6F 0x0002 0x0000 0x0000 199: 0xF71E 0xBC6F 0x0003 0x0000 0x0000 200: 0xF71E 0xBCEF 0x0002 0x0000 0x0000 201: 0xF71E 0xBCEF 0x0001 0x0000 0x0000 202: 0xF71E 0xBCEF 0x0001 0x0000 0x0000 PINs used (in edge connector order) (G=ground,P=power) SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBB LETTER ABCDEFHJKLMNPRSTUVABCDEFHJKLMNPRSTUVABCDEFHJKLMNPRSTUVABCDEFHJKLMNPRSTUV SIDE 111111111111111111222222222222222222111111111111111111222222222222222222 USAGE IIIIOIIIIOIIIIOG P GIIIIOIIIIOIIIIO G P G UUT inputs: 24 UUT outputs: 6 pins used: 30 not used: 36 202 'test steps' 238 lines M516 POSITIVE BUS RECEIVER (6 4-input NAND) (3 7420) PCB REV A SCHEMATIC REV (blank) PINS Main menu Mon Jul 10 15:08:10 2017 test file is: tests\m516.tst delay is: 0 trigger is: 1 1 read test file 2 set test delay 3 set test trigger 4 run test 5 output loading test 8 diags 9 exit UUT power is okay Mon Jul 10 15:08:12 2017 space single step O run once (one test, all steps) F run, stop on fail G go (run tests N run, stop on fail, no print S scope (run, no print) C turn on comment printout + increase speed (less delay) - decrease speed (more delay)(slower) Q quit test scope (run, no print) FFFFFFFFFFFFFFFFFF space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn on comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEDEFHJFHJKLKLMNPMNPRSRSTUV SIDE 111112222211111222221111122222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 00001 step 35 000000000100001000010000100001 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEDEFHJFHJKLKLMNPMNPRSRSTUV SIDE 111112222211111222221111122222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: step 36 000000000100001000010000100001 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEDEFHJFHJKLKLMNPMNPRSRSTUV SIDE 111112222211111222221111122222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 1 step 37 000000000100011000010000100001 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEDEFHJFHJKLKLMNPMNPRSRSTUV SIDE 111112222211111222221111122222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 10 step 38 000000000100101000010000100001 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEDEFHJFHJKLKLMNPMNPRSRSTUV SIDE 111112222211111222221111122222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 1 step 39 000000000100111000010000100001 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEDEFHJFHJKLKLMNPMNPRSRSTUV SIDE 111112222211111222221111122222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 100 step 40 000000000101001000010000100001 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEDEFHJFHJKLKLMNPMNPRSRSTUV SIDE 111112222211111222221111122222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 1 step 41 000000000101011000010000100001 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEDEFHJFHJKLKLMNPMNPRSRSTUV SIDE 111112222211111222221111122222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 10 step 42 000000000101101000010000100001 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEDEFHJFHJKLKLMNPMNPRSRSTUV SIDE 111112222211111222221111122222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 1 step 43 000000000101111000010000100001 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEDEFHJFHJKLKLMNPMNPRSRSTUV SIDE 111112222211111222221111122222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 1000 step 44 000000000110001000010000100001 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEDEFHJFHJKLKLMNPMNPRSRSTUV SIDE 111112222211111222221111122222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 1 step 45 000000000110011000010000100001 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEDEFHJFHJKLKLMNPMNPRSRSTUV SIDE 111112222211111222221111122222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 10 step 46 000000000110101000010000100001 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEDEFHJFHJKLKLMNPMNPRSRSTUV SIDE 111112222211111222221111122222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 1 step 47 000000000110111000010000100001 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEDEFHJFHJKLKLMNPMNPRSRSTUV SIDE 111112222211111222221111122222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 100 step 48 000000000111001000010000100001 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEDEFHJFHJKLKLMNPMNPRSRSTUV SIDE 111112222211111222221111122222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 1 step 49 000000000111011000010000100001 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEDEFHJFHJKLKLMNPMNPRSRSTUV SIDE 111112222211111222221111122222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 10 step 50 000000000111101000010000100001 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEDEFHJFHJKLKLMNPMNPRSRSTUV SIDE 111112222211111222221111122222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 10 step 51 000000000111110000010000100001 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEDEFHJFHJKLKLMNPMNPRSRSTUV SIDE 111112222211111222221111122222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 00001 step 52 000000000100001000010000100001 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEDEFHJFHJKLKLMNPMNPRSRSTUV SIDE 111112222211111222221111122222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: step 53 000000000100001000010000100001 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEDEFHJFHJKLKLMNPMNPRSRSTUV SIDE 111112222211111222221111122222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 1 step 54 000000000100001000110000100001 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEDEFHJFHJKLKLMNPMNPRSRSTUV SIDE 111112222211111222221111122222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 10 step 55 000000000100001001010000100001 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEDEFHJFHJKLKLMNPMNPRSRSTUV SIDE 111112222211111222221111122222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 1 step 56 000000000100001001110000100001 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEDEFHJFHJKLKLMNPMNPRSRSTUV SIDE 111112222211111222221111122222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 100 step 57 000000000100001010010000100001 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEDEFHJFHJKLKLMNPMNPRSRSTUV SIDE 111112222211111222221111122222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 1 step 58 000000000100001010110000100001 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEDEFHJFHJKLKLMNPMNPRSRSTUV SIDE 111112222211111222221111122222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 10 step 59 000000000100001011010000100001 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEDEFHJFHJKLKLMNPMNPRSRSTUV SIDE 111112222211111222221111122222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 1 step 60 000000000100001011110000100001 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEDEFHJFHJKLKLMNPMNPRSRSTUV SIDE 111112222211111222221111122222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 1000 step 61 000000000100001100010000100001 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEDEFHJFHJKLKLMNPMNPRSRSTUV SIDE 111112222211111222221111122222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 1 step 62 000000000100001100110000100001 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEDEFHJFHJKLKLMNPMNPRSRSTUV SIDE 111112222211111222221111122222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 10 step 63 000000000100001101010000100001 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEDEFHJFHJKLKLMNPMNPRSRSTUV SIDE 111112222211111222221111122222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 1 step 64 000000000100001101110000100001 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEDEFHJFHJKLKLMNPMNPRSRSTUV SIDE 111112222211111222221111122222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 100 step 65 000000000100001110010000100001 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEDEFHJFHJKLKLMNPMNPRSRSTUV SIDE 111112222211111222221111122222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 1 step 66 000000000100001110110000100001 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEDEFHJFHJKLKLMNPMNPRSRSTUV SIDE 111112222211111222221111122222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 10 step 67 000000000100001111010000100001 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEDEFHJFHJKLKLMNPMNPRSRSTUV SIDE 111112222211111222221111122222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 10 step 68 000000000100001111100000100001 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEDEFHJFHJKLKLMNPMNPRSRSTUV SIDE 111112222211111222221111122222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 00001 step 69 000000000100001000010000100001 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEDEFHJFHJKLKLMNPMNPRSRSTUV SIDE 111112222211111222221111122222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: step 70 000000000100001000010000100001 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEDEFHJFHJKLKLMNPMNPRSRSTUV SIDE 111112222211111222221111122222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 1 step 71 000000000100001000010001100001 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEDEFHJFHJKLKLMNPMNPRSRSTUV SIDE 111112222211111222221111122222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 10 step 72 000000000100001000010010100001 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEDEFHJFHJKLKLMNPMNPRSRSTUV SIDE 111112222211111222221111122222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 1 step 73 000000000100001000010011100001 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEDEFHJFHJKLKLMNPMNPRSRSTUV SIDE 111112222211111222221111122222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 100 step 74 000000000100001000010100100001 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEDEFHJFHJKLKLMNPMNPRSRSTUV SIDE 111112222211111222221111122222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 1 step 75 000000000100001000010101100001 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEDEFHJFHJKLKLMNPMNPRSRSTUV SIDE 111112222211111222221111122222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 10 step 76 000000000100001000010110100001 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEDEFHJFHJKLKLMNPMNPRSRSTUV SIDE 111112222211111222221111122222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 1 step 77 000000000100001000010111100001 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEDEFHJFHJKLKLMNPMNPRSRSTUV SIDE 111112222211111222221111122222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 1000 step 78 000000000100001000011000100001 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEDEFHJFHJKLKLMNPMNPRSRSTUV SIDE 111112222211111222221111122222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 1 step 79 000000000100001000011001100001 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEDEFHJFHJKLKLMNPMNPRSRSTUV SIDE 111112222211111222221111122222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 10 step 80 000000000100001000011010100001 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEDEFHJFHJKLKLMNPMNPRSRSTUV SIDE 111112222211111222221111122222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 1 step 81 000000000100001000011011100001 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEDEFHJFHJKLKLMNPMNPRSRSTUV SIDE 111112222211111222221111122222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 100 step 82 000000000100001000011100100001 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEDEFHJFHJKLKLMNPMNPRSRSTUV SIDE 111112222211111222221111122222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 1 step 83 000000000100001000011101100001 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEDEFHJFHJKLKLMNPMNPRSRSTUV SIDE 111112222211111222221111122222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 10 step 84 000000000100001000011110100001 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEDEFHJFHJKLKLMNPMNPRSRSTUV SIDE 111112222211111222221111122222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 10 step 85 000000000100001000011111000001 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEDEFHJFHJKLKLMNPMNPRSRSTUV SIDE 111112222211111222221111122222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 00001 step 86 000000000100001000010000100001 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEDEFHJFHJKLKLMNPMNPRSRSTUV SIDE 111112222211111222221111122222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: step 87 000000000100001000010000100001 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEDEFHJFHJKLKLMNPMNPRSRSTUV SIDE 111112222211111222221111122222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 1 step 88 000000000100001000010000100011 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEDEFHJFHJKLKLMNPMNPRSRSTUV SIDE 111112222211111222221111122222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 10 step 89 000000000100001000010000100101 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEDEFHJFHJKLKLMNPMNPRSRSTUV SIDE 111112222211111222221111122222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 1 step 90 000000000100001000010000100111 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEDEFHJFHJKLKLMNPMNPRSRSTUV SIDE 111112222211111222221111122222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 100 step 91 000000000100001000010000101001 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEDEFHJFHJKLKLMNPMNPRSRSTUV SIDE 111112222211111222221111122222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 1 step 92 000000000100001000010000101011 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEDEFHJFHJKLKLMNPMNPRSRSTUV SIDE 111112222211111222221111122222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 10 step 93 000000000100001000010000101101 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEDEFHJFHJKLKLMNPMNPRSRSTUV SIDE 111112222211111222221111122222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 1 step 94 000000000100001000010000101111 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEDEFHJFHJKLKLMNPMNPRSRSTUV SIDE 111112222211111222221111122222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 1000 step 95 000000000100001000010000110001 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEDEFHJFHJKLKLMNPMNPRSRSTUV SIDE 111112222211111222221111122222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 1 step 96 000000000100001000010000110011 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEDEFHJFHJKLKLMNPMNPRSRSTUV SIDE 111112222211111222221111122222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 10 step 97 000000000100001000010000110101 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEDEFHJFHJKLKLMNPMNPRSRSTUV SIDE 111112222211111222221111122222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 1 step 98 000000000100001000010000110111 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEDEFHJFHJKLKLMNPMNPRSRSTUV SIDE 111112222211111222221111122222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 100 step 99 000000000100001000010000111001 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEDEFHJFHJKLKLMNPMNPRSRSTUV SIDE 111112222211111222221111122222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 1 step 100 000000000100001000010000111011 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEDEFHJFHJKLKLMNPMNPRSRSTUV SIDE 111112222211111222221111122222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 10 step 101 000000000100001000010000111101 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEDEFHJFHJKLKLMNPMNPRSRSTUV SIDE 111112222211111222221111122222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 10 step 102 000000000100001000010000111110 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEDEFHJFHJKLKLMNPMNPRSRSTUV SIDE 111112222211111222221111122222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 00001 step 103 000000000100001000010000100001 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEDEFHJFHJKLKLMNPMNPRSRSTUV SIDE 111112222211111222221111122222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: step 104 000000000100001000010000100001 fail ^ step 105 111101111011110111101111011110 SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEDEFHJFHJKLKLMNPMNPRSRSTUV SIDE 111112222211111222221111122222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 0000 step 106 000001111011110111101111011110 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEDEFHJFHJKLKLMNPMNPRSRSTUV SIDE 111112222211111222221111122222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 1 step 107 000101111011110111101111011110 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEDEFHJFHJKLKLMNPMNPRSRSTUV SIDE 111112222211111222221111122222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 10 step 108 001001111011110111101111011110 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEDEFHJFHJKLKLMNPMNPRSRSTUV SIDE 111112222211111222221111122222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 1 step 109 001101111011110111101111011110 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEDEFHJFHJKLKLMNPMNPRSRSTUV SIDE 111112222211111222221111122222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 100 step 110 010001111011110111101111011110 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEDEFHJFHJKLKLMNPMNPRSRSTUV SIDE 111112222211111222221111122222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 1 step 111 010101111011110111101111011110 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEDEFHJFHJKLKLMNPMNPRSRSTUV SIDE 111112222211111222221111122222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 10 step 112 011001111011110111101111011110 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEDEFHJFHJKLKLMNPMNPRSRSTUV SIDE 111112222211111222221111122222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 1 step 113 011101111011110111101111011110 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEDEFHJFHJKLKLMNPMNPRSRSTUV SIDE 111112222211111222221111122222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 1000 step 114 100001111011110111101111011110 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEDEFHJFHJKLKLMNPMNPRSRSTUV SIDE 111112222211111222221111122222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 1 step 115 100101111011110111101111011110 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEDEFHJFHJKLKLMNPMNPRSRSTUV SIDE 111112222211111222221111122222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 10 step 116 101001111011110111101111011110 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEDEFHJFHJKLKLMNPMNPRSRSTUV SIDE 111112222211111222221111122222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 1 step 117 101101111011110111101111011110 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEDEFHJFHJKLKLMNPMNPRSRSTUV SIDE 111112222211111222221111122222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 100 step 118 110001111011110111101111011110 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEDEFHJFHJKLKLMNPMNPRSRSTUV SIDE 111112222211111222221111122222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 1 step 119 110101111011110111101111011110 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEDEFHJFHJKLKLMNPMNPRSRSTUV SIDE 111112222211111222221111122222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 10 step 120 111001111011110111101111011110 fail ^ step 121 111101111011110111101111011110 step 122 111100000111110111101111011110 step 123 111100001111110111101111011110 step 124 111100010111110111101111011110 step 125 111100011111110111101111011110 step 126 111100100111110111101111011110 step 127 111100101111110111101111011110 step 128 111100110111110111101111011110 step 129 111100111111110111101111011110 step 130 111101000111110111101111011110 step 131 111101001111110111101111011110 step 132 111101010111110111101111011110 step 133 111101011111110111101111011110 step 134 111101100111110111101111011110 step 135 111101101111110111101111011110 step 136 111101110111110111101111011110 step 137 111101111011110111101111011110 step 138 111101111000001111101111011110 step 139 111101111000011111101111011110 step 140 111101111000101111101111011110 step 141 111101111000111111101111011110 step 142 111101111001001111101111011110 step 143 111101111001011111101111011110 step 144 111101111001101111101111011110 step 145 111101111001111111101111011110 step 146 111101111010001111101111011110 step 147 111101111010011111101111011110 step 148 111101111010101111101111011110 step 149 111101111010111111101111011110 step 150 111101111011001111101111011110 step 151 111101111011011111101111011110 step 152 111101111011101111101111011110 step 153 111101111011110111101111011110 step 154 111101111011110000011111011110 step 155 111101111011110000111111011110 step 156 111101111011110001011111011110 step 157 111101111011110001111111011110 step 158 111101111011110010011111011110 step 159 111101111011110010111111011110 step 160 111101111011110011011111011110 step 161 111101111011110011111111011110 step 162 111101111011110100011111011110 step 163 111101111011110100111111011110 step 164 111101111011110101011111011110 step 165 111101111011110101111111011110 step 166 111101111011110110011111011110 step 167 111101111011110110111111011110 step 168 111101111011110111011111011110 step 169 111101111011110111101111011110 step 170 111101111011110111100000111110 step 171 111101111011110111100001111110 step 172 111101111011110111100010111110 step 173 111101111011110111100011111110 step 174 111101111011110111100100111110 step 175 111101111011110111100101111110 step 176 111101111011110111100110111110 step 177 111101111011110111100111111110 step 178 111101111011110111101000111110 step 179 111101111011110111101001111110 step 180 111101111011110111101010111110 step 181 111101111011110111101011111110 step 182 111101111011110111101100111110 step 183 111101111011110111101101111110 step 184 111101111011110111101110111110 step 185 111101111011110111101111011110 step 186 111101111011110111101111000001 step 187 111101111011110111101111000011 step 188 111101111011110111101111000101 step 189 111101111011110111101111000111 step 190 111101111011110111101111001001 step 191 111101111011110111101111001011 step 192 111101111011110111101111001101 step 193 111101111011110111101111001111 step 194 111101111011110111101111010001 step 195 111101111011110111101111010011 step 196 111101111011110111101111010101 step 197 111101111011110111101111010111 step 198 111101111011110111101111011001 step 199 111101111011110111101111011011 step 200 111101111011110111101111011101 step 201 111101111011110111101111011110 step 202 111101111011110111101111011110 test 19: *** FAIL *************************** 118 steps failed SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEDEFHJFHJKLKLMNPMNPRSRSTUV SIDE 111112222211111222221111122222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO this fail O all fails O was hi 1111 1111111111111111111111111 rising ^^^^ ^^^^^^^^^^^^^^^^^^^^^^^^^ falling vvvv vvvvvvvvvvvvvvvvvvvvvvvvv was lo 000000000000000000000000000000 total fails 19, total passes 0 space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn on comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEDEFHJFHJKLKLMNPMNPRSRSTUV SIDE 111112222211111222221111122222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 0000 0000100001000010000100001 step 1 000000000100001000010000100001 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEDEFHJFHJKLKLMNPMNPRSRSTUV SIDE 111112222211111222221111122222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: step 2 000000000100001000010000100001 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEDEFHJFHJKLKLMNPMNPRSRSTUV SIDE 111112222211111222221111122222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 1 step 3 000100000100001000010000100001 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEDEFHJFHJKLKLMNPMNPRSRSTUV SIDE 111112222211111222221111122222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 10 step 4 001000000100001000010000100001 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEDEFHJFHJKLKLMNPMNPRSRSTUV SIDE 111112222211111222221111122222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 1 step 5 001100000100001000010000100001 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEDEFHJFHJKLKLMNPMNPRSRSTUV SIDE 111112222211111222221111122222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 100 step 6 010000000100001000010000100001 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEDEFHJFHJKLKLMNPMNPRSRSTUV SIDE 111112222211111222221111122222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 1 step 7 010100000100001000010000100001 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEDEFHJFHJKLKLMNPMNPRSRSTUV SIDE 111112222211111222221111122222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 10 step 8 011000000100001000010000100001 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEDEFHJFHJKLKLMNPMNPRSRSTUV SIDE 111112222211111222221111122222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 1 step 9 011100000100001000010000100001 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEDEFHJFHJKLKLMNPMNPRSRSTUV SIDE 111112222211111222221111122222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 1000 step 10 100000000100001000010000100001 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEDEFHJFHJKLKLMNPMNPRSRSTUV SIDE 111112222211111222221111122222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 1 step 11 100100000100001000010000100001 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEDEFHJFHJKLKLMNPMNPRSRSTUV SIDE 111112222211111222221111122222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 10 step 12 101000000100001000010000100001 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEDEFHJFHJKLKLMNPMNPRSRSTUV SIDE 111112222211111222221111122222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 1 step 13 101100000100001000010000100001 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEDEFHJFHJKLKLMNPMNPRSRSTUV SIDE 111112222211111222221111122222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 100 step 14 110000000100001000010000100001 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEDEFHJFHJKLKLMNPMNPRSRSTUV SIDE 111112222211111222221111122222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 1 step 15 110100000100001000010000100001 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEDEFHJFHJKLKLMNPMNPRSRSTUV SIDE 111112222211111222221111122222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 10 step 16 111000000100001000010000100001 fail ^ step 17 111100000100001000010000100001 SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEDEFHJFHJKLKLMNPMNPRSRSTUV SIDE 111112222211111222221111122222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 0000 step 18 000000000100001000010000100001 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEDEFHJFHJKLKLMNPMNPRSRSTUV SIDE 111112222211111222221111122222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: step 19 000000000100001000010000100001 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEDEFHJFHJKLKLMNPMNPRSRSTUV SIDE 111112222211111222221111122222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 1 step 20 000000001100001000010000100001 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEDEFHJFHJKLKLMNPMNPRSRSTUV SIDE 111112222211111222221111122222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 10 step 21 000000010100001000010000100001 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEDEFHJFHJKLKLMNPMNPRSRSTUV SIDE 111112222211111222221111122222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 1 step 22 000000011100001000010000100001 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEDEFHJFHJKLKLMNPMNPRSRSTUV SIDE 111112222211111222221111122222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 100 step 23 000000100100001000010000100001 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEDEFHJFHJKLKLMNPMNPRSRSTUV SIDE 111112222211111222221111122222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 1 step 24 000000101100001000010000100001 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEDEFHJFHJKLKLMNPMNPRSRSTUV SIDE 111112222211111222221111122222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 10 step 25 000000110100001000010000100001 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEDEFHJFHJKLKLMNPMNPRSRSTUV SIDE 111112222211111222221111122222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 1 step 26 000000111100001000010000100001 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEDEFHJFHJKLKLMNPMNPRSRSTUV SIDE 111112222211111222221111122222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 1000 step 27 000001000100001000010000100001 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEDEFHJFHJKLKLMNPMNPRSRSTUV SIDE 111112222211111222221111122222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 1 step 28 000001001100001000010000100001 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEDEFHJFHJKLKLMNPMNPRSRSTUV SIDE 111112222211111222221111122222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 10 step 29 000001010100001000010000100001 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEDEFHJFHJKLKLMNPMNPRSRSTUV SIDE 111112222211111222221111122222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 1 step 30 000001011100001000010000100001 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEDEFHJFHJKLKLMNPMNPRSRSTUV SIDE 111112222211111222221111122222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 100 step 31 000001100100001000010000100001 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEDEFHJFHJKLKLMNPMNPRSRSTUV SIDE 111112222211111222221111122222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 1 step 32 000001101100001000010000100001 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEDEFHJFHJKLKLMNPMNPRSRSTUV SIDE 111112222211111222221111122222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 10 step 33 000001110100001000010000100001 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEDEFHJFHJKLKLMNPMNPRSRSTUV SIDE 111112222211111222221111122222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 10 step 34 000001111000001000010000100001 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEDEFHJFHJKLKLMNPMNPRSRSTUV SIDE 111112222211111222221111122222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 00001 step 35 000000000100001000010000100001 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEDEFHJFHJKLKLMNPMNPRSRSTUV SIDE 111112222211111222221111122222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: step 36 000000000100001000010000100001 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEDEFHJFHJKLKLMNPMNPRSRSTUV SIDE 111112222211111222221111122222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 1 step 37 000000000100011000010000100001 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEDEFHJFHJKLKLMNPMNPRSRSTUV SIDE 111112222211111222221111122222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 10 step 38 000000000100101000010000100001 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEDEFHJFHJKLKLMNPMNPRSRSTUV SIDE 111112222211111222221111122222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 1 step 39 000000000100111000010000100001 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEDEFHJFHJKLKLMNPMNPRSRSTUV SIDE 111112222211111222221111122222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 100 step 40 000000000101001000010000100001 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEDEFHJFHJKLKLMNPMNPRSRSTUV SIDE 111112222211111222221111122222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 1 step 41 000000000101011000010000100001 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEDEFHJFHJKLKLMNPMNPRSRSTUV SIDE 111112222211111222221111122222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 10 step 42 000000000101101000010000100001 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEDEFHJFHJKLKLMNPMNPRSRSTUV SIDE 111112222211111222221111122222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 1 step 43 000000000101111000010000100001 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEDEFHJFHJKLKLMNPMNPRSRSTUV SIDE 111112222211111222221111122222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 1000 step 44 000000000110001000010000100001 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEDEFHJFHJKLKLMNPMNPRSRSTUV SIDE 111112222211111222221111122222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 1 step 45 000000000110011000010000100001 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEDEFHJFHJKLKLMNPMNPRSRSTUV SIDE 111112222211111222221111122222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 10 step 46 000000000110101000010000100001 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEDEFHJFHJKLKLMNPMNPRSRSTUV SIDE 111112222211111222221111122222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 1 step 47 000000000110111000010000100001 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEDEFHJFHJKLKLMNPMNPRSRSTUV SIDE 111112222211111222221111122222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 100 step 48 000000000111001000010000100001 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEDEFHJFHJKLKLMNPMNPRSRSTUV SIDE 111112222211111222221111122222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 1 step 49 000000000111011000010000100001 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEDEFHJFHJKLKLMNPMNPRSRSTUV SIDE 111112222211111222221111122222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 10 step 50 000000000111101000010000100001 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEDEFHJFHJKLKLMNPMNPRSRSTUV SIDE 111112222211111222221111122222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 10 step 51 000000000111110000010000100001 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEDEFHJFHJKLKLMNPMNPRSRSTUV SIDE 111112222211111222221111122222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 00001 step 52 000000000100001000010000100001 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEDEFHJFHJKLKLMNPMNPRSRSTUV SIDE 111112222211111222221111122222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: step 53 000000000100001000010000100001 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEDEFHJFHJKLKLMNPMNPRSRSTUV SIDE 111112222211111222221111122222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 1 step 54 000000000100001000110000100001 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEDEFHJFHJKLKLMNPMNPRSRSTUV SIDE 111112222211111222221111122222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 10 step 55 000000000100001001010000100001 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEDEFHJFHJKLKLMNPMNPRSRSTUV SIDE 111112222211111222221111122222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 1 step 56 000000000100001001110000100001 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEDEFHJFHJKLKLMNPMNPRSRSTUV SIDE 111112222211111222221111122222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 100 step 57 000000000100001010010000100001 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEDEFHJFHJKLKLMNPMNPRSRSTUV SIDE 111112222211111222221111122222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 1 step 58 000000000100001010110000100001 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEDEFHJFHJKLKLMNPMNPRSRSTUV SIDE 111112222211111222221111122222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 10 step 59 000000000100001011010000100001 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEDEFHJFHJKLKLMNPMNPRSRSTUV SIDE 111112222211111222221111122222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 1 step 60 000000000100001011110000100001 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEDEFHJFHJKLKLMNPMNPRSRSTUV SIDE 111112222211111222221111122222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 1000 step 61 000000000100001100010000100001 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEDEFHJFHJKLKLMNPMNPRSRSTUV SIDE 111112222211111222221111122222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 1 step 62 000000000100001100110000100001 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEDEFHJFHJKLKLMNPMNPRSRSTUV SIDE 111112222211111222221111122222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 10 step 63 000000000100001101010000100001 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEDEFHJFHJKLKLMNPMNPRSRSTUV SIDE 111112222211111222221111122222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 1 step 64 000000000100001101110000100001 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEDEFHJFHJKLKLMNPMNPRSRSTUV SIDE 111112222211111222221111122222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 100 step 65 000000000100001110010000100001 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEDEFHJFHJKLKLMNPMNPRSRSTUV SIDE 111112222211111222221111122222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 1 step 66 000000000100001110110000100001 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEDEFHJFHJKLKLMNPMNPRSRSTUV SIDE 111112222211111222221111122222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 10 step 67 000000000100001111010000100001 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEDEFHJFHJKLKLMNPMNPRSRSTUV SIDE 111112222211111222221111122222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 10 step 68 000000000100001111100000100001 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEDEFHJFHJKLKLMNPMNPRSRSTUV SIDE 111112222211111222221111122222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 00001 step 69 000000000100001000010000100001 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEDEFHJFHJKLKLMNPMNPRSRSTUV SIDE 111112222211111222221111122222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: step 70 000000000100001000010000100001 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEDEFHJFHJKLKLMNPMNPRSRSTUV SIDE 111112222211111222221111122222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 1 step 71 000000000100001000010001100001 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEDEFHJFHJKLKLMNPMNPRSRSTUV SIDE 111112222211111222221111122222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 10 step 72 000000000100001000010010100001 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEDEFHJFHJKLKLMNPMNPRSRSTUV SIDE 111112222211111222221111122222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 1 step 73 000000000100001000010011100001 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEDEFHJFHJKLKLMNPMNPRSRSTUV SIDE 111112222211111222221111122222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 100 step 74 000000000100001000010100100001 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEDEFHJFHJKLKLMNPMNPRSRSTUV SIDE 111112222211111222221111122222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 1 step 75 000000000100001000010101100001 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEDEFHJFHJKLKLMNPMNPRSRSTUV SIDE 111112222211111222221111122222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 10 step 76 000000000100001000010110100001 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEDEFHJFHJKLKLMNPMNPRSRSTUV SIDE 111112222211111222221111122222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 1 step 77 000000000100001000010111100001 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEDEFHJFHJKLKLMNPMNPRSRSTUV SIDE 111112222211111222221111122222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 1000 step 78 000000000100001000011000100001 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEDEFHJFHJKLKLMNPMNPRSRSTUV SIDE 111112222211111222221111122222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 1 step 79 000000000100001000011001100001 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEDEFHJFHJKLKLMNPMNPRSRSTUV SIDE 111112222211111222221111122222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 10 step 80 000000000100001000011010100001 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEDEFHJFHJKLKLMNPMNPRSRSTUV SIDE 111112222211111222221111122222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 1 step 81 000000000100001000011011100001 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEDEFHJFHJKLKLMNPMNPRSRSTUV SIDE 111112222211111222221111122222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 100 step 82 000000000100001000011100100001 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEDEFHJFHJKLKLMNPMNPRSRSTUV SIDE 111112222211111222221111122222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 1 step 83 000000000100001000011101100001 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEDEFHJFHJKLKLMNPMNPRSRSTUV SIDE 111112222211111222221111122222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 10 step 84 000000000100001000011110100001 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEDEFHJFHJKLKLMNPMNPRSRSTUV SIDE 111112222211111222221111122222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 10 step 85 000000000100001000011111000001 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEDEFHJFHJKLKLMNPMNPRSRSTUV SIDE 111112222211111222221111122222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 00001 step 86 000000000100001000010000100001 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEDEFHJFHJKLKLMNPMNPRSRSTUV SIDE 111112222211111222221111122222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: step 87 000000000100001000010000100001 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEDEFHJFHJKLKLMNPMNPRSRSTUV SIDE 111112222211111222221111122222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 1 step 88 000000000100001000010000100011 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEDEFHJFHJKLKLMNPMNPRSRSTUV SIDE 111112222211111222221111122222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 10 step 89 000000000100001000010000100101 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEDEFHJFHJKLKLMNPMNPRSRSTUV SIDE 111112222211111222221111122222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 1 step 90 000000000100001000010000100111 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEDEFHJFHJKLKLMNPMNPRSRSTUV SIDE 111112222211111222221111122222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 100 step 91 000000000100001000010000101001 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEDEFHJFHJKLKLMNPMNPRSRSTUV SIDE 111112222211111222221111122222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 1 step 92 000000000100001000010000101011 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEDEFHJFHJKLKLMNPMNPRSRSTUV SIDE 111112222211111222221111122222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 10 step 93 000000000100001000010000101101 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEDEFHJFHJKLKLMNPMNPRSRSTUV SIDE 111112222211111222221111122222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 1 step 94 000000000100001000010000101111 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEDEFHJFHJKLKLMNPMNPRSRSTUV SIDE 111112222211111222221111122222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 1000 step 95 000000000100001000010000110001 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEDEFHJFHJKLKLMNPMNPRSRSTUV SIDE 111112222211111222221111122222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 1 step 96 000000000100001000010000110011 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEDEFHJFHJKLKLMNPMNPRSRSTUV SIDE 111112222211111222221111122222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 10 step 97 000000000100001000010000110101 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEDEFHJFHJKLKLMNPMNPRSRSTUV SIDE 111112222211111222221111122222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 1 step 98 000000000100001000010000110111 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEDEFHJFHJKLKLMNPMNPRSRSTUV SIDE 111112222211111222221111122222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 100 step 99 000000000100001000010000111001 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEDEFHJFHJKLKLMNPMNPRSRSTUV SIDE 111112222211111222221111122222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 1 step 100 000000000100001000010000111011 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEDEFHJFHJKLKLMNPMNPRSRSTUV SIDE 111112222211111222221111122222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 10 step 101 000000000100001000010000111101 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEDEFHJFHJKLKLMNPMNPRSRSTUV SIDE 111112222211111222221111122222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 10 step 102 000000000100001000010000111110 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEDEFHJFHJKLKLMNPMNPRSRSTUV SIDE 111112222211111222221111122222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 00001 step 103 000000000100001000010000100001 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEDEFHJFHJKLKLMNPMNPRSRSTUV SIDE 111112222211111222221111122222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: step 104 000000000100001000010000100001 fail ^ step 105 111101111011110111101111011110 SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEDEFHJFHJKLKLMNPMNPRSRSTUV SIDE 111112222211111222221111122222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 0000 step 106 000001111011110111101111011110 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEDEFHJFHJKLKLMNPMNPRSRSTUV SIDE 111112222211111222221111122222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 1 step 107 000101111011110111101111011110 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEDEFHJFHJKLKLMNPMNPRSRSTUV SIDE 111112222211111222221111122222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 10 step 108 001001111011110111101111011110 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEDEFHJFHJKLKLMNPMNPRSRSTUV SIDE 111112222211111222221111122222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 1 step 109 001101111011110111101111011110 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEDEFHJFHJKLKLMNPMNPRSRSTUV SIDE 111112222211111222221111122222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 100 step 110 010001111011110111101111011110 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEDEFHJFHJKLKLMNPMNPRSRSTUV SIDE 111112222211111222221111122222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 1 step 111 010101111011110111101111011110 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEDEFHJFHJKLKLMNPMNPRSRSTUV SIDE 111112222211111222221111122222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 10 step 112 011001111011110111101111011110 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEDEFHJFHJKLKLMNPMNPRSRSTUV SIDE 111112222211111222221111122222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 1 step 113 011101111011110111101111011110 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEDEFHJFHJKLKLMNPMNPRSRSTUV SIDE 111112222211111222221111122222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 1000 step 114 100001111011110111101111011110 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEDEFHJFHJKLKLMNPMNPRSRSTUV SIDE 111112222211111222221111122222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 1 step 115 100101111011110111101111011110 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEDEFHJFHJKLKLMNPMNPRSRSTUV SIDE 111112222211111222221111122222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 10 step 116 101001111011110111101111011110 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEDEFHJFHJKLKLMNPMNPRSRSTUV SIDE 111112222211111222221111122222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 1 step 117 101101111011110111101111011110 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEDEFHJFHJKLKLMNPMNPRSRSTUV SIDE 111112222211111222221111122222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 100 step 118 110001111011110111101111011110 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEDEFHJFHJKLKLMNPMNPRSRSTUV SIDE 111112222211111222221111122222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 1 step 119 110101111011110111101111011110 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEDEFHJFHJKLKLMNPMNPRSRSTUV SIDE 111112222211111222221111122222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 10 step 120 111001111011110111101111011110 fail ^ step 121 111101111011110111101111011110 step 122 111100000111110111101111011110 step 123 111100001111110111101111011110 step 124 111100010111110111101111011110 step 125 111100011111110111101111011110 step 126 111100100111110111101111011110 step 127 111100101111110111101111011110 step 128 111100110111110111101111011110 step 129 111100111111110111101111011110 step 130 111101000111110111101111011110 step 131 111101001111110111101111011110 step 132 111101010111110111101111011110 step 133 111101011111110111101111011110 step 134 111101100111110111101111011110 step 135 111101101111110111101111011110 step 136 111101110111110111101111011110 step 137 111101111011110111101111011110 step 138 111101111000001111101111011110 step 139 111101111000011111101111011110 step 140 111101111000101111101111011110 step 141 111101111000111111101111011110 step 142 111101111001001111101111011110 step 143 111101111001011111101111011110 step 144 111101111001101111101111011110 step 145 111101111001111111101111011110 step 146 111101111010001111101111011110 step 147 111101111010011111101111011110 step 148 111101111010101111101111011110 step 149 111101111010111111101111011110 step 150 111101111011001111101111011110 step 151 111101111011011111101111011110 step 152 111101111011101111101111011110 step 153 111101111011110111101111011110 step 154 111101111011110000011111011110 step 155 111101111011110000111111011110 step 156 111101111011110001011111011110 step 157 111101111011110001111111011110 step 158 111101111011110010011111011110 step 159 111101111011110010111111011110 step 160 111101111011110011011111011110 step 161 111101111011110011111111011110 step 162 111101111011110100011111011110 step 163 111101111011110100111111011110 step 164 111101111011110101011111011110 step 165 111101111011110101111111011110 step 166 111101111011110110011111011110 step 167 111101111011110110111111011110 step 168 111101111011110111011111011110 step 169 111101111011110111101111011110 step 170 111101111011110111100000111110 step 171 111101111011110111100001111110 step 172 111101111011110111100010111110 step 173 111101111011110111100011111110 step 174 111101111011110111100100111110 step 175 111101111011110111100101111110 step 176 111101111011110111100110111110 step 177 111101111011110111100111111110 step 178 111101111011110111101000111110 step 179 111101111011110111101001111110 step 180 111101111011110111101010111110 step 181 111101111011110111101011111110 step 182 111101111011110111101100111110 step 183 111101111011110111101101111110 step 184 111101111011110111101110111110 step 185 111101111011110111101111011110 step 186 111101111011110111101111000001 step 187 111101111011110111101111000011 step 188 111101111011110111101111000101 step 189 111101111011110111101111000111 step 190 111101111011110111101111001001 step 191 111101111011110111101111001011 step 192 111101111011110111101111001101 step 193 111101111011110111101111001111 step 194 111101111011110111101111010001 step 195 111101111011110111101111010011 step 196 111101111011110111101111010101 step 197 111101111011110111101111010111 step 198 111101111011110111101111011001 step 199 111101111011110111101111011011 step 200 111101111011110111101111011101 step 201 111101111011110111101111011110 step 202 111101111011110111101111011110 test 20: *** FAIL *************************** 118 steps failed SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEDEFHJFHJKLKLMNPMNPRSRSTUV SIDE 111112222211111222221111122222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO this fail O all fails O was hi 1111 1111111111111111111111111 rising ^^^^ ^^^^^^^^^^^^^^^^^^^^^^^^^ falling vvvv vvvvvvvvvvvvvvvvvvvvvvvvv was lo 000000000000000000000000000000 total fails 20, total passes 0 space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn on comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEDEFHJFHJKLKLMNPMNPRSRSTUV SIDE 111112222211111222221111122222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 0000 0000100001000010000100001 step 1 000000000100001000010000100001 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEDEFHJFHJKLKLMNPMNPRSRSTUV SIDE 111112222211111222221111122222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: step 2 000000000100001000010000100001 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEDEFHJFHJKLKLMNPMNPRSRSTUV SIDE 111112222211111222221111122222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 1 step 3 000100000100001000010000100001 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEDEFHJFHJKLKLMNPMNPRSRSTUV SIDE 111112222211111222221111122222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 10 step 4 001000000100001000010000100001 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEDEFHJFHJKLKLMNPMNPRSRSTUV SIDE 111112222211111222221111122222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 1 step 5 001100000100001000010000100001 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEDEFHJFHJKLKLMNPMNPRSRSTUV SIDE 111112222211111222221111122222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 100 step 6 010000000100001000010000100001 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEDEFHJFHJKLKLMNPMNPRSRSTUV SIDE 111112222211111222221111122222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 1 step 7 010100000100001000010000100001 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEDEFHJFHJKLKLMNPMNPRSRSTUV SIDE 111112222211111222221111122222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 10 step 8 011000000100001000010000100001 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEDEFHJFHJKLKLMNPMNPRSRSTUV SIDE 111112222211111222221111122222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 1 step 9 011100000100001000010000100001 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEDEFHJFHJKLKLMNPMNPRSRSTUV SIDE 111112222211111222221111122222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 1000 step 10 100000000100001000010000100001 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEDEFHJFHJKLKLMNPMNPRSRSTUV SIDE 111112222211111222221111122222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 1 step 11 100100000100001000010000100001 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEDEFHJFHJKLKLMNPMNPRSRSTUV SIDE 111112222211111222221111122222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 10 step 12 101000000100001000010000100001 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEDEFHJFHJKLKLMNPMNPRSRSTUV SIDE 111112222211111222221111122222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 1 step 13 101100000100001000010000100001 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEDEFHJFHJKLKLMNPMNPRSRSTUV SIDE 111112222211111222221111122222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 100 step 14 110000000100001000010000100001 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEDEFHJFHJKLKLMNPMNPRSRSTUV SIDE 111112222211111222221111122222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 1 step 15 110100000100001000010000100001 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEDEFHJFHJKLKLMNPMNPRSRSTUV SIDE 111112222211111222221111122222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 10 step 16 111000000100001000010000100001 fail ^ step 17 111100000100001000010000100001 SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEDEFHJFHJKLKLMNPMNPRSRSTUV SIDE 111112222211111222221111122222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 0000 step 18 000000000100001000010000100001 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEDEFHJFHJKLKLMNPMNPRSRSTUV SIDE 111112222211111222221111122222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: step 19 000000000100001000010000100001 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEDEFHJFHJKLKLMNPMNPRSRSTUV SIDE 111112222211111222221111122222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 1 step 20 000000001100001000010000100001 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEDEFHJFHJKLKLMNPMNPRSRSTUV SIDE 111112222211111222221111122222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 10 step 21 000000010100001000010000100001 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEDEFHJFHJKLKLMNPMNPRSRSTUV SIDE 111112222211111222221111122222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 1 step 22 000000011100001000010000100001 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEDEFHJFHJKLKLMNPMNPRSRSTUV SIDE 111112222211111222221111122222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 100 step 23 000000100100001000010000100001 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEDEFHJFHJKLKLMNPMNPRSRSTUV SIDE 111112222211111222221111122222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 1 step 24 000000101100001000010000100001 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEDEFHJFHJKLKLMNPMNPRSRSTUV SIDE 111112222211111222221111122222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 10 step 25 000000110100001000010000100001 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEDEFHJFHJKLKLMNPMNPRSRSTUV SIDE 111112222211111222221111122222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 1 step 26 000000111100001000010000100001 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEDEFHJFHJKLKLMNPMNPRSRSTUV SIDE 111112222211111222221111122222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 1000 step 27 000001000100001000010000100001 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEDEFHJFHJKLKLMNPMNPRSRSTUV SIDE 111112222211111222221111122222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 1 step 28 000001001100001000010000100001 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEDEFHJFHJKLKLMNPMNPRSRSTUV SIDE 111112222211111222221111122222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 10 step 29 000001010100001000010000100001 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEDEFHJFHJKLKLMNPMNPRSRSTUV SIDE 111112222211111222221111122222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 1 step 30 000001011100001000010000100001 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEDEFHJFHJKLKLMNPMNPRSRSTUV SIDE 111112222211111222221111122222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 100 step 31 000001100100001000010000100001 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEDEFHJFHJKLKLMNPMNPRSRSTUV SIDE 111112222211111222221111122222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 1 step 32 000001101100001000010000100001 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEDEFHJFHJKLKLMNPMNPRSRSTUV SIDE 111112222211111222221111122222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 10 step 33 000001110100001000010000100001 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEDEFHJFHJKLKLMNPMNPRSRSTUV SIDE 111112222211111222221111122222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 10 step 34 000001111000001000010000100001 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEDEFHJFHJKLKLMNPMNPRSRSTUV SIDE 111112222211111222221111122222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 00001 step 35 000000000100001000010000100001 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEDEFHJFHJKLKLMNPMNPRSRSTUV SIDE 111112222211111222221111122222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: step 36 000000000100001000010000100001 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEDEFHJFHJKLKLMNPMNPRSRSTUV SIDE 111112222211111222221111122222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 1 step 37 000000000100011000010000100001 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEDEFHJFHJKLKLMNPMNPRSRSTUV SIDE 111112222211111222221111122222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 10 step 38 000000000100101000010000100001 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEDEFHJFHJKLKLMNPMNPRSRSTUV SIDE 111112222211111222221111122222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 1 step 39 000000000100111000010000100001 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEDEFHJFHJKLKLMNPMNPRSRSTUV SIDE 111112222211111222221111122222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 100 step 40 000000000101001000010000100001 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEDEFHJFHJKLKLMNPMNPRSRSTUV SIDE 111112222211111222221111122222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 1 step 41 000000000101011000010000100001 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEDEFHJFHJKLKLMNPMNPRSRSTUV SIDE 111112222211111222221111122222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 10 step 42 000000000101101000010000100001 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEDEFHJFHJKLKLMNPMNPRSRSTUV SIDE 111112222211111222221111122222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 1 step 43 000000000101111000010000100001 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEDEFHJFHJKLKLMNPMNPRSRSTUV SIDE 111112222211111222221111122222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 1000 step 44 000000000110001000010000100001 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEDEFHJFHJKLKLMNPMNPRSRSTUV SIDE 111112222211111222221111122222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 1 step 45 000000000110011000010000100001 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEDEFHJFHJKLKLMNPMNPRSRSTUV SIDE 111112222211111222221111122222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 10 step 46 000000000110101000010000100001 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEDEFHJFHJKLKLMNPMNPRSRSTUV SIDE 111112222211111222221111122222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 1 step 47 000000000110111000010000100001 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEDEFHJFHJKLKLMNPMNPRSRSTUV SIDE 111112222211111222221111122222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 100 step 48 000000000111001000010000100001 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEDEFHJFHJKLKLMNPMNPRSRSTUV SIDE 111112222211111222221111122222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 1 step 49 000000000111011000010000100001 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEDEFHJFHJKLKLMNPMNPRSRSTUV SIDE 111112222211111222221111122222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 10 step 50 000000000111101000010000100001 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEDEFHJFHJKLKLMNPMNPRSRSTUV SIDE 111112222211111222221111122222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 10 step 51 000000000111110000010000100001 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEDEFHJFHJKLKLMNPMNPRSRSTUV SIDE 111112222211111222221111122222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 00001 step 52 000000000100001000010000100001 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEDEFHJFHJKLKLMNPMNPRSRSTUV SIDE 111112222211111222221111122222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: step 53 000000000100001000010000100001 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEDEFHJFHJKLKLMNPMNPRSRSTUV SIDE 111112222211111222221111122222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 1 step 54 000000000100001000110000100001 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEDEFHJFHJKLKLMNPMNPRSRSTUV SIDE 111112222211111222221111122222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 10 step 55 000000000100001001010000100001 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEDEFHJFHJKLKLMNPMNPRSRSTUV SIDE 111112222211111222221111122222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 1 step 56 000000000100001001110000100001 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEDEFHJFHJKLKLMNPMNPRSRSTUV SIDE 111112222211111222221111122222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 100 step 57 000000000100001010010000100001 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEDEFHJFHJKLKLMNPMNPRSRSTUV SIDE 111112222211111222221111122222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 1 step 58 000000000100001010110000100001 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEDEFHJFHJKLKLMNPMNPRSRSTUV SIDE 111112222211111222221111122222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 10 step 59 000000000100001011010000100001 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEDEFHJFHJKLKLMNPMNPRSRSTUV SIDE 111112222211111222221111122222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 1 step 60 000000000100001011110000100001 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEDEFHJFHJKLKLMNPMNPRSRSTUV SIDE 111112222211111222221111122222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 1000 step 61 000000000100001100010000100001 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEDEFHJFHJKLKLMNPMNPRSRSTUV SIDE 111112222211111222221111122222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 1 step 62 000000000100001100110000100001 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEDEFHJFHJKLKLMNPMNPRSRSTUV SIDE 111112222211111222221111122222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 10 step 63 000000000100001101010000100001 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEDEFHJFHJKLKLMNPMNPRSRSTUV SIDE 111112222211111222221111122222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 1 step 64 000000000100001101110000100001 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEDEFHJFHJKLKLMNPMNPRSRSTUV SIDE 111112222211111222221111122222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 100 step 65 000000000100001110010000100001 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEDEFHJFHJKLKLMNPMNPRSRSTUV SIDE 111112222211111222221111122222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 1 step 66 000000000100001110110000100001 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEDEFHJFHJKLKLMNPMNPRSRSTUV SIDE 111112222211111222221111122222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 10 step 67 000000000100001111010000100001 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEDEFHJFHJKLKLMNPMNPRSRSTUV SIDE 111112222211111222221111122222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 10 step 68 000000000100001111100000100001 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEDEFHJFHJKLKLMNPMNPRSRSTUV SIDE 111112222211111222221111122222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 00001 step 69 000000000100001000010000100001 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEDEFHJFHJKLKLMNPMNPRSRSTUV SIDE 111112222211111222221111122222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: step 70 000000000100001000010000100001 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEDEFHJFHJKLKLMNPMNPRSRSTUV SIDE 111112222211111222221111122222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 1 step 71 000000000100001000010001100001 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEDEFHJFHJKLKLMNPMNPRSRSTUV SIDE 111112222211111222221111122222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 10 step 72 000000000100001000010010100001 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEDEFHJFHJKLKLMNPMNPRSRSTUV SIDE 111112222211111222221111122222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 1 step 73 000000000100001000010011100001 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEDEFHJFHJKLKLMNPMNPRSRSTUV SIDE 111112222211111222221111122222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 100 step 74 000000000100001000010100100001 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEDEFHJFHJKLKLMNPMNPRSRSTUV SIDE 111112222211111222221111122222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 1 step 75 000000000100001000010101100001 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEDEFHJFHJKLKLMNPMNPRSRSTUV SIDE 111112222211111222221111122222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 10 step 76 000000000100001000010110100001 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEDEFHJFHJKLKLMNPMNPRSRSTUV SIDE 111112222211111222221111122222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 1 step 77 000000000100001000010111100001 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEDEFHJFHJKLKLMNPMNPRSRSTUV SIDE 111112222211111222221111122222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 1000 step 78 000000000100001000011000100001 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEDEFHJFHJKLKLMNPMNPRSRSTUV SIDE 111112222211111222221111122222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 1 step 79 000000000100001000011001100001 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEDEFHJFHJKLKLMNPMNPRSRSTUV SIDE 111112222211111222221111122222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 10 step 80 000000000100001000011010100001 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEDEFHJFHJKLKLMNPMNPRSRSTUV SIDE 111112222211111222221111122222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 1 step 81 000000000100001000011011100001 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEDEFHJFHJKLKLMNPMNPRSRSTUV SIDE 111112222211111222221111122222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 100 step 82 000000000100001000011100100001 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEDEFHJFHJKLKLMNPMNPRSRSTUV SIDE 111112222211111222221111122222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 1 step 83 000000000100001000011101100001 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEDEFHJFHJKLKLMNPMNPRSRSTUV SIDE 111112222211111222221111122222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 10 step 84 000000000100001000011110100001 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEDEFHJFHJKLKLMNPMNPRSRSTUV SIDE 111112222211111222221111122222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 10 step 85 000000000100001000011111000001 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEDEFHJFHJKLKLMNPMNPRSRSTUV SIDE 111112222211111222221111122222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 00001 step 86 000000000100001000010000100001 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEDEFHJFHJKLKLMNPMNPRSRSTUV SIDE 111112222211111222221111122222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: step 87 000000000100001000010000100001 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEDEFHJFHJKLKLMNPMNPRSRSTUV SIDE 111112222211111222221111122222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 1 step 88 000000000100001000010000100011 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEDEFHJFHJKLKLMNPMNPRSRSTUV SIDE 111112222211111222221111122222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 10 step 89 000000000100001000010000100101 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEDEFHJFHJKLKLMNPMNPRSRSTUV SIDE 111112222211111222221111122222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 1 step 90 000000000100001000010000100111 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEDEFHJFHJKLKLMNPMNPRSRSTUV SIDE 111112222211111222221111122222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 100 step 91 000000000100001000010000101001 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEDEFHJFHJKLKLMNPMNPRSRSTUV SIDE 111112222211111222221111122222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 1 step 92 000000000100001000010000101011 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEDEFHJFHJKLKLMNPMNPRSRSTUV SIDE 111112222211111222221111122222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 10 step 93 000000000100001000010000101101 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEDEFHJFHJKLKLMNPMNPRSRSTUV SIDE 111112222211111222221111122222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 1 step 94 000000000100001000010000101111 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEDEFHJFHJKLKLMNPMNPRSRSTUV SIDE 111112222211111222221111122222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 1000 step 95 000000000100001000010000110001 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEDEFHJFHJKLKLMNPMNPRSRSTUV SIDE 111112222211111222221111122222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 1 step 96 000000000100001000010000110011 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEDEFHJFHJKLKLMNPMNPRSRSTUV SIDE 111112222211111222221111122222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 10 step 97 000000000100001000010000110101 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEDEFHJFHJKLKLMNPMNPRSRSTUV SIDE 111112222211111222221111122222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 1 step 98 000000000100001000010000110111 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEDEFHJFHJKLKLMNPMNPRSRSTUV SIDE 111112222211111222221111122222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 100 step 99 000000000100001000010000111001 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEDEFHJFHJKLKLMNPMNPRSRSTUV SIDE 111112222211111222221111122222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 1 step 100 000000000100001000010000111011 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEDEFHJFHJKLKLMNPMNPRSRSTUV SIDE 111112222211111222221111122222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 10 step 101 000000000100001000010000111101 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEDEFHJFHJKLKLMNPMNPRSRSTUV SIDE 111112222211111222221111122222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 10 step 102 000000000100001000010000111110 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEDEFHJFHJKLKLMNPMNPRSRSTUV SIDE 111112222211111222221111122222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 00001 step 103 000000000100001000010000100001 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEDEFHJFHJKLKLMNPMNPRSRSTUV SIDE 111112222211111222221111122222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: step 104 000000000100001000010000100001 fail ^ step 105 111101111011110111101111011110 SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEDEFHJFHJKLKLMNPMNPRSRSTUV SIDE 111112222211111222221111122222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 0000 step 106 000001111011110111101111011110 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEDEFHJFHJKLKLMNPMNPRSRSTUV SIDE 111112222211111222221111122222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 1 step 107 000101111011110111101111011110 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEDEFHJFHJKLKLMNPMNPRSRSTUV SIDE 111112222211111222221111122222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 10 step 108 001001111011110111101111011110 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEDEFHJFHJKLKLMNPMNPRSRSTUV SIDE 111112222211111222221111122222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 1 step 109 001101111011110111101111011110 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEDEFHJFHJKLKLMNPMNPRSRSTUV SIDE 111112222211111222221111122222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 100 step 110 010001111011110111101111011110 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEDEFHJFHJKLKLMNPMNPRSRSTUV SIDE 111112222211111222221111122222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 1 step 111 010101111011110111101111011110 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEDEFHJFHJKLKLMNPMNPRSRSTUV SIDE 111112222211111222221111122222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 10 step 112 011001111011110111101111011110 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEDEFHJFHJKLKLMNPMNPRSRSTUV SIDE 111112222211111222221111122222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 1 step 113 011101111011110111101111011110 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEDEFHJFHJKLKLMNPMNPRSRSTUV SIDE 111112222211111222221111122222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 1000 step 114 100001111011110111101111011110 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEDEFHJFHJKLKLMNPMNPRSRSTUV SIDE 111112222211111222221111122222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 1 step 115 100101111011110111101111011110 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEDEFHJFHJKLKLMNPMNPRSRSTUV SIDE 111112222211111222221111122222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 10 step 116 101001111011110111101111011110 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEDEFHJFHJKLKLMNPMNPRSRSTUV SIDE 111112222211111222221111122222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 1 step 117 101101111011110111101111011110 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEDEFHJFHJKLKLMNPMNPRSRSTUV SIDE 111112222211111222221111122222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 100 step 118 110001111011110111101111011110 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEDEFHJFHJKLKLMNPMNPRSRSTUV SIDE 111112222211111222221111122222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 1 step 119 110101111011110111101111011110 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEDEFHJFHJKLKLMNPMNPRSRSTUV SIDE 111112222211111222221111122222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 10 step 120 111001111011110111101111011110 fail ^ step 121 111101111011110111101111011110 step 122 111100000111110111101111011110 step 123 111100001111110111101111011110 step 124 111100010111110111101111011110 step 125 111100011111110111101111011110 step 126 111100100111110111101111011110 step 127 111100101111110111101111011110 step 128 111100110111110111101111011110 step 129 111100111111110111101111011110 step 130 111101000111110111101111011110 step 131 111101001111110111101111011110 step 132 111101010111110111101111011110 step 133 111101011111110111101111011110 step 134 111101100111110111101111011110 step 135 111101101111110111101111011110 step 136 111101110111110111101111011110 step 137 111101111011110111101111011110 step 138 111101111000001111101111011110 step 139 111101111000011111101111011110 step 140 111101111000101111101111011110 step 141 111101111000111111101111011110 step 142 111101111001001111101111011110 step 143 111101111001011111101111011110 step 144 111101111001101111101111011110 step 145 111101111001111111101111011110 step 146 111101111010001111101111011110 step 147 111101111010011111101111011110 step 148 111101111010101111101111011110 step 149 111101111010111111101111011110 step 150 111101111011001111101111011110 step 151 111101111011011111101111011110 step 152 111101111011101111101111011110 step 153 111101111011110111101111011110 step 154 111101111011110000011111011110 step 155 111101111011110000111111011110 step 156 111101111011110001011111011110 step 157 111101111011110001111111011110 step 158 111101111011110010011111011110 step 159 111101111011110010111111011110 step 160 111101111011110011011111011110 step 161 111101111011110011111111011110 step 162 111101111011110100011111011110 step 163 111101111011110100111111011110 step 164 111101111011110101011111011110 step 165 111101111011110101111111011110 step 166 111101111011110110011111011110 step 167 111101111011110110111111011110 step 168 111101111011110111011111011110 step 169 111101111011110111101111011110 step 170 111101111011110111100000111110 step 171 111101111011110111100001111110 step 172 111101111011110111100010111110 step 173 111101111011110111100011111110 step 174 111101111011110111100100111110 step 175 111101111011110111100101111110 step 176 111101111011110111100110111110 step 177 111101111011110111100111111110 step 178 111101111011110111101000111110 step 179 111101111011110111101001111110 step 180 111101111011110111101010111110 step 181 111101111011110111101011111110 step 182 111101111011110111101100111110 step 183 111101111011110111101101111110 step 184 111101111011110111101110111110 step 185 111101111011110111101111011110 step 186 111101111011110111101111000001 step 187 111101111011110111101111000011 step 188 111101111011110111101111000101 step 189 111101111011110111101111000111 step 190 111101111011110111101111001001 step 191 111101111011110111101111001011 step 192 111101111011110111101111001101 step 193 111101111011110111101111001111 step 194 111101111011110111101111010001 step 195 111101111011110111101111010011 step 196 111101111011110111101111010101 step 197 111101111011110111101111010111 step 198 111101111011110111101111011001 step 199 111101111011110111101111011011 step 200 111101111011110111101111011101 step 201 111101111011110111101111011110 step 202 111101111011110111101111011110 test 21: *** FAIL *************************** 118 steps failed SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEDEFHJFHJKLKLMNPMNPRSRSTUV SIDE 111112222211111222221111122222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO this fail O all fails O was hi 1111 1111111111111111111111111 rising ^^^^ ^^^^^^^^^^^^^^^^^^^^^^^^^ falling vvvv vvvvvvvvvvvvvvvvvvvvvvvvv was lo 000000000000000000000000000000 total fails 21, total passes 0 space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn on comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEDEFHJFHJKLKLMNPMNPRSRSTUV SIDE 111112222211111222221111122222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 0000 0000100001000010000100001 step 1 000000000100001000010000100001 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEDEFHJFHJKLKLMNPMNPRSRSTUV SIDE 111112222211111222221111122222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: step 2 000000000100001000010000100001 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEDEFHJFHJKLKLMNPMNPRSRSTUV SIDE 111112222211111222221111122222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 1 step 3 000100000100001000010000100001 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEDEFHJFHJKLKLMNPMNPRSRSTUV SIDE 111112222211111222221111122222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 10 step 4 001000000100001000010000100001 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEDEFHJFHJKLKLMNPMNPRSRSTUV SIDE 111112222211111222221111122222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 1 step 5 001100000100001000010000100001 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEDEFHJFHJKLKLMNPMNPRSRSTUV SIDE 111112222211111222221111122222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 100 step 6 010000000100001000010000100001 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEDEFHJFHJKLKLMNPMNPRSRSTUV SIDE 111112222211111222221111122222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 1 step 7 010100000100001000010000100001 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEDEFHJFHJKLKLMNPMNPRSRSTUV SIDE 111112222211111222221111122222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 10 step 8 011000000100001000010000100001 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEDEFHJFHJKLKLMNPMNPRSRSTUV SIDE 111112222211111222221111122222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 1 step 9 011100000100001000010000100001 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEDEFHJFHJKLKLMNPMNPRSRSTUV SIDE 111112222211111222221111122222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 1000 step 10 100000000100001000010000100001 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEDEFHJFHJKLKLMNPMNPRSRSTUV SIDE 111112222211111222221111122222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 1 step 11 100100000100001000010000100001 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEDEFHJFHJKLKLMNPMNPRSRSTUV SIDE 111112222211111222221111122222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 10 step 12 101000000100001000010000100001 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEDEFHJFHJKLKLMNPMNPRSRSTUV SIDE 111112222211111222221111122222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 1 step 13 101100000100001000010000100001 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEDEFHJFHJKLKLMNPMNPRSRSTUV SIDE 111112222211111222221111122222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 100 step 14 110000000100001000010000100001 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEDEFHJFHJKLKLMNPMNPRSRSTUV SIDE 111112222211111222221111122222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 1 step 15 110100000100001000010000100001 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEDEFHJFHJKLKLMNPMNPRSRSTUV SIDE 111112222211111222221111122222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 10 step 16 111000000100001000010000100001 fail ^ step 17 111100000100001000010000100001 SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEDEFHJFHJKLKLMNPMNPRSRSTUV SIDE 111112222211111222221111122222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 0000 step 18 000000000100001000010000100001 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEDEFHJFHJKLKLMNPMNPRSRSTUV SIDE 111112222211111222221111122222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: step 19 000000000100001000010000100001 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEDEFHJFHJKLKLMNPMNPRSRSTUV SIDE 111112222211111222221111122222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 1 step 20 000000001100001000010000100001 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEDEFHJFHJKLKLMNPMNPRSRSTUV SIDE 111112222211111222221111122222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 10 step 21 000000010100001000010000100001 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEDEFHJFHJKLKLMNPMNPRSRSTUV SIDE 111112222211111222221111122222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 1 step 22 000000011100001000010000100001 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEDEFHJFHJKLKLMNPMNPRSRSTUV SIDE 111112222211111222221111122222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 100 step 23 000000100100001000010000100001 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEDEFHJFHJKLKLMNPMNPRSRSTUV SIDE 111112222211111222221111122222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 1 step 24 000000101100001000010000100001 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEDEFHJFHJKLKLMNPMNPRSRSTUV SIDE 111112222211111222221111122222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 10 step 25 000000110100001000010000100001 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEDEFHJFHJKLKLMNPMNPRSRSTUV SIDE 111112222211111222221111122222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 1 step 26 000000111100001000010000100001 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEDEFHJFHJKLKLMNPMNPRSRSTUV SIDE 111112222211111222221111122222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 1000 step 27 000001000100001000010000100001 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEDEFHJFHJKLKLMNPMNPRSRSTUV SIDE 111112222211111222221111122222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 1 step 28 000001001100001000010000100001 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEDEFHJFHJKLKLMNPMNPRSRSTUV SIDE 111112222211111222221111122222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 10 step 29 000001010100001000010000100001 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEDEFHJFHJKLKLMNPMNPRSRSTUV SIDE 111112222211111222221111122222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 1 step 30 000001011100001000010000100001 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEDEFHJFHJKLKLMNPMNPRSRSTUV SIDE 111112222211111222221111122222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 100 step 31 000001100100001000010000100001 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEDEFHJFHJKLKLMNPMNPRSRSTUV SIDE 111112222211111222221111122222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 1 step 32 000001101100001000010000100001 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEDEFHJFHJKLKLMNPMNPRSRSTUV SIDE 111112222211111222221111122222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 10 step 33 000001110100001000010000100001 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEDEFHJFHJKLKLMNPMNPRSRSTUV SIDE 111112222211111222221111122222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 10 step 34 000001111000001000010000100001 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEDEFHJFHJKLKLMNPMNPRSRSTUV SIDE 111112222211111222221111122222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 00001 step 35 000000000100001000010000100001 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEDEFHJFHJKLKLMNPMNPRSRSTUV SIDE 111112222211111222221111122222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: step 36 000000000100001000010000100001 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEDEFHJFHJKLKLMNPMNPRSRSTUV SIDE 111112222211111222221111122222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 1 step 37 000000000100011000010000100001 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEDEFHJFHJKLKLMNPMNPRSRSTUV SIDE 111112222211111222221111122222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 10 step 38 000000000100101000010000100001 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEDEFHJFHJKLKLMNPMNPRSRSTUV SIDE 111112222211111222221111122222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 1 step 39 000000000100111000010000100001 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEDEFHJFHJKLKLMNPMNPRSRSTUV SIDE 111112222211111222221111122222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 100 step 40 000000000101001000010000100001 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEDEFHJFHJKLKLMNPMNPRSRSTUV SIDE 111112222211111222221111122222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 1 step 41 000000000101011000010000100001 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEDEFHJFHJKLKLMNPMNPRSRSTUV SIDE 111112222211111222221111122222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 10 step 42 000000000101101000010000100001 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEDEFHJFHJKLKLMNPMNPRSRSTUV SIDE 111112222211111222221111122222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 1 step 43 000000000101111000010000100001 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEDEFHJFHJKLKLMNPMNPRSRSTUV SIDE 111112222211111222221111122222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 1000 step 44 000000000110001000010000100001 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEDEFHJFHJKLKLMNPMNPRSRSTUV SIDE 111112222211111222221111122222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 1 step 45 000000000110011000010000100001 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEDEFHJFHJKLKLMNPMNPRSRSTUV SIDE 111112222211111222221111122222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 10 step 46 000000000110101000010000100001 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEDEFHJFHJKLKLMNPMNPRSRSTUV SIDE 111112222211111222221111122222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 1 step 47 000000000110111000010000100001 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEDEFHJFHJKLKLMNPMNPRSRSTUV SIDE 111112222211111222221111122222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 100 step 48 000000000111001000010000100001 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEDEFHJFHJKLKLMNPMNPRSRSTUV SIDE 111112222211111222221111122222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 1 step 49 000000000111011000010000100001 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEDEFHJFHJKLKLMNPMNPRSRSTUV SIDE 111112222211111222221111122222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 10 step 50 000000000111101000010000100001 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEDEFHJFHJKLKLMNPMNPRSRSTUV SIDE 111112222211111222221111122222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 10 step 51 000000000111110000010000100001 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEDEFHJFHJKLKLMNPMNPRSRSTUV SIDE 111112222211111222221111122222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 00001 step 52 000000000100001000010000100001 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEDEFHJFHJKLKLMNPMNPRSRSTUV SIDE 111112222211111222221111122222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: step 53 000000000100001000010000100001 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEDEFHJFHJKLKLMNPMNPRSRSTUV SIDE 111112222211111222221111122222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 1 step 54 000000000100001000110000100001 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEDEFHJFHJKLKLMNPMNPRSRSTUV SIDE 111112222211111222221111122222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 10 step 55 000000000100001001010000100001 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEDEFHJFHJKLKLMNPMNPRSRSTUV SIDE 111112222211111222221111122222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 1 step 56 000000000100001001110000100001 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEDEFHJFHJKLKLMNPMNPRSRSTUV SIDE 111112222211111222221111122222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 100 step 57 000000000100001010010000100001 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEDEFHJFHJKLKLMNPMNPRSRSTUV SIDE 111112222211111222221111122222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 1 step 58 000000000100001010110000100001 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEDEFHJFHJKLKLMNPMNPRSRSTUV SIDE 111112222211111222221111122222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 10 step 59 000000000100001011010000100001 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEDEFHJFHJKLKLMNPMNPRSRSTUV SIDE 111112222211111222221111122222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 1 step 60 000000000100001011110000100001 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEDEFHJFHJKLKLMNPMNPRSRSTUV SIDE 111112222211111222221111122222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 1000 step 61 000000000100001100010000100001 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEDEFHJFHJKLKLMNPMNPRSRSTUV SIDE 111112222211111222221111122222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 1 step 62 000000000100001100110000100001 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEDEFHJFHJKLKLMNPMNPRSRSTUV SIDE 111112222211111222221111122222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 10 step 63 000000000100001101010000100001 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEDEFHJFHJKLKLMNPMNPRSRSTUV SIDE 111112222211111222221111122222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 1 step 64 000000000100001101110000100001 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEDEFHJFHJKLKLMNPMNPRSRSTUV SIDE 111112222211111222221111122222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 100 step 65 000000000100001110010000100001 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEDEFHJFHJKLKLMNPMNPRSRSTUV SIDE 111112222211111222221111122222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 1 step 66 000000000100001110110000100001 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEDEFHJFHJKLKLMNPMNPRSRSTUV SIDE 111112222211111222221111122222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 10 step 67 000000000100001111010000100001 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEDEFHJFHJKLKLMNPMNPRSRSTUV SIDE 111112222211111222221111122222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 10 step 68 000000000100001111100000100001 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEDEFHJFHJKLKLMNPMNPRSRSTUV SIDE 111112222211111222221111122222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 00001 step 69 000000000100001000010000100001 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEDEFHJFHJKLKLMNPMNPRSRSTUV SIDE 111112222211111222221111122222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: step 70 000000000100001000010000100001 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEDEFHJFHJKLKLMNPMNPRSRSTUV SIDE 111112222211111222221111122222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 1 step 71 000000000100001000010001100001 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEDEFHJFHJKLKLMNPMNPRSRSTUV SIDE 111112222211111222221111122222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 10 step 72 000000000100001000010010100001 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEDEFHJFHJKLKLMNPMNPRSRSTUV SIDE 111112222211111222221111122222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 1 step 73 000000000100001000010011100001 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEDEFHJFHJKLKLMNPMNPRSRSTUV SIDE 111112222211111222221111122222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 100 step 74 000000000100001000010100100001 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEDEFHJFHJKLKLMNPMNPRSRSTUV SIDE 111112222211111222221111122222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 1 step 75 000000000100001000010101100001 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEDEFHJFHJKLKLMNPMNPRSRSTUV SIDE 111112222211111222221111122222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 10 step 76 000000000100001000010110100001 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEDEFHJFHJKLKLMNPMNPRSRSTUV SIDE 111112222211111222221111122222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 1 step 77 000000000100001000010111100001 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEDEFHJFHJKLKLMNPMNPRSRSTUV SIDE 111112222211111222221111122222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 1000 step 78 000000000100001000011000100001 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEDEFHJFHJKLKLMNPMNPRSRSTUV SIDE 111112222211111222221111122222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 1 step 79 000000000100001000011001100001 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEDEFHJFHJKLKLMNPMNPRSRSTUV SIDE 111112222211111222221111122222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 10 step 80 000000000100001000011010100001 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEDEFHJFHJKLKLMNPMNPRSRSTUV SIDE 111112222211111222221111122222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 1 step 81 000000000100001000011011100001 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEDEFHJFHJKLKLMNPMNPRSRSTUV SIDE 111112222211111222221111122222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 100 step 82 000000000100001000011100100001 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEDEFHJFHJKLKLMNPMNPRSRSTUV SIDE 111112222211111222221111122222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 1 step 83 000000000100001000011101100001 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEDEFHJFHJKLKLMNPMNPRSRSTUV SIDE 111112222211111222221111122222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 10 step 84 000000000100001000011110100001 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEDEFHJFHJKLKLMNPMNPRSRSTUV SIDE 111112222211111222221111122222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 10 step 85 000000000100001000011111000001 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEDEFHJFHJKLKLMNPMNPRSRSTUV SIDE 111112222211111222221111122222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 00001 step 86 000000000100001000010000100001 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEDEFHJFHJKLKLMNPMNPRSRSTUV SIDE 111112222211111222221111122222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: step 87 000000000100001000010000100001 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEDEFHJFHJKLKLMNPMNPRSRSTUV SIDE 111112222211111222221111122222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 1 step 88 000000000100001000010000100011 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEDEFHJFHJKLKLMNPMNPRSRSTUV SIDE 111112222211111222221111122222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 10 step 89 000000000100001000010000100101 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEDEFHJFHJKLKLMNPMNPRSRSTUV SIDE 111112222211111222221111122222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 1 step 90 000000000100001000010000100111 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEDEFHJFHJKLKLMNPMNPRSRSTUV SIDE 111112222211111222221111122222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 100 step 91 000000000100001000010000101001 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEDEFHJFHJKLKLMNPMNPRSRSTUV SIDE 111112222211111222221111122222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 1 step 92 000000000100001000010000101011 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEDEFHJFHJKLKLMNPMNPRSRSTUV SIDE 111112222211111222221111122222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 10 step 93 000000000100001000010000101101 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEDEFHJFHJKLKLMNPMNPRSRSTUV SIDE 111112222211111222221111122222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 1 step 94 000000000100001000010000101111 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEDEFHJFHJKLKLMNPMNPRSRSTUV SIDE 111112222211111222221111122222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 1000 step 95 000000000100001000010000110001 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEDEFHJFHJKLKLMNPMNPRSRSTUV SIDE 111112222211111222221111122222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 1 step 96 000000000100001000010000110011 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEDEFHJFHJKLKLMNPMNPRSRSTUV SIDE 111112222211111222221111122222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 10 step 97 000000000100001000010000110101 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEDEFHJFHJKLKLMNPMNPRSRSTUV SIDE 111112222211111222221111122222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 1 step 98 000000000100001000010000110111 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEDEFHJFHJKLKLMNPMNPRSRSTUV SIDE 111112222211111222221111122222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 100 step 99 000000000100001000010000111001 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEDEFHJFHJKLKLMNPMNPRSRSTUV SIDE 111112222211111222221111122222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 1 step 100 000000000100001000010000111011 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEDEFHJFHJKLKLMNPMNPRSRSTUV SIDE 111112222211111222221111122222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 10 step 101 000000000100001000010000111101 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEDEFHJFHJKLKLMNPMNPRSRSTUV SIDE 111112222211111222221111122222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 10 step 102 000000000100001000010000111110 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEDEFHJFHJKLKLMNPMNPRSRSTUV SIDE 111112222211111222221111122222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 00001 step 103 000000000100001000010000100001 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEDEFHJFHJKLKLMNPMNPRSRSTUV SIDE 111112222211111222221111122222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: step 104 000000000100001000010000100001 fail ^ step 105 111101111011110111101111011110 SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEDEFHJFHJKLKLMNPMNPRSRSTUV SIDE 111112222211111222221111122222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 0000 step 106 000001111011110111101111011110 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEDEFHJFHJKLKLMNPMNPRSRSTUV SIDE 111112222211111222221111122222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 1 step 107 000101111011110111101111011110 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEDEFHJFHJKLKLMNPMNPRSRSTUV SIDE 111112222211111222221111122222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 10 step 108 001001111011110111101111011110 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEDEFHJFHJKLKLMNPMNPRSRSTUV SIDE 111112222211111222221111122222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 1 step 109 001101111011110111101111011110 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEDEFHJFHJKLKLMNPMNPRSRSTUV SIDE 111112222211111222221111122222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 100 step 110 010001111011110111101111011110 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEDEFHJFHJKLKLMNPMNPRSRSTUV SIDE 111112222211111222221111122222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 1 step 111 010101111011110111101111011110 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEDEFHJFHJKLKLMNPMNPRSRSTUV SIDE 111112222211111222221111122222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 10 step 112 011001111011110111101111011110 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEDEFHJFHJKLKLMNPMNPRSRSTUV SIDE 111112222211111222221111122222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 1 step 113 011101111011110111101111011110 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEDEFHJFHJKLKLMNPMNPRSRSTUV SIDE 111112222211111222221111122222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 1000 step 114 100001111011110111101111011110 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEDEFHJFHJKLKLMNPMNPRSRSTUV SIDE 111112222211111222221111122222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 1 step 115 100101111011110111101111011110 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEDEFHJFHJKLKLMNPMNPRSRSTUV SIDE 111112222211111222221111122222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 10 step 116 101001111011110111101111011110 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEDEFHJFHJKLKLMNPMNPRSRSTUV SIDE 111112222211111222221111122222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 1 step 117 101101111011110111101111011110 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEDEFHJFHJKLKLMNPMNPRSRSTUV SIDE 111112222211111222221111122222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 100 step 118 110001111011110111101111011110 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEDEFHJFHJKLKLMNPMNPRSRSTUV SIDE 111112222211111222221111122222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 1 step 119 110101111011110111101111011110 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEDEFHJFHJKLKLMNPMNPRSRSTUV SIDE 111112222211111222221111122222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 10 step 120 111001111011110111101111011110 fail ^ step 121 111101111011110111101111011110 step 122 111100000111110111101111011110 step 123 111100001111110111101111011110 step 124 111100010111110111101111011110 step 125 111100011111110111101111011110 step 126 111100100111110111101111011110 step 127 111100101111110111101111011110 step 128 111100110111110111101111011110 step 129 111100111111110111101111011110 step 130 111101000111110111101111011110 step 131 111101001111110111101111011110 step 132 111101010111110111101111011110 step 133 111101011111110111101111011110 step 134 111101100111110111101111011110 step 135 111101101111110111101111011110 step 136 111101110111110111101111011110 step 137 111101111011110111101111011110 step 138 111101111000001111101111011110 step 139 111101111000011111101111011110 step 140 111101111000101111101111011110 step 141 111101111000111111101111011110 step 142 111101111001001111101111011110 step 143 111101111001011111101111011110 step 144 111101111001101111101111011110 step 145 111101111001111111101111011110 step 146 111101111010001111101111011110 step 147 111101111010011111101111011110 step 148 111101111010101111101111011110 step 149 111101111010111111101111011110 step 150 111101111011001111101111011110 step 151 111101111011011111101111011110 step 152 111101111011101111101111011110 step 153 111101111011110111101111011110 step 154 111101111011110000011111011110 step 155 111101111011110000111111011110 step 156 111101111011110001011111011110 step 157 111101111011110001111111011110 step 158 111101111011110010011111011110 step 159 111101111011110010111111011110 step 160 111101111011110011011111011110 step 161 111101111011110011111111011110 step 162 111101111011110100011111011110 step 163 111101111011110100111111011110 step 164 111101111011110101011111011110 step 165 111101111011110101111111011110 step 166 111101111011110110011111011110 step 167 111101111011110110111111011110 step 168 111101111011110111011111011110 step 169 111101111011110111101111011110 step 170 111101111011110111100000111110 step 171 111101111011110111100001111110 step 172 111101111011110111100010111110 step 173 111101111011110111100011111110 step 174 111101111011110111100100111110 step 175 111101111011110111100101111110 step 176 111101111011110111100110111110 step 177 111101111011110111100111111110 step 178 111101111011110111101000111110 step 179 111101111011110111101001111110 step 180 111101111011110111101010111110 step 181 111101111011110111101011111110 step 182 111101111011110111101100111110 step 183 111101111011110111101101111110 step 184 111101111011110111101110111110 step 185 111101111011110111101111011110 step 186 111101111011110111101111000001 step 187 111101111011110111101111000011 step 188 111101111011110111101111000101 step 189 111101111011110111101111000111 step 190 111101111011110111101111001001 step 191 111101111011110111101111001011 step 192 111101111011110111101111001101 step 193 111101111011110111101111001111 step 194 111101111011110111101111010001 step 195 111101111011110111101111010011 step 196 111101111011110111101111010101 step 197 111101111011110111101111010111 step 198 111101111011110111101111011001 step 199 111101111011110111101111011011 step 200 111101111011110111101111011101 step 201 111101111011110111101111011110 step 202 111101111011110111101111011110 test 22: *** FAIL *************************** 118 steps failed SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEDEFHJFHJKLKLMNPMNPRSRSTUV SIDE 111112222211111222221111122222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO this fail O all fails O was hi 1111 1111111111111111111111111 rising ^^^^ ^^^^^^^^^^^^^^^^^^^^^^^^^ falling vvvv vvvvvvvvvvvvvvvvvvvvvvvvv was lo 000000000000000000000000000000 total fails 22, total passes 0 space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn on comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEDEFHJFHJKLKLMNPMNPRSRSTUV SIDE 111112222211111222221111122222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 0000 0000100001000010000100001 step 1 000000000100001000010000100001 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEDEFHJFHJKLKLMNPMNPRSRSTUV SIDE 111112222211111222221111122222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: step 2 000000000100001000010000100001 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEDEFHJFHJKLKLMNPMNPRSRSTUV SIDE 111112222211111222221111122222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 1 step 3 000100000100001000010000100001 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEDEFHJFHJKLKLMNPMNPRSRSTUV SIDE 111112222211111222221111122222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 10 step 4 001000000100001000010000100001 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEDEFHJFHJKLKLMNPMNPRSRSTUV SIDE 111112222211111222221111122222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 1 step 5 001100000100001000010000100001 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEDEFHJFHJKLKLMNPMNPRSRSTUV SIDE 111112222211111222221111122222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 100 step 6 010000000100001000010000100001 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEDEFHJFHJKLKLMNPMNPRSRSTUV SIDE 111112222211111222221111122222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 1 step 7 010100000100001000010000100001 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEDEFHJFHJKLKLMNPMNPRSRSTUV SIDE 111112222211111222221111122222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 10 step 8 011000000100001000010000100001 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEDEFHJFHJKLKLMNPMNPRSRSTUV SIDE 111112222211111222221111122222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 1 step 9 011100000100001000010000100001 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEDEFHJFHJKLKLMNPMNPRSRSTUV SIDE 111112222211111222221111122222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 1000 step 10 100000000100001000010000100001 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEDEFHJFHJKLKLMNPMNPRSRSTUV SIDE 111112222211111222221111122222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 1 step 11 100100000100001000010000100001 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEDEFHJFHJKLKLMNPMNPRSRSTUV SIDE 111112222211111222221111122222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 10 step 12 101000000100001000010000100001 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEDEFHJFHJKLKLMNPMNPRSRSTUV SIDE 111112222211111222221111122222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 1 step 13 101100000100001000010000100001 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEDEFHJFHJKLKLMNPMNPRSRSTUV SIDE 111112222211111222221111122222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 100 step 14 110000000100001000010000100001 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEDEFHJFHJKLKLMNPMNPRSRSTUV SIDE 111112222211111222221111122222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 1 step 15 110100000100001000010000100001 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEDEFHJFHJKLKLMNPMNPRSRSTUV SIDE 111112222211111222221111122222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 10 step 16 111000000100001000010000100001 fail ^ step 17 111100000100001000010000100001 SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEDEFHJFHJKLKLMNPMNPRSRSTUV SIDE 111112222211111222221111122222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 0000 step 18 000000000100001000010000100001 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEDEFHJFHJKLKLMNPMNPRSRSTUV SIDE 111112222211111222221111122222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: step 19 000000000100001000010000100001 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEDEFHJFHJKLKLMNPMNPRSRSTUV SIDE 111112222211111222221111122222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 1 step 20 000000001100001000010000100001 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEDEFHJFHJKLKLMNPMNPRSRSTUV SIDE 111112222211111222221111122222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 10 step 21 000000010100001000010000100001 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEDEFHJFHJKLKLMNPMNPRSRSTUV SIDE 111112222211111222221111122222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 1 step 22 000000011100001000010000100001 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEDEFHJFHJKLKLMNPMNPRSRSTUV SIDE 111112222211111222221111122222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 100 step 23 000000100100001000010000100001 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEDEFHJFHJKLKLMNPMNPRSRSTUV SIDE 111112222211111222221111122222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 1 step 24 000000101100001000010000100001 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEDEFHJFHJKLKLMNPMNPRSRSTUV SIDE 111112222211111222221111122222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 10 step 25 000000110100001000010000100001 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEDEFHJFHJKLKLMNPMNPRSRSTUV SIDE 111112222211111222221111122222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 1 step 26 000000111100001000010000100001 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEDEFHJFHJKLKLMNPMNPRSRSTUV SIDE 111112222211111222221111122222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 1000 step 27 000001000100001000010000100001 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEDEFHJFHJKLKLMNPMNPRSRSTUV SIDE 111112222211111222221111122222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 1 step 28 000001001100001000010000100001 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEDEFHJFHJKLKLMNPMNPRSRSTUV SIDE 111112222211111222221111122222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 10 step 29 000001010100001000010000100001 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEDEFHJFHJKLKLMNPMNPRSRSTUV SIDE 111112222211111222221111122222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 1 step 30 000001011100001000010000100001 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEDEFHJFHJKLKLMNPMNPRSRSTUV SIDE 111112222211111222221111122222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 100 step 31 000001100100001000010000100001 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEDEFHJFHJKLKLMNPMNPRSRSTUV SIDE 111112222211111222221111122222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 1 step 32 000001101100001000010000100001 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEDEFHJFHJKLKLMNPMNPRSRSTUV SIDE 111112222211111222221111122222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 10 step 33 000001110100001000010000100001 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEDEFHJFHJKLKLMNPMNPRSRSTUV SIDE 111112222211111222221111122222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 10 step 34 000001111000001000010000100001 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEDEFHJFHJKLKLMNPMNPRSRSTUV SIDE 111112222211111222221111122222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 00001 step 35 000000000100001000010000100001 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEDEFHJFHJKLKLMNPMNPRSRSTUV SIDE 111112222211111222221111122222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: step 36 000000000100001000010000100001 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEDEFHJFHJKLKLMNPMNPRSRSTUV SIDE 111112222211111222221111122222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 1 step 37 000000000100011000010000100001 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEDEFHJFHJKLKLMNPMNPRSRSTUV SIDE 111112222211111222221111122222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 10 step 38 000000000100101000010000100001 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEDEFHJFHJKLKLMNPMNPRSRSTUV SIDE 111112222211111222221111122222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 1 step 39 000000000100111000010000100001 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEDEFHJFHJKLKLMNPMNPRSRSTUV SIDE 111112222211111222221111122222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 100 step 40 000000000101001000010000100001 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEDEFHJFHJKLKLMNPMNPRSRSTUV SIDE 111112222211111222221111122222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 1 step 41 000000000101011000010000100001 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEDEFHJFHJKLKLMNPMNPRSRSTUV SIDE 111112222211111222221111122222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 10 step 42 000000000101101000010000100001 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEDEFHJFHJKLKLMNPMNPRSRSTUV SIDE 111112222211111222221111122222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 1 step 43 000000000101111000010000100001 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEDEFHJFHJKLKLMNPMNPRSRSTUV SIDE 111112222211111222221111122222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 1000 step 44 000000000110001000010000100001 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEDEFHJFHJKLKLMNPMNPRSRSTUV SIDE 111112222211111222221111122222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 1 step 45 000000000110011000010000100001 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEDEFHJFHJKLKLMNPMNPRSRSTUV SIDE 111112222211111222221111122222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 10 step 46 000000000110101000010000100001 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEDEFHJFHJKLKLMNPMNPRSRSTUV SIDE 111112222211111222221111122222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 1 step 47 000000000110111000010000100001 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEDEFHJFHJKLKLMNPMNPRSRSTUV SIDE 111112222211111222221111122222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 100 step 48 000000000111001000010000100001 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEDEFHJFHJKLKLMNPMNPRSRSTUV SIDE 111112222211111222221111122222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 1 step 49 000000000111011000010000100001 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEDEFHJFHJKLKLMNPMNPRSRSTUV SIDE 111112222211111222221111122222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 10 step 50 000000000111101000010000100001 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEDEFHJFHJKLKLMNPMNPRSRSTUV SIDE 111112222211111222221111122222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 10 step 51 000000000111110000010000100001 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEDEFHJFHJKLKLMNPMNPRSRSTUV SIDE 111112222211111222221111122222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 00001 step 52 000000000100001000010000100001 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEDEFHJFHJKLKLMNPMNPRSRSTUV SIDE 111112222211111222221111122222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: step 53 000000000100001000010000100001 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEDEFHJFHJKLKLMNPMNPRSRSTUV SIDE 111112222211111222221111122222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 1 step 54 000000000100001000110000100001 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEDEFHJFHJKLKLMNPMNPRSRSTUV SIDE 111112222211111222221111122222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 10 step 55 000000000100001001010000100001 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEDEFHJFHJKLKLMNPMNPRSRSTUV SIDE 111112222211111222221111122222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 1 step 56 000000000100001001110000100001 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEDEFHJFHJKLKLMNPMNPRSRSTUV SIDE 111112222211111222221111122222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 100 step 57 000000000100001010010000100001 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEDEFHJFHJKLKLMNPMNPRSRSTUV SIDE 111112222211111222221111122222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 1 step 58 000000000100001010110000100001 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEDEFHJFHJKLKLMNPMNPRSRSTUV SIDE 111112222211111222221111122222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 10 step 59 000000000100001011010000100001 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEDEFHJFHJKLKLMNPMNPRSRSTUV SIDE 111112222211111222221111122222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 1 step 60 000000000100001011110000100001 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEDEFHJFHJKLKLMNPMNPRSRSTUV SIDE 111112222211111222221111122222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 1000 step 61 000000000100001100010000100001 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEDEFHJFHJKLKLMNPMNPRSRSTUV SIDE 111112222211111222221111122222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 1 step 62 000000000100001100110000100001 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEDEFHJFHJKLKLMNPMNPRSRSTUV SIDE 111112222211111222221111122222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 10 step 63 000000000100001101010000100001 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEDEFHJFHJKLKLMNPMNPRSRSTUV SIDE 111112222211111222221111122222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 1 step 64 000000000100001101110000100001 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEDEFHJFHJKLKLMNPMNPRSRSTUV SIDE 111112222211111222221111122222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 100 step 65 000000000100001110010000100001 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEDEFHJFHJKLKLMNPMNPRSRSTUV SIDE 111112222211111222221111122222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 1 step 66 000000000100001110110000100001 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEDEFHJFHJKLKLMNPMNPRSRSTUV SIDE 111112222211111222221111122222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 10 step 67 000000000100001111010000100001 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEDEFHJFHJKLKLMNPMNPRSRSTUV SIDE 111112222211111222221111122222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 10 step 68 000000000100001111100000100001 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEDEFHJFHJKLKLMNPMNPRSRSTUV SIDE 111112222211111222221111122222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 00001 step 69 000000000100001000010000100001 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEDEFHJFHJKLKLMNPMNPRSRSTUV SIDE 111112222211111222221111122222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: step 70 000000000100001000010000100001 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEDEFHJFHJKLKLMNPMNPRSRSTUV SIDE 111112222211111222221111122222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 1 step 71 000000000100001000010001100001 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEDEFHJFHJKLKLMNPMNPRSRSTUV SIDE 111112222211111222221111122222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 10 step 72 000000000100001000010010100001 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEDEFHJFHJKLKLMNPMNPRSRSTUV SIDE 111112222211111222221111122222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 1 step 73 000000000100001000010011100001 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEDEFHJFHJKLKLMNPMNPRSRSTUV SIDE 111112222211111222221111122222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 100 step 74 000000000100001000010100100001 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEDEFHJFHJKLKLMNPMNPRSRSTUV SIDE 111112222211111222221111122222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 1 step 75 000000000100001000010101100001 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEDEFHJFHJKLKLMNPMNPRSRSTUV SIDE 111112222211111222221111122222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 10 step 76 000000000100001000010110100001 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEDEFHJFHJKLKLMNPMNPRSRSTUV SIDE 111112222211111222221111122222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 1 step 77 000000000100001000010111100001 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEDEFHJFHJKLKLMNPMNPRSRSTUV SIDE 111112222211111222221111122222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 1000 step 78 000000000100001000011000100001 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEDEFHJFHJKLKLMNPMNPRSRSTUV SIDE 111112222211111222221111122222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 1 step 79 000000000100001000011001100001 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEDEFHJFHJKLKLMNPMNPRSRSTUV SIDE 111112222211111222221111122222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 10 step 80 000000000100001000011010100001 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEDEFHJFHJKLKLMNPMNPRSRSTUV SIDE 111112222211111222221111122222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 1 step 81 000000000100001000011011100001 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEDEFHJFHJKLKLMNPMNPRSRSTUV SIDE 111112222211111222221111122222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 100 step 82 000000000100001000011100100001 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEDEFHJFHJKLKLMNPMNPRSRSTUV SIDE 111112222211111222221111122222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 1 step 83 000000000100001000011101100001 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEDEFHJFHJKLKLMNPMNPRSRSTUV SIDE 111112222211111222221111122222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 10 step 84 000000000100001000011110100001 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEDEFHJFHJKLKLMNPMNPRSRSTUV SIDE 111112222211111222221111122222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 10 step 85 000000000100001000011111000001 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEDEFHJFHJKLKLMNPMNPRSRSTUV SIDE 111112222211111222221111122222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 00001 step 86 000000000100001000010000100001 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEDEFHJFHJKLKLMNPMNPRSRSTUV SIDE 111112222211111222221111122222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: step 87 000000000100001000010000100001 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEDEFHJFHJKLKLMNPMNPRSRSTUV SIDE 111112222211111222221111122222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 1 step 88 000000000100001000010000100011 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEDEFHJFHJKLKLMNPMNPRSRSTUV SIDE 111112222211111222221111122222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 10 step 89 000000000100001000010000100101 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEDEFHJFHJKLKLMNPMNPRSRSTUV SIDE 111112222211111222221111122222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 1 step 90 000000000100001000010000100111 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEDEFHJFHJKLKLMNPMNPRSRSTUV SIDE 111112222211111222221111122222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 100 step 91 000000000100001000010000101001 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEDEFHJFHJKLKLMNPMNPRSRSTUV SIDE 111112222211111222221111122222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 1 step 92 000000000100001000010000101011 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEDEFHJFHJKLKLMNPMNPRSRSTUV SIDE 111112222211111222221111122222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 10 step 93 000000000100001000010000101101 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEDEFHJFHJKLKLMNPMNPRSRSTUV SIDE 111112222211111222221111122222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 1 step 94 000000000100001000010000101111 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEDEFHJFHJKLKLMNPMNPRSRSTUV SIDE 111112222211111222221111122222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 1000 step 95 000000000100001000010000110001 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEDEFHJFHJKLKLMNPMNPRSRSTUV SIDE 111112222211111222221111122222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 1 step 96 000000000100001000010000110011 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEDEFHJFHJKLKLMNPMNPRSRSTUV SIDE 111112222211111222221111122222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 10 step 97 000000000100001000010000110101 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEDEFHJFHJKLKLMNPMNPRSRSTUV SIDE 111112222211111222221111122222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 1 step 98 000000000100001000010000110111 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEDEFHJFHJKLKLMNPMNPRSRSTUV SIDE 111112222211111222221111122222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 100 step 99 000000000100001000010000111001 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEDEFHJFHJKLKLMNPMNPRSRSTUV SIDE 111112222211111222221111122222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 1 step 100 000000000100001000010000111011 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEDEFHJFHJKLKLMNPMNPRSRSTUV SIDE 111112222211111222221111122222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 10 step 101 000000000100001000010000111101 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEDEFHJFHJKLKLMNPMNPRSRSTUV SIDE 111112222211111222221111122222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 10 step 102 000000000100001000010000111110 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEDEFHJFHJKLKLMNPMNPRSRSTUV SIDE 111112222211111222221111122222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 00001 step 103 000000000100001000010000100001 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEDEFHJFHJKLKLMNPMNPRSRSTUV SIDE 111112222211111222221111122222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: step 104 000000000100001000010000100001 fail ^ step 105 111101111011110111101111011110 SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEDEFHJFHJKLKLMNPMNPRSRSTUV SIDE 111112222211111222221111122222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 0000 step 106 000001111011110111101111011110 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEDEFHJFHJKLKLMNPMNPRSRSTUV SIDE 111112222211111222221111122222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 1 step 107 000101111011110111101111011110 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEDEFHJFHJKLKLMNPMNPRSRSTUV SIDE 111112222211111222221111122222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 10 step 108 001001111011110111101111011110 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEDEFHJFHJKLKLMNPMNPRSRSTUV SIDE 111112222211111222221111122222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 1 step 109 001101111011110111101111011110 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEDEFHJFHJKLKLMNPMNPRSRSTUV SIDE 111112222211111222221111122222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 100 step 110 010001111011110111101111011110 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEDEFHJFHJKLKLMNPMNPRSRSTUV SIDE 111112222211111222221111122222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 1 step 111 010101111011110111101111011110 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEDEFHJFHJKLKLMNPMNPRSRSTUV SIDE 111112222211111222221111122222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 10 step 112 011001111011110111101111011110 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEDEFHJFHJKLKLMNPMNPRSRSTUV SIDE 111112222211111222221111122222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 1 step 113 011101111011110111101111011110 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEDEFHJFHJKLKLMNPMNPRSRSTUV SIDE 111112222211111222221111122222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 1000 step 114 100001111011110111101111011110 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEDEFHJFHJKLKLMNPMNPRSRSTUV SIDE 111112222211111222221111122222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 1 step 115 100101111011110111101111011110 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEDEFHJFHJKLKLMNPMNPRSRSTUV SIDE 111112222211111222221111122222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 10 step 116 101001111011110111101111011110 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEDEFHJFHJKLKLMNPMNPRSRSTUV SIDE 111112222211111222221111122222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 1 step 117 101101111011110111101111011110 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEDEFHJFHJKLKLMNPMNPRSRSTUV SIDE 111112222211111222221111122222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 100 step 118 110001111011110111101111011110 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEDEFHJFHJKLKLMNPMNPRSRSTUV SIDE 111112222211111222221111122222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 1 step 119 110101111011110111101111011110 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEDEFHJFHJKLKLMNPMNPRSRSTUV SIDE 111112222211111222221111122222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 10 step 120 111001111011110111101111011110 fail ^ step 121 111101111011110111101111011110 step 122 111100000111110111101111011110 step 123 111100001111110111101111011110 step 124 111100010111110111101111011110 step 125 111100011111110111101111011110 step 126 111100100111110111101111011110 step 127 111100101111110111101111011110 step 128 111100110111110111101111011110 step 129 111100111111110111101111011110 step 130 111101000111110111101111011110 step 131 111101001111110111101111011110 step 132 111101010111110111101111011110 step 133 111101011111110111101111011110 step 134 111101100111110111101111011110 step 135 111101101111110111101111011110 step 136 111101110111110111101111011110 step 137 111101111011110111101111011110 step 138 111101111000001111101111011110 step 139 111101111000011111101111011110 step 140 111101111000101111101111011110 step 141 111101111000111111101111011110 step 142 111101111001001111101111011110 step 143 111101111001011111101111011110 step 144 111101111001101111101111011110 step 145 111101111001111111101111011110 step 146 111101111010001111101111011110 step 147 111101111010011111101111011110 step 148 111101111010101111101111011110 step 149 111101111010111111101111011110 step 150 111101111011001111101111011110 step 151 111101111011011111101111011110 step 152 111101111011101111101111011110 step 153 111101111011110111101111011110 step 154 111101111011110000011111011110 step 155 111101111011110000111111011110 step 156 111101111011110001011111011110 step 157 111101111011110001111111011110 step 158 111101111011110010011111011110 step 159 111101111011110010111111011110 step 160 111101111011110011011111011110 step 161 111101111011110011111111011110 step 162 111101111011110100011111011110 step 163 111101111011110100111111011110 step 164 111101111011110101011111011110 step 165 111101111011110101111111011110 step 166 111101111011110110011111011110 step 167 111101111011110110111111011110 step 168 111101111011110111011111011110 step 169 111101111011110111101111011110 step 170 111101111011110111100000111110 step 171 111101111011110111100001111110 step 172 111101111011110111100010111110 step 173 111101111011110111100011111110 step 174 111101111011110111100100111110 step 175 111101111011110111100101111110 step 176 111101111011110111100110111110 step 177 111101111011110111100111111110 step 178 111101111011110111101000111110 step 179 111101111011110111101001111110 step 180 111101111011110111101010111110 step 181 111101111011110111101011111110 step 182 111101111011110111101100111110 step 183 111101111011110111101101111110 step 184 111101111011110111101110111110 step 185 111101111011110111101111011110 step 186 111101111011110111101111000001 step 187 111101111011110111101111000011 step 188 111101111011110111101111000101 step 189 111101111011110111101111000111 step 190 111101111011110111101111001001 step 191 111101111011110111101111001011 step 192 111101111011110111101111001101 step 193 111101111011110111101111001111 step 194 111101111011110111101111010001 step 195 111101111011110111101111010011 step 196 111101111011110111101111010101 step 197 111101111011110111101111010111 step 198 111101111011110111101111011001 step 199 111101111011110111101111011011 step 200 111101111011110111101111011101 step 201 111101111011110111101111011110 step 202 111101111011110111101111011110 test 23: *** FAIL *************************** 118 steps failed SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEDEFHJFHJKLKLMNPMNPRSRSTUV SIDE 111112222211111222221111122222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO this fail O all fails O was hi 1111 1111111111111111111111111 rising ^^^^ ^^^^^^^^^^^^^^^^^^^^^^^^^ falling vvvv vvvvvvvvvvvvvvvvvvvvvvvvv was lo 000000000000000000000000000000 total fails 23, total passes 0 space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn on comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEDEFHJFHJKLKLMNPMNPRSRSTUV SIDE 111112222211111222221111122222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 0000 0000100001000010000100001 step 1 000000000100001000010000100001 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEDEFHJFHJKLKLMNPMNPRSRSTUV SIDE 111112222211111222221111122222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: step 2 000000000100001000010000100001 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEDEFHJFHJKLKLMNPMNPRSRSTUV SIDE 111112222211111222221111122222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 1 step 3 000100000100001000010000100001 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEDEFHJFHJKLKLMNPMNPRSRSTUV SIDE 111112222211111222221111122222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 10 step 4 001000000100001000010000100001 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEDEFHJFHJKLKLMNPMNPRSRSTUV SIDE 111112222211111222221111122222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 1 step 5 001100000100001000010000100001 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEDEFHJFHJKLKLMNPMNPRSRSTUV SIDE 111112222211111222221111122222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 100 step 6 010000000100001000010000100001 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEDEFHJFHJKLKLMNPMNPRSRSTUV SIDE 111112222211111222221111122222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 1 step 7 010100000100001000010000100001 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEDEFHJFHJKLKLMNPMNPRSRSTUV SIDE 111112222211111222221111122222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 10 step 8 011000000100001000010000100001 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEDEFHJFHJKLKLMNPMNPRSRSTUV SIDE 111112222211111222221111122222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 1 step 9 011100000100001000010000100001 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEDEFHJFHJKLKLMNPMNPRSRSTUV SIDE 111112222211111222221111122222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 1000 step 10 100000000100001000010000100001 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEDEFHJFHJKLKLMNPMNPRSRSTUV SIDE 111112222211111222221111122222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 1 step 11 100100000100001000010000100001 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEDEFHJFHJKLKLMNPMNPRSRSTUV SIDE 111112222211111222221111122222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 10 step 12 101000000100001000010000100001 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEDEFHJFHJKLKLMNPMNPRSRSTUV SIDE 111112222211111222221111122222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 1 step 13 101100000100001000010000100001 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEDEFHJFHJKLKLMNPMNPRSRSTUV SIDE 111112222211111222221111122222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 100 step 14 110000000100001000010000100001 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEDEFHJFHJKLKLMNPMNPRSRSTUV SIDE 111112222211111222221111122222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 1 step 15 110100000100001000010000100001 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEDEFHJFHJKLKLMNPMNPRSRSTUV SIDE 111112222211111222221111122222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 10 step 16 111000000100001000010000100001 fail ^ step 17 111100000100001000010000100001 SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEDEFHJFHJKLKLMNPMNPRSRSTUV SIDE 111112222211111222221111122222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 0000 step 18 000000000100001000010000100001 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEDEFHJFHJKLKLMNPMNPRSRSTUV SIDE 111112222211111222221111122222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: step 19 000000000100001000010000100001 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEDEFHJFHJKLKLMNPMNPRSRSTUV SIDE 111112222211111222221111122222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 1 step 20 000000001100001000010000100001 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEDEFHJFHJKLKLMNPMNPRSRSTUV SIDE 111112222211111222221111122222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 10 step 21 000000010100001000010000100001 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEDEFHJFHJKLKLMNPMNPRSRSTUV SIDE 111112222211111222221111122222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 1 step 22 000000011100001000010000100001 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEDEFHJFHJKLKLMNPMNPRSRSTUV SIDE 111112222211111222221111122222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 100 step 23 000000100100001000010000100001 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEDEFHJFHJKLKLMNPMNPRSRSTUV SIDE 111112222211111222221111122222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 1 step 24 000000101100001000010000100001 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEDEFHJFHJKLKLMNPMNPRSRSTUV SIDE 111112222211111222221111122222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 10 step 25 000000110100001000010000100001 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEDEFHJFHJKLKLMNPMNPRSRSTUV SIDE 111112222211111222221111122222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 1 step 26 000000111100001000010000100001 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEDEFHJFHJKLKLMNPMNPRSRSTUV SIDE 111112222211111222221111122222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 1000 step 27 000001000100001000010000100001 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEDEFHJFHJKLKLMNPMNPRSRSTUV SIDE 111112222211111222221111122222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 1 step 28 000001001100001000010000100001 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEDEFHJFHJKLKLMNPMNPRSRSTUV SIDE 111112222211111222221111122222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 10 step 29 000001010100001000010000100001 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEDEFHJFHJKLKLMNPMNPRSRSTUV SIDE 111112222211111222221111122222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 1 step 30 000001011100001000010000100001 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEDEFHJFHJKLKLMNPMNPRSRSTUV SIDE 111112222211111222221111122222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 100 step 31 000001100100001000010000100001 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEDEFHJFHJKLKLMNPMNPRSRSTUV SIDE 111112222211111222221111122222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 1 step 32 000001101100001000010000100001 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEDEFHJFHJKLKLMNPMNPRSRSTUV SIDE 111112222211111222221111122222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 10 step 33 000001110100001000010000100001 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEDEFHJFHJKLKLMNPMNPRSRSTUV SIDE 111112222211111222221111122222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 10 step 34 000001111000001000010000100001 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEDEFHJFHJKLKLMNPMNPRSRSTUV SIDE 111112222211111222221111122222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 00001 step 35 000000000100001000010000100001 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEDEFHJFHJKLKLMNPMNPRSRSTUV SIDE 111112222211111222221111122222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: step 36 000000000100001000010000100001 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEDEFHJFHJKLKLMNPMNPRSRSTUV SIDE 111112222211111222221111122222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 1 step 37 000000000100011000010000100001 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEDEFHJFHJKLKLMNPMNPRSRSTUV SIDE 111112222211111222221111122222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 10 step 38 000000000100101000010000100001 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEDEFHJFHJKLKLMNPMNPRSRSTUV SIDE 111112222211111222221111122222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 1 step 39 000000000100111000010000100001 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEDEFHJFHJKLKLMNPMNPRSRSTUV SIDE 111112222211111222221111122222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 100 step 40 000000000101001000010000100001 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEDEFHJFHJKLKLMNPMNPRSRSTUV SIDE 111112222211111222221111122222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 1 step 41 000000000101011000010000100001 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEDEFHJFHJKLKLMNPMNPRSRSTUV SIDE 111112222211111222221111122222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 10 step 42 000000000101101000010000100001 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEDEFHJFHJKLKLMNPMNPRSRSTUV SIDE 111112222211111222221111122222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 1 step 43 000000000101111000010000100001 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEDEFHJFHJKLKLMNPMNPRSRSTUV SIDE 111112222211111222221111122222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 1000 step 44 000000000110001000010000100001 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEDEFHJFHJKLKLMNPMNPRSRSTUV SIDE 111112222211111222221111122222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 1 step 45 000000000110011000010000100001 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEDEFHJFHJKLKLMNPMNPRSRSTUV SIDE 111112222211111222221111122222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 10 step 46 000000000110101000010000100001 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEDEFHJFHJKLKLMNPMNPRSRSTUV SIDE 111112222211111222221111122222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 1 step 47 000000000110111000010000100001 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEDEFHJFHJKLKLMNPMNPRSRSTUV SIDE 111112222211111222221111122222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 100 step 48 000000000111001000010000100001 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEDEFHJFHJKLKLMNPMNPRSRSTUV SIDE 111112222211111222221111122222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 1 step 49 000000000111011000010000100001 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEDEFHJFHJKLKLMNPMNPRSRSTUV SIDE 111112222211111222221111122222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 10 step 50 000000000111101000010000100001 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEDEFHJFHJKLKLMNPMNPRSRSTUV SIDE 111112222211111222221111122222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 10 step 51 000000000111110000010000100001 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEDEFHJFHJKLKLMNPMNPRSRSTUV SIDE 111112222211111222221111122222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 00001 step 52 000000000100001000010000100001 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEDEFHJFHJKLKLMNPMNPRSRSTUV SIDE 111112222211111222221111122222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: step 53 000000000100001000010000100001 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEDEFHJFHJKLKLMNPMNPRSRSTUV SIDE 111112222211111222221111122222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 1 step 54 000000000100001000110000100001 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEDEFHJFHJKLKLMNPMNPRSRSTUV SIDE 111112222211111222221111122222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 10 step 55 000000000100001001010000100001 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEDEFHJFHJKLKLMNPMNPRSRSTUV SIDE 111112222211111222221111122222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 1 step 56 000000000100001001110000100001 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEDEFHJFHJKLKLMNPMNPRSRSTUV SIDE 111112222211111222221111122222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 100 step 57 000000000100001010010000100001 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEDEFHJFHJKLKLMNPMNPRSRSTUV SIDE 111112222211111222221111122222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 1 step 58 000000000100001010110000100001 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEDEFHJFHJKLKLMNPMNPRSRSTUV SIDE 111112222211111222221111122222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 10 step 59 000000000100001011010000100001 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEDEFHJFHJKLKLMNPMNPRSRSTUV SIDE 111112222211111222221111122222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 1 step 60 000000000100001011110000100001 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEDEFHJFHJKLKLMNPMNPRSRSTUV SIDE 111112222211111222221111122222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 1000 step 61 000000000100001100010000100001 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEDEFHJFHJKLKLMNPMNPRSRSTUV SIDE 111112222211111222221111122222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 1 step 62 000000000100001100110000100001 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEDEFHJFHJKLKLMNPMNPRSRSTUV SIDE 111112222211111222221111122222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 10 step 63 000000000100001101010000100001 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEDEFHJFHJKLKLMNPMNPRSRSTUV SIDE 111112222211111222221111122222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 1 step 64 000000000100001101110000100001 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEDEFHJFHJKLKLMNPMNPRSRSTUV SIDE 111112222211111222221111122222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 100 step 65 000000000100001110010000100001 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEDEFHJFHJKLKLMNPMNPRSRSTUV SIDE 111112222211111222221111122222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 1 step 66 000000000100001110110000100001 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEDEFHJFHJKLKLMNPMNPRSRSTUV SIDE 111112222211111222221111122222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 10 step 67 000000000100001111010000100001 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEDEFHJFHJKLKLMNPMNPRSRSTUV SIDE 111112222211111222221111122222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 10 step 68 000000000100001111100000100001 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEDEFHJFHJKLKLMNPMNPRSRSTUV SIDE 111112222211111222221111122222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 00001 step 69 000000000100001000010000100001 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEDEFHJFHJKLKLMNPMNPRSRSTUV SIDE 111112222211111222221111122222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: step 70 000000000100001000010000100001 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEDEFHJFHJKLKLMNPMNPRSRSTUV SIDE 111112222211111222221111122222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 1 step 71 000000000100001000010001100001 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEDEFHJFHJKLKLMNPMNPRSRSTUV SIDE 111112222211111222221111122222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 10 step 72 000000000100001000010010100001 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEDEFHJFHJKLKLMNPMNPRSRSTUV SIDE 111112222211111222221111122222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 1 step 73 000000000100001000010011100001 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEDEFHJFHJKLKLMNPMNPRSRSTUV SIDE 111112222211111222221111122222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 100 step 74 000000000100001000010100100001 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEDEFHJFHJKLKLMNPMNPRSRSTUV SIDE 111112222211111222221111122222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 1 step 75 000000000100001000010101100001 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEDEFHJFHJKLKLMNPMNPRSRSTUV SIDE 111112222211111222221111122222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 10 step 76 000000000100001000010110100001 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEDEFHJFHJKLKLMNPMNPRSRSTUV SIDE 111112222211111222221111122222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 1 step 77 000000000100001000010111100001 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEDEFHJFHJKLKLMNPMNPRSRSTUV SIDE 111112222211111222221111122222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 1000 step 78 000000000100001000011000100001 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEDEFHJFHJKLKLMNPMNPRSRSTUV SIDE 111112222211111222221111122222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 1 step 79 000000000100001000011001100001 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEDEFHJFHJKLKLMNPMNPRSRSTUV SIDE 111112222211111222221111122222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 10 step 80 000000000100001000011010100001 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEDEFHJFHJKLKLMNPMNPRSRSTUV SIDE 111112222211111222221111122222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 1 step 81 000000000100001000011011100001 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEDEFHJFHJKLKLMNPMNPRSRSTUV SIDE 111112222211111222221111122222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 100 step 82 000000000100001000011100100001 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEDEFHJFHJKLKLMNPMNPRSRSTUV SIDE 111112222211111222221111122222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 1 step 83 000000000100001000011101100001 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEDEFHJFHJKLKLMNPMNPRSRSTUV SIDE 111112222211111222221111122222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 10 step 84 000000000100001000011110100001 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEDEFHJFHJKLKLMNPMNPRSRSTUV SIDE 111112222211111222221111122222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 10 step 85 000000000100001000011111000001 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEDEFHJFHJKLKLMNPMNPRSRSTUV SIDE 111112222211111222221111122222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 00001 step 86 000000000100001000010000100001 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEDEFHJFHJKLKLMNPMNPRSRSTUV SIDE 111112222211111222221111122222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: step 87 000000000100001000010000100001 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEDEFHJFHJKLKLMNPMNPRSRSTUV SIDE 111112222211111222221111122222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 1 step 88 000000000100001000010000100011 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEDEFHJFHJKLKLMNPMNPRSRSTUV SIDE 111112222211111222221111122222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 10 step 89 000000000100001000010000100101 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEDEFHJFHJKLKLMNPMNPRSRSTUV SIDE 111112222211111222221111122222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 1 step 90 000000000100001000010000100111 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEDEFHJFHJKLKLMNPMNPRSRSTUV SIDE 111112222211111222221111122222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 100 step 91 000000000100001000010000101001 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEDEFHJFHJKLKLMNPMNPRSRSTUV SIDE 111112222211111222221111122222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 1 step 92 000000000100001000010000101011 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEDEFHJFHJKLKLMNPMNPRSRSTUV SIDE 111112222211111222221111122222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 10 step 93 000000000100001000010000101101 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEDEFHJFHJKLKLMNPMNPRSRSTUV SIDE 111112222211111222221111122222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 1 step 94 000000000100001000010000101111 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEDEFHJFHJKLKLMNPMNPRSRSTUV SIDE 111112222211111222221111122222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 1000 step 95 000000000100001000010000110001 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEDEFHJFHJKLKLMNPMNPRSRSTUV SIDE 111112222211111222221111122222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 1 step 96 000000000100001000010000110011 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEDEFHJFHJKLKLMNPMNPRSRSTUV SIDE 111112222211111222221111122222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 10 step 97 000000000100001000010000110101 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEDEFHJFHJKLKLMNPMNPRSRSTUV SIDE 111112222211111222221111122222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 1 step 98 000000000100001000010000110111 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEDEFHJFHJKLKLMNPMNPRSRSTUV SIDE 111112222211111222221111122222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 100 step 99 000000000100001000010000111001 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEDEFHJFHJKLKLMNPMNPRSRSTUV SIDE 111112222211111222221111122222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 1 step 100 000000000100001000010000111011 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEDEFHJFHJKLKLMNPMNPRSRSTUV SIDE 111112222211111222221111122222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 10 step 101 000000000100001000010000111101 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEDEFHJFHJKLKLMNPMNPRSRSTUV SIDE 111112222211111222221111122222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 10 step 102 000000000100001000010000111110 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEDEFHJFHJKLKLMNPMNPRSRSTUV SIDE 111112222211111222221111122222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 00001 step 103 000000000100001000010000100001 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEDEFHJFHJKLKLMNPMNPRSRSTUV SIDE 111112222211111222221111122222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: step 104 000000000100001000010000100001 fail ^ step 105 111101111011110111101111011110 SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEDEFHJFHJKLKLMNPMNPRSRSTUV SIDE 111112222211111222221111122222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 0000 step 106 000001111011110111101111011110 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEDEFHJFHJKLKLMNPMNPRSRSTUV SIDE 111112222211111222221111122222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 1 step 107 000101111011110111101111011110 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEDEFHJFHJKLKLMNPMNPRSRSTUV SIDE 111112222211111222221111122222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 10 step 108 001001111011110111101111011110 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEDEFHJFHJKLKLMNPMNPRSRSTUV SIDE 111112222211111222221111122222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 1 step 109 001101111011110111101111011110 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEDEFHJFHJKLKLMNPMNPRSRSTUV SIDE 111112222211111222221111122222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 100 step 110 010001111011110111101111011110 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEDEFHJFHJKLKLMNPMNPRSRSTUV SIDE 111112222211111222221111122222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 1 step 111 010101111011110111101111011110 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEDEFHJFHJKLKLMNPMNPRSRSTUV SIDE 111112222211111222221111122222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 10 step 112 011001111011110111101111011110 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEDEFHJFHJKLKLMNPMNPRSRSTUV SIDE 111112222211111222221111122222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 1 step 113 011101111011110111101111011110 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEDEFHJFHJKLKLMNPMNPRSRSTUV SIDE 111112222211111222221111122222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 1000 step 114 100001111011110111101111011110 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEDEFHJFHJKLKLMNPMNPRSRSTUV SIDE 111112222211111222221111122222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 1 step 115 100101111011110111101111011110 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEDEFHJFHJKLKLMNPMNPRSRSTUV SIDE 111112222211111222221111122222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 10 step 116 101001111011110111101111011110 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEDEFHJFHJKLKLMNPMNPRSRSTUV SIDE 111112222211111222221111122222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 1 step 117 101101111011110111101111011110 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEDEFHJFHJKLKLMNPMNPRSRSTUV SIDE 111112222211111222221111122222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 100 step 118 110001111011110111101111011110 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEDEFHJFHJKLKLMNPMNPRSRSTUV SIDE 111112222211111222221111122222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 1 step 119 110101111011110111101111011110 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEDEFHJFHJKLKLMNPMNPRSRSTUV SIDE 111112222211111222221111122222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 10 step 120 111001111011110111101111011110 fail ^ step 121 111101111011110111101111011110 step 122 111100000111110111101111011110 step 123 111100001111110111101111011110 step 124 111100010111110111101111011110 step 125 111100011111110111101111011110 step 126 111100100111110111101111011110 step 127 111100101111110111101111011110 step 128 111100110111110111101111011110 step 129 111100111111110111101111011110 step 130 111101000111110111101111011110 step 131 111101001111110111101111011110 step 132 111101010111110111101111011110 step 133 111101011111110111101111011110 step 134 111101100111110111101111011110 step 135 111101101111110111101111011110 step 136 111101110111110111101111011110 step 137 111101111011110111101111011110 step 138 111101111000001111101111011110 step 139 111101111000011111101111011110 step 140 111101111000101111101111011110 step 141 111101111000111111101111011110 step 142 111101111001001111101111011110 step 143 111101111001011111101111011110 step 144 111101111001101111101111011110 step 145 111101111001111111101111011110 step 146 111101111010001111101111011110 step 147 111101111010011111101111011110 step 148 111101111010101111101111011110 step 149 111101111010111111101111011110 step 150 111101111011001111101111011110 step 151 111101111011011111101111011110 step 152 111101111011101111101111011110 step 153 111101111011110111101111011110 step 154 111101111011110000011111011110 step 155 111101111011110000111111011110 step 156 111101111011110001011111011110 step 157 111101111011110001111111011110 step 158 111101111011110010011111011110 step 159 111101111011110010111111011110 step 160 111101111011110011011111011110 step 161 111101111011110011111111011110 step 162 111101111011110100011111011110 step 163 111101111011110100111111011110 step 164 111101111011110101011111011110 step 165 111101111011110101111111011110 step 166 111101111011110110011111011110 step 167 111101111011110110111111011110 step 168 111101111011110111011111011110 step 169 111101111011110111101111011110 step 170 111101111011110111100000111110 step 171 111101111011110111100001111110 step 172 111101111011110111100010111110 step 173 111101111011110111100011111110 step 174 111101111011110111100100111110 step 175 111101111011110111100101111110 step 176 111101111011110111100110111110 step 177 111101111011110111100111111110 step 178 111101111011110111101000111110 step 179 111101111011110111101001111110 step 180 111101111011110111101010111110 step 181 111101111011110111101011111110 step 182 111101111011110111101100111110 step 183 111101111011110111101101111110 step 184 111101111011110111101110111110 step 185 111101111011110111101111011110 step 186 111101111011110111101111000001 step 187 111101111011110111101111000011 step 188 111101111011110111101111000101 step 189 111101111011110111101111000111 step 190 111101111011110111101111001001 step 191 111101111011110111101111001011 step 192 111101111011110111101111001101 step 193 111101111011110111101111001111 step 194 111101111011110111101111010001 step 195 111101111011110111101111010011 step 196 111101111011110111101111010101 step 197 111101111011110111101111010111 step 198 111101111011110111101111011001 step 199 111101111011110111101111011011 step 200 111101111011110111101111011101 step 201 111101111011110111101111011110 step 202 111101111011110111101111011110 test 24: *** FAIL *************************** 118 steps failed SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEDEFHJFHJKLKLMNPMNPRSRSTUV SIDE 111112222211111222221111122222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO this fail O all fails O was hi 1111 1111111111111111111111111 rising ^^^^ ^^^^^^^^^^^^^^^^^^^^^^^^^ falling vvvv vvvvvvvvvvvvvvvvvvvvvvvvv was lo 000000000000000000000000000000 total fails 24, total passes 0 space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn on comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEDEFHJFHJKLKLMNPMNPRSRSTUV SIDE 111112222211111222221111122222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 0000 0000100001000010000100001 step 1 000000000100001000010000100001 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEDEFHJFHJKLKLMNPMNPRSRSTUV SIDE 111112222211111222221111122222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: step 2 000000000100001000010000100001 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEDEFHJFHJKLKLMNPMNPRSRSTUV SIDE 111112222211111222221111122222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 1 step 3 000100000100001000010000100001 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEDEFHJFHJKLKLMNPMNPRSRSTUV SIDE 111112222211111222221111122222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 10 step 4 001000000100001000010000100001 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEDEFHJFHJKLKLMNPMNPRSRSTUV SIDE 111112222211111222221111122222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 1 step 5 001100000100001000010000100001 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEDEFHJFHJKLKLMNPMNPRSRSTUV SIDE 111112222211111222221111122222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 100 step 6 010000000100001000010000100001 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEDEFHJFHJKLKLMNPMNPRSRSTUV SIDE 111112222211111222221111122222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 1 step 7 010100000100001000010000100001 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEDEFHJFHJKLKLMNPMNPRSRSTUV SIDE 111112222211111222221111122222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 10 step 8 011000000100001000010000100001 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEDEFHJFHJKLKLMNPMNPRSRSTUV SIDE 111112222211111222221111122222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 1 step 9 011100000100001000010000100001 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEDEFHJFHJKLKLMNPMNPRSRSTUV SIDE 111112222211111222221111122222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 1000 step 10 100000000100001000010000100001 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEDEFHJFHJKLKLMNPMNPRSRSTUV SIDE 111112222211111222221111122222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 1 step 11 100100000100001000010000100001 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEDEFHJFHJKLKLMNPMNPRSRSTUV SIDE 111112222211111222221111122222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 10 step 12 101000000100001000010000100001 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEDEFHJFHJKLKLMNPMNPRSRSTUV SIDE 111112222211111222221111122222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 1 step 13 101100000100001000010000100001 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEDEFHJFHJKLKLMNPMNPRSRSTUV SIDE 111112222211111222221111122222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 100 step 14 110000000100001000010000100001 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEDEFHJFHJKLKLMNPMNPRSRSTUV SIDE 111112222211111222221111122222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 1 step 15 110100000100001000010000100001 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEDEFHJFHJKLKLMNPMNPRSRSTUV SIDE 111112222211111222221111122222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 10 step 16 111000000100001000010000100001 fail ^ step 17 111100000100001000010000100001 SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEDEFHJFHJKLKLMNPMNPRSRSTUV SIDE 111112222211111222221111122222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 0000 step 18 000000000100001000010000100001 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEDEFHJFHJKLKLMNPMNPRSRSTUV SIDE 111112222211111222221111122222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: step 19 000000000100001000010000100001 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEDEFHJFHJKLKLMNPMNPRSRSTUV SIDE 111112222211111222221111122222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 1 step 20 000000001100001000010000100001 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEDEFHJFHJKLKLMNPMNPRSRSTUV SIDE 111112222211111222221111122222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 10 step 21 000000010100001000010000100001 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEDEFHJFHJKLKLMNPMNPRSRSTUV SIDE 111112222211111222221111122222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 1 step 22 000000011100001000010000100001 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEDEFHJFHJKLKLMNPMNPRSRSTUV SIDE 111112222211111222221111122222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 100 step 23 000000100100001000010000100001 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEDEFHJFHJKLKLMNPMNPRSRSTUV SIDE 111112222211111222221111122222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 1 step 24 000000101100001000010000100001 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEDEFHJFHJKLKLMNPMNPRSRSTUV SIDE 111112222211111222221111122222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 10 step 25 000000110100001000010000100001 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEDEFHJFHJKLKLMNPMNPRSRSTUV SIDE 111112222211111222221111122222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 1 step 26 000000111100001000010000100001 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEDEFHJFHJKLKLMNPMNPRSRSTUV SIDE 111112222211111222221111122222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 1000 step 27 000001000100001000010000100001 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEDEFHJFHJKLKLMNPMNPRSRSTUV SIDE 111112222211111222221111122222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 1 step 28 000001001100001000010000100001 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEDEFHJFHJKLKLMNPMNPRSRSTUV SIDE 111112222211111222221111122222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 10 step 29 000001010100001000010000100001 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEDEFHJFHJKLKLMNPMNPRSRSTUV SIDE 111112222211111222221111122222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 1 step 30 000001011100001000010000100001 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEDEFHJFHJKLKLMNPMNPRSRSTUV SIDE 111112222211111222221111122222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 100 step 31 000001100100001000010000100001 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEDEFHJFHJKLKLMNPMNPRSRSTUV SIDE 111112222211111222221111122222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 1 step 32 000001101100001000010000100001 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEDEFHJFHJKLKLMNPMNPRSRSTUV SIDE 111112222211111222221111122222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 10 step 33 000001110100001000010000100001 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEDEFHJFHJKLKLMNPMNPRSRSTUV SIDE 111112222211111222221111122222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 10 step 34 000001111000001000010000100001 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEDEFHJFHJKLKLMNPMNPRSRSTUV SIDE 111112222211111222221111122222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 00001 step 35 000000000100001000010000100001 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEDEFHJFHJKLKLMNPMNPRSRSTUV SIDE 111112222211111222221111122222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: step 36 000000000100001000010000100001 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEDEFHJFHJKLKLMNPMNPRSRSTUV SIDE 111112222211111222221111122222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 1 step 37 000000000100011000010000100001 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEDEFHJFHJKLKLMNPMNPRSRSTUV SIDE 111112222211111222221111122222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 10 step 38 000000000100101000010000100001 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEDEFHJFHJKLKLMNPMNPRSRSTUV SIDE 111112222211111222221111122222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 1 step 39 000000000100111000010000100001 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEDEFHJFHJKLKLMNPMNPRSRSTUV SIDE 111112222211111222221111122222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 100 step 40 000000000101001000010000100001 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEDEFHJFHJKLKLMNPMNPRSRSTUV SIDE 111112222211111222221111122222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 1 step 41 000000000101011000010000100001 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEDEFHJFHJKLKLMNPMNPRSRSTUV SIDE 111112222211111222221111122222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 10 step 42 000000000101101000010000100001 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEDEFHJFHJKLKLMNPMNPRSRSTUV SIDE 111112222211111222221111122222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 1 step 43 000000000101111000010000100001 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEDEFHJFHJKLKLMNPMNPRSRSTUV SIDE 111112222211111222221111122222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 1000 step 44 000000000110001000010000100001 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEDEFHJFHJKLKLMNPMNPRSRSTUV SIDE 111112222211111222221111122222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 1 step 45 000000000110011000010000100001 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEDEFHJFHJKLKLMNPMNPRSRSTUV SIDE 111112222211111222221111122222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 10 step 46 000000000110101000010000100001 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEDEFHJFHJKLKLMNPMNPRSRSTUV SIDE 111112222211111222221111122222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 1 step 47 000000000110111000010000100001 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEDEFHJFHJKLKLMNPMNPRSRSTUV SIDE 111112222211111222221111122222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 100 step 48 000000000111001000010000100001 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEDEFHJFHJKLKLMNPMNPRSRSTUV SIDE 111112222211111222221111122222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 1 step 49 000000000111011000010000100001 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEDEFHJFHJKLKLMNPMNPRSRSTUV SIDE 111112222211111222221111122222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 10 step 50 000000000111101000010000100001 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEDEFHJFHJKLKLMNPMNPRSRSTUV SIDE 111112222211111222221111122222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 10 step 51 000000000111110000010000100001 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEDEFHJFHJKLKLMNPMNPRSRSTUV SIDE 111112222211111222221111122222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 00001 step 52 000000000100001000010000100001 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEDEFHJFHJKLKLMNPMNPRSRSTUV SIDE 111112222211111222221111122222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: step 53 000000000100001000010000100001 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEDEFHJFHJKLKLMNPMNPRSRSTUV SIDE 111112222211111222221111122222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 1 step 54 000000000100001000110000100001 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEDEFHJFHJKLKLMNPMNPRSRSTUV SIDE 111112222211111222221111122222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 10 step 55 000000000100001001010000100001 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEDEFHJFHJKLKLMNPMNPRSRSTUV SIDE 111112222211111222221111122222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 1 step 56 000000000100001001110000100001 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEDEFHJFHJKLKLMNPMNPRSRSTUV SIDE 111112222211111222221111122222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 100 step 57 000000000100001010010000100001 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEDEFHJFHJKLKLMNPMNPRSRSTUV SIDE 111112222211111222221111122222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 1 step 58 000000000100001010110000100001 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEDEFHJFHJKLKLMNPMNPRSRSTUV SIDE 111112222211111222221111122222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 10 step 59 000000000100001011010000100001 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEDEFHJFHJKLKLMNPMNPRSRSTUV SIDE 111112222211111222221111122222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 1 step 60 000000000100001011110000100001 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEDEFHJFHJKLKLMNPMNPRSRSTUV SIDE 111112222211111222221111122222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 1000 step 61 000000000100001100010000100001 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEDEFHJFHJKLKLMNPMNPRSRSTUV SIDE 111112222211111222221111122222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 1 step 62 000000000100001100110000100001 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEDEFHJFHJKLKLMNPMNPRSRSTUV SIDE 111112222211111222221111122222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 10 step 63 000000000100001101010000100001 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEDEFHJFHJKLKLMNPMNPRSRSTUV SIDE 111112222211111222221111122222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 1 step 64 000000000100001101110000100001 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEDEFHJFHJKLKLMNPMNPRSRSTUV SIDE 111112222211111222221111122222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 100 step 65 000000000100001110010000100001 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEDEFHJFHJKLKLMNPMNPRSRSTUV SIDE 111112222211111222221111122222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 1 step 66 000000000100001110110000100001 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEDEFHJFHJKLKLMNPMNPRSRSTUV SIDE 111112222211111222221111122222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 10 step 67 000000000100001111010000100001 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEDEFHJFHJKLKLMNPMNPRSRSTUV SIDE 111112222211111222221111122222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 10 step 68 000000000100001111100000100001 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEDEFHJFHJKLKLMNPMNPRSRSTUV SIDE 111112222211111222221111122222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 00001 step 69 000000000100001000010000100001 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEDEFHJFHJKLKLMNPMNPRSRSTUV SIDE 111112222211111222221111122222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: step 70 000000000100001000010000100001 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEDEFHJFHJKLKLMNPMNPRSRSTUV SIDE 111112222211111222221111122222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 1 step 71 000000000100001000010001100001 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEDEFHJFHJKLKLMNPMNPRSRSTUV SIDE 111112222211111222221111122222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 10 step 72 000000000100001000010010100001 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEDEFHJFHJKLKLMNPMNPRSRSTUV SIDE 111112222211111222221111122222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 1 step 73 000000000100001000010011100001 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEDEFHJFHJKLKLMNPMNPRSRSTUV SIDE 111112222211111222221111122222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 100 step 74 000000000100001000010100100001 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEDEFHJFHJKLKLMNPMNPRSRSTUV SIDE 111112222211111222221111122222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 1 step 75 000000000100001000010101100001 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEDEFHJFHJKLKLMNPMNPRSRSTUV SIDE 111112222211111222221111122222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 10 step 76 000000000100001000010110100001 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEDEFHJFHJKLKLMNPMNPRSRSTUV SIDE 111112222211111222221111122222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 1 step 77 000000000100001000010111100001 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEDEFHJFHJKLKLMNPMNPRSRSTUV SIDE 111112222211111222221111122222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 1000 step 78 000000000100001000011000100001 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEDEFHJFHJKLKLMNPMNPRSRSTUV SIDE 111112222211111222221111122222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 1 step 79 000000000100001000011001100001 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEDEFHJFHJKLKLMNPMNPRSRSTUV SIDE 111112222211111222221111122222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 10 step 80 000000000100001000011010100001 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEDEFHJFHJKLKLMNPMNPRSRSTUV SIDE 111112222211111222221111122222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 1 step 81 000000000100001000011011100001 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEDEFHJFHJKLKLMNPMNPRSRSTUV SIDE 111112222211111222221111122222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 100 step 82 000000000100001000011100100001 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEDEFHJFHJKLKLMNPMNPRSRSTUV SIDE 111112222211111222221111122222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 1 step 83 000000000100001000011101100001 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEDEFHJFHJKLKLMNPMNPRSRSTUV SIDE 111112222211111222221111122222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 10 step 84 000000000100001000011110100001 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEDEFHJFHJKLKLMNPMNPRSRSTUV SIDE 111112222211111222221111122222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 10 step 85 000000000100001000011111000001 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEDEFHJFHJKLKLMNPMNPRSRSTUV SIDE 111112222211111222221111122222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 00001 step 86 000000000100001000010000100001 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEDEFHJFHJKLKLMNPMNPRSRSTUV SIDE 111112222211111222221111122222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: step 87 000000000100001000010000100001 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEDEFHJFHJKLKLMNPMNPRSRSTUV SIDE 111112222211111222221111122222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 1 step 88 000000000100001000010000100011 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEDEFHJFHJKLKLMNPMNPRSRSTUV SIDE 111112222211111222221111122222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 10 step 89 000000000100001000010000100101 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEDEFHJFHJKLKLMNPMNPRSRSTUV SIDE 111112222211111222221111122222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 1 step 90 000000000100001000010000100111 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEDEFHJFHJKLKLMNPMNPRSRSTUV SIDE 111112222211111222221111122222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 100 step 91 000000000100001000010000101001 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEDEFHJFHJKLKLMNPMNPRSRSTUV SIDE 111112222211111222221111122222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 1 step 92 000000000100001000010000101011 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEDEFHJFHJKLKLMNPMNPRSRSTUV SIDE 111112222211111222221111122222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 10 step 93 000000000100001000010000101101 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEDEFHJFHJKLKLMNPMNPRSRSTUV SIDE 111112222211111222221111122222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 1 step 94 000000000100001000010000101111 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEDEFHJFHJKLKLMNPMNPRSRSTUV SIDE 111112222211111222221111122222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 1000 step 95 000000000100001000010000110001 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEDEFHJFHJKLKLMNPMNPRSRSTUV SIDE 111112222211111222221111122222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 1 step 96 000000000100001000010000110011 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEDEFHJFHJKLKLMNPMNPRSRSTUV SIDE 111112222211111222221111122222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 10 step 97 000000000100001000010000110101 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEDEFHJFHJKLKLMNPMNPRSRSTUV SIDE 111112222211111222221111122222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 1 step 98 000000000100001000010000110111 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEDEFHJFHJKLKLMNPMNPRSRSTUV SIDE 111112222211111222221111122222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 100 step 99 000000000100001000010000111001 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEDEFHJFHJKLKLMNPMNPRSRSTUV SIDE 111112222211111222221111122222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 1 step 100 000000000100001000010000111011 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEDEFHJFHJKLKLMNPMNPRSRSTUV SIDE 111112222211111222221111122222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 10 step 101 000000000100001000010000111101 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEDEFHJFHJKLKLMNPMNPRSRSTUV SIDE 111112222211111222221111122222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 10 step 102 000000000100001000010000111110 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEDEFHJFHJKLKLMNPMNPRSRSTUV SIDE 111112222211111222221111122222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 00001 step 103 000000000100001000010000100001 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEDEFHJFHJKLKLMNPMNPRSRSTUV SIDE 111112222211111222221111122222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: step 104 000000000100001000010000100001 fail ^ step 105 111101111011110111101111011110 SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEDEFHJFHJKLKLMNPMNPRSRSTUV SIDE 111112222211111222221111122222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 0000 step 106 000001111011110111101111011110 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEDEFHJFHJKLKLMNPMNPRSRSTUV SIDE 111112222211111222221111122222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 1 step 107 000101111011110111101111011110 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEDEFHJFHJKLKLMNPMNPRSRSTUV SIDE 111112222211111222221111122222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 10 step 108 001001111011110111101111011110 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEDEFHJFHJKLKLMNPMNPRSRSTUV SIDE 111112222211111222221111122222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 1 step 109 001101111011110111101111011110 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEDEFHJFHJKLKLMNPMNPRSRSTUV SIDE 111112222211111222221111122222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 100 step 110 010001111011110111101111011110 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEDEFHJFHJKLKLMNPMNPRSRSTUV SIDE 111112222211111222221111122222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 1 step 111 010101111011110111101111011110 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEDEFHJFHJKLKLMNPMNPRSRSTUV SIDE 111112222211111222221111122222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 10 step 112 011001111011110111101111011110 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEDEFHJFHJKLKLMNPMNPRSRSTUV SIDE 111112222211111222221111122222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 1 step 113 011101111011110111101111011110 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEDEFHJFHJKLKLMNPMNPRSRSTUV SIDE 111112222211111222221111122222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 1000 step 114 100001111011110111101111011110 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEDEFHJFHJKLKLMNPMNPRSRSTUV SIDE 111112222211111222221111122222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 1 step 115 100101111011110111101111011110 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEDEFHJFHJKLKLMNPMNPRSRSTUV SIDE 111112222211111222221111122222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 10 step 116 101001111011110111101111011110 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEDEFHJFHJKLKLMNPMNPRSRSTUV SIDE 111112222211111222221111122222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 1 step 117 101101111011110111101111011110 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEDEFHJFHJKLKLMNPMNPRSRSTUV SIDE 111112222211111222221111122222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 100 step 118 110001111011110111101111011110 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEDEFHJFHJKLKLMNPMNPRSRSTUV SIDE 111112222211111222221111122222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 1 step 119 110101111011110111101111011110 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEDEFHJFHJKLKLMNPMNPRSRSTUV SIDE 111112222211111222221111122222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 10 step 120 111001111011110111101111011110 fail ^ step 121 111101111011110111101111011110 step 122 111100000111110111101111011110 step 123 111100001111110111101111011110 step 124 111100010111110111101111011110 step 125 111100011111110111101111011110 step 126 111100100111110111101111011110 step 127 111100101111110111101111011110 step 128 111100110111110111101111011110 step 129 111100111111110111101111011110 step 130 111101000111110111101111011110 step 131 111101001111110111101111011110 step 132 111101010111110111101111011110 step 133 111101011111110111101111011110 step 134 111101100111110111101111011110 step 135 111101101111110111101111011110 step 136 111101110111110111101111011110 step 137 111101111011110111101111011110 step 138 111101111000001111101111011110 step 139 111101111000011111101111011110 step 140 111101111000101111101111011110 step 141 111101111000111111101111011110 step 142 111101111001001111101111011110 step 143 111101111001011111101111011110 step 144 111101111001101111101111011110 step 145 111101111001111111101111011110 step 146 111101111010001111101111011110 step 147 111101111010011111101111011110 step 148 111101111010101111101111011110 step 149 111101111010111111101111011110 step 150 111101111011001111101111011110 step 151 111101111011011111101111011110 step 152 111101111011101111101111011110 step 153 111101111011110111101111011110 step 154 111101111011110000011111011110 step 155 111101111011110000111111011110 step 156 111101111011110001011111011110 step 157 111101111011110001111111011110 step 158 111101111011110010011111011110 step 159 111101111011110010111111011110 step 160 111101111011110011011111011110 step 161 111101111011110011111111011110 step 162 111101111011110100011111011110 step 163 111101111011110100111111011110 step 164 111101111011110101011111011110 step 165 111101111011110101111111011110 step 166 111101111011110110011111011110 step 167 111101111011110110111111011110 step 168 111101111011110111011111011110 step 169 111101111011110111101111011110 step 170 111101111011110111100000111110 step 171 111101111011110111100001111110 step 172 111101111011110111100010111110 step 173 111101111011110111100011111110 step 174 111101111011110111100100111110 step 175 111101111011110111100101111110 step 176 111101111011110111100110111110 step 177 111101111011110111100111111110 step 178 111101111011110111101000111110 step 179 111101111011110111101001111110 step 180 111101111011110111101010111110 step 181 111101111011110111101011111110 step 182 111101111011110111101100111110 step 183 111101111011110111101101111110 step 184 111101111011110111101110111110 step 185 111101111011110111101111011110 step 186 111101111011110111101111000001 step 187 111101111011110111101111000011 step 188 111101111011110111101111000101 step 189 111101111011110111101111000111 step 190 111101111011110111101111001001 step 191 111101111011110111101111001011 step 192 111101111011110111101111001101 step 193 111101111011110111101111001111 step 194 111101111011110111101111010001 step 195 111101111011110111101111010011 step 196 111101111011110111101111010101 step 197 111101111011110111101111010111 step 198 111101111011110111101111011001 step 199 111101111011110111101111011011 step 200 111101111011110111101111011101 step 201 111101111011110111101111011110 step 202 111101111011110111101111011110 test 25: *** FAIL *************************** 118 steps failed SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEDEFHJFHJKLKLMNPMNPRSRSTUV SIDE 111112222211111222221111122222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO this fail O all fails O was hi 1111 1111111111111111111111111 rising ^^^^ ^^^^^^^^^^^^^^^^^^^^^^^^^ falling vvvv vvvvvvvvvvvvvvvvvvvvvvvvv was lo 000000000000000000000000000000 total fails 25, total passes 0 space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn on comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn on comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit 1 I AA1 E1-2 INPUT 1A 2 I AB1 E1-1 INPUT 1B 3 I AC1 E1-4 INPUT 1C 4 I AD1 E1-5 INPUT 1D 5 O AE1 E1-6 OUTPUT 1 = (1A NAND 1B NAND 1C NAND 1D) 6 I AD2 E1-13 INPUT 2A 7 I AE2 E1-12 INPUT 2B 8 I AF2 E1-10 INPUT 2C 9 I AH2 E1-9 INPUT 2D 10 O AJ2 E1-8 OUTPUT 2 = (2A NAND 2B NAND 2C NAND 2D) 11 I AF1 E2-2 INPUT 3A 12 I AH1 E2-1 INPUT 3B 13 I AJ1 E2-4 INPUT 3C 14 I AK1 E2-5 INPUT 3D 15 O AL1 E2-6 OUTPUT 3 = (3A NAND 3B NAND 3C NAND 3D) 16 I AK2 E2-13 INPUT 4A 17 I AL2 E2-12 INPUT 4B 18 I AM2 E2-10 INPUT 4C 19 I AN2 E2-9 INPUT 4D 20 O AP2 E2-8 OUTPUT 4 = (4A NAND 4B NAND 4C NAND 4D) 21 I AM1 E3-1 INPUT 5A 22 I AN1 E3-2 INPUT 5B 23 I AP1 E3-4 INPUT 5C 24 I AR1 E3-5 INPUT 5D 25 O AS1 E3-6 OUTPUT 5 = (5A NAND 5B NAND 5C NAND 5D) 26 I AR2 E3-13 INPUT 6A 27 I AS2 E3-12 INPUT 6B 28 I AT2 E3-10 INPUT 6C 29 I AU2 E3-9 INPUT 6D 30 O AV2 E3-8 OUTPUT 6 = (6A NAND 6B NAND 6C NAND 6D) space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn on comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn on comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit 1 I AA1 E1-2 INPUT 1A 2 I AB1 E1-1 INPUT 1B 3 I AC1 E1-4 INPUT 1C 4 I AD1 E1-5 INPUT 1D 5 O AE1 E1-6 OUTPUT 1 = (1A NAND 1B NAND 1C NAND 1D) 6 I AD2 E1-13 INPUT 2A 7 I AE2 E1-12 INPUT 2B 8 I AF2 E1-10 INPUT 2C 9 I AH2 E1-9 INPUT 2D 10 O AJ2 E1-8 OUTPUT 2 = (2A NAND 2B NAND 2C NAND 2D) 11 I AF1 E2-2 INPUT 3A 12 I AH1 E2-1 INPUT 3B 13 I AJ1 E2-4 INPUT 3C 14 I AK1 E2-5 INPUT 3D 15 O AL1 E2-6 OUTPUT 3 = (3A NAND 3B NAND 3C NAND 3D) 16 I AK2 E2-13 INPUT 4A 17 I AL2 E2-12 INPUT 4B 18 I AM2 E2-10 INPUT 4C 19 I AN2 E2-9 INPUT 4D 20 O AP2 E2-8 OUTPUT 4 = (4A NAND 4B NAND 4C NAND 4D) 21 I AM1 E3-1 INPUT 5A 22 I AN1 E3-2 INPUT 5B 23 I AP1 E3-4 INPUT 5C 24 I AR1 E3-5 INPUT 5D 25 O AS1 E3-6 OUTPUT 5 = (5A NAND 5B NAND 5C NAND 5D) 26 I AR2 E3-13 INPUT 6A 27 I AS2 E3-12 INPUT 6B 28 I AT2 E3-10 INPUT 6C 29 I AU2 E3-9 INPUT 6D 30 O AV2 E3-8 OUTPUT 6 = (6A NAND 6B NAND 6C NAND 6D) space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn on comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn on comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit 1 I AA1 E1-2 INPUT 1A 2 I AB1 E1-1 INPUT 1B 3 I AC1 E1-4 INPUT 1C 4 I AD1 E1-5 INPUT 1D 5 O AE1 E1-6 OUTPUT 1 = (1A NAND 1B NAND 1C NAND 1D) 6 I AD2 E1-13 INPUT 2A 7 I AE2 E1-12 INPUT 2B 8 I AF2 E1-10 INPUT 2C 9 I AH2 E1-9 INPUT 2D 10 O AJ2 E1-8 OUTPUT 2 = (2A NAND 2B NAND 2C NAND 2D) 11 I AF1 E2-2 INPUT 3A 12 I AH1 E2-1 INPUT 3B 13 I AJ1 E2-4 INPUT 3C 14 I AK1 E2-5 INPUT 3D 15 O AL1 E2-6 OUTPUT 3 = (3A NAND 3B NAND 3C NAND 3D) 16 I AK2 E2-13 INPUT 4A 17 I AL2 E2-12 INPUT 4B 18 I AM2 E2-10 INPUT 4C 19 I AN2 E2-9 INPUT 4D 20 O AP2 E2-8 OUTPUT 4 = (4A NAND 4B NAND 4C NAND 4D) 21 I AM1 E3-1 INPUT 5A 22 I AN1 E3-2 INPUT 5B 23 I AP1 E3-4 INPUT 5C 24 I AR1 E3-5 INPUT 5D 25 O AS1 E3-6 OUTPUT 5 = (5A NAND 5B NAND 5C NAND 5D) 26 I AR2 E3-13 INPUT 6A 27 I AS2 E3-12 INPUT 6B 28 I AT2 E3-10 INPUT 6C 29 I AU2 E3-9 INPUT 6D 30 O AV2 E3-8 OUTPUT 6 = (6A NAND 6B NAND 6C NAND 6D) space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn on comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn on comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit 1 I AA1 E1-2 INPUT 1A 2 I AB1 E1-1 INPUT 1B 3 I AC1 E1-4 INPUT 1C 4 I AD1 E1-5 INPUT 1D 5 O AE1 E1-6 OUTPUT 1 = (1A NAND 1B NAND 1C NAND 1D) 6 I AD2 E1-13 INPUT 2A 7 I AE2 E1-12 INPUT 2B 8 I AF2 E1-10 INPUT 2C 9 I AH2 E1-9 INPUT 2D 10 O AJ2 E1-8 OUTPUT 2 = (2A NAND 2B NAND 2C NAND 2D) 11 I AF1 E2-2 INPUT 3A 12 I AH1 E2-1 INPUT 3B 13 I AJ1 E2-4 INPUT 3C 14 I AK1 E2-5 INPUT 3D 15 O AL1 E2-6 OUTPUT 3 = (3A NAND 3B NAND 3C NAND 3D) 16 I AK2 E2-13 INPUT 4A 17 I AL2 E2-12 INPUT 4B 18 I AM2 E2-10 INPUT 4C 19 I AN2 E2-9 INPUT 4D 20 O AP2 E2-8 OUTPUT 4 = (4A NAND 4B NAND 4C NAND 4D) 21 I AM1 E3-1 INPUT 5A 22 I AN1 E3-2 INPUT 5B 23 I AP1 E3-4 INPUT 5C 24 I AR1 E3-5 INPUT 5D 25 O AS1 E3-6 OUTPUT 5 = (5A NAND 5B NAND 5C NAND 5D) 26 I AR2 E3-13 INPUT 6A 27 I AS2 E3-12 INPUT 6B 28 I AT2 E3-10 INPUT 6C 29 I AU2 E3-9 INPUT 6D 30 O AV2 E3-8 OUTPUT 6 = (6A NAND 6B NAND 6C NAND 6D) space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn on comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn on comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit 1 I AA1 E1-2 INPUT 1A 2 I AB1 E1-1 INPUT 1B 3 I AC1 E1-4 INPUT 1C 4 I AD1 E1-5 INPUT 1D 5 O AE1 E1-6 OUTPUT 1 = (1A NAND 1B NAND 1C NAND 1D) 6 I AD2 E1-13 INPUT 2A 7 I AE2 E1-12 INPUT 2B 8 I AF2 E1-10 INPUT 2C 9 I AH2 E1-9 INPUT 2D 10 O AJ2 E1-8 OUTPUT 2 = (2A NAND 2B NAND 2C NAND 2D) 11 I AF1 E2-2 INPUT 3A 12 I AH1 E2-1 INPUT 3B 13 I AJ1 E2-4 INPUT 3C 14 I AK1 E2-5 INPUT 3D 15 O AL1 E2-6 OUTPUT 3 = (3A NAND 3B NAND 3C NAND 3D) 16 I AK2 E2-13 INPUT 4A 17 I AL2 E2-12 INPUT 4B 18 I AM2 E2-10 INPUT 4C 19 I AN2 E2-9 INPUT 4D 20 O AP2 E2-8 OUTPUT 4 = (4A NAND 4B NAND 4C NAND 4D) 21 I AM1 E3-1 INPUT 5A 22 I AN1 E3-2 INPUT 5B 23 I AP1 E3-4 INPUT 5C 24 I AR1 E3-5 INPUT 5D 25 O AS1 E3-6 OUTPUT 5 = (5A NAND 5B NAND 5C NAND 5D) 26 I AR2 E3-13 INPUT 6A 27 I AS2 E3-12 INPUT 6B 28 I AT2 E3-10 INPUT 6C 29 I AU2 E3-9 INPUT 6D 30 O AV2 E3-8 OUTPUT 6 = (6A NAND 6B NAND 6C NAND 6D) space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn on comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn on comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit 1 I AA1 E1-2 INPUT 1A 2 I AB1 E1-1 INPUT 1B 3 I AC1 E1-4 INPUT 1C 4 I AD1 E1-5 INPUT 1D 5 O AE1 E1-6 OUTPUT 1 = (1A NAND 1B NAND 1C NAND 1D) 6 I AD2 E1-13 INPUT 2A 7 I AE2 E1-12 INPUT 2B 8 I AF2 E1-10 INPUT 2C 9 I AH2 E1-9 INPUT 2D 10 O AJ2 E1-8 OUTPUT 2 = (2A NAND 2B NAND 2C NAND 2D) 11 I AF1 E2-2 INPUT 3A 12 I AH1 E2-1 INPUT 3B 13 I AJ1 E2-4 INPUT 3C 14 I AK1 E2-5 INPUT 3D 15 O AL1 E2-6 OUTPUT 3 = (3A NAND 3B NAND 3C NAND 3D) 16 I AK2 E2-13 INPUT 4A 17 I AL2 E2-12 INPUT 4B 18 I AM2 E2-10 INPUT 4C 19 I AN2 E2-9 INPUT 4D 20 O AP2 E2-8 OUTPUT 4 = (4A NAND 4B NAND 4C NAND 4D) 21 I AM1 E3-1 INPUT 5A 22 I AN1 E3-2 INPUT 5B 23 I AP1 E3-4 INPUT 5C 24 I AR1 E3-5 INPUT 5D 25 O AS1 E3-6 OUTPUT 5 = (5A NAND 5B NAND 5C NAND 5D) 26 I AR2 E3-13 INPUT 6A 27 I AS2 E3-12 INPUT 6B 28 I AT2 E3-10 INPUT 6C 29 I AU2 E3-9 INPUT 6D 30 O AV2 E3-8 OUTPUT 6 = (6A NAND 6B NAND 6C NAND 6D) space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn on comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit IODIR 01/00 08E1h 00001000 11100001 4310h FFFAh FFFFh F0FFh GPPU 0D/0C 0000h 00000000 00000000 0000h 0000h 0000h 0000h OLAT 15/14 F71Eh 11110111 00011110 BCEFh 0001h 0000h 0000h GPIO 13/12 F7DEh 11110111 11011110 BCEFh 0001h 0000h 0000h IODIR 01/00 08E1h 00001000 11100001 4310h FFFAh FFFFh F0FFh GPPU 0D/0C 0000h 00000000 00000000 0000h 0000h 0000h 0000h OLAT 15/14 F71Eh 11110111 00011110 BCEFh 0001h 0000h 0000h GPIO 13/12 F7DEh 11110111 11011110 BCEFh 0001h 0000h 0000h space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn on comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit comment_flag is 1 space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn off comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit failure mode analysis: pin: 5 O AE1 E1-6 OUTPUT 1 = (1A NAND 1B NAND 1C NAND 1D) SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEDEFHJFHJKLKLMNPMNPRSRSTUV SIDE 111112222211111222221111122222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO fails LO: 1111 1111111111111111111111111 fails LO: 0000 0000000000000000000000000 fails HI: fails HI: space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn off comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit up to this point: PINS that are always low 5 O AE1 E1-6 OUTPUT 1 = (1A NAND 1B NAND 1C NAND 1D) PINS that are always high space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn off comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEDEFHJFHJKLKLMNPMNPRSRSTUV SIDE 111112222211111222221111122222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO source: 000010000100001000010000100001 changed: 0000 0000100001000010000100001 step 1 000000000100001000010000100001 fail ^ space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn off comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEDEFHJFHJKLKLMNPMNPRSRSTUV SIDE 111112222211111222221111122222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO source: 00001 changed: step 2 000000000100001000010000100001 fail ^ space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn off comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEDEFHJFHJKLKLMNPMNPRSRSTUV SIDE 111112222211111222221111122222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO source: 00011 changed: 1 step 3 000100000100001000010000100001 fail ^ space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn off comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEDEFHJFHJKLKLMNPMNPRSRSTUV SIDE 111112222211111222221111122222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO source: 00101 changed: 10 step 4 001000000100001000010000100001 fail ^ space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn off comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEDEFHJFHJKLKLMNPMNPRSRSTUV SIDE 111112222211111222221111122222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO source: 00111 changed: 1 step 5 001100000100001000010000100001 fail ^ space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn off comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEDEFHJFHJKLKLMNPMNPRSRSTUV SIDE 111112222211111222221111122222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO source: 01001 changed: 100 step 6 010000000100001000010000100001 fail ^ space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn off comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEDEFHJFHJKLKLMNPMNPRSRSTUV SIDE 111112222211111222221111122222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO source: 01011 changed: 1 step 7 010100000100001000010000100001 fail ^ space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn off comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEDEFHJFHJKLKLMNPMNPRSRSTUV SIDE 111112222211111222221111122222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO source: 01101 changed: 10 step 8 011000000100001000010000100001 fail ^ space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn off comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEDEFHJFHJKLKLMNPMNPRSRSTUV SIDE 111112222211111222221111122222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO source: 01111 changed: 1 step 9 011100000100001000010000100001 fail ^ space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn off comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEDEFHJFHJKLKLMNPMNPRSRSTUV SIDE 111112222211111222221111122222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO source: 10001 changed: 1000 step 10 100000000100001000010000100001 fail ^ space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn off comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEDEFHJFHJKLKLMNPMNPRSRSTUV SIDE 111112222211111222221111122222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO source: 10011 changed: 1 step 11 100100000100001000010000100001 fail ^ space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn off comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEDEFHJFHJKLKLMNPMNPRSRSTUV SIDE 111112222211111222221111122222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO source: 10101 changed: 10 step 12 101000000100001000010000100001 fail ^ space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn off comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEDEFHJFHJKLKLMNPMNPRSRSTUV SIDE 111112222211111222221111122222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO source: 10111 changed: 1 step 13 101100000100001000010000100001 fail ^ space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn off comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEDEFHJFHJKLKLMNPMNPRSRSTUV SIDE 111112222211111222221111122222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO source: 11001 changed: 100 step 14 110000000100001000010000100001 fail ^ space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn off comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEDEFHJFHJKLKLMNPMNPRSRSTUV SIDE 111112222211111222221111122222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO source: 11011 changed: 1 step 15 110100000100001000010000100001 fail ^ space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn off comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEDEFHJFHJKLKLMNPMNPRSRSTUV SIDE 111112222211111222221111122222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO source: 11101 changed: 10 step 16 111000000100001000010000100001 fail ^ space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn off comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit source: 11110 changed: 1 step 17 111100000100001000010000100001 SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEDEFHJFHJKLKLMNPMNPRSRSTUV SIDE 111112222211111222221111122222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO source: 00001 changed: 0000 step 18 000000000100001000010000100001 fail ^ space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn off comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEDEFHJFHJKLKLMNPMNPRSRSTUV SIDE 111112222211111222221111122222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO source: 00001 changed: step 19 000000000100001000010000100001 fail ^ space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn off comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEDEFHJFHJKLKLMNPMNPRSRSTUV SIDE 111112222211111222221111122222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO source: 00011 changed: 1 step 20 000000001100001000010000100001 fail ^ space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn off comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEDEFHJFHJKLKLMNPMNPRSRSTUV SIDE 111112222211111222221111122222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO source: 00101 changed: 10 step 21 000000010100001000010000100001 fail ^ space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn off comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEDEFHJFHJKLKLMNPMNPRSRSTUV SIDE 111112222211111222221111122222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO source: 00111 changed: 1 step 22 000000011100001000010000100001 fail ^ space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn off comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEDEFHJFHJKLKLMNPMNPRSRSTUV SIDE 111112222211111222221111122222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO source: 01001 changed: 100 step 23 000000100100001000010000100001 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEDEFHJFHJKLKLMNPMNPRSRSTUV SIDE 111112222211111222221111122222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO source: 01011 changed: 1 step 24 000000101100001000010000100001 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEDEFHJFHJKLKLMNPMNPRSRSTUV SIDE 111112222211111222221111122222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO source: 01101 changed: 10 step 25 000000110100001000010000100001 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEDEFHJFHJKLKLMNPMNPRSRSTUV SIDE 111112222211111222221111122222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO source: 01111 changed: 1 step 26 000000111100001000010000100001 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEDEFHJFHJKLKLMNPMNPRSRSTUV SIDE 111112222211111222221111122222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO source: 10001 changed: 1000 step 27 000001000100001000010000100001 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEDEFHJFHJKLKLMNPMNPRSRSTUV SIDE 111112222211111222221111122222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO source: 10011 changed: 1 step 28 000001001100001000010000100001 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEDEFHJFHJKLKLMNPMNPRSRSTUV SIDE 111112222211111222221111122222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO source: 10101 changed: 10 step 29 000001010100001000010000100001 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEDEFHJFHJKLKLMNPMNPRSRSTUV SIDE 111112222211111222221111122222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO source: 10111 changed: 1 step 30 000001011100001000010000100001 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEDEFHJFHJKLKLMNPMNPRSRSTUV SIDE 111112222211111222221111122222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO source: 11001 changed: 100 step 31 000001100100001000010000100001 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEDEFHJFHJKLKLMNPMNPRSRSTUV SIDE 111112222211111222221111122222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO source: 11011 changed: 1 step 32 000001101100001000010000100001 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEDEFHJFHJKLKLMNPMNPRSRSTUV SIDE 111112222211111222221111122222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO source: 11101 changed: 10 step 33 000001110100001000010000100001 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEDEFHJFHJKLKLMNPMNPRSRSTUV SIDE 111112222211111222221111122222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO source: 11110 changed: 10 step 34 000001111000001000010000100001 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEDEFHJFHJKLKLMNPMNPRSRSTUV SIDE 111112222211111222221111122222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO source: 00001 changed: 00001 step 35 000000000100001000010000100001 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEDEFHJFHJKLKLMNPMNPRSRSTUV SIDE 111112222211111222221111122222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO source: 00001 changed: step 36 000000000100001000010000100001 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEDEFHJFHJKLKLMNPMNPRSRSTUV SIDE 111112222211111222221111122222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO source: 00011 changed: 1 step 37 000000000100011000010000100001 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEDEFHJFHJKLKLMNPMNPRSRSTUV SIDE 111112222211111222221111122222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO source: 00101 changed: 10 step 38 000000000100101000010000100001 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEDEFHJFHJKLKLMNPMNPRSRSTUV SIDE 111112222211111222221111122222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO source: 00111 changed: 1 step 39 000000000100111000010000100001 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEDEFHJFHJKLKLMNPMNPRSRSTUV SIDE 111112222211111222221111122222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO source: 01001 changed: 100 step 40 000000000101001000010000100001 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEDEFHJFHJKLKLMNPMNPRSRSTUV SIDE 111112222211111222221111122222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO source: 01011 changed: 1 step 41 000000000101011000010000100001 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEDEFHJFHJKLKLMNPMNPRSRSTUV SIDE 111112222211111222221111122222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO source: 01101 changed: 10 step 42 000000000101101000010000100001 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEDEFHJFHJKLKLMNPMNPRSRSTUV SIDE 111112222211111222221111122222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO source: 01111 changed: 1 step 43 000000000101111000010000100001 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEDEFHJFHJKLKLMNPMNPRSRSTUV SIDE 111112222211111222221111122222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO source: 10001 changed: 1000 step 44 000000000110001000010000100001 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEDEFHJFHJKLKLMNPMNPRSRSTUV SIDE 111112222211111222221111122222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO source: 10011 changed: 1 step 45 000000000110011000010000100001 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEDEFHJFHJKLKLMNPMNPRSRSTUV SIDE 111112222211111222221111122222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO source: 10101 changed: 10 step 46 000000000110101000010000100001 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEDEFHJFHJKLKLMNPMNPRSRSTUV SIDE 111112222211111222221111122222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO source: 10111 changed: 1 step 47 000000000110111000010000100001 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEDEFHJFHJKLKLMNPMNPRSRSTUV SIDE 111112222211111222221111122222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO source: 11001 changed: 100 step 48 000000000111001000010000100001 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEDEFHJFHJKLKLMNPMNPRSRSTUV SIDE 111112222211111222221111122222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO source: 11011 changed: 1 step 49 000000000111011000010000100001 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEDEFHJFHJKLKLMNPMNPRSRSTUV SIDE 111112222211111222221111122222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO source: 11101 changed: 10 step 50 000000000111101000010000100001 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEDEFHJFHJKLKLMNPMNPRSRSTUV SIDE 111112222211111222221111122222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO source: 11110 changed: 10 step 51 000000000111110000010000100001 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEDEFHJFHJKLKLMNPMNPRSRSTUV SIDE 111112222211111222221111122222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO source: 00001 changed: 00001 step 52 000000000100001000010000100001 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEDEFHJFHJKLKLMNPMNPRSRSTUV SIDE 111112222211111222221111122222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO source: 00001 changed: step 53 000000000100001000010000100001 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEDEFHJFHJKLKLMNPMNPRSRSTUV SIDE 111112222211111222221111122222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO source: 00011 changed: 1 step 54 000000000100001000110000100001 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEDEFHJFHJKLKLMNPMNPRSRSTUV SIDE 111112222211111222221111122222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO source: 00101 changed: 10 step 55 000000000100001001010000100001 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEDEFHJFHJKLKLMNPMNPRSRSTUV SIDE 111112222211111222221111122222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO source: 00111 changed: 1 step 56 000000000100001001110000100001 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEDEFHJFHJKLKLMNPMNPRSRSTUV SIDE 111112222211111222221111122222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO source: 01001 changed: 100 step 57 000000000100001010010000100001 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEDEFHJFHJKLKLMNPMNPRSRSTUV SIDE 111112222211111222221111122222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO source: 01011 changed: 1 step 58 000000000100001010110000100001 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEDEFHJFHJKLKLMNPMNPRSRSTUV SIDE 111112222211111222221111122222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO source: 01101 changed: 10 step 59 000000000100001011010000100001 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEDEFHJFHJKLKLMNPMNPRSRSTUV SIDE 111112222211111222221111122222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO source: 01111 changed: 1 step 60 000000000100001011110000100001 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEDEFHJFHJKLKLMNPMNPRSRSTUV SIDE 111112222211111222221111122222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO source: 10001 changed: 1000 step 61 000000000100001100010000100001 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEDEFHJFHJKLKLMNPMNPRSRSTUV SIDE 111112222211111222221111122222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO source: 10011 changed: 1 step 62 000000000100001100110000100001 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEDEFHJFHJKLKLMNPMNPRSRSTUV SIDE 111112222211111222221111122222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO source: 10101 changed: 10 step 63 000000000100001101010000100001 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEDEFHJFHJKLKLMNPMNPRSRSTUV SIDE 111112222211111222221111122222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO source: 10111 changed: 1 step 64 000000000100001101110000100001 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEDEFHJFHJKLKLMNPMNPRSRSTUV SIDE 111112222211111222221111122222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO source: 11001 changed: 100 step 65 000000000100001110010000100001 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEDEFHJFHJKLKLMNPMNPRSRSTUV SIDE 111112222211111222221111122222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO source: 11011 changed: 1 step 66 000000000100001110110000100001 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEDEFHJFHJKLKLMNPMNPRSRSTUV SIDE 111112222211111222221111122222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO source: 11101 changed: 10 step 67 000000000100001111010000100001 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEDEFHJFHJKLKLMNPMNPRSRSTUV SIDE 111112222211111222221111122222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO source: 11110 changed: 10 step 68 000000000100001111100000100001 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEDEFHJFHJKLKLMNPMNPRSRSTUV SIDE 111112222211111222221111122222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO source: 00001 changed: 00001 step 69 000000000100001000010000100001 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEDEFHJFHJKLKLMNPMNPRSRSTUV SIDE 111112222211111222221111122222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO source: 00001 changed: step 70 000000000100001000010000100001 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEDEFHJFHJKLKLMNPMNPRSRSTUV SIDE 111112222211111222221111122222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO source: 00011 changed: 1 step 71 000000000100001000010001100001 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEDEFHJFHJKLKLMNPMNPRSRSTUV SIDE 111112222211111222221111122222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO source: 00101 changed: 10 step 72 000000000100001000010010100001 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEDEFHJFHJKLKLMNPMNPRSRSTUV SIDE 111112222211111222221111122222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO source: 00111 changed: 1 step 73 000000000100001000010011100001 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEDEFHJFHJKLKLMNPMNPRSRSTUV SIDE 111112222211111222221111122222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO source: 01001 changed: 100 step 74 000000000100001000010100100001 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEDEFHJFHJKLKLMNPMNPRSRSTUV SIDE 111112222211111222221111122222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO source: 01011 changed: 1 step 75 000000000100001000010101100001 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEDEFHJFHJKLKLMNPMNPRSRSTUV SIDE 111112222211111222221111122222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO source: 01101 changed: 10 step 76 000000000100001000010110100001 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEDEFHJFHJKLKLMNPMNPRSRSTUV SIDE 111112222211111222221111122222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO source: 01111 changed: 1 step 77 000000000100001000010111100001 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEDEFHJFHJKLKLMNPMNPRSRSTUV SIDE 111112222211111222221111122222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO source: 10001 changed: 1000 step 78 000000000100001000011000100001 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEDEFHJFHJKLKLMNPMNPRSRSTUV SIDE 111112222211111222221111122222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO source: 10011 changed: 1 step 79 000000000100001000011001100001 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEDEFHJFHJKLKLMNPMNPRSRSTUV SIDE 111112222211111222221111122222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO source: 10101 changed: 10 step 80 000000000100001000011010100001 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEDEFHJFHJKLKLMNPMNPRSRSTUV SIDE 111112222211111222221111122222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO source: 10111 changed: 1 step 81 000000000100001000011011100001 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEDEFHJFHJKLKLMNPMNPRSRSTUV SIDE 111112222211111222221111122222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO source: 11001 changed: 100 step 82 000000000100001000011100100001 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEDEFHJFHJKLKLMNPMNPRSRSTUV SIDE 111112222211111222221111122222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO source: 11011 changed: 1 step 83 000000000100001000011101100001 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEDEFHJFHJKLKLMNPMNPRSRSTUV SIDE 111112222211111222221111122222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO source: 11101 changed: 10 step 84 000000000100001000011110100001 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEDEFHJFHJKLKLMNPMNPRSRSTUV SIDE 111112222211111222221111122222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO source: 11110 changed: 10 step 85 000000000100001000011111000001 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEDEFHJFHJKLKLMNPMNPRSRSTUV SIDE 111112222211111222221111122222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO source: 00001 changed: 00001 step 86 000000000100001000010000100001 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEDEFHJFHJKLKLMNPMNPRSRSTUV SIDE 111112222211111222221111122222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO source: 00001 changed: step 87 000000000100001000010000100001 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEDEFHJFHJKLKLMNPMNPRSRSTUV SIDE 111112222211111222221111122222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO source: 00011 changed: 1 step 88 000000000100001000010000100011 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEDEFHJFHJKLKLMNPMNPRSRSTUV SIDE 111112222211111222221111122222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO source: 00101 changed: 10 step 89 000000000100001000010000100101 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEDEFHJFHJKLKLMNPMNPRSRSTUV SIDE 111112222211111222221111122222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO source: 00111 changed: 1 step 90 000000000100001000010000100111 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEDEFHJFHJKLKLMNPMNPRSRSTUV SIDE 111112222211111222221111122222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO source: 01001 changed: 100 step 91 000000000100001000010000101001 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEDEFHJFHJKLKLMNPMNPRSRSTUV SIDE 111112222211111222221111122222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO source: 01011 changed: 1 step 92 000000000100001000010000101011 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEDEFHJFHJKLKLMNPMNPRSRSTUV SIDE 111112222211111222221111122222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO source: 01101 changed: 10 step 93 000000000100001000010000101101 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEDEFHJFHJKLKLMNPMNPRSRSTUV SIDE 111112222211111222221111122222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO source: 01111 changed: 1 step 94 000000000100001000010000101111 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEDEFHJFHJKLKLMNPMNPRSRSTUV SIDE 111112222211111222221111122222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO source: 10001 changed: 1000 step 95 000000000100001000010000110001 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEDEFHJFHJKLKLMNPMNPRSRSTUV SIDE 111112222211111222221111122222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO source: 10011 changed: 1 step 96 000000000100001000010000110011 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEDEFHJFHJKLKLMNPMNPRSRSTUV SIDE 111112222211111222221111122222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO source: 10101 changed: 10 step 97 000000000100001000010000110101 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEDEFHJFHJKLKLMNPMNPRSRSTUV SIDE 111112222211111222221111122222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO source: 10111 changed: 1 step 98 000000000100001000010000110111 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEDEFHJFHJKLKLMNPMNPRSRSTUV SIDE 111112222211111222221111122222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO source: 11001 changed: 100 step 99 000000000100001000010000111001 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEDEFHJFHJKLKLMNPMNPRSRSTUV SIDE 111112222211111222221111122222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO source: 11011 changed: 1 step 100 000000000100001000010000111011 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEDEFHJFHJKLKLMNPMNPRSRSTUV SIDE 111112222211111222221111122222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO source: 11101 changed: 10 step 101 000000000100001000010000111101 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEDEFHJFHJKLKLMNPMNPRSRSTUV SIDE 111112222211111222221111122222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO source: 11110 changed: 10 step 102 000000000100001000010000111110 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEDEFHJFHJKLKLMNPMNPRSRSTUV SIDE 111112222211111222221111122222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO source: 00001 changed: 00001 step 103 000000000100001000010000100001 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEDEFHJFHJKLKLMNPMNPRSRSTUV SIDE 111112222211111222221111122222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO source: 000010000100001000010000100001 changed: step 104 000000000100001000010000100001 fail ^ source: 111101111011110111101111011110 changed: 1111 1111011110111101111011110 step 105 111101111011110111101111011110 SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEDEFHJFHJKLKLMNPMNPRSRSTUV SIDE 111112222211111222221111122222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO source: 00001 changed: 0000 step 106 000001111011110111101111011110 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEDEFHJFHJKLKLMNPMNPRSRSTUV SIDE 111112222211111222221111122222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO source: 00011 changed: 1 step 107 000101111011110111101111011110 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEDEFHJFHJKLKLMNPMNPRSRSTUV SIDE 111112222211111222221111122222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO source: 00101 changed: 10 step 108 001001111011110111101111011110 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEDEFHJFHJKLKLMNPMNPRSRSTUV SIDE 111112222211111222221111122222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO source: 00111 changed: 1 step 109 001101111011110111101111011110 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEDEFHJFHJKLKLMNPMNPRSRSTUV SIDE 111112222211111222221111122222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO source: 01001 changed: 100 step 110 010001111011110111101111011110 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEDEFHJFHJKLKLMNPMNPRSRSTUV SIDE 111112222211111222221111122222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO source: 01011 changed: 1 step 111 010101111011110111101111011110 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEDEFHJFHJKLKLMNPMNPRSRSTUV SIDE 111112222211111222221111122222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO source: 01101 changed: 10 step 112 011001111011110111101111011110 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEDEFHJFHJKLKLMNPMNPRSRSTUV SIDE 111112222211111222221111122222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO source: 01111 changed: 1 step 113 011101111011110111101111011110 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEDEFHJFHJKLKLMNPMNPRSRSTUV SIDE 111112222211111222221111122222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO source: 10001 changed: 1000 step 114 100001111011110111101111011110 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEDEFHJFHJKLKLMNPMNPRSRSTUV SIDE 111112222211111222221111122222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO source: 10011 changed: 1 step 115 100101111011110111101111011110 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEDEFHJFHJKLKLMNPMNPRSRSTUV SIDE 111112222211111222221111122222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO source: 10101 changed: 10 step 116 101001111011110111101111011110 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEDEFHJFHJKLKLMNPMNPRSRSTUV SIDE 111112222211111222221111122222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO source: 10111 changed: 1 step 117 101101111011110111101111011110 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEDEFHJFHJKLKLMNPMNPRSRSTUV SIDE 111112222211111222221111122222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO source: 11001 changed: 100 step 118 110001111011110111101111011110 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEDEFHJFHJKLKLMNPMNPRSRSTUV SIDE 111112222211111222221111122222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO source: 11011 changed: 1 step 119 110101111011110111101111011110 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEDEFHJFHJKLKLMNPMNPRSRSTUV SIDE 111112222211111222221111122222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO source: 11101 changed: 10 step 120 111001111011110111101111011110 fail ^ source: 11110 changed: 1 step 121 111101111011110111101111011110 source: 00001 changed: 00001 step 122 111100000111110111101111011110 source: 00011 changed: 1 step 123 111100001111110111101111011110 source: 00101 changed: 10 step 124 111100010111110111101111011110 source: 00111 changed: 1 step 125 111100011111110111101111011110 source: 01001 changed: 100 step 126 111100100111110111101111011110 source: 01011 changed: 1 step 127 111100101111110111101111011110 source: 01101 changed: 10 step 128 111100110111110111101111011110 source: 01111 changed: 1 step 129 111100111111110111101111011110 source: 10001 changed: 1000 step 130 111101000111110111101111011110 source: 10011 changed: 1 step 131 111101001111110111101111011110 source: 10101 changed: 10 step 132 111101010111110111101111011110 source: 10111 changed: 1 step 133 111101011111110111101111011110 source: 11001 changed: 100 step 134 111101100111110111101111011110 source: 11011 changed: 1 step 135 111101101111110111101111011110 source: 11101 changed: 10 step 136 111101110111110111101111011110 source: 11110 changed: 10 step 137 111101111011110111101111011110 source: 00001 changed: 00001 step 138 111101111000001111101111011110 source: 00011 changed: 1 step 139 111101111000011111101111011110 source: 00101 changed: 10 step 140 111101111000101111101111011110 source: 00111 changed: 1 step 141 111101111000111111101111011110 source: 01001 changed: 100 step 142 111101111001001111101111011110 source: 01011 changed: 1 step 143 111101111001011111101111011110 source: 01101 changed: 10 step 144 111101111001101111101111011110 source: 01111 changed: 1 step 145 111101111001111111101111011110 source: 10001 changed: 1000 step 146 111101111010001111101111011110 source: 10011 changed: 1 step 147 111101111010011111101111011110 source: 10101 changed: 10 step 148 111101111010101111101111011110 source: 10111 changed: 1 step 149 111101111010111111101111011110 source: 11001 changed: 100 step 150 111101111011001111101111011110 source: 11011 changed: 1 step 151 111101111011011111101111011110 source: 11101 changed: 10 step 152 111101111011101111101111011110 source: 11110 changed: 10 step 153 111101111011110111101111011110 source: 00001 changed: 00001 step 154 111101111011110000011111011110 source: 00011 changed: 1 step 155 111101111011110000111111011110 source: 00101 changed: 10 step 156 111101111011110001011111011110 source: 00111 changed: 1 step 157 111101111011110001111111011110 source: 01001 changed: 100 step 158 111101111011110010011111011110 source: 01011 changed: 1 step 159 111101111011110010111111011110 source: 01101 changed: 10 step 160 111101111011110011011111011110 source: 01111 changed: 1 step 161 111101111011110011111111011110 source: 10001 changed: 1000 step 162 111101111011110100011111011110 source: 10011 changed: 1 step 163 111101111011110100111111011110 source: 10101 changed: 10 step 164 111101111011110101011111011110 source: 10111 changed: 1 step 165 111101111011110101111111011110 source: 11001 changed: 100 step 166 111101111011110110011111011110 source: 11011 changed: 1 step 167 111101111011110110111111011110 source: 11101 changed: 10 step 168 111101111011110111011111011110 source: 11110 changed: 10 step 169 111101111011110111101111011110 source: 00001 changed: 00001 step 170 111101111011110111100000111110 source: 00011 changed: 1 step 171 111101111011110111100001111110 source: 00101 changed: 10 step 172 111101111011110111100010111110 source: 00111 changed: 1 step 173 111101111011110111100011111110 source: 01001 changed: 100 step 174 111101111011110111100100111110 source: 01011 changed: 1 step 175 111101111011110111100101111110 source: 01101 changed: 10 step 176 111101111011110111100110111110 source: 01111 changed: 1 step 177 111101111011110111100111111110 source: 10001 changed: 1000 step 178 111101111011110111101000111110 source: 10011 changed: 1 step 179 111101111011110111101001111110 source: 10101 changed: 10 step 180 111101111011110111101010111110 source: 10111 changed: 1 step 181 111101111011110111101011111110 source: 11001 changed: 100 step 182 111101111011110111101100111110 source: 11011 changed: 1 step 183 111101111011110111101101111110 source: 11101 changed: 10 step 184 111101111011110111101110111110 source: 11110 changed: 10 step 185 111101111011110111101111011110 source: 00001 changed: 00001 step 186 111101111011110111101111000001 source: 00011 changed: 1 step 187 111101111011110111101111000011 source: 00101 changed: 10 step 188 111101111011110111101111000101 source: 00111 changed: 1 step 189 111101111011110111101111000111 source: 01001 changed: 100 step 190 111101111011110111101111001001 source: 01011 changed: 1 step 191 111101111011110111101111001011 source: 01101 changed: 10 step 192 111101111011110111101111001101 source: 01111 changed: 1 step 193 111101111011110111101111001111 source: 10001 changed: 1000 step 194 111101111011110111101111010001 source: 10011 changed: 1 step 195 111101111011110111101111010011 source: 10101 changed: 10 step 196 111101111011110111101111010101 source: 10111 changed: 1 step 197 111101111011110111101111010111 source: 11001 changed: 100 step 198 111101111011110111101111011001 source: 11011 changed: 1 step 199 111101111011110111101111011011 source: 11101 changed: 10 step 200 111101111011110111101111011101 source: 11110 changed: 10 step 201 111101111011110111101111011110 source: 111101111011110111101111011110 changed: step 202 111101111011110111101111011110 test 26: *** FAIL *************************** 118 steps failed SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEDEFHJFHJKLKLMNPMNPRSRSTUV SIDE 111112222211111222221111122222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO this fail O all fails O was hi 1111 1111111111111111111111111 rising ^^^^ ^^^^^^^^^^^^^^^^^^^^^^^^^ falling vvvv vvvvvvvvvvvvvvvvvvvvvvvvv was lo 000000000000000000000000000000 total fails 26, total passes 0 space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn off comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEDEFHJFHJKLKLMNPMNPRSRSTUV SIDE 111112222211111222221111122222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO source: 000010000100001000010000100001 changed: 0000 0000100001000010000100001 step 1 000000000100001000010000100001 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEDEFHJFHJKLKLMNPMNPRSRSTUV SIDE 111112222211111222221111122222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO source: 00001 changed: step 2 000000000100001000010000100001 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEDEFHJFHJKLKLMNPMNPRSRSTUV SIDE 111112222211111222221111122222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO source: 00011 changed: 1 step 3 000100000100001000010000100001 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEDEFHJFHJKLKLMNPMNPRSRSTUV SIDE 111112222211111222221111122222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO source: 00101 changed: 10 step 4 001000000100001000010000100001 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEDEFHJFHJKLKLMNPMNPRSRSTUV SIDE 111112222211111222221111122222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO source: 00111 changed: 1 step 5 001100000100001000010000100001 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEDEFHJFHJKLKLMNPMNPRSRSTUV SIDE 111112222211111222221111122222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO source: 01001 changed: 100 step 6 010000000100001000010000100001 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEDEFHJFHJKLKLMNPMNPRSRSTUV SIDE 111112222211111222221111122222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO source: 01011 changed: 1 step 7 010100000100001000010000100001 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEDEFHJFHJKLKLMNPMNPRSRSTUV SIDE 111112222211111222221111122222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO source: 01101 changed: 10 step 8 011000000100001000010000100001 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEDEFHJFHJKLKLMNPMNPRSRSTUV SIDE 111112222211111222221111122222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO source: 01111 changed: 1 step 9 011100000100001000010000100001 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEDEFHJFHJKLKLMNPMNPRSRSTUV SIDE 111112222211111222221111122222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO source: 10001 changed: 1000 step 10 100000000100001000010000100001 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEDEFHJFHJKLKLMNPMNPRSRSTUV SIDE 111112222211111222221111122222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO source: 10011 changed: 1 step 11 100100000100001000010000100001 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEDEFHJFHJKLKLMNPMNPRSRSTUV SIDE 111112222211111222221111122222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO source: 10101 changed: 10 step 12 101000000100001000010000100001 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEDEFHJFHJKLKLMNPMNPRSRSTUV SIDE 111112222211111222221111122222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO source: 10111 changed: 1 step 13 101100000100001000010000100001 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEDEFHJFHJKLKLMNPMNPRSRSTUV SIDE 111112222211111222221111122222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO source: 11001 changed: 100 step 14 110000000100001000010000100001 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEDEFHJFHJKLKLMNPMNPRSRSTUV SIDE 111112222211111222221111122222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO source: 11011 changed: 1 step 15 110100000100001000010000100001 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEDEFHJFHJKLKLMNPMNPRSRSTUV SIDE 111112222211111222221111122222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO source: 11101 changed: 10 step 16 111000000100001000010000100001 fail ^ source: 11110 changed: 1 step 17 111100000100001000010000100001 SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEDEFHJFHJKLKLMNPMNPRSRSTUV SIDE 111112222211111222221111122222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO source: 00001 changed: 0000 step 18 000000000100001000010000100001 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEDEFHJFHJKLKLMNPMNPRSRSTUV SIDE 111112222211111222221111122222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO source: 00001 changed: step 19 000000000100001000010000100001 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEDEFHJFHJKLKLMNPMNPRSRSTUV SIDE 111112222211111222221111122222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO source: 00011 changed: 1 step 20 000000001100001000010000100001 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEDEFHJFHJKLKLMNPMNPRSRSTUV SIDE 111112222211111222221111122222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO source: 00101 changed: 10 step 21 000000010100001000010000100001 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEDEFHJFHJKLKLMNPMNPRSRSTUV SIDE 111112222211111222221111122222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO source: 00111 changed: 1 step 22 000000011100001000010000100001 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEDEFHJFHJKLKLMNPMNPRSRSTUV SIDE 111112222211111222221111122222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO source: 01001 changed: 100 step 23 000000100100001000010000100001 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEDEFHJFHJKLKLMNPMNPRSRSTUV SIDE 111112222211111222221111122222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO source: 01011 changed: 1 step 24 000000101100001000010000100001 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEDEFHJFHJKLKLMNPMNPRSRSTUV SIDE 111112222211111222221111122222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO source: 01101 changed: 10 step 25 000000110100001000010000100001 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEDEFHJFHJKLKLMNPMNPRSRSTUV SIDE 111112222211111222221111122222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO source: 01111 changed: 1 step 26 000000111100001000010000100001 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEDEFHJFHJKLKLMNPMNPRSRSTUV SIDE 111112222211111222221111122222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO source: 10001 changed: 1000 step 27 000001000100001000010000100001 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEDEFHJFHJKLKLMNPMNPRSRSTUV SIDE 111112222211111222221111122222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO source: 10011 changed: 1 step 28 000001001100001000010000100001 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEDEFHJFHJKLKLMNPMNPRSRSTUV SIDE 111112222211111222221111122222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO source: 10101 changed: 10 step 29 000001010100001000010000100001 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEDEFHJFHJKLKLMNPMNPRSRSTUV SIDE 111112222211111222221111122222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO source: 10111 changed: 1 step 30 000001011100001000010000100001 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEDEFHJFHJKLKLMNPMNPRSRSTUV SIDE 111112222211111222221111122222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO source: 11001 changed: 100 step 31 000001100100001000010000100001 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEDEFHJFHJKLKLMNPMNPRSRSTUV SIDE 111112222211111222221111122222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO source: 11011 changed: 1 step 32 000001101100001000010000100001 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEDEFHJFHJKLKLMNPMNPRSRSTUV SIDE 111112222211111222221111122222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO source: 11101 changed: 10 step 33 000001110100001000010000100001 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEDEFHJFHJKLKLMNPMNPRSRSTUV SIDE 111112222211111222221111122222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO source: 11110 changed: 10 step 34 000001111000001000010000100001 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEDEFHJFHJKLKLMNPMNPRSRSTUV SIDE 111112222211111222221111122222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO source: 00001 changed: 00001 step 35 000000000100001000010000100001 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEDEFHJFHJKLKLMNPMNPRSRSTUV SIDE 111112222211111222221111122222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO source: 00001 changed: step 36 000000000100001000010000100001 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEDEFHJFHJKLKLMNPMNPRSRSTUV SIDE 111112222211111222221111122222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO source: 00011 changed: 1 step 37 000000000100011000010000100001 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEDEFHJFHJKLKLMNPMNPRSRSTUV SIDE 111112222211111222221111122222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO source: 00101 changed: 10 step 38 000000000100101000010000100001 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEDEFHJFHJKLKLMNPMNPRSRSTUV SIDE 111112222211111222221111122222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO source: 00111 changed: 1 step 39 000000000100111000010000100001 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEDEFHJFHJKLKLMNPMNPRSRSTUV SIDE 111112222211111222221111122222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO source: 01001 changed: 100 step 40 000000000101001000010000100001 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEDEFHJFHJKLKLMNPMNPRSRSTUV SIDE 111112222211111222221111122222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO source: 01011 changed: 1 step 41 000000000101011000010000100001 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEDEFHJFHJKLKLMNPMNPRSRSTUV SIDE 111112222211111222221111122222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO source: 01101 changed: 10 step 42 000000000101101000010000100001 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEDEFHJFHJKLKLMNPMNPRSRSTUV SIDE 111112222211111222221111122222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO source: 01111 changed: 1 step 43 000000000101111000010000100001 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEDEFHJFHJKLKLMNPMNPRSRSTUV SIDE 111112222211111222221111122222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO source: 10001 changed: 1000 step 44 000000000110001000010000100001 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEDEFHJFHJKLKLMNPMNPRSRSTUV SIDE 111112222211111222221111122222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO source: 10011 changed: 1 step 45 000000000110011000010000100001 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEDEFHJFHJKLKLMNPMNPRSRSTUV SIDE 111112222211111222221111122222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO source: 10101 changed: 10 step 46 000000000110101000010000100001 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEDEFHJFHJKLKLMNPMNPRSRSTUV SIDE 111112222211111222221111122222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO source: 10111 changed: 1 step 47 000000000110111000010000100001 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEDEFHJFHJKLKLMNPMNPRSRSTUV SIDE 111112222211111222221111122222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO source: 11001 changed: 100 step 48 000000000111001000010000100001 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEDEFHJFHJKLKLMNPMNPRSRSTUV SIDE 111112222211111222221111122222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO source: 11011 changed: 1 step 49 000000000111011000010000100001 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEDEFHJFHJKLKLMNPMNPRSRSTUV SIDE 111112222211111222221111122222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO source: 11101 changed: 10 step 50 000000000111101000010000100001 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEDEFHJFHJKLKLMNPMNPRSRSTUV SIDE 111112222211111222221111122222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO source: 11110 changed: 10 step 51 000000000111110000010000100001 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEDEFHJFHJKLKLMNPMNPRSRSTUV SIDE 111112222211111222221111122222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO source: 00001 changed: 00001 step 52 000000000100001000010000100001 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEDEFHJFHJKLKLMNPMNPRSRSTUV SIDE 111112222211111222221111122222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO source: 00001 changed: step 53 000000000100001000010000100001 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEDEFHJFHJKLKLMNPMNPRSRSTUV SIDE 111112222211111222221111122222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO source: 00011 changed: 1 step 54 000000000100001000110000100001 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEDEFHJFHJKLKLMNPMNPRSRSTUV SIDE 111112222211111222221111122222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO source: 00101 changed: 10 step 55 000000000100001001010000100001 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEDEFHJFHJKLKLMNPMNPRSRSTUV SIDE 111112222211111222221111122222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO source: 00111 changed: 1 step 56 000000000100001001110000100001 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEDEFHJFHJKLKLMNPMNPRSRSTUV SIDE 111112222211111222221111122222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO source: 01001 changed: 100 step 57 000000000100001010010000100001 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEDEFHJFHJKLKLMNPMNPRSRSTUV SIDE 111112222211111222221111122222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO source: 01011 changed: 1 step 58 000000000100001010110000100001 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEDEFHJFHJKLKLMNPMNPRSRSTUV SIDE 111112222211111222221111122222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO source: 01101 changed: 10 step 59 000000000100001011010000100001 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEDEFHJFHJKLKLMNPMNPRSRSTUV SIDE 111112222211111222221111122222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO source: 01111 changed: 1 step 60 000000000100001011110000100001 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEDEFHJFHJKLKLMNPMNPRSRSTUV SIDE 111112222211111222221111122222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO source: 10001 changed: 1000 step 61 000000000100001100010000100001 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEDEFHJFHJKLKLMNPMNPRSRSTUV SIDE 111112222211111222221111122222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO source: 10011 changed: 1 step 62 000000000100001100110000100001 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEDEFHJFHJKLKLMNPMNPRSRSTUV SIDE 111112222211111222221111122222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO source: 10101 changed: 10 step 63 000000000100001101010000100001 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEDEFHJFHJKLKLMNPMNPRSRSTUV SIDE 111112222211111222221111122222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO source: 10111 changed: 1 step 64 000000000100001101110000100001 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEDEFHJFHJKLKLMNPMNPRSRSTUV SIDE 111112222211111222221111122222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO source: 11001 changed: 100 step 65 000000000100001110010000100001 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEDEFHJFHJKLKLMNPMNPRSRSTUV SIDE 111112222211111222221111122222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO source: 11011 changed: 1 step 66 000000000100001110110000100001 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEDEFHJFHJKLKLMNPMNPRSRSTUV SIDE 111112222211111222221111122222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO source: 11101 changed: 10 step 67 000000000100001111010000100001 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEDEFHJFHJKLKLMNPMNPRSRSTUV SIDE 111112222211111222221111122222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO source: 11110 changed: 10 step 68 000000000100001111100000100001 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEDEFHJFHJKLKLMNPMNPRSRSTUV SIDE 111112222211111222221111122222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO source: 00001 changed: 00001 step 69 000000000100001000010000100001 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEDEFHJFHJKLKLMNPMNPRSRSTUV SIDE 111112222211111222221111122222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO source: 00001 changed: step 70 000000000100001000010000100001 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEDEFHJFHJKLKLMNPMNPRSRSTUV SIDE 111112222211111222221111122222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO source: 00011 changed: 1 step 71 000000000100001000010001100001 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEDEFHJFHJKLKLMNPMNPRSRSTUV SIDE 111112222211111222221111122222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO source: 00101 changed: 10 step 72 000000000100001000010010100001 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEDEFHJFHJKLKLMNPMNPRSRSTUV SIDE 111112222211111222221111122222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO source: 00111 changed: 1 step 73 000000000100001000010011100001 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEDEFHJFHJKLKLMNPMNPRSRSTUV SIDE 111112222211111222221111122222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO source: 01001 changed: 100 step 74 000000000100001000010100100001 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEDEFHJFHJKLKLMNPMNPRSRSTUV SIDE 111112222211111222221111122222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO source: 01011 changed: 1 step 75 000000000100001000010101100001 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEDEFHJFHJKLKLMNPMNPRSRSTUV SIDE 111112222211111222221111122222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO source: 01101 changed: 10 step 76 000000000100001000010110100001 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEDEFHJFHJKLKLMNPMNPRSRSTUV SIDE 111112222211111222221111122222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO source: 01111 changed: 1 step 77 000000000100001000010111100001 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEDEFHJFHJKLKLMNPMNPRSRSTUV SIDE 111112222211111222221111122222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO source: 10001 changed: 1000 step 78 000000000100001000011000100001 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEDEFHJFHJKLKLMNPMNPRSRSTUV SIDE 111112222211111222221111122222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO source: 10011 changed: 1 step 79 000000000100001000011001100001 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEDEFHJFHJKLKLMNPMNPRSRSTUV SIDE 111112222211111222221111122222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO source: 10101 changed: 10 step 80 000000000100001000011010100001 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEDEFHJFHJKLKLMNPMNPRSRSTUV SIDE 111112222211111222221111122222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO source: 10111 changed: 1 step 81 000000000100001000011011100001 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEDEFHJFHJKLKLMNPMNPRSRSTUV SIDE 111112222211111222221111122222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO source: 11001 changed: 100 step 82 000000000100001000011100100001 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEDEFHJFHJKLKLMNPMNPRSRSTUV SIDE 111112222211111222221111122222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO source: 11011 changed: 1 step 83 000000000100001000011101100001 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEDEFHJFHJKLKLMNPMNPRSRSTUV SIDE 111112222211111222221111122222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO source: 11101 changed: 10 step 84 000000000100001000011110100001 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEDEFHJFHJKLKLMNPMNPRSRSTUV SIDE 111112222211111222221111122222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO source: 11110 changed: 10 step 85 000000000100001000011111000001 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEDEFHJFHJKLKLMNPMNPRSRSTUV SIDE 111112222211111222221111122222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO source: 00001 changed: 00001 step 86 000000000100001000010000100001 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEDEFHJFHJKLKLMNPMNPRSRSTUV SIDE 111112222211111222221111122222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO source: 00001 changed: step 87 000000000100001000010000100001 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEDEFHJFHJKLKLMNPMNPRSRSTUV SIDE 111112222211111222221111122222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO source: 00011 changed: 1 step 88 000000000100001000010000100011 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEDEFHJFHJKLKLMNPMNPRSRSTUV SIDE 111112222211111222221111122222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO source: 00101 changed: 10 step 89 000000000100001000010000100101 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEDEFHJFHJKLKLMNPMNPRSRSTUV SIDE 111112222211111222221111122222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO source: 00111 changed: 1 step 90 000000000100001000010000100111 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEDEFHJFHJKLKLMNPMNPRSRSTUV SIDE 111112222211111222221111122222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO source: 01001 changed: 100 step 91 000000000100001000010000101001 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEDEFHJFHJKLKLMNPMNPRSRSTUV SIDE 111112222211111222221111122222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO source: 01011 changed: 1 step 92 000000000100001000010000101011 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEDEFHJFHJKLKLMNPMNPRSRSTUV SIDE 111112222211111222221111122222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO source: 01101 changed: 10 step 93 000000000100001000010000101101 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEDEFHJFHJKLKLMNPMNPRSRSTUV SIDE 111112222211111222221111122222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO source: 01111 changed: 1 step 94 000000000100001000010000101111 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEDEFHJFHJKLKLMNPMNPRSRSTUV SIDE 111112222211111222221111122222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO source: 10001 changed: 1000 step 95 000000000100001000010000110001 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEDEFHJFHJKLKLMNPMNPRSRSTUV SIDE 111112222211111222221111122222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO source: 10011 changed: 1 step 96 000000000100001000010000110011 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEDEFHJFHJKLKLMNPMNPRSRSTUV SIDE 111112222211111222221111122222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO source: 10101 changed: 10 step 97 000000000100001000010000110101 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEDEFHJFHJKLKLMNPMNPRSRSTUV SIDE 111112222211111222221111122222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO source: 10111 changed: 1 step 98 000000000100001000010000110111 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEDEFHJFHJKLKLMNPMNPRSRSTUV SIDE 111112222211111222221111122222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO source: 11001 changed: 100 step 99 000000000100001000010000111001 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEDEFHJFHJKLKLMNPMNPRSRSTUV SIDE 111112222211111222221111122222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO source: 11011 changed: 1 step 100 000000000100001000010000111011 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEDEFHJFHJKLKLMNPMNPRSRSTUV SIDE 111112222211111222221111122222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO source: 11101 changed: 10 step 101 000000000100001000010000111101 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEDEFHJFHJKLKLMNPMNPRSRSTUV SIDE 111112222211111222221111122222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO source: 11110 changed: 10 step 102 000000000100001000010000111110 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEDEFHJFHJKLKLMNPMNPRSRSTUV SIDE 111112222211111222221111122222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO source: 00001 changed: 00001 step 103 000000000100001000010000100001 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEDEFHJFHJKLKLMNPMNPRSRSTUV SIDE 111112222211111222221111122222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO source: 000010000100001000010000100001 changed: step 104 000000000100001000010000100001 fail ^ source: 111101111011110111101111011110 changed: 1111 1111011110111101111011110 step 105 111101111011110111101111011110 SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEDEFHJFHJKLKLMNPMNPRSRSTUV SIDE 111112222211111222221111122222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO source: 00001 changed: 0000 step 106 000001111011110111101111011110 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEDEFHJFHJKLKLMNPMNPRSRSTUV SIDE 111112222211111222221111122222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO source: 00011 changed: 1 step 107 000101111011110111101111011110 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEDEFHJFHJKLKLMNPMNPRSRSTUV SIDE 111112222211111222221111122222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO source: 00101 changed: 10 step 108 001001111011110111101111011110 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEDEFHJFHJKLKLMNPMNPRSRSTUV SIDE 111112222211111222221111122222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO source: 00111 changed: 1 step 109 001101111011110111101111011110 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEDEFHJFHJKLKLMNPMNPRSRSTUV SIDE 111112222211111222221111122222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO source: 01001 changed: 100 step 110 010001111011110111101111011110 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEDEFHJFHJKLKLMNPMNPRSRSTUV SIDE 111112222211111222221111122222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO source: 01011 changed: 1 step 111 010101111011110111101111011110 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEDEFHJFHJKLKLMNPMNPRSRSTUV SIDE 111112222211111222221111122222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO source: 01101 changed: 10 step 112 011001111011110111101111011110 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEDEFHJFHJKLKLMNPMNPRSRSTUV SIDE 111112222211111222221111122222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO source: 01111 changed: 1 step 113 011101111011110111101111011110 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEDEFHJFHJKLKLMNPMNPRSRSTUV SIDE 111112222211111222221111122222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO source: 10001 changed: 1000 step 114 100001111011110111101111011110 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEDEFHJFHJKLKLMNPMNPRSRSTUV SIDE 111112222211111222221111122222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO source: 10011 changed: 1 step 115 100101111011110111101111011110 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEDEFHJFHJKLKLMNPMNPRSRSTUV SIDE 111112222211111222221111122222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO source: 10101 changed: 10 step 116 101001111011110111101111011110 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEDEFHJFHJKLKLMNPMNPRSRSTUV SIDE 111112222211111222221111122222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO source: 10111 changed: 1 step 117 101101111011110111101111011110 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEDEFHJFHJKLKLMNPMNPRSRSTUV SIDE 111112222211111222221111122222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO source: 11001 changed: 100 step 118 110001111011110111101111011110 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEDEFHJFHJKLKLMNPMNPRSRSTUV SIDE 111112222211111222221111122222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO source: 11011 changed: 1 step 119 110101111011110111101111011110 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEDEFHJFHJKLKLMNPMNPRSRSTUV SIDE 111112222211111222221111122222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO source: 11101 changed: 10 step 120 111001111011110111101111011110 fail ^ source: 11110 changed: 1 step 121 111101111011110111101111011110 source: 00001 changed: 00001 step 122 111100000111110111101111011110 source: 00011 changed: 1 step 123 111100001111110111101111011110 source: 00101 changed: 10 step 124 111100010111110111101111011110 source: 00111 changed: 1 step 125 111100011111110111101111011110 source: 01001 changed: 100 step 126 111100100111110111101111011110 source: 01011 changed: 1 step 127 111100101111110111101111011110 source: 01101 changed: 10 step 128 111100110111110111101111011110 source: 01111 changed: 1 step 129 111100111111110111101111011110 source: 10001 changed: 1000 step 130 111101000111110111101111011110 source: 10011 changed: 1 step 131 111101001111110111101111011110 source: 10101 changed: 10 step 132 111101010111110111101111011110 source: 10111 changed: 1 step 133 111101011111110111101111011110 source: 11001 changed: 100 step 134 111101100111110111101111011110 source: 11011 changed: 1 step 135 111101101111110111101111011110 source: 11101 changed: 10 step 136 111101110111110111101111011110 source: 11110 changed: 10 step 137 111101111011110111101111011110 source: 00001 changed: 00001 step 138 111101111000001111101111011110 source: 00011 changed: 1 step 139 111101111000011111101111011110 source: 00101 changed: 10 step 140 111101111000101111101111011110 source: 00111 changed: 1 step 141 111101111000111111101111011110 source: 01001 changed: 100 step 142 111101111001001111101111011110 source: 01011 changed: 1 step 143 111101111001011111101111011110 source: 01101 changed: 10 step 144 111101111001101111101111011110 source: 01111 changed: 1 step 145 111101111001111111101111011110 source: 10001 changed: 1000 step 146 111101111010001111101111011110 source: 10011 changed: 1 step 147 111101111010011111101111011110 source: 10101 changed: 10 step 148 111101111010101111101111011110 source: 10111 changed: 1 step 149 111101111010111111101111011110 source: 11001 changed: 100 step 150 111101111011001111101111011110 source: 11011 changed: 1 step 151 111101111011011111101111011110 source: 11101 changed: 10 step 152 111101111011101111101111011110 source: 11110 changed: 10 step 153 111101111011110111101111011110 source: 00001 changed: 00001 step 154 111101111011110000011111011110 source: 00011 changed: 1 step 155 111101111011110000111111011110 source: 00101 changed: 10 step 156 111101111011110001011111011110 source: 00111 changed: 1 step 157 111101111011110001111111011110 source: 01001 changed: 100 step 158 111101111011110010011111011110 source: 01011 changed: 1 step 159 111101111011110010111111011110 source: 01101 changed: 10 step 160 111101111011110011011111011110 source: 01111 changed: 1 step 161 111101111011110011111111011110 source: 10001 changed: 1000 step 162 111101111011110100011111011110 source: 10011 changed: 1 step 163 111101111011110100111111011110 source: 10101 changed: 10 step 164 111101111011110101011111011110 source: 10111 changed: 1 step 165 111101111011110101111111011110 source: 11001 changed: 100 step 166 111101111011110110011111011110 source: 11011 changed: 1 step 167 111101111011110110111111011110 source: 11101 changed: 10 step 168 111101111011110111011111011110 source: 11110 changed: 10 step 169 111101111011110111101111011110 source: 00001 changed: 00001 step 170 111101111011110111100000111110 source: 00011 changed: 1 step 171 111101111011110111100001111110 source: 00101 changed: 10 step 172 111101111011110111100010111110 source: 00111 changed: 1 step 173 111101111011110111100011111110 source: 01001 changed: 100 step 174 111101111011110111100100111110 source: 01011 changed: 1 step 175 111101111011110111100101111110 source: 01101 changed: 10 step 176 111101111011110111100110111110 source: 01111 changed: 1 step 177 111101111011110111100111111110 source: 10001 changed: 1000 step 178 111101111011110111101000111110 source: 10011 changed: 1 step 179 111101111011110111101001111110 source: 10101 changed: 10 step 180 111101111011110111101010111110 source: 10111 changed: 1 step 181 111101111011110111101011111110 source: 11001 changed: 100 step 182 111101111011110111101100111110 source: 11011 changed: 1 step 183 111101111011110111101101111110 source: 11101 changed: 10 step 184 111101111011110111101110111110 source: 11110 changed: 10 step 185 111101111011110111101111011110 source: 00001 changed: 00001 step 186 111101111011110111101111000001 source: 00011 changed: 1 step 187 111101111011110111101111000011 source: 00101 changed: 10 step 188 111101111011110111101111000101 source: 00111 changed: 1 step 189 111101111011110111101111000111 source: 01001 changed: 100 step 190 111101111011110111101111001001 source: 01011 changed: 1 step 191 111101111011110111101111001011 source: 01101 changed: 10 step 192 111101111011110111101111001101 source: 01111 changed: 1 step 193 111101111011110111101111001111 source: 10001 changed: 1000 step 194 111101111011110111101111010001 source: 10011 changed: 1 step 195 111101111011110111101111010011 source: 10101 changed: 10 step 196 111101111011110111101111010101 source: 10111 changed: 1 step 197 111101111011110111101111010111 source: 11001 changed: 100 step 198 111101111011110111101111011001 source: 11011 changed: 1 step 199 111101111011110111101111011011 source: 11101 changed: 10 step 200 111101111011110111101111011101 source: 11110 changed: 10 step 201 111101111011110111101111011110 source: 111101111011110111101111011110 changed: step 202 111101111011110111101111011110 test 27: *** FAIL *************************** 118 steps failed SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEDEFHJFHJKLKLMNPMNPRSRSTUV SIDE 111112222211111222221111122222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO this fail O all fails O was hi 1111 1111111111111111111111111 rising ^^^^ ^^^^^^^^^^^^^^^^^^^^^^^^^ falling vvvv vvvvvvvvvvvvvvvvvvvvvvvvv was lo 000000000000000000000000000000 total fails 27, total passes 0 space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn off comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn off comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn off comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEDEFHJFHJKLKLMNPMNPRSRSTUV SIDE 111112222211111222221111122222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO all fails O was lo 000000000000000000000000000000 falling vvvv vvvvvvvvvvvvvvvvvvvvvvvvv rising ^^^^ ^^^^^^^^^^^^^^^^^^^^^^^^^ was hi 1111 1111111111111111111111111 total fails 27, total passes 0 Main menu Mon Jul 10 15:36:53 2017 test file is: tests\m516.tst delay is: 0 trigger is: 1 1 read test file 2 set test delay 3 set test trigger 4 run test 5 output loading test 8 diags 9 exit Enter test file name? trying to open test file: tests\m117.tst reading test file: tests\m117.tst comment: M117 REV 3 6 4-input NAND comment: pins: PINS pins: 1 I AA1 E1-13 pins: 2 I AB1 E1-12 pins: 3 I AC1 E1-10 pins: 4 I AD1 E1-9 pins: 5 O AE1 E1-8 pins: 6 I AF1 E2-13 pins: 7 I AH1 E2-12 pins: 8 I AJ1 E2-10 pins: 9 I AK1 E2-9 pins: 10 O AL1 E2-8 pins: 11 I AM1 E3-13 pins: 12 I AN1 E3-12 pins: 13 I AP1 E3-10 pins: 14 I AR1 E3-9 pins: 15 O AS1 E3-8 pins: 16 I AD2 E1-5 pins: 17 I AE2 E1-4 pins: 18 I AF2 E1-2 pins: 19 I AH2 E1-1 pins: 20 O AJ2 E1-6 pins: 21 I AK2 E2-5 pins: 22 I AL2 E2-4 pins: 23 I AM2 E2-2 pins: 24 I AN2 E2-1 pins: 25 O AP2 E2-6 pins: 26 I AR2 E3-1 pins: 27 I AS2 E3-2 pins: 28 I AT2 E3-4 pins: 29 I AU2 E3-5 pins: 30 O AV2 E3-6 pins: direction: IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO test 1: 000010000100001000010000100001 test 2: 00001 test 3: 00011 test 4: 00101 test 5: 00111 test 6: 01001 test 7: 01011 test 8: 01101 test 9: 01111 test 10: 10001 test 11: 10011 test 12: 10101 test 13: 10111 test 14: 11001 test 15: 11011 test 16: 11101 test 17: 11110 test 18: 00001 test 19: 00001 test 20: 00011 test 21: 00101 test 22: 00111 test 23: 01001 test 24: 01011 test 25: 01101 test 26: 01111 test 27: 10001 test 28: 10011 test 29: 10101 test 30: 10111 test 31: 11001 test 32: 11011 test 33: 11101 test 34: 11110 test 35: 00001 test 36: 00001 test 37: 00011 test 38: 00101 test 39: 00111 test 40: 01001 test 41: 01011 test 42: 01101 test 43: 01111 test 44: 10001 test 45: 10011 test 46: 10101 test 47: 10111 test 48: 11001 test 49: 11011 test 50: 11101 test 51: 11110 test 52: 00001 test 53: 00001 test 54: 00011 test 55: 00101 test 56: 00111 test 57: 01001 test 58: 01011 test 59: 01101 test 60: 01111 test 61: 10001 test 62: 10011 test 63: 10101 test 64: 10111 test 65: 11001 test 66: 11011 test 67: 11101 test 68: 11110 test 69: 00001 test 70: 00001 test 71: 00011 test 72: 00101 test 73: 00111 test 74: 01001 test 75: 01011 test 76: 01101 test 77: 01111 test 78: 10001 test 79: 10011 test 80: 10101 test 81: 10111 test 82: 11001 test 83: 11011 test 84: 11101 test 85: 11110 test 86: 00001 test 87: 00001 test 88: 00011 test 89: 00101 test 90: 00111 test 91: 01001 test 92: 01011 test 93: 01101 test 94: 01111 test 95: 10001 test 96: 10011 test 97: 10101 test 98: 10111 test 99: 11001 test 100: 11011 test 101: 11101 test 102: 11110 test 103: 00001 test 104: 000010000100001000010000100001 test 105: 111101111011110111101111011110 test 106: 00001 test 107: 00011 test 108: 00101 test 109: 00111 test 110: 01001 test 111: 01011 test 112: 01101 test 113: 01111 test 114: 10001 test 115: 10011 test 116: 10101 test 117: 10111 test 118: 11001 test 119: 11011 test 120: 11101 test 121: 11110 test 122: 00001 test 123: 00011 test 124: 00101 test 125: 00111 test 126: 01001 test 127: 01011 test 128: 01101 test 129: 01111 test 130: 10001 test 131: 10011 test 132: 10101 test 133: 10111 test 134: 11001 test 135: 11011 test 136: 11101 test 137: 11110 test 138: 00001 test 139: 00011 test 140: 00101 test 141: 00111 test 142: 01001 test 143: 01011 test 144: 01101 test 145: 01111 test 146: 10001 test 147: 10011 test 148: 10101 test 149: 10111 test 150: 11001 test 151: 11011 test 152: 11101 test 153: 11110 test 154: 00001 test 155: 00011 test 156: 00101 test 157: 00111 test 158: 01001 test 159: 01011 test 160: 01101 test 161: 01111 test 162: 10001 test 163: 10011 test 164: 10101 test 165: 10111 test 166: 11001 test 167: 11011 test 168: 11101 test 169: 11110 test 170: 00001 test 171: 00011 test 172: 00101 test 173: 00111 test 174: 01001 test 175: 01011 test 176: 01101 test 177: 01111 test 178: 10001 test 179: 10011 test 180: 10101 test 181: 10111 test 182: 11001 test 183: 11011 test 184: 11101 test 185: 11110 test 186: 00001 test 187: 00011 test 188: 00101 test 189: 00111 test 190: 01001 test 191: 01011 test 192: 01101 test 193: 01111 test 194: 10001 test 195: 10011 test 196: 10101 test 197: 10111 test 198: 11001 test 199: 11011 test 200: 11101 test 201: 11110 test 202: 111101111011110111101111011110 end: END summary column 1: offset 0, mask 0x8000 column 2: offset 0, mask 0x4000 column 3: offset 0, mask 0x2000 column 4: offset 0, mask 0x1000 column 5: offset 0, mask 0x0800 column 6: offset 0, mask 0x0400 column 7: offset 0, mask 0x0200 column 8: offset 0, mask 0x0100 column 9: offset 1, mask 0x8000 column 10: offset 1, mask 0x4000 column 11: offset 1, mask 0x2000 column 12: offset 1, mask 0x1000 column 13: offset 1, mask 0x0800 column 14: offset 1, mask 0x0400 column 15: offset 1, mask 0x0200 column 16: offset 0, mask 0x0010 column 17: offset 0, mask 0x0008 column 18: offset 0, mask 0x0004 column 19: offset 0, mask 0x0002 column 20: offset 0, mask 0x0001 column 21: offset 1, mask 0x0001 column 22: offset 1, mask 0x0002 column 23: offset 1, mask 0x0004 column 24: offset 1, mask 0x0008 column 25: offset 1, mask 0x0010 column 26: offset 1, mask 0x0020 column 27: offset 1, mask 0x0040 column 28: offset 1, mask 0x0080 column 29: offset 2, mask 0x0001 column 30: offset 2, mask 0x0002 direction bits (1=input) 0x08E1 0x4310 0xFFFA 0xFFFF 0xF0FF pullup bits (1=pullup) 0x0000 0x0000 0x0000 0x0000 0x0000 test step out_data dont care 1: 0x0801 0x4210 0x0002 0x0000 0x0000 2: 0x0801 0x4210 0x0002 0x0000 0x0000 3: 0x1801 0x4210 0x0002 0x0000 0x0000 4: 0x2801 0x4210 0x0002 0x0000 0x0000 5: 0x3801 0x4210 0x0002 0x0000 0x0000 6: 0x4801 0x4210 0x0002 0x0000 0x0000 7: 0x5801 0x4210 0x0002 0x0000 0x0000 8: 0x6801 0x4210 0x0002 0x0000 0x0000 9: 0x7801 0x4210 0x0002 0x0000 0x0000 10: 0x8801 0x4210 0x0002 0x0000 0x0000 11: 0x9801 0x4210 0x0002 0x0000 0x0000 12: 0xA801 0x4210 0x0002 0x0000 0x0000 13: 0xB801 0x4210 0x0002 0x0000 0x0000 14: 0xC801 0x4210 0x0002 0x0000 0x0000 15: 0xD801 0x4210 0x0002 0x0000 0x0000 16: 0xE801 0x4210 0x0002 0x0000 0x0000 17: 0xF001 0x4210 0x0002 0x0000 0x0000 18: 0x0801 0x4210 0x0002 0x0000 0x0000 19: 0x0801 0x4210 0x0002 0x0000 0x0000 20: 0x0801 0xC210 0x0002 0x0000 0x0000 21: 0x0901 0x4210 0x0002 0x0000 0x0000 22: 0x0901 0xC210 0x0002 0x0000 0x0000 23: 0x0A01 0x4210 0x0002 0x0000 0x0000 24: 0x0A01 0xC210 0x0002 0x0000 0x0000 25: 0x0B01 0x4210 0x0002 0x0000 0x0000 26: 0x0B01 0xC210 0x0002 0x0000 0x0000 27: 0x0C01 0x4210 0x0002 0x0000 0x0000 28: 0x0C01 0xC210 0x0002 0x0000 0x0000 29: 0x0D01 0x4210 0x0002 0x0000 0x0000 30: 0x0D01 0xC210 0x0002 0x0000 0x0000 31: 0x0E01 0x4210 0x0002 0x0000 0x0000 32: 0x0E01 0xC210 0x0002 0x0000 0x0000 33: 0x0F01 0x4210 0x0002 0x0000 0x0000 34: 0x0F01 0x8210 0x0002 0x0000 0x0000 35: 0x0801 0x4210 0x0002 0x0000 0x0000 36: 0x0801 0x4210 0x0002 0x0000 0x0000 37: 0x0801 0x4610 0x0002 0x0000 0x0000 38: 0x0801 0x4A10 0x0002 0x0000 0x0000 39: 0x0801 0x4E10 0x0002 0x0000 0x0000 40: 0x0801 0x5210 0x0002 0x0000 0x0000 41: 0x0801 0x5610 0x0002 0x0000 0x0000 42: 0x0801 0x5A10 0x0002 0x0000 0x0000 43: 0x0801 0x5E10 0x0002 0x0000 0x0000 44: 0x0801 0x6210 0x0002 0x0000 0x0000 45: 0x0801 0x6610 0x0002 0x0000 0x0000 46: 0x0801 0x6A10 0x0002 0x0000 0x0000 47: 0x0801 0x6E10 0x0002 0x0000 0x0000 48: 0x0801 0x7210 0x0002 0x0000 0x0000 49: 0x0801 0x7610 0x0002 0x0000 0x0000 50: 0x0801 0x7A10 0x0002 0x0000 0x0000 51: 0x0801 0x7C10 0x0002 0x0000 0x0000 52: 0x0801 0x4210 0x0002 0x0000 0x0000 53: 0x0801 0x4210 0x0002 0x0000 0x0000 54: 0x0803 0x4210 0x0002 0x0000 0x0000 55: 0x0805 0x4210 0x0002 0x0000 0x0000 56: 0x0807 0x4210 0x0002 0x0000 0x0000 57: 0x0809 0x4210 0x0002 0x0000 0x0000 58: 0x080B 0x4210 0x0002 0x0000 0x0000 59: 0x080D 0x4210 0x0002 0x0000 0x0000 60: 0x080F 0x4210 0x0002 0x0000 0x0000 61: 0x0811 0x4210 0x0002 0x0000 0x0000 62: 0x0813 0x4210 0x0002 0x0000 0x0000 63: 0x0815 0x4210 0x0002 0x0000 0x0000 64: 0x0817 0x4210 0x0002 0x0000 0x0000 65: 0x0819 0x4210 0x0002 0x0000 0x0000 66: 0x081B 0x4210 0x0002 0x0000 0x0000 67: 0x081D 0x4210 0x0002 0x0000 0x0000 68: 0x081E 0x4210 0x0002 0x0000 0x0000 69: 0x0801 0x4210 0x0002 0x0000 0x0000 70: 0x0801 0x4210 0x0002 0x0000 0x0000 71: 0x0801 0x4218 0x0002 0x0000 0x0000 72: 0x0801 0x4214 0x0002 0x0000 0x0000 73: 0x0801 0x421C 0x0002 0x0000 0x0000 74: 0x0801 0x4212 0x0002 0x0000 0x0000 75: 0x0801 0x421A 0x0002 0x0000 0x0000 76: 0x0801 0x4216 0x0002 0x0000 0x0000 77: 0x0801 0x421E 0x0002 0x0000 0x0000 78: 0x0801 0x4211 0x0002 0x0000 0x0000 79: 0x0801 0x4219 0x0002 0x0000 0x0000 80: 0x0801 0x4215 0x0002 0x0000 0x0000 81: 0x0801 0x421D 0x0002 0x0000 0x0000 82: 0x0801 0x4213 0x0002 0x0000 0x0000 83: 0x0801 0x421B 0x0002 0x0000 0x0000 84: 0x0801 0x4217 0x0002 0x0000 0x0000 85: 0x0801 0x420F 0x0002 0x0000 0x0000 86: 0x0801 0x4210 0x0002 0x0000 0x0000 87: 0x0801 0x4210 0x0002 0x0000 0x0000 88: 0x0801 0x4210 0x0003 0x0000 0x0000 89: 0x0801 0x4290 0x0002 0x0000 0x0000 90: 0x0801 0x4290 0x0003 0x0000 0x0000 91: 0x0801 0x4250 0x0002 0x0000 0x0000 92: 0x0801 0x4250 0x0003 0x0000 0x0000 93: 0x0801 0x42D0 0x0002 0x0000 0x0000 94: 0x0801 0x42D0 0x0003 0x0000 0x0000 95: 0x0801 0x4230 0x0002 0x0000 0x0000 96: 0x0801 0x4230 0x0003 0x0000 0x0000 97: 0x0801 0x42B0 0x0002 0x0000 0x0000 98: 0x0801 0x42B0 0x0003 0x0000 0x0000 99: 0x0801 0x4270 0x0002 0x0000 0x0000 100: 0x0801 0x4270 0x0003 0x0000 0x0000 101: 0x0801 0x42F0 0x0002 0x0000 0x0000 102: 0x0801 0x42F0 0x0001 0x0000 0x0000 103: 0x0801 0x4210 0x0002 0x0000 0x0000 104: 0x0801 0x4210 0x0002 0x0000 0x0000 105: 0xF71E 0xBCEF 0x0001 0x0000 0x0000 106: 0x0F1E 0xBCEF 0x0001 0x0000 0x0000 107: 0x1F1E 0xBCEF 0x0001 0x0000 0x0000 108: 0x2F1E 0xBCEF 0x0001 0x0000 0x0000 109: 0x3F1E 0xBCEF 0x0001 0x0000 0x0000 110: 0x4F1E 0xBCEF 0x0001 0x0000 0x0000 111: 0x5F1E 0xBCEF 0x0001 0x0000 0x0000 112: 0x6F1E 0xBCEF 0x0001 0x0000 0x0000 113: 0x7F1E 0xBCEF 0x0001 0x0000 0x0000 114: 0x8F1E 0xBCEF 0x0001 0x0000 0x0000 115: 0x9F1E 0xBCEF 0x0001 0x0000 0x0000 116: 0xAF1E 0xBCEF 0x0001 0x0000 0x0000 117: 0xBF1E 0xBCEF 0x0001 0x0000 0x0000 118: 0xCF1E 0xBCEF 0x0001 0x0000 0x0000 119: 0xDF1E 0xBCEF 0x0001 0x0000 0x0000 120: 0xEF1E 0xBCEF 0x0001 0x0000 0x0000 121: 0xF71E 0xBCEF 0x0001 0x0000 0x0000 122: 0xF01E 0x7CEF 0x0001 0x0000 0x0000 123: 0xF01E 0xFCEF 0x0001 0x0000 0x0000 124: 0xF11E 0x7CEF 0x0001 0x0000 0x0000 125: 0xF11E 0xFCEF 0x0001 0x0000 0x0000 126: 0xF21E 0x7CEF 0x0001 0x0000 0x0000 127: 0xF21E 0xFCEF 0x0001 0x0000 0x0000 128: 0xF31E 0x7CEF 0x0001 0x0000 0x0000 129: 0xF31E 0xFCEF 0x0001 0x0000 0x0000 130: 0xF41E 0x7CEF 0x0001 0x0000 0x0000 131: 0xF41E 0xFCEF 0x0001 0x0000 0x0000 132: 0xF51E 0x7CEF 0x0001 0x0000 0x0000 133: 0xF51E 0xFCEF 0x0001 0x0000 0x0000 134: 0xF61E 0x7CEF 0x0001 0x0000 0x0000 135: 0xF61E 0xFCEF 0x0001 0x0000 0x0000 136: 0xF71E 0x7CEF 0x0001 0x0000 0x0000 137: 0xF71E 0xBCEF 0x0001 0x0000 0x0000 138: 0xF71E 0x82EF 0x0001 0x0000 0x0000 139: 0xF71E 0x86EF 0x0001 0x0000 0x0000 140: 0xF71E 0x8AEF 0x0001 0x0000 0x0000 141: 0xF71E 0x8EEF 0x0001 0x0000 0x0000 142: 0xF71E 0x92EF 0x0001 0x0000 0x0000 143: 0xF71E 0x96EF 0x0001 0x0000 0x0000 144: 0xF71E 0x9AEF 0x0001 0x0000 0x0000 145: 0xF71E 0x9EEF 0x0001 0x0000 0x0000 146: 0xF71E 0xA2EF 0x0001 0x0000 0x0000 147: 0xF71E 0xA6EF 0x0001 0x0000 0x0000 148: 0xF71E 0xAAEF 0x0001 0x0000 0x0000 149: 0xF71E 0xAEEF 0x0001 0x0000 0x0000 150: 0xF71E 0xB2EF 0x0001 0x0000 0x0000 151: 0xF71E 0xB6EF 0x0001 0x0000 0x0000 152: 0xF71E 0xBAEF 0x0001 0x0000 0x0000 153: 0xF71E 0xBCEF 0x0001 0x0000 0x0000 154: 0xF701 0xBCEF 0x0001 0x0000 0x0000 155: 0xF703 0xBCEF 0x0001 0x0000 0x0000 156: 0xF705 0xBCEF 0x0001 0x0000 0x0000 157: 0xF707 0xBCEF 0x0001 0x0000 0x0000 158: 0xF709 0xBCEF 0x0001 0x0000 0x0000 159: 0xF70B 0xBCEF 0x0001 0x0000 0x0000 160: 0xF70D 0xBCEF 0x0001 0x0000 0x0000 161: 0xF70F 0xBCEF 0x0001 0x0000 0x0000 162: 0xF711 0xBCEF 0x0001 0x0000 0x0000 163: 0xF713 0xBCEF 0x0001 0x0000 0x0000 164: 0xF715 0xBCEF 0x0001 0x0000 0x0000 165: 0xF717 0xBCEF 0x0001 0x0000 0x0000 166: 0xF719 0xBCEF 0x0001 0x0000 0x0000 167: 0xF71B 0xBCEF 0x0001 0x0000 0x0000 168: 0xF71D 0xBCEF 0x0001 0x0000 0x0000 169: 0xF71E 0xBCEF 0x0001 0x0000 0x0000 170: 0xF71E 0xBCF0 0x0001 0x0000 0x0000 171: 0xF71E 0xBCF8 0x0001 0x0000 0x0000 172: 0xF71E 0xBCF4 0x0001 0x0000 0x0000 173: 0xF71E 0xBCFC 0x0001 0x0000 0x0000 174: 0xF71E 0xBCF2 0x0001 0x0000 0x0000 175: 0xF71E 0xBCFA 0x0001 0x0000 0x0000 176: 0xF71E 0xBCF6 0x0001 0x0000 0x0000 177: 0xF71E 0xBCFE 0x0001 0x0000 0x0000 178: 0xF71E 0xBCF1 0x0001 0x0000 0x0000 179: 0xF71E 0xBCF9 0x0001 0x0000 0x0000 180: 0xF71E 0xBCF5 0x0001 0x0000 0x0000 181: 0xF71E 0xBCFD 0x0001 0x0000 0x0000 182: 0xF71E 0xBCF3 0x0001 0x0000 0x0000 183: 0xF71E 0xBCFB 0x0001 0x0000 0x0000 184: 0xF71E 0xBCF7 0x0001 0x0000 0x0000 185: 0xF71E 0xBCEF 0x0001 0x0000 0x0000 186: 0xF71E 0xBC0F 0x0002 0x0000 0x0000 187: 0xF71E 0xBC0F 0x0003 0x0000 0x0000 188: 0xF71E 0xBC8F 0x0002 0x0000 0x0000 189: 0xF71E 0xBC8F 0x0003 0x0000 0x0000 190: 0xF71E 0xBC4F 0x0002 0x0000 0x0000 191: 0xF71E 0xBC4F 0x0003 0x0000 0x0000 192: 0xF71E 0xBCCF 0x0002 0x0000 0x0000 193: 0xF71E 0xBCCF 0x0003 0x0000 0x0000 194: 0xF71E 0xBC2F 0x0002 0x0000 0x0000 195: 0xF71E 0xBC2F 0x0003 0x0000 0x0000 196: 0xF71E 0xBCAF 0x0002 0x0000 0x0000 197: 0xF71E 0xBCAF 0x0003 0x0000 0x0000 198: 0xF71E 0xBC6F 0x0002 0x0000 0x0000 199: 0xF71E 0xBC6F 0x0003 0x0000 0x0000 200: 0xF71E 0xBCEF 0x0002 0x0000 0x0000 201: 0xF71E 0xBCEF 0x0001 0x0000 0x0000 202: 0xF71E 0xBCEF 0x0001 0x0000 0x0000 PINs used (in edge connector order) (G=ground,P=power) SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBB LETTER ABCDEFHJKLMNPRSTUVABCDEFHJKLMNPRSTUVABCDEFHJKLMNPRSTUVABCDEFHJKLMNPRSTUV SIDE 111111111111111111222222222222222222111111111111111111222222222222222222 USAGE IIIIOIIIIOIIIIOG P GIIIIOIIIIOIIIIO G P G UUT inputs: 24 UUT outputs: 6 pins used: 30 not used: 36 202 'test steps' 238 lines M117 REV 3 6 4-input NAND PINS Main menu Mon Jul 10 15:36:57 2017 test file is: tests\m117.tst delay is: 0 trigger is: 1 1 read test file 2 set test delay 3 set test trigger 4 run test 5 output loading test 8 diags 9 exit UUT power is okay Mon Jul 10 15:37:01 2017 space single step O run once (one test, all steps) F run, stop on fail G go (run tests N run, stop on fail, no print S scope (run, no print) C turn on comment printout + increase speed (less delay) - decrease speed (more delay)(slower) Q quit test scope (run, no print) pppppppppppppppppppppppppp space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn on comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFHJKLMNPRSDEFHJKLMNPRSTUV SIDE 111111111111111222222222222222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO all fails was lo 000000000000000000000000000000 falling vvvvvvvvvvvvvvvvvvvvvvvvvvvvvv rising ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ was hi 111111111111111111111111111111 total fails 0, total passes 26 Main menu Mon Jul 10 15:37:05 2017 test file is: tests\m117.tst delay is: 0 trigger is: 1 1 read test file 2 set test delay 3 set test trigger 4 run test 5 output loading test 8 diags 9 exit Enter test file name? trying to open test file: tests\m516.tst reading test file: tests\m516.tst comment: M516 POSITIVE BUS RECEIVER (6 4-input NAND) (3 7420) PCB REV A SCHEMATIC REV (blank) comment: pins: PINS pins: 1 I AA1 E1-2 INPUT 1A pins: 2 I AB1 E1-1 INPUT 1B pins: 3 I AC1 E1-4 INPUT 1C pins: 4 I AD1 E1-5 INPUT 1D pins: 5 O AE1 E1-6 OUTPUT 1 = (1A NAND 1B NAND 1C NAND 1D) pins: 6 I AD2 E1-13 INPUT 2A pins: 7 I AE2 E1-12 INPUT 2B pins: 8 I AF2 E1-10 INPUT 2C pins: 9 I AH2 E1-9 INPUT 2D pins: 10 O AJ2 E1-8 OUTPUT 2 = (2A NAND 2B NAND 2C NAND 2D) pins: 11 I AF1 E2-2 INPUT 3A pins: 12 I AH1 E2-1 INPUT 3B pins: 13 I AJ1 E2-4 INPUT 3C pins: 14 I AK1 E2-5 INPUT 3D pins: 15 O AL1 E2-6 OUTPUT 3 = (3A NAND 3B NAND 3C NAND 3D) pins: 16 I AK2 E2-13 INPUT 4A pins: 17 I AL2 E2-12 INPUT 4B pins: 18 I AM2 E2-10 INPUT 4C pins: 19 I AN2 E2-9 INPUT 4D pins: 20 O AP2 E2-8 OUTPUT 4 = (4A NAND 4B NAND 4C NAND 4D) pins: 21 I AM1 E3-1 INPUT 5A pins: 22 I AN1 E3-2 INPUT 5B pins: 23 I AP1 E3-4 INPUT 5C pins: 24 I AR1 E3-5 INPUT 5D pins: 25 O AS1 E3-6 OUTPUT 5 = (5A NAND 5B NAND 5C NAND 5D) pins: 26 I AR2 E3-13 INPUT 6A pins: 27 I AS2 E3-12 INPUT 6B pins: 28 I AT2 E3-10 INPUT 6C pins: 29 I AU2 E3-9 INPUT 6D pins: 30 O AV2 E3-8 OUTPUT 6 = (6A NAND 6B NAND 6C NAND 6D) pins: direction: IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO test 1: 000010000100001000010000100001 test 2: 00001 test 3: 00011 test 4: 00101 test 5: 00111 test 6: 01001 test 7: 01011 test 8: 01101 test 9: 01111 test 10: 10001 test 11: 10011 test 12: 10101 test 13: 10111 test 14: 11001 test 15: 11011 test 16: 11101 test 17: 11110 test 18: 00001 test 19: 00001 test 20: 00011 test 21: 00101 test 22: 00111 test 23: 01001 test 24: 01011 test 25: 01101 test 26: 01111 test 27: 10001 test 28: 10011 test 29: 10101 test 30: 10111 test 31: 11001 test 32: 11011 test 33: 11101 test 34: 11110 test 35: 00001 test 36: 00001 test 37: 00011 test 38: 00101 test 39: 00111 test 40: 01001 test 41: 01011 test 42: 01101 test 43: 01111 test 44: 10001 test 45: 10011 test 46: 10101 test 47: 10111 test 48: 11001 test 49: 11011 test 50: 11101 test 51: 11110 test 52: 00001 test 53: 00001 test 54: 00011 test 55: 00101 test 56: 00111 test 57: 01001 test 58: 01011 test 59: 01101 test 60: 01111 test 61: 10001 test 62: 10011 test 63: 10101 test 64: 10111 test 65: 11001 test 66: 11011 test 67: 11101 test 68: 11110 test 69: 00001 test 70: 00001 test 71: 00011 test 72: 00101 test 73: 00111 test 74: 01001 test 75: 01011 test 76: 01101 test 77: 01111 test 78: 10001 test 79: 10011 test 80: 10101 test 81: 10111 test 82: 11001 test 83: 11011 test 84: 11101 test 85: 11110 test 86: 00001 test 87: 00001 test 88: 00011 test 89: 00101 test 90: 00111 test 91: 01001 test 92: 01011 test 93: 01101 test 94: 01111 test 95: 10001 test 96: 10011 test 97: 10101 test 98: 10111 test 99: 11001 test 100: 11011 test 101: 11101 test 102: 11110 test 103: 00001 test 104: 000010000100001000010000100001 test 105: 111101111011110111101111011110 test 106: 00001 test 107: 00011 test 108: 00101 test 109: 00111 test 110: 01001 test 111: 01011 test 112: 01101 test 113: 01111 test 114: 10001 test 115: 10011 test 116: 10101 test 117: 10111 test 118: 11001 test 119: 11011 test 120: 11101 test 121: 11110 test 122: 00001 test 123: 00011 test 124: 00101 test 125: 00111 test 126: 01001 test 127: 01011 test 128: 01101 test 129: 01111 test 130: 10001 test 131: 10011 test 132: 10101 test 133: 10111 test 134: 11001 test 135: 11011 test 136: 11101 test 137: 11110 test 138: 00001 test 139: 00011 test 140: 00101 test 141: 00111 test 142: 01001 test 143: 01011 test 144: 01101 test 145: 01111 test 146: 10001 test 147: 10011 test 148: 10101 test 149: 10111 test 150: 11001 test 151: 11011 test 152: 11101 test 153: 11110 test 154: 00001 test 155: 00011 test 156: 00101 test 157: 00111 test 158: 01001 test 159: 01011 test 160: 01101 test 161: 01111 test 162: 10001 test 163: 10011 test 164: 10101 test 165: 10111 test 166: 11001 test 167: 11011 test 168: 11101 test 169: 11110 test 170: 00001 test 171: 00011 test 172: 00101 test 173: 00111 test 174: 01001 test 175: 01011 test 176: 01101 test 177: 01111 test 178: 10001 test 179: 10011 test 180: 10101 test 181: 10111 test 182: 11001 test 183: 11011 test 184: 11101 test 185: 11110 test 186: 00001 test 187: 00011 test 188: 00101 test 189: 00111 test 190: 01001 test 191: 01011 test 192: 01101 test 193: 01111 test 194: 10001 test 195: 10011 test 196: 10101 test 197: 10111 test 198: 11001 test 199: 11011 test 200: 11101 test 201: 11110 test 202: 111101111011110111101111011110 end: END summary column 1: offset 0, mask 0x8000 column 2: offset 0, mask 0x4000 column 3: offset 0, mask 0x2000 column 4: offset 0, mask 0x1000 column 5: offset 0, mask 0x0800 column 6: offset 0, mask 0x0010 column 7: offset 0, mask 0x0008 column 8: offset 0, mask 0x0004 column 9: offset 0, mask 0x0002 column 10: offset 0, mask 0x0001 column 11: offset 0, mask 0x0400 column 12: offset 0, mask 0x0200 column 13: offset 0, mask 0x0100 column 14: offset 1, mask 0x8000 column 15: offset 1, mask 0x4000 column 16: offset 1, mask 0x0001 column 17: offset 1, mask 0x0002 column 18: offset 1, mask 0x0004 column 19: offset 1, mask 0x0008 column 20: offset 1, mask 0x0010 column 21: offset 1, mask 0x2000 column 22: offset 1, mask 0x1000 column 23: offset 1, mask 0x0800 column 24: offset 1, mask 0x0400 column 25: offset 1, mask 0x0200 column 26: offset 1, mask 0x0020 column 27: offset 1, mask 0x0040 column 28: offset 1, mask 0x0080 column 29: offset 2, mask 0x0001 column 30: offset 2, mask 0x0002 direction bits (1=input) 0x08E1 0x4310 0xFFFA 0xFFFF 0xF0FF pullup bits (1=pullup) 0x0000 0x0000 0x0000 0x0000 0x0000 test step out_data dont care 1: 0x0801 0x4210 0x0002 0x0000 0x0000 2: 0x0801 0x4210 0x0002 0x0000 0x0000 3: 0x1801 0x4210 0x0002 0x0000 0x0000 4: 0x2801 0x4210 0x0002 0x0000 0x0000 5: 0x3801 0x4210 0x0002 0x0000 0x0000 6: 0x4801 0x4210 0x0002 0x0000 0x0000 7: 0x5801 0x4210 0x0002 0x0000 0x0000 8: 0x6801 0x4210 0x0002 0x0000 0x0000 9: 0x7801 0x4210 0x0002 0x0000 0x0000 10: 0x8801 0x4210 0x0002 0x0000 0x0000 11: 0x9801 0x4210 0x0002 0x0000 0x0000 12: 0xA801 0x4210 0x0002 0x0000 0x0000 13: 0xB801 0x4210 0x0002 0x0000 0x0000 14: 0xC801 0x4210 0x0002 0x0000 0x0000 15: 0xD801 0x4210 0x0002 0x0000 0x0000 16: 0xE801 0x4210 0x0002 0x0000 0x0000 17: 0xF001 0x4210 0x0002 0x0000 0x0000 18: 0x0801 0x4210 0x0002 0x0000 0x0000 19: 0x0801 0x4210 0x0002 0x0000 0x0000 20: 0x0803 0x4210 0x0002 0x0000 0x0000 21: 0x0805 0x4210 0x0002 0x0000 0x0000 22: 0x0807 0x4210 0x0002 0x0000 0x0000 23: 0x0809 0x4210 0x0002 0x0000 0x0000 24: 0x080B 0x4210 0x0002 0x0000 0x0000 25: 0x080D 0x4210 0x0002 0x0000 0x0000 26: 0x080F 0x4210 0x0002 0x0000 0x0000 27: 0x0811 0x4210 0x0002 0x0000 0x0000 28: 0x0813 0x4210 0x0002 0x0000 0x0000 29: 0x0815 0x4210 0x0002 0x0000 0x0000 30: 0x0817 0x4210 0x0002 0x0000 0x0000 31: 0x0819 0x4210 0x0002 0x0000 0x0000 32: 0x081B 0x4210 0x0002 0x0000 0x0000 33: 0x081D 0x4210 0x0002 0x0000 0x0000 34: 0x081E 0x4210 0x0002 0x0000 0x0000 35: 0x0801 0x4210 0x0002 0x0000 0x0000 36: 0x0801 0x4210 0x0002 0x0000 0x0000 37: 0x0801 0xC210 0x0002 0x0000 0x0000 38: 0x0901 0x4210 0x0002 0x0000 0x0000 39: 0x0901 0xC210 0x0002 0x0000 0x0000 40: 0x0A01 0x4210 0x0002 0x0000 0x0000 41: 0x0A01 0xC210 0x0002 0x0000 0x0000 42: 0x0B01 0x4210 0x0002 0x0000 0x0000 43: 0x0B01 0xC210 0x0002 0x0000 0x0000 44: 0x0C01 0x4210 0x0002 0x0000 0x0000 45: 0x0C01 0xC210 0x0002 0x0000 0x0000 46: 0x0D01 0x4210 0x0002 0x0000 0x0000 47: 0x0D01 0xC210 0x0002 0x0000 0x0000 48: 0x0E01 0x4210 0x0002 0x0000 0x0000 49: 0x0E01 0xC210 0x0002 0x0000 0x0000 50: 0x0F01 0x4210 0x0002 0x0000 0x0000 51: 0x0F01 0x8210 0x0002 0x0000 0x0000 52: 0x0801 0x4210 0x0002 0x0000 0x0000 53: 0x0801 0x4210 0x0002 0x0000 0x0000 54: 0x0801 0x4218 0x0002 0x0000 0x0000 55: 0x0801 0x4214 0x0002 0x0000 0x0000 56: 0x0801 0x421C 0x0002 0x0000 0x0000 57: 0x0801 0x4212 0x0002 0x0000 0x0000 58: 0x0801 0x421A 0x0002 0x0000 0x0000 59: 0x0801 0x4216 0x0002 0x0000 0x0000 60: 0x0801 0x421E 0x0002 0x0000 0x0000 61: 0x0801 0x4211 0x0002 0x0000 0x0000 62: 0x0801 0x4219 0x0002 0x0000 0x0000 63: 0x0801 0x4215 0x0002 0x0000 0x0000 64: 0x0801 0x421D 0x0002 0x0000 0x0000 65: 0x0801 0x4213 0x0002 0x0000 0x0000 66: 0x0801 0x421B 0x0002 0x0000 0x0000 67: 0x0801 0x4217 0x0002 0x0000 0x0000 68: 0x0801 0x420F 0x0002 0x0000 0x0000 69: 0x0801 0x4210 0x0002 0x0000 0x0000 70: 0x0801 0x4210 0x0002 0x0000 0x0000 71: 0x0801 0x4610 0x0002 0x0000 0x0000 72: 0x0801 0x4A10 0x0002 0x0000 0x0000 73: 0x0801 0x4E10 0x0002 0x0000 0x0000 74: 0x0801 0x5210 0x0002 0x0000 0x0000 75: 0x0801 0x5610 0x0002 0x0000 0x0000 76: 0x0801 0x5A10 0x0002 0x0000 0x0000 77: 0x0801 0x5E10 0x0002 0x0000 0x0000 78: 0x0801 0x6210 0x0002 0x0000 0x0000 79: 0x0801 0x6610 0x0002 0x0000 0x0000 80: 0x0801 0x6A10 0x0002 0x0000 0x0000 81: 0x0801 0x6E10 0x0002 0x0000 0x0000 82: 0x0801 0x7210 0x0002 0x0000 0x0000 83: 0x0801 0x7610 0x0002 0x0000 0x0000 84: 0x0801 0x7A10 0x0002 0x0000 0x0000 85: 0x0801 0x7C10 0x0002 0x0000 0x0000 86: 0x0801 0x4210 0x0002 0x0000 0x0000 87: 0x0801 0x4210 0x0002 0x0000 0x0000 88: 0x0801 0x4210 0x0003 0x0000 0x0000 89: 0x0801 0x4290 0x0002 0x0000 0x0000 90: 0x0801 0x4290 0x0003 0x0000 0x0000 91: 0x0801 0x4250 0x0002 0x0000 0x0000 92: 0x0801 0x4250 0x0003 0x0000 0x0000 93: 0x0801 0x42D0 0x0002 0x0000 0x0000 94: 0x0801 0x42D0 0x0003 0x0000 0x0000 95: 0x0801 0x4230 0x0002 0x0000 0x0000 96: 0x0801 0x4230 0x0003 0x0000 0x0000 97: 0x0801 0x42B0 0x0002 0x0000 0x0000 98: 0x0801 0x42B0 0x0003 0x0000 0x0000 99: 0x0801 0x4270 0x0002 0x0000 0x0000 100: 0x0801 0x4270 0x0003 0x0000 0x0000 101: 0x0801 0x42F0 0x0002 0x0000 0x0000 102: 0x0801 0x42F0 0x0001 0x0000 0x0000 103: 0x0801 0x4210 0x0002 0x0000 0x0000 104: 0x0801 0x4210 0x0002 0x0000 0x0000 105: 0xF71E 0xBCEF 0x0001 0x0000 0x0000 106: 0x0F1E 0xBCEF 0x0001 0x0000 0x0000 107: 0x1F1E 0xBCEF 0x0001 0x0000 0x0000 108: 0x2F1E 0xBCEF 0x0001 0x0000 0x0000 109: 0x3F1E 0xBCEF 0x0001 0x0000 0x0000 110: 0x4F1E 0xBCEF 0x0001 0x0000 0x0000 111: 0x5F1E 0xBCEF 0x0001 0x0000 0x0000 112: 0x6F1E 0xBCEF 0x0001 0x0000 0x0000 113: 0x7F1E 0xBCEF 0x0001 0x0000 0x0000 114: 0x8F1E 0xBCEF 0x0001 0x0000 0x0000 115: 0x9F1E 0xBCEF 0x0001 0x0000 0x0000 116: 0xAF1E 0xBCEF 0x0001 0x0000 0x0000 117: 0xBF1E 0xBCEF 0x0001 0x0000 0x0000 118: 0xCF1E 0xBCEF 0x0001 0x0000 0x0000 119: 0xDF1E 0xBCEF 0x0001 0x0000 0x0000 120: 0xEF1E 0xBCEF 0x0001 0x0000 0x0000 121: 0xF71E 0xBCEF 0x0001 0x0000 0x0000 122: 0xF701 0xBCEF 0x0001 0x0000 0x0000 123: 0xF703 0xBCEF 0x0001 0x0000 0x0000 124: 0xF705 0xBCEF 0x0001 0x0000 0x0000 125: 0xF707 0xBCEF 0x0001 0x0000 0x0000 126: 0xF709 0xBCEF 0x0001 0x0000 0x0000 127: 0xF70B 0xBCEF 0x0001 0x0000 0x0000 128: 0xF70D 0xBCEF 0x0001 0x0000 0x0000 129: 0xF70F 0xBCEF 0x0001 0x0000 0x0000 130: 0xF711 0xBCEF 0x0001 0x0000 0x0000 131: 0xF713 0xBCEF 0x0001 0x0000 0x0000 132: 0xF715 0xBCEF 0x0001 0x0000 0x0000 133: 0xF717 0xBCEF 0x0001 0x0000 0x0000 134: 0xF719 0xBCEF 0x0001 0x0000 0x0000 135: 0xF71B 0xBCEF 0x0001 0x0000 0x0000 136: 0xF71D 0xBCEF 0x0001 0x0000 0x0000 137: 0xF71E 0xBCEF 0x0001 0x0000 0x0000 138: 0xF01E 0x7CEF 0x0001 0x0000 0x0000 139: 0xF01E 0xFCEF 0x0001 0x0000 0x0000 140: 0xF11E 0x7CEF 0x0001 0x0000 0x0000 141: 0xF11E 0xFCEF 0x0001 0x0000 0x0000 142: 0xF21E 0x7CEF 0x0001 0x0000 0x0000 143: 0xF21E 0xFCEF 0x0001 0x0000 0x0000 144: 0xF31E 0x7CEF 0x0001 0x0000 0x0000 145: 0xF31E 0xFCEF 0x0001 0x0000 0x0000 146: 0xF41E 0x7CEF 0x0001 0x0000 0x0000 147: 0xF41E 0xFCEF 0x0001 0x0000 0x0000 148: 0xF51E 0x7CEF 0x0001 0x0000 0x0000 149: 0xF51E 0xFCEF 0x0001 0x0000 0x0000 150: 0xF61E 0x7CEF 0x0001 0x0000 0x0000 151: 0xF61E 0xFCEF 0x0001 0x0000 0x0000 152: 0xF71E 0x7CEF 0x0001 0x0000 0x0000 153: 0xF71E 0xBCEF 0x0001 0x0000 0x0000 154: 0xF71E 0xBCF0 0x0001 0x0000 0x0000 155: 0xF71E 0xBCF8 0x0001 0x0000 0x0000 156: 0xF71E 0xBCF4 0x0001 0x0000 0x0000 157: 0xF71E 0xBCFC 0x0001 0x0000 0x0000 158: 0xF71E 0xBCF2 0x0001 0x0000 0x0000 159: 0xF71E 0xBCFA 0x0001 0x0000 0x0000 160: 0xF71E 0xBCF6 0x0001 0x0000 0x0000 161: 0xF71E 0xBCFE 0x0001 0x0000 0x0000 162: 0xF71E 0xBCF1 0x0001 0x0000 0x0000 163: 0xF71E 0xBCF9 0x0001 0x0000 0x0000 164: 0xF71E 0xBCF5 0x0001 0x0000 0x0000 165: 0xF71E 0xBCFD 0x0001 0x0000 0x0000 166: 0xF71E 0xBCF3 0x0001 0x0000 0x0000 167: 0xF71E 0xBCFB 0x0001 0x0000 0x0000 168: 0xF71E 0xBCF7 0x0001 0x0000 0x0000 169: 0xF71E 0xBCEF 0x0001 0x0000 0x0000 170: 0xF71E 0x82EF 0x0001 0x0000 0x0000 171: 0xF71E 0x86EF 0x0001 0x0000 0x0000 172: 0xF71E 0x8AEF 0x0001 0x0000 0x0000 173: 0xF71E 0x8EEF 0x0001 0x0000 0x0000 174: 0xF71E 0x92EF 0x0001 0x0000 0x0000 175: 0xF71E 0x96EF 0x0001 0x0000 0x0000 176: 0xF71E 0x9AEF 0x0001 0x0000 0x0000 177: 0xF71E 0x9EEF 0x0001 0x0000 0x0000 178: 0xF71E 0xA2EF 0x0001 0x0000 0x0000 179: 0xF71E 0xA6EF 0x0001 0x0000 0x0000 180: 0xF71E 0xAAEF 0x0001 0x0000 0x0000 181: 0xF71E 0xAEEF 0x0001 0x0000 0x0000 182: 0xF71E 0xB2EF 0x0001 0x0000 0x0000 183: 0xF71E 0xB6EF 0x0001 0x0000 0x0000 184: 0xF71E 0xBAEF 0x0001 0x0000 0x0000 185: 0xF71E 0xBCEF 0x0001 0x0000 0x0000 186: 0xF71E 0xBC0F 0x0002 0x0000 0x0000 187: 0xF71E 0xBC0F 0x0003 0x0000 0x0000 188: 0xF71E 0xBC8F 0x0002 0x0000 0x0000 189: 0xF71E 0xBC8F 0x0003 0x0000 0x0000 190: 0xF71E 0xBC4F 0x0002 0x0000 0x0000 191: 0xF71E 0xBC4F 0x0003 0x0000 0x0000 192: 0xF71E 0xBCCF 0x0002 0x0000 0x0000 193: 0xF71E 0xBCCF 0x0003 0x0000 0x0000 194: 0xF71E 0xBC2F 0x0002 0x0000 0x0000 195: 0xF71E 0xBC2F 0x0003 0x0000 0x0000 196: 0xF71E 0xBCAF 0x0002 0x0000 0x0000 197: 0xF71E 0xBCAF 0x0003 0x0000 0x0000 198: 0xF71E 0xBC6F 0x0002 0x0000 0x0000 199: 0xF71E 0xBC6F 0x0003 0x0000 0x0000 200: 0xF71E 0xBCEF 0x0002 0x0000 0x0000 201: 0xF71E 0xBCEF 0x0001 0x0000 0x0000 202: 0xF71E 0xBCEF 0x0001 0x0000 0x0000 PINs used (in edge connector order) (G=ground,P=power) SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBB LETTER ABCDEFHJKLMNPRSTUVABCDEFHJKLMNPRSTUVABCDEFHJKLMNPRSTUVABCDEFHJKLMNPRSTUV SIDE 111111111111111111222222222222222222111111111111111111222222222222222222 USAGE IIIIOIIIIOIIIIOG P GIIIIOIIIIOIIIIO G P G UUT inputs: 24 UUT outputs: 6 pins used: 30 not used: 36 202 'test steps' 238 lines M516 POSITIVE BUS RECEIVER (6 4-input NAND) (3 7420) PCB REV A SCHEMATIC REV (blank) PINS Main menu Mon Jul 10 15:37:12 2017 test file is: tests\m516.tst delay is: 0 trigger is: 1 1 read test file 2 set test delay 3 set test trigger 4 run test 5 output loading test 8 diags 9 exit UUT power is okay Mon Jul 10 15:37:12 2017 space single step O run once (one test, all steps) F run, stop on fail G go (run tests N run, stop on fail, no print S scope (run, no print) C turn on comment printout + increase speed (less delay) - decrease speed (more delay)(slower) Q quit test scope (run, no print) ppppppppppppppppppppppppppppppppppppppppppp space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn on comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEDEFHJFHJKLKLMNPMNPRSRSTUV SIDE 111112222211111222221111122222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO all fails was lo 000000000000000000000000000000 falling vvvvvvvvvvvvvvvvvvvvvvvvvvvvvv rising ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ was hi 111111111111111111111111111111 total fails 0, total passes 43 Main menu Mon Jul 10 15:37:22 2017 test file is: tests\m516.tst delay is: 0 trigger is: 1 1 read test file 2 set test delay 3 set test trigger 4 run test 5 output loading test 8 diags 9 exit UUT power is okay Mon Jul 10 15:37:38 2017 space single step O run once (one test, all steps) F run, stop on fail G go (run tests N run, stop on fail, no print S scope (run, no print) C turn on comment printout + increase speed (less delay) - decrease speed (more delay)(slower) Q quit test SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEDEFHJFHJKLKLMNPMNPRSRSTUV SIDE 111112222211111222221111122222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO all fails was lo falling rising was hi total fails 0, total passes 0 Main menu Mon Jul 10 15:37:54 2017 test file is: tests\m516.tst delay is: 0 trigger is: 1 1 read test file 2 set test delay 3 set test trigger 4 run test 5 output loading test 8 diags 9 exit UUT power is okay Mon Jul 10 15:37:58 2017 space single step O run once (one test, all steps) F run, stop on fail G go (run tests N run, stop on fail, no print S scope (run, no print) C turn on comment printout + increase speed (less delay) - decrease speed (more delay)(slower) Q quit test scope (run, no print) ppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppFFFFFFFFF FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF FFFFFFFFFFFpFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF FFFFFF space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn on comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEDEFHJFHJKLKLMNPMNPRSRSTUV SIDE 111112222211111222221111122222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO all fails O was lo 000000000000000000000000000000 falling vvvvvvvvvvvvvvvvvvvvvvvvvvvvvv rising ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ was hi 111111111111111111111111111111 total fails 172, total passes 71 Main menu Mon Jul 10 15:53:06 2017 test file is: tests\m516.tst delay is: 0 trigger is: 1 1 read test file 2 set test delay 3 set test trigger 4 run test 5 output loading test 8 diags 9 exit exiting tester- PDP8 card tester via printer port version 0.91 November 27, 2015 mapping[] is verified Main menu Thu Jul 13 13:10:14 2017 test file is: delay is: 0 trigger is: 1 1 read test file 2 set test delay 3 set test trigger 4 run test 5 output loading test 8 diags 9 exit Enter test file name? trying to open test file: tests\m216.tst reading test file: tests\m216.tst comment: M216 6 FLIP FLOPS comment: pins: PINS pins: 1 I AA1 E1-1 CLEAR-N E1-5/6 E1-8/9 E2-5/6 pins: 2 I AB1 E1-3 CLOCK E1-5/6 pins: 3 I AC1 E1-2 DATA E1-5/6 pins: 4 I AD1 E1-4 SET-N E1-5/6 pins: 5 O AE1 E1-5 Q E1-5/6 pins: 6 O AF1 E1-5 Q-N E1-5/6 pins: 7 I AD2 E1-11 CLOCK E1-8/9 pins: 8 I AE2 E1-12 DATA E1-8/9 pins: 9 I AF2 E1-10 SET-N E1-8/9 pins: 10 O AH2 E1-9 Q E1-8/9 pins: 11 O AJ2 E1-8 Q-N E1-8/9 pins: 12 I AH1 E2-3 CLOCK E2-5/6 pins: 13 I AJ1 E2-2 DATA E2-5/6 pins: 14 I AK1 E2-4 SET-N E2-5/6 pins: 15 O AL1 E2-5 Q E2-5/6 pins: 16 O AM1 E2-6 Q-N E2-5/6 pins: 17 I AK2 E3-13 CLEAR-N E3-8/9 E3-5/6 E2-8/9 pins: 18 I AL2 E3-11 CLOCK E3-8/9 pins: 19 I AM2 E3-12 DATA E3-8/9 pins: 20 I AN2 E3-10 SET-N E3-8/9 pins: 21 O AP2 E3-9 Q E3-8/9 pins: 22 O AR2 E3-8 Q-N E3-8/9 pins: 23 I AN1 E3-3 CLOCK E3-5/6 pins: 24 I AP1 E3-2 DATA E3-5/6 pins: 25 I AR1 E3-4 SET-N E3-5/6 pins: 26 O AS1 E3-5 Q E3-5/6 pins: 27 O AU1 E3-6 Q-N E3-5/6 pins: 28 I AS2 E2-11 CLOCK E2-8/9 pins: 29 I AT2 E2-12 DATA E2-8/9 pins: 30 I AU2 E2-10 SET-N E2-8/9 pins: 31 O AV2 E2-9 Q E2-8/9 pins: 32 O AV1 E2-8 Q-N E2-8/9 pins: direction: IIIIOOIIIOOIIIOOIIIIOOIIIOOIIIOO test 1: 00001100011000110000110001100011 test 2: 100010 10 10 test 3: 100110 test 4: 110101 test 5: 111101 test 6: 101101 test 7: 111110 test 8: 110110 test 9: 100110 test 10: 000101 11 11 test 11: 100101 10 10 test 12: 100010 test 13: 00001100011000110000110001100011 test 14: 1 1000010 10 test 15: 1 00110 test 16: 1 10101 test 17: 1 11101 test 18: 1 01101 test 19: 1 11110 test 20: 1 10110 test 21: 1 00110 test 22: 0 1100101 11 test 23: 1 1000101 10 test 24: 1 00010 test 25: 00001100011000110000110001100011 test 26: 1 10 1000010 test 27: 1 00110 test 28: 1 10101 test 29: 1 11101 test 30: 1 01101 test 31: 1 11110 test 32: 1 10110 test 33: 1 00110 test 34: 0 11 1100101 test 35: 1 10 1000101 test 36: 1 00010 test 37: 00001100011000110000110001100011 test 38: 100010 10 10 test 39: 100110 test 40: 110101 test 41: 111101 test 42: 101101 test 43: 111110 test 44: 110110 test 45: 100110 test 46: 000101 11 11 test 47: 100101 10 10 test 48: 100010 test 49: 00001100011000110000110001100011 test 50: 1 1000010 10 test 51: 1 00110 test 52: 1 10101 test 53: 1 11101 test 54: 1 01101 test 55: 1 11110 test 56: 1 10110 test 57: 1 00110 test 58: 0 1100101 11 test 59: 1 1000101 10 test 60: 1 00010 test 61: 00001100011000110000110001100011 test 62: 1 10 1000010 test 63: 1 00110 test 64: 1 10101 test 65: 1 11101 test 66: 1 01101 test 67: 1 11110 test 68: 1 10110 test 69: 1 00110 test 70: 0 11 1100101 test 71: 1 10 1000101 test 72: 1 00010 test 73: 00001100011000110000110001100011 end: END summary column 1: offset 0, mask 0x8000 column 2: offset 0, mask 0x4000 column 3: offset 0, mask 0x2000 column 4: offset 0, mask 0x1000 column 5: offset 0, mask 0x0800 column 6: offset 0, mask 0x0400 column 7: offset 0, mask 0x0010 column 8: offset 0, mask 0x0008 column 9: offset 0, mask 0x0004 column 10: offset 0, mask 0x0002 column 11: offset 0, mask 0x0001 column 12: offset 0, mask 0x0200 column 13: offset 0, mask 0x0100 column 14: offset 1, mask 0x8000 column 15: offset 1, mask 0x4000 column 16: offset 1, mask 0x2000 column 17: offset 1, mask 0x0001 column 18: offset 1, mask 0x0002 column 19: offset 1, mask 0x0004 column 20: offset 1, mask 0x0008 column 21: offset 1, mask 0x0010 column 22: offset 1, mask 0x0020 column 23: offset 1, mask 0x1000 column 24: offset 1, mask 0x0800 column 25: offset 1, mask 0x0400 column 26: offset 1, mask 0x0200 column 27: offset 2, mask 0x8000 column 28: offset 1, mask 0x0040 column 29: offset 1, mask 0x0080 column 30: offset 2, mask 0x0001 column 31: offset 2, mask 0x0002 column 32: offset 2, mask 0x4000 direction bits (1=input) 0x0CE3 0x6330 0xFFFA 0xFFFF 0xF0FF pullup bits (1=pullup) 0x0000 0x0000 0x0000 0x0000 0x0000 test step out_data dont care 1: 0x0C03 0x6230 0xC002 0x0000 0x0000 2: 0x8802 0x4230 0xC002 0x0000 0x0000 3: 0x9802 0x4230 0xC002 0x0000 0x0000 4: 0xD402 0x4230 0xC002 0x0000 0x0000 5: 0xF402 0x4230 0xC002 0x0000 0x0000 6: 0xB402 0x4230 0xC002 0x0000 0x0000 7: 0xF802 0x4230 0xC002 0x0000 0x0000 8: 0xD802 0x4230 0xC002 0x0000 0x0000 9: 0x9802 0x4230 0xC002 0x0000 0x0000 10: 0x1403 0x6230 0xC002 0x0000 0x0000 11: 0x9402 0x4230 0xC002 0x0000 0x0000 12: 0x8802 0x4230 0xC002 0x0000 0x0000 13: 0x0C03 0x6230 0xC002 0x0000 0x0000 14: 0x8802 0x4230 0xC002 0x0000 0x0000 15: 0x8806 0x4230 0xC002 0x0000 0x0000 16: 0x8815 0x4230 0xC002 0x0000 0x0000 17: 0x881D 0x4230 0xC002 0x0000 0x0000 18: 0x880D 0x4230 0xC002 0x0000 0x0000 19: 0x881E 0x4230 0xC002 0x0000 0x0000 20: 0x8816 0x4230 0xC002 0x0000 0x0000 21: 0x8806 0x4230 0xC002 0x0000 0x0000 22: 0x0C05 0x6230 0xC002 0x0000 0x0000 23: 0x8805 0x4230 0xC002 0x0000 0x0000 24: 0x8802 0x4230 0xC002 0x0000 0x0000 25: 0x0C03 0x6230 0xC002 0x0000 0x0000 26: 0x8802 0x4230 0xC002 0x0000 0x0000 27: 0x8802 0xC230 0xC002 0x0000 0x0000 28: 0x8A02 0xA230 0xC002 0x0000 0x0000 29: 0x8B02 0xA230 0xC002 0x0000 0x0000 30: 0x8902 0xA230 0xC002 0x0000 0x0000 31: 0x8B02 0xC230 0xC002 0x0000 0x0000 32: 0x8A02 0xC230 0xC002 0x0000 0x0000 33: 0x8802 0xC230 0xC002 0x0000 0x0000 34: 0x0C03 0xA230 0xC002 0x0000 0x0000 35: 0x8802 0xA230 0xC002 0x0000 0x0000 36: 0x8802 0x4230 0xC002 0x0000 0x0000 37: 0x0C03 0x6230 0xC002 0x0000 0x0000 38: 0x0C03 0x6211 0x0002 0x0000 0x0000 39: 0x0C03 0x6219 0x0002 0x0000 0x0000 40: 0x0C03 0x622B 0x0002 0x0000 0x0000 41: 0x0C03 0x622F 0x0002 0x0000 0x0000 42: 0x0C03 0x622D 0x0002 0x0000 0x0000 43: 0x0C03 0x621F 0x0002 0x0000 0x0000 44: 0x0C03 0x621B 0x0002 0x0000 0x0000 45: 0x0C03 0x6219 0x0002 0x0000 0x0000 46: 0x0C03 0x6228 0xC002 0x0000 0x0000 47: 0x0C03 0x6229 0x0002 0x0000 0x0000 48: 0x0C03 0x6211 0x0002 0x0000 0x0000 49: 0x0C03 0x6230 0xC002 0x0000 0x0000 50: 0x0C03 0x6211 0x0002 0x0000 0x0000 51: 0x0C03 0x6611 0x0002 0x0000 0x0000 52: 0x0C03 0x7411 0x8002 0x0000 0x0000 53: 0x0C03 0x7C11 0x8002 0x0000 0x0000 54: 0x0C03 0x6C11 0x8002 0x0000 0x0000 55: 0x0C03 0x7E11 0x0002 0x0000 0x0000 56: 0x0C03 0x7611 0x0002 0x0000 0x0000 57: 0x0C03 0x6611 0x0002 0x0000 0x0000 58: 0x0C03 0x6430 0xC002 0x0000 0x0000 59: 0x0C03 0x6411 0x8002 0x0000 0x0000 60: 0x0C03 0x6211 0x0002 0x0000 0x0000 61: 0x0C03 0x6230 0xC002 0x0000 0x0000 62: 0x0C03 0x6211 0x0002 0x0000 0x0000 63: 0x0C03 0x6211 0x0003 0x0000 0x0000 64: 0x0C03 0x6251 0x4001 0x0000 0x0000 65: 0x0C03 0x62D1 0x4001 0x0000 0x0000 66: 0x0C03 0x6291 0x4001 0x0000 0x0000 67: 0x0C03 0x62D1 0x0003 0x0000 0x0000 68: 0x0C03 0x6251 0x0003 0x0000 0x0000 69: 0x0C03 0x6211 0x0003 0x0000 0x0000 70: 0x0C03 0x6230 0xC001 0x0000 0x0000 71: 0x0C03 0x6211 0x4001 0x0000 0x0000 72: 0x0C03 0x6211 0x0002 0x0000 0x0000 73: 0x0C03 0x6230 0xC002 0x0000 0x0000 PINs used (in edge connector order) (G=ground,P=power) SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBB LETTER ABCDEFHJKLMNPRSTUVABCDEFHJKLMNPRSTUVABCDEFHJKLMNPRSTUVABCDEFHJKLMNPRSTUV SIDE 111111111111111111222222222222222222111111111111111111222222222222222222 USAGE IIIIOOIIIOOIIIOGOOP GIIIOOIIIIOOIIIO G P G UUT inputs: 20 UUT outputs: 12 pins used: 32 not used: 34 73 'test steps' 111 lines M216 6 FLIP FLOPS PINS Main menu Thu Jul 13 13:10:19 2017 test file is: tests\m216.tst delay is: 0 trigger is: 1 1 read test file 2 set test delay 3 set test trigger 4 run test 5 output loading test 8 diags 9 exit UUT power is okay Thu Jul 13 13:10:23 2017 space single step O run once (one test, all steps) F run, stop on fail G go (run tests N run, stop on fail, no print S scope (run, no print) C turn on comment printout + increase speed (less delay) - decrease speed (more delay)(slower) Q quit test scope (run, no print) ppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppp ppppppppppppppp space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn on comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFDEFHJHJKLMKLMNPRNPRSUSTUVV SIDE 11111122222111112222221111122221 DIRECTION IIIIOOIIIOOIIIOOIIIIOOIIIOOIIIOO all fails was lo 00000000000000000000000000000000 falling vvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvv rising ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ was hi 11111111111111111111111111111111 total fails 0, total passes 94 Main menu Thu Jul 13 13:10:27 2017 test file is: tests\m216.tst delay is: 0 trigger is: 1 1 read test file 2 set test delay 3 set test trigger 4 run test 5 output loading test 8 diags 9 exit exiting