tester- PDP8 card tester via printer port version 0.85 June 4, 2015 mapping[] is verified Main menu Sat Jul 11 10:55:36 2015 test file is: delay is: 0 trigger is: 1 1 read test file 2 set test delay 3 set test trigger 4 run test 5 output loading test 8 diags 9 exit Enter test file name? trying to open test file: tests\m222.new reading test file: tests\m222.new comment: M222 PCB REV B SCHEMATIC REV A LINC TAPE REGISTERS comment: comment: TERMINOLOGY- SIGNALS REFER TO VOL4 M222 SCHEMATIC. comment: comment: BUT... comment: comment: DEC USES AND-NOR GATES TO ROUTE THE ADDER A AND B INPUTS, SO... comment: DEC RENAMED THE ADDER TO NEGATIVE LOGIC TERMS (I.E. A-N + B-N + C-N -> SUM-N, C1-N). comment: (NOT THE 7482 DATASHEET NAMES OF A + B + C -> SUM, C1). comment: comment: SO, WITH ALL 'AND ENABLES' LOW, THE AND-NOR OUTPUTS = HIGH. comment: WITH C-L HIGH, THE ADDER OUTPUT IS SUM-N=1, C1-N=1; comment: THE INVERTED ADDER OUTPUT IS LOW (TAPE BUS). comment: AND THERE IS NO CARRY (C1-N IS HI). comment: comment: THE TWO ADDERS, TWO REGISTER BITS, ETC ARE LABELED BIT 2 (EVEN, MSB) AND BIT 3 (ODD, LSB). comment: THE ADDERS ARE REFERRED TO AS 'ADDER2' (MSB) AND 'ADDER3' (LSB). comment: comment: POWER PINS: comment: AA2 +5V comment: AT1 GROUND comment: AC2 GROUND comment: BA2 +5V comment: BT1 GROUND comment: BC2 GROUND comment: comment: (ALL PINS ARE USED). comment: comment: pins: PINS pins: 1 I BA1 CARRY IN-N, (TO E9-5 7482 C0) C-N TO ADDER2 pins: 2 I AL2 AND-NOR ENABLE: TAC TAC3 TO PIN BB2 (TO ADDER3) TAC2 TO PIN AN2 (TO ADDER2) pins: 3 I AP1 AND-NOR ENABLE: TMA SETUP (TMAS)3 TO PIN BB2 (TO ADDER3), (TMAS)3 TO PIN AN2 (TO ADDER2) pins: 4 I AS2 AND-NOR ENABLE: TMA TMA3 TO PIN BB2 (TO ADDER3), TMA2 TO PIN AN2 (TO ADDER2) pins: 5 I AL1 AND-NOR ENABLE: PIN AF2 TO PIN BB2 (TO ADDER3), PIN AM1 TO PIN AN2 (TO ADDER2) pins: 6 I AF2 AND-NOR INPUT (AL1 ENABLES) TO PIN BB2 (TO ADDER3). pins: 7 I AM1 AND-NOR INPUT (AL1 ENABLES) TO PIN AN2 (TO ADDER2) pins: 8 I AD2 AND-NOR ENABLE: RWB RWB3 TO PIN BB2 (TO ADDER3), RWB2 TO PIN AN2 (TO ADDER2) pins: 9 I AE2 AND-NOR ENABLE: PIN AE1 TO PIN BB2 (TO ADDER3), PIN AM2 TO PIN AN2 (TO ADDER2) pins: 10 I AE1 AND-NOR INPUT (AE2 ENABLES) TO PIN BB2 (TO ADDER3). pins: 11 I AM2 AND-NOR INPUT (AE2 ENABLES) TO PIN AN2 (TO ADDER2) pins: 12 I AC1 AND-NOR INPUT, AND WITH PIN AB2 TO PIN BB2 (TO ADDER3) pins: 13 I AB2 AND-NOR INPUT, AND WITH PIN AC1 TO PIN BB2 (TO ADDER3) pins: 14 I AF1 AND-NOR INPUT (AND WITH ITSELF) TO PIN BB2 (TO ADDER3) pins: 15 I AR2 AND-NOR INPUT, AND WITH PIN AS1 TO PIN AN2 (TO ADDER2) pins: 16 I AS1 AND-NOR INPUT, AND WITH PIN AR2 TO PIN AN2 (TO ADDER2) pins: 17 I AP2 AND-NOR INPUT (AND WITH ITSELF) TO PIN AN2 (TO ADDER2) pins: 18 I BK1 AND-NOR ENABLE: TB3 TO PIN BB1 (TO ADDER3), TB2 TO PIN BN1 (TO ADDER2) pins: 19 I BL1 AND-NOR ENABLE: PIN BE1 TO PIN BB1 (TO ADDER3), PIN BM1 TO PIN BN1 (TO ADDER2) pins: 20 I BE1 AND-NOR INPUT (BL1 ENABLES) TO PIN BB1 (TO ADDER3). pins: 21 I BM1 AND-NOR INPUT (BL1 ENABLES) TO PIN BN1 (TO ADDER2) pins: 22 I BF1 AND-NOR ENABLE: PIN BH1 TO PIN BB1 (TO ADDER3), PIN BR1 TO PIN BN1 (TO ADDER2) pins: 23 I BH1 AND-NOR INPUT (BF1 ENABLES): TO PIN BB1 (TO ADDER3), pins: 24 I BR1 AND-NOR INPUT (BF1 ENABLES): TO PIN BN1 (TO ADDER2) pins: 25 I BS1 AND-NOR ENABLE: PIN BC1 TO PIN BB1 (TO ADDER3), PIN BJ2 TO PIN BN1 (TO ADDER2) pins: 26 I BC1 AND-NOR INPUT (BS1 ENABLES): TO PIN BB1 (TO ADDER3), pins: 27 I BJ2 AND-NOR INPUT (BS1 ENABLES): TO PIN BN1 (TO ADDER2) pins: 28 I BL2 AND-NOR ENABLE: PIN BJ1 TO PIN BB1 (TO ADDER3), PIN BK2 TO PIN BN1 (TO ADDER2) pins: 29 I BJ1 AND-NOR INPUT (BL2 ENABLES): TO PIN BB1 (TO ADDER3), pins: 30 I BK2 AND-NOR INPUT (BL2 ENABLES): TO PIN BN1 (TO ADDER2) pins: 31 I BU1 AND-NOR ENABLE: PIN BH2 TO PIN BB1 (TO ADDER3), PIN BP2 TO PIN BN1 (TO ADDER2) pins: 32 I BH2 AND-NOR INPUT (BU1 ENABLES): TO PIN BB1 (TO ADDER3), pins: 33 I BP2 AND-NOR INPUT (BU1 ENABLES): TO PIN BN1 (TO ADDER2) pins: 34 I BN2 AND-NOR INPUT (AND WITH BM2): TO PIN BN1 (TO ADDER2) pins: 35 I BM2 AND-NOR INPUT (AND WITH BM2): TO PIN BN1 (TO ADDER2) pins: 36 O BB2 AND-NOR OUTPUT, (DRIVES E9-2 7482 A1) TO ADDER3 INPUT pins: 37 O BB1 AND-NOR OUTPUT, (DRIVES E9-3 7482 B1) TO ADDER3 INPUT pins: 38 O BN1 AND-NOR OUTPUT, (DRIVES E9-14 7482 A2) TO ADDER2 INPUT pins: 39 O AN2 AND-NOR OUTPUT, (DRIVES E9-13 7482 B2) TO ADDER2 INPUT pins: 40 O AV2 CARRY OUT-N (E9-10 7482 C2) pins: 41 O BV2 TAPE BUS 2 OUTPUT (INVERTED ADDER2 SUM-N (E9-12 7482 SUM2) pins: 42 O BR2 TAPE BUS 3 OUTPUT (INVERTED ADDER3 SUM-N (E9-1 7482 SUM1) pins: 43 I AK1 LOAD TMA SETUP (FROM TAPE BUS) (RISING EDGE CLOCK) pins: 44 O AR1 TMA SETUP 2 pins: 45 O AH1 TMA SETUP 3 pins: 46 I AU2 LOAD TMA (FROM TAPE BUS) (RISING EDGE CLOCK) pins: 47 O AT2 TMA 2 pins: 48 O AD1 TMA 3 pins: 49 I AJ1 LOAD TBN (FROM TAPE BUS) (RISING EDGE CLOCK) pins: 50 O AU1 TBN 2 pins: 51 O AK2 TBN 3 pins: 52 I AA1 LOAD TAC (FROM TAPE BUS) (RISING EDGE CLOCK) pins: 53 O AN1 TAC 2 pins: 54 O AJ2 TAC 2-N pins: 55 O AH2 TAC 3 pins: 56 O AB1 TAC 3-N pins: 57 I BT2 LOAD TB (FROM TAPE BUS) (RISING EDGE CLOCK) pins: 58 O BP1 TB 2 pins: 59 O BD1 TB 3 pins: 60 I BF2 LOAD RWB (FROM TB) (JAMS CLEAR,SET) pins: 61 I BS2 PHASE (SELECTS POLARITY OF RWB OUT, 0 -> INVERTED) pins: 62 O BV1 RWB OUT (=RWB 2 IF PHASE=1; =RWB 2-N IF PHASE=0) pins: 63 O BD2 RWB 3 pins: 64 I BE2 SHIFT RWB (SHIFTS PIN AV1 INTO RWB 3, SHIFTS RWB3 TO RWB2) (RISING CLOCK) pins: 65 I AV1 RWB IN (SHIFTED INTO RWB 2) pins: 66 O BU2 +3.5V pins: direction: IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIOOOOOOOIOOIOOIOOIOOOOIOOIIOOIIO comment: ; all registers are unknown comment: ; turn on C0, PHASE comment: ; with no ENABLES, BUS2,BUS3 is 11, C2 is 1 test 1: 1000000000000000000000000000000000011111000XX0XX0XX0XXXX0XX01XX001 comment: comment: ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; comment: ; comment: ; set all registers LOW comment: ; comment: ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; comment: comment: ; load TMA SETUP from tape bus (00) test 2: 100 test 3: 0 comment: ; load TMA from tape bus (00) test 4: 100 test 5: 0 comment: ; load TBN from tape bus (00) test 6: 100 test 7: 0 comment: ; load TAC from tape bus (00) test 8: 10101 test 9: 0 comment: ; load TB from tape bus (00) test 10: 100 test 11: 0 comment: ; load RWB from TB (JAMS CLEAR AND PRESET) test 12: 1 00 test 13: 0 comment: ; (no change) test 14: 100000000000000000000000000000000001111100000000000001010000100001 comment: comment: comment: ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; comment: ; comment: ; set all registers HIGH comment: ; comment: ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; comment: comment: ; set pin AF1 (AND with itself) to clear pin BB2 (AND-NOR output) and set pin BR2 TAPE BUS 3 OUTPUT test 15: 1 0 1 comment: ; set pin AP2 (AND with itself) to clear pin AN2 (AND-NOR output) and set pin BV2 TAPE BUS 2 OUTPUT test 16: 1 0 1 comment: comment: comment: ; load TMA SETUP from tape bus (11) test 17: 111 test 18: 0 comment: ; load TMA from tape bus (11) test 19: 111 test 20: 0 comment: ; load TBN from tape bus (11) test 21: 111 test 22: 0 comment: ; load TAC from tape bus (11) test 23: 11010 test 24: 0 comment: ; load TB from tape bus (11) test 25: 111 test 26: 0 comment: ; load RWB from TB (JAMS CLEAR AND PRESET) test 27: 1 11 test 28: 0 comment: ; clear pin AF1 (AND with itself) to set pin BB2 (AND-NOR output) and clear pin BR2 TAPE BUS 3 OUTPUT test 29: 0 1 0 comment: ; clear pin AP2 (AND with itself) to set pin AN2 (AND-NOR output) and clear pin BV2 TAPE BUS 2 OUTPUT test 30: 0 1 0 comment: ; (no change) test 31: 100000000000000000000000000000000001111100011011011010100110111001 comment: comment: comment: ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; comment: ; comment: ; test AND-NOR logic comment: ; comment: ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; comment: comment: ; (all registers are HIGH) comment: ; set all pins HIGH except ENABLES comment: comment: ; set pin AF2 HIGH test 32: 1 comment: ; set pin AM1 HIGH test 33: 1 comment: ; set pin AE1 HIGH test 34: 1 comment: ; set pin AM2 HIGH test 35: 1 comment: ; set pin AB2 HIGH test 36: 1 comment: ; set pin AS1 HIGH test 37: 1 comment: ; set pin BE1 HIGH test 38: 1 comment: ; set pin BM1 HIGH test 39: 1 comment: ; set pin BH1 HIGH test 40: 1 comment: ; set pin BR1 HIGH test 41: 1 comment: ; set pin BC1 HIGH test 42: 1 comment: ; set pin BJ2 HIGH test 43: 1 comment: ; set pin BJ1 HIGH test 44: 1 comment: ; set pin BK2 HIGH test 45: 1 comment: ; set pin BH2 HIGH test 46: 1 comment: ; set pin BP2 HIGH test 47: 1 comment: ; set pin BN2 HIGH test 48: 1 comment: ; toggle each ENABLE comment: comment: ; set pin AL2 to clear pin BB2 and pin AN2 AND-NOR OUTPUTS and set TAPE BUS 2 OUTPUT and TAPE BUS 3 OUTPUT test 49: 1 0 0 11 test 50: 0 1 1 00 comment: ; set pin AP1 to clear pin BB2 and pin AN2 AND-NOR OUTPUTS and set TAPE BUS 2 OUTPUT and TAPE BUS 3 OUTPUT test 51: 1 0 0 11 test 52: 0 1 1 00 comment: ; set pin AS2 to clear pin BB2 and pin AN2 AND-NOR OUTPUTS and set TAPE BUS 2 OUTPUT and TAPE BUS 3 OUTPUT test 53: 1 0 0 11 test 54: 0 1 1 00 comment: ; set pin AL1 to clear pin BB2 and pin AN2 AND-NOR OUTPUTS and set TAPE BUS 2 OUTPUT and TAPE BUS 3 OUTPUT test 55: 1 0 0 11 test 56: 0 1 1 00 comment: ; set pin AL1 to clear pin BB2 and pin AN2 AND-NOR OUTPUTS and set TAPE BUS 2 OUTPUT and TAPE BUS 3 OUTPUT test 57: 1 0 0 11 test 58: 0 1 1 00 comment: ; set pin AE2 to clear pin BB2 and pin AN2 AND-NOR OUTPUTS and set TAPE BUS 2 OUTPUT and TAPE BUS 3 OUTPUT test 59: 1 0 0 11 test 60: 0 1 1 00 comment: ; set pin AC1 to clear pin BB2 and set TAPE BUS 3 OUTPUT test 61: 1 0 1 test 62: 0 1 0 comment: ; set pin AF1 to clear pin BB2 and set TAPE BUS 3 OUTPUT test 63: 1 0 1 test 64: 0 1 0 comment: ; set pin AR2 to clear pin AN2 AND-NOR OUTPUTS and set TAPE BUS 2 OUTPUT test 65: 1 0 1 test 66: 0 1 0 comment: ; set pin AP2 to clear pin AN2 AND-NOR OUTPUTS and set TAPE BUS 2 OUTPUT test 67: 1 0 1 test 68: 0 1 0 comment: comment: ; set pin BK1 to clear pin BB1 and pin BN1 AND-NOR OUTPUTS and set TAPE BUS 2 OUTPUT and TAPE BUS 3 OUTPUT test 69: 1 00 11 test 70: 0 11 00 comment: ; set pin BL1 to clear pin BB1 and pin BN1 AND-NOR OUTPUTS and set TAPE BUS 2 OUTPUT and TAPE BUS 3 OUTPUT test 71: 1 00 11 test 72: 0 11 00 comment: ; set pin BF1 to clear pin BB1 and pin BN1 AND-NOR OUTPUTS and set TAPE BUS 2 OUTPUT and TAPE BUS 3 OUTPUT test 73: 1 00 11 test 74: 0 11 00 comment: ; set pin BS1 to clear pin BB1 and pin BN1 AND-NOR OUTPUTS and set TAPE BUS 2 OUTPUT and TAPE BUS 3 OUTPUT test 75: 1 00 11 test 76: 0 11 00 comment: ; set pin BL2 to clear pin BB1 and pin BN1 AND-NOR OUTPUTS and set TAPE BUS 2 OUTPUT and TAPE BUS 3 OUTPUT test 77: 1 00 11 test 78: 0 11 00 comment: ; set pin BU1 to clear pin BB1 and pin BN1 AND-NOR OUTPUTS and set TAPE BUS 2 OUTPUT and TAPE BUS 3 OUTPUT test 79: 1 00 11 test 80: 0 11 00 comment: ; set pin BM2 to clear pin BB1 and TAPE BUS 3 OUTPUT test 81: 1 0 1 test 82: 0 1 0 comment: comment: comment: ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; comment: ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; comment: ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; comment: ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; comment: ; needs work comment: ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; comment: ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; comment: ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; comment: ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; end: END summary column 1: offset 2, mask 0x2000 column 2: offset 1, mask 0x0002 column 3: offset 1, mask 0x0800 column 4: offset 1, mask 0x0040 column 5: offset 1, mask 0x4000 column 6: offset 0, mask 0x0004 column 7: offset 1, mask 0x2000 column 8: offset 0, mask 0x0010 column 9: offset 0, mask 0x0008 column 10: offset 0, mask 0x0800 column 11: offset 1, mask 0x0004 column 12: offset 0, mask 0x2000 column 13: offset 0, mask 0x0040 column 14: offset 0, mask 0x0400 column 15: offset 1, mask 0x0020 column 16: offset 1, mask 0x0200 column 17: offset 1, mask 0x0010 column 18: offset 3, mask 0x2000 column 19: offset 3, mask 0x1000 column 20: offset 2, mask 0x0200 column 21: offset 3, mask 0x0800 column 22: offset 2, mask 0x0100 column 23: offset 3, mask 0x8000 column 24: offset 3, mask 0x0100 column 25: offset 4, mask 0x8000 column 26: offset 2, mask 0x0800 column 27: offset 3, mask 0x0002 column 28: offset 3, mask 0x0008 column 29: offset 3, mask 0x4000 column 30: offset 3, mask 0x0004 column 31: offset 4, mask 0x2000 column 32: offset 3, mask 0x0001 column 33: offset 3, mask 0x0040 column 34: offset 3, mask 0x0020 column 35: offset 3, mask 0x0010 column 36: offset 2, mask 0x0008 column 37: offset 2, mask 0x1000 column 38: offset 3, mask 0x0400 column 39: offset 1, mask 0x0008 column 40: offset 2, mask 0x0002 column 41: offset 4, mask 0x0008 column 42: offset 3, mask 0x0080 column 43: offset 1, mask 0x8000 column 44: offset 1, mask 0x0400 column 45: offset 0, mask 0x0200 column 46: offset 2, mask 0x0001 column 47: offset 1, mask 0x0080 column 48: offset 0, mask 0x1000 column 49: offset 0, mask 0x0100 column 50: offset 2, mask 0x8000 column 51: offset 1, mask 0x0001 column 52: offset 0, mask 0x8000 column 53: offset 1, mask 0x1000 column 54: offset 0, mask 0x0001 column 55: offset 0, mask 0x0002 column 56: offset 0, mask 0x4000 column 57: offset 4, mask 0x0002 column 58: offset 3, mask 0x0200 column 59: offset 2, mask 0x0400 column 60: offset 2, mask 0x0080 column 61: offset 4, mask 0x0001 column 62: offset 4, mask 0x1000 column 63: offset 2, mask 0x0020 column 64: offset 2, mask 0x0040 column 65: offset 2, mask 0x4000 column 66: offset 4, mask 0x0004 direction bits (1=input) 0x52A3 0x1589 0x943A 0x0680 0x50FC pullup bits (1=pullup) 0x0000 0x0000 0x0000 0x0000 0x0000 test step out_data dont care 1: 0x0000 0x0008 0x300A 0x0400 0x0005 0x5203 0x1481 0x8420 0x0200 0x1000 2: 0x0000 0x8008 0x300A 0x0400 0x0005 0x5003 0x1081 0x8420 0x0200 0x1000 3: 0x0000 0x0008 0x300A 0x0400 0x0005 0x5003 0x1081 0x8420 0x0200 0x1000 4: 0x0000 0x0008 0x300B 0x0400 0x0005 0x4003 0x1001 0x8420 0x0200 0x1000 5: 0x0000 0x0008 0x300A 0x0400 0x0005 0x4003 0x1001 0x8420 0x0200 0x1000 6: 0x0100 0x0008 0x300A 0x0400 0x0005 0x4003 0x1000 0x0420 0x0200 0x1000 7: 0x0000 0x0008 0x300A 0x0400 0x0005 0x4003 0x1000 0x0420 0x0200 0x1000 8: 0xC001 0x0008 0x300A 0x0400 0x0005 0x0000 0x0000 0x0420 0x0200 0x1000 9: 0x4001 0x0008 0x300A 0x0400 0x0005 0x0000 0x0000 0x0420 0x0200 0x1000 10: 0x4001 0x0008 0x300A 0x0400 0x0007 0x0000 0x0000 0x0020 0x0000 0x1000 11: 0x4001 0x0008 0x300A 0x0400 0x0005 0x0000 0x0000 0x0020 0x0000 0x1000 12: 0x4001 0x0008 0x308A 0x0400 0x0005 13: 0x4001 0x0008 0x300A 0x0400 0x0005 14: 0x4001 0x0008 0x300A 0x0400 0x0005 15: 0x4401 0x0008 0x3002 0x0480 0x0005 16: 0x4401 0x0010 0x3002 0x0480 0x000D 17: 0x4601 0x8410 0x3002 0x0480 0x000D 18: 0x4601 0x0410 0x3002 0x0480 0x000D 19: 0x5601 0x0490 0x3003 0x0480 0x000D 20: 0x5601 0x0490 0x3002 0x0480 0x000D 21: 0x5701 0x0491 0xB002 0x0480 0x000D 22: 0x5601 0x0491 0xB002 0x0480 0x000D 23: 0x9602 0x1491 0xB002 0x0480 0x000D 24: 0x1602 0x1491 0xB002 0x0480 0x000D 25: 0x1602 0x1491 0xB402 0x0680 0x000F 26: 0x1602 0x1491 0xB402 0x0680 0x000D 27: 0x1602 0x1491 0xB4A2 0x0680 0x100D 28: 0x1602 0x1491 0xB422 0x0680 0x100D 29: 0x1202 0x1491 0xB42A 0x0600 0x100D 30: 0x1202 0x1489 0xB42A 0x0600 0x1005 31: 0x1202 0x1489 0xB42A 0x0600 0x1005 32: 0x1206 0x1489 0xB42A 0x0600 0x1005 33: 0x1206 0x3489 0xB42A 0x0600 0x1005 34: 0x1A06 0x3489 0xB42A 0x0600 0x1005 35: 0x1A06 0x348D 0xB42A 0x0600 0x1005 36: 0x1A46 0x348D 0xB42A 0x0600 0x1005 37: 0x1A46 0x368D 0xB42A 0x0600 0x1005 38: 0x1A46 0x368D 0xB62A 0x0600 0x1005 39: 0x1A46 0x368D 0xB62A 0x0E00 0x1005 40: 0x1A46 0x368D 0xB62A 0x8E00 0x1005 41: 0x1A46 0x368D 0xB62A 0x8F00 0x1005 42: 0x1A46 0x368D 0xBE2A 0x8F00 0x1005 43: 0x1A46 0x368D 0xBE2A 0x8F02 0x1005 44: 0x1A46 0x368D 0xBE2A 0xCF02 0x1005 45: 0x1A46 0x368D 0xBE2A 0xCF06 0x1005 46: 0x1A46 0x368D 0xBE2A 0xCF07 0x1005 47: 0x1A46 0x368D 0xBE2A 0xCF47 0x1005 48: 0x1A46 0x368D 0xBE2A 0xCF67 0x1005 49: 0x1A46 0x3687 0xBE22 0xCFE7 0x100D 50: 0x1A46 0x368D 0xBE2A 0xCF67 0x1005 51: 0x1A46 0x3E85 0xBE22 0xCFE7 0x100D 52: 0x1A46 0x368D 0xBE2A 0xCF67 0x1005 53: 0x1A46 0x36C5 0xBE22 0xCFE7 0x100D 54: 0x1A46 0x368D 0xBE2A 0xCF67 0x1005 55: 0x1A46 0x7685 0xBE22 0xCFE7 0x100D 56: 0x1A46 0x368D 0xBE2A 0xCF67 0x1005 57: 0x1A56 0x3685 0xBE22 0xCFE7 0x100D 58: 0x1A46 0x368D 0xBE2A 0xCF67 0x1005 59: 0x1A4E 0x3685 0xBE22 0xCFE7 0x100D 60: 0x1A46 0x368D 0xBE2A 0xCF67 0x1005 61: 0x3A46 0x368D 0xBE22 0xCFE7 0x1005 62: 0x1A46 0x368D 0xBE2A 0xCF67 0x1005 63: 0x1E46 0x368D 0xBE22 0xCFE7 0x1005 64: 0x1A46 0x368D 0xBE2A 0xCF67 0x1005 65: 0x1A46 0x36A5 0xBE2A 0xCF67 0x100D 66: 0x1A46 0x368D 0xBE2A 0xCF67 0x1005 67: 0x1A46 0x3695 0xBE2A 0xCF67 0x100D 68: 0x1A46 0x368D 0xBE2A 0xCF67 0x1005 69: 0x1A46 0x368D 0xAE2A 0xEBE7 0x100D 70: 0x1A46 0x368D 0xBE2A 0xCF67 0x1005 71: 0x1A46 0x368D 0xAE2A 0xDBE7 0x100D 72: 0x1A46 0x368D 0xBE2A 0xCF67 0x1005 73: 0x1A46 0x368D 0xAF2A 0xCBE7 0x100D 74: 0x1A46 0x368D 0xBE2A 0xCF67 0x1005 75: 0x1A46 0x368D 0xAE2A 0xCBE7 0x900D 76: 0x1A46 0x368D 0xBE2A 0xCF67 0x1005 77: 0x1A46 0x368D 0xAE2A 0xCBEF 0x100D 78: 0x1A46 0x368D 0xBE2A 0xCF67 0x1005 79: 0x1A46 0x368D 0xAE2A 0xCBE7 0x300D 80: 0x1A46 0x368D 0xBE2A 0xCF67 0x1005 81: 0x1A46 0x368D 0xBE2A 0xCB77 0x100D 82: 0x1A46 0x368D 0xBE2A 0xCF67 0x1005 PINs used (in edge connector order) (G=ground,P=power) SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBB LETTER ABCDEFHJKLMNPRSTUVABCDEFHJKLMNPRSTUVABCDEFHJKLMNPRSTUVABCDEFHJKLMNPRSTUV SIDE 111111111111111111222222222222222222111111111111111111222222222222222222 USAGE IOIOIIOIIIIOIOIGOIPIGIIIOOOIIOIIIOIOIOIOIIIIIIIOOIIGIOPOGOIIIIIIIIIOIIOO UUT has 44 inputs UUT has 22 outputs contains 66 pins/columns 0 pins are not used contains 82 'test steps' M222 PCB REV B SCHEMATIC REV A LINC TAPE REGISTERS TERMINOLOGY- SIGNALS REFER TO VOL4 M222 SCHEMATIC. BUT... DEC USES AND-NOR GATES TO ROUTE THE ADDER A AND B INPUTS, SO... DEC RENAMED THE ADDER TO NEGATIVE LOGIC TERMS (I.E. A-N + B-N + C-N -> SUM-N, C1-N). (NOT THE 7482 DATASHEET NAMES OF A + B + C -> SUM, C1). SO, WITH ALL 'AND ENABLES' LOW, THE AND-NOR OUTPUTS = HIGH. WITH C-L HIGH, THE ADDER OUTPUT IS SUM-N=1, C1-N=1; THE INVERTED ADDER OUTPUT IS LOW (TAPE BUS). AND THERE IS NO CARRY (C1-N IS HI). THE TWO ADDERS, TWO REGISTER BITS, ETC ARE LABELED BIT 2 (EVEN, MSB) AND BIT 3 (ODD, LSB). THE ADDERS ARE REFERRED TO AS 'ADDER2' (MSB) AND 'ADDER3' (LSB). POWER PINS: AA2 +5V AT1 GROUND AC2 GROUND BA2 +5V BT1 GROUND BC2 GROUND (ALL PINS ARE USED). PINS Main menu Sat Jul 11 10:55:43 2015 test file is: tests\m222.new delay is: 0 trigger is: 1 1 read test file 2 set test delay 3 set test trigger 4 run test 5 output loading test 8 diags 9 exit UUT power is okay Sat Jul 11 10:55:45 2015 space single step O run once (one test, all steps) F run, stop on fail G go (run tests N run, stop on fail, no print S scope (run, no print) C toggle comment printout + increase speed (less delay) - decrease speed (more delay)(slower) Q quit test step 1 100000000000000000000000000000000001111100011011011010010000100001 step 2 100000000000000000000000000000000001111100100011011010010000100001 step 3 100000000000000000000000000000000001111100000011011010010000100001 step 4 100000000000000000000000000000000001111100000100011010010000100001 step 5 100000000000000000000000000000000001111100000000011010010000100001 step 6 100000000000000000000000000000000001111100000000100010010000100001 step 7 100000000000000000000000000000000001111100000000000010010000100001 step 8 100000000000000000000000000000000001111100000000000101010000100001 step 9 100000000000000000000000000000000001111100000000000001010000100001 step 10 100000000000000000000000000000000001111100000000000001011000100001 step 11 100000000000000000000000000000000001111100000000000001010000100001 step 12 100000000000000000000000000000000001111100000000000001010001100001 step 13 100000000000000000000000000000000001111100000000000001010000100001 step 14 100000000000000000000000000000000001111100000000000001010000100001 step 15 100000000000010000000000000000000000111101000000000001010000100001 step 16 100000000000010010000000000000000000110111000000000001010000100001 step 17 100000000000010010000000000000000000110111111000000001010000100001 step 18 100000000000010010000000000000000000110111011000000001010000100001 step 19 100000000000010010000000000000000000110111011111000001010000100001 step 20 100000000000010010000000000000000000110111011011000001010000100001 step 21 100000000000010010000000000000000000110111011011111001010000100001 step 22 100000000000010010000000000000000000110111011011011001010000100001 step 23 100000000000010010000000000000000000110111011011011110100000100001 step 24 100000000000010010000000000000000000110111011011011010100000100001 step 25 100000000000010010000000000000000000110111011011011010101110100001 step 26 100000000000010010000000000000000000110111011011011010100110100001 step 27 100000000000010010000000000000000000110111011011011010100111111001 step 28 100000000000010010000000000000000000110111011011011010100110111001 step 29 100000000000000010000000000000000001110110011011011010100110111001 step 30 100000000000000000000000000000000001111100011011011010100110111001 step 31 100000000000000000000000000000000001111100011011011010100110111001 step 32 100001000000000000000000000000000001111100011011011010100110111001 step 33 100001100000000000000000000000000001111100011011011010100110111001 step 34 100001100100000000000000000000000001111100011011011010100110111001 step 35 100001100110000000000000000000000001111100011011011010100110111001 step 36 100001100110100000000000000000000001111100011011011010100110111001 step 37 100001100110100100000000000000000001111100011011011010100110111001 step 38 100001100110100100010000000000000001111100011011011010100110111001 step 39 100001100110100100011000000000000001111100011011011010100110111001 step 40 100001100110100100011010000000000001111100011011011010100110111001 step 41 100001100110100100011011000000000001111100011011011010100110111001 step 42 100001100110100100011011010000000001111100011011011010100110111001 step 43 100001100110100100011011011000000001111100011011011010100110111001 step 44 100001100110100100011011011010000001111100011011011010100110111001 step 45 100001100110100100011011011011000001111100011011011010100110111001 step 46 100001100110100100011011011011010001111100011011011010100110111001 step 47 100001100110100100011011011011011001111100011011011010100110111001 step 48 100001100110100100011011011011011101111100011011011010100110111001 step 49 110001100110100100011011011011011100110111011011011010100110111001 step 50 100001100110100100011011011011011101111100011011011010100110111001 step 51 101001100110100100011011011011011100110111011011011010100110111001 step 52 100001100110100100011011011011011101111100011011011010100110111001 step 53 100101100110100100011011011011011100110111011011011010100110111001 step 54 100001100110100100011011011011011101111100011011011010100110111001 step 55 100011100110100100011011011011011100110111011011011010100110111001 step 56 100001100110100100011011011011011101111100011011011010100110111001 step 57 100001110110100100011011011011011100110111011011011010100110111001 step 58 100001100110100100011011011011011101111100011011011010100110111001 step 59 100001101110100100011011011011011100110111011011011010100110111001 step 60 100001100110100100011011011011011101111100011011011010100110111001 step 61 100001100111100100011011011011011100111101011011011010100110111001 step 62 100001100110100100011011011011011101111100011011011010100110111001 step 63 100001100110110100011011011011011100111101011011011010100110111001 step 64 100001100110100100011011011011011101111100011011011010100110111001 step 65 100001100110101100011011011011011101110110011011011010100110111001 step 66 100001100110100100011011011011011101111100011011011010100110111001 step 67 100001100110100110011011011011011101110110011011011010100110111001 step 68 100001100110100100011011011011011101111100011011011010100110111001 step 69 100001100110100101011011011011011101001111011011011010100110111001 step 70 100001100110100100011011011011011101111100011011011010100110111001 step 71 100001100110100100111011011011011101001111011011011010100110111001 step 72 100001100110100100011011011011011101111100011011011010100110111001 step 73 100001100110100100011111011011011101001111011011011010100110111001 step 74 100001100110100100011011011011011101111100011011011010100110111001 step 75 100001100110100100011011111011011101001111011011011010100110111001 step 76 100001100110100100011011011011011101111100011011011010100110111001 step 77 100001100110100100011011011111011101001111011011011010100110111001 step 78 100001100110100100011011011011011101111100011011011010100110111001 step 79 100001100110100100011011011011111101001111011011011010100110111001 step 80 100001100110100100011011011011011101111100011011011010100110111001 step 81 100001100110100100011011011011011111101110011011011010100110111001 step 82 100001100110100100011011011011011101111100011011011010100110111001 test 1: pass SLOT BAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBAABBAAAAAAAAAAAAAABBBBBBBBAB LETTER ALPSLFMDEEMCBFRSPKLEMFHRSCJLJKUHPNMBBNNVVRKRHUTDJUKANJHBTPDFSVDEVU SIDE 121212122121212121111111112212122222112222111221112112212112212212 DIRECTION IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIOOOOOOOIOOIOOIOOIOOOOIOOIIOOIIO this fail all fails was hi 111111111111111111111111111111111111111111111111111111111111111 1 rising ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ ^^^^^^^^^^^^^^^ ^^^^ ^^ falling vvvv vv v vv vvv v v v v vvvvv vvvvvvvvvvvvvv vv v was lo 00000000000000000000000000000000000000 00000000000000000000 0000 total fails 0, total passes 1 step 1 100000000000000000000000000000000001111100011011011010100110111001 step 2 100000000000000000000000000000000001111100100011011010100110111001 step 3 100000000000000000000000000000000001111100000011011010100110111001 step 4 100000000000000000000000000000000001111100000100011010100110111001 step 5 100000000000000000000000000000000001111100000000011010100110111001 step 6 100000000000000000000000000000000001111100000000100010100110111001 step 7 100000000000000000000000000000000001111100000000000010100110111001 step 8 100000000000000000000000000000000001111100000000000101010110111001 step 9 100000000000000000000000000000000001111100000000000001010110111001 step 10 100000000000000000000000000000000001111100000000000001011000111001 step 11 100000000000000000000000000000000001111100000000000001010000111001 step 12 100000000000000000000000000000000001111100000000000001010001100001 step 13 100000000000000000000000000000000001111100000000000001010000100001 step 14 100000000000000000000000000000000001111100000000000001010000100001 step 15 100000000000010000000000000000000000111101000000000001010000100001 step 16 100000000000010010000000000000000000110111000000000001010000100001 step 17 100000000000010010000000000000000000110111111000000001010000100001 step 18 100000000000010010000000000000000000110111011000000001010000100001 step 19 100000000000010010000000000000000000110111011111000001010000100001 step 20 100000000000010010000000000000000000110111011011000001010000100001 step 21 100000000000010010000000000000000000110111011011111001010000100001 step 22 100000000000010010000000000000000000110111011011011001010000100001 step 23 100000000000010010000000000000000000110111011011011110100000100001 step 24 100000000000010010000000000000000000110111011011011010100000100001 step 25 100000000000010010000000000000000000110111011011011010101110100001 step 26 100000000000010010000000000000000000110111011011011010100110100001 step 27 100000000000010010000000000000000000110111011011011010100111111001 step 28 100000000000010010000000000000000000110111011011011010100110111001 step 29 100000000000000010000000000000000001110110011011011010100110111001 step 30 100000000000000000000000000000000001111100011011011010100110111001 step 31 100000000000000000000000000000000001111100011011011010100110111001 step 32 100001000000000000000000000000000001111100011011011010100110111001 step 33 100001100000000000000000000000000001111100011011011010100110111001 step 34 100001100100000000000000000000000001111100011011011010100110111001 step 35 100001100110000000000000000000000001111100011011011010100110111001 step 36 100001100110100000000000000000000001111100011011011010100110111001 step 37 100001100110100100000000000000000001111100011011011010100110111001 step 38 100001100110100100010000000000000001111100011011011010100110111001 step 39 100001100110100100011000000000000001111100011011011010100110111001 step 40 100001100110100100011010000000000001111100011011011010100110111001 step 41 100001100110100100011011000000000001111100011011011010100110111001 step 42 100001100110100100011011010000000001111100011011011010100110111001 step 43 100001100110100100011011011000000001111100011011011010100110111001 step 44 100001100110100100011011011010000001111100011011011010100110111001 step 45 100001100110100100011011011011000001111100011011011010100110111001 step 46 100001100110100100011011011011010001111100011011011010100110111001 step 47 100001100110100100011011011011011001111100011011011010100110111001 step 48 100001100110100100011011011011011101111100011011011010100110111001 step 49 110001100110100100011011011011011100110111011011011010100110111001 step 50 100001100110100100011011011011011101111100011011011010100110111001 step 51 101001100110100100011011011011011100110111011011011010100110111001 step 52 100001100110100100011011011011011101111100011011011010100110111001 step 53 100101100110100100011011011011011100110111011011011010100110111001 step 54 100001100110100100011011011011011101111100011011011010100110111001 step 55 100011100110100100011011011011011100110111011011011010100110111001 step 56 100001100110100100011011011011011101111100011011011010100110111001 step 57 100001110110100100011011011011011100110111011011011010100110111001 step 58 100001100110100100011011011011011101111100011011011010100110111001 step 59 100001101110100100011011011011011100110111011011011010100110111001 step 60 100001100110100100011011011011011101111100011011011010100110111001 step 61 100001100111100100011011011011011100111101011011011010100110111001 step 62 100001100110100100011011011011011101111100011011011010100110111001 step 63 100001100110110100011011011011011100111101011011011010100110111001 step 64 100001100110100100011011011011011101111100011011011010100110111001 step 65 100001100110101100011011011011011101110110011011011010100110111001 step 66 100001100110100100011011011011011101111100011011011010100110111001 step 67 100001100110100110011011011011011101110110011011011010100110111001 step 68 100001100110100100011011011011011101111100011011011010100110111001 step 69 100001100110100101011011011011011101001111011011011010100110111001 step 70 100001100110100100011011011011011101111100011011011010100110111001 step 71 100001100110100100111011011011011101001111011011011010100110111001 step 72 100001100110100100011011011011011101111100011011011010100110111001 step 73 100001100110100100011111011011011101001111011011011010100110111001 step 74 100001100110100100011011011011011101111100011011011010100110111001 step 75 100001100110100100011011111011011101001111011011011010100110111001 step 76 100001100110100100011011011011011101111100011011011010100110111001 step 77 100001100110100100011011011111011101001111011011011010100110111001 step 78 100001100110100100011011011011011101111100011011011010100110111001 step 79 100001100110100100011011011011111101001111011011011010100110111001 step 80 100001100110100100011011011011011101111100011011011010100110111001 step 81 100001100110100100011011011011011111101110011011011010100110111001 step 82 100001100110100100011011011011011101111100011011011010100110111001 test 2: pass SLOT BAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBAABBAAAAAAAAAAAAAABBBBBBBBAB LETTER ALPSLFMDEEMCBFRSPKLEMFHRSCJLJKUHPNMBBNNVVRKRHUTDJUKANJHBTPDFSVDEVU SIDE 121212122121212121111111112212122222112222111221112112212112212212 DIRECTION IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIOOOOOOOIOOIOOIOOIOOOOIOOIIOOIIO this fail all fails was hi 111111111111111111111111111111111111111111111111111111111111111 1 rising ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ ^^^^^^^^^^^^^^^^^^^^ ^^ falling vvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvv vvvvvvvvvvvvvvvvvvvv vv was lo 00000000000000000000000000000000000000 00000000000000000000 0000 total fails 0, total passes 2 step 1 100000000000000000000000000000000001111100011011011010100110111001 step 2 100000000000000000000000000000000001111100100011011010100110111001 step 3 100000000000000000000000000000000001111100000011011010100110111001 step 4 100000000000000000000000000000000001111100000100011010100110111001 step 5 100000000000000000000000000000000001111100000000011010100110111001 step 6 100000000000000000000000000000000001111100000000100010100110111001 step 7 100000000000000000000000000000000001111100000000000010100110111001 step 8 100000000000000000000000000000000001111100000000000101010110111001 step 9 100000000000000000000000000000000001111100000000000001010110111001 step 10 100000000000000000000000000000000001111100000000000001011000111001 step 11 100000000000000000000000000000000001111100000000000001010000111001 step 12 100000000000000000000000000000000001111100000000000001010001100001 step 13 100000000000000000000000000000000001111100000000000001010000100001 step 14 100000000000000000000000000000000001111100000000000001010000100001 step 15 100000000000010000000000000000000000111101000000000001010000100001 step 16 100000000000010010000000000000000000110111000000000001010000100001 step 17 100000000000010010000000000000000000110111111000000001010000100001 step 18 100000000000010010000000000000000000110111011000000001010000100001 step 19 100000000000010010000000000000000000110111011111000001010000100001 step 20 100000000000010010000000000000000000110111011011000001010000100001 step 21 100000000000010010000000000000000000110111011011111001010000100001 step 22 100000000000010010000000000000000000110111011011011001010000100001 step 23 100000000000010010000000000000000000110111011011011110100000100001 step 24 100000000000010010000000000000000000110111011011011010100000100001 step 25 100000000000010010000000000000000000110111011011011010101110100001 step 26 100000000000010010000000000000000000110111011011011010100110100001 step 27 100000000000010010000000000000000000110111011011011010100111111001 step 28 100000000000010010000000000000000000110111011011011010100110111001 step 29 100000000000000010000000000000000001110110011011011010100110111001 step 30 100000000000000000000000000000000001111100011011011010100110111001 step 31 100000000000000000000000000000000001111100011011011010100110111001 step 32 100001000000000000000000000000000001111100011011011010100110111001 step 33 100001100000000000000000000000000001111100011011011010100110111001 step 34 100001100100000000000000000000000001111100011011011010100110111001 step 35 100001100110000000000000000000000001111100011011011010100110111001 step 36 100001100110100000000000000000000001111100011011011010100110111001 step 37 100001100110100100000000000000000001111100011011011010100110111001 step 38 100001100110100100010000000000000001111100011011011010100110111001 step 39 100001100110100100011000000000000001111100011011011010100110111001 step 40 100001100110100100011010000000000001111100011011011010100110111001 step 41 100001100110100100011011000000000001111100011011011010100110111001 step 42 100001100110100100011011010000000001111100011011011010100110111001 step 43 100001100110100100011011011000000001111100011011011010100110111001 step 44 100001100110100100011011011010000001111100011011011010100110111001 step 45 100001100110100100011011011011000001111100011011011010100110111001 step 46 100001100110100100011011011011010001111100011011011010100110111001 step 47 100001100110100100011011011011011001111100011011011010100110111001 step 48 100001100110100100011011011011011101111100011011011010100110111001 step 49 110001100110100100011011011011011100110111011011011010100110111001 step 50 100001100110100100011011011011011101111100011011011010100110111001 step 51 101001100110100100011011011011011100110111011011011010100110111001 step 52 100001100110100100011011011011011101111100011011011010100110111001 step 53 100101100110100100011011011011011100110111011011011010100110111001 step 54 100001100110100100011011011011011101111100011011011010100110111001 step 55 100011100110100100011011011011011100110111011011011010100110111001 step 56 100001100110100100011011011011011101111100011011011010100110111001 step 57 100001110110100100011011011011011100110111011011011010100110111001 step 58 100001100110100100011011011011011101111100011011011010100110111001 step 59 100001101110100100011011011011011100110111011011011010100110111001 step 60 100001100110100100011011011011011101111100011011011010100110111001 step 61 100001100111100100011011011011011100111101011011011010100110111001 step 62 100001100110100100011011011011011101111100011011011010100110111001 step 63 100001100110110100011011011011011100111101011011011010100110111001 step 64 100001100110100100011011011011011101111100011011011010100110111001 step 65 100001100110101100011011011011011101110110011011011010100110111001 step 66 100001100110100100011011011011011101111100011011011010100110111001 step 67 100001100110100110011011011011011101110110011011011010100110111001 step 68 100001100110100100011011011011011101111100011011011010100110111001 step 69 100001100110100101011011011011011101001111011011011010100110111001 step 70 100001100110100100011011011011011101111100011011011010100110111001 step 71 100001100110100100111011011011011101001111011011011010100110111001 step 72 100001100110100100011011011011011101111100011011011010100110111001 step 73 100001100110100100011111011011011101001111011011011010100110111001 step 74 100001100110100100011011011011011101111100011011011010100110111001 step 75 100001100110100100011011111011011101001111011011011010100110111001 step 76 100001100110100100011011011011011101111100011011011010100110111001 step 77 100001100110100100011011011111011101001111011011011010100110111001 step 78 100001100110100100011011011011011101111100011011011010100110111001 step 79 100001100110100100011011011011111101001111011011011010100110111001 step 80 100001100110100100011011011011011101111100011011011010100110111001 step 81 100001100110100100011011011011011111101110011011011010100110111001 step 82 100001100110100100011011011011011101111100011011011010100110111001 test 3: pass SLOT BAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBAABBAAAAAAAAAAAAAABBBBBBBBAB LETTER ALPSLFMDEEMCBFRSPKLEMFHRSCJLJKUHPNMBBNNVVRKRHUTDJUKANJHBTPDFSVDEVU SIDE 121212122121212121111111112212122222112222111221112112212112212212 DIRECTION IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIOOOOOOOIOOIOOIOOIOOOOIOOIIOOIIO this fail all fails was hi 111111111111111111111111111111111111111111111111111111111111111 1 rising ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ ^^^^^^^^^^^^^^^^^^^^ ^^ falling vvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvv vvvvvvvvvvvvvvvvvvvv vv was lo 00000000000000000000000000000000000000 00000000000000000000 0000 total fails 0, total passes 3 step 1 100000000000000000000000000000000001111100011011011010100110111001 step 2 100000000000000000000000000000000001111100100011011010100110111001 step 3 100000000000000000000000000000000001111100000011011010100110111001 step 4 100000000000000000000000000000000001111100000100011010100110111001 step 5 100000000000000000000000000000000001111100000000011010100110111001 step 6 100000000000000000000000000000000001111100000000100010100110111001 step 7 100000000000000000000000000000000001111100000000000010100110111001 step 8 100000000000000000000000000000000001111100000000000101010110111001 step 9 100000000000000000000000000000000001111100000000000001010110111001 step 10 100000000000000000000000000000000001111100000000000001011000111001 step 11 100000000000000000000000000000000001111100000000000001010000111001 step 12 100000000000000000000000000000000001111100000000000001010001100001 step 13 100000000000000000000000000000000001111100000000000001010000100001 step 14 100000000000000000000000000000000001111100000000000001010000100001 step 15 100000000000010000000000000000000000111101000000000001010000100001 step 16 100000000000010010000000000000000000110111000000000001010000100001 step 17 100000000000010010000000000000000000110111111000000001010000100001 step 18 100000000000010010000000000000000000110111011000000001010000100001 step 19 100000000000010010000000000000000000110111011111000001010000100001 step 20 100000000000010010000000000000000000110111011011000001010000100001 step 21 100000000000010010000000000000000000110111011011111001010000100001 step 22 100000000000010010000000000000000000110111011011011001010000100001 step 23 100000000000010010000000000000000000110111011011011110100000100001 step 24 100000000000010010000000000000000000110111011011011010100000100001 step 25 100000000000010010000000000000000000110111011011011010101110100001 step 26 100000000000010010000000000000000000110111011011011010100110100001 step 27 100000000000010010000000000000000000110111011011011010100111111001 step 28 100000000000010010000000000000000000110111011011011010100110111001 step 29 100000000000000010000000000000000001110110011011011010100110111001 step 30 100000000000000000000000000000000001111100011011011010100110111001 step 31 100000000000000000000000000000000001111100011011011010100110111001 step 32 100001000000000000000000000000000001111100011011011010100110111001 step 33 100001100000000000000000000000000001111100011011011010100110111001 step 34 100001100100000000000000000000000001111100011011011010100110111001 step 35 100001100110000000000000000000000001111100011011011010100110111001 step 36 100001100110100000000000000000000001111100011011011010100110111001 step 37 100001100110100100000000000000000001111100011011011010100110111001 step 38 100001100110100100010000000000000001111100011011011010100110111001 step 39 100001100110100100011000000000000001111100011011011010100110111001 step 40 100001100110100100011010000000000001111100011011011010100110111001 step 41 100001100110100100011011000000000001111100011011011010100110111001 step 42 100001100110100100011011010000000001111100011011011010100110111001 step 43 100001100110100100011011011000000001111100011011011010100110111001 step 44 100001100110100100011011011010000001111100011011011010100110111001 step 45 100001100110100100011011011011000001111100011011011010100110111001 step 46 100001100110100100011011011011010001111100011011011010100110111001 step 47 100001100110100100011011011011011001111100011011011010100110111001 step 48 100001100110100100011011011011011101111100011011011010100110111001 step 49 110001100110100100011011011011011100110111011011011010100110111001 step 50 100001100110100100011011011011011101111100011011011010100110111001 step 51 101001100110100100011011011011011100110111011011011010100110111001 step 52 100001100110100100011011011011011101111100011011011010100110111001 step 53 100101100110100100011011011011011100110111011011011010100110111001 step 54 100001100110100100011011011011011101111100011011011010100110111001 step 55 100011100110100100011011011011011100110111011011011010100110111001 step 56 100001100110100100011011011011011101111100011011011010100110111001 step 57 100001110110100100011011011011011100110111011011011010100110111001 step 58 100001100110100100011011011011011101111100011011011010100110111001 step 59 100001101110100100011011011011011100110111011011011010100110111001 step 60 100001100110100100011011011011011101111100011011011010100110111001 step 61 100001100111100100011011011011011100111101011011011010100110111001 step 62 100001100110100100011011011011011101111100011011011010100110111001 step 63 100001100110110100011011011011011100111101011011011010100110111001 step 64 100001100110100100011011011011011101111100011011011010100110111001 step 65 100001100110101100011011011011011101110110011011011010100110111001 step 66 100001100110100100011011011011011101111100011011011010100110111001 step 67 100001100110100110011011011011011101110110011011011010100110111001 step 68 100001100110100100011011011011011101111100011011011010100110111001 step 69 100001100110100101011011011011011101001111011011011010100110111001 step 70 100001100110100100011011011011011101111100011011011010100110111001 step 71 100001100110100100111011011011011101001111011011011010100110111001 step 72 100001100110100100011011011011011101111100011011011010100110111001 step 73 100001100110100100011111011011011101001111011011011010100110111001 step 74 100001100110100100011011011011011101111100011011011010100110111001 step 75 100001100110100100011011111011011101001111011011011010100110111001 step 76 100001100110100100011011011011011101111100011011011010100110111001 step 77 100001100110100100011011011111011101001111011011011010100110111001 step 78 100001100110100100011011011011011101111100011011011010100110111001 step 79 100001100110100100011011011011111101001111011011011010100110111001 step 80 100001100110100100011011011011011101111100011011011010100110111001 step 81 100001100110100100011011011011011111101110011011011010100110111001 step 82 100001100110100100011011011011011101111100011011011010100110111001 test 4: pass SLOT BAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBAABBAAAAAAAAAAAAAABBBBBBBBAB LETTER ALPSLFMDEEMCBFRSPKLEMFHRSCJLJKUHPNMBBNNVVRKRHUTDJUKANJHBTPDFSVDEVU SIDE 121212122121212121111111112212122222112222111221112112212112212212 DIRECTION IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIOOOOOOOIOOIOOIOOIOOOOIOOIIOOIIO this fail all fails was hi 111111111111111111111111111111111111111111111111111111111111111 1 rising ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ ^^^^^^^^^^^^^^^^^^^^ ^^ falling vvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvv vvvvvvvvvvvvvvvvvvvv vv was lo 00000000000000000000000000000000000000 00000000000000000000 0000 total fails 0, total passes 4 step 1 100000000000000000000000000000000001111100011011011010100110111001 step 2 100000000000000000000000000000000001111100100011011010100110111001 step 3 100000000000000000000000000000000001111100000011011010100110111001 step 4 100000000000000000000000000000000001111100000100011010100110111001 step 5 100000000000000000000000000000000001111100000000011010100110111001 step 6 100000000000000000000000000000000001111100000000100010100110111001 step 7 100000000000000000000000000000000001111100000000000010100110111001 step 8 100000000000000000000000000000000001111100000000000101010110111001 step 9 100000000000000000000000000000000001111100000000000001010110111001 step 10 100000000000000000000000000000000001111100000000000001011000111001 step 11 100000000000000000000000000000000001111100000000000001010000111001 step 12 100000000000000000000000000000000001111100000000000001010001100001 step 13 100000000000000000000000000000000001111100000000000001010000100001 step 14 100000000000000000000000000000000001111100000000000001010000100001 step 15 100000000000010000000000000000000000111101000000000001010000100001 step 16 100000000000010010000000000000000000110111000000000001010000100001 step 17 100000000000010010000000000000000000110111111000000001010000100001 step 18 100000000000010010000000000000000000110111011000000001010000100001 step 19 100000000000010010000000000000000000110111011111000001010000100001 step 20 100000000000010010000000000000000000110111011011000001010000100001 step 21 100000000000010010000000000000000000110111011011111001010000100001 step 22 100000000000010010000000000000000000110111011011011001010000100001 step 23 100000000000010010000000000000000000110111011011011110100000100001 step 24 100000000000010010000000000000000000110111011011011010100000100001 step 25 100000000000010010000000000000000000110111011011011010101110100001 step 26 100000000000010010000000000000000000110111011011011010100110100001 step 27 100000000000010010000000000000000000110111011011011010100111111001 step 28 100000000000010010000000000000000000110111011011011010100110111001 step 29 100000000000000010000000000000000001110110011011011010100110111001 step 30 100000000000000000000000000000000001111100011011011010100110111001 step 31 100000000000000000000000000000000001111100011011011010100110111001 step 32 100001000000000000000000000000000001111100011011011010100110111001 step 33 100001100000000000000000000000000001111100011011011010100110111001 step 34 100001100100000000000000000000000001111100011011011010100110111001 step 35 100001100110000000000000000000000001111100011011011010100110111001 step 36 100001100110100000000000000000000001111100011011011010100110111001 step 37 100001100110100100000000000000000001111100011011011010100110111001 step 38 100001100110100100010000000000000001111100011011011010100110111001 step 39 100001100110100100011000000000000001111100011011011010100110111001 step 40 100001100110100100011010000000000001111100011011011010100110111001 step 41 100001100110100100011011000000000001111100011011011010100110111001 step 42 100001100110100100011011010000000001111100011011011010100110111001 step 43 100001100110100100011011011000000001111100011011011010100110111001 step 44 100001100110100100011011011010000001111100011011011010100110111001 step 45 100001100110100100011011011011000001111100011011011010100110111001 step 46 100001100110100100011011011011010001111100011011011010100110111001 step 47 100001100110100100011011011011011001111100011011011010100110111001 step 48 100001100110100100011011011011011101111100011011011010100110111001 step 49 110001100110100100011011011011011100110111011011011010100110111001 step 50 100001100110100100011011011011011101111100011011011010100110111001 step 51 101001100110100100011011011011011100110111011011011010100110111001 step 52 100001100110100100011011011011011101111100011011011010100110111001 step 53 100101100110100100011011011011011100110111011011011010100110111001 step 54 100001100110100100011011011011011101111100011011011010100110111001 step 55 100011100110100100011011011011011100110111011011011010100110111001 step 56 100001100110100100011011011011011101111100011011011010100110111001 step 57 100001110110100100011011011011011100110111011011011010100110111001 step 58 100001100110100100011011011011011101111100011011011010100110111001 step 59 100001101110100100011011011011011100110111011011011010100110111001 step 60 100001100110100100011011011011011101111100011011011010100110111001 step 61 100001100111100100011011011011011100111101011011011010100110111001 step 62 100001100110100100011011011011011101111100011011011010100110111001 step 63 100001100110110100011011011011011100111101011011011010100110111001 step 64 100001100110100100011011011011011101111100011011011010100110111001 step 65 100001100110101100011011011011011101110110011011011010100110111001 step 66 100001100110100100011011011011011101111100011011011010100110111001 step 67 100001100110100110011011011011011101110110011011011010100110111001 step 68 100001100110100100011011011011011101111100011011011010100110111001 step 69 100001100110100101011011011011011101001111011011011010100110111001 step 70 100001100110100100011011011011011101111100011011011010100110111001 step 71 100001100110100100111011011011011101001111011011011010100110111001 step 72 100001100110100100011011011011011101111100011011011010100110111001 step 73 100001100110100100011111011011011101001111011011011010100110111001 step 74 100001100110100100011011011011011101111100011011011010100110111001 step 75 100001100110100100011011111011011101001111011011011010100110111001 step 76 100001100110100100011011011011011101111100011011011010100110111001 step 77 100001100110100100011011011111011101001111011011011010100110111001 step 78 100001100110100100011011011011011101111100011011011010100110111001 step 79 100001100110100100011011011011111101001111011011011010100110111001 step 80 100001100110100100011011011011011101111100011011011010100110111001 step 81 100001100110100100011011011011011111101110011011011010100110111001 step 82 100001100110100100011011011011011101111100011011011010100110111001 test 5: pass SLOT BAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBAABBAAAAAAAAAAAAAABBBBBBBBAB LETTER ALPSLFMDEEMCBFRSPKLEMFHRSCJLJKUHPNMBBNNVVRKRHUTDJUKANJHBTPDFSVDEVU SIDE 121212122121212121111111112212122222112222111221112112212112212212 DIRECTION IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIOOOOOOOIOOIOOIOOIOOOOIOOIIOOIIO this fail all fails was hi 111111111111111111111111111111111111111111111111111111111111111 1 rising ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ ^^^^^^^^^^^^^^^^^^^^ ^^ falling vvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvv vvvvvvvvvvvvvvvvvvvv vv was lo 00000000000000000000000000000000000000 00000000000000000000 0000 total fails 0, total passes 5 step 1 100000000000000000000000000000000001111100011011011010100110111001 step 2 100000000000000000000000000000000001111100100011011010100110111001 step 3 100000000000000000000000000000000001111100000011011010100110111001 step 4 100000000000000000000000000000000001111100000100011010100110111001 step 5 100000000000000000000000000000000001111100000000011010100110111001 step 6 100000000000000000000000000000000001111100000000100010100110111001 step 7 100000000000000000000000000000000001111100000000000010100110111001 step 8 100000000000000000000000000000000001111100000000000101010110111001 step 9 100000000000000000000000000000000001111100000000000001010110111001 step 10 100000000000000000000000000000000001111100000000000001011000111001 step 11 100000000000000000000000000000000001111100000000000001010000111001 step 12 100000000000000000000000000000000001111100000000000001010001100001 step 13 100000000000000000000000000000000001111100000000000001010000100001 step 14 100000000000000000000000000000000001111100000000000001010000100001 step 15 100000000000010000000000000000000000111101000000000001010000100001 step 16 100000000000010010000000000000000000110111000000000001010000100001 step 17 100000000000010010000000000000000000110111111000000001010000100001 step 18 100000000000010010000000000000000000110111011000000001010000100001 step 19 100000000000010010000000000000000000110111011111000001010000100001 step 20 100000000000010010000000000000000000110111011011000001010000100001 step 21 100000000000010010000000000000000000110111011011111001010000100001 step 22 100000000000010010000000000000000000110111011011011001010000100001 step 23 100000000000010010000000000000000000110111011011011110100000100001 step 24 100000000000010010000000000000000000110111011011011010100000100001 step 25 100000000000010010000000000000000000110111011011011010101110100001 step 26 100000000000010010000000000000000000110111011011011010100110100001 step 27 100000000000010010000000000000000000110111011011011010100111111001 step 28 100000000000010010000000000000000000110111011011011010100110111001 step 29 100000000000000010000000000000000001110110011011011010100110111001 step 30 100000000000000000000000000000000001111100011011011010100110111001 step 31 100000000000000000000000000000000001111100011011011010100110111001 step 32 100001000000000000000000000000000001111100011011011010100110111001 step 33 100001100000000000000000000000000001111100011011011010100110111001 step 34 100001100100000000000000000000000001111100011011011010100110111001 step 35 100001100110000000000000000000000001111100011011011010100110111001 step 36 100001100110100000000000000000000001111100011011011010100110111001 step 37 100001100110100100000000000000000001111100011011011010100110111001 step 38 100001100110100100010000000000000001111100011011011010100110111001 step 39 100001100110100100011000000000000001111100011011011010100110111001 step 40 100001100110100100011010000000000001111100011011011010100110111001 step 41 100001100110100100011011000000000001111100011011011010100110111001 step 42 100001100110100100011011010000000001111100011011011010100110111001 step 43 100001100110100100011011011000000001111100011011011010100110111001 step 44 100001100110100100011011011010000001111100011011011010100110111001 step 45 100001100110100100011011011011000001111100011011011010100110111001 step 46 100001100110100100011011011011010001111100011011011010100110111001 step 47 100001100110100100011011011011011001111100011011011010100110111001 step 48 100001100110100100011011011011011101111100011011011010100110111001 step 49 110001100110100100011011011011011100110111011011011010100110111001 step 50 100001100110100100011011011011011101111100011011011010100110111001 step 51 101001100110100100011011011011011100110111011011011010100110111001 step 52 100001100110100100011011011011011101111100011011011010100110111001 step 53 100101100110100100011011011011011100110111011011011010100110111001 step 54 100001100110100100011011011011011101111100011011011010100110111001 step 55 100011100110100100011011011011011100110111011011011010100110111001 step 56 100001100110100100011011011011011101111100011011011010100110111001 step 57 100001110110100100011011011011011100110111011011011010100110111001 step 58 100001100110100100011011011011011101111100011011011010100110111001 step 59 100001101110100100011011011011011100110111011011011010100110111001 step 60 100001100110100100011011011011011101111100011011011010100110111001 step 61 100001100111100100011011011011011100111101011011011010100110111001 step 62 100001100110100100011011011011011101111100011011011010100110111001 step 63 100001100110110100011011011011011100111101011011011010100110111001 step 64 100001100110100100011011011011011101111100011011011010100110111001 step 65 100001100110101100011011011011011101110110011011011010100110111001 step 66 100001100110100100011011011011011101111100011011011010100110111001 step 67 100001100110100110011011011011011101110110011011011010100110111001 step 68 100001100110100100011011011011011101111100011011011010100110111001 step 69 100001100110100101011011011011011101001111011011011010100110111001 step 70 100001100110100100011011011011011101111100011011011010100110111001 step 71 100001100110100100111011011011011101001111011011011010100110111001 step 72 100001100110100100011011011011011101111100011011011010100110111001 step 73 100001100110100100011111011011011101001111011011011010100110111001 step 74 100001100110100100011011011011011101111100011011011010100110111001 step 75 100001100110100100011011111011011101001111011011011010100110111001 step 76 100001100110100100011011011011011101111100011011011010100110111001 step 77 100001100110100100011011011111011101001111011011011010100110111001 step 78 100001100110100100011011011011011101111100011011011010100110111001 step 79 100001100110100100011011011011111101001111011011011010100110111001 step 80 100001100110100100011011011011011101111100011011011010100110111001 step 81 100001100110100100011011011011011111101110011011011010100110111001 step 82 100001100110100100011011011011011101111100011011011010100110111001 test 6: pass SLOT BAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBAABBAAAAAAAAAAAAAABBBBBBBBAB LETTER ALPSLFMDEEMCBFRSPKLEMFHRSCJLJKUHPNMBBNNVVRKRHUTDJUKANJHBTPDFSVDEVU SIDE 121212122121212121111111112212122222112222111221112112212112212212 DIRECTION IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIOOOOOOOIOOIOOIOOIOOOOIOOIIOOIIO this fail all fails was hi 111111111111111111111111111111111111111111111111111111111111111 1 rising ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ ^^^^^^^^^^^^^^^^^^^^ ^^ falling vvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvv vvvvvvvvvvvvvvvvvvvv vv was lo 00000000000000000000000000000000000000 00000000000000000000 0000 total fails 0, total passes 6 step 1 100000000000000000000000000000000001111100011011011010100110111001 step 2 100000000000000000000000000000000001111100100011011010100110111001 step 3 100000000000000000000000000000000001111100000011011010100110111001 step 4 100000000000000000000000000000000001111100000100011010100110111001 step 5 100000000000000000000000000000000001111100000000011010100110111001 step 6 100000000000000000000000000000000001111100000000100010100110111001 step 7 100000000000000000000000000000000001111100000000000010100110111001 step 8 100000000000000000000000000000000001111100000000000101010110111001 step 9 100000000000000000000000000000000001111100000000000001010110111001 step 10 100000000000000000000000000000000001111100000000000001011000111001 step 11 100000000000000000000000000000000001111100000000000001010000111001 step 12 100000000000000000000000000000000001111100000000000001010001100001 step 13 100000000000000000000000000000000001111100000000000001010000100001 step 14 100000000000000000000000000000000001111100000000000001010000100001 step 15 100000000000010000000000000000000000111101000000000001010000100001 step 16 100000000000010010000000000000000000110111000000000001010000100001 step 17 100000000000010010000000000000000000110111111000000001010000100001 step 18 100000000000010010000000000000000000110111011000000001010000100001 step 19 100000000000010010000000000000000000110111011111000001010000100001 step 20 100000000000010010000000000000000000110111011011000001010000100001 step 21 100000000000010010000000000000000000110111011011111001010000100001 step 22 100000000000010010000000000000000000110111011011011001010000100001 step 23 100000000000010010000000000000000000110111011011011110100000100001 step 24 100000000000010010000000000000000000110111011011011010100000100001 step 25 100000000000010010000000000000000000110111011011011010101110100001 step 26 100000000000010010000000000000000000110111011011011010100110100001 step 27 100000000000010010000000000000000000110111011011011010100111111001 step 28 100000000000010010000000000000000000110111011011011010100110111001 step 29 100000000000000010000000000000000001110110011011011010100110111001 step 30 100000000000000000000000000000000001111100011011011010100110111001 step 31 100000000000000000000000000000000001111100011011011010100110111001 step 32 100001000000000000000000000000000001111100011011011010100110111001 step 33 100001100000000000000000000000000001111100011011011010100110111001 step 34 100001100100000000000000000000000001111100011011011010100110111001 step 35 100001100110000000000000000000000001111100011011011010100110111001 step 36 100001100110100000000000000000000001111100011011011010100110111001 step 37 100001100110100100000000000000000001111100011011011010100110111001 step 38 100001100110100100010000000000000001111100011011011010100110111001 step 39 100001100110100100011000000000000001111100011011011010100110111001 step 40 100001100110100100011010000000000001111100011011011010100110111001 step 41 100001100110100100011011000000000001111100011011011010100110111001 step 42 100001100110100100011011010000000001111100011011011010100110111001 step 43 100001100110100100011011011000000001111100011011011010100110111001 step 44 100001100110100100011011011010000001111100011011011010100110111001 step 45 100001100110100100011011011011000001111100011011011010100110111001 step 46 100001100110100100011011011011010001111100011011011010100110111001 step 47 100001100110100100011011011011011001111100011011011010100110111001 step 48 100001100110100100011011011011011101111100011011011010100110111001 step 49 110001100110100100011011011011011100110111011011011010100110111001 step 50 100001100110100100011011011011011101111100011011011010100110111001 step 51 101001100110100100011011011011011100110111011011011010100110111001 step 52 100001100110100100011011011011011101111100011011011010100110111001 step 53 100101100110100100011011011011011100110111011011011010100110111001 step 54 100001100110100100011011011011011101111100011011011010100110111001 step 55 100011100110100100011011011011011100110111011011011010100110111001 step 56 100001100110100100011011011011011101111100011011011010100110111001 step 57 100001110110100100011011011011011100110111011011011010100110111001 step 58 100001100110100100011011011011011101111100011011011010100110111001 step 59 100001101110100100011011011011011100110111011011011010100110111001 step 60 100001100110100100011011011011011101111100011011011010100110111001 step 61 100001100111100100011011011011011100111101011011011010100110111001 step 62 100001100110100100011011011011011101111100011011011010100110111001 step 63 100001100110110100011011011011011100111101011011011010100110111001 step 64 100001100110100100011011011011011101111100011011011010100110111001 step 65 100001100110101100011011011011011101110110011011011010100110111001 step 66 100001100110100100011011011011011101111100011011011010100110111001 step 67 100001100110100110011011011011011101110110011011011010100110111001 step 68 100001100110100100011011011011011101111100011011011010100110111001 step 69 100001100110100101011011011011011101001111011011011010100110111001 step 70 100001100110100100011011011011011101111100011011011010100110111001 step 71 100001100110100100111011011011011101001111011011011010100110111001 step 72 100001100110100100011011011011011101111100011011011010100110111001 step 73 100001100110100100011111011011011101001111011011011010100110111001 step 74 100001100110100100011011011011011101111100011011011010100110111001 step 75 100001100110100100011011111011011101001111011011011010100110111001 step 76 100001100110100100011011011011011101111100011011011010100110111001 step 77 100001100110100100011011011111011101001111011011011010100110111001 step 78 100001100110100100011011011011011101111100011011011010100110111001 step 79 100001100110100100011011011011111101001111011011011010100110111001 step 80 100001100110100100011011011011011101111100011011011010100110111001 step 81 100001100110100100011011011011011111101110011011011010100110111001 step 82 100001100110100100011011011011011101111100011011011010100110111001 test 7: pass SLOT BAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBAABBAAAAAAAAAAAAAABBBBBBBBAB LETTER ALPSLFMDEEMCBFRSPKLEMFHRSCJLJKUHPNMBBNNVVRKRHUTDJUKANJHBTPDFSVDEVU SIDE 121212122121212121111111112212122222112222111221112112212112212212 DIRECTION IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIOOOOOOOIOOIOOIOOIOOOOIOOIIOOIIO this fail all fails was hi 111111111111111111111111111111111111111111111111111111111111111 1 rising ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ ^^^^^^^^^^^^^^^^^^^^ ^^ falling vvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvv vvvvvvvvvvvvvvvvvvvv vv was lo 00000000000000000000000000000000000000 00000000000000000000 0000 total fails 0, total passes 7 step 1 100000000000000000000000000000000001111100011011011010100110111001 step 2 100000000000000000000000000000000001111100100011011010100110111001 step 3 100000000000000000000000000000000001111100000011011010100110111001 step 4 100000000000000000000000000000000001111100000100011010100110111001 step 5 100000000000000000000000000000000001111100000000011010100110111001 step 6 100000000000000000000000000000000001111100000000100010100110111001 step 7 100000000000000000000000000000000001111100000000000010100110111001 step 8 100000000000000000000000000000000001111100000000000101010110111001 step 9 100000000000000000000000000000000001111100000000000001010110111001 step 10 100000000000000000000000000000000001111100000000000001011000111001 step 11 100000000000000000000000000000000001111100000000000001010000111001 step 12 100000000000000000000000000000000001111100000000000001010001100001 step 13 100000000000000000000000000000000001111100000000000001010000100001 step 14 100000000000000000000000000000000001111100000000000001010000100001 step 15 100000000000010000000000000000000000111101000000000001010000100001 step 16 100000000000010010000000000000000000110111000000000001010000100001 step 17 100000000000010010000000000000000000110111111000000001010000100001 step 18 100000000000010010000000000000000000110111011000000001010000100001 step 19 100000000000010010000000000000000000110111011111000001010000100001 step 20 100000000000010010000000000000000000110111011011000001010000100001 step 21 100000000000010010000000000000000000110111011011111001010000100001 step 22 100000000000010010000000000000000000110111011011011001010000100001 step 23 100000000000010010000000000000000000110111011011011110100000100001 step 24 100000000000010010000000000000000000110111011011011010100000100001 step 25 100000000000010010000000000000000000110111011011011010101110100001 step 26 100000000000010010000000000000000000110111011011011010100110100001 step 27 100000000000010010000000000000000000110111011011011010100111111001 step 28 100000000000010010000000000000000000110111011011011010100110111001 step 29 100000000000000010000000000000000001110110011011011010100110111001 step 30 100000000000000000000000000000000001111100011011011010100110111001 step 31 100000000000000000000000000000000001111100011011011010100110111001 step 32 100001000000000000000000000000000001111100011011011010100110111001 step 33 100001100000000000000000000000000001111100011011011010100110111001 step 34 100001100100000000000000000000000001111100011011011010100110111001 step 35 100001100110000000000000000000000001111100011011011010100110111001 step 36 100001100110100000000000000000000001111100011011011010100110111001 step 37 100001100110100100000000000000000001111100011011011010100110111001 step 38 100001100110100100010000000000000001111100011011011010100110111001 step 39 100001100110100100011000000000000001111100011011011010100110111001 step 40 100001100110100100011010000000000001111100011011011010100110111001 step 41 100001100110100100011011000000000001111100011011011010100110111001 step 42 100001100110100100011011010000000001111100011011011010100110111001 step 43 100001100110100100011011011000000001111100011011011010100110111001 step 44 100001100110100100011011011010000001111100011011011010100110111001 step 45 100001100110100100011011011011000001111100011011011010100110111001 step 46 100001100110100100011011011011010001111100011011011010100110111001 step 47 100001100110100100011011011011011001111100011011011010100110111001 step 48 100001100110100100011011011011011101111100011011011010100110111001 step 49 110001100110100100011011011011011100110111011011011010100110111001 step 50 100001100110100100011011011011011101111100011011011010100110111001 step 51 101001100110100100011011011011011100110111011011011010100110111001 step 52 100001100110100100011011011011011101111100011011011010100110111001 step 53 100101100110100100011011011011011100110111011011011010100110111001 step 54 100001100110100100011011011011011101111100011011011010100110111001 step 55 100011100110100100011011011011011100110111011011011010100110111001 step 56 100001100110100100011011011011011101111100011011011010100110111001 step 57 100001110110100100011011011011011100110111011011011010100110111001 step 58 100001100110100100011011011011011101111100011011011010100110111001 step 59 100001101110100100011011011011011100110111011011011010100110111001 step 60 100001100110100100011011011011011101111100011011011010100110111001 step 61 100001100111100100011011011011011100111101011011011010100110111001 step 62 100001100110100100011011011011011101111100011011011010100110111001 step 63 100001100110110100011011011011011100111101011011011010100110111001 step 64 100001100110100100011011011011011101111100011011011010100110111001 step 65 100001100110101100011011011011011101110110011011011010100110111001 step 66 100001100110100100011011011011011101111100011011011010100110111001 step 67 100001100110100110011011011011011101110110011011011010100110111001 step 68 100001100110100100011011011011011101111100011011011010100110111001 step 69 100001100110100101011011011011011101001111011011011010100110111001 step 70 100001100110100100011011011011011101111100011011011010100110111001 step 71 100001100110100100111011011011011101001111011011011010100110111001 step 72 100001100110100100011011011011011101111100011011011010100110111001 step 73 100001100110100100011111011011011101001111011011011010100110111001 step 74 100001100110100100011011011011011101111100011011011010100110111001 step 75 100001100110100100011011111011011101001111011011011010100110111001 step 76 100001100110100100011011011011011101111100011011011010100110111001 step 77 100001100110100100011011011111011101001111011011011010100110111001 step 78 100001100110100100011011011011011101111100011011011010100110111001 step 79 100001100110100100011011011011111101001111011011011010100110111001 step 80 100001100110100100011011011011011101111100011011011010100110111001 step 81 100001100110100100011011011011011111101110011011011010100110111001 step 82 100001100110100100011011011011011101111100011011011010100110111001 test 8: pass SLOT BAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBAABBAAAAAAAAAAAAAABBBBBBBBAB LETTER ALPSLFMDEEMCBFRSPKLEMFHRSCJLJKUHPNMBBNNVVRKRHUTDJUKANJHBTPDFSVDEVU SIDE 121212122121212121111111112212122222112222111221112112212112212212 DIRECTION IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIOOOOOOOIOOIOOIOOIOOOOIOOIIOOIIO this fail all fails was hi 111111111111111111111111111111111111111111111111111111111111111 1 rising ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ ^^^^^^^^^^^^^^^^^^^^ ^^ falling vvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvv vvvvvvvvvvvvvvvvvvvv vv was lo 00000000000000000000000000000000000000 00000000000000000000 0000 total fails 0, total passes 8 step 1 100000000000000000000000000000000001111100011011011010100110111001 step 2 100000000000000000000000000000000001111100100011011010100110111001 step 3 100000000000000000000000000000000001111100000011011010100110111001 step 4 100000000000000000000000000000000001111100000100011010100110111001 step 5 100000000000000000000000000000000001111100000000011010100110111001 step 6 100000000000000000000000000000000001111100000000100010100110111001 step 7 100000000000000000000000000000000001111100000000000010100110111001 step 8 100000000000000000000000000000000001111100000000000101010110111001 step 9 100000000000000000000000000000000001111100000000000001010110111001 step 10 100000000000000000000000000000000001111100000000000001011000111001 step 11 100000000000000000000000000000000001111100000000000001010000111001 step 12 100000000000000000000000000000000001111100000000000001010001100001 step 13 100000000000000000000000000000000001111100000000000001010000100001 step 14 100000000000000000000000000000000001111100000000000001010000100001 step 15 100000000000010000000000000000000000111101000000000001010000100001 step 16 100000000000010010000000000000000000110111000000000001010000100001 step 17 100000000000010010000000000000000000110111111000000001010000100001 step 18 100000000000010010000000000000000000110111011000000001010000100001 step 19 100000000000010010000000000000000000110111011111000001010000100001 step 20 100000000000010010000000000000000000110111011011000001010000100001 step 21 100000000000010010000000000000000000110111011011111001010000100001 space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C toggle comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit scope (run, no print) ppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppp pppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppp space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C toggle comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit step 79 100001100110100100011011011011111101001111011011011010100110111001 step 80 100001100110100100011011011011011101111100011011011010100110111001 step 81 100001100110100100011011011011011111101110011011011010100110111001 step 82 100001100110100100011011011011011101111100011011011010100110111001 test 162: pass SLOT BAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBAABBAAAAAAAAAAAAAABBBBBBBBAB LETTER ALPSLFMDEEMCBFRSPKLEMFHRSCJLJKUHPNMBBNNVVRKRHUTDJUKANJHBTPDFSVDEVU SIDE 121212122121212121111111112212122222112222111221112112212112212212 DIRECTION IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIOOOOOOOIOOIOOIOOIOOOOIOOIIOOIIO this fail all fails was hi 111111111111111111111111111111111111111111111111111111111111111 1 rising ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ ^^^^^^^^^^^^^^^^^^^^ ^^ falling vvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvv vvvvvvvvvvvvvvvvvvvv vv was lo 00000000000000000000000000000000000000 00000000000000000000 0000 total fails 0, total passes 162 space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C toggle comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit step 1 100000000000000000000000000000000001111100011011011010100110111001 step 2 100000000000000000000000000000000001111100100011011010100110111001 step 3 100000000000000000000000000000000001111100000011011010100110111001 step 4 100000000000000000000000000000000001111100000100011010100110111001 step 5 100000000000000000000000000000000001111100000000011010100110111001 step 6 100000000000000000000000000000000001111100000000100010100110111001 step 7 100000000000000000000000000000000001111100000000000010100110111001 step 8 100000000000000000000000000000000001111100000000000101010110111001 step 9 100000000000000000000000000000000001111100000000000001010110111001 step 10 100000000000000000000000000000000001111100000000000001011000111001 step 11 100000000000000000000000000000000001111100000000000001010000111001 step 12 100000000000000000000000000000000001111100000000000001010001100001 step 13 100000000000000000000000000000000001111100000000000001010000100001 step 14 100000000000000000000000000000000001111100000000000001010000100001 step 15 100000000000010000000000000000000000111101000000000001010000100001 step 16 100000000000010010000000000000000000110111000000000001010000100001 step 17 100000000000010010000000000000000000110111111000000001010000100001 step 18 100000000000010010000000000000000000110111011000000001010000100001 step 19 100000000000010010000000000000000000110111011111000001010000100001 step 20 100000000000010010000000000000000000110111011011000001010000100001 step 21 100000000000010010000000000000000000110111011011111001010000100001 step 22 100000000000010010000000000000000000110111011011011001010000100001 step 23 100000000000010010000000000000000000110111011011011110100000100001 step 24 100000000000010010000000000000000000110111011011011010100000100001 step 25 100000000000010010000000000000000000110111011011011010101110100001 step 26 100000000000010010000000000000000000110111011011011010100110100001 step 27 100000000000010010000000000000000000110111011011011010100111111001 step 28 100000000000010010000000000000000000110111011011011010100110111001 step 29 100000000000000010000000000000000001110110011011011010100110111001 step 30 100000000000000000000000000000000001111100011011011010100110111001 step 31 100000000000000000000000000000000001111100011011011010100110111001 step 32 100001000000000000000000000000000001111100011011011010100110111001 step 33 100001100000000000000000000000000001111100011011011010100110111001 step 34 100001100100000000000000000000000001111100011011011010100110111001 step 35 100001100110000000000000000000000001111100011011011010100110111001 step 36 100001100110100000000000000000000001111100011011011010100110111001 step 37 100001100110100100000000000000000001111100011011011010100110111001 step 38 100001100110100100010000000000000001111100011011011010100110111001 step 39 100001100110100100011000000000000001111100011011011010100110111001 step 40 100001100110100100011010000000000001111100011011011010100110111001 step 41 100001100110100100011011000000000001111100011011011010100110111001 step 42 100001100110100100011011010000000001111100011011011010100110111001 step 43 100001100110100100011011011000000001111100011011011010100110111001 step 44 100001100110100100011011011010000001111100011011011010100110111001 step 45 100001100110100100011011011011000001111100011011011010100110111001 step 46 100001100110100100011011011011010001111100011011011010100110111001 step 47 100001100110100100011011011011011001111100011011011010100110111001 step 48 100001100110100100011011011011011101111100011011011010100110111001 step 49 110001100110100100011011011011011100110111011011011010100110111001 step 50 100001100110100100011011011011011101111100011011011010100110111001 step 51 101001100110100100011011011011011100110111011011011010100110111001 step 52 100001100110100100011011011011011101111100011011011010100110111001 step 53 100101100110100100011011011011011100110111011011011010100110111001 step 54 100001100110100100011011011011011101111100011011011010100110111001 step 55 100011100110100100011011011011011100110111011011011010100110111001 step 56 100001100110100100011011011011011101111100011011011010100110111001 step 57 100001110110100100011011011011011100110111011011011010100110111001 step 58 100001100110100100011011011011011101111100011011011010100110111001 step 59 100001101110100100011011011011011100110111011011011010100110111001 step 60 100001100110100100011011011011011101111100011011011010100110111001 step 61 100001100111100100011011011011011100111101011011011010100110111001 step 62 100001100110100100011011011011011101111100011011011010100110111001 step 63 100001100110110100011011011011011100111101011011011010100110111001 step 64 100001100110100100011011011011011101111100011011011010100110111001 step 65 100001100110101100011011011011011101110110011011011010100110111001 step 66 100001100110100100011011011011011101111100011011011010100110111001 step 67 100001100110100110011011011011011101110110011011011010100110111001 step 68 100001100110100100011011011011011101111100011011011010100110111001 step 69 100001100110100101011011011011011101001111011011011010100110111001 step 70 100001100110100100011011011011011101111100011011011010100110111001 step 71 100001100110100100111011011011011101001111011011011010100110111001 step 72 100001100110100100011011011011011101111100011011011010100110111001 step 73 100001100110100100011111011011011101001111011011011010100110111001 step 74 100001100110100100011011011011011101111100011011011010100110111001 step 75 100001100110100100011011111011011101001111011011011010100110111001 step 76 100001100110100100011011011011011101111100011011011010100110111001 step 77 100001100110100100011011011111011101001111011011011010100110111001 step 78 100001100110100100011011011011011101111100011011011010100110111001 step 79 100001100110100100011011011011111101001111011011011010100110111001 step 80 100001100110100100011011011011011101111100011011011010100110111001 step 81 100001100110100100011011011011011111101110011011011010100110111001 step 82 100001100110100100011011011011011101111100011011011010100110111001 test 163: pass SLOT BAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBAABBAAAAAAAAAAAAAABBBBBBBBAB LETTER ALPSLFMDEEMCBFRSPKLEMFHRSCJLJKUHPNMBBNNVVRKRHUTDJUKANJHBTPDFSVDEVU SIDE 121212122121212121111111112212122222112222111221112112212112212212 DIRECTION IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIOOOOOOOIOOIOOIOOIOOOOIOOIIOOIIO this fail all fails was hi 111111111111111111111111111111111111111111111111111111111111111 1 rising ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ ^^^^^^^^^^^^^^^^^^^^ ^^ falling vvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvv vvvvvvvvvvvvvvvvvvvv vv was lo 00000000000000000000000000000000000000 00000000000000000000 0000 total fails 0, total passes 163 space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C toggle comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit step 1 100000000000000000000000000000000001111100011011011010100110111001 step 2 100000000000000000000000000000000001111100100011011010100110111001 step 3 100000000000000000000000000000000001111100000011011010100110111001 step 4 100000000000000000000000000000000001111100000100011010100110111001 step 5 100000000000000000000000000000000001111100000000011010100110111001 step 6 100000000000000000000000000000000001111100000000100010100110111001 step 7 100000000000000000000000000000000001111100000000000010100110111001 step 8 100000000000000000000000000000000001111100000000000101010110111001 step 9 100000000000000000000000000000000001111100000000000001010110111001 step 10 100000000000000000000000000000000001111100000000000001011000111001 step 11 100000000000000000000000000000000001111100000000000001010000111001 step 12 100000000000000000000000000000000001111100000000000001010001100001 step 13 100000000000000000000000000000000001111100000000000001010000100001 step 14 100000000000000000000000000000000001111100000000000001010000100001 step 15 100000000000010000000000000000000000111101000000000001010000100001 step 16 100000000000010010000000000000000000110111000000000001010000100001 step 17 100000000000010010000000000000000000110111111000000001010000100001 step 18 100000000000010010000000000000000000110111011000000001010000100001 step 19 100000000000010010000000000000000000110111011111000001010000100001 step 20 100000000000010010000000000000000000110111011011000001010000100001 step 21 100000000000010010000000000000000000110111011011111001010000100001 step 22 100000000000010010000000000000000000110111011011011001010000100001 step 23 100000000000010010000000000000000000110111011011011110100000100001 step 24 100000000000010010000000000000000000110111011011011010100000100001 step 25 100000000000010010000000000000000000110111011011011010101110100001 step 26 100000000000010010000000000000000000110111011011011010100110100001 step 27 100000000000010010000000000000000000110111011011011010100111111001 step 28 100000000000010010000000000000000000110111011011011010100110111001 step 29 100000000000000010000000000000000001110110011011011010100110111001 step 30 100000000000000000000000000000000001111100011011011010100110111001 step 31 100000000000000000000000000000000001111100011011011010100110111001 step 32 100001000000000000000000000000000001111100011011011010100110111001 step 33 100001100000000000000000000000000001111100011011011010100110111001 step 34 100001100100000000000000000000000001111100011011011010100110111001 step 35 100001100110000000000000000000000001111100011011011010100110111001 step 36 100001100110100000000000000000000001111100011011011010100110111001 step 37 100001100110100100000000000000000001111100011011011010100110111001 step 38 100001100110100100010000000000000001111100011011011010100110111001 step 39 100001100110100100011000000000000001111100011011011010100110111001 step 40 100001100110100100011010000000000001111100011011011010100110111001 step 41 100001100110100100011011000000000001111100011011011010100110111001 step 42 100001100110100100011011010000000001111100011011011010100110111001 step 43 100001100110100100011011011000000001111100011011011010100110111001 step 44 100001100110100100011011011010000001111100011011011010100110111001 step 45 100001100110100100011011011011000001111100011011011010100110111001 step 46 100001100110100100011011011011010001111100011011011010100110111001 step 47 100001100110100100011011011011011001111100011011011010100110111001 step 48 100001100110100100011011011011011101111100011011011010100110111001 step 49 110001100110100100011011011011011100110111011011011010100110111001 step 50 100001100110100100011011011011011101111100011011011010100110111001 step 51 101001100110100100011011011011011100110111011011011010100110111001 step 52 100001100110100100011011011011011101111100011011011010100110111001 step 53 100101100110100100011011011011011100110111011011011010100110111001 step 54 100001100110100100011011011011011101111100011011011010100110111001 step 55 100011100110100100011011011011011100110111011011011010100110111001 step 56 100001100110100100011011011011011101111100011011011010100110111001 step 57 100001110110100100011011011011011100110111011011011010100110111001 step 58 100001100110100100011011011011011101111100011011011010100110111001 step 59 100001101110100100011011011011011100110111011011011010100110111001 step 60 100001100110100100011011011011011101111100011011011010100110111001 step 61 100001100111100100011011011011011100111101011011011010100110111001 step 62 100001100110100100011011011011011101111100011011011010100110111001 step 63 100001100110110100011011011011011100111101011011011010100110111001 step 64 100001100110100100011011011011011101111100011011011010100110111001 step 65 100001100110101100011011011011011101110110011011011010100110111001 step 66 100001100110100100011011011011011101111100011011011010100110111001 step 67 100001100110100110011011011011011101110110011011011010100110111001 step 68 100001100110100100011011011011011101111100011011011010100110111001 step 69 100001100110100101011011011011011101001111011011011010100110111001 step 70 100001100110100100011011011011011101111100011011011010100110111001 step 71 100001100110100100111011011011011101001111011011011010100110111001 step 72 100001100110100100011011011011011101111100011011011010100110111001 step 73 100001100110100100011111011011011101001111011011011010100110111001 step 74 100001100110100100011011011011011101111100011011011010100110111001 step 75 100001100110100100011011111011011101001111011011011010100110111001 step 76 100001100110100100011011011011011101111100011011011010100110111001 step 77 100001100110100100011011011111011101001111011011011010100110111001 step 78 100001100110100100011011011011011101111100011011011010100110111001 step 79 100001100110100100011011011011111101001111011011011010100110111001 step 80 100001100110100100011011011011011101111100011011011010100110111001 step 81 100001100110100100011011011011011111101110011011011010100110111001 step 82 100001100110100100011011011011011101111100011011011010100110111001 test 164: pass SLOT BAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBAABBAAAAAAAAAAAAAABBBBBBBBAB LETTER ALPSLFMDEEMCBFRSPKLEMFHRSCJLJKUHPNMBBNNVVRKRHUTDJUKANJHBTPDFSVDEVU SIDE 121212122121212121111111112212122222112222111221112112212112212212 DIRECTION IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIOOOOOOOIOOIOOIOOIOOOOIOOIIOOIIO this fail all fails was hi 111111111111111111111111111111111111111111111111111111111111111 1 rising ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ ^^^^^^^^^^^^^^^^^^^^ ^^ falling vvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvv vvvvvvvvvvvvvvvvvvvv vv was lo 00000000000000000000000000000000000000 00000000000000000000 0000 total fails 0, total passes 164 space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C toggle comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT BAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBAABBAAAAAAAAAAAAAABBBBBBBBAB LETTER ALPSLFMDEEMCBFRSPKLEMFHRSCJLJKUHPNMBBNNVVRKRHUTDJUKANJHBTPDFSVDEVU SIDE 121212122121212121111111112212122222112222111221112112212112212212 DIRECTION IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIOOOOOOOIOOIOOIOOIOOOOIOOIIOOIIO changed: 00 00 0 0 00 00 00 00 000 step 1 100000000000000000000000000000000001111100011011011010100110111001 okay space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C toggle comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit comment_flag is 1 space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C toggle comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT BAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBAABBAAAAAAAAAAAAAABBBBBBBBAB LETTER ALPSLFMDEEMCBFRSPKLEMFHRSCJLJKUHPNMBBNNVVRKRHUTDJUKANJHBTPDFSVDEVU SIDE 121212122121212121111111112212122222112222111221112112212112212212 DIRECTION IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIOOOOOOOIOOIOOIOOIOOOOIOOIIOOIIO all fails was lo 00000000000000000000000000000000000000 00000000000000000000 0000 falling vvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvv vvvvvvvvvvvvvvvvvvvv vv rising ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ ^^^^^^^^^^^^^^^^^^^^ ^^ was hi 111111111111111111111111111111111111111111111111111111111111111 1 total fails 0, total passes 164 Main menu Sat Jul 11 10:57:08 2015 test file is: tests\m222.new delay is: 0 trigger is: 1 1 read test file 2 set test delay 3 set test trigger 4 run test 5 output loading test 8 diags 9 exit exiting tester- PDP8 card tester via printer port version 0.85 June 4, 2015 mapping[] is verified Main menu Sat Jul 11 11:01:46 2015 test file is: delay is: 0 trigger is: 1 1 read test file 2 set test delay 3 set test trigger 4 run test 5 output loading test 8 diags 9 exit Enter test file name? trying to open test file: tests\m222.new reading test file: tests\m222.new comment: M222 PCB REV B SCHEMATIC REV A LINC TAPE REGISTERS comment: comment: TERMINOLOGY- SIGNALS REFER TO VOL4 M222 SCHEMATIC. comment: comment: BUT... comment: comment: DEC USES AND-NOR GATES TO ROUTE THE ADDER A AND B INPUTS, SO... comment: DEC RENAMED THE ADDER TO NEGATIVE LOGIC TERMS (I.E. A-N + B-N + C-N -> SUM-N, C1-N). comment: (NOT THE 7482 DATASHEET NAMES OF A + B + C -> SUM, C1). comment: comment: SO, WITH ALL 'AND ENABLES' LOW, THE AND-NOR OUTPUTS = HIGH. comment: WITH C-L HIGH, THE ADDER OUTPUT IS SUM-N=1, C1-N=1; comment: THE INVERTED ADDER OUTPUT IS LOW (TAPE BUS). comment: AND THERE IS NO CARRY (C1-N IS HI). comment: comment: THE TWO ADDERS, TWO REGISTER BITS, ETC ARE LABELED BIT 2 (EVEN, MSB) AND BIT 3 (ODD, LSB). comment: THE ADDERS ARE REFERRED TO AS 'ADDER2' (MSB) AND 'ADDER3' (LSB). comment: comment: POWER PINS: comment: AA2 +5V comment: AT1 GROUND comment: AC2 GROUND comment: BA2 +5V comment: BT1 GROUND comment: BC2 GROUND comment: comment: (ALL PINS ARE USED). comment: comment: pins: PINS pins: 1 I BA1 CARRY IN-N, (TO E9-5 7482 C0) C-N TO ADDER2 pins: 2 I AL2 AND-NOR ENABLE: TAC TAC3 TO PIN BB2 (TO ADDER3) TAC2 TO PIN AN2 (TO ADDER2) pins: 3 I AP1 AND-NOR ENABLE: TMA SETUP (TMAS)3 TO PIN BB2 (TO ADDER3), (TMAS)3 TO PIN AN2 (TO ADDER2) pins: 4 I AS2 AND-NOR ENABLE: TMA TMA3 TO PIN BB2 (TO ADDER3), TMA2 TO PIN AN2 (TO ADDER2) pins: 5 I AL1 AND-NOR ENABLE: PIN AF2 TO PIN BB2 (TO ADDER3), PIN AM1 TO PIN AN2 (TO ADDER2) pins: 6 I AF2 AND-NOR INPUT (AL1 ENABLES) TO PIN BB2 (TO ADDER3). pins: 7 I AM1 AND-NOR INPUT (AL1 ENABLES) TO PIN AN2 (TO ADDER2) pins: 8 I AD2 AND-NOR ENABLE: RWB RWB3 TO PIN BB2 (TO ADDER3), RWB2 TO PIN AN2 (TO ADDER2) pins: 9 I AE2 AND-NOR ENABLE: PIN AE1 TO PIN BB2 (TO ADDER3), PIN AM2 TO PIN AN2 (TO ADDER2) pins: 10 I AE1 AND-NOR INPUT (AE2 ENABLES) TO PIN BB2 (TO ADDER3). pins: 11 I AM2 AND-NOR INPUT (AE2 ENABLES) TO PIN AN2 (TO ADDER2) pins: 12 I AC1 AND-NOR INPUT, AND WITH PIN AB2 TO PIN BB2 (TO ADDER3) pins: 13 I AB2 AND-NOR INPUT, AND WITH PIN AC1 TO PIN BB2 (TO ADDER3) pins: 14 I AF1 AND-NOR INPUT (AND WITH ITSELF) TO PIN BB2 (TO ADDER3) pins: 15 I AR2 AND-NOR INPUT, AND WITH PIN AS1 TO PIN AN2 (TO ADDER2) pins: 16 I AS1 AND-NOR INPUT, AND WITH PIN AR2 TO PIN AN2 (TO ADDER2) pins: 17 I AP2 AND-NOR INPUT (AND WITH ITSELF) TO PIN AN2 (TO ADDER2) pins: 18 I BK1 AND-NOR ENABLE: TB3 TO PIN BB1 (TO ADDER3), TB2 TO PIN BN1 (TO ADDER2) pins: 19 I BL1 AND-NOR ENABLE: PIN BE1 TO PIN BB1 (TO ADDER3), PIN BM1 TO PIN BN1 (TO ADDER2) pins: 20 I BE1 AND-NOR INPUT (BL1 ENABLES) TO PIN BB1 (TO ADDER3). pins: 21 I BM1 AND-NOR INPUT (BL1 ENABLES) TO PIN BN1 (TO ADDER2) pins: 22 I BF1 AND-NOR ENABLE: PIN BH1 TO PIN BB1 (TO ADDER3), PIN BR1 TO PIN BN1 (TO ADDER2) pins: 23 I BH1 AND-NOR INPUT (BF1 ENABLES): TO PIN BB1 (TO ADDER3), pins: 24 I BR1 AND-NOR INPUT (BF1 ENABLES): TO PIN BN1 (TO ADDER2) pins: 25 I BS1 AND-NOR ENABLE: PIN BC1 TO PIN BB1 (TO ADDER3), PIN BJ2 TO PIN BN1 (TO ADDER2) pins: 26 I BC1 AND-NOR INPUT (BS1 ENABLES): TO PIN BB1 (TO ADDER3), pins: 27 I BJ2 AND-NOR INPUT (BS1 ENABLES): TO PIN BN1 (TO ADDER2) pins: 28 I BL2 AND-NOR ENABLE: PIN BJ1 TO PIN BB1 (TO ADDER3), PIN BK2 TO PIN BN1 (TO ADDER2) pins: 29 I BJ1 AND-NOR INPUT (BL2 ENABLES): TO PIN BB1 (TO ADDER3), pins: 30 I BK2 AND-NOR INPUT (BL2 ENABLES): TO PIN BN1 (TO ADDER2) pins: 31 I BU1 AND-NOR ENABLE: PIN BH2 TO PIN BB1 (TO ADDER3), PIN BP2 TO PIN BN1 (TO ADDER2) pins: 32 I BH2 AND-NOR INPUT (BU1 ENABLES): TO PIN BB1 (TO ADDER3), pins: 33 I BP2 AND-NOR INPUT (BU1 ENABLES): TO PIN BN1 (TO ADDER2) pins: 34 I BN2 AND-NOR INPUT (AND WITH BM2): TO PIN BN1 (TO ADDER2) pins: 35 I BM2 AND-NOR INPUT (AND WITH BM2): TO PIN BN1 (TO ADDER2) pins: 36 O BB2 AND-NOR OUTPUT, (DRIVES E9-2 7482 A1) TO ADDER3 INPUT pins: 37 O BB1 AND-NOR OUTPUT, (DRIVES E9-3 7482 B1) TO ADDER3 INPUT pins: 38 O BN1 AND-NOR OUTPUT, (DRIVES E9-14 7482 A2) TO ADDER2 INPUT pins: 39 O AN2 AND-NOR OUTPUT, (DRIVES E9-13 7482 B2) TO ADDER2 INPUT pins: 40 O AV2 CARRY OUT-N (E9-10 7482 C2) pins: 41 O BV2 TAPE BUS 2 OUTPUT (INVERTED ADDER2 SUM-N (E9-12 7482 SUM2) pins: 42 O BR2 TAPE BUS 3 OUTPUT (INVERTED ADDER3 SUM-N (E9-1 7482 SUM1) pins: 43 I AK1 LOAD TMA SETUP (FROM TAPE BUS) (RISING EDGE CLOCK) pins: 44 O AR1 TMA SETUP 2 pins: 45 O AH1 TMA SETUP 3 pins: 46 I AU2 LOAD TMA (FROM TAPE BUS) (RISING EDGE CLOCK) pins: 47 O AT2 TMA 2 pins: 48 O AD1 TMA 3 pins: 49 I AJ1 LOAD TBN (FROM TAPE BUS) (RISING EDGE CLOCK) pins: 50 O AU1 TBN 2 pins: 51 O AK2 TBN 3 pins: 52 I AA1 LOAD TAC (FROM TAPE BUS) (RISING EDGE CLOCK) pins: 53 O AN1 TAC 2 pins: 54 O AJ2 TAC 2-N pins: 55 O AH2 TAC 3 pins: 56 O AB1 TAC 3-N pins: 57 I BT2 LOAD TB (FROM TAPE BUS) (RISING EDGE CLOCK) pins: 58 O BP1 TB 2 pins: 59 O BD1 TB 3 pins: 60 I BF2 LOAD RWB (FROM TB) (JAMS CLEAR,SET) pins: 61 I BS2 PHASE (SELECTS POLARITY OF RWB OUT, 0 -> INVERTED) pins: 62 O BV1 RWB OUT (=RWB 2 IF PHASE=1; =RWB 2-N IF PHASE=0) pins: 63 O BD2 RWB 3 pins: 64 I BE2 SHIFT RWB (SHIFTS PIN AV1 INTO RWB 3, SHIFTS RWB3 TO RWB2) (RISING CLOCK) pins: 65 I AV1 RWB IN (SHIFTED INTO RWB 2) pins: 66 O BU2 +3.5V pins: direction: IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIOOOOOOOIOOIOOIOOIOOOOIOOIIOOIIO comment: ; all registers are unknown comment: ; turn on C0, PHASE comment: ; with no ENABLES, BUS2,BUS3 is 11, C2 is 1 test 1: 1000000000000000000000000000000000011111000XX0XX0XX0XXXX0XX01XX001 comment: comment: ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; comment: ; comment: ; set all registers LOW comment: ; comment: ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; comment: comment: ; load TMA SETUP from tape bus (00) test 2: 100 test 3: 0 comment: ; load TMA from tape bus (00) test 4: 100 test 5: 0 comment: ; load TBN from tape bus (00) test 6: 100 test 7: 0 comment: ; load TAC from tape bus (00) test 8: 10101 test 9: 0 comment: ; load TB from tape bus (00) test 10: 100 test 11: 0 comment: ; load RWB from TB (JAMS CLEAR AND PRESET) test 12: 1 00 test 13: 0 comment: ; (no change) test 14: 100000000000000000000000000000000001111100000000000001010000100001 comment: comment: comment: ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; comment: ; comment: ; set all registers HIGH comment: ; comment: ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; comment: comment: ; set pin AF1 (AND with itself) to clear pin BB2 (AND-NOR output) and set pin BR2 TAPE BUS 3 OUTPUT test 15: 1 0 1 comment: ; set pin AP2 (AND with itself) to clear pin AN2 (AND-NOR output) and set pin BV2 TAPE BUS 2 OUTPUT test 16: 1 0 1 comment: comment: comment: ; load TMA SETUP from tape bus (11) test 17: 111 test 18: 0 comment: ; load TMA from tape bus (11) test 19: 111 test 20: 0 comment: ; load TBN from tape bus (11) test 21: 111 test 22: 0 comment: ; load TAC from tape bus (11) test 23: 11010 test 24: 0 comment: ; load TB from tape bus (11) test 25: 111 test 26: 0 comment: ; load RWB from TB (JAMS CLEAR AND PRESET) test 27: 1 11 test 28: 0 comment: ; clear pin AF1 (AND with itself) to set pin BB2 (AND-NOR output) and clear pin BR2 TAPE BUS 3 OUTPUT test 29: 0 1 0 comment: ; clear pin AP2 (AND with itself) to set pin AN2 (AND-NOR output) and clear pin BV2 TAPE BUS 2 OUTPUT test 30: 0 1 0 comment: ; (no change) test 31: 100000000000000000000000000000000001111100011011011010100110111001 comment: comment: comment: ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; comment: ; comment: ; test AND-NOR logic comment: ; comment: ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; comment: comment: ; (all registers are HIGH) comment: ; set all pins HIGH except ENABLES comment: comment: ; set pin AF2 HIGH test 32: 1 comment: ; set pin AM1 HIGH test 33: 1 comment: ; set pin AE1 HIGH test 34: 1 comment: ; set pin AM2 HIGH test 35: 1 comment: ; set pin AB2 HIGH test 36: 1 comment: ; set pin AS1 HIGH test 37: 1 comment: ; set pin BE1 HIGH test 38: 1 comment: ; set pin BM1 HIGH test 39: 1 comment: ; set pin BH1 HIGH test 40: 1 comment: ; set pin BR1 HIGH test 41: 1 comment: ; set pin BC1 HIGH test 42: 1 comment: ; set pin BJ2 HIGH test 43: 1 comment: ; set pin BJ1 HIGH test 44: 1 comment: ; set pin BK2 HIGH test 45: 1 comment: ; set pin BH2 HIGH test 46: 1 comment: ; set pin BP2 HIGH test 47: 1 comment: ; set pin BN2 HIGH test 48: 1 comment: ; toggle each ENABLE comment: comment: ; set pin AL2 to clear pin BB2 and pin AN2 AND-NOR OUTPUTS and set TAPE BUS 2 OUTPUT and TAPE BUS 3 OUTPUT test 49: 1 0 0 11 test 50: 0 1 1 00 comment: ; set pin AP1 to clear pin BB2 and pin AN2 AND-NOR OUTPUTS and set TAPE BUS 2 OUTPUT and TAPE BUS 3 OUTPUT test 51: 1 0 0 11 test 52: 0 1 1 00 comment: ; set pin AS2 to clear pin BB2 and pin AN2 AND-NOR OUTPUTS and set TAPE BUS 2 OUTPUT and TAPE BUS 3 OUTPUT test 53: 1 0 0 11 test 54: 0 1 1 00 comment: ; set pin AL1 to clear pin BB2 and pin AN2 AND-NOR OUTPUTS and set TAPE BUS 2 OUTPUT and TAPE BUS 3 OUTPUT test 55: 1 0 0 11 test 56: 0 1 1 00 comment: ; set pin AL1 to clear pin BB2 and pin AN2 AND-NOR OUTPUTS and set TAPE BUS 2 OUTPUT and TAPE BUS 3 OUTPUT test 57: 1 0 0 11 test 58: 0 1 1 00 comment: ; set pin AE2 to clear pin BB2 and pin AN2 AND-NOR OUTPUTS and set TAPE BUS 2 OUTPUT and TAPE BUS 3 OUTPUT test 59: 1 0 0 11 test 60: 0 1 1 00 comment: ; set pin AC1 to clear pin BB2 and set TAPE BUS 3 OUTPUT test 61: 1 0 1 test 62: 0 1 0 comment: ; set pin AF1 to clear pin BB2 and set TAPE BUS 3 OUTPUT test 63: 1 0 1 test 64: 0 1 0 comment: ; set pin AR2 to clear pin AN2 AND-NOR OUTPUTS and set TAPE BUS 2 OUTPUT test 65: 1 0 1 test 66: 0 1 0 comment: ; set pin AP2 to clear pin AN2 AND-NOR OUTPUTS and set TAPE BUS 2 OUTPUT test 67: 1 0 1 test 68: 0 1 0 comment: comment: ; set pin BK1 to clear pin BB1 and pin BN1 AND-NOR OUTPUTS and set TAPE BUS 2 OUTPUT and TAPE BUS 3 OUTPUT test 69: 1 00 11 test 70: 0 11 00 comment: ; set pin BL1 to clear pin BB1 and pin BN1 AND-NOR OUTPUTS and set TAPE BUS 2 OUTPUT and TAPE BUS 3 OUTPUT test 71: 1 00 11 test 72: 0 11 00 comment: ; set pin BF1 to clear pin BB1 and pin BN1 AND-NOR OUTPUTS and set TAPE BUS 2 OUTPUT and TAPE BUS 3 OUTPUT test 73: 1 00 11 test 74: 0 11 00 comment: ; set pin BS1 to clear pin BB1 and pin BN1 AND-NOR OUTPUTS and set TAPE BUS 2 OUTPUT and TAPE BUS 3 OUTPUT test 75: 1 00 11 test 76: 0 11 00 comment: ; set pin BL2 to clear pin BB1 and pin BN1 AND-NOR OUTPUTS and set TAPE BUS 2 OUTPUT and TAPE BUS 3 OUTPUT test 77: 1 00 11 test 78: 0 11 00 comment: ; set pin BU1 to clear pin BB1 and pin BN1 AND-NOR OUTPUTS and set TAPE BUS 2 OUTPUT and TAPE BUS 3 OUTPUT test 79: 1 00 11 test 80: 0 11 00 comment: ; set pin BM2 to clear pin BB1 and TAPE BUS 3 OUTPUT test 81: 1 0 1 test 82: 0 1 0 comment: comment: comment: ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; comment: ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; comment: ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; comment: ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; comment: ; needs work comment: ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; comment: ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; comment: ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; comment: ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; end: END summary column 1: offset 2, mask 0x2000 column 2: offset 1, mask 0x0002 column 3: offset 1, mask 0x0800 column 4: offset 1, mask 0x0040 column 5: offset 1, mask 0x4000 column 6: offset 0, mask 0x0004 column 7: offset 1, mask 0x2000 column 8: offset 0, mask 0x0010 column 9: offset 0, mask 0x0008 column 10: offset 0, mask 0x0800 column 11: offset 1, mask 0x0004 column 12: offset 0, mask 0x2000 column 13: offset 0, mask 0x0040 column 14: offset 0, mask 0x0400 column 15: offset 1, mask 0x0020 column 16: offset 1, mask 0x0200 column 17: offset 1, mask 0x0010 column 18: offset 3, mask 0x2000 column 19: offset 3, mask 0x1000 column 20: offset 2, mask 0x0200 column 21: offset 3, mask 0x0800 column 22: offset 2, mask 0x0100 column 23: offset 3, mask 0x8000 column 24: offset 3, mask 0x0100 column 25: offset 4, mask 0x8000 column 26: offset 2, mask 0x0800 column 27: offset 3, mask 0x0002 column 28: offset 3, mask 0x0008 column 29: offset 3, mask 0x4000 column 30: offset 3, mask 0x0004 column 31: offset 4, mask 0x2000 column 32: offset 3, mask 0x0001 column 33: offset 3, mask 0x0040 column 34: offset 3, mask 0x0020 column 35: offset 3, mask 0x0010 column 36: offset 2, mask 0x0008 column 37: offset 2, mask 0x1000 column 38: offset 3, mask 0x0400 column 39: offset 1, mask 0x0008 column 40: offset 2, mask 0x0002 column 41: offset 4, mask 0x0008 column 42: offset 3, mask 0x0080 column 43: offset 1, mask 0x8000 column 44: offset 1, mask 0x0400 column 45: offset 0, mask 0x0200 column 46: offset 2, mask 0x0001 column 47: offset 1, mask 0x0080 column 48: offset 0, mask 0x1000 column 49: offset 0, mask 0x0100 column 50: offset 2, mask 0x8000 column 51: offset 1, mask 0x0001 column 52: offset 0, mask 0x8000 column 53: offset 1, mask 0x1000 column 54: offset 0, mask 0x0001 column 55: offset 0, mask 0x0002 column 56: offset 0, mask 0x4000 column 57: offset 4, mask 0x0002 column 58: offset 3, mask 0x0200 column 59: offset 2, mask 0x0400 column 60: offset 2, mask 0x0080 column 61: offset 4, mask 0x0001 column 62: offset 4, mask 0x1000 column 63: offset 2, mask 0x0020 column 64: offset 2, mask 0x0040 column 65: offset 2, mask 0x4000 column 66: offset 4, mask 0x0004 direction bits (1=input) 0x52A3 0x1589 0x943A 0x0680 0x50FC pullup bits (1=pullup) 0x0000 0x0000 0x0000 0x0000 0x0000 test step out_data dont care 1: 0x0000 0x0008 0x300A 0x0400 0x0005 0x5203 0x1481 0x8420 0x0200 0x1000 2: 0x0000 0x8008 0x300A 0x0400 0x0005 0x5003 0x1081 0x8420 0x0200 0x1000 3: 0x0000 0x0008 0x300A 0x0400 0x0005 0x5003 0x1081 0x8420 0x0200 0x1000 4: 0x0000 0x0008 0x300B 0x0400 0x0005 0x4003 0x1001 0x8420 0x0200 0x1000 5: 0x0000 0x0008 0x300A 0x0400 0x0005 0x4003 0x1001 0x8420 0x0200 0x1000 6: 0x0100 0x0008 0x300A 0x0400 0x0005 0x4003 0x1000 0x0420 0x0200 0x1000 7: 0x0000 0x0008 0x300A 0x0400 0x0005 0x4003 0x1000 0x0420 0x0200 0x1000 8: 0xC001 0x0008 0x300A 0x0400 0x0005 0x0000 0x0000 0x0420 0x0200 0x1000 9: 0x4001 0x0008 0x300A 0x0400 0x0005 0x0000 0x0000 0x0420 0x0200 0x1000 10: 0x4001 0x0008 0x300A 0x0400 0x0007 0x0000 0x0000 0x0020 0x0000 0x1000 11: 0x4001 0x0008 0x300A 0x0400 0x0005 0x0000 0x0000 0x0020 0x0000 0x1000 12: 0x4001 0x0008 0x308A 0x0400 0x0005 13: 0x4001 0x0008 0x300A 0x0400 0x0005 14: 0x4001 0x0008 0x300A 0x0400 0x0005 15: 0x4401 0x0008 0x3002 0x0480 0x0005 16: 0x4401 0x0010 0x3002 0x0480 0x000D 17: 0x4601 0x8410 0x3002 0x0480 0x000D 18: 0x4601 0x0410 0x3002 0x0480 0x000D 19: 0x5601 0x0490 0x3003 0x0480 0x000D 20: 0x5601 0x0490 0x3002 0x0480 0x000D 21: 0x5701 0x0491 0xB002 0x0480 0x000D 22: 0x5601 0x0491 0xB002 0x0480 0x000D 23: 0x9602 0x1491 0xB002 0x0480 0x000D 24: 0x1602 0x1491 0xB002 0x0480 0x000D 25: 0x1602 0x1491 0xB402 0x0680 0x000F 26: 0x1602 0x1491 0xB402 0x0680 0x000D 27: 0x1602 0x1491 0xB4A2 0x0680 0x100D 28: 0x1602 0x1491 0xB422 0x0680 0x100D 29: 0x1202 0x1491 0xB42A 0x0600 0x100D 30: 0x1202 0x1489 0xB42A 0x0600 0x1005 31: 0x1202 0x1489 0xB42A 0x0600 0x1005 32: 0x1206 0x1489 0xB42A 0x0600 0x1005 33: 0x1206 0x3489 0xB42A 0x0600 0x1005 34: 0x1A06 0x3489 0xB42A 0x0600 0x1005 35: 0x1A06 0x348D 0xB42A 0x0600 0x1005 36: 0x1A46 0x348D 0xB42A 0x0600 0x1005 37: 0x1A46 0x368D 0xB42A 0x0600 0x1005 38: 0x1A46 0x368D 0xB62A 0x0600 0x1005 39: 0x1A46 0x368D 0xB62A 0x0E00 0x1005 40: 0x1A46 0x368D 0xB62A 0x8E00 0x1005 41: 0x1A46 0x368D 0xB62A 0x8F00 0x1005 42: 0x1A46 0x368D 0xBE2A 0x8F00 0x1005 43: 0x1A46 0x368D 0xBE2A 0x8F02 0x1005 44: 0x1A46 0x368D 0xBE2A 0xCF02 0x1005 45: 0x1A46 0x368D 0xBE2A 0xCF06 0x1005 46: 0x1A46 0x368D 0xBE2A 0xCF07 0x1005 47: 0x1A46 0x368D 0xBE2A 0xCF47 0x1005 48: 0x1A46 0x368D 0xBE2A 0xCF67 0x1005 49: 0x1A46 0x3687 0xBE22 0xCFE7 0x100D 50: 0x1A46 0x368D 0xBE2A 0xCF67 0x1005 51: 0x1A46 0x3E85 0xBE22 0xCFE7 0x100D 52: 0x1A46 0x368D 0xBE2A 0xCF67 0x1005 53: 0x1A46 0x36C5 0xBE22 0xCFE7 0x100D 54: 0x1A46 0x368D 0xBE2A 0xCF67 0x1005 55: 0x1A46 0x7685 0xBE22 0xCFE7 0x100D 56: 0x1A46 0x368D 0xBE2A 0xCF67 0x1005 57: 0x1A56 0x3685 0xBE22 0xCFE7 0x100D 58: 0x1A46 0x368D 0xBE2A 0xCF67 0x1005 59: 0x1A4E 0x3685 0xBE22 0xCFE7 0x100D 60: 0x1A46 0x368D 0xBE2A 0xCF67 0x1005 61: 0x3A46 0x368D 0xBE22 0xCFE7 0x1005 62: 0x1A46 0x368D 0xBE2A 0xCF67 0x1005 63: 0x1E46 0x368D 0xBE22 0xCFE7 0x1005 64: 0x1A46 0x368D 0xBE2A 0xCF67 0x1005 65: 0x1A46 0x36A5 0xBE2A 0xCF67 0x100D 66: 0x1A46 0x368D 0xBE2A 0xCF67 0x1005 67: 0x1A46 0x3695 0xBE2A 0xCF67 0x100D 68: 0x1A46 0x368D 0xBE2A 0xCF67 0x1005 69: 0x1A46 0x368D 0xAE2A 0xEBE7 0x100D 70: 0x1A46 0x368D 0xBE2A 0xCF67 0x1005 71: 0x1A46 0x368D 0xAE2A 0xDBE7 0x100D 72: 0x1A46 0x368D 0xBE2A 0xCF67 0x1005 73: 0x1A46 0x368D 0xAF2A 0xCBE7 0x100D 74: 0x1A46 0x368D 0xBE2A 0xCF67 0x1005 75: 0x1A46 0x368D 0xAE2A 0xCBE7 0x900D 76: 0x1A46 0x368D 0xBE2A 0xCF67 0x1005 77: 0x1A46 0x368D 0xAE2A 0xCBEF 0x100D 78: 0x1A46 0x368D 0xBE2A 0xCF67 0x1005 79: 0x1A46 0x368D 0xAE2A 0xCBE7 0x300D 80: 0x1A46 0x368D 0xBE2A 0xCF67 0x1005 81: 0x1A46 0x368D 0xBE2A 0xCB77 0x100D 82: 0x1A46 0x368D 0xBE2A 0xCF67 0x1005 PINs used (in edge connector order) (G=ground,P=power) SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBB LETTER ABCDEFHJKLMNPRSTUVABCDEFHJKLMNPRSTUVABCDEFHJKLMNPRSTUVABCDEFHJKLMNPRSTUV SIDE 111111111111111111222222222222222222111111111111111111222222222222222222 USAGE IOIOIIOIIIIOIOIGOIPIGIIIOOOIIOIIIOIOIOIOIIIIIIIOOIIGIOPOGOIIIIIIIIIOIIOO UUT has 44 inputs UUT has 22 outputs contains 66 pins/columns 0 pins are not used contains 82 'test steps' M222 PCB REV B SCHEMATIC REV A LINC TAPE REGISTERS TERMINOLOGY- SIGNALS REFER TO VOL4 M222 SCHEMATIC. BUT... DEC USES AND-NOR GATES TO ROUTE THE ADDER A AND B INPUTS, SO... DEC RENAMED THE ADDER TO NEGATIVE LOGIC TERMS (I.E. A-N + B-N + C-N -> SUM-N, C1-N). (NOT THE 7482 DATASHEET NAMES OF A + B + C -> SUM, C1). SO, WITH ALL 'AND ENABLES' LOW, THE AND-NOR OUTPUTS = HIGH. WITH C-L HIGH, THE ADDER OUTPUT IS SUM-N=1, C1-N=1; THE INVERTED ADDER OUTPUT IS LOW (TAPE BUS). AND THERE IS NO CARRY (C1-N IS HI). THE TWO ADDERS, TWO REGISTER BITS, ETC ARE LABELED BIT 2 (EVEN, MSB) AND BIT 3 (ODD, LSB). THE ADDERS ARE REFERRED TO AS 'ADDER2' (MSB) AND 'ADDER3' (LSB). POWER PINS: AA2 +5V AT1 GROUND AC2 GROUND BA2 +5V BT1 GROUND BC2 GROUND (ALL PINS ARE USED). PINS Main menu Sat Jul 11 11:01:53 2015 test file is: tests\m222.new delay is: 0 trigger is: 1 1 read test file 2 set test delay 3 set test trigger 4 run test 5 output loading test 8 diags 9 exit UUT power is okay Sat Jul 11 11:06:13 2015 space single step O run once (one test, all steps) F run, stop on fail G go (run tests N run, stop on fail, no print S scope (run, no print) C toggle comment printout + increase speed (less delay) - decrease speed (more delay)(slower) Q quit test SLOT BAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBAABBAAAAAAAAAAAAAABBBBBBBBAB LETTER ALPSLFMDEEMCBFRSPKLEMFHRSCJLJKUHPNMBBNNVVRKRHUTDJUKANJHBTPDFSVDEVU SIDE 121212122121212121111111112212122222112222111221112112212112212212 DIRECTION IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIOOOOOOOIOOIOOIOOIOOOOIOOIIOOIIO all fails was lo falling rising was hi total fails 0, total passes 0 Main menu Sat Jul 11 11:06:16 2015 test file is: tests\m222.new delay is: 0 trigger is: 1 1 read test file 2 set test delay 3 set test trigger 4 run test 5 output loading test 8 diags 9 exit ***************************** UUT power is OFF * ***************************** Main menu Sat Jul 11 11:06:17 2015 test file is: tests\m222.new delay is: 0 trigger is: 1 1 read test file 2 set test delay 3 set test trigger 4 run test 5 output loading test 8 diags 9 exit UUT power is okay Sat Jul 11 11:06:23 2015 space single step O run once (one test, all steps) F run, stop on fail G go (run tests N run, stop on fail, no print S scope (run, no print) C toggle comment printout + increase speed (less delay) - decrease speed (more delay)(slower) Q quit test comment_flag is 1 space single step O run once (one test, all steps) F run, stop on fail G go (run tests N run, stop on fail, no print S scope (run, no print) C toggle comment printout + increase speed (less delay) - decrease speed (more delay)(slower) Q quit test SLOT BAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBAABBAAAAAAAAAAAAAABBBBBBBBAB LETTER ALPSLFMDEEMCBFRSPKLEMFHRSCJLJKUHPNMBBNNVVRKRHUTDJUKANJHBTPDFSVDEVU SIDE 121212122121212121111111112212122222112222111221112112212112212212 DIRECTION IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIOOOOOOOIOOIOOIOOIOOOOIOOIIOOIIO source: ; all registers are unknown source: ; turn on C0, PHASE source: ; with no ENABLES, BUS2,BUS3 is 11, C2 is 1 source: 1000000000000000000000000000000000011111000XX0XX0XX0XXXX0XX01XX001 changed: step 1 100000000000000000000000000000000001111100011011011010100100110001 okay space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C toggle comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT BAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBAABBAAAAAAAAAAAAAABBBBBBBBAB LETTER ALPSLFMDEEMCBFRSPKLEMFHRSCJLJKUHPNMBBNNVVRKRHUTDJUKANJHBTPDFSVDEVU SIDE 121212122121212121111111112212122222112222111221112112212112212212 DIRECTION IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIOOOOOOOIOOIOOIOOIOOOOIOOIIOOIIO source: source: ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; source: ; source: ; set all registers LOW source: ; source: ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; source: source: ; load TMA SETUP from tape bus (00) source: 100 changed: 100 step 2 100000000000000000000000000000000001111100100011011010100100110001 okay space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C toggle comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit 43 I AK1 LOAD TMA SETUP (FROM TAPE BUS) (RISING EDGE CLOCK) 44 O AR1 TMA SETUP 2 45 O AH1 TMA SETUP 3 space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C toggle comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit 1 I BA1 CARRY IN-N, (TO E9-5 7482 C0) C-N TO ADDER2 2 I AL2 AND-NOR ENABLE: TAC TAC3 TO PIN BB2 (TO ADDER3) TAC2 TO PIN AN2 (TO ADDER2) 3 I AP1 AND-NOR ENABLE: TMA SETUP (TMAS)3 TO PIN BB2 (TO ADDER3), (TMAS)3 TO PIN AN2 (TO ADDER2) 4 I AS2 AND-NOR ENABLE: TMA TMA3 TO PIN BB2 (TO ADDER3), TMA2 TO PIN AN2 (TO ADDER2) 5 I AL1 AND-NOR ENABLE: PIN AF2 TO PIN BB2 (TO ADDER3), PIN AM1 TO PIN AN2 (TO ADDER2) 6 I AF2 AND-NOR INPUT (AL1 ENABLES) TO PIN BB2 (TO ADDER3). 7 I AM1 AND-NOR INPUT (AL1 ENABLES) TO PIN AN2 (TO ADDER2) 8 I AD2 AND-NOR ENABLE: RWB RWB3 TO PIN BB2 (TO ADDER3), RWB2 TO PIN AN2 (TO ADDER2) 9 I AE2 AND-NOR ENABLE: PIN AE1 TO PIN BB2 (TO ADDER3), PIN AM2 TO PIN AN2 (TO ADDER2) 10 I AE1 AND-NOR INPUT (AE2 ENABLES) TO PIN BB2 (TO ADDER3). 11 I AM2 AND-NOR INPUT (AE2 ENABLES) TO PIN AN2 (TO ADDER2) 12 I AC1 AND-NOR INPUT, AND WITH PIN AB2 TO PIN BB2 (TO ADDER3) 13 I AB2 AND-NOR INPUT, AND WITH PIN AC1 TO PIN BB2 (TO ADDER3) 14 I AF1 AND-NOR INPUT (AND WITH ITSELF) TO PIN BB2 (TO ADDER3) 15 I AR2 AND-NOR INPUT, AND WITH PIN AS1 TO PIN AN2 (TO ADDER2) 16 I AS1 AND-NOR INPUT, AND WITH PIN AR2 TO PIN AN2 (TO ADDER2) 17 I AP2 AND-NOR INPUT (AND WITH ITSELF) TO PIN AN2 (TO ADDER2) 18 I BK1 AND-NOR ENABLE: TB3 TO PIN BB1 (TO ADDER3), TB2 TO PIN BN1 (TO ADDER2) 19 I BL1 AND-NOR ENABLE: PIN BE1 TO PIN BB1 (TO ADDER3), PIN BM1 TO PIN BN1 (TO ADDER2) 20 I BE1 AND-NOR INPUT (BL1 ENABLES) TO PIN BB1 (TO ADDER3). 21 I BM1 AND-NOR INPUT (BL1 ENABLES) TO PIN BN1 (TO ADDER2) 22 I BF1 AND-NOR ENABLE: PIN BH1 TO PIN BB1 (TO ADDER3), PIN BR1 TO PIN BN1 (TO ADDER2) 23 I BH1 AND-NOR INPUT (BF1 ENABLES): TO PIN BB1 (TO ADDER3), 24 I BR1 AND-NOR INPUT (BF1 ENABLES): TO PIN BN1 (TO ADDER2) 25 I BS1 AND-NOR ENABLE: PIN BC1 TO PIN BB1 (TO ADDER3), PIN BJ2 TO PIN BN1 (TO ADDER2) 26 I BC1 AND-NOR INPUT (BS1 ENABLES): TO PIN BB1 (TO ADDER3), 27 I BJ2 AND-NOR INPUT (BS1 ENABLES): TO PIN BN1 (TO ADDER2) 28 I BL2 AND-NOR ENABLE: PIN BJ1 TO PIN BB1 (TO ADDER3), PIN BK2 TO PIN BN1 (TO ADDER2) 29 I BJ1 AND-NOR INPUT (BL2 ENABLES): TO PIN BB1 (TO ADDER3), 30 I BK2 AND-NOR INPUT (BL2 ENABLES): TO PIN BN1 (TO ADDER2) 31 I BU1 AND-NOR ENABLE: PIN BH2 TO PIN BB1 (TO ADDER3), PIN BP2 TO PIN BN1 (TO ADDER2) 32 I BH2 AND-NOR INPUT (BU1 ENABLES): TO PIN BB1 (TO ADDER3), 33 I BP2 AND-NOR INPUT (BU1 ENABLES): TO PIN BN1 (TO ADDER2) 34 I BN2 AND-NOR INPUT (AND WITH BM2): TO PIN BN1 (TO ADDER2) 35 I BM2 AND-NOR INPUT (AND WITH BM2): TO PIN BN1 (TO ADDER2) 36 O BB2 AND-NOR OUTPUT, (DRIVES E9-2 7482 A1) TO ADDER3 INPUT 37 O BB1 AND-NOR OUTPUT, (DRIVES E9-3 7482 B1) TO ADDER3 INPUT 38 O BN1 AND-NOR OUTPUT, (DRIVES E9-14 7482 A2) TO ADDER2 INPUT 39 O AN2 AND-NOR OUTPUT, (DRIVES E9-13 7482 B2) TO ADDER2 INPUT 40 O AV2 CARRY OUT-N (E9-10 7482 C2) 41 O BV2 TAPE BUS 2 OUTPUT (INVERTED ADDER2 SUM-N (E9-12 7482 SUM2) 42 O BR2 TAPE BUS 3 OUTPUT (INVERTED ADDER3 SUM-N (E9-1 7482 SUM1) 43 I AK1 LOAD TMA SETUP (FROM TAPE BUS) (RISING EDGE CLOCK) 44 O AR1 TMA SETUP 2 45 O AH1 TMA SETUP 3 46 I AU2 LOAD TMA (FROM TAPE BUS) (RISING EDGE CLOCK) 47 O AT2 TMA 2 48 O AD1 TMA 3 49 I AJ1 LOAD TBN (FROM TAPE BUS) (RISING EDGE CLOCK) 50 O AU1 TBN 2 51 O AK2 TBN 3 52 I AA1 LOAD TAC (FROM TAPE BUS) (RISING EDGE CLOCK) 53 O AN1 TAC 2 54 O AJ2 TAC 2-N 55 O AH2 TAC 3 56 O AB1 TAC 3-N 57 I BT2 LOAD TB (FROM TAPE BUS) (RISING EDGE CLOCK) 58 O BP1 TB 2 59 O BD1 TB 3 60 I BF2 LOAD RWB (FROM TB) (JAMS CLEAR,SET) 61 I BS2 PHASE (SELECTS POLARITY OF RWB OUT, 0 -> INVERTED) 62 O BV1 RWB OUT (=RWB 2 IF PHASE=1; =RWB 2-N IF PHASE=0) 63 O BD2 RWB 3 64 I BE2 SHIFT RWB (SHIFTS PIN AV1 INTO RWB 3, SHIFTS RWB3 TO RWB2) (RISING CLOCK) 65 I AV1 RWB IN (SHIFTED INTO RWB 2) 66 O BU2 +3.5V space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C toggle comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit 43 I AK1 LOAD TMA SETUP (FROM TAPE BUS) (RISING EDGE CLOCK) 44 O AR1 TMA SETUP 2 45 O AH1 TMA SETUP 3 space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C toggle comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit 1 I BA1 CARRY IN-N, (TO E9-5 7482 C0) C-N TO ADDER2 2 I AL2 AND-NOR ENABLE: TAC TAC3 TO PIN BB2 (TO ADDER3) TAC2 TO PIN AN2 (TO ADDER2) 3 I AP1 AND-NOR ENABLE: TMA SETUP (TMAS)3 TO PIN BB2 (TO ADDER3), (TMAS)3 TO PIN AN2 (TO ADDER2) 4 I AS2 AND-NOR ENABLE: TMA TMA3 TO PIN BB2 (TO ADDER3), TMA2 TO PIN AN2 (TO ADDER2) 5 I AL1 AND-NOR ENABLE: PIN AF2 TO PIN BB2 (TO ADDER3), PIN AM1 TO PIN AN2 (TO ADDER2) 6 I AF2 AND-NOR INPUT (AL1 ENABLES) TO PIN BB2 (TO ADDER3). 7 I AM1 AND-NOR INPUT (AL1 ENABLES) TO PIN AN2 (TO ADDER2) 8 I AD2 AND-NOR ENABLE: RWB RWB3 TO PIN BB2 (TO ADDER3), RWB2 TO PIN AN2 (TO ADDER2) 9 I AE2 AND-NOR ENABLE: PIN AE1 TO PIN BB2 (TO ADDER3), PIN AM2 TO PIN AN2 (TO ADDER2) 10 I AE1 AND-NOR INPUT (AE2 ENABLES) TO PIN BB2 (TO ADDER3). 11 I AM2 AND-NOR INPUT (AE2 ENABLES) TO PIN AN2 (TO ADDER2) 12 I AC1 AND-NOR INPUT, AND WITH PIN AB2 TO PIN BB2 (TO ADDER3) 13 I AB2 AND-NOR INPUT, AND WITH PIN AC1 TO PIN BB2 (TO ADDER3) 14 I AF1 AND-NOR INPUT (AND WITH ITSELF) TO PIN BB2 (TO ADDER3) 15 I AR2 AND-NOR INPUT, AND WITH PIN AS1 TO PIN AN2 (TO ADDER2) 16 I AS1 AND-NOR INPUT, AND WITH PIN AR2 TO PIN AN2 (TO ADDER2) 17 I AP2 AND-NOR INPUT (AND WITH ITSELF) TO PIN AN2 (TO ADDER2) 18 I BK1 AND-NOR ENABLE: TB3 TO PIN BB1 (TO ADDER3), TB2 TO PIN BN1 (TO ADDER2) 19 I BL1 AND-NOR ENABLE: PIN BE1 TO PIN BB1 (TO ADDER3), PIN BM1 TO PIN BN1 (TO ADDER2) 20 I BE1 AND-NOR INPUT (BL1 ENABLES) TO PIN BB1 (TO ADDER3). 21 I BM1 AND-NOR INPUT (BL1 ENABLES) TO PIN BN1 (TO ADDER2) 22 I BF1 AND-NOR ENABLE: PIN BH1 TO PIN BB1 (TO ADDER3), PIN BR1 TO PIN BN1 (TO ADDER2) 23 I BH1 AND-NOR INPUT (BF1 ENABLES): TO PIN BB1 (TO ADDER3), 24 I BR1 AND-NOR INPUT (BF1 ENABLES): TO PIN BN1 (TO ADDER2) 25 I BS1 AND-NOR ENABLE: PIN BC1 TO PIN BB1 (TO ADDER3), PIN BJ2 TO PIN BN1 (TO ADDER2) 26 I BC1 AND-NOR INPUT (BS1 ENABLES): TO PIN BB1 (TO ADDER3), 27 I BJ2 AND-NOR INPUT (BS1 ENABLES): TO PIN BN1 (TO ADDER2) 28 I BL2 AND-NOR ENABLE: PIN BJ1 TO PIN BB1 (TO ADDER3), PIN BK2 TO PIN BN1 (TO ADDER2) 29 I BJ1 AND-NOR INPUT (BL2 ENABLES): TO PIN BB1 (TO ADDER3), 30 I BK2 AND-NOR INPUT (BL2 ENABLES): TO PIN BN1 (TO ADDER2) 31 I BU1 AND-NOR ENABLE: PIN BH2 TO PIN BB1 (TO ADDER3), PIN BP2 TO PIN BN1 (TO ADDER2) 32 I BH2 AND-NOR INPUT (BU1 ENABLES): TO PIN BB1 (TO ADDER3), 33 I BP2 AND-NOR INPUT (BU1 ENABLES): TO PIN BN1 (TO ADDER2) 34 I BN2 AND-NOR INPUT (AND WITH BM2): TO PIN BN1 (TO ADDER2) 35 I BM2 AND-NOR INPUT (AND WITH BM2): TO PIN BN1 (TO ADDER2) 36 O BB2 AND-NOR OUTPUT, (DRIVES E9-2 7482 A1) TO ADDER3 INPUT 37 O BB1 AND-NOR OUTPUT, (DRIVES E9-3 7482 B1) TO ADDER3 INPUT 38 O BN1 AND-NOR OUTPUT, (DRIVES E9-14 7482 A2) TO ADDER2 INPUT 39 O AN2 AND-NOR OUTPUT, (DRIVES E9-13 7482 B2) TO ADDER2 INPUT 40 O AV2 CARRY OUT-N (E9-10 7482 C2) 41 O BV2 TAPE BUS 2 OUTPUT (INVERTED ADDER2 SUM-N (E9-12 7482 SUM2) 42 O BR2 TAPE BUS 3 OUTPUT (INVERTED ADDER3 SUM-N (E9-1 7482 SUM1) 43 I AK1 LOAD TMA SETUP (FROM TAPE BUS) (RISING EDGE CLOCK) 44 O AR1 TMA SETUP 2 45 O AH1 TMA SETUP 3 46 I AU2 LOAD TMA (FROM TAPE BUS) (RISING EDGE CLOCK) 47 O AT2 TMA 2 48 O AD1 TMA 3 49 I AJ1 LOAD TBN (FROM TAPE BUS) (RISING EDGE CLOCK) 50 O AU1 TBN 2 51 O AK2 TBN 3 52 I AA1 LOAD TAC (FROM TAPE BUS) (RISING EDGE CLOCK) 53 O AN1 TAC 2 54 O AJ2 TAC 2-N 55 O AH2 TAC 3 56 O AB1 TAC 3-N 57 I BT2 LOAD TB (FROM TAPE BUS) (RISING EDGE CLOCK) 58 O BP1 TB 2 59 O BD1 TB 3 60 I BF2 LOAD RWB (FROM TB) (JAMS CLEAR,SET) 61 I BS2 PHASE (SELECTS POLARITY OF RWB OUT, 0 -> INVERTED) 62 O BV1 RWB OUT (=RWB 2 IF PHASE=1; =RWB 2-N IF PHASE=0) 63 O BD2 RWB 3 64 I BE2 SHIFT RWB (SHIFTS PIN AV1 INTO RWB 3, SHIFTS RWB3 TO RWB2) (RISING CLOCK) 65 I AV1 RWB IN (SHIFTED INTO RWB 2) 66 O BU2 +3.5V space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C toggle comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit 43 I AK1 LOAD TMA SETUP (FROM TAPE BUS) (RISING EDGE CLOCK) 44 O AR1 TMA SETUP 2 45 O AH1 TMA SETUP 3 space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C toggle comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit 1 I BA1 CARRY IN-N, (TO E9-5 7482 C0) C-N TO ADDER2 2 I AL2 AND-NOR ENABLE: TAC TAC3 TO PIN BB2 (TO ADDER3) TAC2 TO PIN AN2 (TO ADDER2) 3 I AP1 AND-NOR ENABLE: TMA SETUP (TMAS)3 TO PIN BB2 (TO ADDER3), (TMAS)3 TO PIN AN2 (TO ADDER2) 4 I AS2 AND-NOR ENABLE: TMA TMA3 TO PIN BB2 (TO ADDER3), TMA2 TO PIN AN2 (TO ADDER2) 5 I AL1 AND-NOR ENABLE: PIN AF2 TO PIN BB2 (TO ADDER3), PIN AM1 TO PIN AN2 (TO ADDER2) 6 I AF2 AND-NOR INPUT (AL1 ENABLES) TO PIN BB2 (TO ADDER3). 7 I AM1 AND-NOR INPUT (AL1 ENABLES) TO PIN AN2 (TO ADDER2) 8 I AD2 AND-NOR ENABLE: RWB RWB3 TO PIN BB2 (TO ADDER3), RWB2 TO PIN AN2 (TO ADDER2) 9 I AE2 AND-NOR ENABLE: PIN AE1 TO PIN BB2 (TO ADDER3), PIN AM2 TO PIN AN2 (TO ADDER2) 10 I AE1 AND-NOR INPUT (AE2 ENABLES) TO PIN BB2 (TO ADDER3). 11 I AM2 AND-NOR INPUT (AE2 ENABLES) TO PIN AN2 (TO ADDER2) 12 I AC1 AND-NOR INPUT, AND WITH PIN AB2 TO PIN BB2 (TO ADDER3) 13 I AB2 AND-NOR INPUT, AND WITH PIN AC1 TO PIN BB2 (TO ADDER3) 14 I AF1 AND-NOR INPUT (AND WITH ITSELF) TO PIN BB2 (TO ADDER3) 15 I AR2 AND-NOR INPUT, AND WITH PIN AS1 TO PIN AN2 (TO ADDER2) 16 I AS1 AND-NOR INPUT, AND WITH PIN AR2 TO PIN AN2 (TO ADDER2) 17 I AP2 AND-NOR INPUT (AND WITH ITSELF) TO PIN AN2 (TO ADDER2) 18 I BK1 AND-NOR ENABLE: TB3 TO PIN BB1 (TO ADDER3), TB2 TO PIN BN1 (TO ADDER2) 19 I BL1 AND-NOR ENABLE: PIN BE1 TO PIN BB1 (TO ADDER3), PIN BM1 TO PIN BN1 (TO ADDER2) 20 I BE1 AND-NOR INPUT (BL1 ENABLES) TO PIN BB1 (TO ADDER3). 21 I BM1 AND-NOR INPUT (BL1 ENABLES) TO PIN BN1 (TO ADDER2) 22 I BF1 AND-NOR ENABLE: PIN BH1 TO PIN BB1 (TO ADDER3), PIN BR1 TO PIN BN1 (TO ADDER2) 23 I BH1 AND-NOR INPUT (BF1 ENABLES): TO PIN BB1 (TO ADDER3), 24 I BR1 AND-NOR INPUT (BF1 ENABLES): TO PIN BN1 (TO ADDER2) 25 I BS1 AND-NOR ENABLE: PIN BC1 TO PIN BB1 (TO ADDER3), PIN BJ2 TO PIN BN1 (TO ADDER2) 26 I BC1 AND-NOR INPUT (BS1 ENABLES): TO PIN BB1 (TO ADDER3), 27 I BJ2 AND-NOR INPUT (BS1 ENABLES): TO PIN BN1 (TO ADDER2) 28 I BL2 AND-NOR ENABLE: PIN BJ1 TO PIN BB1 (TO ADDER3), PIN BK2 TO PIN BN1 (TO ADDER2) 29 I BJ1 AND-NOR INPUT (BL2 ENABLES): TO PIN BB1 (TO ADDER3), 30 I BK2 AND-NOR INPUT (BL2 ENABLES): TO PIN BN1 (TO ADDER2) 31 I BU1 AND-NOR ENABLE: PIN BH2 TO PIN BB1 (TO ADDER3), PIN BP2 TO PIN BN1 (TO ADDER2) 32 I BH2 AND-NOR INPUT (BU1 ENABLES): TO PIN BB1 (TO ADDER3), 33 I BP2 AND-NOR INPUT (BU1 ENABLES): TO PIN BN1 (TO ADDER2) 34 I BN2 AND-NOR INPUT (AND WITH BM2): TO PIN BN1 (TO ADDER2) 35 I BM2 AND-NOR INPUT (AND WITH BM2): TO PIN BN1 (TO ADDER2) 36 O BB2 AND-NOR OUTPUT, (DRIVES E9-2 7482 A1) TO ADDER3 INPUT 37 O BB1 AND-NOR OUTPUT, (DRIVES E9-3 7482 B1) TO ADDER3 INPUT 38 O BN1 AND-NOR OUTPUT, (DRIVES E9-14 7482 A2) TO ADDER2 INPUT 39 O AN2 AND-NOR OUTPUT, (DRIVES E9-13 7482 B2) TO ADDER2 INPUT 40 O AV2 CARRY OUT-N (E9-10 7482 C2) 41 O BV2 TAPE BUS 2 OUTPUT (INVERTED ADDER2 SUM-N (E9-12 7482 SUM2) 42 O BR2 TAPE BUS 3 OUTPUT (INVERTED ADDER3 SUM-N (E9-1 7482 SUM1) 43 I AK1 LOAD TMA SETUP (FROM TAPE BUS) (RISING EDGE CLOCK) 44 O AR1 TMA SETUP 2 45 O AH1 TMA SETUP 3 46 I AU2 LOAD TMA (FROM TAPE BUS) (RISING EDGE CLOCK) 47 O AT2 TMA 2 48 O AD1 TMA 3 49 I AJ1 LOAD TBN (FROM TAPE BUS) (RISING EDGE CLOCK) 50 O AU1 TBN 2 51 O AK2 TBN 3 52 I AA1 LOAD TAC (FROM TAPE BUS) (RISING EDGE CLOCK) 53 O AN1 TAC 2 54 O AJ2 TAC 2-N 55 O AH2 TAC 3 56 O AB1 TAC 3-N 57 I BT2 LOAD TB (FROM TAPE BUS) (RISING EDGE CLOCK) 58 O BP1 TB 2 59 O BD1 TB 3 60 I BF2 LOAD RWB (FROM TB) (JAMS CLEAR,SET) 61 I BS2 PHASE (SELECTS POLARITY OF RWB OUT, 0 -> INVERTED) 62 O BV1 RWB OUT (=RWB 2 IF PHASE=1; =RWB 2-N IF PHASE=0) 63 O BD2 RWB 3 64 I BE2 SHIFT RWB (SHIFTS PIN AV1 INTO RWB 3, SHIFTS RWB3 TO RWB2) (RISING CLOCK) 65 I AV1 RWB IN (SHIFTED INTO RWB 2) 66 O BU2 +3.5V space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C toggle comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit 43 I AK1 LOAD TMA SETUP (FROM TAPE BUS) (RISING EDGE CLOCK) 44 O AR1 TMA SETUP 2 45 O AH1 TMA SETUP 3 space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C toggle comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit 1 I BA1 CARRY IN-N, (TO E9-5 7482 C0) C-N TO ADDER2 2 I AL2 AND-NOR ENABLE: TAC TAC3 TO PIN BB2 (TO ADDER3) TAC2 TO PIN AN2 (TO ADDER2) 3 I AP1 AND-NOR ENABLE: TMA SETUP (TMAS)3 TO PIN BB2 (TO ADDER3), (TMAS)3 TO PIN AN2 (TO ADDER2) 4 I AS2 AND-NOR ENABLE: TMA TMA3 TO PIN BB2 (TO ADDER3), TMA2 TO PIN AN2 (TO ADDER2) 5 I AL1 AND-NOR ENABLE: PIN AF2 TO PIN BB2 (TO ADDER3), PIN AM1 TO PIN AN2 (TO ADDER2) 6 I AF2 AND-NOR INPUT (AL1 ENABLES) TO PIN BB2 (TO ADDER3). 7 I AM1 AND-NOR INPUT (AL1 ENABLES) TO PIN AN2 (TO ADDER2) 8 I AD2 AND-NOR ENABLE: RWB RWB3 TO PIN BB2 (TO ADDER3), RWB2 TO PIN AN2 (TO ADDER2) 9 I AE2 AND-NOR ENABLE: PIN AE1 TO PIN BB2 (TO ADDER3), PIN AM2 TO PIN AN2 (TO ADDER2) 10 I AE1 AND-NOR INPUT (AE2 ENABLES) TO PIN BB2 (TO ADDER3). 11 I AM2 AND-NOR INPUT (AE2 ENABLES) TO PIN AN2 (TO ADDER2) 12 I AC1 AND-NOR INPUT, AND WITH PIN AB2 TO PIN BB2 (TO ADDER3) 13 I AB2 AND-NOR INPUT, AND WITH PIN AC1 TO PIN BB2 (TO ADDER3) 14 I AF1 AND-NOR INPUT (AND WITH ITSELF) TO PIN BB2 (TO ADDER3) 15 I AR2 AND-NOR INPUT, AND WITH PIN AS1 TO PIN AN2 (TO ADDER2) 16 I AS1 AND-NOR INPUT, AND WITH PIN AR2 TO PIN AN2 (TO ADDER2) 17 I AP2 AND-NOR INPUT (AND WITH ITSELF) TO PIN AN2 (TO ADDER2) 18 I BK1 AND-NOR ENABLE: TB3 TO PIN BB1 (TO ADDER3), TB2 TO PIN BN1 (TO ADDER2) 19 I BL1 AND-NOR ENABLE: PIN BE1 TO PIN BB1 (TO ADDER3), PIN BM1 TO PIN BN1 (TO ADDER2) 20 I BE1 AND-NOR INPUT (BL1 ENABLES) TO PIN BB1 (TO ADDER3). 21 I BM1 AND-NOR INPUT (BL1 ENABLES) TO PIN BN1 (TO ADDER2) 22 I BF1 AND-NOR ENABLE: PIN BH1 TO PIN BB1 (TO ADDER3), PIN BR1 TO PIN BN1 (TO ADDER2) 23 I BH1 AND-NOR INPUT (BF1 ENABLES): TO PIN BB1 (TO ADDER3), 24 I BR1 AND-NOR INPUT (BF1 ENABLES): TO PIN BN1 (TO ADDER2) 25 I BS1 AND-NOR ENABLE: PIN BC1 TO PIN BB1 (TO ADDER3), PIN BJ2 TO PIN BN1 (TO ADDER2) 26 I BC1 AND-NOR INPUT (BS1 ENABLES): TO PIN BB1 (TO ADDER3), 27 I BJ2 AND-NOR INPUT (BS1 ENABLES): TO PIN BN1 (TO ADDER2) 28 I BL2 AND-NOR ENABLE: PIN BJ1 TO PIN BB1 (TO ADDER3), PIN BK2 TO PIN BN1 (TO ADDER2) 29 I BJ1 AND-NOR INPUT (BL2 ENABLES): TO PIN BB1 (TO ADDER3), 30 I BK2 AND-NOR INPUT (BL2 ENABLES): TO PIN BN1 (TO ADDER2) 31 I BU1 AND-NOR ENABLE: PIN BH2 TO PIN BB1 (TO ADDER3), PIN BP2 TO PIN BN1 (TO ADDER2) 32 I BH2 AND-NOR INPUT (BU1 ENABLES): TO PIN BB1 (TO ADDER3), 33 I BP2 AND-NOR INPUT (BU1 ENABLES): TO PIN BN1 (TO ADDER2) 34 I BN2 AND-NOR INPUT (AND WITH BM2): TO PIN BN1 (TO ADDER2) 35 I BM2 AND-NOR INPUT (AND WITH BM2): TO PIN BN1 (TO ADDER2) 36 O BB2 AND-NOR OUTPUT, (DRIVES E9-2 7482 A1) TO ADDER3 INPUT 37 O BB1 AND-NOR OUTPUT, (DRIVES E9-3 7482 B1) TO ADDER3 INPUT 38 O BN1 AND-NOR OUTPUT, (DRIVES E9-14 7482 A2) TO ADDER2 INPUT 39 O AN2 AND-NOR OUTPUT, (DRIVES E9-13 7482 B2) TO ADDER2 INPUT 40 O AV2 CARRY OUT-N (E9-10 7482 C2) 41 O BV2 TAPE BUS 2 OUTPUT (INVERTED ADDER2 SUM-N (E9-12 7482 SUM2) 42 O BR2 TAPE BUS 3 OUTPUT (INVERTED ADDER3 SUM-N (E9-1 7482 SUM1) 43 I AK1 LOAD TMA SETUP (FROM TAPE BUS) (RISING EDGE CLOCK) 44 O AR1 TMA SETUP 2 45 O AH1 TMA SETUP 3 46 I AU2 LOAD TMA (FROM TAPE BUS) (RISING EDGE CLOCK) 47 O AT2 TMA 2 48 O AD1 TMA 3 49 I AJ1 LOAD TBN (FROM TAPE BUS) (RISING EDGE CLOCK) 50 O AU1 TBN 2 51 O AK2 TBN 3 52 I AA1 LOAD TAC (FROM TAPE BUS) (RISING EDGE CLOCK) 53 O AN1 TAC 2 54 O AJ2 TAC 2-N 55 O AH2 TAC 3 56 O AB1 TAC 3-N 57 I BT2 LOAD TB (FROM TAPE BUS) (RISING EDGE CLOCK) 58 O BP1 TB 2 59 O BD1 TB 3 60 I BF2 LOAD RWB (FROM TB) (JAMS CLEAR,SET) 61 I BS2 PHASE (SELECTS POLARITY OF RWB OUT, 0 -> INVERTED) 62 O BV1 RWB OUT (=RWB 2 IF PHASE=1; =RWB 2-N IF PHASE=0) 63 O BD2 RWB 3 64 I BE2 SHIFT RWB (SHIFTS PIN AV1 INTO RWB 3, SHIFTS RWB3 TO RWB2) (RISING CLOCK) 65 I AV1 RWB IN (SHIFTED INTO RWB 2) 66 O BU2 +3.5V space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C toggle comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit 43 I AK1 LOAD TMA SETUP (FROM TAPE BUS) (RISING EDGE CLOCK) 44 O AR1 TMA SETUP 2 45 O AH1 TMA SETUP 3 space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C toggle comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit 1 I BA1 CARRY IN-N, (TO E9-5 7482 C0) C-N TO ADDER2 2 I AL2 AND-NOR ENABLE: TAC TAC3 TO PIN BB2 (TO ADDER3) TAC2 TO PIN AN2 (TO ADDER2) 3 I AP1 AND-NOR ENABLE: TMA SETUP (TMAS)3 TO PIN BB2 (TO ADDER3), (TMAS)3 TO PIN AN2 (TO ADDER2) 4 I AS2 AND-NOR ENABLE: TMA TMA3 TO PIN BB2 (TO ADDER3), TMA2 TO PIN AN2 (TO ADDER2) 5 I AL1 AND-NOR ENABLE: PIN AF2 TO PIN BB2 (TO ADDER3), PIN AM1 TO PIN AN2 (TO ADDER2) 6 I AF2 AND-NOR INPUT (AL1 ENABLES) TO PIN BB2 (TO ADDER3). 7 I AM1 AND-NOR INPUT (AL1 ENABLES) TO PIN AN2 (TO ADDER2) 8 I AD2 AND-NOR ENABLE: RWB RWB3 TO PIN BB2 (TO ADDER3), RWB2 TO PIN AN2 (TO ADDER2) 9 I AE2 AND-NOR ENABLE: PIN AE1 TO PIN BB2 (TO ADDER3), PIN AM2 TO PIN AN2 (TO ADDER2) 10 I AE1 AND-NOR INPUT (AE2 ENABLES) TO PIN BB2 (TO ADDER3). 11 I AM2 AND-NOR INPUT (AE2 ENABLES) TO PIN AN2 (TO ADDER2) 12 I AC1 AND-NOR INPUT, AND WITH PIN AB2 TO PIN BB2 (TO ADDER3) 13 I AB2 AND-NOR INPUT, AND WITH PIN AC1 TO PIN BB2 (TO ADDER3) 14 I AF1 AND-NOR INPUT (AND WITH ITSELF) TO PIN BB2 (TO ADDER3) 15 I AR2 AND-NOR INPUT, AND WITH PIN AS1 TO PIN AN2 (TO ADDER2) 16 I AS1 AND-NOR INPUT, AND WITH PIN AR2 TO PIN AN2 (TO ADDER2) 17 I AP2 AND-NOR INPUT (AND WITH ITSELF) TO PIN AN2 (TO ADDER2) 18 I BK1 AND-NOR ENABLE: TB3 TO PIN BB1 (TO ADDER3), TB2 TO PIN BN1 (TO ADDER2) 19 I BL1 AND-NOR ENABLE: PIN BE1 TO PIN BB1 (TO ADDER3), PIN BM1 TO PIN BN1 (TO ADDER2) 20 I BE1 AND-NOR INPUT (BL1 ENABLES) TO PIN BB1 (TO ADDER3). 21 I BM1 AND-NOR INPUT (BL1 ENABLES) TO PIN BN1 (TO ADDER2) 22 I BF1 AND-NOR ENABLE: PIN BH1 TO PIN BB1 (TO ADDER3), PIN BR1 TO PIN BN1 (TO ADDER2) 23 I BH1 AND-NOR INPUT (BF1 ENABLES): TO PIN BB1 (TO ADDER3), 24 I BR1 AND-NOR INPUT (BF1 ENABLES): TO PIN BN1 (TO ADDER2) 25 I BS1 AND-NOR ENABLE: PIN BC1 TO PIN BB1 (TO ADDER3), PIN BJ2 TO PIN BN1 (TO ADDER2) 26 I BC1 AND-NOR INPUT (BS1 ENABLES): TO PIN BB1 (TO ADDER3), 27 I BJ2 AND-NOR INPUT (BS1 ENABLES): TO PIN BN1 (TO ADDER2) 28 I BL2 AND-NOR ENABLE: PIN BJ1 TO PIN BB1 (TO ADDER3), PIN BK2 TO PIN BN1 (TO ADDER2) 29 I BJ1 AND-NOR INPUT (BL2 ENABLES): TO PIN BB1 (TO ADDER3), 30 I BK2 AND-NOR INPUT (BL2 ENABLES): TO PIN BN1 (TO ADDER2) 31 I BU1 AND-NOR ENABLE: PIN BH2 TO PIN BB1 (TO ADDER3), PIN BP2 TO PIN BN1 (TO ADDER2) 32 I BH2 AND-NOR INPUT (BU1 ENABLES): TO PIN BB1 (TO ADDER3), 33 I BP2 AND-NOR INPUT (BU1 ENABLES): TO PIN BN1 (TO ADDER2) 34 I BN2 AND-NOR INPUT (AND WITH BM2): TO PIN BN1 (TO ADDER2) 35 I BM2 AND-NOR INPUT (AND WITH BM2): TO PIN BN1 (TO ADDER2) 36 O BB2 AND-NOR OUTPUT, (DRIVES E9-2 7482 A1) TO ADDER3 INPUT 37 O BB1 AND-NOR OUTPUT, (DRIVES E9-3 7482 B1) TO ADDER3 INPUT 38 O BN1 AND-NOR OUTPUT, (DRIVES E9-14 7482 A2) TO ADDER2 INPUT 39 O AN2 AND-NOR OUTPUT, (DRIVES E9-13 7482 B2) TO ADDER2 INPUT 40 O AV2 CARRY OUT-N (E9-10 7482 C2) 41 O BV2 TAPE BUS 2 OUTPUT (INVERTED ADDER2 SUM-N (E9-12 7482 SUM2) 42 O BR2 TAPE BUS 3 OUTPUT (INVERTED ADDER3 SUM-N (E9-1 7482 SUM1) 43 I AK1 LOAD TMA SETUP (FROM TAPE BUS) (RISING EDGE CLOCK) 44 O AR1 TMA SETUP 2 45 O AH1 TMA SETUP 3 46 I AU2 LOAD TMA (FROM TAPE BUS) (RISING EDGE CLOCK) 47 O AT2 TMA 2 48 O AD1 TMA 3 49 I AJ1 LOAD TBN (FROM TAPE BUS) (RISING EDGE CLOCK) 50 O AU1 TBN 2 51 O AK2 TBN 3 52 I AA1 LOAD TAC (FROM TAPE BUS) (RISING EDGE CLOCK) 53 O AN1 TAC 2 54 O AJ2 TAC 2-N 55 O AH2 TAC 3 56 O AB1 TAC 3-N 57 I BT2 LOAD TB (FROM TAPE BUS) (RISING EDGE CLOCK) 58 O BP1 TB 2 59 O BD1 TB 3 60 I BF2 LOAD RWB (FROM TB) (JAMS CLEAR,SET) 61 I BS2 PHASE (SELECTS POLARITY OF RWB OUT, 0 -> INVERTED) 62 O BV1 RWB OUT (=RWB 2 IF PHASE=1; =RWB 2-N IF PHASE=0) 63 O BD2 RWB 3 64 I BE2 SHIFT RWB (SHIFTS PIN AV1 INTO RWB 3, SHIFTS RWB3 TO RWB2) (RISING CLOCK) 65 I AV1 RWB IN (SHIFTED INTO RWB 2) 66 O BU2 +3.5V space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C toggle comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit 43 I AK1 LOAD TMA SETUP (FROM TAPE BUS) (RISING EDGE CLOCK) 44 O AR1 TMA SETUP 2 45 O AH1 TMA SETUP 3 space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C toggle comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit 1 I BA1 CARRY IN-N, (TO E9-5 7482 C0) C-N TO ADDER2 2 I AL2 AND-NOR ENABLE: TAC TAC3 TO PIN BB2 (TO ADDER3) TAC2 TO PIN AN2 (TO ADDER2) 3 I AP1 AND-NOR ENABLE: TMA SETUP (TMAS)3 TO PIN BB2 (TO ADDER3), (TMAS)3 TO PIN AN2 (TO ADDER2) 4 I AS2 AND-NOR ENABLE: TMA TMA3 TO PIN BB2 (TO ADDER3), TMA2 TO PIN AN2 (TO ADDER2) 5 I AL1 AND-NOR ENABLE: PIN AF2 TO PIN BB2 (TO ADDER3), PIN AM1 TO PIN AN2 (TO ADDER2) 6 I AF2 AND-NOR INPUT (AL1 ENABLES) TO PIN BB2 (TO ADDER3). 7 I AM1 AND-NOR INPUT (AL1 ENABLES) TO PIN AN2 (TO ADDER2) 8 I AD2 AND-NOR ENABLE: RWB RWB3 TO PIN BB2 (TO ADDER3), RWB2 TO PIN AN2 (TO ADDER2) 9 I AE2 AND-NOR ENABLE: PIN AE1 TO PIN BB2 (TO ADDER3), PIN AM2 TO PIN AN2 (TO ADDER2) 10 I AE1 AND-NOR INPUT (AE2 ENABLES) TO PIN BB2 (TO ADDER3). 11 I AM2 AND-NOR INPUT (AE2 ENABLES) TO PIN AN2 (TO ADDER2) 12 I AC1 AND-NOR INPUT, AND WITH PIN AB2 TO PIN BB2 (TO ADDER3) 13 I AB2 AND-NOR INPUT, AND WITH PIN AC1 TO PIN BB2 (TO ADDER3) 14 I AF1 AND-NOR INPUT (AND WITH ITSELF) TO PIN BB2 (TO ADDER3) 15 I AR2 AND-NOR INPUT, AND WITH PIN AS1 TO PIN AN2 (TO ADDER2) 16 I AS1 AND-NOR INPUT, AND WITH PIN AR2 TO PIN AN2 (TO ADDER2) 17 I AP2 AND-NOR INPUT (AND WITH ITSELF) TO PIN AN2 (TO ADDER2) 18 I BK1 AND-NOR ENABLE: TB3 TO PIN BB1 (TO ADDER3), TB2 TO PIN BN1 (TO ADDER2) 19 I BL1 AND-NOR ENABLE: PIN BE1 TO PIN BB1 (TO ADDER3), PIN BM1 TO PIN BN1 (TO ADDER2) 20 I BE1 AND-NOR INPUT (BL1 ENABLES) TO PIN BB1 (TO ADDER3). 21 I BM1 AND-NOR INPUT (BL1 ENABLES) TO PIN BN1 (TO ADDER2) 22 I BF1 AND-NOR ENABLE: PIN BH1 TO PIN BB1 (TO ADDER3), PIN BR1 TO PIN BN1 (TO ADDER2) 23 I BH1 AND-NOR INPUT (BF1 ENABLES): TO PIN BB1 (TO ADDER3), 24 I BR1 AND-NOR INPUT (BF1 ENABLES): TO PIN BN1 (TO ADDER2) 25 I BS1 AND-NOR ENABLE: PIN BC1 TO PIN BB1 (TO ADDER3), PIN BJ2 TO PIN BN1 (TO ADDER2) 26 I BC1 AND-NOR INPUT (BS1 ENABLES): TO PIN BB1 (TO ADDER3), 27 I BJ2 AND-NOR INPUT (BS1 ENABLES): TO PIN BN1 (TO ADDER2) 28 I BL2 AND-NOR ENABLE: PIN BJ1 TO PIN BB1 (TO ADDER3), PIN BK2 TO PIN BN1 (TO ADDER2) 29 I BJ1 AND-NOR INPUT (BL2 ENABLES): TO PIN BB1 (TO ADDER3), 30 I BK2 AND-NOR INPUT (BL2 ENABLES): TO PIN BN1 (TO ADDER2) 31 I BU1 AND-NOR ENABLE: PIN BH2 TO PIN BB1 (TO ADDER3), PIN BP2 TO PIN BN1 (TO ADDER2) 32 I BH2 AND-NOR INPUT (BU1 ENABLES): TO PIN BB1 (TO ADDER3), 33 I BP2 AND-NOR INPUT (BU1 ENABLES): TO PIN BN1 (TO ADDER2) 34 I BN2 AND-NOR INPUT (AND WITH BM2): TO PIN BN1 (TO ADDER2) 35 I BM2 AND-NOR INPUT (AND WITH BM2): TO PIN BN1 (TO ADDER2) 36 O BB2 AND-NOR OUTPUT, (DRIVES E9-2 7482 A1) TO ADDER3 INPUT 37 O BB1 AND-NOR OUTPUT, (DRIVES E9-3 7482 B1) TO ADDER3 INPUT 38 O BN1 AND-NOR OUTPUT, (DRIVES E9-14 7482 A2) TO ADDER2 INPUT 39 O AN2 AND-NOR OUTPUT, (DRIVES E9-13 7482 B2) TO ADDER2 INPUT 40 O AV2 CARRY OUT-N (E9-10 7482 C2) 41 O BV2 TAPE BUS 2 OUTPUT (INVERTED ADDER2 SUM-N (E9-12 7482 SUM2) 42 O BR2 TAPE BUS 3 OUTPUT (INVERTED ADDER3 SUM-N (E9-1 7482 SUM1) 43 I AK1 LOAD TMA SETUP (FROM TAPE BUS) (RISING EDGE CLOCK) 44 O AR1 TMA SETUP 2 45 O AH1 TMA SETUP 3 46 I AU2 LOAD TMA (FROM TAPE BUS) (RISING EDGE CLOCK) 47 O AT2 TMA 2 48 O AD1 TMA 3 49 I AJ1 LOAD TBN (FROM TAPE BUS) (RISING EDGE CLOCK) 50 O AU1 TBN 2 51 O AK2 TBN 3 52 I AA1 LOAD TAC (FROM TAPE BUS) (RISING EDGE CLOCK) 53 O AN1 TAC 2 54 O AJ2 TAC 2-N 55 O AH2 TAC 3 56 O AB1 TAC 3-N 57 I BT2 LOAD TB (FROM TAPE BUS) (RISING EDGE CLOCK) 58 O BP1 TB 2 59 O BD1 TB 3 60 I BF2 LOAD RWB (FROM TB) (JAMS CLEAR,SET) 61 I BS2 PHASE (SELECTS POLARITY OF RWB OUT, 0 -> INVERTED) 62 O BV1 RWB OUT (=RWB 2 IF PHASE=1; =RWB 2-N IF PHASE=0) 63 O BD2 RWB 3 64 I BE2 SHIFT RWB (SHIFTS PIN AV1 INTO RWB 3, SHIFTS RWB3 TO RWB2) (RISING CLOCK) 65 I AV1 RWB IN (SHIFTED INTO RWB 2) 66 O BU2 +3.5V space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C toggle comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit 43 I AK1 LOAD TMA SETUP (FROM TAPE BUS) (RISING EDGE CLOCK) 44 O AR1 TMA SETUP 2 45 O AH1 TMA SETUP 3 space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C toggle comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT BAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBAABBAAAAAAAAAAAAAABBBBBBBBAB LETTER ALPSLFMDEEMCBFRSPKLEMFHRSCJLJKUHPNMBBNNVVRKRHUTDJUKANJHBTPDFSVDEVU SIDE 121212122121212121111111112212122222112222111221112112212112212212 DIRECTION IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIOOOOOOOIOOIOOIOOIOOOOIOOIIOOIIO source: 0 changed: 0 step 3 100000000000000000000000000000000001111100000011011010100100110001 okay space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C toggle comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT BAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBAABBAAAAAAAAAAAAAABBBBBBBBAB LETTER ALPSLFMDEEMCBFRSPKLEMFHRSCJLJKUHPNMBBNNVVRKRHUTDJUKANJHBTPDFSVDEVU SIDE 121212122121212121111111112212122222112222111221112112212112212212 DIRECTION IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIOOOOOOOIOOIOOIOOIOOOOIOOIIOOIIO source: ; load TMA from tape bus (00) source: 100 changed: 100 step 4 100000000000000000000000000000000001111100000100011010100100110001 okay space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C toggle comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT BAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBAABBAAAAAAAAAAAAAABBBBBBBBAB LETTER ALPSLFMDEEMCBFRSPKLEMFHRSCJLJKUHPNMBBNNVVRKRHUTDJUKANJHBTPDFSVDEVU SIDE 121212122121212121111111112212122222112222111221112112212112212212 DIRECTION IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIOOOOOOOIOOIOOIOOIOOOOIOOIIOOIIO source: 0 changed: 0 step 5 100000000000000000000000000000000001111100000000011010100100110001 okay space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C toggle comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT BAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBAABBAAAAAAAAAAAAAABBBBBBBBAB LETTER ALPSLFMDEEMCBFRSPKLEMFHRSCJLJKUHPNMBBNNVVRKRHUTDJUKANJHBTPDFSVDEVU SIDE 121212122121212121111111112212122222112222111221112112212112212212 DIRECTION IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIOOOOOOOIOOIOOIOOIOOOOIOOIIOOIIO source: ; load TBN from tape bus (00) source: 100 changed: 100 step 6 100000000000000000000000000000000001111100000000100010100100110001 okay space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C toggle comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT BAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBAABBAAAAAAAAAAAAAABBBBBBBBAB LETTER ALPSLFMDEEMCBFRSPKLEMFHRSCJLJKUHPNMBBNNVVRKRHUTDJUKANJHBTPDFSVDEVU SIDE 121212122121212121111111112212122222112222111221112112212112212212 DIRECTION IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIOOOOOOOIOOIOOIOOIOOOOIOOIIOOIIO source: 0 changed: 0 step 7 100000000000000000000000000000000001111100000000000010100100110001 okay space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C toggle comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT BAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBAABBAAAAAAAAAAAAAABBBBBBBBAB LETTER ALPSLFMDEEMCBFRSPKLEMFHRSCJLJKUHPNMBBNNVVRKRHUTDJUKANJHBTPDFSVDEVU SIDE 121212122121212121111111112212122222112222111221112112212112212212 DIRECTION IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIOOOOOOOIOOIOOIOOIOOOOIOOIIOOIIO source: ; load TAC from tape bus (00) source: 10101 changed: 10101 step 8 100000000000000000000000000000000001111100000000000101010100110001 okay space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C toggle comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT BAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBAABBAAAAAAAAAAAAAABBBBBBBBAB LETTER ALPSLFMDEEMCBFRSPKLEMFHRSCJLJKUHPNMBBNNVVRKRHUTDJUKANJHBTPDFSVDEVU SIDE 121212122121212121111111112212122222112222111221112112212112212212 DIRECTION IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIOOOOOOOIOOIOOIOOIOOOOIOOIIOOIIO source: 0 changed: 0 step 9 100000000000000000000000000000000001111100000000000001010100110001 okay space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C toggle comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT BAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBAABBAAAAAAAAAAAAAABBBBBBBBAB LETTER ALPSLFMDEEMCBFRSPKLEMFHRSCJLJKUHPNMBBNNVVRKRHUTDJUKANJHBTPDFSVDEVU SIDE 121212122121212121111111112212122222112222111221112112212112212212 DIRECTION IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIOOOOOOOIOOIOOIOOIOOOOIOOIIOOIIO source: ; load TB from tape bus (00) source: 100 changed: 10 step 10 100000000000000000000000000000000001111100000000000001011000110001 okay space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C toggle comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT BAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBAABBAAAAAAAAAAAAAABBBBBBBBAB LETTER ALPSLFMDEEMCBFRSPKLEMFHRSCJLJKUHPNMBBNNVVRKRHUTDJUKANJHBTPDFSVDEVU SIDE 121212122121212121111111112212122222112222111221112112212112212212 DIRECTION IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIOOOOOOOIOOIOOIOOIOOOOIOOIIOOIIO source: 0 changed: 0 step 11 100000000000000000000000000000000001111100000000000001010000110001 okay space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C toggle comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT BAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBAABBAAAAAAAAAAAAAABBBBBBBBAB LETTER ALPSLFMDEEMCBFRSPKLEMFHRSCJLJKUHPNMBBNNVVRKRHUTDJUKANJHBTPDFSVDEVU SIDE 121212122121212121111111112212122222112222111221112112212112212212 DIRECTION IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIOOOOOOOIOOIOOIOOIOOOOIOOIIOOIIO source: ; load RWB from TB (JAMS CLEAR AND PRESET) source: 1 00 changed: 1 0 step 12 100000000000000000000000000000000001111100000000000001010001100001 okay space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C toggle comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT BAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBAABBAAAAAAAAAAAAAABBBBBBBBAB LETTER ALPSLFMDEEMCBFRSPKLEMFHRSCJLJKUHPNMBBNNVVRKRHUTDJUKANJHBTPDFSVDEVU SIDE 121212122121212121111111112212122222112222111221112112212112212212 DIRECTION IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIOOOOOOOIOOIOOIOOIOOOOIOOIIOOIIO source: 0 changed: 0 step 13 100000000000000000000000000000000001111100000000000001010000100001 okay space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C toggle comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT BAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBAABBAAAAAAAAAAAAAABBBBBBBBAB LETTER ALPSLFMDEEMCBFRSPKLEMFHRSCJLJKUHPNMBBNNVVRKRHUTDJUKANJHBTPDFSVDEVU SIDE 121212122121212121111111112212122222112222111221112112212112212212 DIRECTION IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIOOOOOOOIOOIOOIOOIOOOOIOOIIOOIIO source: ; (no change) source: 100000000000000000000000000000000001111100000000000001010000100001 changed: step 14 100000000000000000000000000000000001111100000000000001010000100001 okay space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C toggle comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT BAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBAABBAAAAAAAAAAAAAABBBBBBBBAB LETTER ALPSLFMDEEMCBFRSPKLEMFHRSCJLJKUHPNMBBNNVVRKRHUTDJUKANJHBTPDFSVDEVU SIDE 121212122121212121111111112212122222112222111221112112212112212212 DIRECTION IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIOOOOOOOIOOIOOIOOIOOOOIOOIIOOIIO source: source: source: ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; source: ; source: ; set all registers HIGH source: ; source: ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; source: source: ; set pin AF1 (AND with itself) to clear pin BB2 (AND-NOR output) and set pin BR2 TAPE BUS 3 OUTPUT source: 1 0 1 changed: 1 0 1 step 15 100000000000010000000000000000000000111101000000000001010000100001 okay space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C toggle comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT BAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBAABBAAAAAAAAAAAAAABBBBBBBBAB LETTER ALPSLFMDEEMCBFRSPKLEMFHRSCJLJKUHPNMBBNNVVRKRHUTDJUKANJHBTPDFSVDEVU SIDE 121212122121212121111111112212122222112222111221112112212112212212 DIRECTION IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIOOOOOOOIOOIOOIOOIOOOOIOOIIOOIIO source: ; set pin AP2 (AND with itself) to clear pin AN2 (AND-NOR output) and set pin BV2 TAPE BUS 2 OUTPUT source: 1 0 1 changed: 1 0 1 step 16 100000000000010010000000000000000000110111000000000001010000100001 okay space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C toggle comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT BAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBAABBAAAAAAAAAAAAAABBBBBBBBAB LETTER ALPSLFMDEEMCBFRSPKLEMFHRSCJLJKUHPNMBBNNVVRKRHUTDJUKANJHBTPDFSVDEVU SIDE 121212122121212121111111112212122222112222111221112112212112212212 DIRECTION IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIOOOOOOOIOOIOOIOOIOOOOIOOIIOOIIO source: source: source: ; load TMA SETUP from tape bus (11) source: 111 changed: 111 step 17 100000000000010010000000000000000000110111111000000001010000100001 okay space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C toggle comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit source: 0 changed: 0 step 18 100000000000010010000000000000000000110111011000000001010000100001 source: ; load TMA from tape bus (11) source: 111 changed: 111 step 19 100000000000010010000000000000000000110111011111000001010000100001 source: 0 changed: 0 step 20 100000000000010010000000000000000000110111011011000001010000100001 source: ; load TBN from tape bus (11) source: 111 changed: 111 step 21 100000000000010010000000000000000000110111011011111001010000100001 source: 0 changed: 0 step 22 100000000000010010000000000000000000110111011011011001010000100001 source: ; load TAC from tape bus (11) source: 11010 changed: 11010 step 23 100000000000010010000000000000000000110111011011011110100000100001 source: 0 changed: 0 step 24 100000000000010010000000000000000000110111011011011010100000100001 source: ; load TB from tape bus (11) source: 111 changed: 111 step 25 100000000000010010000000000000000000110111011011011010101110100001 source: 0 changed: 0 step 26 100000000000010010000000000000000000110111011011011010100110100001 source: ; load RWB from TB (JAMS CLEAR AND PRESET) source: 1 11 changed: 1 11 step 27 100000000000010010000000000000000000110111011011011010100111111001 source: 0 changed: 0 step 28 100000000000010010000000000000000000110111011011011010100110111001 source: ; clear pin AF1 (AND with itself) to set pin BB2 (AND-NOR output) and clear pin BR2 TAPE BUS 3 OUTPUT source: 0 1 0 changed: 0 1 0 step 29 100000000000000010000000000000000001110110011011011010100110111001 source: ; clear pin AP2 (AND with itself) to set pin AN2 (AND-NOR output) and clear pin BV2 TAPE BUS 2 OUTPUT source: 0 1 0 changed: 0 1 0 step 30 100000000000000000000000000000000001111100011011011010100110111001 source: ; (no change) source: 100000000000000000000000000000000001111100011011011010100110111001 changed: step 31 100000000000000000000000000000000001111100011011011010100110111001 source: source: source: ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; source: ; source: ; test AND-NOR logic source: ; source: ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; source: source: ; (all registers are HIGH) source: ; set all pins HIGH except ENABLES source: source: ; set pin AF2 HIGH source: 1 changed: 1 step 32 100001000000000000000000000000000001111100011011011010100110111001 source: ; set pin AM1 HIGH source: 1 changed: 1 step 33 100001100000000000000000000000000001111100011011011010100110111001 source: ; set pin AE1 HIGH source: 1 changed: 1 step 34 100001100100000000000000000000000001111100011011011010100110111001 source: ; set pin AM2 HIGH source: 1 changed: 1 step 35 100001100110000000000000000000000001111100011011011010100110111001 source: ; set pin AB2 HIGH source: 1 changed: 1 step 36 100001100110100000000000000000000001111100011011011010100110111001 source: ; set pin AS1 HIGH source: 1 changed: 1 step 37 100001100110100100000000000000000001111100011011011010100110111001 source: ; set pin BE1 HIGH source: 1 changed: 1 step 38 100001100110100100010000000000000001111100011011011010100110111001 source: ; set pin BM1 HIGH source: 1 changed: 1 step 39 100001100110100100011000000000000001111100011011011010100110111001 source: ; set pin BH1 HIGH source: 1 changed: 1 step 40 100001100110100100011010000000000001111100011011011010100110111001 source: ; set pin BR1 HIGH source: 1 changed: 1 step 41 100001100110100100011011000000000001111100011011011010100110111001 source: ; set pin BC1 HIGH source: 1 changed: 1 step 42 100001100110100100011011010000000001111100011011011010100110111001 source: ; set pin BJ2 HIGH source: 1 changed: 1 step 43 100001100110100100011011011000000001111100011011011010100110111001 source: ; set pin BJ1 HIGH source: 1 changed: 1 step 44 100001100110100100011011011010000001111100011011011010100110111001 source: ; set pin BK2 HIGH source: 1 changed: 1 step 45 100001100110100100011011011011000001111100011011011010100110111001 source: ; set pin BH2 HIGH source: 1 changed: 1 step 46 100001100110100100011011011011010001111100011011011010100110111001 source: ; set pin BP2 HIGH source: 1 changed: 1 step 47 100001100110100100011011011011011001111100011011011010100110111001 source: ; set pin BN2 HIGH source: 1 changed: 1 step 48 100001100110100100011011011011011101111100011011011010100110111001 source: ; toggle each ENABLE source: source: ; set pin AL2 to clear pin BB2 and pin AN2 AND-NOR OUTPUTS and set TAPE BUS 2 OUTPUT and TAPE BUS 3 OUTPUT source: 1 0 0 11 changed: 1 0 0 11 step 49 110001100110100100011011011011011100110111011011011010100110111001 source: 0 1 1 00 changed: 0 1 1 00 step 50 100001100110100100011011011011011101111100011011011010100110111001 source: ; set pin AP1 to clear pin BB2 and pin AN2 AND-NOR OUTPUTS and set TAPE BUS 2 OUTPUT and TAPE BUS 3 OUTPUT source: 1 0 0 11 changed: 1 0 0 11 step 51 101001100110100100011011011011011100110111011011011010100110111001 source: 0 1 1 00 changed: 0 1 1 00 step 52 100001100110100100011011011011011101111100011011011010100110111001 source: ; set pin AS2 to clear pin BB2 and pin AN2 AND-NOR OUTPUTS and set TAPE BUS 2 OUTPUT and TAPE BUS 3 OUTPUT source: 1 0 0 11 changed: 1 0 0 11 step 53 100101100110100100011011011011011100110111011011011010100110111001 source: 0 1 1 00 changed: 0 1 1 00 step 54 100001100110100100011011011011011101111100011011011010100110111001 source: ; set pin AL1 to clear pin BB2 and pin AN2 AND-NOR OUTPUTS and set TAPE BUS 2 OUTPUT and TAPE BUS 3 OUTPUT source: 1 0 0 11 changed: 1 0 0 11 step 55 100011100110100100011011011011011100110111011011011010100110111001 source: 0 1 1 00 changed: 0 1 1 00 step 56 100001100110100100011011011011011101111100011011011010100110111001 source: ; set pin AL1 to clear pin BB2 and pin AN2 AND-NOR OUTPUTS and set TAPE BUS 2 OUTPUT and TAPE BUS 3 OUTPUT source: 1 0 0 11 changed: 1 0 0 11 step 57 100001110110100100011011011011011100110111011011011010100110111001 source: 0 1 1 00 changed: 0 1 1 00 step 58 100001100110100100011011011011011101111100011011011010100110111001 source: ; set pin AE2 to clear pin BB2 and pin AN2 AND-NOR OUTPUTS and set TAPE BUS 2 OUTPUT and TAPE BUS 3 OUTPUT source: 1 0 0 11 changed: 1 0 0 11 step 59 100001101110100100011011011011011100110111011011011010100110111001 source: 0 1 1 00 changed: 0 1 1 00 step 60 100001100110100100011011011011011101111100011011011010100110111001 source: ; set pin AC1 to clear pin BB2 and set TAPE BUS 3 OUTPUT source: 1 0 1 changed: 1 0 1 step 61 100001100111100100011011011011011100111101011011011010100110111001 source: 0 1 0 changed: 0 1 0 step 62 100001100110100100011011011011011101111100011011011010100110111001 source: ; set pin AF1 to clear pin BB2 and set TAPE BUS 3 OUTPUT source: 1 0 1 changed: 1 0 1 step 63 100001100110110100011011011011011100111101011011011010100110111001 source: 0 1 0 changed: 0 1 0 step 64 100001100110100100011011011011011101111100011011011010100110111001 source: ; set pin AR2 to clear pin AN2 AND-NOR OUTPUTS and set TAPE BUS 2 OUTPUT source: 1 0 1 changed: 1 0 1 step 65 100001100110101100011011011011011101110110011011011010100110111001 source: 0 1 0 changed: 0 1 0 step 66 100001100110100100011011011011011101111100011011011010100110111001 source: ; set pin AP2 to clear pin AN2 AND-NOR OUTPUTS and set TAPE BUS 2 OUTPUT source: 1 0 1 changed: 1 0 1 step 67 100001100110100110011011011011011101110110011011011010100110111001 source: 0 1 0 changed: 0 1 0 step 68 100001100110100100011011011011011101111100011011011010100110111001 source: source: ; set pin BK1 to clear pin BB1 and pin BN1 AND-NOR OUTPUTS and set TAPE BUS 2 OUTPUT and TAPE BUS 3 OUTPUT source: 1 00 11 changed: 1 00 11 step 69 100001100110100101011011011011011101001111011011011010100110111001 source: 0 11 00 changed: 0 11 00 step 70 100001100110100100011011011011011101111100011011011010100110111001 source: ; set pin BL1 to clear pin BB1 and pin BN1 AND-NOR OUTPUTS and set TAPE BUS 2 OUTPUT and TAPE BUS 3 OUTPUT source: 1 00 11 changed: 1 00 11 step 71 100001100110100100111011011011011101001111011011011010100110111001 source: 0 11 00 changed: 0 11 00 step 72 100001100110100100011011011011011101111100011011011010100110111001 source: ; set pin BF1 to clear pin BB1 and pin BN1 AND-NOR OUTPUTS and set TAPE BUS 2 OUTPUT and TAPE BUS 3 OUTPUT source: 1 00 11 changed: 1 00 11 step 73 100001100110100100011111011011011101001111011011011010100110111001 source: 0 11 00 changed: 0 11 00 step 74 100001100110100100011011011011011101111100011011011010100110111001 source: ; set pin BS1 to clear pin BB1 and pin BN1 AND-NOR OUTPUTS and set TAPE BUS 2 OUTPUT and TAPE BUS 3 OUTPUT source: 1 00 11 changed: 1 00 11 step 75 100001100110100100011011111011011101001111011011011010100110111001 source: 0 11 00 changed: 0 11 00 step 76 100001100110100100011011011011011101111100011011011010100110111001 source: ; set pin BL2 to clear pin BB1 and pin BN1 AND-NOR OUTPUTS and set TAPE BUS 2 OUTPUT and TAPE BUS 3 OUTPUT source: 1 00 11 changed: 1 00 11 step 77 100001100110100100011011011111011101001111011011011010100110111001 source: 0 11 00 changed: 0 11 00 step 78 100001100110100100011011011011011101111100011011011010100110111001 source: ; set pin BU1 to clear pin BB1 and pin BN1 AND-NOR OUTPUTS and set TAPE BUS 2 OUTPUT and TAPE BUS 3 OUTPUT source: 1 00 11 changed: 1 00 11 step 79 100001100110100100011011011011111101001111011011011010100110111001 source: 0 11 00 changed: 0 11 00 step 80 100001100110100100011011011011011101111100011011011010100110111001 source: ; set pin BM2 to clear pin BB1 and TAPE BUS 3 OUTPUT source: 1 0 1 changed: 1 0 1 step 81 100001100110100100011011011011011111101110011011011010100110111001 source: 0 1 0 changed: 0 1 0 step 82 100001100110100100011011011011011101111100011011011010100110111001 test 1: pass SLOT BAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBAABBAAAAAAAAAAAAAABBBBBBBBAB LETTER ALPSLFMDEEMCBFRSPKLEMFHRSCJLJKUHPNMBBNNVVRKRHUTDJUKANJHBTPDFSVDEVU SIDE 121212122121212121111111112212122222112222111221112112212112212212 DIRECTION IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIOOOOOOOIOOIOOIOOIOOOOIOOIIOOIIO this fail all fails was hi 111111111111111111111111111111111111111111111111111111111111111 1 rising ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ ^^^^^^^^^^^^^^^^^^^^ ^^ falling vvvv vv v vv vvv v v v v vvvvv vvvvvvvvvvvvvvvvvv v v was lo 00000000000000000000000000000000000000 00000000000000000000 0000 total fails 0, total passes 1 space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C toggle comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit comment_flag is 0 space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C toggle comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit step 1 100000000000000000000000000000000001111100011011011010100110111001 step 2 100000000000000000000000000000000001111100100011011010100110111001 step 3 100000000000000000000000000000000001111100000011011010100110111001 step 4 100000000000000000000000000000000001111100000100011010100110111001 step 5 100000000000000000000000000000000001111100000000011010100110111001 step 6 100000000000000000000000000000000001111100000000100010100110111001 step 7 100000000000000000000000000000000001111100000000000010100110111001 step 8 100000000000000000000000000000000001111100000000000101010110111001 step 9 100000000000000000000000000000000001111100000000000001010110111001 step 10 100000000000000000000000000000000001111100000000000001011000111001 step 11 100000000000000000000000000000000001111100000000000001010000111001 step 12 100000000000000000000000000000000001111100000000000001010001100001 step 13 100000000000000000000000000000000001111100000000000001010000100001 step 14 100000000000000000000000000000000001111100000000000001010000100001 step 15 100000000000010000000000000000000000111101000000000001010000100001 step 16 100000000000010010000000000000000000110111000000000001010000100001 step 17 100000000000010010000000000000000000110111111000000001010000100001 step 18 100000000000010010000000000000000000110111011000000001010000100001 step 19 100000000000010010000000000000000000110111011111000001010000100001 step 20 100000000000010010000000000000000000110111011011000001010000100001 step 21 100000000000010010000000000000000000110111011011111001010000100001 step 22 100000000000010010000000000000000000110111011011011001010000100001 step 23 100000000000010010000000000000000000110111011011011110100000100001 step 24 100000000000010010000000000000000000110111011011011010100000100001 step 25 100000000000010010000000000000000000110111011011011010101110100001 step 26 100000000000010010000000000000000000110111011011011010100110100001 step 27 100000000000010010000000000000000000110111011011011010100111111001 step 28 100000000000010010000000000000000000110111011011011010100110111001 step 29 100000000000000010000000000000000001110110011011011010100110111001 step 30 100000000000000000000000000000000001111100011011011010100110111001 step 31 100000000000000000000000000000000001111100011011011010100110111001 step 32 100001000000000000000000000000000001111100011011011010100110111001 step 33 100001100000000000000000000000000001111100011011011010100110111001 step 34 100001100100000000000000000000000001111100011011011010100110111001 step 35 100001100110000000000000000000000001111100011011011010100110111001 step 36 100001100110100000000000000000000001111100011011011010100110111001 step 37 100001100110100100000000000000000001111100011011011010100110111001 step 38 100001100110100100010000000000000001111100011011011010100110111001 step 39 100001100110100100011000000000000001111100011011011010100110111001 step 40 100001100110100100011010000000000001111100011011011010100110111001 step 41 100001100110100100011011000000000001111100011011011010100110111001 step 42 100001100110100100011011010000000001111100011011011010100110111001 step 43 100001100110100100011011011000000001111100011011011010100110111001 step 44 100001100110100100011011011010000001111100011011011010100110111001 step 45 100001100110100100011011011011000001111100011011011010100110111001 step 46 100001100110100100011011011011010001111100011011011010100110111001 step 47 100001100110100100011011011011011001111100011011011010100110111001 step 48 100001100110100100011011011011011101111100011011011010100110111001 step 49 110001100110100100011011011011011100110111011011011010100110111001 step 50 100001100110100100011011011011011101111100011011011010100110111001 step 51 101001100110100100011011011011011100110111011011011010100110111001 step 52 100001100110100100011011011011011101111100011011011010100110111001 step 53 100101100110100100011011011011011100110111011011011010100110111001 step 54 100001100110100100011011011011011101111100011011011010100110111001 step 55 100011100110100100011011011011011100110111011011011010100110111001 step 56 100001100110100100011011011011011101111100011011011010100110111001 step 57 100001110110100100011011011011011100110111011011011010100110111001 step 58 100001100110100100011011011011011101111100011011011010100110111001 step 59 100001101110100100011011011011011100110111011011011010100110111001 step 60 100001100110100100011011011011011101111100011011011010100110111001 step 61 100001100111100100011011011011011100111101011011011010100110111001 step 62 100001100110100100011011011011011101111100011011011010100110111001 step 63 100001100110110100011011011011011100111101011011011010100110111001 step 64 100001100110100100011011011011011101111100011011011010100110111001 step 65 100001100110101100011011011011011101110110011011011010100110111001 step 66 100001100110100100011011011011011101111100011011011010100110111001 step 67 100001100110100110011011011011011101110110011011011010100110111001 step 68 100001100110100100011011011011011101111100011011011010100110111001 step 69 100001100110100101011011011011011101001111011011011010100110111001 step 70 100001100110100100011011011011011101111100011011011010100110111001 step 71 100001100110100100111011011011011101001111011011011010100110111001 step 72 100001100110100100011011011011011101111100011011011010100110111001 step 73 100001100110100100011111011011011101001111011011011010100110111001 step 74 100001100110100100011011011011011101111100011011011010100110111001 step 75 100001100110100100011011111011011101001111011011011010100110111001 step 76 100001100110100100011011011011011101111100011011011010100110111001 step 77 100001100110100100011011011111011101001111011011011010100110111001 step 78 100001100110100100011011011011011101111100011011011010100110111001 step 79 100001100110100100011011011011111101001111011011011010100110111001 step 80 100001100110100100011011011011011101111100011011011010100110111001 step 81 100001100110100100011011011011011111101110011011011010100110111001 step 82 100001100110100100011011011011011101111100011011011010100110111001 test 2: pass SLOT BAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBAABBAAAAAAAAAAAAAABBBBBBBBAB LETTER ALPSLFMDEEMCBFRSPKLEMFHRSCJLJKUHPNMBBNNVVRKRHUTDJUKANJHBTPDFSVDEVU SIDE 121212122121212121111111112212122222112222111221112112212112212212 DIRECTION IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIOOOOOOOIOOIOOIOOIOOOOIOOIIOOIIO this fail all fails was hi 111111111111111111111111111111111111111111111111111111111111111 1 rising ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ ^^^^^^^^^^^^^^^^^^^^ ^^ falling vvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvv vvvvvvvvvvvvvvvvvvvv vv was lo 00000000000000000000000000000000000000 00000000000000000000 0000 total fails 0, total passes 2 space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C toggle comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit step 1 100000000000000000000000000000000001111100011011011010100110111001 step 2 100000000000000000000000000000000001111100100011011010100110111001 step 3 100000000000000000000000000000000001111100000011011010100110111001 step 4 100000000000000000000000000000000001111100000100011010100110111001 step 5 100000000000000000000000000000000001111100000000011010100110111001 step 6 100000000000000000000000000000000001111100000000100010100110111001 step 7 100000000000000000000000000000000001111100000000000010100110111001 step 8 100000000000000000000000000000000001111100000000000101010110111001 step 9 100000000000000000000000000000000001111100000000000001010110111001 step 10 100000000000000000000000000000000001111100000000000001011000111001 step 11 100000000000000000000000000000000001111100000000000001010000111001 step 12 100000000000000000000000000000000001111100000000000001010001100001 step 13 100000000000000000000000000000000001111100000000000001010000100001 step 14 100000000000000000000000000000000001111100000000000001010000100001 step 15 100000000000010000000000000000000000111101000000000001010000100001 step 16 100000000000010010000000000000000000110111000000000001010000100001 step 17 100000000000010010000000000000000000110111111000000001010000100001 step 18 100000000000010010000000000000000000110111011000000001010000100001 step 19 100000000000010010000000000000000000110111011111000001010000100001 step 20 100000000000010010000000000000000000110111011011000001010000100001 step 21 100000000000010010000000000000000000110111011011111001010000100001 step 22 100000000000010010000000000000000000110111011011011001010000100001 step 23 100000000000010010000000000000000000110111011011011110100000100001 step 24 100000000000010010000000000000000000110111011011011010100000100001 step 25 100000000000010010000000000000000000110111011011011010101110100001 step 26 100000000000010010000000000000000000110111011011011010100110100001 step 27 100000000000010010000000000000000000110111011011011010100111111001 step 28 100000000000010010000000000000000000110111011011011010100110111001 step 29 100000000000000010000000000000000001110110011011011010100110111001 step 30 100000000000000000000000000000000001111100011011011010100110111001 step 31 100000000000000000000000000000000001111100011011011010100110111001 step 32 100001000000000000000000000000000001111100011011011010100110111001 step 33 100001100000000000000000000000000001111100011011011010100110111001 step 34 100001100100000000000000000000000001111100011011011010100110111001 step 35 100001100110000000000000000000000001111100011011011010100110111001 step 36 100001100110100000000000000000000001111100011011011010100110111001 step 37 100001100110100100000000000000000001111100011011011010100110111001 step 38 100001100110100100010000000000000001111100011011011010100110111001 step 39 100001100110100100011000000000000001111100011011011010100110111001 step 40 100001100110100100011010000000000001111100011011011010100110111001 step 41 100001100110100100011011000000000001111100011011011010100110111001 step 42 100001100110100100011011010000000001111100011011011010100110111001 step 43 100001100110100100011011011000000001111100011011011010100110111001 step 44 100001100110100100011011011010000001111100011011011010100110111001 step 45 100001100110100100011011011011000001111100011011011010100110111001 step 46 100001100110100100011011011011010001111100011011011010100110111001 step 47 100001100110100100011011011011011001111100011011011010100110111001 step 48 100001100110100100011011011011011101111100011011011010100110111001 step 49 110001100110100100011011011011011100110111011011011010100110111001 step 50 100001100110100100011011011011011101111100011011011010100110111001 step 51 101001100110100100011011011011011100110111011011011010100110111001 step 52 100001100110100100011011011011011101111100011011011010100110111001 step 53 100101100110100100011011011011011100110111011011011010100110111001 step 54 100001100110100100011011011011011101111100011011011010100110111001 step 55 100011100110100100011011011011011100110111011011011010100110111001 step 56 100001100110100100011011011011011101111100011011011010100110111001 step 57 100001110110100100011011011011011100110111011011011010100110111001 step 58 100001100110100100011011011011011101111100011011011010100110111001 step 59 100001101110100100011011011011011100110111011011011010100110111001 step 60 100001100110100100011011011011011101111100011011011010100110111001 step 61 100001100111100100011011011011011100111101011011011010100110111001 step 62 100001100110100100011011011011011101111100011011011010100110111001 step 63 100001100110110100011011011011011100111101011011011010100110111001 step 64 100001100110100100011011011011011101111100011011011010100110111001 step 65 100001100110101100011011011011011101110110011011011010100110111001 step 66 100001100110100100011011011011011101111100011011011010100110111001 step 67 100001100110100110011011011011011101110110011011011010100110111001 step 68 100001100110100100011011011011011101111100011011011010100110111001 step 69 100001100110100101011011011011011101001111011011011010100110111001 step 70 100001100110100100011011011011011101111100011011011010100110111001 step 71 100001100110100100111011011011011101001111011011011010100110111001 step 72 100001100110100100011011011011011101111100011011011010100110111001 step 73 100001100110100100011111011011011101001111011011011010100110111001 step 74 100001100110100100011011011011011101111100011011011010100110111001 step 75 100001100110100100011011111011011101001111011011011010100110111001 step 76 100001100110100100011011011011011101111100011011011010100110111001 step 77 100001100110100100011011011111011101001111011011011010100110111001 step 78 100001100110100100011011011011011101111100011011011010100110111001 step 79 100001100110100100011011011011111101001111011011011010100110111001 step 80 100001100110100100011011011011011101111100011011011010100110111001 step 81 100001100110100100011011011011011111101110011011011010100110111001 step 82 100001100110100100011011011011011101111100011011011010100110111001 test 3: pass SLOT BAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBAABBAAAAAAAAAAAAAABBBBBBBBAB LETTER ALPSLFMDEEMCBFRSPKLEMFHRSCJLJKUHPNMBBNNVVRKRHUTDJUKANJHBTPDFSVDEVU SIDE 121212122121212121111111112212122222112222111221112112212112212212 DIRECTION IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIOOOOOOOIOOIOOIOOIOOOOIOOIIOOIIO this fail all fails was hi 111111111111111111111111111111111111111111111111111111111111111 1 rising ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ ^^^^^^^^^^^^^^^^^^^^ ^^ falling vvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvv vvvvvvvvvvvvvvvvvvvv vv was lo 00000000000000000000000000000000000000 00000000000000000000 0000 total fails 0, total passes 3 space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C toggle comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit up to this point: PINS that are always low 64 I BE2 SHIFT RWB (SHIFTS PIN AV1 INTO RWB 3, SHIFTS RWB3 TO RWB2) (RISING CLOCK) 65 I AV1 RWB IN (SHIFTED INTO RWB 2) PINS that are always high 1 I BA1 CARRY IN-N, (TO E9-5 7482 C0) C-N TO ADDER2 40 O AV2 CARRY OUT-N (E9-10 7482 C2) 61 I BS2 PHASE (SELECTS POLARITY OF RWB OUT, 0 -> INVERTED) 66 O BU2 +3.5V space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C toggle comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit failure mode analysis: space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C toggle comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit scope (run, no print) ppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppp ppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppp ppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppp ppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppp ppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppp ppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppp ppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppp ppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppp ppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppp ppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppp ppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppp ppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppp ppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppp ppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppp ppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppp ppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppp ppppppppppppppppppppppppppppppppppppppppp space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C toggle comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT BAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBAABBAAAAAAAAAAAAAABBBBBBBBAB LETTER ALPSLFMDEEMCBFRSPKLEMFHRSCJLJKUHPNMBBNNVVRKRHUTDJUKANJHBTPDFSVDEVU SIDE 121212122121212121111111112212122222112222111221112112212112212212 DIRECTION IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIOOOOOOOIOOIOOIOOIOOOOIOOIIOOIIO all fails was lo 00000000000000000000000000000000000000 00000000000000000000 0000 falling vvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvv vvvvvvvvvvvvvvvvvvvv vv rising ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ ^^^^^^^^^^^^^^^^^^^^ ^^ was hi 111111111111111111111111111111111111111111111111111111111111111 1 total fails 0, total passes 1308 Main menu Sat Jul 11 11:39:14 2015 test file is: tests\m222.new delay is: 0 trigger is: 1 1 read test file 2 set test delay 3 set test trigger 4 run test 5 output loading test 8 diags 9 exit exiting tester- PDP8 card tester via printer port version 0.85 June 4, 2015 mapping[] is verified Main menu Sat Jul 11 12:05:37 2015 test file is: delay is: 0 trigger is: 1 1 read test file 2 set test delay 3 set test trigger 4 run test 5 output loading test 8 diags 9 exit Enter test file name? trying to open test file: tests\m220.tst reading test file: tests\m220.tst comment: M220 PCB REV ? SCHEMATIC REV C MAJOR REGISTERS comment: pins: PINS pins: 1 I BE2 E12-13 (ADD 01) BE2 TO ADDER3 A1 pins: 2 I BH2 E16-3 E12-3 AC ENABLE AC2 TO ADDER2 A2 AC3 TO ADDER3 A1 pins: 3 I BJ2 E16-5 E12-5 AC-N ENABLE AC2-N TO ADDER2 A2 AC3-N TO ADDER3 A1 pins: 4 I BF1 E16-10 E12-10 MQ ENABLE MQ2 TO ADDER2 A2 MQ3 TO ADDER3 A1 pins: 5 I BH1 E16-9 MQ2 (AND) ADDER2 A2 ADDER3 A1 pins: 6 I BN2 E12-9 MQ3 ADDER2 A2 ADDER3 A1 pins: 7 I BC1 E14-1 E15-1 SR ENABLE SR2 TO ADDER2 A2 SR3 TO ADDER3 A1 pins: 8 I BE1 E14-13 SR2 (AND) ADDER2 A2 pins: 9 I BD2 E15-13 SR3 (AND) ADDER3 A1 pins: 10 I BF2 SC ENABLE SC2 TO ADDER2 A2 SC3 TO ADDER3 A1 pins: 11 I BD1 E14-2 SC2 (AND) ADDER2 A2 pins: 12 I BN1 E15-2 SC3 (AND) ADDER3 A1 pins: 13 I BL1 E14-5 E15-5 DATA ENABLE DATA2 TO ADDER2 A2 DATA3 TO ADDER3 A1 pins: 14 I BM2 E14-4 DATA2 (AND) ADDER2 A2 pins: 15 I BP2 E15-4 DATA3 (AND) ADDER3 A1 pins: 16 I BL2 E14-10 E15-10 IO ENABLE IO2 TO ADDER2 A2 IO3 TO ADDER3 A1 pins: 17 I BK1 E14-9 IO2 (AND) ADDER2 A2 pins: 18 I BM1 E15-9 IO3 (AND) ADDER3 A1 pins: 19 I BP1 E17-13 MA ENABLE MA2 TO ADDER2 B2 pins: 20 I BR2 E18-13 (MA3 ENABLE) MA3 TO ADDER3 B1 pins: 21 I BS2 E17-3 E18-3 PC ENABLE PC2 TO ADDER2 B2 PC3 TO ADDER3 B1 pins: 22 I BU2 E17-5 MEM ENABLE MEM2 TO ADDER2 B2 pins: 23 I BR1 E17-4 MEM2 (AND) ADDER2 B2 pins: 24 I BV1 E18-5 (MEM3 ENABLE) MA3 TO ADDER3 B1 pins: 25 I BV2 E18-4 MEM3 (AND) ADDER3 B1 pins: 26 I BT2 E17-10 E18-10 DATA ADDR EN DADDR2 TO ADDER2 B2 DADDR3 TO ADDER3 B1 pins: 27 I BS1 E17-9 DADDR2 (AND) ADDER2 B2 pins: 28 I BU1 E18-9 DADDR3 (AND) ADDER3 B1 pins: 29 I BJ1 E13-5 CO ADDER3 C0 pins: 30 O BK2 E13-10 C2 ADDER2 C2 pins: 31 O AE2 E13-12 ADDER2 ADDER2 SUM2 pins: 32 O AF1 E13-1 ADDER3 ADDER3 SUM1 pins: 33 I AA1 E3-13 E5-13 AND MB2 TO BUS2 MB3 TO BUS3 pins: 34 I AD2 E1-1 E2-5 SHIFT RIGHT ADDER1 TO BUS2 ADDER2 TO BUS3 pins: 35 I AD1 E1-9 E2-9 SHIFT RIGHT TWICE ADDER0 TO BUS2 ADDER1 TO BUS3 pins: 36 I AB1 E1-10 ADDER0 (AND) BUS2 pins: 37 I AC1 E1-13 E2-10 ADDER1 (AND) BUS2 (AND) BUS3 pins: 38 I AH2 E3-8 E1-1 ADDER4 (AND) BUS2 (AND) BUS3 pins: 39 I AJ2 E3-6 ADDER5 (AND) BUS3 pins: 40 I AE1 E1-2 E2-3 NO SHIFT ADDER2 TO BUS2 ADDER3 TO BUS3 pins: 41 I AF2 E1-5 E2-13 SHIFT LEFT ADDER3 TO BUS2 ADDER4 TO BUS3 pins: 42 I AH1 E3-8 E5-8 SHIFT LEFT TWICE ADDER4 TO BUS2 ADDER5 TO BUS3 pins: 43 I AB2 R,Q TT LINE SHIFT-N TTLINE TO BUS2 ADDER3 TO BUS3 pins: 44 I BB2 E6-1 (TTLINE) (AND) BUS2 pins: 45 O AJ1 E1-8 (BUS 2) pins: 46 O AK2 E2-8 (BUS 3) pins: 47 I AK1 E4-3 E4-11 (MA LOAD) pins: 48 O AM1 E4-6 (MA2 Q-N) pins: 49 O AM2 E4-5 (MA2 Q) pins: 50 O AL1 E4-8 (MA3 Q-N) pins: 51 O AL2 E4-9 (MA3 Q) pins: 52 I AN2 E4-3 E4-11 (PC LOAD) pins: 53 O AR2 E9-6 (PC2 Q-N) pins: 54 O AP1 E9-5 (PC2 Q) pins: 55 O AP2 E9-8 (PC3 Q-N) pins: 56 O AN1 E9-9 (PC3 Q) pins: 57 I AR1 E8-3 E8-11 (MB LOAD) pins: 58 O AU2 E11-6 (BUFFERED MB2 Q-N) pins: 59 O AT2 E11-8 (BUFFERED MB2 Q) pins: 60 O AS1 E7-8 (BUFFERED MB3 Q-N) pins: 61 O AS2 E7-6 (BUFFERED MB3 Q) pins: 62 I AU1 E10-3 E10-11 (AC LOAD) pins: 63 O BB1 E10-6 (AC2 Q-N) pins: 64 O BA1 E10-5 (AC2 Q) pins: 65 O AV2 E10-8 (AC3 Q-N) pins: 66 O AV1 E10-9 (AC3 Q) pins: direction: IIIIIIIIIIIIIIIIIIIIIIIIIIIIIOOOIIIIIIIIIIIIOOIOOOOIOOOOIOOOOIOOOO comment: ; all registers are unknown comment: ; turn on C0, TT LINE SHIFT-N (C2,ADDER2,ADDER3 to 111) comment: ; with no ENABLES, BUS2,BUS3 is 11 test 1: 00000000000000000000000000001111000000000010110XXXX0XXXX0XXXX0XXXX comment: ; comment: ; test all registers using SHIFT RIGHT TWICE path comment: ; comment: ; use SHIFT RIGHT TWICE, ADDER0, ADDER1 to setup BUS2,BUS3 test 2: 111 00 comment: ; set all registers to 00 test 3: 11010110101101011010 test 4: 0 0 0 0 comment: ; set all registers to 01 test 5: 110 01 test 6: 1 011 011 011 01 test 7: 0 0 0 0 comment: ; set all registers to 11 test 8: 100 11 test 9: 10101101011010110101 test 10: 0 0 0 0 comment: ; set all registers to 01 test 11: 110 01 test 12: 110 110 110 110 test 13: 0 0 0 0 comment: ; set all registers to 00 test 14: 111 00 test 15: 11010110101101011010 test 16: 0 0 0 0 comment: ; remove SHIFT RIGHT TWICE, ADDER0, ADDER1 test 17: 000 11 test 18: 000000000000000000000000000011110000000000101101010010100101001010 comment: ; comment: ; same tests, but use SHIFT LEFT TWICE path comment: ; comment: ; use SHIFT LEFT TWICE, ADDER4, ADDER5 to setup BUS2,BUS3 test 19: 11 1 00 comment: ; set all registers to 00 test 20: 11010110101101011010 test 21: 0 0 0 0 comment: ; set all registers to 01 test 22: 10 1 01 test 23: 1 011 011 011 01 test 24: 0 0 0 0 comment: ; set all registers to 11 test 25: 00 1 11 test 26: 10101101011010110101 test 27: 0 0 0 0 comment: ; set all registers to 01 test 28: 10 1 01 test 29: 110 110 110 110 test 30: 0 0 0 0 comment: ; set all registers to 00 test 31: 11 1 00 test 32: 11010110101101011010 test 33: 0 0 0 0 comment: ; remove SHIFT LEFT TWICE, ADDER4, ADDER5 test 34: 00 0 11 test 35: 000000000000000000000000000011110000000000101101010010100101001010 comment: ; comment: ; change each register individually (only one bit changes per strobe) comment: ; comment: ; use SHIFT RIGHT TWICE, ADDER0, ADDER1 to setup BUS2,BUS3 comment: ; set each register to 00 test 36: 111 00 test 37: 1 test 38: 0 test 39: 1 test 40: 0 test 41: 1 test 42: 0 test 43: 1 test 44: 0 comment: ; set each register to 01 test 45: 110 01 test 46: 1 01 test 47: 0 test 48: 1 01 test 49: 0 test 50: 1 01 test 51: 0 test 52: 1 01 test 53: 0 comment: ; set each register to 11 test 54: 100 11 test 55: 101 test 56: 0 test 57: 101 test 58: 0 test 59: 101 test 60: 0 test 61: 101 test 62: 0 comment: ; set each register to 10 test 63: 101 10 test 64: 1 10 test 65: 0 test 66: 1 10 test 67: 0 test 68: 1 10 test 69: 0 test 70: 1 10 test 71: 0 comment: ; set each register to 00 test 72: 111 00 test 73: 110 test 74: 0 test 75: 110 test 76: 0 test 77: 110 test 78: 0 test 79: 110 test 80: 0 comment: ; all registers are 00 test 81: 000000000000000000000000000011110011100000100001010010100101001010 comment: ; comment: ; with all registers 00; change each register individually to 00,01,10,11 comment: ; comment: ; use SHIFT RIGHT TWICE, ADDER0, ADDER1 to setup BUS2,BUS3 comment: ; change each regster to 00 and back to 00 test 82: 111 1 test 83: 0 test 84: 111 1 test 85: 0 test 86: 111 1 test 87: 0 test 88: 111 1 test 89: 0 comment: ; change each register to 01 and back to 00 test 90: 110 01 test 91: 1 01 test 92: 0 test 93: 111 00 test 94: 1 10 test 95: 0 test 96: 110 01 test 97: 1 01 test 98: 0 test 99: 111 00 test 100: 1 10 test 101: 0 test 102: 110 01 test 103: 1 01 test 104: 0 test 105: 111 00 test 106: 1 10 test 107: 0 test 108: 110 01 test 109: 1 01 test 110: 0 test 111: 111 00 test 112: 1 10 test 113: 0 comment: ; change each register to 10 and back to 00 test 114: 101 10 test 115: 101 test 116: 0 test 117: 111 00 test 118: 110 test 119: 0 test 120: 101 10 test 121: 101 test 122: 0 test 123: 111 00 test 124: 110 test 125: 0 test 126: 101 10 test 127: 101 test 128: 0 test 129: 111 00 test 130: 110 test 131: 0 test 132: 101 10 test 133: 101 test 134: 0 test 135: 111 00 test 136: 110 test 137: 0 comment: ; change each register to 11 and back to 00 test 138: 100 11 test 139: 1110101 test 140: 0 test 141: 111 00 test 142: 11010 test 143: 0 test 144: 100 11 test 145: 10101 test 146: 0 test 147: 111 00 test 148: 11010 test 149: 0 test 150: 100 11 test 151: 10101 test 152: 0 test 153: 111 00 test 154: 11010 test 155: 0 test 156: 100 11 test 157: 10101 test 158: 0 test 159: 111 00 test 160: 11010 test 161: 0 comment: ; all registers are 00 test 162: 000000000000000000000000000011110011100000100001010010100101001010 comment: ; comment: ; with all registers 01; change each register individually to 00,01,10,11 comment: ; comment: ; use SHIFT RIGHT TWICE, ADDER0, ADDER1 to setup BUS2,BUS3 comment: ; set all registers to 01 test 163: 110 01 test 164: 11001110011100111001 test 165: 0 0 0 0 comment: ; all registers are 01 test 166: 000000000000000000000000000011110011000000100101001010010100101001 comment: ; use SHIFT RIGHT TWICE, ADDER0, ADDER1 to setup BUS2,BUS3 comment: ; set each register to 00 and back to 01 test 167: 111 00 test 168: 1 10 test 169: 0 test 170: 110 01 test 171: 1 01 test 172: 0 test 173: 111 00 test 174: 1 10 test 175: 0 test 176: 110 01 test 177: 1 01 test 178: 0 test 179: 111 00 test 180: 1 10 test 181: 0 test 182: 110 01 test 183: 1 01 test 184: 0 test 185: 111 00 test 186: 1 10 test 187: 0 test 188: 110 01 test 189: 1 01 test 190: 0 comment: ; set each register to 01 and back to 01 test 191: 1 test 192: 0 test 193: 1 test 194: 0 test 195: 1 test 196: 0 test 197: 1 test 198: 0 comment: ; set each register to 10 and back to 01 test 199: 101 10 test 200: 10110 test 201: 0 test 202: 110 01 test 203: 11001 test 204: 0 test 205: 101 10 test 206: 10110 test 207: 0 test 208: 110 01 test 209: 11001 test 210: 0 test 211: 101 10 test 212: 10110 test 213: 0 test 214: 110 01 test 215: 11001 test 216: 0 test 217: 101 10 test 218: 10110 test 219: 0 test 220: 110 01 test 221: 11001 test 222: 0 comment: ; set each register to 11 and back to 01 test 223: 100 11 test 224: 101 test 225: 0 test 226: 110 01 test 227: 110 test 228: 0 test 229: 100 11 test 230: 101 test 231: 0 test 232: 110 01 test 233: 110 test 234: 0 test 235: 100 11 test 236: 101 test 237: 0 test 238: 110 01 test 239: 110 test 240: 0 test 241: 100 11 test 242: 101 test 243: 0 test 244: 110 01 test 245: 110 test 246: 0 comment: ; all registers are 01 test 247: 000000000000000000000000000011110011000000100101001010010100101001 comment: ; comment: ; with all registers 10; change each register individually to 00,01,10,11 comment: ; comment: ; use SHIFT RIGHT TWICE, ADDER0, ADDER1 to setup BUS2,BUS3 comment: ; set all registers to 10 test 248: 101 10 test 249: 10110101101011010110 test 250: 0 0 0 0 comment: ; all registers are 10 test 251: 000000000000000000000000000011110010100000101000110001100011000110 comment: ; use SHIFT RIGHT TWICE, ADDER0, ADDER1 to setup BUS2,BUS3 comment: ; set each register to 00 and back to 10 test 252: 111 00 test 253: 110 test 254: 0 test 255: 101 10 test 256: 101 test 257: 0 test 258: 111 00 test 259: 110 test 260: 0 test 261: 101 10 test 262: 101 test 263: 0 test 264: 111 00 test 265: 110 test 266: 0 test 267: 101 10 test 268: 101 test 269: 0 test 270: 111 00 test 271: 110 test 272: 0 test 273: 101 10 test 274: 101 test 275: 0 comment: ; set each register to 01 and back to 10 test 276: 110 01 test 277: 11001 test 278: 0 test 279: 101 10 test 280: 10110 test 281: 0 test 282: 110 01 test 283: 11001 test 284: 0 test 285: 101 10 test 286: 10110 test 287: 0 test 288: 110 01 test 289: 11001 test 290: 0 test 291: 101 10 test 292: 10110 test 293: 0 test 294: 110 01 test 295: 11001 test 296: 0 test 297: 101 10 test 298: 10110 test 299: 0 comment: ; set each register to 10 and back to 10 test 300: 101 10 test 301: 1 test 302: 0 test 303: 1 test 304: 0 test 305: 1 test 306: 0 test 307: 1 test 308: 0 comment: ; set each register to 11 and back to 10 test 309: 100 11 test 310: 1 01 test 311: 0 test 312: 101 10 test 313: 1 10 test 314: 0 test 315: 100 11 test 316: 1 01 test 317: 0 test 318: 101 10 test 319: 1 10 test 320: 0 test 321: 100 11 test 322: 1 01 test 323: 0 test 324: 101 10 test 325: 1 10 test 326: 0 test 327: 100 11 test 328: 1 01 test 329: 0 test 330: 101 10 test 331: 1 10 test 332: 0 comment: ; all registers are 10 test 333: 000000000000000000000000000011110010000000101100110001100011000110 comment: ; comment: ; with all registers 11; change each register individually to 00,01,10,11 comment: ; comment: ; use SHIFT RIGHT TWICE, ADDER0, ADDER1 to setup BUS2,BUS3 comment: ; set all registers to 11 test 334: 100 11 test 335: 10101101011010110101 test 336: 0 0 0 0 comment: ; all registers are 11 test 337: 000000000000000000000000000011110010000000101100101001010010100101 comment: ; use SHIFT RIGHT TWICE, ADDER0, ADDER1 to setup BUS2,BUS3 comment: ; set each register to 00 and back to 11 test 338: 111 00 test 339: 11010 test 340: 0 test 341: 100 11 test 342: 10101 test 343: 0 test 344: 111 00 test 345: 11010 test 346: 0 test 347: 100 11 test 348: 10101 test 349: 0 test 350: 111 00 test 351: 11010 test 352: 0 test 353: 100 11 test 354: 10101 test 355: 0 test 356: 111 00 test 357: 11010 test 358: 0 test 359: 100 11 test 360: 10101 test 361: 0 comment: ; set each register to 01 and back to 11 test 362: 110 01 test 363: 110 test 364: 0 test 365: 100 11 test 366: 101 test 367: 0 test 368: 110 01 test 369: 110 test 370: 0 test 371: 100 11 test 372: 101 test 373: 0 test 374: 110 01 test 375: 110 test 376: 0 test 377: 100 11 test 378: 101 test 379: 0 test 380: 110 01 test 381: 110 test 382: 0 test 383: 100 11 test 384: 101 test 385: 0 comment: ; set each register to 10 and back to 11 test 386: 101 10 test 387: 1 10 test 388: 0 test 389: 100 11 test 390: 1 01 test 391: 0 test 392: 101 10 test 393: 1 10 test 394: 0 test 395: 100 11 test 396: 1 01 test 397: 0 test 398: 101 10 test 399: 1 10 test 400: 0 test 401: 100 11 test 402: 1 01 test 403: 0 test 404: 101 10 test 405: 1 10 test 406: 0 test 407: 100 11 test 408: 1 01 test 409: 0 comment: ; set each register to 11 and back to 11 test 410: 100 11 test 411: 1 test 412: 0 test 413: 100 1 test 414: 0 test 415: 100 1 test 416: 0 test 417: 100 1 test 418: 0 comment: ; all registers are 11 test 419: 000000000000000000000000000011110010000000101100101001010010100101 comment: ; use SHIFT RIGHT TWICE, ADDER0, ADDER1 to setup BUS2,BUS3 comment: ; set registers to 00 test 420: 111 00 test 421: 11010110101101011010 test 422: 0 0 0 0 comment: ; all registers are 00 test 423: 000000000000000000000000000011110011100000100001010010100101001010 comment: ; comment: ; now test each register using SHIFT LEFT TWICE/ADDER4/ADDER5 comment: comment: ; disable SHIFT RIGHT TWICE, ADDER0, ADDER1 test 424: 000 11 comment: ; use SHIFT LEFT TWICE, ADDER4, ADDER5 to set BUS2,BUS3 to 00 test 425: 11 1 00 comment: ; all registers are 00 test 426: 000000000000000000000000000011110000011001100001010010100101001010 comment: ; use SHIFT LEFT TWICE, ADDER4, ADDER5 to set BUS2,BUS3 to 00 comment: ; set each register to 00 test 427: 11 1 001 test 428: 0 test 429: 00 1 test 430: 0 test 431: 00 1 test 432: 0 test 433: 00 1 test 434: 0 test 435: 00 comment: ; set each register to 01 test 436: 10 1 01 test 437: 011 01 test 438: 0 test 439: 01 1 01 test 440: 0 test 441: 01 1 01 test 442: 0 test 443: 01 1 01 test 444: 0 comment: ; set each register to 11 test 445: 00 1 11 test 446: 11101 test 447: 0 test 448: 11 101 test 449: 0 test 450: 11 101 test 451: 0 test 452: 11 101 test 453: 0 comment: ; set each register to 10 test 454: 01 1 10 test 455: 101 10 test 456: 0 test 457: 10 1 10 test 458: 0 test 459: 10 1 10 test 460: 0 test 461: 10 1 10 test 462: 0 comment: ; set each register to 00 test 463: 11 1 00110 test 464: 0 test 465: 00 110 test 466: 0 test 467: 00 110 test 468: 0 test 469: 00 110 test 470: 0 test 471: 00 comment: ; all registers are 00 test 472: 000000000000000000000000000011110000011001100001010010100101001010 comment: ; comment: ; test AND/MB path comment: ; comment: ; set registers MA,PC,MB,AC to 00,00,11,00 comment: ; use SHIFT LEFT TWICE, ADDER4, ADDER5 to set BUS2,BUS3 to 00 test 473: 00 1 11 test 474: 10101 test 475: 0 test 476: 11 1 00 test 477: 1101011010 11010 test 478: 0 0 0 comment: ; use AND enable to setup BUS2,BUS3 to 11 comment: ; set MA,PC,xx,AC to 11 and back to 00 test 479: 11 0 11 test 480: 1 11 test 481: 10101 test 482: 0 test 483: 0 11 test 484: 11 1 00 test 485: 11010 test 486: 0 test 487: 11 0 11 test 488: 1 11 test 489: 10101 test 490: 0 test 491: 0 test 492: 11 1 00 test 493: 11010 test 494: 0 test 495: 11 0 11 test 496: 1 11 test 497: 1 test 498: 0 test 499: 10101 test 500: 0 test 501: 0 test 502: 11 1 00 test 503: 11010 test 504: 0 test 505: 11 0 11 comment: ; set registers MA,PC,MB,AC to 01,01,10,01 comment: ; use SHIFT LEFT TWICE, ADDER4, ADDER5 to set BUS2,BUS3 to 01 test 506: 01 1 10 test 507: 10110 test 508: 0 test 509: 10 1 01 test 510: 1100111001 11001 test 511: 0 0 0 comment: ; use AND enable to setup BUS2,BUS3 to 10 comment: ; set MA,PC,xx,AC to 10 and back to 01 test 512: 01 0 11 test 513: 1 10 test 514: 10110 test 515: 0 test 516: 0 11 test 517: 10 1 01 test 518: 11001 test 519: 0 test 520: 10 0 11 test 521: 1 10 test 522: 10110 test 523: 0 test 524: 0 11 test 525: 10 1 01 test 526: 11001 test 527: 0 test 528: 10 0 11 test 529: 1 10 test 530: 1 test 531: 0 test 532: 10110 test 533: 0 test 534: 0 11 test 535: 10 1 01 test 536: 11001 test 537: 0 test 538: 10 0 11 comment: ; set registers MA,PC,MB,AC to 10,10,01,10 comment: ; use SHIFT LEFT TWICE, ADDER4, ADDER5 to set BUS2,BUS3 to 01 test 539: 10 1 01 test 540: 11001 test 541: 0 test 542: 01 1 10 test 543: 1011010110 10110 test 544: 0 0 0 comment: ; use AND enable to setup BUS2,BUS3 to 01 comment: ; set MA,PC,xx,AC to 01 and back to 10 test 545: 01 0 11 test 546: 1 01 test 547: 11001 test 548: 0 test 549: 0 11 test 550: 01 1 10 test 551: 10110 test 552: 0 test 553: 01 0 11 test 554: 1 01 test 555: 11001 test 556: 0 test 557: 0 11 test 558: 01 1 10 test 559: 10110 test 560: 0 test 561: 01 0 11 test 562: 1 01 test 563: 1 test 564: 0 test 565: 11001 test 566: 0 test 567: 0 11 test 568: 01 1 10 test 569: 10110 test 570: 0 test 571: 01 0 11 comment: ; set registers MA,PC,MB,AC to 11,11,00,11 comment: ; use SHIFT LEFT TWICE, ADDER4, ADDER5 to set BUS2,BUS3 to 01 test 572: 11 1 00 test 573: 11010 test 574: 0 test 575: 00 1 11 test 576: 1010110101 10101 test 577: 0 0 0 comment: ; use AND enable to setup BUS2,BUS3 to 00 comment: ; set MA,PC,xx,AC to 00 and back to 11 test 578: 00 0 11 test 579: 1 00 test 580: 11010 test 581: 0 test 582: 0 11 test 583: 00 1 11 test 584: 10101 test 585: 0 test 586: 00 0 11 test 587: 1 00 test 588: 11010 test 589: 0 test 590: 0 11 test 591: 00 1 11 test 592: 10101 test 593: 0 test 594: 00 0 11 test 595: 1 00 test 596: 1 test 597: 0 test 598: 11010 test 599: 0 test 600: 0 11 test 601: 00 1 11 test 602: 10101 test 603: 0 test 604: 00 0 11 comment: comment: ; using SHIFT LEFT TWICE,ADDER4,ADDER5; set all registers to 00 test 605: 11 1 00 test 606: 11010110101101011010 test 607: 0 0 0 0 comment: ; disable SHIFT LEFT TWICE, ADDER4, ADDER5 test 608: 00 0 11 comment: ; all registers are 00 test 609: 000000000000000000000000000011110000000000101101010010100101001010 comment: ; comment: ; initial ADDER tests comment: ; comment: ; with no ENABLES, C0 HI, should have ADDER2,ADDER3,C2 test 610: 1111 comment: ; enable MQ ENABLE; toggle MQ2, MQ3 to ADDER2, ADDER3 test 611: 100 1111 test 612: 101 1110 test 613: 111 1100 test 614: 110 1101 test 615: 100 1111 comment: ; disable MQ ENABLE test 616: 0 1111 comment: ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; comment: ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; comment: ; need more ENABLE tests to isolate AND/OR errors comment: ; (should set all regsters to 11) comment: ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; comment: ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; comment: ; enable NO SHIFT to connect ADDER2,ADDER3 to BUS2,BUS3 test 617: 111 1100 1 11 test 618: 110 1101 1 10 test 619: 101 1110 1 01 test 620: 100 1111 1 00 comment: ; disable NO SHIFT test 621: 100 1111 0 11 comment: ; enable SHIFT RIGHT to connect ADDER1,ADDER2 to BUS2,BUS3 test 622: 100 1111 1 1 00 test 623: 101 1110 1 test 624: 110 1101 1 1 01 test 625: 111 1100 1 test 626: 111 1100 1 0 11 test 627: 110 1101 1 test 628: 101 1110 1 0 10 test 629: 100 1111 1 comment: ; disable SHIFT RIGHT test 630: 100 1111 0 11 comment: ; enable SHIFT RIGHT TWICE to connect ADDER0, ADDER1 to BUS2,BUS3 test 631: 111 00 test 632: 110 01 test 633: 101 10 test 634: 100 11 comment: ; disable SHIFT RIGHT TWICE test 635: 0 11 comment: ;enable SHIFT LEFT TWICE to connect ADDER4,ADDER5 to BUS2,BUS3 test 636: 11 1 00 test 637: 10 1 01 test 638: 01 1 10 test 639: 00 1 11 comment: ; disable SHIFT LEFT TWICE test 640: 0 11 comment: ; enable SHIFT LEFT to connect ADDER3,ADDER4 to BUS2,BUS3 test 641: 100 1111 1 1 00 test 642: 110 1101 1 test 643: 111 1100 1 1 10 test 644: 101 1110 1 test 645: 101 1110 0 1 11 test 646: 111 1100 1 test 647: 110 1101 0 1 01 test 648: 100 1111 1 comment: ; disable SHIFT LEFT test 649: 100 1111 0 11 test 650: 100 1111 1 comment: ; enable TT LINE SHIFT-N to connect TTLINE,ADDER3 to BUS2,BUS3 test 651: 100 1111 0100 test 652: 110 1101 0 test 653: 111 1100 0101 test 654: 101 1110 0 test 655: 101 1110 0011 test 656: 111 1100 0 test 657: 110 1101 0010 test 658: 100 1111 0 comment: ; disable TT LINE SHIFT-N test 659: 1111 1 11 comment: ; disable MQ ENABLE test 660: 0 test 661: 000000000000000000000000000011110000000000101101010010100101001010 comment: ; using SHIFT LEFT TWICE,ADDER4,ADDER5; set all registers to 00 test 662: 11 1 00 test 663: 11010110101101011010 test 664: 0 0 0 0 comment: ; disable SHIFT LEFT TWICE, ADDER4, ADDER5 test 665: 00 0 11 comment: ; all registers are 00 test 666: 000000000000000000000000000011110000000000101101010010100101001010 comment: ; set all registers to 00 test 667: 11 1 00 test 668: 11010110101101011010 test 669: 0 0 0 0 comment: ; disable SHIFT LEFT TWICE, ADDER4, ADDER5 test 670: 00 0 11 comment: ; all registers are 00 test 671: 000000000000000000000000000011110000000000101101010010100101001010 comment: ; use NO SHIFT to route ADDER2,ADDER3 to BUS2,BUS3 comment: ; toggle C0 test 672: 1111 1 00 test 673: 0110 1 01 test 674: 1111 1 00 comment: ; enable (add 01); toggle C0 test 675: 1 1110 1 01 test 676: 1 0101 1 10 test 677: 1 1110 1 01 test 678: 0 1111 1 00 comment: ; enable MQ ENABLE; toggle C0, MQ2, MQ3 test 679: 100 1111 1 00 test 680: 100 0110 1 01 test 681: 100 1111 1 00 test 682: 101 1110 1 01 test 683: 101 0101 1 10 test 684: 101 1110 1 01 test 685: 110 1101 1 10 test 686: 110 0100 1 11 test 687: 110 1101 1 10 test 688: 111 1100 1 11 test 689: 111 0011 1 00 test 690: 111 1100 1 11 test 691: 000 1111 1 00 comment: ; enable SR ENABLE; toggle C0, SR2, SR3 test 692: 100 1111 1 00 test 693: 100 0110 1 01 test 694: 100 1111 1 00 test 695: 101 1110 1 01 test 696: 101 0101 1 10 test 697: 101 1110 1 01 test 698: 110 1101 1 10 test 699: 110 0100 1 11 test 700: 110 1101 1 10 test 701: 111 1100 1 11 test 702: 111 0011 1 00 test 703: 111 1100 1 11 test 704: 000 1111 1 00 comment: ; enable SC ENABLE; toggel C0, SC2, SC3 test 705: 100 1111 1 00 test 706: 100 0110 1 01 test 707: 100 1111 1 00 test 708: 101 1110 1 01 test 709: 101 0101 1 10 test 710: 101 1110 1 01 test 711: 110 1101 1 10 test 712: 110 0100 1 11 test 713: 110 1101 1 10 test 714: 111 1100 1 11 test 715: 111 0011 1 00 test 716: 111 1100 1 11 test 717: 000 1111 1 00 comment: ; enable DATA ENABLE; toggle C0, DATA2, DATA3 test 718: 100 1111 1 00 test 719: 100 0110 1 01 test 720: 100 1111 1 00 test 721: 101 1110 1 01 test 722: 101 0101 1 10 test 723: 101 1110 1 01 test 724: 110 1101 1 10 test 725: 110 0100 1 11 test 726: 110 1101 1 10 test 727: 111 1100 1 11 test 728: 111 0011 1 00 test 729: 111 1100 1 11 test 730: 000 1111 1 00 comment: ; enable IO ENABLE; toggle C0, IO2, IO3 test 731: 100 1111 1 00 test 732: 100 0110 1 01 test 733: 100 1111 1 00 test 734: 101 1110 1 01 test 735: 101 0101 1 10 test 736: 101 1110 1 01 test 737: 110 1101 1 10 test 738: 110 0100 1 11 test 739: 110 1101 1 10 test 740: 111 1100 1 11 test 741: 111 0011 1 00 test 742: 111 1100 1 11 test 743: 000 1111 1 00 comment: ; enable MEM ENABLE; toggle C0, MEM2 test 744: 10 1111 1 00 test 745: 10 0110 1 01 test 746: 10 1111 1 00 test 747: 11 1101 1 10 test 748: 11 0100 1 11 test 749: 11 1101 1 10 test 750: 00 1111 1 00 comment: ; enable (MEM3 ENABLE); toggle C0, MEM3 test 751: 10 1111 1 00 test 752: 10 0110 1 01 test 753: 10 1111 1 00 test 754: 11 1110 1 01 test 755: 11 0101 1 10 test 756: 11 1110 1 01 test 757: 00 1111 1 00 comment: ; enable MEM ENABLE, (MEM3 ENABLE); toggle C0, MEM2, MEM3 test 758: 1010 1111 1 00 test 759: 1010 0110 1 01 test 760: 1010 1111 1 00 test 761: 1011 1110 1 01 test 762: 1011 0101 1 10 test 763: 1011 1110 1 01 test 764: 1110 1101 1 10 test 765: 1110 0100 1 11 test 766: 1110 1101 1 10 test 767: 1111 1100 1 11 test 768: 1111 0011 1 00 test 769: 1111 1100 1 11 test 770: 0000 1111 1 00 comment: ; enable DATA ADDR EN; toggle C0, DADDR2, DADDR3 test 771: 1001111 1 00 test 772: 1000110 1 01 test 773: 1001111 1 00 test 774: 1011110 1 01 test 775: 1010101 1 10 test 776: 1011110 1 01 test 777: 1101101 1 10 test 778: 1100100 1 11 test 779: 1101101 1 10 test 780: 1111100 1 11 test 781: 1110011 1 00 test 782: 1111100 1 11 test 783: 0001111 1 00 test 784: 000000000000000000000000000011110000000100100001010010100101001010 comment: ; turn on MQ2 (not enabled) test 785: 1 1111 1 00 comment: ; turn on MQ3 (not enabled) test 786: 1 1111 1 00 comment: ; turn on SR2 (not enabled) test 787: 1 1111 1 00 comment: ; turn on SR3 (not enabled) test 788: 1 1111 1 00 comment: ; turn on SC2 (not enabled) test 789: 1 1111 1 00 comment: ; turn on SC3 (not enabled) test 790: 1 1111 1 00 comment: ; turn on DATA2 (not enabled) test 791: 1 1111 1 00 comment: ; turn on DATA3 (not enabled) test 792: 1 1111 1 00 comment: ; turn on IO2 (not enabled) test 793: 1 1111 1 00 comment: ; turn on IO3 (not enabled) test 794: 1 1111 1 00 comment: ; turn on MEM2 (not enabled) test 795: 1 1111 1 00 comment: ; turn on MEM3 (not enabled) test 796: 1 1111 1 00 comment: ; turn on DADDR2 (not enabled) test 797: 1 1111 1 00 comment: ; turn on DADDR3 (not enabled) test 798: 11111 1 00 comment: ; turn on ADDER0 (not enabled) test 799: 1111 1 1 00 comment: ; turn on ADDER1 (not enabled) test 800: 1111 1 1 00 comment: ; turn on ADDER4 (not enabled) test 801: 1111 1 1 00 comment: ; turn on ADDER5 (not enabled) test 802: 1111 11 00 comment: ; turn on (TTLINE) (not enabled) test 803: 1111 1 100 comment: ; not enabled, signals hi test 804: 000011011011011011000010101111110001111100110001010010100101001010 comment: ; toggle C0 test 805: 1111 1 00 test 806: 0110 1 01 test 807: 1111 1 00 comment: ; enable (add 01); toggle C0 test 808: 1 1110 1 01 test 809: 1 0101 1 10 test 810: 1 1110 1 01 test 811: 0 1111 1 00 comment: ; enable MQ ENABLE; toggle C0, MQ2, MQ3 test 812: 100 1111 1 00 test 813: 100 0110 1 01 test 814: 100 1111 1 00 test 815: 101 1110 1 01 test 816: 101 0101 1 10 test 817: 101 1110 1 01 test 818: 110 1101 1 10 test 819: 110 0100 1 11 test 820: 110 1101 1 10 test 821: 111 1100 1 11 test 822: 111 0011 1 00 test 823: 111 1100 1 11 test 824: 0 1111 1 00 comment: ; enable SR ENABLE; toggle C0, SR2, SR3 test 825: 100 1111 1 00 test 826: 100 0110 1 01 test 827: 100 1111 1 00 test 828: 101 1110 1 01 test 829: 101 0101 1 10 test 830: 101 1110 1 01 test 831: 110 1101 1 10 test 832: 110 0100 1 11 test 833: 110 1101 1 10 test 834: 111 1100 1 11 test 835: 111 0011 1 00 test 836: 111 1100 1 11 test 837: 0 1111 1 00 comment: ; enable SC ENABLE; toggel C0, SC2, SC3 test 838: 100 1111 1 00 test 839: 100 0110 1 01 test 840: 100 1111 1 00 test 841: 101 1110 1 01 test 842: 101 0101 1 10 test 843: 101 1110 1 01 test 844: 110 1101 1 10 test 845: 110 0100 1 11 test 846: 110 1101 1 10 test 847: 111 1100 1 11 test 848: 111 0011 1 00 test 849: 111 1100 1 11 test 850: 0 1111 1 00 comment: ; enable DATA ENABLE; toggle C0, DATA2, DATA3 test 851: 100 1111 1 00 test 852: 100 0110 1 01 test 853: 100 1111 1 00 test 854: 101 1110 1 01 test 855: 101 0101 1 10 test 856: 101 1110 1 01 test 857: 110 1101 1 10 test 858: 110 0100 1 11 test 859: 110 1101 1 10 test 860: 111 1100 1 11 test 861: 111 0011 1 00 test 862: 111 1100 1 11 test 863: 0 1111 1 00 comment: ; enable IO ENABLE; toggle C0, IO2, IO3 test 864: 100 1111 1 00 test 865: 100 0110 1 01 test 866: 100 1111 1 00 test 867: 101 1110 1 01 test 868: 101 0101 1 10 test 869: 101 1110 1 01 test 870: 110 1101 1 10 test 871: 110 0100 1 11 test 872: 110 1101 1 10 test 873: 111 1100 1 11 test 874: 111 0011 1 00 test 875: 111 1100 1 11 test 876: 0 1111 1 00 comment: ; enable MEM ENABLE; toggle C0, MEM2 test 877: 10 1111 1 00 test 878: 10 0110 1 01 test 879: 10 1111 1 00 test 880: 11 1101 1 10 test 881: 11 0100 1 11 test 882: 11 1101 1 10 test 883: 0 1111 1 00 comment: ; enable (MEM3 ENABLE); toggle C0, MEM3 test 884: 10 1111 1 00 test 885: 10 0110 1 01 test 886: 10 1111 1 00 test 887: 11 1110 1 01 test 888: 11 0101 1 10 test 889: 11 1110 1 01 test 890: 0 1111 1 00 comment: ; enable MEM ENABLE, (MEM3 ENABLE); toggle C0, MEM2, MEM3 test 891: 1010 1111 1 00 test 892: 1010 0110 1 01 test 893: 1010 1111 1 00 test 894: 1011 1110 1 01 test 895: 1011 0101 1 10 test 896: 1011 1110 1 01 test 897: 1110 1101 1 10 test 898: 1110 0100 1 11 test 899: 1110 1101 1 10 test 900: 1111 1100 1 11 test 901: 1111 0011 1 00 test 902: 1111 1100 1 11 test 903: 0 0 1111 1 00 comment: ; enable DATA ADDR EN; toggle C0, DADDR2, DADDR3 test 904: 1001111 1 00 test 905: 1000110 1 01 test 906: 1001111 1 00 test 907: 1011110 1 01 test 908: 1010101 1 10 test 909: 1011110 1 01 test 910: 1101101 1 10 test 911: 1100100 1 11 test 912: 1101101 1 10 test 913: 1111100 1 11 test 914: 1110011 1 00 test 915: 1111100 1 11 test 916: 0 1111 1 00 comment: ; not enabled, signals hi test 917: 000011011011011011000010101111110011100100100001010010100101001010 comment: ; all registers are 00 test 918: 000000000000000000000000000011110000000000101101010010100101001010 comment: ; use SHIFT RIGHT TWICE, ADDER0, ADDER1 to setup BUS2,BUS3 comment: ; set registers MA,PC,MB,AC to 11,11,11,00 test 919: 100 11 test 920: 101011010110101 test 921: 0 0 0 test 922: 111 00 test 923: 11010 test 924: 0 test 925: 000 11 comment: ; use NO SHIFT to route ADDER2,ADDER3 to BUS2,BUS3 test 926: 1111 1 00 comment: ; enable AC ENABLE to ADDER2,ADDER3 test 927: 1 1111 1 00 test 928: 11010 test 929: 0 test 930: 11010 test 931: 0 test 932: 11010 test 933: 0 test 934: 1 test 935: 0 comment: ; disable AC ENABLE test 936: 0 1111 1 00 comment: ; enable AC ENABLE-N to ADDER2,ADDER3 test 937: 1 1100 1 11 test 938: 10101 test 939: 0 test 940: 10101 test 941: 0 test 942: 10101 test 943: 0 test 944: 1100 1 11 comment: ; note that ADDER2,ADDER3 and BUS2,BUS3 are the NEW values test 945: 1111 1 00 10101 test 946: 0 test 947: 1111 1 00 comment: ; note that ADDER2,ADDER3 and BUS2,BUS3 are the NEW values test 948: 1100 1 11 11010 test 949: 0 test 950: 1100 1 11 comment: ; note that ADDER2,ADDER3 and BUS2,BUS3 are the NEW values test 951: 1111 1 00 10101 test 952: 0 comment: ; disable AC ENABLE-N test 953: 0 1111 1 00 comment: ; disable NO SHIFT 0 11 comment: ; all registers are 11 test 954: 000000000000000000000000000011110000000000101100101001010010100101 comment: ; use SHIFT RIGHT TWICE, ADDER0, ADDER1 to setup BUS2,BUS3 comment: ; set registers MA,PC,MB,AC to 10,10,10,01 test 955: 101 10 test 956: 101101011010110 test 957: 0 0 0 test 958: 110 01 test 959: 11001 test 960: 0 test 961: 000 11 comment: ; use NO SHIFT to route ADDER2,ADDER3 to BUS2,BUS3 test 962: 1111 1 00 comment: ; enable AC ENABLE to ADDER2,ADDER3 test 963: 1 1110 1 01 test 964: 11001 test 965: 0 test 966: 11001 test 967: 0 test 968: 11001 test 969: 0 test 970: 1 test 971: 0 comment: ; disable AC ENABLE test 972: 0 1111 1 00 comment: ; enable AC ENABLE-N to ADDER2,ADDER3 test 973: 1 1101 1 10 test 974: 10110 test 975: 0 test 976: 10110 test 977: 0 test 978: 10110 test 979: 0 test 980: 1101 1 10 comment: ; note that ADDER2,ADDER3 and BUS2,BUS3 are the NEW values test 981: 1110 1 01 10110 test 982: 0 test 983: 1110 1 01 comment: ; note that ADDER2,ADDER3 and BUS2,BUS3 are the NEW values test 984: 1101 1 10 11001 test 985: 0 test 986: 1101 1 10 comment: ; note that ADDER2,ADDER3 and BUS2,BUS3 are the NEW values test 987: 1110 1 01 10110 comment: ; disable AC ENABLE-N test 988: 0 1111 1 00 comment: ; disable NO SHIFT 0 11 comment: ; all registers are 10 test 989: 000000000000000000000000000011110000000000101100110001100011000110 comment: ; use SHIFT RIGHT TWICE, ADDER0, ADDER1 to setup BUS2,BUS3 comment: ; set registers MA,PC,MB,AC to 01,01,01,10 test 990: 110 01 test 991: 110011100111001 test 992: 0 0 0 test 993: 101 10 test 994: 10110 test 995: 0 test 996: 000 11 comment: ; use NO SHIFT to route ADDER2,ADDER3 to BUS2,BUS3 test 997: 1111 1 00 comment: ; enable AC ENABLE to ADDER2,ADDER3 test 998: 1 1101 1 10 test 999: 10110 test 1000: 0 test 1001: 10110 test 1002: 0 test 1003: 10110 test 1004: 0 test 1005: 1 test 1006: 0 comment: ; disable AC ENABLE test 1007: 0 1111 1 00 comment: ; enable AC ENABLE-N to ADDER2,ADDER3 test 1008: 1 1110 1 01 test 1009: 11001 test 1010: 0 test 1011: 11001 test 1012: 0 test 1013: 11001 test 1014: 0 test 1015: 1110 1 01 comment: ; note that ADDER2,ADDER3 and BUS2,BUS3 are the NEW values test 1016: 1101 1 10 11001 test 1017: 0 test 1018: 1101 1 10 comment: ; note that ADDER2,ADDER3 and BUS2,BUS3 are the NEW values test 1019: 1110 1 01 10110 test 1020: 0 test 1021: 1110 1 01 comment: ; note that ADDER2,ADDER3 and BUS2,BUS3 are the NEW values test 1022: 1101 1 10 11001 comment: ; disable AC ENABLE-N test 1023: 0 1111 1 00 comment: ; disable NO SHIFT 0 11 comment: ; all registers are 01 test 1024: 000000000000000000000000000011110000000000101101001010010100101001 comment: ; use SHIFT RIGHT TWICE, ADDER0, ADDER1 to setup BUS2,BUS3 comment: ; set registers MA,PC,MB,AC to 00,00,00,11 test 1025: 111 00 test 1026: 110101101011010 test 1027: 0 0 0 test 1028: 100 11 test 1029: 10101 test 1030: 0 test 1031: 000 11 comment: ; use NO SHIFT to route ADDER2,ADDER3 to BUS2,BUS3 test 1032: 1111 1 00 comment: ; enable AC ENABLE to ADDER2,ADDER3 test 1033: 1 1100 1 11 test 1034: 10101 test 1035: 0 test 1036: 10101 test 1037: 0 test 1038: 10101 test 1039: 0 test 1040: 1 test 1041: 0 comment: ; disable AC ENABLE test 1042: 0 1111 1 00 comment: ; enable AC ENABLE-N to ADDER2,ADDER3 test 1043: 1 1111 1 00 test 1044: 11010 test 1045: 0 test 1046: 11010 test 1047: 0 test 1048: 11010 test 1049: 0 test 1050: 1111 1 00 comment: ; note that ADDER2,ADDER3 and BUS2,BUS3 are the NEW values test 1051: 1100 1 11 11010 test 1052: 0 test 1053: 1100 1 11 comment: ; note that ADDER2,ADDER3 and BUS2,BUS3 are the NEW values test 1054: 1111 1 00 10101 test 1055: 0 test 1056: 1111 1 00 comment: ; note that ADDER2,ADDER3 and BUS2,BUS3 are the NEW values test 1057: 1100 1 11 11010 test 1058: 0 comment: ; disable AC ENABLE-N test 1059: 0 1111 1 00 comment: ; disable NO SHIFT 0 11 comment: ; all registers are 00 test 1060: 000000000000000000000000000011110000000000101101010010100101001010 comment: ; comment: ; test MA ENABLES (they are separate) comment: ; comment: ; use SHIFT RIGHT TWICE, ADDER0, ADDER1 to setup BUS2,BUS3 comment: ; set registers MA,PC,MB,AC to 11,00,00,00 test 1061: 111 00 test 1062: 110101101011010 test 1063: 0 0 0 test 1064: 100 11 test 1065: 10101 test 1066: 0 comment: ; enable MA ENABLE/(MA3 ENABLE) to ADDER2/ADDER3 test 1067: 10 01 test 1068: 11 00 test 1069: 01 10 test 1070: 00 11 comment: ; set registers MA,PC,MB,AC to 01,10,10,10 test 1071: 101 10 test 1072: 101101011010110 test 1073: 0 0 0 test 1074: 110 01 test 1075: 11001 test 1076: 0 comment: ; enable MA ENABLE/(MA3 ENABLE) to ADDER2/ADDER3 test 1077: 10 11 test 1078: 11 10 test 1079: 01 10 test 1080: 00 11 comment: ; set registers MA,PC,MB,AC to 00,11,11,11 test 1081: 100 11 test 1082: 101011010110101 test 1083: 0 0 0 test 1084: 111 00 test 1085: 11010 test 1086: 0 comment: ; enable MA ENABLE/(MA3 ENABLE) to ADDER2/ADDER3 test 1087: 10 11 test 1088: 11 11 test 1089: 01 11 test 1090: 00 11 comment: ; set registers MA,PC,MB,AC to 10,01,01,01 test 1091: 110 01 test 1092: 110011100111001 test 1093: 0 0 0 test 1094: 101 10 test 1095: 10110 test 1096: 0 comment: ; enable MA ENABLE/(MA3 ENABLE) to ADDER2/ADDER3 test 1097: 10 01 test 1098: 11 01 test 1099: 01 11 test 1100: 00 11 comment: ; set registers MA,PC,MB,AC to 00,00,00,00 test 1101: 111 00 test 1102: 11010110101101011010 test 1103: 0 0 0 0 comment: ; disable SHIFT RIGHT TWICE/ADDER0/ADDER1 test 1104: 000 11 comment: ; all registers are 00 test 1105: 000000000000000000000000000011110000000000101101010010100101001010 comment: ; comment: ; test PC ENABLE comment: ; comment: ; use SHIFT RIGHT TWICE, ADDER0, ADDER1 to setup BUS2,BUS3 comment: ; set registers MA,PC,MB,AC to 00,11,00,00 test 1106: 111 00 test 1107: 11010 1101011010 test 1108: 0 0 0 test 1109: 100 11 test 1110: 10101 test 1111: 0 comment: ; enable PC ENABLE to ADDER2/ADDER3 test 1112: 1 00 test 1113: 0 11 comment: ; set registers MA,PC,MB,AC to 10,01,10,10 test 1114: 101 10 test 1115: 10110 1011010110 test 1116: 0 0 0 test 1117: 110 01 test 1118: 11001 test 1119: 0 comment: ; enable PC ENABLE to ADDER2/ADDER3 test 1120: 1 10 test 1121: 0 11 comment: ; set registers MA,PC,MB,AC to 11,00,11,11 test 1122: 100 11 test 1123: 10101 1010110101 test 1124: 0 0 0 test 1125: 111 00 test 1126: 11010 test 1127: 0 comment: ; enable PC ENABLE to ADDER2/ADDER3 test 1128: 1 11 test 1129: 0 11 comment: ; set registers MA,PC,MB,AC to 01,10,01,01 test 1130: 110 01 test 1131: 11001 1100111001 test 1132: 0 0 0 test 1133: 101 10 test 1134: 10110 test 1135: 0 comment: ; enable PC ENABLE to ADDER2/ADDER3 test 1136: 1 01 test 1137: 0 11 comment: ; set registers MA,PC,MB,AC to 00,00,00,00 test 1138: 111 00 test 1139: 11010110101101011010 test 1140: 0 0 0 0 comment: ; disable SHIFT RIGHT TWICE/ADDER0/ADDER1 test 1141: 000 11 comment: ; all registers are 00 test 1142: 000000000000000000000000000011110000000000101101010010100101001010 comment: ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; comment: ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; comment: ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; comment: ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; comment: ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; comment: ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; comment: ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; comment: ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; comment: ; comment: ; still need comment: ; comment: ; more adder tests comment: ; comment: ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; comment: ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; comment: ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; comment: ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; comment: ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; comment: ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; comment: ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; comment: ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; end: END summary column 1: offset 2, mask 0x0040 column 2: offset 3, mask 0x0001 column 3: offset 3, mask 0x0002 column 4: offset 2, mask 0x0100 column 5: offset 3, mask 0x8000 column 6: offset 3, mask 0x0020 column 7: offset 2, mask 0x0800 column 8: offset 2, mask 0x0200 column 9: offset 2, mask 0x0020 column 10: offset 2, mask 0x0080 column 11: offset 2, mask 0x0400 column 12: offset 3, mask 0x0400 column 13: offset 3, mask 0x1000 column 14: offset 3, mask 0x0010 column 15: offset 3, mask 0x0040 column 16: offset 3, mask 0x0008 column 17: offset 3, mask 0x2000 column 18: offset 3, mask 0x0800 column 19: offset 3, mask 0x0200 column 20: offset 3, mask 0x0080 column 21: offset 4, mask 0x0001 column 22: offset 4, mask 0x0004 column 23: offset 3, mask 0x0100 column 24: offset 4, mask 0x1000 column 25: offset 4, mask 0x0008 column 26: offset 4, mask 0x0002 column 27: offset 4, mask 0x8000 column 28: offset 4, mask 0x2000 column 29: offset 3, mask 0x4000 column 30: offset 3, mask 0x0004 column 31: offset 0, mask 0x0008 column 32: offset 0, mask 0x0400 column 33: offset 0, mask 0x8000 column 34: offset 0, mask 0x0010 column 35: offset 0, mask 0x1000 column 36: offset 0, mask 0x4000 column 37: offset 0, mask 0x2000 column 38: offset 0, mask 0x0002 column 39: offset 0, mask 0x0001 column 40: offset 0, mask 0x0800 column 41: offset 0, mask 0x0004 column 42: offset 0, mask 0x0200 column 43: offset 0, mask 0x0040 column 44: offset 2, mask 0x0008 column 45: offset 0, mask 0x0100 column 46: offset 1, mask 0x0001 column 47: offset 1, mask 0x8000 column 48: offset 1, mask 0x2000 column 49: offset 1, mask 0x0004 column 50: offset 1, mask 0x4000 column 51: offset 1, mask 0x0002 column 52: offset 1, mask 0x0008 column 53: offset 1, mask 0x0020 column 54: offset 1, mask 0x0800 column 55: offset 1, mask 0x0010 column 56: offset 1, mask 0x1000 column 57: offset 1, mask 0x0400 column 58: offset 2, mask 0x0001 column 59: offset 1, mask 0x0080 column 60: offset 1, mask 0x0200 column 61: offset 1, mask 0x0040 column 62: offset 2, mask 0x8000 column 63: offset 2, mask 0x1000 column 64: offset 2, mask 0x2000 column 65: offset 2, mask 0x0002 column 66: offset 2, mask 0x4000 direction bits (1=input) 0x05A8 0x7BF7 0x7013 0x0004 0x40F0 pullup bits (1=pullup) 0x0000 0x0000 0x0000 0x0000 0x0000 test step out_data dont care 1: 0x0548 0x0001 0x0000 0x4004 0x0000 0x0000 0x7AF6 0x7003 0x0000 0x0000 2: 0x7448 0x0000 0x0000 0x4004 0x0000 0x0000 0x7AF6 0x7003 0x0000 0x0000 3: 0x7448 0xE638 0x9003 0x4004 0x0000 4: 0x7448 0x6230 0x1003 0x4004 0x0000 5: 0x5448 0x6231 0x1003 0x4004 0x0000 6: 0x5448 0xB46B 0xD001 0x4004 0x0000 7: 0x5448 0x3063 0x5001 0x4004 0x0000 8: 0x1548 0x3063 0x5001 0x4004 0x0000 9: 0x1548 0x9CCF 0xE000 0x4004 0x0000 10: 0x1548 0x18C7 0x6000 0x4004 0x0000 11: 0x5448 0x18C7 0x6000 0x4004 0x0000 12: 0x5448 0xB46B 0xD001 0x4004 0x0000 13: 0x5448 0x3063 0x5001 0x4004 0x0000 14: 0x7448 0x3062 0x5001 0x4004 0x0000 15: 0x7448 0xE638 0x9003 0x4004 0x0000 16: 0x7448 0x6230 0x1003 0x4004 0x0000 17: 0x0548 0x6231 0x1003 0x4004 0x0000 18: 0x0548 0x6231 0x1003 0x4004 0x0000 19: 0x064B 0x6230 0x1003 0x4004 0x0000 20: 0x064B 0xE638 0x9003 0x4004 0x0000 21: 0x064B 0x6230 0x1003 0x4004 0x0000 22: 0x064A 0x6231 0x1003 0x4004 0x0000 23: 0x064A 0xB46B 0xD001 0x4004 0x0000 24: 0x064A 0x3063 0x5001 0x4004 0x0000 25: 0x0748 0x3063 0x5001 0x4004 0x0000 26: 0x0748 0x9CCF 0xE000 0x4004 0x0000 27: 0x0748 0x18C7 0x6000 0x4004 0x0000 28: 0x064A 0x18C7 0x6000 0x4004 0x0000 29: 0x064A 0xB46B 0xD001 0x4004 0x0000 30: 0x064A 0x3063 0x5001 0x4004 0x0000 31: 0x064B 0x3062 0x5001 0x4004 0x0000 32: 0x064B 0xE638 0x9003 0x4004 0x0000 33: 0x064B 0x6230 0x1003 0x4004 0x0000 34: 0x0548 0x6231 0x1003 0x4004 0x0000 35: 0x0548 0x6231 0x1003 0x4004 0x0000 36: 0x7448 0x6230 0x1003 0x4004 0x0000 37: 0x7448 0xE230 0x1003 0x4004 0x0000 38: 0x7448 0x6230 0x1003 0x4004 0x0000 39: 0x7448 0x6238 0x1003 0x4004 0x0000 40: 0x7448 0x6230 0x1003 0x4004 0x0000 41: 0x7448 0x6630 0x1003 0x4004 0x0000 42: 0x7448 0x6230 0x1003 0x4004 0x0000 43: 0x7448 0x6230 0x9003 0x4004 0x0000 44: 0x7448 0x6230 0x1003 0x4004 0x0000 45: 0x5448 0x6231 0x1003 0x4004 0x0000 46: 0x5448 0xA233 0x1003 0x4004 0x0000 47: 0x5448 0x2233 0x1003 0x4004 0x0000 48: 0x5448 0x322B 0x1003 0x4004 0x0000 49: 0x5448 0x3223 0x1003 0x4004 0x0000 50: 0x5448 0x3463 0x1003 0x4004 0x0000 51: 0x5448 0x3063 0x1003 0x4004 0x0000 52: 0x5448 0x3063 0xD001 0x4004 0x0000 53: 0x5448 0x3063 0x5001 0x4004 0x0000 54: 0x1548 0x3063 0x5001 0x4004 0x0000 55: 0x1548 0x9067 0x5001 0x4004 0x0000 56: 0x1548 0x1067 0x5001 0x4004 0x0000 57: 0x1548 0x184F 0x5001 0x4004 0x0000 58: 0x1548 0x1847 0x5001 0x4004 0x0000 59: 0x1548 0x1CC7 0x5000 0x4004 0x0000 60: 0x1548 0x18C7 0x5000 0x4004 0x0000 61: 0x1548 0x18C7 0xE000 0x4004 0x0000 62: 0x1548 0x18C7 0x6000 0x4004 0x0000 63: 0x3548 0x18C6 0x6000 0x4004 0x0000 64: 0x3548 0xD8C4 0x6000 0x4004 0x0000 65: 0x3548 0x58C4 0x6000 0x4004 0x0000 66: 0x3548 0x48DC 0x6000 0x4004 0x0000 67: 0x3548 0x48D4 0x6000 0x4004 0x0000 68: 0x3548 0x4E94 0x6000 0x4004 0x0000 69: 0x3548 0x4A94 0x6000 0x4004 0x0000 70: 0x3548 0x4A94 0xA002 0x4004 0x0000 71: 0x3548 0x4A94 0x2002 0x4004 0x0000 72: 0x7448 0x4A94 0x2002 0x4004 0x0000 73: 0x7448 0xEA90 0x2002 0x4004 0x0000 74: 0x7448 0x6A90 0x2002 0x4004 0x0000 75: 0x7448 0x62B8 0x2002 0x4004 0x0000 76: 0x7448 0x62B0 0x2002 0x4004 0x0000 77: 0x7448 0x6630 0x2003 0x4004 0x0000 78: 0x7448 0x6230 0x2003 0x4004 0x0000 79: 0x7448 0x6230 0x9003 0x4004 0x0000 80: 0x7448 0x6230 0x1003 0x4004 0x0000 81: 0x7448 0x6230 0x1003 0x4004 0x0000 82: 0x7448 0xE230 0x1003 0x4004 0x0000 83: 0x7448 0x6230 0x1003 0x4004 0x0000 84: 0x7448 0x6238 0x1003 0x4004 0x0000 85: 0x7448 0x6230 0x1003 0x4004 0x0000 86: 0x7448 0x6630 0x1003 0x4004 0x0000 87: 0x7448 0x6230 0x1003 0x4004 0x0000 88: 0x7448 0x6230 0x9003 0x4004 0x0000 89: 0x7448 0x6230 0x1003 0x4004 0x0000 90: 0x5448 0x6231 0x1003 0x4004 0x0000 91: 0x5448 0xA233 0x1003 0x4004 0x0000 92: 0x5448 0x2233 0x1003 0x4004 0x0000 93: 0x7448 0x2232 0x1003 0x4004 0x0000 94: 0x7448 0xE230 0x1003 0x4004 0x0000 95: 0x7448 0x6230 0x1003 0x4004 0x0000 96: 0x5448 0x6231 0x1003 0x4004 0x0000 97: 0x5448 0x7229 0x1003 0x4004 0x0000 98: 0x5448 0x7221 0x1003 0x4004 0x0000 99: 0x7448 0x7220 0x1003 0x4004 0x0000 100: 0x7448 0x6238 0x1003 0x4004 0x0000 101: 0x7448 0x6230 0x1003 0x4004 0x0000 102: 0x5448 0x6231 0x1003 0x4004 0x0000 103: 0x5448 0x6471 0x1003 0x4004 0x0000 104: 0x5448 0x6071 0x1003 0x4004 0x0000 105: 0x7448 0x6070 0x1003 0x4004 0x0000 106: 0x7448 0x6630 0x1003 0x4004 0x0000 107: 0x7448 0x6230 0x1003 0x4004 0x0000 108: 0x5448 0x6231 0x1003 0x4004 0x0000 109: 0x5448 0x6231 0xD001 0x4004 0x0000 110: 0x5448 0x6231 0x5001 0x4004 0x0000 111: 0x7448 0x6230 0x5001 0x4004 0x0000 112: 0x7448 0x6230 0x9003 0x4004 0x0000 113: 0x7448 0x6230 0x1003 0x4004 0x0000 114: 0x3548 0x6230 0x1003 0x4004 0x0000 115: 0x3548 0xC234 0x1003 0x4004 0x0000 116: 0x3548 0x4234 0x1003 0x4004 0x0000 117: 0x7448 0x4234 0x1003 0x4004 0x0000 118: 0x7448 0xE230 0x1003 0x4004 0x0000 119: 0x7448 0x6230 0x1003 0x4004 0x0000 120: 0x3548 0x6230 0x1003 0x4004 0x0000 121: 0x3548 0x6A18 0x1003 0x4004 0x0000 122: 0x3548 0x6A10 0x1003 0x4004 0x0000 123: 0x7448 0x6A10 0x1003 0x4004 0x0000 124: 0x7448 0x6238 0x1003 0x4004 0x0000 125: 0x7448 0x6230 0x1003 0x4004 0x0000 126: 0x3548 0x6230 0x1003 0x4004 0x0000 127: 0x3548 0x66B0 0x1002 0x4004 0x0000 128: 0x3548 0x62B0 0x1002 0x4004 0x0000 129: 0x7448 0x62B0 0x1002 0x4004 0x0000 130: 0x7448 0x6630 0x1003 0x4004 0x0000 131: 0x7448 0x6230 0x1003 0x4004 0x0000 132: 0x3548 0x6230 0x1003 0x4004 0x0000 133: 0x3548 0x6230 0xA003 0x4004 0x0000 134: 0x3548 0x6230 0x2003 0x4004 0x0000 135: 0x7448 0x6230 0x2003 0x4004 0x0000 136: 0x7448 0x6230 0x9003 0x4004 0x0000 137: 0x7448 0x6230 0x1003 0x4004 0x0000 138: 0x1548 0x6231 0x1003 0x4004 0x0000 139: 0x1548 0x8237 0x1003 0x4004 0x0000 140: 0x1548 0x0237 0x1003 0x4004 0x0000 141: 0x7448 0x0236 0x1003 0x4004 0x0000 142: 0x7448 0xE230 0x1003 0x4004 0x0000 143: 0x7448 0x6230 0x1003 0x4004 0x0000 144: 0x1548 0x6231 0x1003 0x4004 0x0000 145: 0x1548 0x7A09 0x1003 0x4004 0x0000 146: 0x1548 0x7A01 0x1003 0x4004 0x0000 147: 0x7448 0x7A00 0x1003 0x4004 0x0000 148: 0x7448 0x6238 0x1003 0x4004 0x0000 149: 0x7448 0x6230 0x1003 0x4004 0x0000 150: 0x1548 0x6231 0x1003 0x4004 0x0000 151: 0x1548 0x64F1 0x1002 0x4004 0x0000 152: 0x1548 0x60F1 0x1002 0x4004 0x0000 153: 0x7448 0x60F0 0x1002 0x4004 0x0000 154: 0x7448 0x6630 0x1003 0x4004 0x0000 155: 0x7448 0x6230 0x1003 0x4004 0x0000 156: 0x1548 0x6231 0x1003 0x4004 0x0000 157: 0x1548 0x6231 0xE001 0x4004 0x0000 158: 0x1548 0x6231 0x6001 0x4004 0x0000 159: 0x7448 0x6230 0x6001 0x4004 0x0000 160: 0x7448 0x6230 0x9003 0x4004 0x0000 161: 0x7448 0x6230 0x1003 0x4004 0x0000 162: 0x7448 0x6230 0x1003 0x4004 0x0000 163: 0x5448 0x6231 0x1003 0x4004 0x0000 164: 0x5448 0xB46B 0xD001 0x4004 0x0000 165: 0x5448 0x3063 0x5001 0x4004 0x0000 166: 0x5448 0x3063 0x5001 0x4004 0x0000 167: 0x7448 0x3062 0x5001 0x4004 0x0000 168: 0x7448 0xF060 0x5001 0x4004 0x0000 169: 0x7448 0x7060 0x5001 0x4004 0x0000 170: 0x5448 0x7061 0x5001 0x4004 0x0000 171: 0x5448 0xB063 0x5001 0x4004 0x0000 172: 0x5448 0x3063 0x5001 0x4004 0x0000 173: 0x7448 0x3062 0x5001 0x4004 0x0000 174: 0x7448 0x207A 0x5001 0x4004 0x0000 175: 0x7448 0x2072 0x5001 0x4004 0x0000 176: 0x5448 0x2073 0x5001 0x4004 0x0000 177: 0x5448 0x306B 0x5001 0x4004 0x0000 178: 0x5448 0x3063 0x5001 0x4004 0x0000 179: 0x7448 0x3062 0x5001 0x4004 0x0000 180: 0x7448 0x3622 0x5001 0x4004 0x0000 181: 0x7448 0x3222 0x5001 0x4004 0x0000 182: 0x5448 0x3223 0x5001 0x4004 0x0000 183: 0x5448 0x3463 0x5001 0x4004 0x0000 184: 0x5448 0x3063 0x5001 0x4004 0x0000 185: 0x7448 0x3062 0x5001 0x4004 0x0000 186: 0x7448 0x3062 0x9003 0x4004 0x0000 187: 0x7448 0x3062 0x1003 0x4004 0x0000 188: 0x5448 0x3063 0x1003 0x4004 0x0000 189: 0x5448 0x3063 0xD001 0x4004 0x0000 190: 0x5448 0x3063 0x5001 0x4004 0x0000 191: 0x5448 0xB063 0x5001 0x4004 0x0000 192: 0x5448 0x3063 0x5001 0x4004 0x0000 193: 0x5448 0x306B 0x5001 0x4004 0x0000 194: 0x5448 0x3063 0x5001 0x4004 0x0000 195: 0x5448 0x3463 0x5001 0x4004 0x0000 196: 0x5448 0x3063 0x5001 0x4004 0x0000 197: 0x5448 0x3063 0xD001 0x4004 0x0000 198: 0x5448 0x3063 0x5001 0x4004 0x0000 199: 0x3548 0x3062 0x5001 0x4004 0x0000 200: 0x3548 0xD064 0x5001 0x4004 0x0000 201: 0x3548 0x5064 0x5001 0x4004 0x0000 202: 0x5448 0x5065 0x5001 0x4004 0x0000 203: 0x5448 0xB063 0x5001 0x4004 0x0000 204: 0x5448 0x3063 0x5001 0x4004 0x0000 205: 0x3548 0x3062 0x5001 0x4004 0x0000 206: 0x3548 0x285A 0x5001 0x4004 0x0000 207: 0x3548 0x2852 0x5001 0x4004 0x0000 208: 0x5448 0x2853 0x5001 0x4004 0x0000 209: 0x5448 0x306B 0x5001 0x4004 0x0000 210: 0x5448 0x3063 0x5001 0x4004 0x0000 211: 0x3548 0x3062 0x5001 0x4004 0x0000 212: 0x3548 0x36A2 0x5000 0x4004 0x0000 213: 0x3548 0x32A2 0x5000 0x4004 0x0000 214: 0x5448 0x32A3 0x5000 0x4004 0x0000 215: 0x5448 0x3463 0x5001 0x4004 0x0000 216: 0x5448 0x3063 0x5001 0x4004 0x0000 217: 0x3548 0x3062 0x5001 0x4004 0x0000 218: 0x3548 0x3062 0xA003 0x4004 0x0000 219: 0x3548 0x3062 0x2003 0x4004 0x0000 220: 0x5448 0x3063 0x2003 0x4004 0x0000 221: 0x5448 0x3063 0xD001 0x4004 0x0000 222: 0x5448 0x3063 0x5001 0x4004 0x0000 223: 0x1548 0x3063 0x5001 0x4004 0x0000 224: 0x1548 0x9067 0x5001 0x4004 0x0000 225: 0x1548 0x1067 0x5001 0x4004 0x0000 226: 0x5448 0x1067 0x5001 0x4004 0x0000 227: 0x5448 0xB063 0x5001 0x4004 0x0000 228: 0x5448 0x3063 0x5001 0x4004 0x0000 229: 0x1548 0x3063 0x5001 0x4004 0x0000 230: 0x1548 0x384B 0x5001 0x4004 0x0000 231: 0x1548 0x3843 0x5001 0x4004 0x0000 232: 0x5448 0x3843 0x5001 0x4004 0x0000 233: 0x5448 0x306B 0x5001 0x4004 0x0000 234: 0x5448 0x3063 0x5001 0x4004 0x0000 235: 0x1548 0x3063 0x5001 0x4004 0x0000 236: 0x1548 0x34E3 0x5000 0x4004 0x0000 237: 0x1548 0x30E3 0x5000 0x4004 0x0000 238: 0x5448 0x30E3 0x5000 0x4004 0x0000 239: 0x5448 0x3463 0x5001 0x4004 0x0000 240: 0x5448 0x3063 0x5001 0x4004 0x0000 241: 0x1548 0x3063 0x5001 0x4004 0x0000 242: 0x1548 0x3063 0xE001 0x4004 0x0000 243: 0x1548 0x3063 0x6001 0x4004 0x0000 244: 0x5448 0x3063 0x6001 0x4004 0x0000 245: 0x5448 0x3063 0xD001 0x4004 0x0000 246: 0x5448 0x3063 0x5001 0x4004 0x0000 247: 0x5448 0x3063 0x5001 0x4004 0x0000 248: 0x3548 0x3062 0x5001 0x4004 0x0000 249: 0x3548 0xCE9C 0xA002 0x4004 0x0000 250: 0x3548 0x4A94 0x2002 0x4004 0x0000 251: 0x3548 0x4A94 0x2002 0x4004 0x0000 252: 0x7448 0x4A94 0x2002 0x4004 0x0000 253: 0x7448 0xEA90 0x2002 0x4004 0x0000 254: 0x7448 0x6A90 0x2002 0x4004 0x0000 255: 0x3548 0x6A90 0x2002 0x4004 0x0000 256: 0x3548 0xCA94 0x2002 0x4004 0x0000 257: 0x3548 0x4A94 0x2002 0x4004 0x0000 258: 0x7448 0x4A94 0x2002 0x4004 0x0000 259: 0x7448 0x42BC 0x2002 0x4004 0x0000 260: 0x7448 0x42B4 0x2002 0x4004 0x0000 261: 0x3548 0x42B4 0x2002 0x4004 0x0000 262: 0x3548 0x4A9C 0x2002 0x4004 0x0000 263: 0x3548 0x4A94 0x2002 0x4004 0x0000 264: 0x7448 0x4A94 0x2002 0x4004 0x0000 265: 0x7448 0x4E14 0x2003 0x4004 0x0000 266: 0x7448 0x4A14 0x2003 0x4004 0x0000 267: 0x3548 0x4A14 0x2003 0x4004 0x0000 268: 0x3548 0x4E94 0x2002 0x4004 0x0000 269: 0x3548 0x4A94 0x2002 0x4004 0x0000 270: 0x7448 0x4A94 0x2002 0x4004 0x0000 271: 0x7448 0x4A94 0x9002 0x4004 0x0000 272: 0x7448 0x4A94 0x1002 0x4004 0x0000 273: 0x3548 0x4A94 0x1002 0x4004 0x0000 274: 0x3548 0x4A94 0xA002 0x4004 0x0000 275: 0x3548 0x4A94 0x2002 0x4004 0x0000 276: 0x5448 0x4A95 0x2002 0x4004 0x0000 277: 0x5448 0xAA93 0x2002 0x4004 0x0000 278: 0x5448 0x2A93 0x2002 0x4004 0x0000 279: 0x3548 0x2A92 0x2002 0x4004 0x0000 280: 0x3548 0xCA94 0x2002 0x4004 0x0000 281: 0x3548 0x4A94 0x2002 0x4004 0x0000 282: 0x5448 0x4A95 0x2002 0x4004 0x0000 283: 0x5448 0x52AD 0x2002 0x4004 0x0000 284: 0x5448 0x52A5 0x2002 0x4004 0x0000 285: 0x3548 0x52A4 0x2002 0x4004 0x0000 286: 0x3548 0x4A9C 0x2002 0x4004 0x0000 287: 0x3548 0x4A94 0x2002 0x4004 0x0000 288: 0x5448 0x4A95 0x2002 0x4004 0x0000 289: 0x5448 0x4C55 0x2003 0x4004 0x0000 290: 0x5448 0x4855 0x2003 0x4004 0x0000 291: 0x3548 0x4854 0x2003 0x4004 0x0000 292: 0x3548 0x4E94 0x2002 0x4004 0x0000 293: 0x3548 0x4A94 0x2002 0x4004 0x0000 294: 0x5448 0x4A95 0x2002 0x4004 0x0000 295: 0x5448 0x4A95 0xD000 0x4004 0x0000 296: 0x5448 0x4A95 0x5000 0x4004 0x0000 297: 0x3548 0x4A94 0x5000 0x4004 0x0000 298: 0x3548 0x4A94 0xA002 0x4004 0x0000 299: 0x3548 0x4A94 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0x5001 0x4006 0x0000 975: 0x0D40 0x5064 0x5001 0x4006 0x0000 976: 0x0D40 0x485C 0x5001 0x4006 0x0000 977: 0x0D40 0x4854 0x5001 0x4006 0x0000 978: 0x0D40 0x4E94 0x5000 0x4006 0x0000 979: 0x0D40 0x4A94 0x5000 0x4006 0x0000 980: 0x0D40 0x4A94 0x5000 0x4006 0x0000 981: 0x0848 0x4A95 0xA002 0x4006 0x0000 982: 0x0848 0x4A95 0x2002 0x4006 0x0000 983: 0x0848 0x4A95 0x2002 0x4006 0x0000 984: 0x0D40 0x4A94 0xD000 0x4006 0x0000 985: 0x0D40 0x4A94 0x5000 0x4006 0x0000 986: 0x0D40 0x4A94 0x5000 0x4006 0x0000 987: 0x0848 0x4A95 0xA002 0x4006 0x0000 988: 0x0C48 0x4A94 0xA002 0x4004 0x0000 989: 0x0548 0x4A95 0x2002 0x4004 0x0000 990: 0x5448 0x4A95 0x2002 0x4004 0x0000 991: 0x5448 0xB46B 0x2003 0x4004 0x0000 992: 0x5448 0x3063 0x2003 0x4004 0x0000 993: 0x3548 0x3062 0x2003 0x4004 0x0000 994: 0x3548 0x3062 0xA003 0x4004 0x0000 995: 0x3548 0x3062 0x2003 0x4004 0x0000 996: 0x0548 0x3063 0x2003 0x4004 0x0000 997: 0x0C48 0x3062 0x2003 0x4004 0x0000 998: 0x0D40 0x3062 0x2003 0x4005 0x0000 999: 0x0D40 0xD064 0x2003 0x4005 0x0000 1000: 0x0D40 0x5064 0x2003 0x4005 0x0000 1001: 0x0D40 0x485C 0x2003 0x4005 0x0000 1002: 0x0D40 0x4854 0x2003 0x4005 0x0000 1003: 0x0D40 0x4E94 0x2002 0x4005 0x0000 1004: 0x0D40 0x4A94 0x2002 0x4005 0x0000 1005: 0x0D40 0x4A94 0xA002 0x4005 0x0000 1006: 0x0D40 0x4A94 0x2002 0x4005 0x0000 1007: 0x0C48 0x4A94 0x2002 0x4004 0x0000 1008: 0x0848 0x4A95 0x2002 0x4006 0x0000 1009: 0x0848 0xAA93 0x2002 0x4006 0x0000 1010: 0x0848 0x2A93 0x2002 0x4006 0x0000 1011: 0x0848 0x32AB 0x2002 0x4006 0x0000 1012: 0x0848 0x32A3 0x2002 0x4006 0x0000 1013: 0x0848 0x3463 0x2003 0x4006 0x0000 1014: 0x0848 0x3063 0x2003 0x4006 0x0000 1015: 0x0848 0x3063 0x2003 0x4006 0x0000 1016: 0x0D40 0x3062 0xD001 0x4006 0x0000 1017: 0x0D40 0x3062 0x5001 0x4006 0x0000 1018: 0x0D40 0x3062 0x5001 0x4006 0x0000 1019: 0x0848 0x3063 0xA003 0x4006 0x0000 1020: 0x0848 0x3063 0x2003 0x4006 0x0000 1021: 0x0848 0x3063 0x2003 0x4006 0x0000 1022: 0x0D40 0x3062 0xD001 0x4006 0x0000 1023: 0x0C48 0x3062 0xD001 0x4004 0x0000 1024: 0x0548 0x3063 0x5001 0x4004 0x0000 1025: 0x7448 0x3062 0x5001 0x4004 0x0000 1026: 0x7448 0xE638 0x5001 0x4004 0x0000 1027: 0x7448 0x6230 0x5001 0x4004 0x0000 1028: 0x1548 0x6231 0x5001 0x4004 0x0000 1029: 0x1548 0x6231 0xE001 0x4004 0x0000 1030: 0x1548 0x6231 0x6001 0x4004 0x0000 1031: 0x0548 0x6231 0x6001 0x4004 0x0000 1032: 0x0C48 0x6230 0x6001 0x4004 0x0000 1033: 0x0940 0x6231 0x6001 0x4005 0x0000 1034: 0x0940 0x8237 0x6001 0x4005 0x0000 1035: 0x0940 0x0237 0x6001 0x4005 0x0000 1036: 0x0940 0x1A0F 0x6001 0x4005 0x0000 1037: 0x0940 0x1A07 0x6001 0x4005 0x0000 1038: 0x0940 0x1CC7 0x6000 0x4005 0x0000 1039: 0x0940 0x18C7 0x6000 0x4005 0x0000 1040: 0x0940 0x18C7 0xE000 0x4005 0x0000 1041: 0x0940 0x18C7 0x6000 0x4005 0x0000 1042: 0x0C48 0x18C6 0x6000 0x4004 0x0000 1043: 0x0C48 0x18C6 0x6000 0x4006 0x0000 1044: 0x0C48 0xF8C0 0x6000 0x4006 0x0000 1045: 0x0C48 0x78C0 0x6000 0x4006 0x0000 1046: 0x0C48 0x60F8 0x6000 0x4006 0x0000 1047: 0x0C48 0x60F0 0x6000 0x4006 0x0000 1048: 0x0C48 0x6630 0x6001 0x4006 0x0000 1049: 0x0C48 0x6230 0x6001 0x4006 0x0000 1050: 0x0C48 0x6230 0x6001 0x4006 0x0000 1051: 0x0940 0x6231 0x9003 0x4006 0x0000 1052: 0x0940 0x6231 0x1003 0x4006 0x0000 1053: 0x0940 0x6231 0x1003 0x4006 0x0000 1054: 0x0C48 0x6230 0xE001 0x4006 0x0000 1055: 0x0C48 0x6230 0x6001 0x4006 0x0000 1056: 0x0C48 0x6230 0x6001 0x4006 0x0000 1057: 0x0940 0x6231 0x9003 0x4006 0x0000 1058: 0x0940 0x6231 0x1003 0x4006 0x0000 1059: 0x0C48 0x6230 0x1003 0x4004 0x0000 1060: 0x0548 0x6231 0x1003 0x4004 0x0000 1061: 0x7448 0x6230 0x1003 0x4004 0x0000 1062: 0x7448 0x6638 0x9003 0x4004 0x0000 1063: 0x7448 0x6230 0x1003 0x4004 0x0000 1064: 0x1548 0x6231 0x1003 0x4004 0x0000 1065: 0x1548 0x8237 0x1003 0x4004 0x0000 1066: 0x1548 0x0237 0x1003 0x4004 0x0000 1067: 0x1540 0x0237 0x1003 0x4204 0x0000 1068: 0x1140 0x0237 0x1003 0x4284 0x0000 1069: 0x1148 0x0237 0x1003 0x4084 0x0000 1070: 0x1548 0x0237 0x1003 0x4004 0x0000 1071: 0x3548 0x0236 0x1003 0x4004 0x0000 1072: 0x3548 0x0E9E 0xA002 0x4004 0x0000 1073: 0x3548 0x0A96 0x2002 0x4004 0x0000 1074: 0x5448 0x0A97 0x2002 0x4004 0x0000 1075: 0x5448 0xAA93 0x2002 0x4004 0x0000 1076: 0x5448 0x2A93 0x2002 0x4004 0x0000 1077: 0x5448 0x2A93 0x2002 0x4204 0x0000 1078: 0x5048 0x2A93 0x2002 0x4284 0x0000 1079: 0x5048 0x2A93 0x2002 0x4084 0x0000 1080: 0x5448 0x2A93 0x2002 0x4004 0x0000 1081: 0x1548 0x2A93 0x2002 0x4004 0x0000 1082: 0x1548 0x3CCB 0xE000 0x4004 0x0000 1083: 0x1548 0x38C3 0x6000 0x4004 0x0000 1084: 0x7448 0x38C2 0x6000 0x4004 0x0000 1085: 0x7448 0xF8C0 0x6000 0x4004 0x0000 1086: 0x7448 0x78C0 0x6000 0x4004 0x0000 1087: 0x7448 0x78C0 0x6000 0x4204 0x0000 1088: 0x7448 0x78C0 0x6000 0x4284 0x0000 1089: 0x7448 0x78C0 0x6000 0x4084 0x0000 1090: 0x7448 0x78C0 0x6000 0x4004 0x0000 1091: 0x5448 0x78C1 0x6000 0x4004 0x0000 1092: 0x5448 0x7469 0xD001 0x4004 0x0000 1093: 0x5448 0x7061 0x5001 0x4004 0x0000 1094: 0x3548 0x7060 0x5001 0x4004 0x0000 1095: 0x3548 0xD064 0x5001 0x4004 0x0000 1096: 0x3548 0x5064 0x5001 0x4004 0x0000 1097: 0x3540 0x5064 0x5001 0x4204 0x0000 1098: 0x3540 0x5064 0x5001 0x4284 0x0000 1099: 0x3548 0x5064 0x5001 0x4084 0x0000 1100: 0x3548 0x5064 0x5001 0x4004 0x0000 1101: 0x7448 0x5064 0x5001 0x4004 0x0000 1102: 0x7448 0xE638 0x9003 0x4004 0x0000 1103: 0x7448 0x6230 0x1003 0x4004 0x0000 1104: 0x0548 0x6231 0x1003 0x4004 0x0000 1105: 0x0548 0x6231 0x1003 0x4004 0x0000 1106: 0x7448 0x6230 0x1003 0x4004 0x0000 1107: 0x7448 0xE630 0x9003 0x4004 0x0000 1108: 0x7448 0x6230 0x1003 0x4004 0x0000 1109: 0x1548 0x6231 0x1003 0x4004 0x0000 1110: 0x1548 0x7A09 0x1003 0x4004 0x0000 1111: 0x1548 0x7A01 0x1003 0x4004 0x0000 1112: 0x1140 0x7A01 0x1003 0x4004 0x0001 1113: 0x1548 0x7A01 0x1003 0x4004 0x0000 1114: 0x3548 0x7A00 0x1003 0x4004 0x0000 1115: 0x3548 0xDE84 0xA002 0x4004 0x0000 1116: 0x3548 0x5A84 0x2002 0x4004 0x0000 1117: 0x5448 0x5A85 0x2002 0x4004 0x0000 1118: 0x5448 0x52AD 0x2002 0x4004 0x0000 1119: 0x5448 0x52A5 0x2002 0x4004 0x0000 1120: 0x5048 0x52A5 0x2002 0x4004 0x0001 1121: 0x5448 0x52A5 0x2002 0x4004 0x0000 1122: 0x1548 0x52A5 0x2002 0x4004 0x0000 1123: 0x1548 0x94E7 0xE000 0x4004 0x0000 1124: 0x1548 0x10E7 0x6000 0x4004 0x0000 1125: 0x7448 0x10E6 0x6000 0x4004 0x0000 1126: 0x7448 0x00FE 0x6000 0x4004 0x0000 1127: 0x7448 0x00F6 0x6000 0x4004 0x0000 1128: 0x7448 0x00F6 0x6000 0x4004 0x0001 1129: 0x7448 0x00F6 0x6000 0x4004 0x0000 1130: 0x5448 0x00F7 0x6000 0x4004 0x0000 1131: 0x5448 0xA473 0xD001 0x4004 0x0000 1132: 0x5448 0x2073 0x5001 0x4004 0x0000 1133: 0x3548 0x2072 0x5001 0x4004 0x0000 1134: 0x3548 0x285A 0x5001 0x4004 0x0000 1135: 0x3548 0x2852 0x5001 0x4004 0x0000 1136: 0x3540 0x2852 0x5001 0x4004 0x0001 1137: 0x3548 0x2852 0x5001 0x4004 0x0000 1138: 0x7448 0x2852 0x5001 0x4004 0x0000 1139: 0x7448 0xE638 0x9003 0x4004 0x0000 1140: 0x7448 0x6230 0x1003 0x4004 0x0000 1141: 0x0548 0x6231 0x1003 0x4004 0x0000 1142: 0x0548 0x6231 0x1003 0x4004 0x0000 PINs used (in edge connector order) (G=ground,P=power) SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBB LETTER ABCDEFHJKLMNPRSTUVABCDEFHJKLMNPRSTUVABCDEFHJKLMNPRSTUVABCDEFHJKLMNPRSTUV SIDE 111111111111111111222222222222222222111111111111111111222222222222222222 USAGE IIIIIOIOIOOOOIOGIOPIGIOIIIOOOIOOOOOOOOIIIIIIIIIIIIIGIIPIGIIIIIOIIIIIIIII UUT has 45 inputs UUT has 21 outputs contains 66 pins/columns 0 pins are not used contains 1142 'test steps' M220 PCB REV ? SCHEMATIC REV C MAJOR REGISTERS PINS Main menu Sat Jul 11 12:05:46 2015 test file is: tests\m220.tst delay is: 0 trigger is: 1 1 read test file 2 set test delay 3 set test trigger 4 run test 5 output loading test 8 diags 9 exit UUT power is okay Sat Jul 11 12:05:49 2015 space single step O run once (one test, all steps) F run, stop on fail G go (run tests N run, stop on fail, no print S scope (run, no print) C toggle comment printout + increase speed (less delay) - decrease speed (more delay)(slower) Q quit test scope (run, no print) ppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppp ppppppppppppppppppppppppppppppppppppFpppppppppppppppppppppppppppppppppFpppppppp pppppppppppppppppppp space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C toggle comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit failure mode analysis: pin: 5 I BH1 E16-9 MQ2 (AND) ADDER2 A2 ADDER3 A1 SLOT BBBBBBBBBBBBBBBBBBBBBBBBBBBBBBAAAAAAAAAAAAABAAAAAAAAAAAAAAAAAABBAA LETTER EHJFHNCEDFDNLMPLKMPRSURVVTSUJKEFADDBCHJEFHBBJKKMMLLNRPPNRUTSSUBAVV SIDE 222112112211122211122211221112211211122121221211212221211221211121 DIRECTION IIIIIIIIIIIIIIIIIIIIIIIIIIIIIOOOIIIIIIIIIIIIOOIOOOOIOOOOIOOOOIOOOO fails LO: fails LO: fails HI: 11111 111 1 11 1 111 111 11 fails HI: 0000 00000000000000000000000 0 00000 000 0 0000 0000 000 0 pin: 33 I AA1 E3-13 E5-13 AND MB2 TO BUS2 MB3 TO BUS3 SLOT BBBBBBBBBBBBBBBBBBBBBBBBBBBBBBAAAAAAAAAAAAABAAAAAAAAAAAAAAAAAABBAA LETTER EHJFHNCEDFDNLMPLKMPRSURVVTSUJKEFADDBCHJEFHBBJKKMMLLNRPPNRUTSSUBAVV SIDE 222112112211122211122211221112211211122121221211212221211221211121 DIRECTION IIIIIIIIIIIIIIIIIIIIIIIIIIIIIOOOIIIIIIIIIIIIOOIOOOOIOOOOIOOOOIOOOO fails LO: fails LO: fails HI: 1 1111 111 1 11 1 111 111 11 fails HI: 0000 00000000000000000000000 0 00000 000 0 0000 0000 000 0 pin: 35 I AD1 E1-9 E2-9 SHIFT RIGHT TWICE ADDER0 TO BUS2 ADDER1 TO BUS3 SLOT BBBBBBBBBBBBBBBBBBBBBBBBBBBBBBAAAAAAAAAAAAABAAAAAAAAAAAAAAAAAABBAA LETTER EHJFHNCEDFDNLMPLKMPRSURVVTSUJKEFADDBCHJEFHBBJKKMMLLNRPPNRUTSSUBAVV SIDE 222112112211122211122211221112211211122121221211212221211221211121 DIRECTION IIIIIIIIIIIIIIIIIIIIIIIIIIIIIOOOIIIIIIIIIIIIOOIOOOOIOOOOIOOOOIOOOO fails LO: 1111 1 11 1 1 1 1 1 1 1 1 fails LO: 0000000000000000000000000000 00 0000000 0 0 00 00 0 00 0 00 0 fails HI: fails HI: pin: 47 I AK1 E4-3 E4-11 (MA LOAD) SLOT BBBBBBBBBBBBBBBBBBBBBBBBBBBBBBAAAAAAAAAAAAABAAAAAAAAAAAAAAAAAABBAA LETTER EHJFHNCEDFDNLMPLKMPRSURVVTSUJKEFADDBCHJEFHBBJKKMMLLNRPPNRUTSSUBAVV SIDE 222112112211122211122211221112211211122121221211212221211221211121 DIRECTION IIIIIIIIIIIIIIIIIIIIIIIIIIIIIOOOIIIIIIIIIIIIOOIOOOOIOOOOIOOOOIOOOO fails LO: fails LO: fails HI: 1 11111 111 1 1 1 111 111 11 fails HI: 0000 00000000000000000000000 0 00000 000 0 0000 0000 000 0 space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C toggle comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit up to this point: PINS that are always low PINS that are always high space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C toggle comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT BBBBBBBBBBBBBBBBBBBBBBBBBBBBBBAAAAAAAAAAAAABAAAAAAAAAAAAAAAAAABBAA LETTER EHJFHNCEDFDNLMPLKMPRSURVVTSUJKEFADDBCHJEFHBBJKKMMLLNRPPNRUTSSUBAVV SIDE 222112112211122211122211221112211211122121221211212221211221211121 DIRECTION IIIIIIIIIIIIIIIIIIIIIIIIIIIIIOOOIIIIIIIIIIIIOOIOOOOIOOOOIOOOOIOOOO all fails I I I I was lo 000000000000000000000000000000000000000000000000000000000000000000 falling vvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvv rising ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ was hi 111111111111111111111111111111111111111111111111111111111111111111 total fails 2, total passes 176 Main menu Sat Jul 11 12:08:06 2015 test file is: tests\m220.tst delay is: 0 trigger is: 1 1 read test file 2 set test delay 3 set test trigger 4 run test 5 output loading test 8 diags 9 exit UUT power is okay Sat Jul 11 12:08:12 2015 space single step O run once (one test, all steps) F run, stop on fail G go (run tests N run, stop on fail, no print S scope (run, no print) C toggle comment printout + increase speed (less delay) - decrease speed (more delay)(slower) Q quit test scope (run, no print) pppppppppppppppppppppppppp space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C toggle comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT BBBBBBBBBBBBBBBBBBBBBBBBBBBBBBAAAAAAAAAAAAABAAAAAAAAAAAAAAAAAABBAA LETTER EHJFHNCEDFDNLMPLKMPRSURVVTSUJKEFADDBCHJEFHBBJKKMMLLNRPPNRUTSSUBAVV SIDE 222112112211122211122211221112211211122121221211212221211221211121 DIRECTION IIIIIIIIIIIIIIIIIIIIIIIIIIIIIOOOIIIIIIIIIIIIOOIOOOOIOOOOIOOOOIOOOO all fails was lo 000000000000000000000000000000000000000000000000000000000000000000 falling vvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvv rising ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ was hi 111111111111111111111111111111111111111111111111111111111111111111 total fails 0, total passes 26 Main menu Sat Jul 11 12:08:30 2015 test file is: tests\m220.tst delay is: 0 trigger is: 1 1 read test file 2 set test delay 3 set test trigger 4 run test 5 output loading test 8 diags 9 exit exiting tester- PDP8 card tester via printer port version 0.85 June 4, 2015 mapping[] is verified Main menu Sat Jul 11 14:33:26 2015 test file is: delay is: 0 trigger is: 1 1 read test file 2 set test delay 3 set test trigger 4 run test 5 output loading test 8 diags 9 exit Enter test file name? trying to open test file: tests\m222.new reading test file: tests\m222.new comment: M222 PCB REV B SCHEMATIC REV A LINC TAPE REGISTERS comment: comment: TERMINOLOGY- SIGNALS REFER TO VOL4 M222 SCHEMATIC. comment: comment: BUT... comment: comment: DEC USES AND-NOR GATES TO ROUTE THE ADDER A AND B INPUTS, SO... comment: DEC RENAMED THE ADDER TO NEGATIVE LOGIC TERMS (I.E. A-N + B-N + C-N -> SUM-N, C1-N). comment: (NOT THE 7482 DATASHEET NAMES OF A + B + C -> SUM, C1). comment: comment: SO, WITH ALL 'AND ENABLES' LOW, THE AND-NOR OUTPUTS = HIGH. comment: WITH C-L HIGH, THE ADDER OUTPUT IS SUM-N=1, C1-N=1; comment: THE INVERTED ADDER OUTPUT IS LOW (TAPE BUS). comment: AND THERE IS NO CARRY (C1-N IS HI). comment: comment: THE TWO ADDERS, TWO REGISTER BITS, ETC ARE LABELED BIT 2 (EVEN, MSB) AND BIT 3 (ODD, LSB). comment: THE ADDERS ARE REFERRED TO AS 'ADDER2' (MSB) AND 'ADDER3' (LSB). comment: comment: POWER PINS: comment: AA2 +5V comment: AT1 GROUND comment: AC2 GROUND comment: BA2 +5V comment: BT1 GROUND comment: BC2 GROUND comment: comment: (ALL PINS ARE USED). comment: comment: pins: PINS pins: 1 I BA1 CARRY IN-N, (TO E9-5 7482 C0) C-N TO ADDER2 pins: 2 I AL2 AND-NOR ENABLE: TAC TAC3 TO PIN BB2 (TO ADDER3) TAC2 TO PIN AN2 (TO ADDER2) pins: 3 I AP1 AND-NOR ENABLE: TMA SETUP (TMAS)3 TO PIN BB2 (TO ADDER3), (TMAS)3 TO PIN AN2 (TO ADDER2) pins: 4 I AS2 AND-NOR ENABLE: TMA TMA3 TO PIN BB2 (TO ADDER3), TMA2 TO PIN AN2 (TO ADDER2) pins: 5 I AL1 AND-NOR ENABLE: PIN AF2 TO PIN BB2 (TO ADDER3), PIN AM1 TO PIN AN2 (TO ADDER2) pins: 6 I AF2 AND-NOR INPUT (AL1 ENABLES) TO PIN BB2 (TO ADDER3). pins: 7 I AM1 AND-NOR INPUT (AL1 ENABLES) TO PIN AN2 (TO ADDER2) pins: 8 I AD2 AND-NOR ENABLE: RWB RWB3 TO PIN BB2 (TO ADDER3), RWB2 TO PIN AN2 (TO ADDER2) pins: 9 I AE2 AND-NOR ENABLE: PIN AE1 TO PIN BB2 (TO ADDER3), PIN AM2 TO PIN AN2 (TO ADDER2) pins: 10 I AE1 AND-NOR INPUT (AE2 ENABLES) TO PIN BB2 (TO ADDER3). pins: 11 I AM2 AND-NOR INPUT (AE2 ENABLES) TO PIN AN2 (TO ADDER2) pins: 12 I AC1 AND-NOR INPUT, AND WITH PIN AB2 TO PIN BB2 (TO ADDER3) pins: 13 I AB2 AND-NOR INPUT, AND WITH PIN AC1 TO PIN BB2 (TO ADDER3) pins: 14 I AF1 AND-NOR INPUT (AND WITH ITSELF) TO PIN BB2 (TO ADDER3) pins: 15 I AR2 AND-NOR INPUT, AND WITH PIN AS1 TO PIN AN2 (TO ADDER2) pins: 16 I AS1 AND-NOR INPUT, AND WITH PIN AR2 TO PIN AN2 (TO ADDER2) pins: 17 I AP2 AND-NOR INPUT (AND WITH ITSELF) TO PIN AN2 (TO ADDER2) pins: 18 I BK1 AND-NOR ENABLE: TB3 TO PIN BB1 (TO ADDER3), TB2 TO PIN BN1 (TO ADDER2) pins: 19 I BL1 AND-NOR ENABLE: PIN BE1 TO PIN BB1 (TO ADDER3), PIN BM1 TO PIN BN1 (TO ADDER2) pins: 20 I BE1 AND-NOR INPUT (BL1 ENABLES) TO PIN BB1 (TO ADDER3). pins: 21 I BM1 AND-NOR INPUT (BL1 ENABLES) TO PIN BN1 (TO ADDER2) pins: 22 I BF1 AND-NOR ENABLE: PIN BH1 TO PIN BB1 (TO ADDER3), PIN BR1 TO PIN BN1 (TO ADDER2) pins: 23 I BH1 AND-NOR INPUT (BF1 ENABLES): TO PIN BB1 (TO ADDER3), pins: 24 I BR1 AND-NOR INPUT (BF1 ENABLES): TO PIN BN1 (TO ADDER2) pins: 25 I BS1 AND-NOR ENABLE: PIN BC1 TO PIN BB1 (TO ADDER3), PIN BJ2 TO PIN BN1 (TO ADDER2) pins: 26 I BC1 AND-NOR INPUT (BS1 ENABLES): TO PIN BB1 (TO ADDER3), pins: 27 I BJ2 AND-NOR INPUT (BS1 ENABLES): TO PIN BN1 (TO ADDER2) pins: 28 I BL2 AND-NOR ENABLE: PIN BJ1 TO PIN BB1 (TO ADDER3), PIN BK2 TO PIN BN1 (TO ADDER2) pins: 29 I BJ1 AND-NOR INPUT (BL2 ENABLES): TO PIN BB1 (TO ADDER3), pins: 30 I BK2 AND-NOR INPUT (BL2 ENABLES): TO PIN BN1 (TO ADDER2) pins: 31 I BU1 AND-NOR ENABLE: PIN BH2 TO PIN BB1 (TO ADDER3), PIN BP2 TO PIN BN1 (TO ADDER2) pins: 32 I BH2 AND-NOR INPUT (BU1 ENABLES): TO PIN BB1 (TO ADDER3), pins: 33 I BP2 AND-NOR INPUT (BU1 ENABLES): TO PIN BN1 (TO ADDER2) pins: 34 I BN2 AND-NOR INPUT (AND WITH BM2): TO PIN BN1 (TO ADDER2) pins: 35 I BM2 AND-NOR INPUT (AND WITH BM2): TO PIN BN1 (TO ADDER2) pins: 36 O BB2 AND-NOR OUTPUT, (DRIVES E9-2 7482 A1) TO ADDER3 INPUT pins: 37 O BB1 AND-NOR OUTPUT, (DRIVES E9-3 7482 B1) TO ADDER3 INPUT pins: 38 O BN1 AND-NOR OUTPUT, (DRIVES E9-14 7482 A2) TO ADDER2 INPUT pins: 39 O AN2 AND-NOR OUTPUT, (DRIVES E9-13 7482 B2) TO ADDER2 INPUT pins: 40 O AV2 CARRY OUT-N (E9-10 7482 C2) pins: 41 O BV2 TAPE BUS 2 OUTPUT (INVERTED ADDER2 SUM-N (E9-12 7482 SUM2) pins: 42 O BR2 TAPE BUS 3 OUTPUT (INVERTED ADDER3 SUM-N (E9-1 7482 SUM1) pins: 43 I AK1 LOAD TMA SETUP (FROM TAPE BUS) (RISING EDGE CLOCK) pins: 44 O AR1 TMA SETUP 2 pins: 45 O AH1 TMA SETUP 3 pins: 46 I AU2 LOAD TMA (FROM TAPE BUS) (RISING EDGE CLOCK) pins: 47 O AT2 TMA 2 pins: 48 O AD1 TMA 3 pins: 49 I AJ1 LOAD TBN (FROM TAPE BUS) (RISING EDGE CLOCK) pins: 50 O AU1 TBN 2 pins: 51 O AK2 TBN 3 pins: 52 I AA1 LOAD TAC (FROM TAPE BUS) (RISING EDGE CLOCK) pins: 53 O AN1 TAC 2 pins: 54 O AJ2 TAC 2-N pins: 55 O AH2 TAC 3 pins: 56 O AB1 TAC 3-N pins: 57 I BT2 LOAD TB (FROM TAPE BUS) (RISING EDGE CLOCK) pins: 58 O BP1 TB 2 pins: 59 O BD1 TB 3 pins: 60 I BF2 LOAD RWB (FROM TB) (JAMS CLEAR,SET) pins: 61 I BS2 PHASE (SELECTS POLARITY OF RWB OUT, 0 -> INVERTED) pins: 62 O BV1 RWB OUT (=RWB 2 IF PHASE=1; =RWB 2-N IF PHASE=0) pins: 63 O BD2 RWB 3 pins: 64 I BE2 SHIFT RWB (SHIFTS PIN AV1 INTO RWB 3, SHIFTS RWB3 TO RWB2) (RISING CLOCK) pins: 65 I AV1 RWB IN (SHIFTED INTO RWB 2) pins: 66 O BU2 +3.5V pins: direction: IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIOOOOOOOIOOIOOIOOIOOOOIOOIIOOIIO comment: ; all registers are unknown comment: ; turn on C0, PHASE comment: ; with no ENABLES, BUS2,BUS3 is 11, C2 is 1 test 1: 1000000000000000000000000000000000011111000XX0XX0XX0XXXX0XX01XX001 comment: comment: ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; comment: ; comment: ; set all registers LOW comment: ; comment: ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; comment: comment: ; load TMA SETUP from tape bus (00) test 2: 100 test 3: 0 comment: ; load TMA from tape bus (00) test 4: 100 test 5: 0 comment: ; load TBN from tape bus (00) test 6: 100 test 7: 0 comment: ; load TAC from tape bus (00) test 8: 10101 test 9: 0 comment: ; load TB from tape bus (00) test 10: 100 test 11: 0 comment: ; load RWB from TB (JAMS CLEAR AND PRESET) test 12: 1 00 test 13: 0 comment: ; (no change) test 14: 100000000000000000000000000000000001111100000000000001010000100001 comment: comment: comment: ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; comment: ; comment: ; set all registers HIGH comment: ; comment: ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; comment: comment: ; set pin AF1 (AND with itself) to clear pin BB2 (AND-NOR output) and set pin BR2 TAPE BUS 3 OUTPUT test 15: 1 0 1 comment: ; set pin AP2 (AND with itself) to clear pin AN2 (AND-NOR output) and set pin BV2 TAPE BUS 2 OUTPUT test 16: 1 0 1 comment: comment: comment: ; load TMA SETUP from tape bus (11) test 17: 111 test 18: 0 comment: ; load TMA from tape bus (11) test 19: 111 test 20: 0 comment: ; load TBN from tape bus (11) test 21: 111 test 22: 0 comment: ; load TAC from tape bus (11) test 23: 11010 test 24: 0 comment: ; load TB from tape bus (11) test 25: 111 test 26: 0 comment: ; load RWB from TB (JAMS CLEAR AND PRESET) test 27: 1 11 test 28: 0 comment: ; clear pin AF1 (AND with itself) to set pin BB2 (AND-NOR output) and clear pin BR2 TAPE BUS 3 OUTPUT test 29: 0 1 0 comment: ; clear pin AP2 (AND with itself) to set pin AN2 (AND-NOR output) and clear pin BV2 TAPE BUS 2 OUTPUT test 30: 0 1 0 comment: ; (no change) test 31: 100000000000000000000000000000000001111100011011011010100110111001 comment: comment: comment: ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; comment: ; comment: ; test AND-NOR logic comment: ; comment: ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; comment: comment: ; (all registers are HIGH) comment: ; set all pins HIGH except ENABLES comment: comment: ; set pin AF2 HIGH test 32: 1 comment: ; set pin AM1 HIGH test 33: 1 comment: ; set pin AE1 HIGH test 34: 1 comment: ; set pin AM2 HIGH test 35: 1 comment: ; set pin AB2 HIGH test 36: 1 comment: ; set pin AS1 HIGH test 37: 1 comment: ; set pin BE1 HIGH test 38: 1 comment: ; set pin BM1 HIGH test 39: 1 comment: ; set pin BH1 HIGH test 40: 1 comment: ; set pin BR1 HIGH test 41: 1 comment: ; set pin BC1 HIGH test 42: 1 comment: ; set pin BJ2 HIGH test 43: 1 comment: ; set pin BJ1 HIGH test 44: 1 comment: ; set pin BK2 HIGH test 45: 1 comment: ; set pin BH2 HIGH test 46: 1 comment: ; set pin BP2 HIGH test 47: 1 comment: ; set pin BN2 HIGH test 48: 1 comment: ; toggle each ENABLE comment: comment: ; set pin AL2 to clear pin BB2 and pin AN2 AND-NOR OUTPUTS and set TAPE BUS 2 OUTPUT and TAPE BUS 3 OUTPUT test 49: 1 0 0 11 test 50: 0 1 1 00 comment: ; set pin AP1 to clear pin BB2 and pin AN2 AND-NOR OUTPUTS and set TAPE BUS 2 OUTPUT and TAPE BUS 3 OUTPUT test 51: 1 0 0 11 test 52: 0 1 1 00 comment: ; set pin AS2 to clear pin BB2 and pin AN2 AND-NOR OUTPUTS and set TAPE BUS 2 OUTPUT and TAPE BUS 3 OUTPUT test 53: 1 0 0 11 test 54: 0 1 1 00 comment: ; set pin AL1 to clear pin BB2 and pin AN2 AND-NOR OUTPUTS and set TAPE BUS 2 OUTPUT and TAPE BUS 3 OUTPUT test 55: 1 0 0 11 test 56: 0 1 1 00 comment: ; set pin AL1 to clear pin BB2 and pin AN2 AND-NOR OUTPUTS and set TAPE BUS 2 OUTPUT and TAPE BUS 3 OUTPUT test 57: 1 0 0 11 test 58: 0 1 1 00 comment: ; set pin AE2 to clear pin BB2 and pin AN2 AND-NOR OUTPUTS and set TAPE BUS 2 OUTPUT and TAPE BUS 3 OUTPUT test 59: 1 0 0 11 test 60: 0 1 1 00 comment: ; set pin AC1 to clear pin BB2 and set TAPE BUS 3 OUTPUT test 61: 1 0 1 test 62: 0 1 0 comment: ; set pin AF1 to clear pin BB2 and set TAPE BUS 3 OUTPUT test 63: 1 0 1 test 64: 0 1 0 comment: ; set pin AR2 to clear pin AN2 AND-NOR OUTPUTS and set TAPE BUS 2 OUTPUT test 65: 1 0 1 test 66: 0 1 0 comment: ; set pin AP2 to clear pin AN2 AND-NOR OUTPUTS and set TAPE BUS 2 OUTPUT test 67: 1 0 1 test 68: 0 1 0 comment: comment: ; set pin BK1 to clear pin BB1 and pin BN1 AND-NOR OUTPUTS and set TAPE BUS 2 OUTPUT and TAPE BUS 3 OUTPUT test 69: 1 00 11 test 70: 0 11 00 comment: ; set pin BL1 to clear pin BB1 and pin BN1 AND-NOR OUTPUTS and set TAPE BUS 2 OUTPUT and TAPE BUS 3 OUTPUT test 71: 1 00 11 test 72: 0 11 00 comment: ; set pin BF1 to clear pin BB1 and pin BN1 AND-NOR OUTPUTS and set TAPE BUS 2 OUTPUT and TAPE BUS 3 OUTPUT test 73: 1 00 11 test 74: 0 11 00 comment: ; set pin BS1 to clear pin BB1 and pin BN1 AND-NOR OUTPUTS and set TAPE BUS 2 OUTPUT and TAPE BUS 3 OUTPUT test 75: 1 00 11 test 76: 0 11 00 comment: ; set pin BL2 to clear pin BB1 and pin BN1 AND-NOR OUTPUTS and set TAPE BUS 2 OUTPUT and TAPE BUS 3 OUTPUT test 77: 1 00 11 test 78: 0 11 00 comment: ; set pin BU1 to clear pin BB1 and pin BN1 AND-NOR OUTPUTS and set TAPE BUS 2 OUTPUT and TAPE BUS 3 OUTPUT test 79: 1 00 11 test 80: 0 11 00 comment: ; set pin BM2 to clear pin BB1 and TAPE BUS 3 OUTPUT test 81: 1 0 1 test 82: 0 1 0 comment: comment: comment: ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; comment: ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; comment: ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; comment: ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; comment: ; needs work comment: ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; comment: ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; comment: ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; comment: ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; end: END summary column 1: offset 2, mask 0x2000 column 2: offset 1, mask 0x0002 column 3: offset 1, mask 0x0800 column 4: offset 1, mask 0x0040 column 5: offset 1, mask 0x4000 column 6: offset 0, mask 0x0004 column 7: offset 1, mask 0x2000 column 8: offset 0, mask 0x0010 column 9: offset 0, mask 0x0008 column 10: offset 0, mask 0x0800 column 11: offset 1, mask 0x0004 column 12: offset 0, mask 0x2000 column 13: offset 0, mask 0x0040 column 14: offset 0, mask 0x0400 column 15: offset 1, mask 0x0020 column 16: offset 1, mask 0x0200 column 17: offset 1, mask 0x0010 column 18: offset 3, mask 0x2000 column 19: offset 3, mask 0x1000 column 20: offset 2, mask 0x0200 column 21: offset 3, mask 0x0800 column 22: offset 2, mask 0x0100 column 23: offset 3, mask 0x8000 column 24: offset 3, mask 0x0100 column 25: offset 4, mask 0x8000 column 26: offset 2, mask 0x0800 column 27: offset 3, mask 0x0002 column 28: offset 3, mask 0x0008 column 29: offset 3, mask 0x4000 column 30: offset 3, mask 0x0004 column 31: offset 4, mask 0x2000 column 32: offset 3, mask 0x0001 column 33: offset 3, mask 0x0040 column 34: offset 3, mask 0x0020 column 35: offset 3, mask 0x0010 column 36: offset 2, mask 0x0008 column 37: offset 2, mask 0x1000 column 38: offset 3, mask 0x0400 column 39: offset 1, mask 0x0008 column 40: offset 2, mask 0x0002 column 41: offset 4, mask 0x0008 column 42: offset 3, mask 0x0080 column 43: offset 1, mask 0x8000 column 44: offset 1, mask 0x0400 column 45: offset 0, mask 0x0200 column 46: offset 2, mask 0x0001 column 47: offset 1, mask 0x0080 column 48: offset 0, mask 0x1000 column 49: offset 0, mask 0x0100 column 50: offset 2, mask 0x8000 column 51: offset 1, mask 0x0001 column 52: offset 0, mask 0x8000 column 53: offset 1, mask 0x1000 column 54: offset 0, mask 0x0001 column 55: offset 0, mask 0x0002 column 56: offset 0, mask 0x4000 column 57: offset 4, mask 0x0002 column 58: offset 3, mask 0x0200 column 59: offset 2, mask 0x0400 column 60: offset 2, mask 0x0080 column 61: offset 4, mask 0x0001 column 62: offset 4, mask 0x1000 column 63: offset 2, mask 0x0020 column 64: offset 2, mask 0x0040 column 65: offset 2, mask 0x4000 column 66: offset 4, mask 0x0004 direction bits (1=input) 0x52A3 0x1589 0x943A 0x0680 0x50FC pullup bits (1=pullup) 0x0000 0x0000 0x0000 0x0000 0x0000 test step out_data dont care 1: 0x0000 0x0008 0x300A 0x0400 0x0005 0x5203 0x1481 0x8420 0x0200 0x1000 2: 0x0000 0x8008 0x300A 0x0400 0x0005 0x5003 0x1081 0x8420 0x0200 0x1000 3: 0x0000 0x0008 0x300A 0x0400 0x0005 0x5003 0x1081 0x8420 0x0200 0x1000 4: 0x0000 0x0008 0x300B 0x0400 0x0005 0x4003 0x1001 0x8420 0x0200 0x1000 5: 0x0000 0x0008 0x300A 0x0400 0x0005 0x4003 0x1001 0x8420 0x0200 0x1000 6: 0x0100 0x0008 0x300A 0x0400 0x0005 0x4003 0x1000 0x0420 0x0200 0x1000 7: 0x0000 0x0008 0x300A 0x0400 0x0005 0x4003 0x1000 0x0420 0x0200 0x1000 8: 0xC001 0x0008 0x300A 0x0400 0x0005 0x0000 0x0000 0x0420 0x0200 0x1000 9: 0x4001 0x0008 0x300A 0x0400 0x0005 0x0000 0x0000 0x0420 0x0200 0x1000 10: 0x4001 0x0008 0x300A 0x0400 0x0007 0x0000 0x0000 0x0020 0x0000 0x1000 11: 0x4001 0x0008 0x300A 0x0400 0x0005 0x0000 0x0000 0x0020 0x0000 0x1000 12: 0x4001 0x0008 0x308A 0x0400 0x0005 13: 0x4001 0x0008 0x300A 0x0400 0x0005 14: 0x4001 0x0008 0x300A 0x0400 0x0005 15: 0x4401 0x0008 0x3002 0x0480 0x0005 16: 0x4401 0x0010 0x3002 0x0480 0x000D 17: 0x4601 0x8410 0x3002 0x0480 0x000D 18: 0x4601 0x0410 0x3002 0x0480 0x000D 19: 0x5601 0x0490 0x3003 0x0480 0x000D 20: 0x5601 0x0490 0x3002 0x0480 0x000D 21: 0x5701 0x0491 0xB002 0x0480 0x000D 22: 0x5601 0x0491 0xB002 0x0480 0x000D 23: 0x9602 0x1491 0xB002 0x0480 0x000D 24: 0x1602 0x1491 0xB002 0x0480 0x000D 25: 0x1602 0x1491 0xB402 0x0680 0x000F 26: 0x1602 0x1491 0xB402 0x0680 0x000D 27: 0x1602 0x1491 0xB4A2 0x0680 0x100D 28: 0x1602 0x1491 0xB422 0x0680 0x100D 29: 0x1202 0x1491 0xB42A 0x0600 0x100D 30: 0x1202 0x1489 0xB42A 0x0600 0x1005 31: 0x1202 0x1489 0xB42A 0x0600 0x1005 32: 0x1206 0x1489 0xB42A 0x0600 0x1005 33: 0x1206 0x3489 0xB42A 0x0600 0x1005 34: 0x1A06 0x3489 0xB42A 0x0600 0x1005 35: 0x1A06 0x348D 0xB42A 0x0600 0x1005 36: 0x1A46 0x348D 0xB42A 0x0600 0x1005 37: 0x1A46 0x368D 0xB42A 0x0600 0x1005 38: 0x1A46 0x368D 0xB62A 0x0600 0x1005 39: 0x1A46 0x368D 0xB62A 0x0E00 0x1005 40: 0x1A46 0x368D 0xB62A 0x8E00 0x1005 41: 0x1A46 0x368D 0xB62A 0x8F00 0x1005 42: 0x1A46 0x368D 0xBE2A 0x8F00 0x1005 43: 0x1A46 0x368D 0xBE2A 0x8F02 0x1005 44: 0x1A46 0x368D 0xBE2A 0xCF02 0x1005 45: 0x1A46 0x368D 0xBE2A 0xCF06 0x1005 46: 0x1A46 0x368D 0xBE2A 0xCF07 0x1005 47: 0x1A46 0x368D 0xBE2A 0xCF47 0x1005 48: 0x1A46 0x368D 0xBE2A 0xCF67 0x1005 49: 0x1A46 0x3687 0xBE22 0xCFE7 0x100D 50: 0x1A46 0x368D 0xBE2A 0xCF67 0x1005 51: 0x1A46 0x3E85 0xBE22 0xCFE7 0x100D 52: 0x1A46 0x368D 0xBE2A 0xCF67 0x1005 53: 0x1A46 0x36C5 0xBE22 0xCFE7 0x100D 54: 0x1A46 0x368D 0xBE2A 0xCF67 0x1005 55: 0x1A46 0x7685 0xBE22 0xCFE7 0x100D 56: 0x1A46 0x368D 0xBE2A 0xCF67 0x1005 57: 0x1A56 0x3685 0xBE22 0xCFE7 0x100D 58: 0x1A46 0x368D 0xBE2A 0xCF67 0x1005 59: 0x1A4E 0x3685 0xBE22 0xCFE7 0x100D 60: 0x1A46 0x368D 0xBE2A 0xCF67 0x1005 61: 0x3A46 0x368D 0xBE22 0xCFE7 0x1005 62: 0x1A46 0x368D 0xBE2A 0xCF67 0x1005 63: 0x1E46 0x368D 0xBE22 0xCFE7 0x1005 64: 0x1A46 0x368D 0xBE2A 0xCF67 0x1005 65: 0x1A46 0x36A5 0xBE2A 0xCF67 0x100D 66: 0x1A46 0x368D 0xBE2A 0xCF67 0x1005 67: 0x1A46 0x3695 0xBE2A 0xCF67 0x100D 68: 0x1A46 0x368D 0xBE2A 0xCF67 0x1005 69: 0x1A46 0x368D 0xAE2A 0xEBE7 0x100D 70: 0x1A46 0x368D 0xBE2A 0xCF67 0x1005 71: 0x1A46 0x368D 0xAE2A 0xDBE7 0x100D 72: 0x1A46 0x368D 0xBE2A 0xCF67 0x1005 73: 0x1A46 0x368D 0xAF2A 0xCBE7 0x100D 74: 0x1A46 0x368D 0xBE2A 0xCF67 0x1005 75: 0x1A46 0x368D 0xAE2A 0xCBE7 0x900D 76: 0x1A46 0x368D 0xBE2A 0xCF67 0x1005 77: 0x1A46 0x368D 0xAE2A 0xCBEF 0x100D 78: 0x1A46 0x368D 0xBE2A 0xCF67 0x1005 79: 0x1A46 0x368D 0xAE2A 0xCBE7 0x300D 80: 0x1A46 0x368D 0xBE2A 0xCF67 0x1005 81: 0x1A46 0x368D 0xBE2A 0xCB77 0x100D 82: 0x1A46 0x368D 0xBE2A 0xCF67 0x1005 PINs used (in edge connector order) (G=ground,P=power) SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBB LETTER ABCDEFHJKLMNPRSTUVABCDEFHJKLMNPRSTUVABCDEFHJKLMNPRSTUVABCDEFHJKLMNPRSTUV SIDE 111111111111111111222222222222222222111111111111111111222222222222222222 USAGE IOIOIIOIIIIOIOIGOIPIGIIIOOOIIOIIIOIOIOIOIIIIIIIOOIIGIOPOGOIIIIIIIIIOIIOO UUT has 44 inputs UUT has 22 outputs contains 66 pins/columns 0 pins are not used contains 82 'test steps' M222 PCB REV B SCHEMATIC REV A LINC TAPE REGISTERS TERMINOLOGY- SIGNALS REFER TO VOL4 M222 SCHEMATIC. BUT... DEC USES AND-NOR GATES TO ROUTE THE ADDER A AND B INPUTS, SO... DEC RENAMED THE ADDER TO NEGATIVE LOGIC TERMS (I.E. A-N + B-N + C-N -> SUM-N, C1-N). (NOT THE 7482 DATASHEET NAMES OF A + B + C -> SUM, C1). SO, WITH ALL 'AND ENABLES' LOW, THE AND-NOR OUTPUTS = HIGH. WITH C-L HIGH, THE ADDER OUTPUT IS SUM-N=1, C1-N=1; THE INVERTED ADDER OUTPUT IS LOW (TAPE BUS). AND THERE IS NO CARRY (C1-N IS HI). THE TWO ADDERS, TWO REGISTER BITS, ETC ARE LABELED BIT 2 (EVEN, MSB) AND BIT 3 (ODD, LSB). THE ADDERS ARE REFERRED TO AS 'ADDER2' (MSB) AND 'ADDER3' (LSB). POWER PINS: AA2 +5V AT1 GROUND AC2 GROUND BA2 +5V BT1 GROUND BC2 GROUND (ALL PINS ARE USED). PINS Main menu Sat Jul 11 14:33:36 2015 test file is: tests\m222.new delay is: 0 trigger is: 1 1 read test file 2 set test delay 3 set test trigger 4 run test 5 output loading test 8 diags 9 exit ***************************** UUT power is OFF * ***************************** Main menu Sat Jul 11 14:33:40 2015 test file is: tests\m222.new delay is: 0 trigger is: 1 1 read test file 2 set test delay 3 set test trigger 4 run test 5 output loading test 8 diags 9 exit key is 0x0073 Main menu Sat Jul 11 14:33:45 2015 test file is: tests\m222.new delay is: 0 trigger is: 1 1 read test file 2 set test delay 3 set test trigger 4 run test 5 output loading test 8 diags 9 exit UUT power is okay Sat Jul 11 14:33:48 2015 space single step O run once (one test, all steps) F run, stop on fail G go (run tests N run, stop on fail, no print S scope (run, no print) C toggle comment printout + increase speed (less delay) - decrease speed (more delay)(slower) Q quit test scope (run, no print) FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF FFFFFFFFFFFFFFFFFFFFFFF space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C toggle comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit step 16 100000000000010010000000000000000000110111000000000001010000100001 step 17 100000000000010010000000000000000000110111111000000001010000100001 step 18 100000000000010010000000000000000000110111011000000001010000100001 step 19 100000000000010010000000000000000000110111011111000001010000100001 step 20 100000000000010010000000000000000000110111011011000001010000100001 step 21 100000000000010010000000000000000000110111011011111001010000100001 step 22 100000000000010010000000000000000000110111011011011001010000100001 step 23 100000000000010010000000000000000000110111011011011110100000100001 step 24 100000000000010010000000000000000000110111011011011010100000100001 step 25 100000000000010010000000000000000000110111011011011010101110100001 step 26 100000000000010010000000000000000000110111011011011010100110100001 step 27 100000000000010010000000000000000000110111011011011010100111111001 step 28 100000000000010010000000000000000000110111011011011010100110111001 step 29 100000000000000010000000000000000001110110011011011010100110111001 step 30 100000000000000000000000000000000001111100011011011010100110111001 step 31 100000000000000000000000000000000001111100011011011010100110111001 step 32 100001000000000000000000000000000001111100011011011010100110111001 step 33 100001100000000000000000000000000001111100011011011010100110111001 step 34 100001100100000000000000000000000001111100011011011010100110111001 step 35 100001100110000000000000000000000001111100011011011010100110111001 step 36 100001100110100000000000000000000001111100011011011010100110111001 step 37 100001100110100100000000000000000001111100011011011010100110111001 step 38 100001100110100100010000000000000001111100011011011010100110111001 step 39 100001100110100100011000000000000001111100011011011010100110111001 step 40 100001100110100100011010000000000001111100011011011010100110111001 step 41 100001100110100100011011000000000001111100011011011010100110111001 step 42 100001100110100100011011010000000001111100011011011010100110111001 step 43 100001100110100100011011011000000001111100011011011010100110111001 step 44 100001100110100100011011011010000001111100011011011010100110111001 step 45 100001100110100100011011011011000001111100011011011010100110111001 step 46 100001100110100100011011011011010001111100011011011010100110111001 step 47 100001100110100100011011011011011001111100011011011010100110111001 step 48 100001100110100100011011011011011101111100011011011010100110111001 step 49 110001100110100100011011011011011100110111011011011010100110111001 step 50 100001100110100100011011011011011101111100011011011010100110111001 step 51 101001100110100100011011011011011100110111011011011010100110111001 step 52 100001100110100100011011011011011101111100011011011010100110111001 step 53 100101100110100100011011011011011100110111011011011010100110111001 step 54 100001100110100100011011011011011101111100011011011010100110111001 step 55 100011100110100100011011011011011100110111011011011010100110111001 step 56 100001100110100100011011011011011101111100011011011010100110111001 step 57 100001110110100100011011011011011100110111011011011010100110111001 step 58 100001100110100100011011011011011101111100011011011010100110111001 step 59 100001101110100100011011011011011100110111011011011010100110111001 step 60 100001100110100100011011011011011101111100011011011010100110111001 step 61 100001100111100100011011011011011100111101011011011010100110111001 step 62 100001100110100100011011011011011101111100011011011010100110111001 step 63 100001100110110100011011011011011100111101011011011010100110111001 step 64 100001100110100100011011011011011101111100011011011010100110111001 step 65 100001100110101100011011011011011101110110011011011010100110111001 step 66 100001100110100100011011011011011101111100011011011010100110111001 step 67 100001100110100110011011011011011101110110011011011010100110111001 step 68 100001100110100100011011011011011101111100011011011010100110111001 step 69 100001100110100101011011011011011101001111011011011010100110111001 SLOT BAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBAABBAAAAAAAAAAAAAABBBBBBBBAB LETTER ALPSLFMDEEMCBFRSPKLEMFHRSCJLJKUHPNMBBNNVVRKRHUTDJUKANJHBTPDFSVDEVU SIDE 121212122121212121111111112212122222112222111221112112212112212212 DIRECTION IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIOOOOOOOIOOIOOIOOIOOOOIOOIIOOIIO changed: 0 1 00 step 70 100001100110100100011011011011011101011100011011011010100110111001 fail ^ step 71 100001100110100100111011011011011101001111011011011010100110111001 SLOT BAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBAABBAAAAAAAAAAAAAABBBBBBBBAB LETTER ALPSLFMDEEMCBFRSPKLEMFHRSCJLJKUHPNMBBNNVVRKRHUTDJUKANJHBTPDFSVDEVU SIDE 121212122121212121111111112212122222112222111221112112212112212212 DIRECTION IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIOOOOOOOIOOIOOIOOIOOOOIOOIIOOIIO changed: 0 1 00 step 72 100001100110100100011011011011011101011100011011011010100110111001 fail ^ step 73 100001100110100100011111011011011101001111011011011010100110111001 SLOT BAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBAABBAAAAAAAAAAAAAABBBBBBBBAB LETTER ALPSLFMDEEMCBFRSPKLEMFHRSCJLJKUHPNMBBNNVVRKRHUTDJUKANJHBTPDFSVDEVU SIDE 121212122121212121111111112212122222112222111221112112212112212212 DIRECTION IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIOOOOOOOIOOIOOIOOIOOOOIOOIIOOIIO changed: 0 1 00 step 74 100001100110100100011011011011011101011100011011011010100110111001 fail ^ step 75 100001100110100100011011111011011101001111011011011010100110111001 SLOT BAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBAABBAAAAAAAAAAAAAABBBBBBBBAB LETTER ALPSLFMDEEMCBFRSPKLEMFHRSCJLJKUHPNMBBNNVVRKRHUTDJUKANJHBTPDFSVDEVU SIDE 121212122121212121111111112212122222112222111221112112212112212212 DIRECTION IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIOOOOOOOIOOIOOIOOIOOOOIOOIIOOIIO changed: 0 1 00 step 76 100001100110100100011011011011011101011100011011011010100110111001 fail ^ SLOT BAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBAABBAAAAAAAAAAAAAABBBBBBBBAB LETTER ALPSLFMDEEMCBFRSPKLEMFHRSCJLJKUHPNMBBNNVVRKRHUTDJUKANJHBTPDFSVDEVU SIDE 121212122121212121111111112212122222112222111221112112212112212212 DIRECTION IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIOOOOOOOIOOIOOIOOIOOOOIOOIIOOIIO changed: 1 0 1 step 77 100001100110100100011011011111011101001110011011011010100110111001 fail ^ SLOT BAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBAABBAAAAAAAAAAAAAABBBBBBBBAB LETTER ALPSLFMDEEMCBFRSPKLEMFHRSCJLJKUHPNMBBNNVVRKRHUTDJUKANJHBTPDFSVDEVU SIDE 121212122121212121111111112212122222112222111221112112212112212212 DIRECTION IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIOOOOOOOIOOIOOIOOIOOOOIOOIIOOIIO changed: 0 1 0 step 78 100001100110100100011011011011011101011100011011011010100110111001 fail ^ SLOT BAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBAABBAAAAAAAAAAAAAABBBBBBBBAB LETTER ALPSLFMDEEMCBFRSPKLEMFHRSCJLJKUHPNMBBNNVVRKRHUTDJUKANJHBTPDFSVDEVU SIDE 121212122121212121111111112212122222112222111221112112212112212212 DIRECTION IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIOOOOOOOIOOIOOIOOIOOOOIOOIIOOIIO changed: 1 0 1 step 79 100001100110100100011011011011111101001110011011011010100110111001 fail ^ SLOT BAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBAABBAAAAAAAAAAAAAABBBBBBBBAB LETTER ALPSLFMDEEMCBFRSPKLEMFHRSCJLJKUHPNMBBNNVVRKRHUTDJUKANJHBTPDFSVDEVU SIDE 121212122121212121111111112212122222112222111221112112212112212212 DIRECTION IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIOOOOOOOIOOIOOIOOIOOOOIOOIIOOIIO changed: 0 1 0 step 80 100001100110100100011011011011011101011100011011011010100110111001 fail ^ SLOT BAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBAABBAAAAAAAAAAAAAABBBBBBBBAB LETTER ALPSLFMDEEMCBFRSPKLEMFHRSCJLJKUHPNMBBNNVVRKRHUTDJUKANJHBTPDFSVDEVU SIDE 121212122121212121111111112212122222112222111221112112212112212212 DIRECTION IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIOOOOOOOIOOIOOIOOIOOOOIOOIIOOIIO changed: 1 0 1 step 81 100001100110100100011011011011011111001110011011011010100110111001 fail ^ SLOT BAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBAABBAAAAAAAAAAAAAABBBBBBBBAB LETTER ALPSLFMDEEMCBFRSPKLEMFHRSCJLJKUHPNMBBNNVVRKRHUTDJUKANJHBTPDFSVDEVU SIDE 121212122121212121111111112212122222112222111221112112212112212212 DIRECTION IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIOOOOOOOIOOIOOIOOIOOOOIOOIIOOIIO changed: 0 1 0 step 82 100001100110100100011011011011011101011100011011011010100110111001 fail ^ test 103: *** FAIL *************************** 10 steps failed SLOT BAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBAABBAAAAAAAAAAAAAABBBBBBBBAB LETTER ALPSLFMDEEMCBFRSPKLEMFHRSCJLJKUHPNMBBNNVVRKRHUTDJUKANJHBTPDFSVDEVU SIDE 121212122121212121111111112212122222112222111221112112212112212212 DIRECTION IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIOOOOOOOIOOIOOIOOIOOOOIOOIIOOIIO this fail O O all fails O O was hi 111111111111111111111111111111111111111111111111111111111111111 1 rising ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ ^^^^^^^^^^^^^^^^^^^^ ^^ falling vvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvv vvvvvvvvvvvvvvvvvvvv vv was lo 00000000000000000000000000000000000000 00000000000000000000 0000 total fails 103, total passes 0 space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C toggle comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit comment_flag is 1 space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C toggle comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit source: ; all registers are unknown source: ; turn on C0, PHASE source: ; with no ENABLES, BUS2,BUS3 is 11, C2 is 1 source: 1000000000000000000000000000000000011111000XX0XX0XX0XXXX0XX01XX001 changed: 00 00 0 0 00 00 00 00 000 1 step 1 100000000000000000000000000000000001111100011011011010100110111001 source: source: ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; source: ; source: ; set all registers LOW source: ; source: ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; source: source: ; load TMA SETUP from tape bus (00) source: 100 changed: 100 step 2 100000000000000000000000000000000001111100100011011010100110111001 source: 0 changed: 0 step 3 100000000000000000000000000000000001111100000011011010100110111001 source: ; load TMA from tape bus (00) source: 100 changed: 100 step 4 100000000000000000000000000000000001111100000100011010100110111001 source: 0 changed: 0 step 5 100000000000000000000000000000000001111100000000011010100110111001 source: ; load TBN from tape bus (00) source: 100 changed: 100 step 6 100000000000000000000000000000000001111100000000100010100110111001 source: 0 changed: 0 step 7 100000000000000000000000000000000001111100000000000010100110111001 source: ; load TAC from tape bus (00) source: 10101 changed: 10101 step 8 100000000000000000000000000000000001111100000000000101010110111001 source: 0 changed: 0 step 9 100000000000000000000000000000000001111100000000000001010110111001 source: ; load TB from tape bus (00) source: 100 changed: 100 step 10 100000000000000000000000000000000001111100000000000001011000111001 source: 0 changed: 0 step 11 100000000000000000000000000000000001111100000000000001010000111001 source: ; load RWB from TB (JAMS CLEAR AND PRESET) source: 1 00 changed: 1 00 step 12 100000000000000000000000000000000001111100000000000001010001100001 source: 0 changed: 0 step 13 100000000000000000000000000000000001111100000000000001010000100001 source: ; (no change) source: 100000000000000000000000000000000001111100000000000001010000100001 changed: step 14 100000000000000000000000000000000001111100000000000001010000100001 source: source: source: ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; source: ; source: ; set all registers HIGH source: ; source: ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; source: source: ; set pin AF1 (AND with itself) to clear pin BB2 (AND-NOR output) and set pin BR2 TAPE BUS 3 OUTPUT source: 1 0 1 changed: 1 0 1 step 15 100000000000010000000000000000000000111101000000000001010000100001 source: ; set pin AP2 (AND with itself) to clear pin AN2 (AND-NOR output) and set pin BV2 TAPE BUS 2 OUTPUT source: 1 0 1 changed: 1 0 1 step 16 100000000000010010000000000000000000110111000000000001010000100001 source: source: source: ; load TMA SETUP from tape bus (11) source: 111 changed: 111 step 17 100000000000010010000000000000000000110111111000000001010000100001 source: 0 changed: 0 step 18 100000000000010010000000000000000000110111011000000001010000100001 source: ; load TMA from tape bus (11) source: 111 changed: 111 step 19 100000000000010010000000000000000000110111011111000001010000100001 source: 0 changed: 0 step 20 100000000000010010000000000000000000110111011011000001010000100001 source: ; load TBN from tape bus (11) source: 111 changed: 111 step 21 100000000000010010000000000000000000110111011011111001010000100001 source: 0 changed: 0 step 22 100000000000010010000000000000000000110111011011011001010000100001 source: ; load TAC from tape bus (11) source: 11010 changed: 11010 step 23 100000000000010010000000000000000000110111011011011110100000100001 source: 0 changed: 0 step 24 100000000000010010000000000000000000110111011011011010100000100001 source: ; load TB from tape bus (11) source: 111 changed: 111 step 25 100000000000010010000000000000000000110111011011011010101110100001 source: 0 changed: 0 step 26 100000000000010010000000000000000000110111011011011010100110100001 source: ; load RWB from TB (JAMS CLEAR AND PRESET) source: 1 11 changed: 1 11 step 27 100000000000010010000000000000000000110111011011011010100111111001 source: 0 changed: 0 step 28 100000000000010010000000000000000000110111011011011010100110111001 source: ; clear pin AF1 (AND with itself) to set pin BB2 (AND-NOR output) and clear pin BR2 TAPE BUS 3 OUTPUT source: 0 1 0 changed: 0 1 0 step 29 100000000000000010000000000000000001110110011011011010100110111001 source: ; clear pin AP2 (AND with itself) to set pin AN2 (AND-NOR output) and clear pin BV2 TAPE BUS 2 OUTPUT source: 0 1 0 changed: 0 1 0 step 30 100000000000000000000000000000000001111100011011011010100110111001 source: ; (no change) source: 100000000000000000000000000000000001111100011011011010100110111001 changed: step 31 100000000000000000000000000000000001111100011011011010100110111001 source: source: source: ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; source: ; source: ; test AND-NOR logic source: ; source: ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; source: source: ; (all registers are HIGH) source: ; set all pins HIGH except ENABLES source: source: ; set pin AF2 HIGH source: 1 changed: 1 step 32 100001000000000000000000000000000001111100011011011010100110111001 source: ; set pin AM1 HIGH source: 1 changed: 1 step 33 100001100000000000000000000000000001111100011011011010100110111001 source: ; set pin AE1 HIGH source: 1 changed: 1 step 34 100001100100000000000000000000000001111100011011011010100110111001 source: ; set pin AM2 HIGH source: 1 changed: 1 step 35 100001100110000000000000000000000001111100011011011010100110111001 source: ; set pin AB2 HIGH source: 1 changed: 1 step 36 100001100110100000000000000000000001111100011011011010100110111001 source: ; set pin AS1 HIGH source: 1 changed: 1 step 37 100001100110100100000000000000000001111100011011011010100110111001 source: ; set pin BE1 HIGH source: 1 changed: 1 step 38 100001100110100100010000000000000001111100011011011010100110111001 source: ; set pin BM1 HIGH source: 1 changed: 1 step 39 100001100110100100011000000000000001111100011011011010100110111001 source: ; set pin BH1 HIGH source: 1 changed: 1 step 40 100001100110100100011010000000000001111100011011011010100110111001 source: ; set pin BR1 HIGH source: 1 changed: 1 step 41 100001100110100100011011000000000001111100011011011010100110111001 source: ; set pin BC1 HIGH source: 1 changed: 1 step 42 100001100110100100011011010000000001111100011011011010100110111001 source: ; set pin BJ2 HIGH source: 1 changed: 1 step 43 100001100110100100011011011000000001111100011011011010100110111001 source: ; set pin BJ1 HIGH source: 1 changed: 1 step 44 100001100110100100011011011010000001111100011011011010100110111001 source: ; set pin BK2 HIGH source: 1 changed: 1 step 45 100001100110100100011011011011000001111100011011011010100110111001 source: ; set pin BH2 HIGH source: 1 changed: 1 step 46 100001100110100100011011011011010001111100011011011010100110111001 source: ; set pin BP2 HIGH source: 1 changed: 1 step 47 100001100110100100011011011011011001111100011011011010100110111001 source: ; set pin BN2 HIGH source: 1 changed: 1 step 48 100001100110100100011011011011011101111100011011011010100110111001 source: ; toggle each ENABLE source: source: ; set pin AL2 to clear pin BB2 and pin AN2 AND-NOR OUTPUTS and set TAPE BUS 2 OUTPUT and TAPE BUS 3 OUTPUT source: 1 0 0 11 changed: 1 0 0 11 step 49 110001100110100100011011011011011100110111011011011010100110111001 source: 0 1 1 00 changed: 0 1 1 00 step 50 100001100110100100011011011011011101111100011011011010100110111001 source: ; set pin AP1 to clear pin BB2 and pin AN2 AND-NOR OUTPUTS and set TAPE BUS 2 OUTPUT and TAPE BUS 3 OUTPUT source: 1 0 0 11 changed: 1 0 0 11 step 51 101001100110100100011011011011011100110111011011011010100110111001 source: 0 1 1 00 changed: 0 1 1 00 step 52 100001100110100100011011011011011101111100011011011010100110111001 source: ; set pin AS2 to clear pin BB2 and pin AN2 AND-NOR OUTPUTS and set TAPE BUS 2 OUTPUT and TAPE BUS 3 OUTPUT source: 1 0 0 11 changed: 1 0 0 11 step 53 100101100110100100011011011011011100110111011011011010100110111001 source: 0 1 1 00 changed: 0 1 1 00 step 54 100001100110100100011011011011011101111100011011011010100110111001 source: ; set pin AL1 to clear pin BB2 and pin AN2 AND-NOR OUTPUTS and set TAPE BUS 2 OUTPUT and TAPE BUS 3 OUTPUT source: 1 0 0 11 changed: 1 0 0 11 step 55 100011100110100100011011011011011100110111011011011010100110111001 source: 0 1 1 00 changed: 0 1 1 00 step 56 100001100110100100011011011011011101111100011011011010100110111001 source: ; set pin AL1 to clear pin BB2 and pin AN2 AND-NOR OUTPUTS and set TAPE BUS 2 OUTPUT and TAPE BUS 3 OUTPUT source: 1 0 0 11 changed: 1 0 0 11 step 57 100001110110100100011011011011011100110111011011011010100110111001 source: 0 1 1 00 changed: 0 1 1 00 step 58 100001100110100100011011011011011101111100011011011010100110111001 source: ; set pin AE2 to clear pin BB2 and pin AN2 AND-NOR OUTPUTS and set TAPE BUS 2 OUTPUT and TAPE BUS 3 OUTPUT source: 1 0 0 11 changed: 1 0 0 11 step 59 100001101110100100011011011011011100110111011011011010100110111001 source: 0 1 1 00 changed: 0 1 1 00 step 60 100001100110100100011011011011011101111100011011011010100110111001 source: ; set pin AC1 to clear pin BB2 and set TAPE BUS 3 OUTPUT source: 1 0 1 changed: 1 0 1 step 61 100001100111100100011011011011011100111101011011011010100110111001 source: 0 1 0 changed: 0 1 0 step 62 100001100110100100011011011011011101111100011011011010100110111001 source: ; set pin AF1 to clear pin BB2 and set TAPE BUS 3 OUTPUT source: 1 0 1 changed: 1 0 1 step 63 100001100110110100011011011011011100111101011011011010100110111001 source: 0 1 0 changed: 0 1 0 step 64 100001100110100100011011011011011101111100011011011010100110111001 source: ; set pin AR2 to clear pin AN2 AND-NOR OUTPUTS and set TAPE BUS 2 OUTPUT source: 1 0 1 changed: 1 0 1 step 65 100001100110101100011011011011011101110110011011011010100110111001 source: 0 1 0 changed: 0 1 0 step 66 100001100110100100011011011011011101111100011011011010100110111001 source: ; set pin AP2 to clear pin AN2 AND-NOR OUTPUTS and set TAPE BUS 2 OUTPUT source: 1 0 1 changed: 1 0 1 step 67 100001100110100110011011011011011101110110011011011010100110111001 source: 0 1 0 changed: 0 1 0 step 68 100001100110100100011011011011011101111100011011011010100110111001 source: source: ; set pin BK1 to clear pin BB1 and pin BN1 AND-NOR OUTPUTS and set TAPE BUS 2 OUTPUT and TAPE BUS 3 OUTPUT source: 1 00 11 changed: 1 00 11 step 69 100001100110100101011011011011011101001111011011011010100110111001 SLOT BAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBAABBAAAAAAAAAAAAAABBBBBBBBAB LETTER ALPSLFMDEEMCBFRSPKLEMFHRSCJLJKUHPNMBBNNVVRKRHUTDJUKANJHBTPDFSVDEVU SIDE 121212122121212121111111112212122222112222111221112112212112212212 DIRECTION IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIOOOOOOOIOOIOOIOOIOOOOIOOIIOOIIO source: 0 11 00 changed: 0 1 00 step 70 100001100110100100011011011011011101011100011011011010100110111001 fail ^ space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C toggle comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT BAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBAABBAAAAAAAAAAAAAABBBBBBBBAB LETTER ALPSLFMDEEMCBFRSPKLEMFHRSCJLJKUHPNMBBNNVVRKRHUTDJUKANJHBTPDFSVDEVU SIDE 121212122121212121111111112212122222112222111221112112212112212212 DIRECTION IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIOOOOOOOIOOIOOIOOIOOOOIOOIIOOIIO all fails O O was lo 00000000000000000000000000000000000000 00000000000000000000 0000 falling vvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvv vvvvvvvvvvvvvvvvvvvv vv rising ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ ^^^^^^^^^^^^^^^^^^^^ ^^ was hi 111111111111111111111111111111111111111111111111111111111111111 1 total fails 103, total passes 0 Main menu Sat Jul 11 14:35:02 2015 test file is: tests\m222.new delay is: 0 trigger is: 1 1 read test file 2 set test delay 3 set test trigger 4 run test 5 output loading test 8 diags 9 exit UUT power is okay Sat Jul 11 14:35:11 2015 space single step O run once (one test, all steps) F run, stop on fail G go (run tests N run, stop on fail, no print S scope (run, no print) C toggle comment printout + increase speed (less delay) - decrease speed (more delay)(slower) Q quit test SLOT BAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBAABBAAAAAAAAAAAAAABBBBBBBBAB LETTER ALPSLFMDEEMCBFRSPKLEMFHRSCJLJKUHPNMBBNNVVRKRHUTDJUKANJHBTPDFSVDEVU SIDE 121212122121212121111111112212122222112222111221112112212112212212 DIRECTION IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIOOOOOOOIOOIOOIOOIOOOOIOOIIOOIIO all fails was lo falling rising was hi total fails 0, total passes 0 Main menu Sat Jul 11 14:35:19 2015 test file is: tests\m222.new delay is: 0 trigger is: 1 1 read test file 2 set test delay 3 set test trigger 4 run test 5 output loading test 8 diags 9 exit UUT power is okay Sat Jul 11 14:35:24 2015 space single step O run once (one test, all steps) F run, stop on fail G go (run tests N run, stop on fail, no print S scope (run, no print) C toggle comment printout + increase speed (less delay) - decrease speed (more delay)(slower) Q quit test scope (run, no print) ppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppp ppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppp pppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppFppppppppp ppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppp ppppppppppppppppppppppppppppppppppppppppppp space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C toggle comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT BAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBAABBAAAAAAAAAAAAAABBBBBBBBAB LETTER ALPSLFMDEEMCBFRSPKLEMFHRSCJLJKUHPNMBBNNVVRKRHUTDJUKANJHBTPDFSVDEVU SIDE 121212122121212121111111112212122222112222111221112112212112212212 DIRECTION IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIOOOOOOOIOOIOOIOOIOOOOIOOIIOOIIO all fails I II O was lo 00000000000000000000000000000000000000 00000000000000000000 00000 falling vvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvv vvvvvvvvvvvvvvvvvvvv vv v rising ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ ^^^^^^^^^^^^^^^^^^^^ ^^ ^ was hi 111111111111111111111111111111111111111111111111111111111111111 1 total fails 1, total passes 358 Main menu Sat Jul 11 14:35:44 2015 test file is: tests\m222.new delay is: 0 trigger is: 1 1 read test file 2 set test delay 3 set test trigger 4 run test 5 output loading test 8 diags 9 exit UUT power is okay Sat Jul 11 14:35:58 2015 space single step O run once (one test, all steps) F run, stop on fail G go (run tests N run, stop on fail, no print S scope (run, no print) C toggle comment printout + increase speed (less delay) - decrease speed (more delay)(slower) Q quit test step 1 100000000000000000000000000000000001111100010011011010100110111001 step 2 100000000000000000000000000000000001111100100011011010100110111001 step 3 100000000000000000000000000000000001111100000011011010100110111001 step 4 100000000000000000000000000000000001111100000100011010100110111001 step 5 100000000000000000000000000000000001111100000000011010100110111001 step 6 100000000000000000000000000000000001111100000000100010100110111001 step 7 100000000000000000000000000000000001111100000000000010100110111001 step 8 100000000000000000000000000000000001111100000000000101010110111001 step 9 100000000000000000000000000000000001111100000000000001010110111001 step 10 100000000000000000000000000000000001111100000000000001011000111001 step 11 100000000000000000000000000000000001111100000000000001010000111001 step 12 100000000000000000000000000000000001111100000000000001010001100001 step 13 100000000000000000000000000000000001111100000000000001010000100001 step 14 100000000000000000000000000000000001111100000000000001010000100001 step 15 100000000000010000000000000000000000111101000000000001010000100001 step 16 100000000000010010000000000000000000110111000000000001010000100001 step 17 100000000000010010000000000000000000110111111000000001010000100001 step 18 100000000000010010000000000000000000110111011000000001010000100001 step 19 100000000000010010000000000000000000110111011111000001010000100001 step 20 100000000000010010000000000000000000110111011011000001010000100001 step 21 100000000000010010000000000000000000110111011011111001010000100001 step 22 100000000000010010000000000000000000110111011011011001010000100001 step 23 100000000000010010000000000000000000110111011011011110100000100001 step 24 100000000000010010000000000000000000110111011011011010100000100001 step 25 100000000000010010000000000000000000110111011011011010101110100001 step 26 100000000000010010000000000000000000110111011011011010100110100001 step 27 100000000000010010000000000000000000110111011011011010100111111001 step 28 100000000000010010000000000000000000110111011011011010100110111001 step 29 100000000000000010000000000000000001110110011011011010100110111001 step 30 100000000000000000000000000000000001111100011011011010100110111001 step 31 100000000000000000000000000000000001111100011011011010100110111001 step 32 100001000000000000000000000000000001111100011011011010100110111001 step 33 100001100000000000000000000000000001111100011011011010100110111001 step 34 100001100100000000000000000000000001111100011011011010100110111001 step 35 100001100110000000000000000000000001111100011011011010100110111001 step 36 100001100110100000000000000000000001111100011011011010100110111001 step 37 100001100110100100000000000000000001111100011011011010100110111001 step 38 100001100110100100010000000000000001111100011011011010100110111001 step 39 100001100110100100011000000000000001111100011011011010100110111001 step 40 100001100110100100011010000000000001111100011011011010100110111001 step 41 100001100110100100011011000000000001111100011011011010100110111001 step 42 100001100110100100011011010000000001111100011011011010100110111001 step 43 100001100110100100011011011000000001111100011011011010100110111001 step 44 100001100110100100011011011010000001111100011011011010100110111001 step 45 100001100110100100011011011011000001111100011011011010100110111001 step 46 100001100110100100011011011011010001111100011011011010100110111001 step 47 100001100110100100011011011011011001111100011011011010100110111001 step 48 100001100110100100011011011011011101111100011011011010100110111001 step 49 110001100110100100011011011011011100110111011011011010100110111001 step 50 100001100110100100011011011011011101111100011011011010100110111001 step 51 101001100110100100011011011011011100110111011011011010100110111001 step 52 100001100110100100011011011011011101111100011011011010100110111001 step 53 100101100110100100011011011011011100110111011011011010100110111001 step 54 100001100110100100011011011011011101111100011011011010100110111001 step 55 100011100110100100011011011011011100110111011011011010100110111001 step 56 100001100110100100011011011011011101111100011011011010100110111001 step 57 100001110110100100011011011011011100110111011011011010100110111001 step 58 100001100110100100011011011011011101111100011011011010100110111001 step 59 100001101110100100011011011011011100110111011011011010100110111001 step 60 100001100110100100011011011011011101111100011011011010100110111001 step 61 100001100111100100011011011011011100111101011011011010100110111001 step 62 100001100110100100011011011011011101111100011011011010100110111001 step 63 100001100110110100011011011011011100111101011011011010100110111001 step 64 100001100110100100011011011011011101111100011011011010100110111001 step 65 100001100110101100011011011011011101110110011011011010100110111001 step 66 100001100110100100011011011011011101111100011011011010100110111001 step 67 100001100110100110011011011011011101110110011011011010100110111001 step 68 100001100110100100011011011011011101111100011011011010100110111001 step 69 100001100110100101011011011011011101001111011011011010100110111001 SLOT BAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBAABBAAAAAAAAAAAAAABBBBBBBBAB LETTER ALPSLFMDEEMCBFRSPKLEMFHRSCJLJKUHPNMBBNNVVRKRHUTDJUKANJHBTPDFSVDEVU SIDE 121212122121212121111111112212122222112222111221112112212112212212 DIRECTION IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIOOOOOOOIOOIOOIOOIOOOOIOOIIOOIIO changed: 0 1 00 step 70 100001100110100100011011011011011101011100011011011010100110111001 fail ^ space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C toggle comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit comment_flag is 1 space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C toggle comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit source: ; set pin BL1 to clear pin BB1 and pin BN1 AND-NOR OUTPUTS and set TAPE BUS 2 OUTPUT and TAPE BUS 3 OUTPUT source: 1 00 11 changed: 1 0 11 step 71 100001100110100100111011011011011101001111011011011010100110111001 SLOT BAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBAABBAAAAAAAAAAAAAABBBBBBBBAB LETTER ALPSLFMDEEMCBFRSPKLEMFHRSCJLJKUHPNMBBNNVVRKRHUTDJUKANJHBTPDFSVDEVU SIDE 121212122121212121111111112212122222112222111221112112212112212212 DIRECTION IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIOOOOOOOIOOIOOIOOIOOOOIOOIIOOIIO source: 0 11 00 changed: 0 1 00 step 72 100001100110100100011011011011011101011100011011011010100110111001 fail ^ source: ; set pin BF1 to clear pin BB1 and pin BN1 AND-NOR OUTPUTS and set TAPE BUS 2 OUTPUT and TAPE BUS 3 OUTPUT source: 1 00 11 changed: 1 0 11 step 73 100001100110100100011111011011011101001111011011011010100110111001 SLOT BAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBAABBAAAAAAAAAAAAAABBBBBBBBAB LETTER ALPSLFMDEEMCBFRSPKLEMFHRSCJLJKUHPNMBBNNVVRKRHUTDJUKANJHBTPDFSVDEVU SIDE 121212122121212121111111112212122222112222111221112112212112212212 DIRECTION IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIOOOOOOOIOOIOOIOOIOOOOIOOIIOOIIO source: 0 11 00 changed: 0 1 00 step 74 100001100110100100011011011011011101011100011011011010100110111001 fail ^ source: ; set pin BS1 to clear pin BB1 and pin BN1 AND-NOR OUTPUTS and set TAPE BUS 2 OUTPUT and TAPE BUS 3 OUTPUT source: 1 00 11 changed: 1 0 11 step 75 100001100110100100011011111011011101001111011011011010100110111001 SLOT BAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBAABBAAAAAAAAAAAAAABBBBBBBBAB LETTER ALPSLFMDEEMCBFRSPKLEMFHRSCJLJKUHPNMBBNNVVRKRHUTDJUKANJHBTPDFSVDEVU SIDE 121212122121212121111111112212122222112222111221112112212112212212 DIRECTION IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIOOOOOOOIOOIOOIOOIOOOOIOOIIOOIIO source: 0 11 00 changed: 0 1 00 step 76 100001100110100100011011011011011101011100011011011010100110111001 fail ^ SLOT BAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBAABBAAAAAAAAAAAAAABBBBBBBBAB LETTER ALPSLFMDEEMCBFRSPKLEMFHRSCJLJKUHPNMBBNNVVRKRHUTDJUKANJHBTPDFSVDEVU SIDE 121212122121212121111111112212122222112222111221112112212112212212 DIRECTION IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIOOOOOOOIOOIOOIOOIOOOOIOOIIOOIIO source: ; set pin BL2 to clear pin BB1 and pin BN1 AND-NOR OUTPUTS and set TAPE BUS 2 OUTPUT and TAPE BUS 3 OUTPUT source: 1 00 11 changed: 1 0 1 step 77 100001100110100100011011011111011101001110011011011010100110111001 fail ^ SLOT BAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBAABBAAAAAAAAAAAAAABBBBBBBBAB LETTER ALPSLFMDEEMCBFRSPKLEMFHRSCJLJKUHPNMBBNNVVRKRHUTDJUKANJHBTPDFSVDEVU SIDE 121212122121212121111111112212122222112222111221112112212112212212 DIRECTION IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIOOOOOOOIOOIOOIOOIOOOOIOOIIOOIIO source: 0 11 00 changed: 0 1 0 step 78 100001100110100100011011011011011101011100011011011010100110111001 fail ^ SLOT BAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBAABBAAAAAAAAAAAAAABBBBBBBBAB LETTER ALPSLFMDEEMCBFRSPKLEMFHRSCJLJKUHPNMBBNNVVRKRHUTDJUKANJHBTPDFSVDEVU SIDE 121212122121212121111111112212122222112222111221112112212112212212 DIRECTION IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIOOOOOOOIOOIOOIOOIOOOOIOOIIOOIIO source: ; set pin BU1 to clear pin BB1 and pin BN1 AND-NOR OUTPUTS and set TAPE BUS 2 OUTPUT and TAPE BUS 3 OUTPUT source: 1 00 11 changed: 1 0 1 step 79 100001100110100100011011011011111101001110011011011010100110111001 fail ^ SLOT BAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBAABBAAAAAAAAAAAAAABBBBBBBBAB LETTER ALPSLFMDEEMCBFRSPKLEMFHRSCJLJKUHPNMBBNNVVRKRHUTDJUKANJHBTPDFSVDEVU SIDE 121212122121212121111111112212122222112222111221112112212112212212 DIRECTION IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIOOOOOOOIOOIOOIOOIOOOOIOOIIOOIIO source: 0 11 00 changed: 0 1 0 step 80 100001100110100100011011011011011101011100011011011010100110111001 fail ^ SLOT BAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBAABBAAAAAAAAAAAAAABBBBBBBBAB LETTER ALPSLFMDEEMCBFRSPKLEMFHRSCJLJKUHPNMBBNNVVRKRHUTDJUKANJHBTPDFSVDEVU SIDE 121212122121212121111111112212122222112222111221112112212112212212 DIRECTION IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIOOOOOOOIOOIOOIOOIOOOOIOOIIOOIIO source: ; set pin BM2 to clear pin BB1 and TAPE BUS 3 OUTPUT source: 1 0 1 changed: 1 0 1 step 81 100001100110100100011011011011011111001110011011011010100110111001 fail ^ SLOT BAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBAABBAAAAAAAAAAAAAABBBBBBBBAB LETTER ALPSLFMDEEMCBFRSPKLEMFHRSCJLJKUHPNMBBNNVVRKRHUTDJUKANJHBTPDFSVDEVU SIDE 121212122121212121111111112212122222112222111221112112212112212212 DIRECTION IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIOOOOOOOIOOIOOIOOIOOOOIOOIIOOIIO source: 0 1 0 changed: 0 1 0 step 82 100001100110100100011011011011011101011100011011011010100110111001 fail ^ test 1: *** FAIL *************************** 10 steps failed SLOT BAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBAABBAAAAAAAAAAAAAABBBBBBBBAB LETTER ALPSLFMDEEMCBFRSPKLEMFHRSCJLJKUHPNMBBNNVVRKRHUTDJUKANJHBTPDFSVDEVU SIDE 121212122121212121111111112212122222112222111221112112212112212212 DIRECTION IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIOOOOOOOIOOIOOIOOIOOOOIOOIIOOIIO this fail O O all fails O O was hi 111111111111111111111111111111111111111111111111111111111111111 1 rising ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ ^^ ^^^^^^^^^^^^^^^^^^^^ ^^ falling vvvv vv v vv vvv v v v v vvvvv vvvv vvvvvvvvvvvvvvv vv was lo 00000000000000000000000000000000000000 00000000000000000000 0000 total fails 1, total passes 0 space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C toggle comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit source: ; all registers are unknown source: ; turn on C0, PHASE source: ; with no ENABLES, BUS2,BUS3 is 11, C2 is 1 source: 1000000000000000000000000000000000011111000XX0XX0XX0XXXX0XX01XX001 changed: 00 00 0 0 00 00 00 00 000 1 step 1 100000000000000000000000000000000001111100011011011010100110111001 source: source: ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; source: ; source: ; set all registers LOW source: ; source: ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; source: source: ; load TMA SETUP from tape bus (00) source: 100 changed: 100 step 2 100000000000000000000000000000000001111100100011011010100110111001 source: 0 changed: 0 step 3 100000000000000000000000000000000001111100000011011010100110111001 source: ; load TMA from tape bus (00) source: 100 changed: 100 step 4 100000000000000000000000000000000001111100000100011010100110111001 source: 0 changed: 0 step 5 100000000000000000000000000000000001111100000000011010100110111001 source: ; load TBN from tape bus (00) source: 100 changed: 100 step 6 100000000000000000000000000000000001111100000000100010100110111001 source: 0 changed: 0 step 7 100000000000000000000000000000000001111100000000000010100110111001 source: ; load TAC from tape bus (00) source: 10101 changed: 10101 step 8 100000000000000000000000000000000001111100000000000101010110111001 source: 0 changed: 0 step 9 100000000000000000000000000000000001111100000000000001010110111001 source: ; load TB from tape bus (00) source: 100 changed: 100 step 10 100000000000000000000000000000000001111100000000000001011000111001 source: 0 changed: 0 step 11 100000000000000000000000000000000001111100000000000001010000111001 source: ; load RWB from TB (JAMS CLEAR AND PRESET) source: 1 00 changed: 1 00 step 12 100000000000000000000000000000000001111100000000000001010001100001 source: 0 changed: 0 step 13 100000000000000000000000000000000001111100000000000001010000100001 source: ; (no change) source: 100000000000000000000000000000000001111100000000000001010000100001 changed: step 14 100000000000000000000000000000000001111100000000000001010000100001 source: source: source: ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; source: ; source: ; set all registers HIGH source: ; source: ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; source: source: ; set pin AF1 (AND with itself) to clear pin BB2 (AND-NOR output) and set pin BR2 TAPE BUS 3 OUTPUT source: 1 0 1 changed: 1 0 1 step 15 100000000000010000000000000000000000111101000000000001010000100001 source: ; set pin AP2 (AND with itself) to clear pin AN2 (AND-NOR output) and set pin BV2 TAPE BUS 2 OUTPUT source: 1 0 1 changed: 1 0 1 step 16 100000000000010010000000000000000000110111000000000001010000100001 source: source: source: ; load TMA SETUP from tape bus (11) source: 111 changed: 111 step 17 100000000000010010000000000000000000110111111000000001010000100001 source: 0 changed: 0 step 18 100000000000010010000000000000000000110111011000000001010000100001 source: ; load TMA from tape bus (11) source: 111 changed: 111 step 19 100000000000010010000000000000000000110111011111000001010000100001 source: 0 changed: 0 step 20 100000000000010010000000000000000000110111011011000001010000100001 source: ; load TBN from tape bus (11) source: 111 changed: 111 step 21 100000000000010010000000000000000000110111011011111001010000100001 source: 0 changed: 0 step 22 100000000000010010000000000000000000110111011011011001010000100001 source: ; load TAC from tape bus (11) source: 11010 changed: 11010 step 23 100000000000010010000000000000000000110111011011011110100000100001 source: 0 changed: 0 step 24 100000000000010010000000000000000000110111011011011010100000100001 source: ; load TB from tape bus (11) source: 111 changed: 111 step 25 100000000000010010000000000000000000110111011011011010101110100001 source: 0 changed: 0 step 26 100000000000010010000000000000000000110111011011011010100110100001 source: ; load RWB from TB (JAMS CLEAR AND PRESET) source: 1 11 changed: 1 11 step 27 100000000000010010000000000000000000110111011011011010100111111001 source: 0 changed: 0 step 28 100000000000010010000000000000000000110111011011011010100110111001 source: ; clear pin AF1 (AND with itself) to set pin BB2 (AND-NOR output) and clear pin BR2 TAPE BUS 3 OUTPUT source: 0 1 0 changed: 0 1 0 step 29 100000000000000010000000000000000001110110011011011010100110111001 source: ; clear pin AP2 (AND with itself) to set pin AN2 (AND-NOR output) and clear pin BV2 TAPE BUS 2 OUTPUT source: 0 1 0 changed: 0 1 0 step 30 100000000000000000000000000000000001111100011011011010100110111001 source: ; (no change) source: 100000000000000000000000000000000001111100011011011010100110111001 changed: step 31 100000000000000000000000000000000001111100011011011010100110111001 source: source: source: ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; source: ; source: ; test AND-NOR logic source: ; source: ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; source: source: ; (all registers are HIGH) source: ; set all pins HIGH except ENABLES source: source: ; set pin AF2 HIGH source: 1 changed: 1 step 32 100001000000000000000000000000000001111100011011011010100110111001 source: ; set pin AM1 HIGH source: 1 changed: 1 step 33 100001100000000000000000000000000001111100011011011010100110111001 source: ; set pin AE1 HIGH source: 1 changed: 1 step 34 100001100100000000000000000000000001111100011011011010100110111001 source: ; set pin AM2 HIGH source: 1 changed: 1 step 35 100001100110000000000000000000000001111100011011011010100110111001 source: ; set pin AB2 HIGH source: 1 changed: 1 step 36 100001100110100000000000000000000001111100011011011010100110111001 source: ; set pin AS1 HIGH source: 1 changed: 1 step 37 100001100110100100000000000000000001111100011011011010100110111001 source: ; set pin BE1 HIGH source: 1 changed: 1 step 38 100001100110100100010000000000000001111100011011011010100110111001 source: ; set pin BM1 HIGH source: 1 changed: 1 step 39 100001100110100100011000000000000001111100011011011010100110111001 source: ; set pin BH1 HIGH source: 1 changed: 1 step 40 100001100110100100011010000000000001111100011011011010100110111001 source: ; set pin BR1 HIGH source: 1 changed: 1 step 41 100001100110100100011011000000000001111100011011011010100110111001 source: ; set pin BC1 HIGH source: 1 changed: 1 step 42 100001100110100100011011010000000001111100011011011010100110111001 source: ; set pin BJ2 HIGH source: 1 changed: 1 step 43 100001100110100100011011011000000001111100011011011010100110111001 source: ; set pin BJ1 HIGH source: 1 changed: 1 step 44 100001100110100100011011011010000001111100011011011010100110111001 source: ; set pin BK2 HIGH source: 1 changed: 1 step 45 100001100110100100011011011011000001111100011011011010100110111001 source: ; set pin BH2 HIGH source: 1 changed: 1 step 46 100001100110100100011011011011010001111100011011011010100110111001 source: ; set pin BP2 HIGH source: 1 changed: 1 step 47 100001100110100100011011011011011001111100011011011010100110111001 source: ; set pin BN2 HIGH source: 1 changed: 1 step 48 100001100110100100011011011011011101111100011011011010100110111001 source: ; toggle each ENABLE source: source: ; set pin AL2 to clear pin BB2 and pin AN2 AND-NOR OUTPUTS and set TAPE BUS 2 OUTPUT and TAPE BUS 3 OUTPUT source: 1 0 0 11 changed: 1 0 0 11 step 49 110001100110100100011011011011011100110111011011011010100110111001 source: 0 1 1 00 changed: 0 1 1 00 step 50 100001100110100100011011011011011101111100011011011010100110111001 source: ; set pin AP1 to clear pin BB2 and pin AN2 AND-NOR OUTPUTS and set TAPE BUS 2 OUTPUT and TAPE BUS 3 OUTPUT source: 1 0 0 11 changed: 1 0 0 11 step 51 101001100110100100011011011011011100110111011011011010100110111001 source: 0 1 1 00 changed: 0 1 1 00 step 52 100001100110100100011011011011011101111100011011011010100110111001 source: ; set pin AS2 to clear pin BB2 and pin AN2 AND-NOR OUTPUTS and set TAPE BUS 2 OUTPUT and TAPE BUS 3 OUTPUT source: 1 0 0 11 changed: 1 0 0 11 step 53 100101100110100100011011011011011100110111011011011010100110111001 source: 0 1 1 00 changed: 0 1 1 00 step 54 100001100110100100011011011011011101111100011011011010100110111001 source: ; set pin AL1 to clear pin BB2 and pin AN2 AND-NOR OUTPUTS and set TAPE BUS 2 OUTPUT and TAPE BUS 3 OUTPUT source: 1 0 0 11 changed: 1 0 0 11 step 55 100011100110100100011011011011011100110111011011011010100110111001 source: 0 1 1 00 changed: 0 1 1 00 step 56 100001100110100100011011011011011101111100011011011010100110111001 source: ; set pin AL1 to clear pin BB2 and pin AN2 AND-NOR OUTPUTS and set TAPE BUS 2 OUTPUT and TAPE BUS 3 OUTPUT source: 1 0 0 11 changed: 1 0 0 11 step 57 100001110110100100011011011011011100110111011011011010100110111001 source: 0 1 1 00 changed: 0 1 1 00 step 58 100001100110100100011011011011011101111100011011011010100110111001 source: ; set pin AE2 to clear pin BB2 and pin AN2 AND-NOR OUTPUTS and set TAPE BUS 2 OUTPUT and TAPE BUS 3 OUTPUT source: 1 0 0 11 changed: 1 0 0 11 step 59 100001101110100100011011011011011100110111011011011010100110111001 source: 0 1 1 00 changed: 0 1 1 00 step 60 100001100110100100011011011011011101111100011011011010100110111001 source: ; set pin AC1 to clear pin BB2 and set TAPE BUS 3 OUTPUT source: 1 0 1 changed: 1 0 1 step 61 100001100111100100011011011011011100111101011011011010100110111001 source: 0 1 0 changed: 0 1 0 step 62 100001100110100100011011011011011101111100011011011010100110111001 source: ; set pin AF1 to clear pin BB2 and set TAPE BUS 3 OUTPUT source: 1 0 1 changed: 1 0 1 step 63 100001100110110100011011011011011100111101011011011010100110111001 source: 0 1 0 changed: 0 1 0 step 64 100001100110100100011011011011011101111100011011011010100110111001 source: ; set pin AR2 to clear pin AN2 AND-NOR OUTPUTS and set TAPE BUS 2 OUTPUT source: 1 0 1 changed: 1 0 1 step 65 100001100110101100011011011011011101110110011011011010100110111001 source: 0 1 0 changed: 0 1 0 step 66 100001100110100100011011011011011101111100011011011010100110111001 source: ; set pin AP2 to clear pin AN2 AND-NOR OUTPUTS and set TAPE BUS 2 OUTPUT source: 1 0 1 changed: 1 0 1 step 67 100001100110100110011011011011011101110110011011011010100110111001 source: 0 1 0 changed: 0 1 0 step 68 100001100110100100011011011011011101111100011011011010100110111001 source: source: ; set pin BK1 to clear pin BB1 and pin BN1 AND-NOR OUTPUTS and set TAPE BUS 2 OUTPUT and TAPE BUS 3 OUTPUT source: 1 00 11 changed: 1 00 11 step 69 100001100110100101011011011011011101001111011011011010100110111001 SLOT BAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBAABBAAAAAAAAAAAAAABBBBBBBBAB LETTER ALPSLFMDEEMCBFRSPKLEMFHRSCJLJKUHPNMBBNNVVRKRHUTDJUKANJHBTPDFSVDEVU SIDE 121212122121212121111111112212122222112222111221112112212112212212 DIRECTION IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIOOOOOOOIOOIOOIOOIOOOOIOOIIOOIIO source: 0 11 00 changed: 0 1 00 step 70 100001100110100100011011011011011101011100011011011010100110111001 fail ^ space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C toggle comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit scope (run, no print) FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C toggle comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit source: ; set pin BE1 HIGH source: 1 changed: 1 step 38 100001100110100100010000000000000001111100011011011010100110111001 source: ; set pin BM1 HIGH source: 1 changed: 1 step 39 100001100110100100011000000000000001111100011011011010100110111001 source: ; set pin BH1 HIGH source: 1 changed: 1 step 40 100001100110100100011010000000000001111100011011011010100110111001 source: ; set pin BR1 HIGH source: 1 changed: 1 step 41 100001100110100100011011000000000001111100011011011010100110111001 source: ; set pin BC1 HIGH source: 1 changed: 1 step 42 100001100110100100011011010000000001111100011011011010100110111001 source: ; set pin BJ2 HIGH source: 1 changed: 1 step 43 100001100110100100011011011000000001111100011011011010100110111001 source: ; set pin BJ1 HIGH source: 1 changed: 1 step 44 100001100110100100011011011010000001111100011011011010100110111001 source: ; set pin BK2 HIGH source: 1 changed: 1 step 45 100001100110100100011011011011000001111100011011011010100110111001 source: ; set pin BH2 HIGH source: 1 changed: 1 step 46 100001100110100100011011011011010001111100011011011010100110111001 source: ; set pin BP2 HIGH source: 1 changed: 1 step 47 100001100110100100011011011011011001111100011011011010100110111001 source: ; set pin BN2 HIGH source: 1 changed: 1 step 48 100001100110100100011011011011011101111100011011011010100110111001 source: ; toggle each ENABLE source: source: ; set pin AL2 to clear pin BB2 and pin AN2 AND-NOR OUTPUTS and set TAPE BUS 2 OUTPUT and TAPE BUS 3 OUTPUT source: 1 0 0 11 changed: 1 0 0 11 step 49 110001100110100100011011011011011100110111011011011010100110111001 source: 0 1 1 00 changed: 0 1 1 00 step 50 100001100110100100011011011011011101111100011011011010100110111001 source: ; set pin AP1 to clear pin BB2 and pin AN2 AND-NOR OUTPUTS and set TAPE BUS 2 OUTPUT and TAPE BUS 3 OUTPUT source: 1 0 0 11 changed: 1 0 0 11 step 51 101001100110100100011011011011011100110111011011011010100110111001 source: 0 1 1 00 changed: 0 1 1 00 step 52 100001100110100100011011011011011101111100011011011010100110111001 source: ; set pin AS2 to clear pin BB2 and pin AN2 AND-NOR OUTPUTS and set TAPE BUS 2 OUTPUT and TAPE BUS 3 OUTPUT source: 1 0 0 11 changed: 1 0 0 11 step 53 100101100110100100011011011011011100110111011011011010100110111001 source: 0 1 1 00 changed: 0 1 1 00 step 54 100001100110100100011011011011011101111100011011011010100110111001 source: ; set pin AL1 to clear pin BB2 and pin AN2 AND-NOR OUTPUTS and set TAPE BUS 2 OUTPUT and TAPE BUS 3 OUTPUT source: 1 0 0 11 changed: 1 0 0 11 step 55 100011100110100100011011011011011100110111011011011010100110111001 source: 0 1 1 00 changed: 0 1 1 00 step 56 100001100110100100011011011011011101111100011011011010100110111001 source: ; set pin AL1 to clear pin BB2 and pin AN2 AND-NOR OUTPUTS and set TAPE BUS 2 OUTPUT and TAPE BUS 3 OUTPUT source: 1 0 0 11 changed: 1 0 0 11 step 57 100001110110100100011011011011011100110111011011011010100110111001 source: 0 1 1 00 changed: 0 1 1 00 step 58 100001100110100100011011011011011101111100011011011010100110111001 source: ; set pin AE2 to clear pin BB2 and pin AN2 AND-NOR OUTPUTS and set TAPE BUS 2 OUTPUT and TAPE BUS 3 OUTPUT source: 1 0 0 11 changed: 1 0 0 11 step 59 100001101110100100011011011011011100110111011011011010100110111001 source: 0 1 1 00 changed: 0 1 1 00 step 60 100001100110100100011011011011011101111100011011011010100110111001 source: ; set pin AC1 to clear pin BB2 and set TAPE BUS 3 OUTPUT source: 1 0 1 changed: 1 0 1 step 61 100001100111100100011011011011011100111101011011011010100110111001 source: 0 1 0 changed: 0 1 0 step 62 100001100110100100011011011011011101111100011011011010100110111001 source: ; set pin AF1 to clear pin BB2 and set TAPE BUS 3 OUTPUT source: 1 0 1 changed: 1 0 1 step 63 100001100110110100011011011011011100111101011011011010100110111001 source: 0 1 0 changed: 0 1 0 step 64 100001100110100100011011011011011101111100011011011010100110111001 source: ; set pin AR2 to clear pin AN2 AND-NOR OUTPUTS and set TAPE BUS 2 OUTPUT source: 1 0 1 changed: 1 0 1 step 65 100001100110101100011011011011011101110110011011011010100110111001 source: 0 1 0 changed: 0 1 0 step 66 100001100110100100011011011011011101111100011011011010100110111001 source: ; set pin AP2 to clear pin AN2 AND-NOR OUTPUTS and set TAPE BUS 2 OUTPUT source: 1 0 1 changed: 1 0 1 step 67 100001100110100110011011011011011101110110011011011010100110111001 source: 0 1 0 changed: 0 1 0 step 68 100001100110100100011011011011011101111100011011011010100110111001 source: source: ; set pin BK1 to clear pin BB1 and pin BN1 AND-NOR OUTPUTS and set TAPE BUS 2 OUTPUT and TAPE BUS 3 OUTPUT source: 1 00 11 changed: 1 00 11 step 69 100001100110100101011011011011011101001111011011011010100110111001 SLOT BAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBAABBAAAAAAAAAAAAAABBBBBBBBAB LETTER ALPSLFMDEEMCBFRSPKLEMFHRSCJLJKUHPNMBBNNVVRKRHUTDJUKANJHBTPDFSVDEVU SIDE 121212122121212121111111112212122222112222111221112112212112212212 DIRECTION IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIOOOOOOOIOOIOOIOOIOOOOIOOIIOOIIO source: 0 11 00 changed: 0 1 00 step 70 100001100110100100011011011011011101011100011011011010100110111001 fail ^ space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C toggle comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit source: ; set pin BL1 to clear pin BB1 and pin BN1 AND-NOR OUTPUTS and set TAPE BUS 2 OUTPUT and TAPE BUS 3 OUTPUT source: 1 00 11 changed: 1 0 11 step 71 100001100110100100111011011011011101001111011011011010100110111001 SLOT BAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBAABBAAAAAAAAAAAAAABBBBBBBBAB LETTER ALPSLFMDEEMCBFRSPKLEMFHRSCJLJKUHPNMBBNNVVRKRHUTDJUKANJHBTPDFSVDEVU SIDE 121212122121212121111111112212122222112222111221112112212112212212 DIRECTION IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIOOOOOOOIOOIOOIOOIOOOOIOOIIOOIIO source: 0 11 00 changed: 0 1 00 step 72 100001100110100100011011011011011101011100011011011010100110111001 fail ^ space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C toggle comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit source: ; set pin BF1 to clear pin BB1 and pin BN1 AND-NOR OUTPUTS and set TAPE BUS 2 OUTPUT and TAPE BUS 3 OUTPUT source: 1 00 11 changed: 1 0 11 step 73 100001100110100100011111011011011101001111011011011010100110111001 SLOT BAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBAABBAAAAAAAAAAAAAABBBBBBBBAB LETTER ALPSLFMDEEMCBFRSPKLEMFHRSCJLJKUHPNMBBNNVVRKRHUTDJUKANJHBTPDFSVDEVU SIDE 121212122121212121111111112212122222112222111221112112212112212212 DIRECTION IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIOOOOOOOIOOIOOIOOIOOOOIOOIIOOIIO source: 0 11 00 changed: 0 1 00 step 74 100001100110100100011011011011011101011100011011011010100110111001 fail ^ space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C toggle comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit source: ; set pin BS1 to clear pin BB1 and pin BN1 AND-NOR OUTPUTS and set TAPE BUS 2 OUTPUT and TAPE BUS 3 OUTPUT source: 1 00 11 changed: 1 0 11 step 75 100001100110100100011011111011011101001111011011011010100110111001 SLOT BAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBAABBAAAAAAAAAAAAAABBBBBBBBAB LETTER ALPSLFMDEEMCBFRSPKLEMFHRSCJLJKUHPNMBBNNVVRKRHUTDJUKANJHBTPDFSVDEVU SIDE 121212122121212121111111112212122222112222111221112112212112212212 DIRECTION IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIOOOOOOOIOOIOOIOOIOOOOIOOIIOOIIO source: 0 11 00 changed: 0 1 00 step 76 100001100110100100011011011011011101011100011011011010100110111001 fail ^ space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C toggle comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT BAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBAABBAAAAAAAAAAAAAABBBBBBBBAB LETTER ALPSLFMDEEMCBFRSPKLEMFHRSCJLJKUHPNMBBNNVVRKRHUTDJUKANJHBTPDFSVDEVU SIDE 121212122121212121111111112212122222112222111221112112212112212212 DIRECTION IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIOOOOOOOIOOIOOIOOIOOOOIOOIIOOIIO source: ; set pin BL2 to clear pin BB1 and pin BN1 AND-NOR OUTPUTS and set TAPE BUS 2 OUTPUT and TAPE BUS 3 OUTPUT source: 1 00 11 changed: 1 0 1 step 77 100001100110100100011011011111011101001110011011011010100110111001 fail ^ space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C toggle comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT BAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBAABBAAAAAAAAAAAAAABBBBBBBBAB LETTER ALPSLFMDEEMCBFRSPKLEMFHRSCJLJKUHPNMBBNNVVRKRHUTDJUKANJHBTPDFSVDEVU SIDE 121212122121212121111111112212122222112222111221112112212112212212 DIRECTION IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIOOOOOOOIOOIOOIOOIOOOOIOOIIOOIIO source: 0 11 00 changed: 0 1 0 step 78 100001100110100100011011011011011101011100011011011010100110111001 fail ^ space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C toggle comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT BAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBAABBAAAAAAAAAAAAAABBBBBBBBAB LETTER ALPSLFMDEEMCBFRSPKLEMFHRSCJLJKUHPNMBBNNVVRKRHUTDJUKANJHBTPDFSVDEVU SIDE 121212122121212121111111112212122222112222111221112112212112212212 DIRECTION IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIOOOOOOOIOOIOOIOOIOOOOIOOIIOOIIO source: ; set pin BU1 to clear pin BB1 and pin BN1 AND-NOR OUTPUTS and set TAPE BUS 2 OUTPUT and TAPE BUS 3 OUTPUT source: 1 00 11 changed: 1 0 1 step 79 100001100110100100011011011011111101001110011011011010100110111001 fail ^ space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C toggle comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT BAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBAABBAAAAAAAAAAAAAABBBBBBBBAB LETTER ALPSLFMDEEMCBFRSPKLEMFHRSCJLJKUHPNMBBNNVVRKRHUTDJUKANJHBTPDFSVDEVU SIDE 121212122121212121111111112212122222112222111221112112212112212212 DIRECTION IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIOOOOOOOIOOIOOIOOIOOOOIOOIIOOIIO source: 0 11 00 changed: 0 1 0 step 80 100001100110100100011011011011011101011100011011011010100110111001 fail ^ space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C toggle comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT BAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBAABBAAAAAAAAAAAAAABBBBBBBBAB LETTER ALPSLFMDEEMCBFRSPKLEMFHRSCJLJKUHPNMBBNNVVRKRHUTDJUKANJHBTPDFSVDEVU SIDE 121212122121212121111111112212122222112222111221112112212112212212 DIRECTION IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIOOOOOOOIOOIOOIOOIOOOOIOOIIOOIIO source: ; set pin BM2 to clear pin BB1 and TAPE BUS 3 OUTPUT source: 1 0 1 changed: 1 0 1 step 81 100001100110100100011011011011011111001110011011011010100110111001 fail ^ space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C toggle comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT BAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBAABBAAAAAAAAAAAAAABBBBBBBBAB LETTER ALPSLFMDEEMCBFRSPKLEMFHRSCJLJKUHPNMBBNNVVRKRHUTDJUKANJHBTPDFSVDEVU SIDE 121212122121212121111111112212122222112222111221112112212112212212 DIRECTION IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIOOOOOOOIOOIOOIOOIOOOOIOOIIOOIIO source: 0 1 0 changed: 0 1 0 step 82 100001100110100100011011011011011101011100011011011010100110111001 fail ^ test 77: *** FAIL *************************** 10 steps failed SLOT BAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBAABBAAAAAAAAAAAAAABBBBBBBBAB LETTER ALPSLFMDEEMCBFRSPKLEMFHRSCJLJKUHPNMBBNNVVRKRHUTDJUKANJHBTPDFSVDEVU SIDE 121212122121212121111111112212122222112222111221112112212112212212 DIRECTION IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIOOOOOOOIOOIOOIOOIOOOOIOOIIOOIIO this fail O O all fails O O was hi 111111111111111111111111111111111111111111111111111111111111111 1 rising ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ ^^^^^^^^^^^^^^^^^^^^ ^^ falling vvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvv vvvvvvvvvvvvvvvvvvvv vv was lo 00000000000000000000000000000000000000 00000000000000000000 0000 total fails 77, total passes 0 space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C toggle comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit up to this point: PINS that are always low 64 I BE2 SHIFT RWB (SHIFTS PIN AV1 INTO RWB 3, SHIFTS RWB3 TO RWB2) (RISING CLOCK) 65 I AV1 RWB IN (SHIFTED INTO RWB 2) PINS that are always high 1 I BA1 CARRY IN-N, (TO E9-5 7482 C0) C-N TO ADDER2 40 O AV2 CARRY OUT-N (E9-10 7482 C2) 61 I BS2 PHASE (SELECTS POLARITY OF RWB OUT, 0 -> INVERTED) 66 O BU2 +3.5V space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C toggle comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit failure mode analysis: pin: 37 O BB1 AND-NOR OUTPUT, (DRIVES E9-3 7482 B1) TO ADDER3 INPUT SLOT BAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBAABBAAAAAAAAAAAAAABBBBBBBBAB LETTER ALPSLFMDEEMCBFRSPKLEMFHRSCJLJKUHPNMBBNNVVRKRHUTDJUKANJHBTPDFSVDEVU SIDE 121212122121212121111111112212122222112222111221112112212112212212 DIRECTION IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIOOOOOOOIOOIOOIOOIOOOOIOOIIOOIIO fails LO: 1 11 11 1 1 11 11 11 11 11111 1111 11 11 11 1 1 11 111 1 fails LO: 0000 00 0 00 000 0 0 0 0 0 0 000 0 0 0 0 00 0 00 fails HI: fails HI: pin: 42 O BR2 TAPE BUS 3 OUTPUT (INVERTED ADDER3 SUM-N (E9-1 7482 SUM1) SLOT BAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBAABBAAAAAAAAAAAAAABBBBBBBBAB LETTER ALPSLFMDEEMCBFRSPKLEMFHRSCJLJKUHPNMBBNNVVRKRHUTDJUKANJHBTPDFSVDEVU SIDE 121212122121212121111111112212122222112222111221112112212112212212 DIRECTION IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIOOOOOOOIOOIOOIOOIOOOOIOOIIOOIIO fails LO: 1 11 11 1 1 11 11 111111111 1 111 11 11 11 1 1 11 111 1 fails LO: 0000 00 0 00 000 0 0 0 0 0 00 0 0 0 0 0 00 0 00 fails HI: fails HI: space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C toggle comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT BAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBAABBAAAAAAAAAAAAAABBBBBBBBAB LETTER ALPSLFMDEEMCBFRSPKLEMFHRSCJLJKUHPNMBBNNVVRKRHUTDJUKANJHBTPDFSVDEVU SIDE 121212122121212121111111112212122222112222111221112112212112212212 DIRECTION IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIOOOOOOOIOOIOOIOOIOOOOIOOIIOOIIO source: ; all registers are unknown source: ; turn on C0, PHASE source: ; with no ENABLES, BUS2,BUS3 is 11, C2 is 1 source: 1000000000000000000000000000000000011111000XX0XX0XX0XXXX0XX01XX001 changed: 00 00 0 0 00 00 00 00 000 1 step 1 100000000000000000000000000000000001111100011011011010100110111001 okay space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C toggle comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit source: source: ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; source: ; source: ; set all registers LOW source: ; source: ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; source: source: ; load TMA SETUP from tape bus (00) source: 100 changed: 100 step 2 100000000000000000000000000000000001111100100011011010100110111001 source: 0 changed: 0 step 3 100000000000000000000000000000000001111100000011011010100110111001 source: ; load TMA from tape bus (00) source: 100 changed: 100 step 4 100000000000000000000000000000000001111100000100011010100110111001 source: 0 changed: 0 step 5 100000000000000000000000000000000001111100000000011010100110111001 source: ; load TBN from tape bus (00) source: 100 changed: 100 step 6 100000000000000000000000000000000001111100000000100010100110111001 source: 0 changed: 0 step 7 100000000000000000000000000000000001111100000000000010100110111001 source: ; load TAC from tape bus (00) source: 10101 changed: 10101 step 8 100000000000000000000000000000000001111100000000000101010110111001 source: 0 changed: 0 step 9 100000000000000000000000000000000001111100000000000001010110111001 source: ; load TB from tape bus (00) source: 100 changed: 100 step 10 100000000000000000000000000000000001111100000000000001011000111001 source: 0 changed: 0 step 11 100000000000000000000000000000000001111100000000000001010000111001 source: ; load RWB from TB (JAMS CLEAR AND PRESET) source: 1 00 changed: 1 00 step 12 100000000000000000000000000000000001111100000000000001010001100001 source: 0 changed: 0 step 13 100000000000000000000000000000000001111100000000000001010000100001 source: ; (no change) source: 100000000000000000000000000000000001111100000000000001010000100001 changed: step 14 100000000000000000000000000000000001111100000000000001010000100001 source: source: source: ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; source: ; source: ; set all registers HIGH source: ; source: ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; source: source: ; set pin AF1 (AND with itself) to clear pin BB2 (AND-NOR output) and set pin BR2 TAPE BUS 3 OUTPUT source: 1 0 1 changed: 1 0 1 step 15 100000000000010000000000000000000000111101000000000001010000100001 source: ; set pin AP2 (AND with itself) to clear pin AN2 (AND-NOR output) and set pin BV2 TAPE BUS 2 OUTPUT source: 1 0 1 changed: 1 0 1 step 16 100000000000010010000000000000000000110111000000000001010000100001 source: source: source: ; load TMA SETUP from tape bus (11) source: 111 changed: 111 step 17 100000000000010010000000000000000000110111111000000001010000100001 source: 0 changed: 0 step 18 100000000000010010000000000000000000110111011000000001010000100001 source: ; load TMA from tape bus (11) source: 111 changed: 111 step 19 100000000000010010000000000000000000110111011111000001010000100001 source: 0 changed: 0 step 20 100000000000010010000000000000000000110111011011000001010000100001 source: ; load TBN from tape bus (11) source: 111 changed: 111 step 21 100000000000010010000000000000000000110111011011111001010000100001 source: 0 changed: 0 step 22 100000000000010010000000000000000000110111011011011001010000100001 source: ; load TAC from tape bus (11) source: 11010 changed: 11010 step 23 100000000000010010000000000000000000110111011011011110100000100001 source: 0 changed: 0 step 24 100000000000010010000000000000000000110111011011011010100000100001 source: ; load TB from tape bus (11) source: 111 changed: 111 step 25 100000000000010010000000000000000000110111011011011010101110100001 source: 0 changed: 0 step 26 100000000000010010000000000000000000110111011011011010100110100001 source: ; load RWB from TB (JAMS CLEAR AND PRESET) source: 1 11 changed: 1 11 step 27 100000000000010010000000000000000000110111011011011010100111111001 source: 0 changed: 0 step 28 100000000000010010000000000000000000110111011011011010100110111001 source: ; clear pin AF1 (AND with itself) to set pin BB2 (AND-NOR output) and clear pin BR2 TAPE BUS 3 OUTPUT source: 0 1 0 changed: 0 1 0 step 29 100000000000000010000000000000000001110110011011011010100110111001 source: ; clear pin AP2 (AND with itself) to set pin AN2 (AND-NOR output) and clear pin BV2 TAPE BUS 2 OUTPUT source: 0 1 0 changed: 0 1 0 step 30 100000000000000000000000000000000001111100011011011010100110111001 source: ; (no change) source: 100000000000000000000000000000000001111100011011011010100110111001 changed: step 31 100000000000000000000000000000000001111100011011011010100110111001 source: source: source: ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; source: ; source: ; test AND-NOR logic source: ; source: ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; source: source: ; (all registers are HIGH) source: ; set all pins HIGH except ENABLES source: source: ; set pin AF2 HIGH source: 1 changed: 1 step 32 100001000000000000000000000000000001111100011011011010100110111001 source: ; set pin AM1 HIGH source: 1 changed: 1 step 33 100001100000000000000000000000000001111100011011011010100110111001 source: ; set pin AE1 HIGH source: 1 changed: 1 step 34 100001100100000000000000000000000001111100011011011010100110111001 source: ; set pin AM2 HIGH source: 1 changed: 1 step 35 100001100110000000000000000000000001111100011011011010100110111001 source: ; set pin AB2 HIGH source: 1 changed: 1 step 36 100001100110100000000000000000000001111100011011011010100110111001 source: ; set pin AS1 HIGH source: 1 changed: 1 step 37 100001100110100100000000000000000001111100011011011010100110111001 source: ; set pin BE1 HIGH source: 1 changed: 1 step 38 100001100110100100010000000000000001111100011011011010100110111001 source: ; set pin BM1 HIGH source: 1 changed: 1 step 39 100001100110100100011000000000000001111100011011011010100110111001 source: ; set pin BH1 HIGH source: 1 changed: 1 step 40 100001100110100100011010000000000001111100011011011010100110111001 source: ; set pin BR1 HIGH source: 1 changed: 1 step 41 100001100110100100011011000000000001111100011011011010100110111001 source: ; set pin BC1 HIGH source: 1 changed: 1 step 42 100001100110100100011011010000000001111100011011011010100110111001 source: ; set pin BJ2 HIGH source: 1 changed: 1 step 43 100001100110100100011011011000000001111100011011011010100110111001 source: ; set pin BJ1 HIGH source: 1 changed: 1 step 44 100001100110100100011011011010000001111100011011011010100110111001 source: ; set pin BK2 HIGH source: 1 changed: 1 step 45 100001100110100100011011011011000001111100011011011010100110111001 source: ; set pin BH2 HIGH source: 1 changed: 1 step 46 100001100110100100011011011011010001111100011011011010100110111001 source: ; set pin BP2 HIGH source: 1 changed: 1 step 47 100001100110100100011011011011011001111100011011011010100110111001 source: ; set pin BN2 HIGH source: 1 changed: 1 step 48 100001100110100100011011011011011101111100011011011010100110111001 source: ; toggle each ENABLE source: source: ; set pin AL2 to clear pin BB2 and pin AN2 AND-NOR OUTPUTS and set TAPE BUS 2 OUTPUT and TAPE BUS 3 OUTPUT source: 1 0 0 11 changed: 1 0 0 11 step 49 110001100110100100011011011011011100110111011011011010100110111001 source: 0 1 1 00 changed: 0 1 1 00 step 50 100001100110100100011011011011011101111100011011011010100110111001 source: ; set pin AP1 to clear pin BB2 and pin AN2 AND-NOR OUTPUTS and set TAPE BUS 2 OUTPUT and TAPE BUS 3 OUTPUT source: 1 0 0 11 changed: 1 0 0 11 step 51 101001100110100100011011011011011100110111011011011010100110111001 source: 0 1 1 00 changed: 0 1 1 00 step 52 100001100110100100011011011011011101111100011011011010100110111001 source: ; set pin AS2 to clear pin BB2 and pin AN2 AND-NOR OUTPUTS and set TAPE BUS 2 OUTPUT and TAPE BUS 3 OUTPUT source: 1 0 0 11 changed: 1 0 0 11 step 53 100101100110100100011011011011011100110111011011011010100110111001 source: 0 1 1 00 changed: 0 1 1 00 step 54 100001100110100100011011011011011101111100011011011010100110111001 source: ; set pin AL1 to clear pin BB2 and pin AN2 AND-NOR OUTPUTS and set TAPE BUS 2 OUTPUT and TAPE BUS 3 OUTPUT source: 1 0 0 11 changed: 1 0 0 11 step 55 100011100110100100011011011011011100110111011011011010100110111001 source: 0 1 1 00 changed: 0 1 1 00 step 56 100001100110100100011011011011011101111100011011011010100110111001 source: ; set pin AL1 to clear pin BB2 and pin AN2 AND-NOR OUTPUTS and set TAPE BUS 2 OUTPUT and TAPE BUS 3 OUTPUT source: 1 0 0 11 changed: 1 0 0 11 step 57 100001110110100100011011011011011100110111011011011010100110111001 source: 0 1 1 00 changed: 0 1 1 00 step 58 100001100110100100011011011011011101111100011011011010100110111001 source: ; set pin AE2 to clear pin BB2 and pin AN2 AND-NOR OUTPUTS and set TAPE BUS 2 OUTPUT and TAPE BUS 3 OUTPUT source: 1 0 0 11 changed: 1 0 0 11 step 59 100001101110100100011011011011011100110111011011011010100110111001 source: 0 1 1 00 changed: 0 1 1 00 step 60 100001100110100100011011011011011101111100011011011010100110111001 source: ; set pin AC1 to clear pin BB2 and set TAPE BUS 3 OUTPUT source: 1 0 1 changed: 1 0 1 step 61 100001100111100100011011011011011100111101011011011010100110111001 source: 0 1 0 changed: 0 1 0 step 62 100001100110100100011011011011011101111100011011011010100110111001 source: ; set pin AF1 to clear pin BB2 and set TAPE BUS 3 OUTPUT source: 1 0 1 changed: 1 0 1 step 63 100001100110110100011011011011011100111101011011011010100110111001 source: 0 1 0 changed: 0 1 0 step 64 100001100110100100011011011011011101111100011011011010100110111001 source: ; set pin AR2 to clear pin AN2 AND-NOR OUTPUTS and set TAPE BUS 2 OUTPUT source: 1 0 1 changed: 1 0 1 step 65 100001100110101100011011011011011101110110011011011010100110111001 source: 0 1 0 changed: 0 1 0 step 66 100001100110100100011011011011011101111100011011011010100110111001 source: ; set pin AP2 to clear pin AN2 AND-NOR OUTPUTS and set TAPE BUS 2 OUTPUT source: 1 0 1 changed: 1 0 1 step 67 100001100110100110011011011011011101110110011011011010100110111001 source: 0 1 0 changed: 0 1 0 step 68 100001100110100100011011011011011101111100011011011010100110111001 source: source: ; set pin BK1 to clear pin BB1 and pin BN1 AND-NOR OUTPUTS and set TAPE BUS 2 OUTPUT and TAPE BUS 3 OUTPUT source: 1 00 11 changed: 1 00 11 step 69 100001100110100101011011011011011101001111011011011010100110111001 SLOT BAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBAABBAAAAAAAAAAAAAABBBBBBBBAB LETTER ALPSLFMDEEMCBFRSPKLEMFHRSCJLJKUHPNMBBNNVVRKRHUTDJUKANJHBTPDFSVDEVU SIDE 121212122121212121111111112212122222112222111221112112212112212212 DIRECTION IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIOOOOOOOIOOIOOIOOIOOOOIOOIIOOIIO source: 0 11 00 changed: 0 1 00 step 70 100001100110100100011011011011011101011100011011011010100110111001 fail ^ source: ; set pin BL1 to clear pin BB1 and pin BN1 AND-NOR OUTPUTS and set TAPE BUS 2 OUTPUT and TAPE BUS 3 OUTPUT source: 1 00 11 changed: 1 0 11 step 71 100001100110100100111011011011011101001111011011011010100110111001 SLOT BAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBAABBAAAAAAAAAAAAAABBBBBBBBAB LETTER ALPSLFMDEEMCBFRSPKLEMFHRSCJLJKUHPNMBBNNVVRKRHUTDJUKANJHBTPDFSVDEVU SIDE 121212122121212121111111112212122222112222111221112112212112212212 DIRECTION IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIOOOOOOOIOOIOOIOOIOOOOIOOIIOOIIO source: 0 11 00 changed: 0 1 00 step 72 100001100110100100011011011011011101011100011011011010100110111001 fail ^ source: ; set pin BF1 to clear pin BB1 and pin BN1 AND-NOR OUTPUTS and set TAPE BUS 2 OUTPUT and TAPE BUS 3 OUTPUT source: 1 00 11 changed: 1 0 11 step 73 100001100110100100011111011011011101001111011011011010100110111001 SLOT BAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBAABBAAAAAAAAAAAAAABBBBBBBBAB LETTER ALPSLFMDEEMCBFRSPKLEMFHRSCJLJKUHPNMBBNNVVRKRHUTDJUKANJHBTPDFSVDEVU SIDE 121212122121212121111111112212122222112222111221112112212112212212 DIRECTION IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIOOOOOOOIOOIOOIOOIOOOOIOOIIOOIIO source: 0 11 00 changed: 0 1 00 step 74 100001100110100100011011011011011101011100011011011010100110111001 fail ^ source: ; set pin BS1 to clear pin BB1 and pin BN1 AND-NOR OUTPUTS and set TAPE BUS 2 OUTPUT and TAPE BUS 3 OUTPUT source: 1 00 11 changed: 1 0 11 step 75 100001100110100100011011111011011101001111011011011010100110111001 SLOT BAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBAABBAAAAAAAAAAAAAABBBBBBBBAB LETTER ALPSLFMDEEMCBFRSPKLEMFHRSCJLJKUHPNMBBNNVVRKRHUTDJUKANJHBTPDFSVDEVU SIDE 121212122121212121111111112212122222112222111221112112212112212212 DIRECTION IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIOOOOOOOIOOIOOIOOIOOOOIOOIIOOIIO source: 0 11 00 changed: 0 1 00 step 76 100001100110100100011011011011011101011100011011011010100110111001 fail ^ SLOT BAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBAABBAAAAAAAAAAAAAABBBBBBBBAB LETTER ALPSLFMDEEMCBFRSPKLEMFHRSCJLJKUHPNMBBNNVVRKRHUTDJUKANJHBTPDFSVDEVU SIDE 121212122121212121111111112212122222112222111221112112212112212212 DIRECTION IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIOOOOOOOIOOIOOIOOIOOOOIOOIIOOIIO source: ; set pin BL2 to clear pin BB1 and pin BN1 AND-NOR OUTPUTS and set TAPE BUS 2 OUTPUT and TAPE BUS 3 OUTPUT source: 1 00 11 changed: 1 0 1 step 77 100001100110100100011011011111011101001110011011011010100110111001 fail ^ SLOT BAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBAABBAAAAAAAAAAAAAABBBBBBBBAB LETTER ALPSLFMDEEMCBFRSPKLEMFHRSCJLJKUHPNMBBNNVVRKRHUTDJUKANJHBTPDFSVDEVU SIDE 121212122121212121111111112212122222112222111221112112212112212212 DIRECTION IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIOOOOOOOIOOIOOIOOIOOOOIOOIIOOIIO source: 0 11 00 changed: 0 1 0 step 78 100001100110100100011011011011011101011100011011011010100110111001 fail ^ SLOT BAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBAABBAAAAAAAAAAAAAABBBBBBBBAB LETTER ALPSLFMDEEMCBFRSPKLEMFHRSCJLJKUHPNMBBNNVVRKRHUTDJUKANJHBTPDFSVDEVU SIDE 121212122121212121111111112212122222112222111221112112212112212212 DIRECTION IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIOOOOOOOIOOIOOIOOIOOOOIOOIIOOIIO source: ; set pin BU1 to clear pin BB1 and pin BN1 AND-NOR OUTPUTS and set TAPE BUS 2 OUTPUT and TAPE BUS 3 OUTPUT source: 1 00 11 changed: 1 0 1 step 79 100001100110100100011011011011111101001110011011011010100110111001 fail ^ SLOT BAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBAABBAAAAAAAAAAAAAABBBBBBBBAB LETTER ALPSLFMDEEMCBFRSPKLEMFHRSCJLJKUHPNMBBNNVVRKRHUTDJUKANJHBTPDFSVDEVU SIDE 121212122121212121111111112212122222112222111221112112212112212212 DIRECTION IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIOOOOOOOIOOIOOIOOIOOOOIOOIIOOIIO source: 0 11 00 changed: 0 1 0 step 80 100001100110100100011011011011011101011100011011011010100110111001 fail ^ SLOT BAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBAABBAAAAAAAAAAAAAABBBBBBBBAB LETTER ALPSLFMDEEMCBFRSPKLEMFHRSCJLJKUHPNMBBNNVVRKRHUTDJUKANJHBTPDFSVDEVU SIDE 121212122121212121111111112212122222112222111221112112212112212212 DIRECTION IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIOOOOOOOIOOIOOIOOIOOOOIOOIIOOIIO source: ; set pin BM2 to clear pin BB1 and TAPE BUS 3 OUTPUT source: 1 0 1 changed: 1 0 1 step 81 100001100110100100011011011011011111001110011011011010100110111001 fail ^ SLOT BAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBAABBAAAAAAAAAAAAAABBBBBBBBAB LETTER ALPSLFMDEEMCBFRSPKLEMFHRSCJLJKUHPNMBBNNVVRKRHUTDJUKANJHBTPDFSVDEVU SIDE 121212122121212121111111112212122222112222111221112112212112212212 DIRECTION IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIOOOOOOOIOOIOOIOOIOOOOIOOIIOOIIO source: 0 1 0 changed: 0 1 0 step 82 100001100110100100011011011011011101011100011011011010100110111001 fail ^ test 78: *** FAIL *************************** 10 steps failed SLOT BAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBAABBAAAAAAAAAAAAAABBBBBBBBAB LETTER ALPSLFMDEEMCBFRSPKLEMFHRSCJLJKUHPNMBBNNVVRKRHUTDJUKANJHBTPDFSVDEVU SIDE 121212122121212121111111112212122222112222111221112112212112212212 DIRECTION IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIOOOOOOOIOOIOOIOOIOOOOIOOIIOOIIO this fail O O all fails O O was hi 111111111111111111111111111111111111111111111111111111111111111 1 rising ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ ^^^^^^^^^^^^^^^^^^^^ ^^ falling vvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvv vvvvvvvvvvvvvvvvvvvv vv was lo 00000000000000000000000000000000000000 00000000000000000000 0000 total fails 78, total passes 0 space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C toggle comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit source: ; all registers are unknown source: ; turn on C0, PHASE source: ; with no ENABLES, BUS2,BUS3 is 11, C2 is 1 source: 1000000000000000000000000000000000011111000XX0XX0XX0XXXX0XX01XX001 changed: 00 00 0 0 00 00 00 00 000 1 step 1 100000000000000000000000000000000001111100011011011010100110111001 source: source: ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; source: ; source: ; set all registers LOW source: ; source: ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; source: source: ; load TMA SETUP from tape bus (00) source: 100 changed: 100 step 2 100000000000000000000000000000000001111100100011011010100110111001 source: 0 changed: 0 step 3 100000000000000000000000000000000001111100000011011010100110111001 source: ; load TMA from tape bus (00) source: 100 changed: 100 step 4 100000000000000000000000000000000001111100000100011010100110111001 source: 0 changed: 0 step 5 100000000000000000000000000000000001111100000000011010100110111001 source: ; load TBN from tape bus (00) source: 100 changed: 100 step 6 100000000000000000000000000000000001111100000000100010100110111001 source: 0 changed: 0 step 7 100000000000000000000000000000000001111100000000000010100110111001 source: ; load TAC from tape bus (00) source: 10101 changed: 10101 step 8 100000000000000000000000000000000001111100000000000101010110111001 source: 0 changed: 0 step 9 100000000000000000000000000000000001111100000000000001010110111001 source: ; load TB from tape bus (00) source: 100 changed: 100 step 10 100000000000000000000000000000000001111100000000000001011000111001 source: 0 changed: 0 step 11 100000000000000000000000000000000001111100000000000001010000111001 source: ; load RWB from TB (JAMS CLEAR AND PRESET) source: 1 00 changed: 1 00 step 12 100000000000000000000000000000000001111100000000000001010001100001 source: 0 changed: 0 step 13 100000000000000000000000000000000001111100000000000001010000100001 source: ; (no change) source: 100000000000000000000000000000000001111100000000000001010000100001 changed: step 14 100000000000000000000000000000000001111100000000000001010000100001 source: source: source: ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; source: ; source: ; set all registers HIGH source: ; source: ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; source: source: ; set pin AF1 (AND with itself) to clear pin BB2 (AND-NOR output) and set pin BR2 TAPE BUS 3 OUTPUT source: 1 0 1 changed: 1 0 1 step 15 100000000000010000000000000000000000111101000000000001010000100001 source: ; set pin AP2 (AND with itself) to clear pin AN2 (AND-NOR output) and set pin BV2 TAPE BUS 2 OUTPUT source: 1 0 1 changed: 1 0 1 step 16 100000000000010010000000000000000000110111000000000001010000100001 source: source: source: ; load TMA SETUP from tape bus (11) source: 111 changed: 111 step 17 100000000000010010000000000000000000110111111000000001010000100001 source: 0 changed: 0 step 18 100000000000010010000000000000000000110111011000000001010000100001 source: ; load TMA from tape bus (11) source: 111 changed: 111 step 19 100000000000010010000000000000000000110111011111000001010000100001 source: 0 changed: 0 step 20 100000000000010010000000000000000000110111011011000001010000100001 source: ; load TBN from tape bus (11) source: 111 changed: 111 step 21 100000000000010010000000000000000000110111011011111001010000100001 source: 0 changed: 0 step 22 100000000000010010000000000000000000110111011011011001010000100001 source: ; load TAC from tape bus (11) source: 11010 changed: 11010 step 23 100000000000010010000000000000000000110111011011011110100000100001 source: 0 changed: 0 step 24 100000000000010010000000000000000000110111011011011010100000100001 source: ; load TB from tape bus (11) source: 111 changed: 111 step 25 100000000000010010000000000000000000110111011011011010101110100001 source: 0 changed: 0 step 26 100000000000010010000000000000000000110111011011011010100110100001 source: ; load RWB from TB (JAMS CLEAR AND PRESET) source: 1 11 changed: 1 11 step 27 100000000000010010000000000000000000110111011011011010100111111001 source: 0 changed: 0 step 28 100000000000010010000000000000000000110111011011011010100110111001 source: ; clear pin AF1 (AND with itself) to set pin BB2 (AND-NOR output) and clear pin BR2 TAPE BUS 3 OUTPUT source: 0 1 0 changed: 0 1 0 step 29 100000000000000010000000000000000001110110011011011010100110111001 source: ; clear pin AP2 (AND with itself) to set pin AN2 (AND-NOR output) and clear pin BV2 TAPE BUS 2 OUTPUT source: 0 1 0 changed: 0 1 0 step 30 100000000000000000000000000000000001111100011011011010100110111001 source: ; (no change) source: 100000000000000000000000000000000001111100011011011010100110111001 changed: step 31 100000000000000000000000000000000001111100011011011010100110111001 source: source: source: ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; source: ; source: ; test AND-NOR logic source: ; source: ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; source: source: ; (all registers are HIGH) source: ; set all pins HIGH except ENABLES source: source: ; set pin AF2 HIGH source: 1 changed: 1 step 32 100001000000000000000000000000000001111100011011011010100110111001 source: ; set pin AM1 HIGH source: 1 changed: 1 step 33 100001100000000000000000000000000001111100011011011010100110111001 source: ; set pin AE1 HIGH source: 1 changed: 1 step 34 100001100100000000000000000000000001111100011011011010100110111001 source: ; set pin AM2 HIGH source: 1 changed: 1 step 35 100001100110000000000000000000000001111100011011011010100110111001 source: ; set pin AB2 HIGH source: 1 changed: 1 step 36 100001100110100000000000000000000001111100011011011010100110111001 source: ; set pin AS1 HIGH source: 1 changed: 1 step 37 100001100110100100000000000000000001111100011011011010100110111001 source: ; set pin BE1 HIGH source: 1 changed: 1 step 38 100001100110100100010000000000000001111100011011011010100110111001 source: ; set pin BM1 HIGH source: 1 changed: 1 step 39 100001100110100100011000000000000001111100011011011010100110111001 source: ; set pin BH1 HIGH source: 1 changed: 1 step 40 100001100110100100011010000000000001111100011011011010100110111001 source: ; set pin BR1 HIGH source: 1 changed: 1 step 41 100001100110100100011011000000000001111100011011011010100110111001 source: ; set pin BC1 HIGH source: 1 changed: 1 step 42 100001100110100100011011010000000001111100011011011010100110111001 source: ; set pin BJ2 HIGH source: 1 changed: 1 step 43 100001100110100100011011011000000001111100011011011010100110111001 source: ; set pin BJ1 HIGH source: 1 changed: 1 step 44 100001100110100100011011011010000001111100011011011010100110111001 source: ; set pin BK2 HIGH source: 1 changed: 1 step 45 100001100110100100011011011011000001111100011011011010100110111001 source: ; set pin BH2 HIGH source: 1 changed: 1 step 46 100001100110100100011011011011010001111100011011011010100110111001 source: ; set pin BP2 HIGH source: 1 changed: 1 step 47 100001100110100100011011011011011001111100011011011010100110111001 source: ; set pin BN2 HIGH source: 1 changed: 1 step 48 100001100110100100011011011011011101111100011011011010100110111001 source: ; toggle each ENABLE source: source: ; set pin AL2 to clear pin BB2 and pin AN2 AND-NOR OUTPUTS and set TAPE BUS 2 OUTPUT and TAPE BUS 3 OUTPUT source: 1 0 0 11 changed: 1 0 0 11 step 49 110001100110100100011011011011011100110111011011011010100110111001 source: 0 1 1 00 changed: 0 1 1 00 step 50 100001100110100100011011011011011101111100011011011010100110111001 source: ; set pin AP1 to clear pin BB2 and pin AN2 AND-NOR OUTPUTS and set TAPE BUS 2 OUTPUT and TAPE BUS 3 OUTPUT source: 1 0 0 11 changed: 1 0 0 11 step 51 101001100110100100011011011011011100110111011011011010100110111001 source: 0 1 1 00 changed: 0 1 1 00 step 52 100001100110100100011011011011011101111100011011011010100110111001 source: ; set pin AS2 to clear pin BB2 and pin AN2 AND-NOR OUTPUTS and set TAPE BUS 2 OUTPUT and TAPE BUS 3 OUTPUT source: 1 0 0 11 changed: 1 0 0 11 step 53 100101100110100100011011011011011100110111011011011010100110111001 source: 0 1 1 00 changed: 0 1 1 00 step 54 100001100110100100011011011011011101111100011011011010100110111001 source: ; set pin AL1 to clear pin BB2 and pin AN2 AND-NOR OUTPUTS and set TAPE BUS 2 OUTPUT and TAPE BUS 3 OUTPUT source: 1 0 0 11 changed: 1 0 0 11 step 55 100011100110100100011011011011011100110111011011011010100110111001 source: 0 1 1 00 changed: 0 1 1 00 step 56 100001100110100100011011011011011101111100011011011010100110111001 source: ; set pin AL1 to clear pin BB2 and pin AN2 AND-NOR OUTPUTS and set TAPE BUS 2 OUTPUT and TAPE BUS 3 OUTPUT source: 1 0 0 11 changed: 1 0 0 11 step 57 100001110110100100011011011011011100110111011011011010100110111001 source: 0 1 1 00 changed: 0 1 1 00 step 58 100001100110100100011011011011011101111100011011011010100110111001 source: ; set pin AE2 to clear pin BB2 and pin AN2 AND-NOR OUTPUTS and set TAPE BUS 2 OUTPUT and TAPE BUS 3 OUTPUT source: 1 0 0 11 changed: 1 0 0 11 step 59 100001101110100100011011011011011100110111011011011010100110111001 source: 0 1 1 00 changed: 0 1 1 00 step 60 100001100110100100011011011011011101111100011011011010100110111001 source: ; set pin AC1 to clear pin BB2 and set TAPE BUS 3 OUTPUT source: 1 0 1 changed: 1 0 1 step 61 100001100111100100011011011011011100111101011011011010100110111001 source: 0 1 0 changed: 0 1 0 step 62 100001100110100100011011011011011101111100011011011010100110111001 source: ; set pin AF1 to clear pin BB2 and set TAPE BUS 3 OUTPUT source: 1 0 1 changed: 1 0 1 step 63 100001100110110100011011011011011100111101011011011010100110111001 source: 0 1 0 changed: 0 1 0 step 64 100001100110100100011011011011011101111100011011011010100110111001 source: ; set pin AR2 to clear pin AN2 AND-NOR OUTPUTS and set TAPE BUS 2 OUTPUT source: 1 0 1 changed: 1 0 1 step 65 100001100110101100011011011011011101110110011011011010100110111001 source: 0 1 0 changed: 0 1 0 step 66 100001100110100100011011011011011101111100011011011010100110111001 source: ; set pin AP2 to clear pin AN2 AND-NOR OUTPUTS and set TAPE BUS 2 OUTPUT source: 1 0 1 changed: 1 0 1 step 67 100001100110100110011011011011011101110110011011011010100110111001 source: 0 1 0 changed: 0 1 0 step 68 100001100110100100011011011011011101111100011011011010100110111001 source: source: ; set pin BK1 to clear pin BB1 and pin BN1 AND-NOR OUTPUTS and set TAPE BUS 2 OUTPUT and TAPE BUS 3 OUTPUT source: 1 00 11 changed: 1 00 11 step 69 100001100110100101011011011011011101001111011011011010100110111001 SLOT BAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBAABBAAAAAAAAAAAAAABBBBBBBBAB LETTER ALPSLFMDEEMCBFRSPKLEMFHRSCJLJKUHPNMBBNNVVRKRHUTDJUKANJHBTPDFSVDEVU SIDE 121212122121212121111111112212122222112222111221112112212112212212 DIRECTION IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIOOOOOOOIOOIOOIOOIOOOOIOOIIOOIIO source: 0 11 00 changed: 0 1 00 step 70 100001100110100100011011011011011101011100011011011010100110111001 fail ^ space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C toggle comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT BAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBAABBAAAAAAAAAAAAAABBBBBBBBAB LETTER ALPSLFMDEEMCBFRSPKLEMFHRSCJLJKUHPNMBBNNVVRKRHUTDJUKANJHBTPDFSVDEVU SIDE 121212122121212121111111112212122222112222111221112112212112212212 DIRECTION IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIOOOOOOOIOOIOOIOOIOOOOIOOIIOOIIO all fails O O was lo 00000000000000000000000000000000000000 00000000000000000000 0000 falling vvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvv vvvvvvvvvvvvvvvvvvvv vv rising ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ ^^^^^^^^^^^^^^^^^^^^ ^^ was hi 111111111111111111111111111111111111111111111111111111111111111 1 total fails 78, total passes 0 Main menu Sat Jul 11 14:44:21 2015 test file is: tests\m222.new delay is: 0 trigger is: 1 1 read test file 2 set test delay 3 set test trigger 4 run test 5 output loading test 8 diags 9 exit UUT power is okay Sat Jul 11 14:44:36 2015 space single step O run once (one test, all steps) F run, stop on fail G go (run tests N run, stop on fail, no print S scope (run, no print) C toggle comment printout + increase speed (less delay) - decrease speed (more delay)(slower) Q quit test step 1 100000000000000000000000000000000001111100010011011010100110111001 step 2 100000000000000000000000000000000001111100100011011010100110111001 step 3 100000000000000000000000000000000001111100000011011010100110111001 step 4 100000000000000000000000000000000001111100000100011010100110111001 step 5 100000000000000000000000000000000001111100000000011010100110111001 step 6 100000000000000000000000000000000001111100000000100010100110111001 step 7 100000000000000000000000000000000001111100000000000010100110111001 step 8 100000000000000000000000000000000001111100000000000101010110111001 step 9 100000000000000000000000000000000001111100000000000001010110111001 step 10 100000000000000000000000000000000001111100000000000001011000111001 step 11 100000000000000000000000000000000001111100000000000001010000111001 step 12 100000000000000000000000000000000001111100000000000001010001100001 step 13 100000000000000000000000000000000001111100000000000001010000100001 step 14 100000000000000000000000000000000001111100000000000001010000100001 step 15 100000000000010000000000000000000000111101000000000001010000100001 step 16 100000000000010010000000000000000000110111000000000001010000100001 step 17 100000000000010010000000000000000000110111111000000001010000100001 step 18 100000000000010010000000000000000000110111011000000001010000100001 step 19 100000000000010010000000000000000000110111011111000001010000100001 step 20 100000000000010010000000000000000000110111011011000001010000100001 step 21 100000000000010010000000000000000000110111011011111001010000100001 step 22 100000000000010010000000000000000000110111011011011001010000100001 step 23 100000000000010010000000000000000000110111011011011110100000100001 step 24 100000000000010010000000000000000000110111011011011010100000100001 step 25 100000000000010010000000000000000000110111011011011010101110100001 step 26 100000000000010010000000000000000000110111011011011010100110100001 step 27 100000000000010010000000000000000000110111011011011010100111111001 step 28 100000000000010010000000000000000000110111011011011010100110111001 step 29 100000000000000010000000000000000001110110011011011010100110111001 step 30 100000000000000000000000000000000001111100011011011010100110111001 step 31 100000000000000000000000000000000001111100011011011010100110111001 step 32 100001000000000000000000000000000001111100011011011010100110111001 step 33 100001100000000000000000000000000001111100011011011010100110111001 step 34 100001100100000000000000000000000001111100011011011010100110111001 step 35 100001100110000000000000000000000001111100011011011010100110111001 step 36 100001100110100000000000000000000001111100011011011010100110111001 step 37 100001100110100100000000000000000001111100011011011010100110111001 step 38 100001100110100100010000000000000001111100011011011010100110111001 step 39 100001100110100100011000000000000001111100011011011010100110111001 step 40 100001100110100100011010000000000001111100011011011010100110111001 step 41 100001100110100100011011000000000001111100011011011010100110111001 step 42 100001100110100100011011010000000001111100011011011010100110111001 step 43 100001100110100100011011011000000001111100011011011010100110111001 step 44 100001100110100100011011011010000001111100011011011010100110111001 step 45 100001100110100100011011011011000001111100011011011010100110111001 step 46 100001100110100100011011011011010001111100011011011010100110111001 step 47 100001100110100100011011011011011001111100011011011010100110111001 SLOT BAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBAABBAAAAAAAAAAAAAABBBBBBBBAB LETTER ALPSLFMDEEMCBFRSPKLEMFHRSCJLJKUHPNMBBNNVVRKRHUTDJUKANJHBTPDFSVDEVU SIDE 121212122121212121111111112212122222112222111221112112212112212212 DIRECTION IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIOOOOOOOIOOIOOIOOIOOOOIOOIIOOIIO changed: 1 0 1 step 48 100001100110100100011011011011011101101110011011011010100110111001 fail ^ ^ space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C toggle comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT BAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBAABBAAAAAAAAAAAAAABBBBBBBBAB LETTER ALPSLFMDEEMCBFRSPKLEMFHRSCJLJKUHPNMBBNNVVRKRHUTDJUKANJHBTPDFSVDEVU SIDE 121212122121212121111111112212122222112222111221112112212112212212 DIRECTION IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIOOOOOOOIOOIOOIOOIOOOOIOOIIOOIIO changed: 1 0 0001 step 49 110001100110100100011011011011011100100001011011011010100110111001 fail ^ ^^ space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C toggle comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT BAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBAABBAAAAAAAAAAAAAABBBBBBBBAB LETTER ALPSLFMDEEMCBFRSPKLEMFHRSCJLJKUHPNMBBNNVVRKRHUTDJUKANJHBTPDFSVDEVU SIDE 121212122121212121111111112212122222112222111221112112212112212212 DIRECTION IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIOOOOOOOIOOIOOIOOIOOOOIOOIIOOIIO all fails O OO was lo 00000000000000000000000000000000000 00000000000000000000000 0000 falling v v v vvvvvvv vvvvvvvvvvvvvvv vv rising ^ ^^ ^^ ^^ ^^ ^^ ^^ ^^ ^^ ^^^ ^ ^ ^^^^^^^^^^^^^^^^^^^^ ^^ was hi 11 11 11 11 11 11 11 11 11 111 1111111111111111111111111111 1 total fails 0, total passes 0 Main menu Sat Jul 11 14:46:02 2015 test file is: tests\m222.new delay is: 0 trigger is: 1 1 read test file 2 set test delay 3 set test trigger 4 run test 5 output loading test 8 diags 9 exit exiting tester- PDP8 card tester via printer port version 0.85 June 4, 2015 mapping[] is verified Main menu Sat Jul 11 15:46:54 2015 test file is: delay is: 0 trigger is: 1 1 read test file 2 set test delay 3 set test trigger 4 run test 5 output loading test 8 diags 9 exit Enter test file name? trying to open test file: tests\m222.new reading test file: tests\m222.new comment: M222 PCB REV B SCHEMATIC REV A LINC TAPE REGISTERS comment: comment: TERMINOLOGY- SIGNALS REFER TO VOL4 M222 SCHEMATIC. comment: comment: BUT... comment: comment: DEC USES AND-NOR GATES TO ROUTE THE ADDER A AND B INPUTS, SO... comment: DEC RENAMED THE ADDER TO NEGATIVE LOGIC TERMS (I.E. A-N + B-N + C-N -> SUM-N, C1-N). comment: (NOT THE 7482 DATASHEET NAMES OF A + B + C -> SUM, C1). comment: comment: SO, WITH ALL 'AND ENABLES' LOW, THE AND-NOR OUTPUTS = HIGH. comment: WITH C-L HIGH, THE ADDER OUTPUT IS SUM-N=1, C1-N=1; comment: THE INVERTED ADDER OUTPUT IS LOW (TAPE BUS). comment: AND THERE IS NO CARRY (C1-N IS HI). comment: comment: THE TWO ADDERS, TWO REGISTER BITS, ETC ARE LABELED BIT 2 (EVEN, MSB) AND BIT 3 (ODD, LSB). comment: THE ADDERS ARE REFERRED TO AS 'ADDER2' (MSB) AND 'ADDER3' (LSB). comment: comment: POWER PINS: comment: AA2 +5V comment: AT1 GROUND comment: AC2 GROUND comment: BA2 +5V comment: BT1 GROUND comment: BC2 GROUND comment: comment: (ALL PINS ARE USED). comment: comment: pins: PINS pins: 1 I BA1 CARRY IN-N, (TO E9-5 7482 C0) C-N TO ADDER2 pins: 2 I AL2 AND-NOR ENABLE: TAC TAC3 TO PIN BB2 (TO ADDER3) TAC2 TO PIN AN2 (TO ADDER2) pins: 3 I AP1 AND-NOR ENABLE: TMA SETUP (TMAS)3 TO PIN BB2 (TO ADDER3), (TMAS)3 TO PIN AN2 (TO ADDER2) pins: 4 I AS2 AND-NOR ENABLE: TMA TMA3 TO PIN BB2 (TO ADDER3), TMA2 TO PIN AN2 (TO ADDER2) pins: 5 I AL1 AND-NOR ENABLE: PIN AF2 TO PIN BB2 (TO ADDER3), PIN AM1 TO PIN AN2 (TO ADDER2) pins: 6 I AF2 AND-NOR INPUT (AL1 ENABLES) TO PIN BB2 (TO ADDER3). pins: 7 I AM1 AND-NOR INPUT (AL1 ENABLES) TO PIN AN2 (TO ADDER2) pins: 8 I AD2 AND-NOR ENABLE: RWB RWB3 TO PIN BB2 (TO ADDER3), RWB2 TO PIN AN2 (TO ADDER2) pins: 9 I AE2 AND-NOR ENABLE: PIN AE1 TO PIN BB2 (TO ADDER3), PIN AM2 TO PIN AN2 (TO ADDER2) pins: 10 I AE1 AND-NOR INPUT (AE2 ENABLES) TO PIN BB2 (TO ADDER3). pins: 11 I AM2 AND-NOR INPUT (AE2 ENABLES) TO PIN AN2 (TO ADDER2) pins: 12 I AC1 AND-NOR INPUT, AND WITH PIN AB2 TO PIN BB2 (TO ADDER3) pins: 13 I AB2 AND-NOR INPUT, AND WITH PIN AC1 TO PIN BB2 (TO ADDER3) pins: 14 I AF1 AND-NOR INPUT (AND WITH ITSELF) TO PIN BB2 (TO ADDER3) pins: 15 I AR2 AND-NOR INPUT, AND WITH PIN AS1 TO PIN AN2 (TO ADDER2) pins: 16 I AS1 AND-NOR INPUT, AND WITH PIN AR2 TO PIN AN2 (TO ADDER2) pins: 17 I AP2 AND-NOR INPUT (AND WITH ITSELF) TO PIN AN2 (TO ADDER2) pins: 18 I BK1 AND-NOR ENABLE: TB3 TO PIN BB1 (TO ADDER3), TB2 TO PIN BN1 (TO ADDER2) pins: 19 I BL1 AND-NOR ENABLE: PIN BE1 TO PIN BB1 (TO ADDER3), PIN BM1 TO PIN BN1 (TO ADDER2) pins: 20 I BE1 AND-NOR INPUT (BL1 ENABLES) TO PIN BB1 (TO ADDER3). pins: 21 I BM1 AND-NOR INPUT (BL1 ENABLES) TO PIN BN1 (TO ADDER2) pins: 22 I BF1 AND-NOR ENABLE: PIN BH1 TO PIN BB1 (TO ADDER3), PIN BR1 TO PIN BN1 (TO ADDER2) pins: 23 I BH1 AND-NOR INPUT (BF1 ENABLES): TO PIN BB1 (TO ADDER3), pins: 24 I BR1 AND-NOR INPUT (BF1 ENABLES): TO PIN BN1 (TO ADDER2) pins: 25 I BS1 AND-NOR ENABLE: PIN BC1 TO PIN BB1 (TO ADDER3), PIN BJ2 TO PIN BN1 (TO ADDER2) pins: 26 I BC1 AND-NOR INPUT (BS1 ENABLES): TO PIN BB1 (TO ADDER3), pins: 27 I BJ2 AND-NOR INPUT (BS1 ENABLES): TO PIN BN1 (TO ADDER2) pins: 28 I BL2 AND-NOR ENABLE: PIN BJ1 TO PIN BB1 (TO ADDER3), PIN BK2 TO PIN BN1 (TO ADDER2) pins: 29 I BJ1 AND-NOR INPUT (BL2 ENABLES): TO PIN BB1 (TO ADDER3), pins: 30 I BK2 AND-NOR INPUT (BL2 ENABLES): TO PIN BN1 (TO ADDER2) pins: 31 I BU1 AND-NOR ENABLE: PIN BH2 TO PIN BB1 (TO ADDER3), PIN BP2 TO PIN BN1 (TO ADDER2) pins: 32 I BH2 AND-NOR INPUT (BU1 ENABLES): TO PIN BB1 (TO ADDER3), pins: 33 I BP2 AND-NOR INPUT (BU1 ENABLES): TO PIN BN1 (TO ADDER2) pins: 34 I BN2 AND-NOR INPUT (AND WITH BM2): TO PIN BN1 (TO ADDER2) pins: 35 I BM2 AND-NOR INPUT (AND WITH BM2): TO PIN BN1 (TO ADDER2) pins: 36 O BB2 AND-NOR OUTPUT, (DRIVES E9-2 7482 A1) TO ADDER3 INPUT pins: 37 O BB1 AND-NOR OUTPUT, (DRIVES E9-3 7482 B1) TO ADDER3 INPUT pins: 38 O BN1 AND-NOR OUTPUT, (DRIVES E9-14 7482 A2) TO ADDER2 INPUT pins: 39 O AN2 AND-NOR OUTPUT, (DRIVES E9-13 7482 B2) TO ADDER2 INPUT pins: 40 O AV2 CARRY OUT-N (E9-10 7482 C2) pins: 41 O BV2 TAPE BUS 2 OUTPUT (INVERTED ADDER2 SUM-N (E9-12 7482 SUM2) pins: 42 O BR2 TAPE BUS 3 OUTPUT (INVERTED ADDER3 SUM-N (E9-1 7482 SUM1) pins: 43 I AK1 LOAD TMA SETUP (FROM TAPE BUS) (RISING EDGE CLOCK) pins: 44 O AR1 TMA SETUP 2 pins: 45 O AH1 TMA SETUP 3 pins: 46 I AU2 LOAD TMA (FROM TAPE BUS) (RISING EDGE CLOCK) pins: 47 O AT2 TMA 2 pins: 48 O AD1 TMA 3 pins: 49 I AJ1 LOAD TBN (FROM TAPE BUS) (RISING EDGE CLOCK) pins: 50 O AU1 TBN 2 pins: 51 O AK2 TBN 3 pins: 52 I AA1 LOAD TAC (FROM TAPE BUS) (RISING EDGE CLOCK) pins: 53 O AN1 TAC 2 pins: 54 O AJ2 TAC 2-N pins: 55 O AH2 TAC 3 pins: 56 O AB1 TAC 3-N pins: 57 I BT2 LOAD TB (FROM TAPE BUS) (RISING EDGE CLOCK) pins: 58 O BP1 TB 2 pins: 59 O BD1 TB 3 pins: 60 I BF2 LOAD RWB (FROM TB) (JAMS CLEAR,SET) pins: 61 I BS2 PHASE (SELECTS POLARITY OF RWB OUT, 0 -> INVERTED) pins: 62 O BV1 RWB OUT (=RWB 2 IF PHASE=1; =RWB 2-N IF PHASE=0) pins: 63 O BD2 RWB 3 pins: 64 I BE2 SHIFT RWB (SHIFTS PIN AV1 INTO RWB 3, SHIFTS RWB3 TO RWB2) (RISING CLOCK) pins: 65 I AV1 RWB IN (SHIFTED INTO RWB 2) pins: 66 O BU2 +3.5V pins: direction: IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIOOOOOOOIOOIOOIOOIOOOOIOOIIOOIIO comment: ; all registers are unknown comment: ; turn on C0, PHASE comment: ; with no ENABLES, BUS2,BUS3 is 11, C2 is 1 test 1: 1000000000000000000000000000000000011111000XX0XX0XX0XXXX0XX01XX001 comment: comment: ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; comment: ; comment: ; set all registers LOW comment: ; comment: ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; comment: comment: ; load TMA SETUP from tape bus (00) test 2: 100 test 3: 0 comment: ; load TMA from tape bus (00) test 4: 100 test 5: 0 comment: ; load TBN from tape bus (00) test 6: 100 test 7: 0 comment: ; load TAC from tape bus (00) test 8: 10101 test 9: 0 comment: ; load TB from tape bus (00) test 10: 100 test 11: 0 comment: ; load RWB from TB (JAMS CLEAR AND PRESET) test 12: 1 00 test 13: 0 comment: ; (no change) test 14: 100000000000000000000000000000000001111100000000000001010000100001 comment: comment: comment: ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; comment: ; comment: ; set all registers HIGH comment: ; comment: ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; comment: comment: ; set pin AF1 (AND with itself) to clear pin BB2 (AND-NOR output) and set pin BR2 TAPE BUS 3 OUTPUT test 15: 1 0 1 comment: ; set pin AP2 (AND with itself) to clear pin AN2 (AND-NOR output) and set pin BV2 TAPE BUS 2 OUTPUT test 16: 1 0 1 comment: comment: comment: ; load TMA SETUP from tape bus (11) test 17: 111 test 18: 0 comment: ; load TMA from tape bus (11) test 19: 111 test 20: 0 comment: ; load TBN from tape bus (11) test 21: 111 test 22: 0 comment: ; load TAC from tape bus (11) test 23: 11010 test 24: 0 comment: ; load TB from tape bus (11) test 25: 111 test 26: 0 comment: ; load RWB from TB (JAMS CLEAR AND PRESET) test 27: 1 11 test 28: 0 comment: ; clear pin AF1 (AND with itself) to set pin BB2 (AND-NOR output) and clear pin BR2 TAPE BUS 3 OUTPUT test 29: 0 1 0 comment: ; clear pin AP2 (AND with itself) to set pin AN2 (AND-NOR output) and clear pin BV2 TAPE BUS 2 OUTPUT test 30: 0 1 0 comment: ; (no change) test 31: 100000000000000000000000000000000001111100011011011010100110111001 comment: comment: comment: ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; comment: ; comment: ; test AND-NOR logic comment: ; comment: ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; comment: comment: ; (all registers are HIGH) comment: ; set all pins HIGH except ENABLES comment: comment: ; set pin AF2 HIGH test 32: 1 comment: ; set pin AM1 HIGH test 33: 1 comment: ; set pin AE1 HIGH test 34: 1 comment: ; set pin AM2 HIGH test 35: 1 comment: ; set pin AB2 HIGH test 36: 1 comment: ; set pin AS1 HIGH test 37: 1 comment: ; set pin BE1 HIGH test 38: 1 comment: ; set pin BM1 HIGH test 39: 1 comment: ; set pin BH1 HIGH test 40: 1 comment: ; set pin BR1 HIGH test 41: 1 comment: ; set pin BC1 HIGH test 42: 1 comment: ; set pin BJ2 HIGH test 43: 1 comment: ; set pin BJ1 HIGH test 44: 1 comment: ; set pin BK2 HIGH test 45: 1 comment: ; set pin BH2 HIGH test 46: 1 comment: ; set pin BP2 HIGH test 47: 1 comment: ; set pin BN2 HIGH test 48: 1 comment: ; toggle each ENABLE comment: comment: ; set pin AL2 to clear pin BB2 and pin AN2 AND-NOR OUTPUTS and set TAPE BUS 2 OUTPUT and TAPE BUS 3 OUTPUT test 49: 1 0 0 11 test 50: 0 1 1 00 comment: ; set pin AP1 to clear pin BB2 and pin AN2 AND-NOR OUTPUTS and set TAPE BUS 2 OUTPUT and TAPE BUS 3 OUTPUT test 51: 1 0 0 11 test 52: 0 1 1 00 comment: ; set pin AS2 to clear pin BB2 and pin AN2 AND-NOR OUTPUTS and set TAPE BUS 2 OUTPUT and TAPE BUS 3 OUTPUT test 53: 1 0 0 11 test 54: 0 1 1 00 comment: ; set pin AL1 to clear pin BB2 and pin AN2 AND-NOR OUTPUTS and set TAPE BUS 2 OUTPUT and TAPE BUS 3 OUTPUT test 55: 1 0 0 11 test 56: 0 1 1 00 comment: ; set pin AL1 to clear pin BB2 and pin AN2 AND-NOR OUTPUTS and set TAPE BUS 2 OUTPUT and TAPE BUS 3 OUTPUT test 57: 1 0 0 11 test 58: 0 1 1 00 comment: ; set pin AE2 to clear pin BB2 and pin AN2 AND-NOR OUTPUTS and set TAPE BUS 2 OUTPUT and TAPE BUS 3 OUTPUT test 59: 1 0 0 11 test 60: 0 1 1 00 comment: ; set pin AC1 to clear pin BB2 and set TAPE BUS 3 OUTPUT test 61: 1 0 1 test 62: 0 1 0 comment: ; set pin AF1 to clear pin BB2 and set TAPE BUS 3 OUTPUT test 63: 1 0 1 test 64: 0 1 0 comment: ; set pin AR2 to clear pin AN2 AND-NOR OUTPUTS and set TAPE BUS 2 OUTPUT test 65: 1 0 1 test 66: 0 1 0 comment: ; set pin AP2 to clear pin AN2 AND-NOR OUTPUTS and set TAPE BUS 2 OUTPUT test 67: 1 0 1 test 68: 0 1 0 comment: comment: ; set pin BK1 to clear pin BB1 and pin BN1 AND-NOR OUTPUTS and set TAPE BUS 2 OUTPUT and TAPE BUS 3 OUTPUT test 69: 1 00 11 test 70: 0 11 00 comment: ; set pin BL1 to clear pin BB1 and pin BN1 AND-NOR OUTPUTS and set TAPE BUS 2 OUTPUT and TAPE BUS 3 OUTPUT test 71: 1 00 11 test 72: 0 11 00 comment: ; set pin BF1 to clear pin BB1 and pin BN1 AND-NOR OUTPUTS and set TAPE BUS 2 OUTPUT and TAPE BUS 3 OUTPUT test 73: 1 00 11 test 74: 0 11 00 comment: ; set pin BS1 to clear pin BB1 and pin BN1 AND-NOR OUTPUTS and set TAPE BUS 2 OUTPUT and TAPE BUS 3 OUTPUT test 75: 1 00 11 test 76: 0 11 00 comment: ; set pin BL2 to clear pin BB1 and pin BN1 AND-NOR OUTPUTS and set TAPE BUS 2 OUTPUT and TAPE BUS 3 OUTPUT test 77: 1 00 11 test 78: 0 11 00 comment: ; set pin BU1 to clear pin BB1 and pin BN1 AND-NOR OUTPUTS and set TAPE BUS 2 OUTPUT and TAPE BUS 3 OUTPUT test 79: 1 00 11 test 80: 0 11 00 comment: ; set pin BM2 to clear pin BB1 and TAPE BUS 3 OUTPUT test 81: 1 0 1 test 82: 0 1 0 comment: comment: comment: ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; comment: ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; comment: ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; comment: ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; comment: ; needs work comment: ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; comment: ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; comment: ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; comment: ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; end: END summary column 1: offset 2, mask 0x2000 column 2: offset 1, mask 0x0002 column 3: offset 1, mask 0x0800 column 4: offset 1, mask 0x0040 column 5: offset 1, mask 0x4000 column 6: offset 0, mask 0x0004 column 7: offset 1, mask 0x2000 column 8: offset 0, mask 0x0010 column 9: offset 0, mask 0x0008 column 10: offset 0, mask 0x0800 column 11: offset 1, mask 0x0004 column 12: offset 0, mask 0x2000 column 13: offset 0, mask 0x0040 column 14: offset 0, mask 0x0400 column 15: offset 1, mask 0x0020 column 16: offset 1, mask 0x0200 column 17: offset 1, mask 0x0010 column 18: offset 3, mask 0x2000 column 19: offset 3, mask 0x1000 column 20: offset 2, mask 0x0200 column 21: offset 3, mask 0x0800 column 22: offset 2, mask 0x0100 column 23: offset 3, mask 0x8000 column 24: offset 3, mask 0x0100 column 25: offset 4, mask 0x8000 column 26: offset 2, mask 0x0800 column 27: offset 3, mask 0x0002 column 28: offset 3, mask 0x0008 column 29: offset 3, mask 0x4000 column 30: offset 3, mask 0x0004 column 31: offset 4, mask 0x2000 column 32: offset 3, mask 0x0001 column 33: offset 3, mask 0x0040 column 34: offset 3, mask 0x0020 column 35: offset 3, mask 0x0010 column 36: offset 2, mask 0x0008 column 37: offset 2, mask 0x1000 column 38: offset 3, mask 0x0400 column 39: offset 1, mask 0x0008 column 40: offset 2, mask 0x0002 column 41: offset 4, mask 0x0008 column 42: offset 3, mask 0x0080 column 43: offset 1, mask 0x8000 column 44: offset 1, mask 0x0400 column 45: offset 0, mask 0x0200 column 46: offset 2, mask 0x0001 column 47: offset 1, mask 0x0080 column 48: offset 0, mask 0x1000 column 49: offset 0, mask 0x0100 column 50: offset 2, mask 0x8000 column 51: offset 1, mask 0x0001 column 52: offset 0, mask 0x8000 column 53: offset 1, mask 0x1000 column 54: offset 0, mask 0x0001 column 55: offset 0, mask 0x0002 column 56: offset 0, mask 0x4000 column 57: offset 4, mask 0x0002 column 58: offset 3, mask 0x0200 column 59: offset 2, mask 0x0400 column 60: offset 2, mask 0x0080 column 61: offset 4, mask 0x0001 column 62: offset 4, mask 0x1000 column 63: offset 2, mask 0x0020 column 64: offset 2, mask 0x0040 column 65: offset 2, mask 0x4000 column 66: offset 4, mask 0x0004 direction bits (1=input) 0x52A3 0x1589 0x943A 0x0680 0x50FC pullup bits (1=pullup) 0x0000 0x0000 0x0000 0x0000 0x0000 test step out_data dont care 1: 0x0000 0x0008 0x300A 0x0400 0x0005 0x5203 0x1481 0x8420 0x0200 0x1000 2: 0x0000 0x8008 0x300A 0x0400 0x0005 0x5003 0x1081 0x8420 0x0200 0x1000 3: 0x0000 0x0008 0x300A 0x0400 0x0005 0x5003 0x1081 0x8420 0x0200 0x1000 4: 0x0000 0x0008 0x300B 0x0400 0x0005 0x4003 0x1001 0x8420 0x0200 0x1000 5: 0x0000 0x0008 0x300A 0x0400 0x0005 0x4003 0x1001 0x8420 0x0200 0x1000 6: 0x0100 0x0008 0x300A 0x0400 0x0005 0x4003 0x1000 0x0420 0x0200 0x1000 7: 0x0000 0x0008 0x300A 0x0400 0x0005 0x4003 0x1000 0x0420 0x0200 0x1000 8: 0xC001 0x0008 0x300A 0x0400 0x0005 0x0000 0x0000 0x0420 0x0200 0x1000 9: 0x4001 0x0008 0x300A 0x0400 0x0005 0x0000 0x0000 0x0420 0x0200 0x1000 10: 0x4001 0x0008 0x300A 0x0400 0x0007 0x0000 0x0000 0x0020 0x0000 0x1000 11: 0x4001 0x0008 0x300A 0x0400 0x0005 0x0000 0x0000 0x0020 0x0000 0x1000 12: 0x4001 0x0008 0x308A 0x0400 0x0005 13: 0x4001 0x0008 0x300A 0x0400 0x0005 14: 0x4001 0x0008 0x300A 0x0400 0x0005 15: 0x4401 0x0008 0x3002 0x0480 0x0005 16: 0x4401 0x0010 0x3002 0x0480 0x000D 17: 0x4601 0x8410 0x3002 0x0480 0x000D 18: 0x4601 0x0410 0x3002 0x0480 0x000D 19: 0x5601 0x0490 0x3003 0x0480 0x000D 20: 0x5601 0x0490 0x3002 0x0480 0x000D 21: 0x5701 0x0491 0xB002 0x0480 0x000D 22: 0x5601 0x0491 0xB002 0x0480 0x000D 23: 0x9602 0x1491 0xB002 0x0480 0x000D 24: 0x1602 0x1491 0xB002 0x0480 0x000D 25: 0x1602 0x1491 0xB402 0x0680 0x000F 26: 0x1602 0x1491 0xB402 0x0680 0x000D 27: 0x1602 0x1491 0xB4A2 0x0680 0x100D 28: 0x1602 0x1491 0xB422 0x0680 0x100D 29: 0x1202 0x1491 0xB42A 0x0600 0x100D 30: 0x1202 0x1489 0xB42A 0x0600 0x1005 31: 0x1202 0x1489 0xB42A 0x0600 0x1005 32: 0x1206 0x1489 0xB42A 0x0600 0x1005 33: 0x1206 0x3489 0xB42A 0x0600 0x1005 34: 0x1A06 0x3489 0xB42A 0x0600 0x1005 35: 0x1A06 0x348D 0xB42A 0x0600 0x1005 36: 0x1A46 0x348D 0xB42A 0x0600 0x1005 37: 0x1A46 0x368D 0xB42A 0x0600 0x1005 38: 0x1A46 0x368D 0xB62A 0x0600 0x1005 39: 0x1A46 0x368D 0xB62A 0x0E00 0x1005 40: 0x1A46 0x368D 0xB62A 0x8E00 0x1005 41: 0x1A46 0x368D 0xB62A 0x8F00 0x1005 42: 0x1A46 0x368D 0xBE2A 0x8F00 0x1005 43: 0x1A46 0x368D 0xBE2A 0x8F02 0x1005 44: 0x1A46 0x368D 0xBE2A 0xCF02 0x1005 45: 0x1A46 0x368D 0xBE2A 0xCF06 0x1005 46: 0x1A46 0x368D 0xBE2A 0xCF07 0x1005 47: 0x1A46 0x368D 0xBE2A 0xCF47 0x1005 48: 0x1A46 0x368D 0xBE2A 0xCF67 0x1005 49: 0x1A46 0x3687 0xBE22 0xCFE7 0x100D 50: 0x1A46 0x368D 0xBE2A 0xCF67 0x1005 51: 0x1A46 0x3E85 0xBE22 0xCFE7 0x100D 52: 0x1A46 0x368D 0xBE2A 0xCF67 0x1005 53: 0x1A46 0x36C5 0xBE22 0xCFE7 0x100D 54: 0x1A46 0x368D 0xBE2A 0xCF67 0x1005 55: 0x1A46 0x7685 0xBE22 0xCFE7 0x100D 56: 0x1A46 0x368D 0xBE2A 0xCF67 0x1005 57: 0x1A56 0x3685 0xBE22 0xCFE7 0x100D 58: 0x1A46 0x368D 0xBE2A 0xCF67 0x1005 59: 0x1A4E 0x3685 0xBE22 0xCFE7 0x100D 60: 0x1A46 0x368D 0xBE2A 0xCF67 0x1005 61: 0x3A46 0x368D 0xBE22 0xCFE7 0x1005 62: 0x1A46 0x368D 0xBE2A 0xCF67 0x1005 63: 0x1E46 0x368D 0xBE22 0xCFE7 0x1005 64: 0x1A46 0x368D 0xBE2A 0xCF67 0x1005 65: 0x1A46 0x36A5 0xBE2A 0xCF67 0x100D 66: 0x1A46 0x368D 0xBE2A 0xCF67 0x1005 67: 0x1A46 0x3695 0xBE2A 0xCF67 0x100D 68: 0x1A46 0x368D 0xBE2A 0xCF67 0x1005 69: 0x1A46 0x368D 0xAE2A 0xEBE7 0x100D 70: 0x1A46 0x368D 0xBE2A 0xCF67 0x1005 71: 0x1A46 0x368D 0xAE2A 0xDBE7 0x100D 72: 0x1A46 0x368D 0xBE2A 0xCF67 0x1005 73: 0x1A46 0x368D 0xAF2A 0xCBE7 0x100D 74: 0x1A46 0x368D 0xBE2A 0xCF67 0x1005 75: 0x1A46 0x368D 0xAE2A 0xCBE7 0x900D 76: 0x1A46 0x368D 0xBE2A 0xCF67 0x1005 77: 0x1A46 0x368D 0xAE2A 0xCBEF 0x100D 78: 0x1A46 0x368D 0xBE2A 0xCF67 0x1005 79: 0x1A46 0x368D 0xAE2A 0xCBE7 0x300D 80: 0x1A46 0x368D 0xBE2A 0xCF67 0x1005 81: 0x1A46 0x368D 0xBE2A 0xCB77 0x100D 82: 0x1A46 0x368D 0xBE2A 0xCF67 0x1005 PINs used (in edge connector order) (G=ground,P=power) SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBB LETTER ABCDEFHJKLMNPRSTUVABCDEFHJKLMNPRSTUVABCDEFHJKLMNPRSTUVABCDEFHJKLMNPRSTUV SIDE 111111111111111111222222222222222222111111111111111111222222222222222222 USAGE IOIOIIOIIIIOIOIGOIPIGIIIOOOIIOIIIOIOIOIOIIIIIIIOOIIGIOPOGOIIIIIIIIIOIIOO UUT has 44 inputs UUT has 22 outputs contains 66 pins/columns 0 pins are not used contains 82 'test steps' M222 PCB REV B SCHEMATIC REV A LINC TAPE REGISTERS TERMINOLOGY- SIGNALS REFER TO VOL4 M222 SCHEMATIC. BUT... DEC USES AND-NOR GATES TO ROUTE THE ADDER A AND B INPUTS, SO... DEC RENAMED THE ADDER TO NEGATIVE LOGIC TERMS (I.E. A-N + B-N + C-N -> SUM-N, C1-N). (NOT THE 7482 DATASHEET NAMES OF A + B + C -> SUM, C1). SO, WITH ALL 'AND ENABLES' LOW, THE AND-NOR OUTPUTS = HIGH. WITH C-L HIGH, THE ADDER OUTPUT IS SUM-N=1, C1-N=1; THE INVERTED ADDER OUTPUT IS LOW (TAPE BUS). AND THERE IS NO CARRY (C1-N IS HI). THE TWO ADDERS, TWO REGISTER BITS, ETC ARE LABELED BIT 2 (EVEN, MSB) AND BIT 3 (ODD, LSB). THE ADDERS ARE REFERRED TO AS 'ADDER2' (MSB) AND 'ADDER3' (LSB). POWER PINS: AA2 +5V AT1 GROUND AC2 GROUND BA2 +5V BT1 GROUND BC2 GROUND (ALL PINS ARE USED). PINS Main menu Sat Jul 11 15:47:01 2015 test file is: tests\m222.new delay is: 0 trigger is: 1 1 read test file 2 set test delay 3 set test trigger 4 run test 5 output loading test 8 diags 9 exit UUT power is okay Sat Jul 11 15:47:09 2015 space single step O run once (one test, all steps) F run, stop on fail G go (run tests N run, stop on fail, no print S scope (run, no print) C toggle comment printout + increase speed (less delay) - decrease speed (more delay)(slower) Q quit test step 1 100000000000000000000000000000000001111100010010010010010100110001 step 2 100000000000000000000000000000000001111100100010010010010100110001 step 3 100000000000000000000000000000000001111100000010010010010100110001 step 4 100000000000000000000000000000000001111100000100010010010100110001 step 5 100000000000000000000000000000000001111100000000010010010100110001 step 6 100000000000000000000000000000000001111100000000100010010100110001 step 7 100000000000000000000000000000000001111100000000000010010100110001 step 8 100000000000000000000000000000000001111100000000000101010100110001 step 9 100000000000000000000000000000000001111100000000000001010100110001 step 10 100000000000000000000000000000000001111100000000000001011000110001 step 11 100000000000000000000000000000000001111100000000000001010000110001 step 12 100000000000000000000000000000000001111100000000000001010001100001 step 13 100000000000000000000000000000000001111100000000000001010000100001 step 14 100000000000000000000000000000000001111100000000000001010000100001 step 15 100000000000010000000000000000000000111101000000000001010000100001 step 16 100000000000010010000000000000000000110111000000000001010000100001 step 17 100000000000010010000000000000000000110111111000000001010000100001 step 18 100000000000010010000000000000000000110111011000000001010000100001 step 19 100000000000010010000000000000000000110111011111000001010000100001 step 20 100000000000010010000000000000000000110111011011000001010000100001 step 21 100000000000010010000000000000000000110111011011111001010000100001 step 22 100000000000010010000000000000000000110111011011011001010000100001 step 23 100000000000010010000000000000000000110111011011011110100000100001 step 24 100000000000010010000000000000000000110111011011011010100000100001 step 25 100000000000010010000000000000000000110111011011011010101110100001 step 26 100000000000010010000000000000000000110111011011011010100110100001 step 27 100000000000010010000000000000000000110111011011011010100111111001 step 28 100000000000010010000000000000000000110111011011011010100110111001 step 29 100000000000000010000000000000000001110110011011011010100110111001 step 30 100000000000000000000000000000000001111100011011011010100110111001 step 31 100000000000000000000000000000000001111100011011011010100110111001 step 32 100001000000000000000000000000000001111100011011011010100110111001 step 33 100001100000000000000000000000000001111100011011011010100110111001 step 34 100001100100000000000000000000000001111100011011011010100110111001 step 35 100001100110000000000000000000000001111100011011011010100110111001 step 36 100001100110100000000000000000000001111100011011011010100110111001 step 37 100001100110100100000000000000000001111100011011011010100110111001 step 38 100001100110100100010000000000000001111100011011011010100110111001 step 39 100001100110100100011000000000000001111100011011011010100110111001 step 40 100001100110100100011010000000000001111100011011011010100110111001 step 41 100001100110100100011011000000000001111100011011011010100110111001 step 42 100001100110100100011011010000000001111100011011011010100110111001 step 43 100001100110100100011011011000000001111100011011011010100110111001 step 44 100001100110100100011011011010000001111100011011011010100110111001 step 45 100001100110100100011011011011000001111100011011011010100110111001 step 46 100001100110100100011011011011010001111100011011011010100110111001 step 47 100001100110100100011011011011011001111100011011011010100110111001 step 48 100001100110100100011011011011011101111100011011011010100110111001 step 49 110001100110100100011011011011011100110111011011011010100110111001 step 50 100001100110100100011011011011011101111100011011011010100110111001 step 51 101001100110100100011011011011011100110111011011011010100110111001 step 52 100001100110100100011011011011011101111100011011011010100110111001 step 53 100101100110100100011011011011011100110111011011011010100110111001 step 54 100001100110100100011011011011011101111100011011011010100110111001 step 55 100011100110100100011011011011011100110111011011011010100110111001 step 56 100001100110100100011011011011011101111100011011011010100110111001 step 57 100001110110100100011011011011011100110111011011011010100110111001 step 58 100001100110100100011011011011011101111100011011011010100110111001 step 59 100001101110100100011011011011011100110111011011011010100110111001 step 60 100001100110100100011011011011011101111100011011011010100110111001 step 61 100001100111100100011011011011011100111101011011011010100110111001 step 62 100001100110100100011011011011011101111100011011011010100110111001 step 63 100001100110110100011011011011011100111101011011011010100110111001 step 64 100001100110100100011011011011011101111100011011011010100110111001 step 65 100001100110101100011011011011011101110110011011011010100110111001 step 66 100001100110100100011011011011011101111100011011011010100110111001 step 67 100001100110100110011011011011011101110110011011011010100110111001 step 68 100001100110100100011011011011011101111100011011011010100110111001 step 69 100001100110100101011011011011011101001111011011011010100110111001 step 70 100001100110100100011011011011011101111100011011011010100110111001 step 71 100001100110100100111011011011011101001111011011011010100110111001 step 72 100001100110100100011011011011011101111100011011011010100110111001 step 73 100001100110100100011111011011011101001111011011011010100110111001 step 74 100001100110100100011011011011011101111100011011011010100110111001 step 75 100001100110100100011011111011011101001111011011011010100110111001 step 76 100001100110100100011011011011011101111100011011011010100110111001 step 77 100001100110100100011011011111011101001111011011011010100110111001 step 78 100001100110100100011011011011011101111100011011011010100110111001 step 79 100001100110100100011011011011111101001111011011011010100110111001 step 80 100001100110100100011011011011011101111100011011011010100110111001 step 81 100001100110100100011011011011011111101110011011011010100110111001 step 82 100001100110100100011011011011011101111100011011011010100110111001 test 1: pass SLOT BAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBAABBAAAAAAAAAAAAAABBBBBBBBAB LETTER ALPSLFMDEEMCBFRSPKLEMFHRSCJLJKUHPNMBBNNVVRKRHUTDJUKANJHBTPDFSVDEVU SIDE 121212122121212121111111112212122222112222111221112112212112212212 DIRECTION IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIOOOOOOOIOOIOOIOOIOOOOIOOIIOOIIO this fail all fails was hi 111111111111111111111111111111111111111111111111111111111111111 1 rising ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ ^^^^^^^^^^^^^^^ ^^^^ ^^ falling vvvv vv v vv vvv v v v v vvvvv vvvv vv vv vvv vvv v v was lo 00000000000000000000000000000000000000 00000000000000000000 0000 total fails 0, total passes 1 step 1 100000000000000000000000000000000001111100011011011010100110111001 step 2 100000000000000000000000000000000001111100100011011010100110111001 step 3 100000000000000000000000000000000001111100000011011010100110111001 step 4 100000000000000000000000000000000001111100000100011010100110111001 step 5 100000000000000000000000000000000001111100000000011010100110111001 step 6 100000000000000000000000000000000001111100000000100010100110111001 step 7 100000000000000000000000000000000001111100000000000010100110111001 step 8 100000000000000000000000000000000001111100000000000101010110111001 step 9 100000000000000000000000000000000001111100000000000001010110111001 step 10 100000000000000000000000000000000001111100000000000001011000111001 step 11 100000000000000000000000000000000001111100000000000001010000111001 step 12 100000000000000000000000000000000001111100000000000001010001100001 step 13 100000000000000000000000000000000001111100000000000001010000100001 step 14 100000000000000000000000000000000001111100000000000001010000100001 step 15 100000000000010000000000000000000000111101000000000001010000100001 step 16 100000000000010010000000000000000000110111000000000001010000100001 step 17 100000000000010010000000000000000000110111111000000001010000100001 step 18 100000000000010010000000000000000000110111011000000001010000100001 step 19 100000000000010010000000000000000000110111011111000001010000100001 step 20 100000000000010010000000000000000000110111011011000001010000100001 step 21 100000000000010010000000000000000000110111011011111001010000100001 step 22 100000000000010010000000000000000000110111011011011001010000100001 step 23 100000000000010010000000000000000000110111011011011110100000100001 step 24 100000000000010010000000000000000000110111011011011010100000100001 step 25 100000000000010010000000000000000000110111011011011010101110100001 step 26 100000000000010010000000000000000000110111011011011010100110100001 step 27 100000000000010010000000000000000000110111011011011010100111111001 step 28 100000000000010010000000000000000000110111011011011010100110111001 step 29 100000000000000010000000000000000001110110011011011010100110111001 step 30 100000000000000000000000000000000001111100011011011010100110111001 step 31 100000000000000000000000000000000001111100011011011010100110111001 step 32 100001000000000000000000000000000001111100011011011010100110111001 step 33 100001100000000000000000000000000001111100011011011010100110111001 step 34 100001100100000000000000000000000001111100011011011010100110111001 step 35 100001100110000000000000000000000001111100011011011010100110111001 step 36 100001100110100000000000000000000001111100011011011010100110111001 step 37 100001100110100100000000000000000001111100011011011010100110111001 step 38 100001100110100100010000000000000001111100011011011010100110111001 step 39 100001100110100100011000000000000001111100011011011010100110111001 step 40 100001100110100100011010000000000001111100011011011010100110111001 step 41 100001100110100100011011000000000001111100011011011010100110111001 step 42 100001100110100100011011010000000001111100011011011010100110111001 step 43 100001100110100100011011011000000001111100011011011010100110111001 step 44 100001100110100100011011011010000001111100011011011010100110111001 step 45 100001100110100100011011011011000001111100011011011010100110111001 step 46 100001100110100100011011011011010001111100011011011010100110111001 step 47 100001100110100100011011011011011001111100011011011010100110111001 step 48 100001100110100100011011011011011101111100011011011010100110111001 step 49 110001100110100100011011011011011100110111011011011010100110111001 step 50 100001100110100100011011011011011101111100011011011010100110111001 step 51 101001100110100100011011011011011100110111011011011010100110111001 step 52 100001100110100100011011011011011101111100011011011010100110111001 step 53 100101100110100100011011011011011100110111011011011010100110111001 step 54 100001100110100100011011011011011101111100011011011010100110111001 step 55 100011100110100100011011011011011100110111011011011010100110111001 step 56 100001100110100100011011011011011101111100011011011010100110111001 step 57 100001110110100100011011011011011100110111011011011010100110111001 step 58 100001100110100100011011011011011101111100011011011010100110111001 step 59 100001101110100100011011011011011100110111011011011010100110111001 step 60 100001100110100100011011011011011101111100011011011010100110111001 step 61 100001100111100100011011011011011100111101011011011010100110111001 step 62 100001100110100100011011011011011101111100011011011010100110111001 step 63 100001100110110100011011011011011100111101011011011010100110111001 step 64 100001100110100100011011011011011101111100011011011010100110111001 step 65 100001100110101100011011011011011101110110011011011010100110111001 step 66 100001100110100100011011011011011101111100011011011010100110111001 step 67 100001100110100110011011011011011101110110011011011010100110111001 step 68 100001100110100100011011011011011101111100011011011010100110111001 step 69 100001100110100101011011011011011101001111011011011010100110111001 step 70 100001100110100100011011011011011101111100011011011010100110111001 step 71 100001100110100100111011011011011101001111011011011010100110111001 step 72 100001100110100100011011011011011101111100011011011010100110111001 step 73 100001100110100100011111011011011101001111011011011010100110111001 step 74 100001100110100100011011011011011101111100011011011010100110111001 step 75 100001100110100100011011111011011101001111011011011010100110111001 step 76 100001100110100100011011011011011101111100011011011010100110111001 step 77 100001100110100100011011011111011101001111011011011010100110111001 step 78 100001100110100100011011011011011101111100011011011010100110111001 step 79 100001100110100100011011011011111101001111011011011010100110111001 step 80 100001100110100100011011011011011101111100011011011010100110111001 step 81 100001100110100100011011011011011111101110011011011010100110111001 step 82 100001100110100100011011011011011101111100011011011010100110111001 test 2: pass SLOT BAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBAABBAAAAAAAAAAAAAABBBBBBBBAB LETTER ALPSLFMDEEMCBFRSPKLEMFHRSCJLJKUHPNMBBNNVVRKRHUTDJUKANJHBTPDFSVDEVU SIDE 121212122121212121111111112212122222112222111221112112212112212212 DIRECTION IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIOOOOOOOIOOIOOIOOIOOOOIOOIIOOIIO this fail all fails was hi 111111111111111111111111111111111111111111111111111111111111111 1 rising ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ ^^^^^^^^^^^^^^^^^^^^ ^^ falling vvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvv vvvvvvvvvvvvvvvvvvvv vv was lo 00000000000000000000000000000000000000 00000000000000000000 0000 total fails 0, total passes 2 step 1 100000000000000000000000000000000001111100011011011010100110111001 step 2 100000000000000000000000000000000001111100100011011010100110111001 step 3 100000000000000000000000000000000001111100000011011010100110111001 step 4 100000000000000000000000000000000001111100000100011010100110111001 step 5 100000000000000000000000000000000001111100000000011010100110111001 step 6 100000000000000000000000000000000001111100000000100010100110111001 step 7 100000000000000000000000000000000001111100000000000010100110111001 step 8 100000000000000000000000000000000001111100000000000101010110111001 step 9 100000000000000000000000000000000001111100000000000001010110111001 step 10 100000000000000000000000000000000001111100000000000001011000111001 step 11 100000000000000000000000000000000001111100000000000001010000111001 step 12 100000000000000000000000000000000001111100000000000001010001100001 step 13 100000000000000000000000000000000001111100000000000001010000100001 step 14 100000000000000000000000000000000001111100000000000001010000100001 step 15 100000000000010000000000000000000000111101000000000001010000100001 step 16 100000000000010010000000000000000000110111000000000001010000100001 step 17 100000000000010010000000000000000000110111111000000001010000100001 step 18 100000000000010010000000000000000000110111011000000001010000100001 step 19 100000000000010010000000000000000000110111011111000001010000100001 step 20 100000000000010010000000000000000000110111011011000001010000100001 step 21 100000000000010010000000000000000000110111011011111001010000100001 step 22 100000000000010010000000000000000000110111011011011001010000100001 step 23 100000000000010010000000000000000000110111011011011110100000100001 step 24 100000000000010010000000000000000000110111011011011010100000100001 step 25 100000000000010010000000000000000000110111011011011010101110100001 step 26 100000000000010010000000000000000000110111011011011010100110100001 step 27 100000000000010010000000000000000000110111011011011010100111111001 step 28 100000000000010010000000000000000000110111011011011010100110111001 step 29 100000000000000010000000000000000001110110011011011010100110111001 step 30 100000000000000000000000000000000001111100011011011010100110111001 step 31 100000000000000000000000000000000001111100011011011010100110111001 step 32 100001000000000000000000000000000001111100011011011010100110111001 step 33 100001100000000000000000000000000001111100011011011010100110111001 step 34 100001100100000000000000000000000001111100011011011010100110111001 step 35 100001100110000000000000000000000001111100011011011010100110111001 step 36 100001100110100000000000000000000001111100011011011010100110111001 step 37 100001100110100100000000000000000001111100011011011010100110111001 step 38 100001100110100100010000000000000001111100011011011010100110111001 step 39 100001100110100100011000000000000001111100011011011010100110111001 step 40 100001100110100100011010000000000001111100011011011010100110111001 step 41 100001100110100100011011000000000001111100011011011010100110111001 step 42 100001100110100100011011010000000001111100011011011010100110111001 step 43 100001100110100100011011011000000001111100011011011010100110111001 step 44 100001100110100100011011011010000001111100011011011010100110111001 step 45 100001100110100100011011011011000001111100011011011010100110111001 step 46 100001100110100100011011011011010001111100011011011010100110111001 step 47 100001100110100100011011011011011001111100011011011010100110111001 step 48 100001100110100100011011011011011101111100011011011010100110111001 step 49 110001100110100100011011011011011100110111011011011010100110111001 step 50 100001100110100100011011011011011101111100011011011010100110111001 step 51 101001100110100100011011011011011100110111011011011010100110111001 step 52 100001100110100100011011011011011101111100011011011010100110111001 step 53 100101100110100100011011011011011100110111011011011010100110111001 step 54 100001100110100100011011011011011101111100011011011010100110111001 step 55 100011100110100100011011011011011100110111011011011010100110111001 step 56 100001100110100100011011011011011101111100011011011010100110111001 step 57 100001110110100100011011011011011100110111011011011010100110111001 step 58 100001100110100100011011011011011101111100011011011010100110111001 step 59 100001101110100100011011011011011100110111011011011010100110111001 step 60 100001100110100100011011011011011101111100011011011010100110111001 step 61 100001100111100100011011011011011100111101011011011010100110111001 step 62 100001100110100100011011011011011101111100011011011010100110111001 step 63 100001100110110100011011011011011100111101011011011010100110111001 step 64 100001100110100100011011011011011101111100011011011010100110111001 step 65 100001100110101100011011011011011101110110011011011010100110111001 step 66 100001100110100100011011011011011101111100011011011010100110111001 step 67 100001100110100110011011011011011101110110011011011010100110111001 step 68 100001100110100100011011011011011101111100011011011010100110111001 step 69 100001100110100101011011011011011101001111011011011010100110111001 step 70 100001100110100100011011011011011101111100011011011010100110111001 step 71 100001100110100100111011011011011101001111011011011010100110111001 step 72 100001100110100100011011011011011101111100011011011010100110111001 step 73 100001100110100100011111011011011101001111011011011010100110111001 step 74 100001100110100100011011011011011101111100011011011010100110111001 step 75 100001100110100100011011111011011101001111011011011010100110111001 step 76 100001100110100100011011011011011101111100011011011010100110111001 step 77 100001100110100100011011011111011101001111011011011010100110111001 step 78 100001100110100100011011011011011101111100011011011010100110111001 step 79 100001100110100100011011011011111101001111011011011010100110111001 step 80 100001100110100100011011011011011101111100011011011010100110111001 step 81 100001100110100100011011011011011111101110011011011010100110111001 step 82 100001100110100100011011011011011101111100011011011010100110111001 test 3: pass SLOT BAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBAABBAAAAAAAAAAAAAABBBBBBBBAB LETTER ALPSLFMDEEMCBFRSPKLEMFHRSCJLJKUHPNMBBNNVVRKRHUTDJUKANJHBTPDFSVDEVU SIDE 121212122121212121111111112212122222112222111221112112212112212212 DIRECTION IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIOOOOOOOIOOIOOIOOIOOOOIOOIIOOIIO this fail all fails was hi 111111111111111111111111111111111111111111111111111111111111111 1 rising ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ ^^^^^^^^^^^^^^^^^^^^ ^^ falling vvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvv vvvvvvvvvvvvvvvvvvvv vv was lo 00000000000000000000000000000000000000 00000000000000000000 0000 total fails 0, total passes 3 step 1 100000000000000000000000000000000001111100011011011010100110111001 step 2 100000000000000000000000000000000001111100100011011010100110111001 step 3 100000000000000000000000000000000001111100000011011010100110111001 step 4 100000000000000000000000000000000001111100000100011010100110111001 step 5 100000000000000000000000000000000001111100000000011010100110111001 step 6 100000000000000000000000000000000001111100000000100010100110111001 step 7 100000000000000000000000000000000001111100000000000010100110111001 step 8 100000000000000000000000000000000001111100000000000101010110111001 step 9 100000000000000000000000000000000001111100000000000001010110111001 step 10 100000000000000000000000000000000001111100000000000001011000111001 step 11 100000000000000000000000000000000001111100000000000001010000111001 step 12 100000000000000000000000000000000001111100000000000001010001100001 step 13 100000000000000000000000000000000001111100000000000001010000100001 step 14 100000000000000000000000000000000001111100000000000001010000100001 step 15 100000000000010000000000000000000000111101000000000001010000100001 step 16 100000000000010010000000000000000000110111000000000001010000100001 step 17 100000000000010010000000000000000000110111111000000001010000100001 step 18 100000000000010010000000000000000000110111011000000001010000100001 step 19 100000000000010010000000000000000000110111011111000001010000100001 step 20 100000000000010010000000000000000000110111011011000001010000100001 step 21 100000000000010010000000000000000000110111011011111001010000100001 step 22 100000000000010010000000000000000000110111011011011001010000100001 step 23 100000000000010010000000000000000000110111011011011110100000100001 step 24 100000000000010010000000000000000000110111011011011010100000100001 step 25 100000000000010010000000000000000000110111011011011010101110100001 step 26 100000000000010010000000000000000000110111011011011010100110100001 step 27 100000000000010010000000000000000000110111011011011010100111111001 step 28 100000000000010010000000000000000000110111011011011010100110111001 step 29 100000000000000010000000000000000001110110011011011010100110111001 step 30 100000000000000000000000000000000001111100011011011010100110111001 step 31 100000000000000000000000000000000001111100011011011010100110111001 step 32 100001000000000000000000000000000001111100011011011010100110111001 step 33 100001100000000000000000000000000001111100011011011010100110111001 step 34 100001100100000000000000000000000001111100011011011010100110111001 step 35 100001100110000000000000000000000001111100011011011010100110111001 step 36 100001100110100000000000000000000001111100011011011010100110111001 step 37 100001100110100100000000000000000001111100011011011010100110111001 step 38 100001100110100100010000000000000001111100011011011010100110111001 step 39 100001100110100100011000000000000001111100011011011010100110111001 step 40 100001100110100100011010000000000001111100011011011010100110111001 step 41 100001100110100100011011000000000001111100011011011010100110111001 step 42 100001100110100100011011010000000001111100011011011010100110111001 step 43 100001100110100100011011011000000001111100011011011010100110111001 step 44 100001100110100100011011011010000001111100011011011010100110111001 step 45 100001100110100100011011011011000001111100011011011010100110111001 step 46 100001100110100100011011011011010001111100011011011010100110111001 step 47 100001100110100100011011011011011001111100011011011010100110111001 step 48 100001100110100100011011011011011101111100011011011010100110111001 step 49 110001100110100100011011011011011100110111011011011010100110111001 step 50 100001100110100100011011011011011101111100011011011010100110111001 step 51 101001100110100100011011011011011100110111011011011010100110111001 step 52 100001100110100100011011011011011101111100011011011010100110111001 step 53 100101100110100100011011011011011100110111011011011010100110111001 step 54 100001100110100100011011011011011101111100011011011010100110111001 step 55 100011100110100100011011011011011100110111011011011010100110111001 step 56 100001100110100100011011011011011101111100011011011010100110111001 step 57 100001110110100100011011011011011100110111011011011010100110111001 step 58 100001100110100100011011011011011101111100011011011010100110111001 step 59 100001101110100100011011011011011100110111011011011010100110111001 step 60 100001100110100100011011011011011101111100011011011010100110111001 step 61 100001100111100100011011011011011100111101011011011010100110111001 step 62 100001100110100100011011011011011101111100011011011010100110111001 step 63 100001100110110100011011011011011100111101011011011010100110111001 step 64 100001100110100100011011011011011101111100011011011010100110111001 step 65 100001100110101100011011011011011101110110011011011010100110111001 step 66 100001100110100100011011011011011101111100011011011010100110111001 step 67 100001100110100110011011011011011101110110011011011010100110111001 step 68 100001100110100100011011011011011101111100011011011010100110111001 step 69 100001100110100101011011011011011101001111011011011010100110111001 step 70 100001100110100100011011011011011101111100011011011010100110111001 step 71 100001100110100100111011011011011101001111011011011010100110111001 step 72 100001100110100100011011011011011101111100011011011010100110111001 step 73 100001100110100100011111011011011101001111011011011010100110111001 step 74 100001100110100100011011011011011101111100011011011010100110111001 step 75 100001100110100100011011111011011101001111011011011010100110111001 step 76 100001100110100100011011011011011101111100011011011010100110111001 step 77 100001100110100100011011011111011101001111011011011010100110111001 step 78 100001100110100100011011011011011101111100011011011010100110111001 step 79 100001100110100100011011011011111101001111011011011010100110111001 step 80 100001100110100100011011011011011101111100011011011010100110111001 step 81 100001100110100100011011011011011111101110011011011010100110111001 step 82 100001100110100100011011011011011101111100011011011010100110111001 test 4: pass SLOT BAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBAABBAAAAAAAAAAAAAABBBBBBBBAB LETTER ALPSLFMDEEMCBFRSPKLEMFHRSCJLJKUHPNMBBNNVVRKRHUTDJUKANJHBTPDFSVDEVU SIDE 121212122121212121111111112212122222112222111221112112212112212212 DIRECTION IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIOOOOOOOIOOIOOIOOIOOOOIOOIIOOIIO this fail all fails was hi 111111111111111111111111111111111111111111111111111111111111111 1 rising ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ ^^^^^^^^^^^^^^^^^^^^ ^^ falling vvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvv vvvvvvvvvvvvvvvvvvvv vv was lo 00000000000000000000000000000000000000 00000000000000000000 0000 total fails 0, total passes 4 step 1 100000000000000000000000000000000001111100011011011010100110111001 step 2 100000000000000000000000000000000001111100100011011010100110111001 step 3 100000000000000000000000000000000001111100000011011010100110111001 step 4 100000000000000000000000000000000001111100000100011010100110111001 step 5 100000000000000000000000000000000001111100000000011010100110111001 step 6 100000000000000000000000000000000001111100000000100010100110111001 step 7 100000000000000000000000000000000001111100000000000010100110111001 step 8 100000000000000000000000000000000001111100000000000101010110111001 step 9 100000000000000000000000000000000001111100000000000001010110111001 step 10 100000000000000000000000000000000001111100000000000001011000111001 step 11 100000000000000000000000000000000001111100000000000001010000111001 step 12 100000000000000000000000000000000001111100000000000001010001100001 step 13 100000000000000000000000000000000001111100000000000001010000100001 step 14 100000000000000000000000000000000001111100000000000001010000100001 step 15 100000000000010000000000000000000000111101000000000001010000100001 step 16 100000000000010010000000000000000000110111000000000001010000100001 step 17 100000000000010010000000000000000000110111111000000001010000100001 step 18 100000000000010010000000000000000000110111011000000001010000100001 step 19 100000000000010010000000000000000000110111011111000001010000100001 step 20 100000000000010010000000000000000000110111011011000001010000100001 step 21 100000000000010010000000000000000000110111011011111001010000100001 step 22 100000000000010010000000000000000000110111011011011001010000100001 step 23 100000000000010010000000000000000000110111011011011110100000100001 step 24 100000000000010010000000000000000000110111011011011010100000100001 step 25 100000000000010010000000000000000000110111011011011010101110100001 step 26 100000000000010010000000000000000000110111011011011010100110100001 step 27 100000000000010010000000000000000000110111011011011010100111111001 step 28 100000000000010010000000000000000000110111011011011010100110111001 step 29 100000000000000010000000000000000001110110011011011010100110111001 step 30 100000000000000000000000000000000001111100011011011010100110111001 step 31 100000000000000000000000000000000001111100011011011010100110111001 step 32 100001000000000000000000000000000001111100011011011010100110111001 step 33 100001100000000000000000000000000001111100011011011010100110111001 step 34 100001100100000000000000000000000001111100011011011010100110111001 step 35 100001100110000000000000000000000001111100011011011010100110111001 step 36 100001100110100000000000000000000001111100011011011010100110111001 step 37 100001100110100100000000000000000001111100011011011010100110111001 step 38 100001100110100100010000000000000001111100011011011010100110111001 step 39 100001100110100100011000000000000001111100011011011010100110111001 step 40 100001100110100100011010000000000001111100011011011010100110111001 step 41 100001100110100100011011000000000001111100011011011010100110111001 step 42 100001100110100100011011010000000001111100011011011010100110111001 step 43 100001100110100100011011011000000001111100011011011010100110111001 step 44 100001100110100100011011011010000001111100011011011010100110111001 step 45 100001100110100100011011011011000001111100011011011010100110111001 step 46 100001100110100100011011011011010001111100011011011010100110111001 step 47 100001100110100100011011011011011001111100011011011010100110111001 step 48 100001100110100100011011011011011101111100011011011010100110111001 step 49 110001100110100100011011011011011100110111011011011010100110111001 step 50 100001100110100100011011011011011101111100011011011010100110111001 step 51 101001100110100100011011011011011100110111011011011010100110111001 step 52 100001100110100100011011011011011101111100011011011010100110111001 step 53 100101100110100100011011011011011100110111011011011010100110111001 step 54 100001100110100100011011011011011101111100011011011010100110111001 step 55 100011100110100100011011011011011100110111011011011010100110111001 step 56 100001100110100100011011011011011101111100011011011010100110111001 step 57 100001110110100100011011011011011100110111011011011010100110111001 step 58 100001100110100100011011011011011101111100011011011010100110111001 step 59 100001101110100100011011011011011100110111011011011010100110111001 step 60 100001100110100100011011011011011101111100011011011010100110111001 step 61 100001100111100100011011011011011100111101011011011010100110111001 step 62 100001100110100100011011011011011101111100011011011010100110111001 step 63 100001100110110100011011011011011100111101011011011010100110111001 step 64 100001100110100100011011011011011101111100011011011010100110111001 step 65 100001100110101100011011011011011101110110011011011010100110111001 step 66 100001100110100100011011011011011101111100011011011010100110111001 step 67 100001100110100110011011011011011101110110011011011010100110111001 step 68 100001100110100100011011011011011101111100011011011010100110111001 step 69 100001100110100101011011011011011101001111011011011010100110111001 step 70 100001100110100100011011011011011101111100011011011010100110111001 step 71 100001100110100100111011011011011101001111011011011010100110111001 step 72 100001100110100100011011011011011101111100011011011010100110111001 step 73 100001100110100100011111011011011101001111011011011010100110111001 step 74 100001100110100100011011011011011101111100011011011010100110111001 step 75 100001100110100100011011111011011101001111011011011010100110111001 step 76 100001100110100100011011011011011101111100011011011010100110111001 step 77 100001100110100100011011011111011101001111011011011010100110111001 step 78 100001100110100100011011011011011101111100011011011010100110111001 step 79 100001100110100100011011011011111101001111011011011010100110111001 step 80 100001100110100100011011011011011101111100011011011010100110111001 step 81 100001100110100100011011011011011111101110011011011010100110111001 step 82 100001100110100100011011011011011101111100011011011010100110111001 test 5: pass SLOT BAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBAABBAAAAAAAAAAAAAABBBBBBBBAB LETTER ALPSLFMDEEMCBFRSPKLEMFHRSCJLJKUHPNMBBNNVVRKRHUTDJUKANJHBTPDFSVDEVU SIDE 121212122121212121111111112212122222112222111221112112212112212212 DIRECTION IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIOOOOOOOIOOIOOIOOIOOOOIOOIIOOIIO this fail all fails was hi 111111111111111111111111111111111111111111111111111111111111111 1 rising ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ ^^^^^^^^^^^^^^^^^^^^ ^^ falling vvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvv vvvvvvvvvvvvvvvvvvvv vv was lo 00000000000000000000000000000000000000 00000000000000000000 0000 total fails 0, total passes 5 step 1 100000000000000000000000000000000001111100011011011010100110111001 step 2 100000000000000000000000000000000001111100100011011010100110111001 step 3 100000000000000000000000000000000001111100000011011010100110111001 step 4 100000000000000000000000000000000001111100000100011010100110111001 step 5 100000000000000000000000000000000001111100000000011010100110111001 step 6 100000000000000000000000000000000001111100000000100010100110111001 step 7 100000000000000000000000000000000001111100000000000010100110111001 step 8 100000000000000000000000000000000001111100000000000101010110111001 step 9 100000000000000000000000000000000001111100000000000001010110111001 step 10 100000000000000000000000000000000001111100000000000001011000111001 step 11 100000000000000000000000000000000001111100000000000001010000111001 step 12 100000000000000000000000000000000001111100000000000001010001100001 step 13 100000000000000000000000000000000001111100000000000001010000100001 step 14 100000000000000000000000000000000001111100000000000001010000100001 step 15 100000000000010000000000000000000000111101000000000001010000100001 step 16 100000000000010010000000000000000000110111000000000001010000100001 step 17 100000000000010010000000000000000000110111111000000001010000100001 step 18 100000000000010010000000000000000000110111011000000001010000100001 step 19 100000000000010010000000000000000000110111011111000001010000100001 step 20 100000000000010010000000000000000000110111011011000001010000100001 step 21 100000000000010010000000000000000000110111011011111001010000100001 step 22 100000000000010010000000000000000000110111011011011001010000100001 step 23 100000000000010010000000000000000000110111011011011110100000100001 step 24 100000000000010010000000000000000000110111011011011010100000100001 step 25 100000000000010010000000000000000000110111011011011010101110100001 step 26 100000000000010010000000000000000000110111011011011010100110100001 step 27 100000000000010010000000000000000000110111011011011010100111111001 step 28 100000000000010010000000000000000000110111011011011010100110111001 step 29 100000000000000010000000000000000001110110011011011010100110111001 step 30 100000000000000000000000000000000001111100011011011010100110111001 step 31 100000000000000000000000000000000001111100011011011010100110111001 step 32 100001000000000000000000000000000001111100011011011010100110111001 step 33 100001100000000000000000000000000001111100011011011010100110111001 step 34 100001100100000000000000000000000001111100011011011010100110111001 step 35 100001100110000000000000000000000001111100011011011010100110111001 step 36 100001100110100000000000000000000001111100011011011010100110111001 step 37 100001100110100100000000000000000001111100011011011010100110111001 step 38 100001100110100100010000000000000001111100011011011010100110111001 step 39 100001100110100100011000000000000001111100011011011010100110111001 step 40 100001100110100100011010000000000001111100011011011010100110111001 step 41 100001100110100100011011000000000001111100011011011010100110111001 step 42 100001100110100100011011010000000001111100011011011010100110111001 step 43 100001100110100100011011011000000001111100011011011010100110111001 step 44 100001100110100100011011011010000001111100011011011010100110111001 step 45 100001100110100100011011011011000001111100011011011010100110111001 step 46 100001100110100100011011011011010001111100011011011010100110111001 step 47 100001100110100100011011011011011001111100011011011010100110111001 step 48 100001100110100100011011011011011101111100011011011010100110111001 step 49 110001100110100100011011011011011100110111011011011010100110111001 step 50 100001100110100100011011011011011101111100011011011010100110111001 step 51 101001100110100100011011011011011100110111011011011010100110111001 step 52 100001100110100100011011011011011101111100011011011010100110111001 step 53 100101100110100100011011011011011100110111011011011010100110111001 step 54 100001100110100100011011011011011101111100011011011010100110111001 step 55 100011100110100100011011011011011100110111011011011010100110111001 step 56 100001100110100100011011011011011101111100011011011010100110111001 step 57 100001110110100100011011011011011100110111011011011010100110111001 step 58 100001100110100100011011011011011101111100011011011010100110111001 step 59 100001101110100100011011011011011100110111011011011010100110111001 step 60 100001100110100100011011011011011101111100011011011010100110111001 step 61 100001100111100100011011011011011100111101011011011010100110111001 step 62 100001100110100100011011011011011101111100011011011010100110111001 step 63 100001100110110100011011011011011100111101011011011010100110111001 step 64 100001100110100100011011011011011101111100011011011010100110111001 step 65 100001100110101100011011011011011101110110011011011010100110111001 step 66 100001100110100100011011011011011101111100011011011010100110111001 step 67 100001100110100110011011011011011101110110011011011010100110111001 step 68 100001100110100100011011011011011101111100011011011010100110111001 step 69 100001100110100101011011011011011101001111011011011010100110111001 step 70 100001100110100100011011011011011101111100011011011010100110111001 step 71 100001100110100100111011011011011101001111011011011010100110111001 step 72 100001100110100100011011011011011101111100011011011010100110111001 step 73 100001100110100100011111011011011101001111011011011010100110111001 step 74 100001100110100100011011011011011101111100011011011010100110111001 step 75 100001100110100100011011111011011101001111011011011010100110111001 step 76 100001100110100100011011011011011101111100011011011010100110111001 step 77 100001100110100100011011011111011101001111011011011010100110111001 step 78 100001100110100100011011011011011101111100011011011010100110111001 step 79 100001100110100100011011011011111101001111011011011010100110111001 step 80 100001100110100100011011011011011101111100011011011010100110111001 step 81 100001100110100100011011011011011111101110011011011010100110111001 step 82 100001100110100100011011011011011101111100011011011010100110111001 test 6: pass SLOT BAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBAABBAAAAAAAAAAAAAABBBBBBBBAB LETTER ALPSLFMDEEMCBFRSPKLEMFHRSCJLJKUHPNMBBNNVVRKRHUTDJUKANJHBTPDFSVDEVU SIDE 121212122121212121111111112212122222112222111221112112212112212212 DIRECTION IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIOOOOOOOIOOIOOIOOIOOOOIOOIIOOIIO this fail all fails was hi 111111111111111111111111111111111111111111111111111111111111111 1 rising ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ ^^^^^^^^^^^^^^^^^^^^ ^^ falling vvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvv vvvvvvvvvvvvvvvvvvvv vv was lo 00000000000000000000000000000000000000 00000000000000000000 0000 total fails 0, total passes 6 step 1 100000000000000000000000000000000001111100011011011010100110111001 step 2 100000000000000000000000000000000001111100100011011010100110111001 step 3 100000000000000000000000000000000001111100000011011010100110111001 step 4 100000000000000000000000000000000001111100000100011010100110111001 step 5 100000000000000000000000000000000001111100000000011010100110111001 step 6 100000000000000000000000000000000001111100000000100010100110111001 step 7 100000000000000000000000000000000001111100000000000010100110111001 step 8 100000000000000000000000000000000001111100000000000101010110111001 step 9 100000000000000000000000000000000001111100000000000001010110111001 step 10 100000000000000000000000000000000001111100000000000001011000111001 step 11 100000000000000000000000000000000001111100000000000001010000111001 step 12 100000000000000000000000000000000001111100000000000001010001100001 step 13 100000000000000000000000000000000001111100000000000001010000100001 step 14 100000000000000000000000000000000001111100000000000001010000100001 step 15 100000000000010000000000000000000000111101000000000001010000100001 step 16 100000000000010010000000000000000000110111000000000001010000100001 step 17 100000000000010010000000000000000000110111111000000001010000100001 step 18 100000000000010010000000000000000000110111011000000001010000100001 step 19 100000000000010010000000000000000000110111011111000001010000100001 step 20 100000000000010010000000000000000000110111011011000001010000100001 step 21 100000000000010010000000000000000000110111011011111001010000100001 step 22 100000000000010010000000000000000000110111011011011001010000100001 step 23 100000000000010010000000000000000000110111011011011110100000100001 step 24 100000000000010010000000000000000000110111011011011010100000100001 step 25 100000000000010010000000000000000000110111011011011010101110100001 step 26 100000000000010010000000000000000000110111011011011010100110100001 step 27 100000000000010010000000000000000000110111011011011010100111111001 step 28 100000000000010010000000000000000000110111011011011010100110111001 step 29 100000000000000010000000000000000001110110011011011010100110111001 step 30 100000000000000000000000000000000001111100011011011010100110111001 step 31 100000000000000000000000000000000001111100011011011010100110111001 step 32 100001000000000000000000000000000001111100011011011010100110111001 step 33 100001100000000000000000000000000001111100011011011010100110111001 step 34 100001100100000000000000000000000001111100011011011010100110111001 step 35 100001100110000000000000000000000001111100011011011010100110111001 step 36 100001100110100000000000000000000001111100011011011010100110111001 step 37 100001100110100100000000000000000001111100011011011010100110111001 step 38 100001100110100100010000000000000001111100011011011010100110111001 step 39 100001100110100100011000000000000001111100011011011010100110111001 step 40 100001100110100100011010000000000001111100011011011010100110111001 step 41 100001100110100100011011000000000001111100011011011010100110111001 step 42 100001100110100100011011010000000001111100011011011010100110111001 step 43 100001100110100100011011011000000001111100011011011010100110111001 step 44 100001100110100100011011011010000001111100011011011010100110111001 step 45 100001100110100100011011011011000001111100011011011010100110111001 step 46 100001100110100100011011011011010001111100011011011010100110111001 step 47 100001100110100100011011011011011001111100011011011010100110111001 step 48 100001100110100100011011011011011101111100011011011010100110111001 step 49 110001100110100100011011011011011100110111011011011010100110111001 step 50 100001100110100100011011011011011101111100011011011010100110111001 step 51 101001100110100100011011011011011100110111011011011010100110111001 step 52 100001100110100100011011011011011101111100011011011010100110111001 step 53 100101100110100100011011011011011100110111011011011010100110111001 step 54 100001100110100100011011011011011101111100011011011010100110111001 step 55 100011100110100100011011011011011100110111011011011010100110111001 step 56 100001100110100100011011011011011101111100011011011010100110111001 step 57 100001110110100100011011011011011100110111011011011010100110111001 step 58 100001100110100100011011011011011101111100011011011010100110111001 step 59 100001101110100100011011011011011100110111011011011010100110111001 step 60 100001100110100100011011011011011101111100011011011010100110111001 step 61 100001100111100100011011011011011100111101011011011010100110111001 step 62 100001100110100100011011011011011101111100011011011010100110111001 step 63 100001100110110100011011011011011100111101011011011010100110111001 step 64 100001100110100100011011011011011101111100011011011010100110111001 step 65 100001100110101100011011011011011101110110011011011010100110111001 step 66 100001100110100100011011011011011101111100011011011010100110111001 step 67 100001100110100110011011011011011101110110011011011010100110111001 step 68 100001100110100100011011011011011101111100011011011010100110111001 step 69 100001100110100101011011011011011101001111011011011010100110111001 step 70 100001100110100100011011011011011101111100011011011010100110111001 step 71 100001100110100100111011011011011101001111011011011010100110111001 step 72 100001100110100100011011011011011101111100011011011010100110111001 step 73 100001100110100100011111011011011101001111011011011010100110111001 step 74 100001100110100100011011011011011101111100011011011010100110111001 step 75 100001100110100100011011111011011101001111011011011010100110111001 step 76 100001100110100100011011011011011101111100011011011010100110111001 step 77 100001100110100100011011011111011101001111011011011010100110111001 step 78 100001100110100100011011011011011101111100011011011010100110111001 step 79 100001100110100100011011011011111101001111011011011010100110111001 step 80 100001100110100100011011011011011101111100011011011010100110111001 step 81 100001100110100100011011011011011111101110011011011010100110111001 step 82 100001100110100100011011011011011101111100011011011010100110111001 test 7: pass SLOT BAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBAABBAAAAAAAAAAAAAABBBBBBBBAB LETTER ALPSLFMDEEMCBFRSPKLEMFHRSCJLJKUHPNMBBNNVVRKRHUTDJUKANJHBTPDFSVDEVU SIDE 121212122121212121111111112212122222112222111221112112212112212212 DIRECTION IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIOOOOOOOIOOIOOIOOIOOOOIOOIIOOIIO this fail all fails was hi 111111111111111111111111111111111111111111111111111111111111111 1 rising ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ ^^^^^^^^^^^^^^^^^^^^ ^^ falling vvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvv vvvvvvvvvvvvvvvvvvvv vv was lo 00000000000000000000000000000000000000 00000000000000000000 0000 total fails 0, total passes 7 step 1 100000000000000000000000000000000001111100011011011010100110111001 step 2 100000000000000000000000000000000001111100100011011010100110111001 step 3 100000000000000000000000000000000001111100000011011010100110111001 step 4 100000000000000000000000000000000001111100000100011010100110111001 step 5 100000000000000000000000000000000001111100000000011010100110111001 step 6 100000000000000000000000000000000001111100000000100010100110111001 step 7 100000000000000000000000000000000001111100000000000010100110111001 step 8 100000000000000000000000000000000001111100000000000101010110111001 step 9 100000000000000000000000000000000001111100000000000001010110111001 step 10 100000000000000000000000000000000001111100000000000001011000111001 step 11 100000000000000000000000000000000001111100000000000001010000111001 step 12 100000000000000000000000000000000001111100000000000001010001100001 step 13 100000000000000000000000000000000001111100000000000001010000100001 step 14 100000000000000000000000000000000001111100000000000001010000100001 step 15 100000000000010000000000000000000000111101000000000001010000100001 step 16 100000000000010010000000000000000000110111000000000001010000100001 step 17 100000000000010010000000000000000000110111111000000001010000100001 step 18 100000000000010010000000000000000000110111011000000001010000100001 step 19 100000000000010010000000000000000000110111011111000001010000100001 step 20 100000000000010010000000000000000000110111011011000001010000100001 step 21 100000000000010010000000000000000000110111011011111001010000100001 step 22 100000000000010010000000000000000000110111011011011001010000100001 step 23 100000000000010010000000000000000000110111011011011110100000100001 step 24 100000000000010010000000000000000000110111011011011010100000100001 step 25 100000000000010010000000000000000000110111011011011010101110100001 step 26 100000000000010010000000000000000000110111011011011010100110100001 step 27 100000000000010010000000000000000000110111011011011010100111111001 step 28 100000000000010010000000000000000000110111011011011010100110111001 step 29 100000000000000010000000000000000001110110011011011010100110111001 step 30 100000000000000000000000000000000001111100011011011010100110111001 step 31 100000000000000000000000000000000001111100011011011010100110111001 step 32 100001000000000000000000000000000001111100011011011010100110111001 step 33 100001100000000000000000000000000001111100011011011010100110111001 step 34 100001100100000000000000000000000001111100011011011010100110111001 step 35 100001100110000000000000000000000001111100011011011010100110111001 step 36 100001100110100000000000000000000001111100011011011010100110111001 step 37 100001100110100100000000000000000001111100011011011010100110111001 step 38 100001100110100100010000000000000001111100011011011010100110111001 step 39 100001100110100100011000000000000001111100011011011010100110111001 step 40 100001100110100100011010000000000001111100011011011010100110111001 step 41 100001100110100100011011000000000001111100011011011010100110111001 step 42 100001100110100100011011010000000001111100011011011010100110111001 step 43 100001100110100100011011011000000001111100011011011010100110111001 step 44 100001100110100100011011011010000001111100011011011010100110111001 step 45 100001100110100100011011011011000001111100011011011010100110111001 step 46 100001100110100100011011011011010001111100011011011010100110111001 step 47 100001100110100100011011011011011001111100011011011010100110111001 step 48 100001100110100100011011011011011101111100011011011010100110111001 step 49 110001100110100100011011011011011100110111011011011010100110111001 step 50 100001100110100100011011011011011101111100011011011010100110111001 step 51 101001100110100100011011011011011100110111011011011010100110111001 step 52 100001100110100100011011011011011101111100011011011010100110111001 step 53 100101100110100100011011011011011100110111011011011010100110111001 step 54 100001100110100100011011011011011101111100011011011010100110111001 step 55 100011100110100100011011011011011100110111011011011010100110111001 step 56 100001100110100100011011011011011101111100011011011010100110111001 step 57 100001110110100100011011011011011100110111011011011010100110111001 step 58 100001100110100100011011011011011101111100011011011010100110111001 step 59 100001101110100100011011011011011100110111011011011010100110111001 step 60 100001100110100100011011011011011101111100011011011010100110111001 step 61 100001100111100100011011011011011100111101011011011010100110111001 step 62 100001100110100100011011011011011101111100011011011010100110111001 step 63 100001100110110100011011011011011100111101011011011010100110111001 step 64 100001100110100100011011011011011101111100011011011010100110111001 step 65 100001100110101100011011011011011101110110011011011010100110111001 step 66 100001100110100100011011011011011101111100011011011010100110111001 step 67 100001100110100110011011011011011101110110011011011010100110111001 step 68 100001100110100100011011011011011101111100011011011010100110111001 step 69 100001100110100101011011011011011101001111011011011010100110111001 step 70 100001100110100100011011011011011101111100011011011010100110111001 step 71 100001100110100100111011011011011101001111011011011010100110111001 step 72 100001100110100100011011011011011101111100011011011010100110111001 step 73 100001100110100100011111011011011101001111011011011010100110111001 step 74 100001100110100100011011011011011101111100011011011010100110111001 step 75 100001100110100100011011111011011101001111011011011010100110111001 step 76 100001100110100100011011011011011101111100011011011010100110111001 step 77 100001100110100100011011011111011101001111011011011010100110111001 step 78 100001100110100100011011011011011101111100011011011010100110111001 step 79 100001100110100100011011011011111101001111011011011010100110111001 step 80 100001100110100100011011011011011101111100011011011010100110111001 step 81 100001100110100100011011011011011111101110011011011010100110111001 step 82 100001100110100100011011011011011101111100011011011010100110111001 test 8: pass SLOT BAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBAABBAAAAAAAAAAAAAABBBBBBBBAB LETTER ALPSLFMDEEMCBFRSPKLEMFHRSCJLJKUHPNMBBNNVVRKRHUTDJUKANJHBTPDFSVDEVU SIDE 121212122121212121111111112212122222112222111221112112212112212212 DIRECTION IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIOOOOOOOIOOIOOIOOIOOOOIOOIIOOIIO this fail all fails was hi 111111111111111111111111111111111111111111111111111111111111111 1 rising ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ ^^^^^^^^^^^^^^^^^^^^ ^^ falling vvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvv vvvvvvvvvvvvvvvvvvvv vv was lo 00000000000000000000000000000000000000 00000000000000000000 0000 total fails 0, total passes 8 step 1 100000000000000000000000000000000001111100011011011010100110111001 step 2 100000000000000000000000000000000001111100100011011010100110111001 step 3 100000000000000000000000000000000001111100000011011010100110111001 step 4 100000000000000000000000000000000001111100000100011010100110111001 step 5 100000000000000000000000000000000001111100000000011010100110111001 step 6 100000000000000000000000000000000001111100000000100010100110111001 step 7 100000000000000000000000000000000001111100000000000010100110111001 step 8 100000000000000000000000000000000001111100000000000101010110111001 step 9 100000000000000000000000000000000001111100000000000001010110111001 step 10 100000000000000000000000000000000001111100000000000001011000111001 step 11 100000000000000000000000000000000001111100000000000001010000111001 step 12 100000000000000000000000000000000001111100000000000001010001100001 step 13 100000000000000000000000000000000001111100000000000001010000100001 step 14 100000000000000000000000000000000001111100000000000001010000100001 step 15 100000000000010000000000000000000000111101000000000001010000100001 step 16 100000000000010010000000000000000000110111000000000001010000100001 step 17 100000000000010010000000000000000000110111111000000001010000100001 step 18 100000000000010010000000000000000000110111011000000001010000100001 step 19 100000000000010010000000000000000000110111011111000001010000100001 step 20 100000000000010010000000000000000000110111011011000001010000100001 step 21 100000000000010010000000000000000000110111011011111001010000100001 step 22 100000000000010010000000000000000000110111011011011001010000100001 step 23 100000000000010010000000000000000000110111011011011110100000100001 step 24 100000000000010010000000000000000000110111011011011010100000100001 step 25 100000000000010010000000000000000000110111011011011010101110100001 step 26 100000000000010010000000000000000000110111011011011010100110100001 step 27 100000000000010010000000000000000000110111011011011010100111111001 step 28 100000000000010010000000000000000000110111011011011010100110111001 step 29 100000000000000010000000000000000001110110011011011010100110111001 step 30 100000000000000000000000000000000001111100011011011010100110111001 step 31 100000000000000000000000000000000001111100011011011010100110111001 step 32 100001000000000000000000000000000001111100011011011010100110111001 step 33 100001100000000000000000000000000001111100011011011010100110111001 step 34 100001100100000000000000000000000001111100011011011010100110111001 step 35 100001100110000000000000000000000001111100011011011010100110111001 step 36 100001100110100000000000000000000001111100011011011010100110111001 step 37 100001100110100100000000000000000001111100011011011010100110111001 step 38 100001100110100100010000000000000001111100011011011010100110111001 step 39 100001100110100100011000000000000001111100011011011010100110111001 step 40 100001100110100100011010000000000001111100011011011010100110111001 step 41 100001100110100100011011000000000001111100011011011010100110111001 step 42 100001100110100100011011010000000001111100011011011010100110111001 step 43 100001100110100100011011011000000001111100011011011010100110111001 step 44 100001100110100100011011011010000001111100011011011010100110111001 step 45 100001100110100100011011011011000001111100011011011010100110111001 step 46 100001100110100100011011011011010001111100011011011010100110111001 step 47 100001100110100100011011011011011001111100011011011010100110111001 step 48 100001100110100100011011011011011101111100011011011010100110111001 step 49 110001100110100100011011011011011100110111011011011010100110111001 step 50 100001100110100100011011011011011101111100011011011010100110111001 step 51 101001100110100100011011011011011100110111011011011010100110111001 step 52 100001100110100100011011011011011101111100011011011010100110111001 step 53 100101100110100100011011011011011100110111011011011010100110111001 step 54 100001100110100100011011011011011101111100011011011010100110111001 step 55 100011100110100100011011011011011100110111011011011010100110111001 step 56 100001100110100100011011011011011101111100011011011010100110111001 step 57 100001110110100100011011011011011100110111011011011010100110111001 step 58 100001100110100100011011011011011101111100011011011010100110111001 step 59 100001101110100100011011011011011100110111011011011010100110111001 step 60 100001100110100100011011011011011101111100011011011010100110111001 step 61 100001100111100100011011011011011100111101011011011010100110111001 step 62 100001100110100100011011011011011101111100011011011010100110111001 step 63 100001100110110100011011011011011100111101011011011010100110111001 step 64 100001100110100100011011011011011101111100011011011010100110111001 step 65 100001100110101100011011011011011101110110011011011010100110111001 step 66 100001100110100100011011011011011101111100011011011010100110111001 step 67 100001100110100110011011011011011101110110011011011010100110111001 step 68 100001100110100100011011011011011101111100011011011010100110111001 step 69 100001100110100101011011011011011101001111011011011010100110111001 step 70 100001100110100100011011011011011101111100011011011010100110111001 step 71 100001100110100100111011011011011101001111011011011010100110111001 step 72 100001100110100100011011011011011101111100011011011010100110111001 step 73 100001100110100100011111011011011101001111011011011010100110111001 step 74 100001100110100100011011011011011101111100011011011010100110111001 step 75 100001100110100100011011111011011101001111011011011010100110111001 step 76 100001100110100100011011011011011101111100011011011010100110111001 step 77 100001100110100100011011011111011101001111011011011010100110111001 step 78 100001100110100100011011011011011101111100011011011010100110111001 step 79 100001100110100100011011011011111101001111011011011010100110111001 step 80 100001100110100100011011011011011101111100011011011010100110111001 step 81 100001100110100100011011011011011111101110011011011010100110111001 step 82 100001100110100100011011011011011101111100011011011010100110111001 test 9: pass SLOT BAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBAABBAAAAAAAAAAAAAABBBBBBBBAB LETTER ALPSLFMDEEMCBFRSPKLEMFHRSCJLJKUHPNMBBNNVVRKRHUTDJUKANJHBTPDFSVDEVU SIDE 121212122121212121111111112212122222112222111221112112212112212212 DIRECTION IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIOOOOOOOIOOIOOIOOIOOOOIOOIIOOIIO this fail all fails was hi 111111111111111111111111111111111111111111111111111111111111111 1 rising ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ ^^^^^^^^^^^^^^^^^^^^ ^^ falling vvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvv vvvvvvvvvvvvvvvvvvvv vv was lo 00000000000000000000000000000000000000 00000000000000000000 0000 total fails 0, total passes 9 step 1 100000000000000000000000000000000001111100011011011010100110111001 step 2 100000000000000000000000000000000001111100100011011010100110111001 step 3 100000000000000000000000000000000001111100000011011010100110111001 step 4 100000000000000000000000000000000001111100000100011010100110111001 step 5 100000000000000000000000000000000001111100000000011010100110111001 step 6 100000000000000000000000000000000001111100000000100010100110111001 step 7 100000000000000000000000000000000001111100000000000010100110111001 step 8 100000000000000000000000000000000001111100000000000101010110111001 step 9 100000000000000000000000000000000001111100000000000001010110111001 step 10 100000000000000000000000000000000001111100000000000001011000111001 step 11 100000000000000000000000000000000001111100000000000001010000111001 step 12 100000000000000000000000000000000001111100000000000001010001100001 step 13 100000000000000000000000000000000001111100000000000001010000100001 step 14 100000000000000000000000000000000001111100000000000001010000100001 step 15 100000000000010000000000000000000000111101000000000001010000100001 step 16 100000000000010010000000000000000000110111000000000001010000100001 step 17 100000000000010010000000000000000000110111111000000001010000100001 step 18 100000000000010010000000000000000000110111011000000001010000100001 step 19 100000000000010010000000000000000000110111011111000001010000100001 step 20 100000000000010010000000000000000000110111011011000001010000100001 step 21 100000000000010010000000000000000000110111011011111001010000100001 step 22 100000000000010010000000000000000000110111011011011001010000100001 step 23 100000000000010010000000000000000000110111011011011110100000100001 step 24 100000000000010010000000000000000000110111011011011010100000100001 step 25 100000000000010010000000000000000000110111011011011010101110100001 step 26 100000000000010010000000000000000000110111011011011010100110100001 step 27 100000000000010010000000000000000000110111011011011010100111111001 step 28 100000000000010010000000000000000000110111011011011010100110111001 step 29 100000000000000010000000000000000001110110011011011010100110111001 step 30 100000000000000000000000000000000001111100011011011010100110111001 step 31 100000000000000000000000000000000001111100011011011010100110111001 step 32 100001000000000000000000000000000001111100011011011010100110111001 step 33 100001100000000000000000000000000001111100011011011010100110111001 step 34 100001100100000000000000000000000001111100011011011010100110111001 step 35 100001100110000000000000000000000001111100011011011010100110111001 step 36 100001100110100000000000000000000001111100011011011010100110111001 step 37 100001100110100100000000000000000001111100011011011010100110111001 step 38 100001100110100100010000000000000001111100011011011010100110111001 step 39 100001100110100100011000000000000001111100011011011010100110111001 step 40 100001100110100100011010000000000001111100011011011010100110111001 step 41 100001100110100100011011000000000001111100011011011010100110111001 step 42 100001100110100100011011010000000001111100011011011010100110111001 step 43 100001100110100100011011011000000001111100011011011010100110111001 step 44 100001100110100100011011011010000001111100011011011010100110111001 step 45 100001100110100100011011011011000001111100011011011010100110111001 step 46 100001100110100100011011011011010001111100011011011010100110111001 step 47 100001100110100100011011011011011001111100011011011010100110111001 step 48 100001100110100100011011011011011101111100011011011010100110111001 step 49 110001100110100100011011011011011100110111011011011010100110111001 step 50 100001100110100100011011011011011101111100011011011010100110111001 step 51 101001100110100100011011011011011100110111011011011010100110111001 step 52 100001100110100100011011011011011101111100011011011010100110111001 step 53 100101100110100100011011011011011100110111011011011010100110111001 step 54 100001100110100100011011011011011101111100011011011010100110111001 step 55 100011100110100100011011011011011100110111011011011010100110111001 step 56 100001100110100100011011011011011101111100011011011010100110111001 step 57 100001110110100100011011011011011100110111011011011010100110111001 step 58 100001100110100100011011011011011101111100011011011010100110111001 step 59 100001101110100100011011011011011100110111011011011010100110111001 step 60 100001100110100100011011011011011101111100011011011010100110111001 step 61 100001100111100100011011011011011100111101011011011010100110111001 step 62 100001100110100100011011011011011101111100011011011010100110111001 step 63 100001100110110100011011011011011100111101011011011010100110111001 step 64 100001100110100100011011011011011101111100011011011010100110111001 step 65 100001100110101100011011011011011101110110011011011010100110111001 step 66 100001100110100100011011011011011101111100011011011010100110111001 step 67 100001100110100110011011011011011101110110011011011010100110111001 step 68 100001100110100100011011011011011101111100011011011010100110111001 step 69 100001100110100101011011011011011101001111011011011010100110111001 step 70 100001100110100100011011011011011101111100011011011010100110111001 step 71 100001100110100100111011011011011101001111011011011010100110111001 step 72 100001100110100100011011011011011101111100011011011010100110111001 step 73 100001100110100100011111011011011101001111011011011010100110111001 step 74 100001100110100100011011011011011101111100011011011010100110111001 step 75 100001100110100100011011111011011101001111011011011010100110111001 step 76 100001100110100100011011011011011101111100011011011010100110111001 step 77 100001100110100100011011011111011101001111011011011010100110111001 step 78 100001100110100100011011011011011101111100011011011010100110111001 step 79 100001100110100100011011011011111101001111011011011010100110111001 step 80 100001100110100100011011011011011101111100011011011010100110111001 step 81 100001100110100100011011011011011111101110011011011010100110111001 step 82 100001100110100100011011011011011101111100011011011010100110111001 test 10: pass SLOT BAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBAABBAAAAAAAAAAAAAABBBBBBBBAB LETTER ALPSLFMDEEMCBFRSPKLEMFHRSCJLJKUHPNMBBNNVVRKRHUTDJUKANJHBTPDFSVDEVU SIDE 121212122121212121111111112212122222112222111221112112212112212212 DIRECTION IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIOOOOOOOIOOIOOIOOIOOOOIOOIIOOIIO this fail all fails was hi 111111111111111111111111111111111111111111111111111111111111111 1 rising ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ ^^^^^^^^^^^^^^^^^^^^ ^^ falling vvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvv vvvvvvvvvvvvvvvvvvvv vv was lo 00000000000000000000000000000000000000 00000000000000000000 0000 total fails 0, total passes 10 step 1 100000000000000000000000000000000001111100011011011010100110111001 step 2 100000000000000000000000000000000001111100100011011010100110111001 step 3 100000000000000000000000000000000001111100000011011010100110111001 step 4 100000000000000000000000000000000001111100000100011010100110111001 step 5 100000000000000000000000000000000001111100000000011010100110111001 step 6 100000000000000000000000000000000001111100000000100010100110111001 step 7 100000000000000000000000000000000001111100000000000010100110111001 step 8 100000000000000000000000000000000001111100000000000101010110111001 step 9 100000000000000000000000000000000001111100000000000001010110111001 step 10 100000000000000000000000000000000001111100000000000001011000111001 step 11 100000000000000000000000000000000001111100000000000001010000111001 step 12 100000000000000000000000000000000001111100000000000001010001100001 step 13 100000000000000000000000000000000001111100000000000001010000100001 step 14 100000000000000000000000000000000001111100000000000001010000100001 step 15 100000000000010000000000000000000000111101000000000001010000100001 step 16 100000000000010010000000000000000000110111000000000001010000100001 step 17 100000000000010010000000000000000000110111111000000001010000100001 step 18 100000000000010010000000000000000000110111011000000001010000100001 step 19 100000000000010010000000000000000000110111011111000001010000100001 step 20 100000000000010010000000000000000000110111011011000001010000100001 step 21 100000000000010010000000000000000000110111011011111001010000100001 step 22 100000000000010010000000000000000000110111011011011001010000100001 step 23 100000000000010010000000000000000000110111011011011110100000100001 step 24 100000000000010010000000000000000000110111011011011010100000100001 step 25 100000000000010010000000000000000000110111011011011010101110100001 step 26 100000000000010010000000000000000000110111011011011010100110100001 step 27 100000000000010010000000000000000000110111011011011010100111111001 step 28 100000000000010010000000000000000000110111011011011010100110111001 step 29 100000000000000010000000000000000001110110011011011010100110111001 step 30 100000000000000000000000000000000001111100011011011010100110111001 step 31 100000000000000000000000000000000001111100011011011010100110111001 step 32 100001000000000000000000000000000001111100011011011010100110111001 step 33 100001100000000000000000000000000001111100011011011010100110111001 step 34 100001100100000000000000000000000001111100011011011010100110111001 step 35 100001100110000000000000000000000001111100011011011010100110111001 step 36 100001100110100000000000000000000001111100011011011010100110111001 step 37 100001100110100100000000000000000001111100011011011010100110111001 step 38 100001100110100100010000000000000001111100011011011010100110111001 step 39 100001100110100100011000000000000001111100011011011010100110111001 step 40 100001100110100100011010000000000001111100011011011010100110111001 step 41 100001100110100100011011000000000001111100011011011010100110111001 step 42 100001100110100100011011010000000001111100011011011010100110111001 step 43 100001100110100100011011011000000001111100011011011010100110111001 step 44 100001100110100100011011011010000001111100011011011010100110111001 step 45 100001100110100100011011011011000001111100011011011010100110111001 step 46 100001100110100100011011011011010001111100011011011010100110111001 step 47 100001100110100100011011011011011001111100011011011010100110111001 step 48 100001100110100100011011011011011101111100011011011010100110111001 step 49 110001100110100100011011011011011100110111011011011010100110111001 step 50 100001100110100100011011011011011101111100011011011010100110111001 step 51 101001100110100100011011011011011100110111011011011010100110111001 step 52 100001100110100100011011011011011101111100011011011010100110111001 step 53 100101100110100100011011011011011100110111011011011010100110111001 step 54 100001100110100100011011011011011101111100011011011010100110111001 step 55 100011100110100100011011011011011100110111011011011010100110111001 step 56 100001100110100100011011011011011101111100011011011010100110111001 step 57 100001110110100100011011011011011100110111011011011010100110111001 step 58 100001100110100100011011011011011101111100011011011010100110111001 step 59 100001101110100100011011011011011100110111011011011010100110111001 step 60 100001100110100100011011011011011101111100011011011010100110111001 step 61 100001100111100100011011011011011100111101011011011010100110111001 step 62 100001100110100100011011011011011101111100011011011010100110111001 step 63 100001100110110100011011011011011100111101011011011010100110111001 step 64 100001100110100100011011011011011101111100011011011010100110111001 step 65 100001100110101100011011011011011101110110011011011010100110111001 step 66 100001100110100100011011011011011101111100011011011010100110111001 step 67 100001100110100110011011011011011101110110011011011010100110111001 step 68 100001100110100100011011011011011101111100011011011010100110111001 step 69 100001100110100101011011011011011101001111011011011010100110111001 step 70 100001100110100100011011011011011101111100011011011010100110111001 step 71 100001100110100100111011011011011101001111011011011010100110111001 step 72 100001100110100100011011011011011101111100011011011010100110111001 step 73 100001100110100100011111011011011101001111011011011010100110111001 step 74 100001100110100100011011011011011101111100011011011010100110111001 step 75 100001100110100100011011111011011101001111011011011010100110111001 step 76 100001100110100100011011011011011101111100011011011010100110111001 step 77 100001100110100100011011011111011101001111011011011010100110111001 step 78 100001100110100100011011011011011101111100011011011010100110111001 step 79 100001100110100100011011011011111101001111011011011010100110111001 step 80 100001100110100100011011011011011101111100011011011010100110111001 step 81 100001100110100100011011011011011111101110011011011010100110111001 step 82 100001100110100100011011011011011101111100011011011010100110111001 test 11: pass SLOT BAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBAABBAAAAAAAAAAAAAABBBBBBBBAB LETTER ALPSLFMDEEMCBFRSPKLEMFHRSCJLJKUHPNMBBNNVVRKRHUTDJUKANJHBTPDFSVDEVU SIDE 121212122121212121111111112212122222112222111221112112212112212212 DIRECTION IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIOOOOOOOIOOIOOIOOIOOOOIOOIIOOIIO this fail all fails was hi 111111111111111111111111111111111111111111111111111111111111111 1 rising ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ ^^^^^^^^^^^^^^^^^^^^ ^^ falling vvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvv vvvvvvvvvvvvvvvvvvvv vv was lo 00000000000000000000000000000000000000 00000000000000000000 0000 total fails 0, total passes 11 step 1 100000000000000000000000000000000001111100011011011010100110111001 step 2 100000000000000000000000000000000001111100100011011010100110111001 step 3 100000000000000000000000000000000001111100000011011010100110111001 step 4 100000000000000000000000000000000001111100000100011010100110111001 step 5 100000000000000000000000000000000001111100000000011010100110111001 step 6 100000000000000000000000000000000001111100000000100010100110111001 step 7 100000000000000000000000000000000001111100000000000010100110111001 step 8 100000000000000000000000000000000001111100000000000101010110111001 step 9 100000000000000000000000000000000001111100000000000001010110111001 step 10 100000000000000000000000000000000001111100000000000001011000111001 step 11 100000000000000000000000000000000001111100000000000001010000111001 step 12 100000000000000000000000000000000001111100000000000001010001100001 step 13 100000000000000000000000000000000001111100000000000001010000100001 step 14 100000000000000000000000000000000001111100000000000001010000100001 step 15 100000000000010000000000000000000000111101000000000001010000100001 step 16 100000000000010010000000000000000000110111000000000001010000100001 step 17 100000000000010010000000000000000000110111111000000001010000100001 step 18 100000000000010010000000000000000000110111011000000001010000100001 step 19 100000000000010010000000000000000000110111011111000001010000100001 step 20 100000000000010010000000000000000000110111011011000001010000100001 step 21 100000000000010010000000000000000000110111011011111001010000100001 step 22 100000000000010010000000000000000000110111011011011001010000100001 step 23 100000000000010010000000000000000000110111011011011110100000100001 step 24 100000000000010010000000000000000000110111011011011010100000100001 step 25 100000000000010010000000000000000000110111011011011010101110100001 step 26 100000000000010010000000000000000000110111011011011010100110100001 step 27 100000000000010010000000000000000000110111011011011010100111111001 step 28 100000000000010010000000000000000000110111011011011010100110111001 step 29 100000000000000010000000000000000001110110011011011010100110111001 step 30 100000000000000000000000000000000001111100011011011010100110111001 step 31 100000000000000000000000000000000001111100011011011010100110111001 step 32 100001000000000000000000000000000001111100011011011010100110111001 step 33 100001100000000000000000000000000001111100011011011010100110111001 step 34 100001100100000000000000000000000001111100011011011010100110111001 step 35 100001100110000000000000000000000001111100011011011010100110111001 step 36 100001100110100000000000000000000001111100011011011010100110111001 step 37 100001100110100100000000000000000001111100011011011010100110111001 step 38 100001100110100100010000000000000001111100011011011010100110111001 step 39 100001100110100100011000000000000001111100011011011010100110111001 step 40 100001100110100100011010000000000001111100011011011010100110111001 step 41 100001100110100100011011000000000001111100011011011010100110111001 step 42 100001100110100100011011010000000001111100011011011010100110111001 step 43 100001100110100100011011011000000001111100011011011010100110111001 step 44 100001100110100100011011011010000001111100011011011010100110111001 step 45 100001100110100100011011011011000001111100011011011010100110111001 step 46 100001100110100100011011011011010001111100011011011010100110111001 step 47 100001100110100100011011011011011001111100011011011010100110111001 step 48 100001100110100100011011011011011101111100011011011010100110111001 step 49 110001100110100100011011011011011100110111011011011010100110111001 step 50 100001100110100100011011011011011101111100011011011010100110111001 step 51 101001100110100100011011011011011100110111011011011010100110111001 step 52 100001100110100100011011011011011101111100011011011010100110111001 step 53 100101100110100100011011011011011100110111011011011010100110111001 step 54 100001100110100100011011011011011101111100011011011010100110111001 step 55 100011100110100100011011011011011100110111011011011010100110111001 step 56 100001100110100100011011011011011101111100011011011010100110111001 step 57 100001110110100100011011011011011100110111011011011010100110111001 step 58 100001100110100100011011011011011101111100011011011010100110111001 step 59 100001101110100100011011011011011100110111011011011010100110111001 step 60 100001100110100100011011011011011101111100011011011010100110111001 step 61 100001100111100100011011011011011100111101011011011010100110111001 step 62 100001100110100100011011011011011101111100011011011010100110111001 step 63 100001100110110100011011011011011100111101011011011010100110111001 step 64 100001100110100100011011011011011101111100011011011010100110111001 step 65 100001100110101100011011011011011101110110011011011010100110111001 step 66 100001100110100100011011011011011101111100011011011010100110111001 step 67 100001100110100110011011011011011101110110011011011010100110111001 step 68 100001100110100100011011011011011101111100011011011010100110111001 step 69 100001100110100101011011011011011101001111011011011010100110111001 step 70 100001100110100100011011011011011101111100011011011010100110111001 step 71 100001100110100100111011011011011101001111011011011010100110111001 step 72 100001100110100100011011011011011101111100011011011010100110111001 step 73 100001100110100100011111011011011101001111011011011010100110111001 step 74 100001100110100100011011011011011101111100011011011010100110111001 step 75 100001100110100100011011111011011101001111011011011010100110111001 step 76 100001100110100100011011011011011101111100011011011010100110111001 step 77 100001100110100100011011011111011101001111011011011010100110111001 step 78 100001100110100100011011011011011101111100011011011010100110111001 step 79 100001100110100100011011011011111101001111011011011010100110111001 step 80 100001100110100100011011011011011101111100011011011010100110111001 step 81 100001100110100100011011011011011111101110011011011010100110111001 step 82 100001100110100100011011011011011101111100011011011010100110111001 test 12: pass SLOT BAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBAABBAAAAAAAAAAAAAABBBBBBBBAB LETTER ALPSLFMDEEMCBFRSPKLEMFHRSCJLJKUHPNMBBNNVVRKRHUTDJUKANJHBTPDFSVDEVU SIDE 121212122121212121111111112212122222112222111221112112212112212212 DIRECTION IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIOOOOOOOIOOIOOIOOIOOOOIOOIIOOIIO this fail all fails was hi 111111111111111111111111111111111111111111111111111111111111111 1 rising ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ ^^^^^^^^^^^^^^^^^^^^ ^^ falling vvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvv vvvvvvvvvvvvvvvvvvvv vv was lo 00000000000000000000000000000000000000 00000000000000000000 0000 total fails 0, total passes 12 step 1 100000000000000000000000000000000001111100011011011010100110111001 step 2 100000000000000000000000000000000001111100100011011010100110111001 step 3 100000000000000000000000000000000001111100000011011010100110111001 step 4 100000000000000000000000000000000001111100000100011010100110111001 step 5 100000000000000000000000000000000001111100000000011010100110111001 step 6 100000000000000000000000000000000001111100000000100010100110111001 step 7 100000000000000000000000000000000001111100000000000010100110111001 step 8 100000000000000000000000000000000001111100000000000101010110111001 step 9 100000000000000000000000000000000001111100000000000001010110111001 step 10 100000000000000000000000000000000001111100000000000001011000111001 step 11 100000000000000000000000000000000001111100000000000001010000111001 step 12 100000000000000000000000000000000001111100000000000001010001100001 step 13 100000000000000000000000000000000001111100000000000001010000100001 step 14 100000000000000000000000000000000001111100000000000001010000100001 step 15 100000000000010000000000000000000000111101000000000001010000100001 step 16 100000000000010010000000000000000000110111000000000001010000100001 step 17 100000000000010010000000000000000000110111111000000001010000100001 step 18 100000000000010010000000000000000000110111011000000001010000100001 step 19 100000000000010010000000000000000000110111011111000001010000100001 step 20 100000000000010010000000000000000000110111011011000001010000100001 step 21 100000000000010010000000000000000000110111011011111001010000100001 step 22 100000000000010010000000000000000000110111011011011001010000100001 step 23 100000000000010010000000000000000000110111011011011110100000100001 step 24 100000000000010010000000000000000000110111011011011010100000100001 step 25 100000000000010010000000000000000000110111011011011010101110100001 step 26 100000000000010010000000000000000000110111011011011010100110100001 step 27 100000000000010010000000000000000000110111011011011010100111111001 step 28 100000000000010010000000000000000000110111011011011010100110111001 step 29 100000000000000010000000000000000001110110011011011010100110111001 step 30 100000000000000000000000000000000001111100011011011010100110111001 step 31 100000000000000000000000000000000001111100011011011010100110111001 step 32 100001000000000000000000000000000001111100011011011010100110111001 step 33 100001100000000000000000000000000001111100011011011010100110111001 step 34 100001100100000000000000000000000001111100011011011010100110111001 step 35 100001100110000000000000000000000001111100011011011010100110111001 step 36 100001100110100000000000000000000001111100011011011010100110111001 step 37 100001100110100100000000000000000001111100011011011010100110111001 step 38 100001100110100100010000000000000001111100011011011010100110111001 step 39 100001100110100100011000000000000001111100011011011010100110111001 step 40 100001100110100100011010000000000001111100011011011010100110111001 step 41 100001100110100100011011000000000001111100011011011010100110111001 step 42 100001100110100100011011010000000001111100011011011010100110111001 step 43 100001100110100100011011011000000001111100011011011010100110111001 step 44 100001100110100100011011011010000001111100011011011010100110111001 step 45 100001100110100100011011011011000001111100011011011010100110111001 step 46 100001100110100100011011011011010001111100011011011010100110111001 step 47 100001100110100100011011011011011001111100011011011010100110111001 step 48 100001100110100100011011011011011101111100011011011010100110111001 step 49 110001100110100100011011011011011100110111011011011010100110111001 step 50 100001100110100100011011011011011101111100011011011010100110111001 step 51 101001100110100100011011011011011100110111011011011010100110111001 step 52 100001100110100100011011011011011101111100011011011010100110111001 step 53 100101100110100100011011011011011100110111011011011010100110111001 step 54 100001100110100100011011011011011101111100011011011010100110111001 step 55 100011100110100100011011011011011100110111011011011010100110111001 step 56 100001100110100100011011011011011101111100011011011010100110111001 step 57 100001110110100100011011011011011100110111011011011010100110111001 step 58 100001100110100100011011011011011101111100011011011010100110111001 step 59 100001101110100100011011011011011100110111011011011010100110111001 step 60 100001100110100100011011011011011101111100011011011010100110111001 step 61 100001100111100100011011011011011100111101011011011010100110111001 step 62 100001100110100100011011011011011101111100011011011010100110111001 step 63 100001100110110100011011011011011100111101011011011010100110111001 step 64 100001100110100100011011011011011101111100011011011010100110111001 step 65 100001100110101100011011011011011101110110011011011010100110111001 step 66 100001100110100100011011011011011101111100011011011010100110111001 step 67 100001100110100110011011011011011101110110011011011010100110111001 step 68 100001100110100100011011011011011101111100011011011010100110111001 step 69 100001100110100101011011011011011101001111011011011010100110111001 step 70 100001100110100100011011011011011101111100011011011010100110111001 step 71 100001100110100100111011011011011101001111011011011010100110111001 step 72 100001100110100100011011011011011101111100011011011010100110111001 step 73 100001100110100100011111011011011101001111011011011010100110111001 step 74 100001100110100100011011011011011101111100011011011010100110111001 step 75 100001100110100100011011111011011101001111011011011010100110111001 step 76 100001100110100100011011011011011101111100011011011010100110111001 step 77 100001100110100100011011011111011101001111011011011010100110111001 step 78 100001100110100100011011011011011101111100011011011010100110111001 step 79 100001100110100100011011011011111101001111011011011010100110111001 step 80 100001100110100100011011011011011101111100011011011010100110111001 step 81 100001100110100100011011011011011111101110011011011010100110111001 step 82 100001100110100100011011011011011101111100011011011010100110111001 test 13: pass SLOT BAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBAABBAAAAAAAAAAAAAABBBBBBBBAB LETTER ALPSLFMDEEMCBFRSPKLEMFHRSCJLJKUHPNMBBNNVVRKRHUTDJUKANJHBTPDFSVDEVU SIDE 121212122121212121111111112212122222112222111221112112212112212212 DIRECTION IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIOOOOOOOIOOIOOIOOIOOOOIOOIIOOIIO this fail all fails was hi 111111111111111111111111111111111111111111111111111111111111111 1 rising ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ ^^^^^^^^^^^^^^^^^^^^ ^^ falling vvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvv vvvvvvvvvvvvvvvvvvvv vv was lo 00000000000000000000000000000000000000 00000000000000000000 0000 total fails 0, total passes 13 step 1 100000000000000000000000000000000001111100011011011010100110111001 step 2 100000000000000000000000000000000001111100100011011010100110111001 step 3 100000000000000000000000000000000001111100000011011010100110111001 step 4 100000000000000000000000000000000001111100000100011010100110111001 step 5 100000000000000000000000000000000001111100000000011010100110111001 step 6 100000000000000000000000000000000001111100000000100010100110111001 step 7 100000000000000000000000000000000001111100000000000010100110111001 step 8 100000000000000000000000000000000001111100000000000101010110111001 step 9 100000000000000000000000000000000001111100000000000001010110111001 step 10 100000000000000000000000000000000001111100000000000001011000111001 step 11 100000000000000000000000000000000001111100000000000001010000111001 step 12 100000000000000000000000000000000001111100000000000001010001100001 step 13 100000000000000000000000000000000001111100000000000001010000100001 step 14 100000000000000000000000000000000001111100000000000001010000100001 step 15 100000000000010000000000000000000000111101000000000001010000100001 step 16 100000000000010010000000000000000000110111000000000001010000100001 step 17 100000000000010010000000000000000000110111111000000001010000100001 step 18 100000000000010010000000000000000000110111011000000001010000100001 step 19 100000000000010010000000000000000000110111011111000001010000100001 step 20 100000000000010010000000000000000000110111011011000001010000100001 step 21 100000000000010010000000000000000000110111011011111001010000100001 step 22 100000000000010010000000000000000000110111011011011001010000100001 step 23 100000000000010010000000000000000000110111011011011110100000100001 step 24 100000000000010010000000000000000000110111011011011010100000100001 step 25 100000000000010010000000000000000000110111011011011010101110100001 step 26 100000000000010010000000000000000000110111011011011010100110100001 step 27 100000000000010010000000000000000000110111011011011010100111111001 step 28 100000000000010010000000000000000000110111011011011010100110111001 step 29 100000000000000010000000000000000001110110011011011010100110111001 step 30 100000000000000000000000000000000001111100011011011010100110111001 step 31 100000000000000000000000000000000001111100011011011010100110111001 step 32 100001000000000000000000000000000001111100011011011010100110111001 step 33 100001100000000000000000000000000001111100011011011010100110111001 step 34 100001100100000000000000000000000001111100011011011010100110111001 step 35 100001100110000000000000000000000001111100011011011010100110111001 step 36 100001100110100000000000000000000001111100011011011010100110111001 step 37 100001100110100100000000000000000001111100011011011010100110111001 step 38 100001100110100100010000000000000001111100011011011010100110111001 step 39 100001100110100100011000000000000001111100011011011010100110111001 step 40 100001100110100100011010000000000001111100011011011010100110111001 step 41 100001100110100100011011000000000001111100011011011010100110111001 step 42 100001100110100100011011010000000001111100011011011010100110111001 step 43 100001100110100100011011011000000001111100011011011010100110111001 step 44 100001100110100100011011011010000001111100011011011010100110111001 step 45 100001100110100100011011011011000001111100011011011010100110111001 step 46 100001100110100100011011011011010001111100011011011010100110111001 step 47 100001100110100100011011011011011001111100011011011010100110111001 step 48 100001100110100100011011011011011101111100011011011010100110111001 step 49 110001100110100100011011011011011100110111011011011010100110111001 step 50 100001100110100100011011011011011101111100011011011010100110111001 step 51 101001100110100100011011011011011100110111011011011010100110111001 step 52 100001100110100100011011011011011101111100011011011010100110111001 step 53 100101100110100100011011011011011100110111011011011010100110111001 step 54 100001100110100100011011011011011101111100011011011010100110111001 step 55 100011100110100100011011011011011100110111011011011010100110111001 step 56 100001100110100100011011011011011101111100011011011010100110111001 step 57 100001110110100100011011011011011100110111011011011010100110111001 step 58 100001100110100100011011011011011101111100011011011010100110111001 step 59 100001101110100100011011011011011100110111011011011010100110111001 step 60 100001100110100100011011011011011101111100011011011010100110111001 step 61 100001100111100100011011011011011100111101011011011010100110111001 step 62 100001100110100100011011011011011101111100011011011010100110111001 step 63 100001100110110100011011011011011100111101011011011010100110111001 step 64 100001100110100100011011011011011101111100011011011010100110111001 step 65 100001100110101100011011011011011101110110011011011010100110111001 step 66 100001100110100100011011011011011101111100011011011010100110111001 step 67 100001100110100110011011011011011101110110011011011010100110111001 step 68 100001100110100100011011011011011101111100011011011010100110111001 step 69 100001100110100101011011011011011101001111011011011010100110111001 step 70 100001100110100100011011011011011101111100011011011010100110111001 step 71 100001100110100100111011011011011101001111011011011010100110111001 step 72 100001100110100100011011011011011101111100011011011010100110111001 step 73 100001100110100100011111011011011101001111011011011010100110111001 step 74 100001100110100100011011011011011101111100011011011010100110111001 step 75 100001100110100100011011111011011101001111011011011010100110111001 step 76 100001100110100100011011011011011101111100011011011010100110111001 step 77 100001100110100100011011011111011101001111011011011010100110111001 step 78 100001100110100100011011011011011101111100011011011010100110111001 step 79 100001100110100100011011011011111101001111011011011010100110111001 step 80 100001100110100100011011011011011101111100011011011010100110111001 step 81 100001100110100100011011011011011111101110011011011010100110111001 step 82 100001100110100100011011011011011101111100011011011010100110111001 test 14: pass SLOT BAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBAABBAAAAAAAAAAAAAABBBBBBBBAB LETTER ALPSLFMDEEMCBFRSPKLEMFHRSCJLJKUHPNMBBNNVVRKRHUTDJUKANJHBTPDFSVDEVU SIDE 121212122121212121111111112212122222112222111221112112212112212212 DIRECTION IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIOOOOOOOIOOIOOIOOIOOOOIOOIIOOIIO this fail all fails was hi 111111111111111111111111111111111111111111111111111111111111111 1 rising ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ ^^^^^^^^^^^^^^^^^^^^ ^^ falling vvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvv vvvvvvvvvvvvvvvvvvvv vv was lo 00000000000000000000000000000000000000 00000000000000000000 0000 total fails 0, total passes 14 step 1 100000000000000000000000000000000001111100011011011010100110111001 step 2 100000000000000000000000000000000001111100100011011010100110111001 step 3 100000000000000000000000000000000001111100000011011010100110111001 step 4 100000000000000000000000000000000001111100000100011010100110111001 step 5 100000000000000000000000000000000001111100000000011010100110111001 step 6 100000000000000000000000000000000001111100000000100010100110111001 step 7 100000000000000000000000000000000001111100000000000010100110111001 step 8 100000000000000000000000000000000001111100000000000101010110111001 step 9 100000000000000000000000000000000001111100000000000001010110111001 step 10 100000000000000000000000000000000001111100000000000001011000111001 step 11 100000000000000000000000000000000001111100000000000001010000111001 step 12 100000000000000000000000000000000001111100000000000001010001100001 step 13 100000000000000000000000000000000001111100000000000001010000100001 step 14 100000000000000000000000000000000001111100000000000001010000100001 step 15 100000000000010000000000000000000000111101000000000001010000100001 step 16 100000000000010010000000000000000000110111000000000001010000100001 step 17 100000000000010010000000000000000000110111111000000001010000100001 step 18 100000000000010010000000000000000000110111011000000001010000100001 step 19 100000000000010010000000000000000000110111011111000001010000100001 step 20 100000000000010010000000000000000000110111011011000001010000100001 step 21 100000000000010010000000000000000000110111011011111001010000100001 step 22 100000000000010010000000000000000000110111011011011001010000100001 step 23 100000000000010010000000000000000000110111011011011110100000100001 step 24 100000000000010010000000000000000000110111011011011010100000100001 step 25 100000000000010010000000000000000000110111011011011010101110100001 step 26 100000000000010010000000000000000000110111011011011010100110100001 step 27 100000000000010010000000000000000000110111011011011010100111111001 step 28 100000000000010010000000000000000000110111011011011010100110111001 step 29 100000000000000010000000000000000001110110011011011010100110111001 step 30 100000000000000000000000000000000001111100011011011010100110111001 step 31 100000000000000000000000000000000001111100011011011010100110111001 step 32 100001000000000000000000000000000001111100011011011010100110111001 step 33 100001100000000000000000000000000001111100011011011010100110111001 step 34 100001100100000000000000000000000001111100011011011010100110111001 step 35 100001100110000000000000000000000001111100011011011010100110111001 step 36 100001100110100000000000000000000001111100011011011010100110111001 step 37 100001100110100100000000000000000001111100011011011010100110111001 step 38 100001100110100100010000000000000001111100011011011010100110111001 step 39 100001100110100100011000000000000001111100011011011010100110111001 step 40 100001100110100100011010000000000001111100011011011010100110111001 step 41 100001100110100100011011000000000001111100011011011010100110111001 step 42 100001100110100100011011010000000001111100011011011010100110111001 step 43 100001100110100100011011011000000001111100011011011010100110111001 step 44 100001100110100100011011011010000001111100011011011010100110111001 step 45 100001100110100100011011011011000001111100011011011010100110111001 step 46 100001100110100100011011011011010001111100011011011010100110111001 step 47 100001100110100100011011011011011001111100011011011010100110111001 step 48 100001100110100100011011011011011101111100011011011010100110111001 step 49 110001100110100100011011011011011100110111011011011010100110111001 step 50 100001100110100100011011011011011101111100011011011010100110111001 step 51 101001100110100100011011011011011100110111011011011010100110111001 step 52 100001100110100100011011011011011101111100011011011010100110111001 step 53 100101100110100100011011011011011100110111011011011010100110111001 step 54 100001100110100100011011011011011101111100011011011010100110111001 step 55 100011100110100100011011011011011100110111011011011010100110111001 step 56 100001100110100100011011011011011101111100011011011010100110111001 step 57 100001110110100100011011011011011100110111011011011010100110111001 step 58 100001100110100100011011011011011101111100011011011010100110111001 step 59 100001101110100100011011011011011100110111011011011010100110111001 step 60 100001100110100100011011011011011101111100011011011010100110111001 step 61 100001100111100100011011011011011100111101011011011010100110111001 step 62 100001100110100100011011011011011101111100011011011010100110111001 step 63 100001100110110100011011011011011100111101011011011010100110111001 step 64 100001100110100100011011011011011101111100011011011010100110111001 step 65 100001100110101100011011011011011101110110011011011010100110111001 step 66 100001100110100100011011011011011101111100011011011010100110111001 step 67 100001100110100110011011011011011101110110011011011010100110111001 step 68 100001100110100100011011011011011101111100011011011010100110111001 step 69 100001100110100101011011011011011101001111011011011010100110111001 step 70 100001100110100100011011011011011101111100011011011010100110111001 step 71 100001100110100100111011011011011101001111011011011010100110111001 step 72 100001100110100100011011011011011101111100011011011010100110111001 step 73 100001100110100100011111011011011101001111011011011010100110111001 step 74 100001100110100100011011011011011101111100011011011010100110111001 step 75 100001100110100100011011111011011101001111011011011010100110111001 step 76 100001100110100100011011011011011101111100011011011010100110111001 step 77 100001100110100100011011011111011101001111011011011010100110111001 step 78 100001100110100100011011011011011101111100011011011010100110111001 step 79 100001100110100100011011011011111101001111011011011010100110111001 step 80 100001100110100100011011011011011101111100011011011010100110111001 step 81 100001100110100100011011011011011111101110011011011010100110111001 step 82 100001100110100100011011011011011101111100011011011010100110111001 test 15: pass SLOT BAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBAABBAAAAAAAAAAAAAABBBBBBBBAB LETTER ALPSLFMDEEMCBFRSPKLEMFHRSCJLJKUHPNMBBNNVVRKRHUTDJUKANJHBTPDFSVDEVU SIDE 121212122121212121111111112212122222112222111221112112212112212212 DIRECTION IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIOOOOOOOIOOIOOIOOIOOOOIOOIIOOIIO this fail all fails was hi 111111111111111111111111111111111111111111111111111111111111111 1 rising ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ ^^^^^^^^^^^^^^^^^^^^ ^^ falling vvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvv vvvvvvvvvvvvvvvvvvvv vv was lo 00000000000000000000000000000000000000 00000000000000000000 0000 total fails 0, total passes 15 step 1 100000000000000000000000000000000001111100011011011010100110111001 step 2 100000000000000000000000000000000001111100100011011010100110111001 step 3 100000000000000000000000000000000001111100000011011010100110111001 step 4 100000000000000000000000000000000001111100000100011010100110111001 step 5 100000000000000000000000000000000001111100000000011010100110111001 step 6 100000000000000000000000000000000001111100000000100010100110111001 step 7 100000000000000000000000000000000001111100000000000010100110111001 step 8 100000000000000000000000000000000001111100000000000101010110111001 step 9 100000000000000000000000000000000001111100000000000001010110111001 step 10 100000000000000000000000000000000001111100000000000001011000111001 step 11 100000000000000000000000000000000001111100000000000001010000111001 step 12 100000000000000000000000000000000001111100000000000001010001100001 step 13 100000000000000000000000000000000001111100000000000001010000100001 step 14 100000000000000000000000000000000001111100000000000001010000100001 step 15 100000000000010000000000000000000000111101000000000001010000100001 step 16 100000000000010010000000000000000000110111000000000001010000100001 step 17 100000000000010010000000000000000000110111111000000001010000100001 step 18 100000000000010010000000000000000000110111011000000001010000100001 step 19 100000000000010010000000000000000000110111011111000001010000100001 step 20 100000000000010010000000000000000000110111011011000001010000100001 step 21 100000000000010010000000000000000000110111011011111001010000100001 step 22 100000000000010010000000000000000000110111011011011001010000100001 step 23 100000000000010010000000000000000000110111011011011110100000100001 step 24 100000000000010010000000000000000000110111011011011010100000100001 step 25 100000000000010010000000000000000000110111011011011010101110100001 step 26 100000000000010010000000000000000000110111011011011010100110100001 step 27 100000000000010010000000000000000000110111011011011010100111111001 step 28 100000000000010010000000000000000000110111011011011010100110111001 step 29 100000000000000010000000000000000001110110011011011010100110111001 step 30 100000000000000000000000000000000001111100011011011010100110111001 step 31 100000000000000000000000000000000001111100011011011010100110111001 step 32 100001000000000000000000000000000001111100011011011010100110111001 step 33 100001100000000000000000000000000001111100011011011010100110111001 step 34 100001100100000000000000000000000001111100011011011010100110111001 step 35 100001100110000000000000000000000001111100011011011010100110111001 step 36 100001100110100000000000000000000001111100011011011010100110111001 step 37 100001100110100100000000000000000001111100011011011010100110111001 step 38 100001100110100100010000000000000001111100011011011010100110111001 step 39 100001100110100100011000000000000001111100011011011010100110111001 step 40 100001100110100100011010000000000001111100011011011010100110111001 step 41 100001100110100100011011000000000001111100011011011010100110111001 step 42 100001100110100100011011010000000001111100011011011010100110111001 step 43 100001100110100100011011011000000001111100011011011010100110111001 step 44 100001100110100100011011011010000001111100011011011010100110111001 step 45 100001100110100100011011011011000001111100011011011010100110111001 step 46 100001100110100100011011011011010001111100011011011010100110111001 step 47 100001100110100100011011011011011001111100011011011010100110111001 step 48 100001100110100100011011011011011101111100011011011010100110111001 step 49 110001100110100100011011011011011100110111011011011010100110111001 step 50 100001100110100100011011011011011101111100011011011010100110111001 step 51 101001100110100100011011011011011100110111011011011010100110111001 step 52 100001100110100100011011011011011101111100011011011010100110111001 step 53 100101100110100100011011011011011100110111011011011010100110111001 step 54 100001100110100100011011011011011101111100011011011010100110111001 step 55 100011100110100100011011011011011100110111011011011010100110111001 step 56 100001100110100100011011011011011101111100011011011010100110111001 step 57 100001110110100100011011011011011100110111011011011010100110111001 step 58 100001100110100100011011011011011101111100011011011010100110111001 step 59 100001101110100100011011011011011100110111011011011010100110111001 step 60 100001100110100100011011011011011101111100011011011010100110111001 step 61 100001100111100100011011011011011100111101011011011010100110111001 step 62 100001100110100100011011011011011101111100011011011010100110111001 step 63 100001100110110100011011011011011100111101011011011010100110111001 step 64 100001100110100100011011011011011101111100011011011010100110111001 step 65 100001100110101100011011011011011101110110011011011010100110111001 step 66 100001100110100100011011011011011101111100011011011010100110111001 step 67 100001100110100110011011011011011101110110011011011010100110111001 step 68 100001100110100100011011011011011101111100011011011010100110111001 step 69 100001100110100101011011011011011101001111011011011010100110111001 step 70 100001100110100100011011011011011101111100011011011010100110111001 step 71 100001100110100100111011011011011101001111011011011010100110111001 step 72 100001100110100100011011011011011101111100011011011010100110111001 step 73 100001100110100100011111011011011101001111011011011010100110111001 step 74 100001100110100100011011011011011101111100011011011010100110111001 step 75 100001100110100100011011111011011101001111011011011010100110111001 step 76 100001100110100100011011011011011101111100011011011010100110111001 step 77 100001100110100100011011011111011101001111011011011010100110111001 step 78 100001100110100100011011011011011101111100011011011010100110111001 step 79 100001100110100100011011011011111101001111011011011010100110111001 step 80 100001100110100100011011011011011101111100011011011010100110111001 step 81 100001100110100100011011011011011111101110011011011010100110111001 step 82 100001100110100100011011011011011101111100011011011010100110111001 test 16: pass SLOT BAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBAABBAAAAAAAAAAAAAABBBBBBBBAB LETTER ALPSLFMDEEMCBFRSPKLEMFHRSCJLJKUHPNMBBNNVVRKRHUTDJUKANJHBTPDFSVDEVU SIDE 121212122121212121111111112212122222112222111221112112212112212212 DIRECTION IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIOOOOOOOIOOIOOIOOIOOOOIOOIIOOIIO this fail all fails was hi 111111111111111111111111111111111111111111111111111111111111111 1 rising ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ ^^^^^^^^^^^^^^^^^^^^ ^^ falling vvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvv vvvvvvvvvvvvvvvvvvvv vv was lo 00000000000000000000000000000000000000 00000000000000000000 0000 total fails 0, total passes 16 step 1 100000000000000000000000000000000001111100011011011010100110111001 step 2 100000000000000000000000000000000001111100100011011010100110111001 step 3 100000000000000000000000000000000001111100000011011010100110111001 step 4 100000000000000000000000000000000001111100000100011010100110111001 step 5 100000000000000000000000000000000001111100000000011010100110111001 step 6 100000000000000000000000000000000001111100000000100010100110111001 step 7 100000000000000000000000000000000001111100000000000010100110111001 step 8 100000000000000000000000000000000001111100000000000101010110111001 step 9 100000000000000000000000000000000001111100000000000001010110111001 step 10 100000000000000000000000000000000001111100000000000001011000111001 step 11 100000000000000000000000000000000001111100000000000001010000111001 step 12 100000000000000000000000000000000001111100000000000001010001100001 step 13 100000000000000000000000000000000001111100000000000001010000100001 step 14 100000000000000000000000000000000001111100000000000001010000100001 step 15 100000000000010000000000000000000000111101000000000001010000100001 step 16 100000000000010010000000000000000000110111000000000001010000100001 step 17 100000000000010010000000000000000000110111111000000001010000100001 step 18 100000000000010010000000000000000000110111011000000001010000100001 step 19 100000000000010010000000000000000000110111011111000001010000100001 step 20 100000000000010010000000000000000000110111011011000001010000100001 step 21 100000000000010010000000000000000000110111011011111001010000100001 step 22 100000000000010010000000000000000000110111011011011001010000100001 step 23 100000000000010010000000000000000000110111011011011110100000100001 step 24 100000000000010010000000000000000000110111011011011010100000100001 step 25 100000000000010010000000000000000000110111011011011010101110100001 step 26 100000000000010010000000000000000000110111011011011010100110100001 step 27 100000000000010010000000000000000000110111011011011010100111111001 step 28 100000000000010010000000000000000000110111011011011010100110111001 step 29 100000000000000010000000000000000001110110011011011010100110111001 step 30 100000000000000000000000000000000001111100011011011010100110111001 step 31 100000000000000000000000000000000001111100011011011010100110111001 step 32 100001000000000000000000000000000001111100011011011010100110111001 step 33 100001100000000000000000000000000001111100011011011010100110111001 step 34 100001100100000000000000000000000001111100011011011010100110111001 step 35 100001100110000000000000000000000001111100011011011010100110111001 step 36 100001100110100000000000000000000001111100011011011010100110111001 step 37 100001100110100100000000000000000001111100011011011010100110111001 step 38 100001100110100100010000000000000001111100011011011010100110111001 step 39 100001100110100100011000000000000001111100011011011010100110111001 step 40 100001100110100100011010000000000001111100011011011010100110111001 step 41 100001100110100100011011000000000001111100011011011010100110111001 step 42 100001100110100100011011010000000001111100011011011010100110111001 step 43 100001100110100100011011011000000001111100011011011010100110111001 step 44 100001100110100100011011011010000001111100011011011010100110111001 step 45 100001100110100100011011011011000001111100011011011010100110111001 step 46 100001100110100100011011011011010001111100011011011010100110111001 step 47 100001100110100100011011011011011001111100011011011010100110111001 step 48 100001100110100100011011011011011101111100011011011010100110111001 step 49 110001100110100100011011011011011100110111011011011010100110111001 step 50 100001100110100100011011011011011101111100011011011010100110111001 step 51 101001100110100100011011011011011100110111011011011010100110111001 step 52 100001100110100100011011011011011101111100011011011010100110111001 step 53 100101100110100100011011011011011100110111011011011010100110111001 step 54 100001100110100100011011011011011101111100011011011010100110111001 step 55 100011100110100100011011011011011100110111011011011010100110111001 step 56 100001100110100100011011011011011101111100011011011010100110111001 step 57 100001110110100100011011011011011100110111011011011010100110111001 step 58 100001100110100100011011011011011101111100011011011010100110111001 step 59 100001101110100100011011011011011100110111011011011010100110111001 step 60 100001100110100100011011011011011101111100011011011010100110111001 step 61 100001100111100100011011011011011100111101011011011010100110111001 step 62 100001100110100100011011011011011101111100011011011010100110111001 step 63 100001100110110100011011011011011100111101011011011010100110111001 step 64 100001100110100100011011011011011101111100011011011010100110111001 step 65 100001100110101100011011011011011101110110011011011010100110111001 step 66 100001100110100100011011011011011101111100011011011010100110111001 step 67 100001100110100110011011011011011101110110011011011010100110111001 step 68 100001100110100100011011011011011101111100011011011010100110111001 step 69 100001100110100101011011011011011101001111011011011010100110111001 step 70 100001100110100100011011011011011101111100011011011010100110111001 step 71 100001100110100100111011011011011101001111011011011010100110111001 step 72 100001100110100100011011011011011101111100011011011010100110111001 step 73 100001100110100100011111011011011101001111011011011010100110111001 step 74 100001100110100100011011011011011101111100011011011010100110111001 step 75 100001100110100100011011111011011101001111011011011010100110111001 step 76 100001100110100100011011011011011101111100011011011010100110111001 step 77 100001100110100100011011011111011101001111011011011010100110111001 step 78 100001100110100100011011011011011101111100011011011010100110111001 step 79 100001100110100100011011011011111101001111011011011010100110111001 step 80 100001100110100100011011011011011101111100011011011010100110111001 step 81 100001100110100100011011011011011111101110011011011010100110111001 step 82 100001100110100100011011011011011101111100011011011010100110111001 test 17: pass SLOT BAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBAABBAAAAAAAAAAAAAABBBBBBBBAB LETTER ALPSLFMDEEMCBFRSPKLEMFHRSCJLJKUHPNMBBNNVVRKRHUTDJUKANJHBTPDFSVDEVU SIDE 121212122121212121111111112212122222112222111221112112212112212212 DIRECTION IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIOOOOOOOIOOIOOIOOIOOOOIOOIIOOIIO this fail all fails was hi 111111111111111111111111111111111111111111111111111111111111111 1 rising ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ ^^^^^^^^^^^^^^^^^^^^ ^^ falling vvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvv vvvvvvvvvvvvvvvvvvvv vv was lo 00000000000000000000000000000000000000 00000000000000000000 0000 total fails 0, total passes 17 step 1 100000000000000000000000000000000001111100011011011010100110111001 step 2 100000000000000000000000000000000001111100100011011010100110111001 step 3 100000000000000000000000000000000001111100000011011010100110111001 step 4 100000000000000000000000000000000001111100000100011010100110111001 step 5 100000000000000000000000000000000001111100000000011010100110111001 step 6 100000000000000000000000000000000001111100000000100010100110111001 step 7 100000000000000000000000000000000001111100000000000010100110111001 step 8 100000000000000000000000000000000001111100000000000101010110111001 step 9 100000000000000000000000000000000001111100000000000001010110111001 step 10 100000000000000000000000000000000001111100000000000001011000111001 step 11 100000000000000000000000000000000001111100000000000001010000111001 step 12 100000000000000000000000000000000001111100000000000001010001100001 step 13 100000000000000000000000000000000001111100000000000001010000100001 step 14 100000000000000000000000000000000001111100000000000001010000100001 step 15 100000000000010000000000000000000000111101000000000001010000100001 step 16 100000000000010010000000000000000000110111000000000001010000100001 step 17 100000000000010010000000000000000000110111111000000001010000100001 step 18 100000000000010010000000000000000000110111011000000001010000100001 step 19 100000000000010010000000000000000000110111011111000001010000100001 step 20 100000000000010010000000000000000000110111011011000001010000100001 step 21 100000000000010010000000000000000000110111011011111001010000100001 step 22 100000000000010010000000000000000000110111011011011001010000100001 step 23 100000000000010010000000000000000000110111011011011110100000100001 step 24 100000000000010010000000000000000000110111011011011010100000100001 step 25 100000000000010010000000000000000000110111011011011010101110100001 step 26 100000000000010010000000000000000000110111011011011010100110100001 step 27 100000000000010010000000000000000000110111011011011010100111111001 step 28 100000000000010010000000000000000000110111011011011010100110111001 step 29 100000000000000010000000000000000001110110011011011010100110111001 step 30 100000000000000000000000000000000001111100011011011010100110111001 step 31 100000000000000000000000000000000001111100011011011010100110111001 step 32 100001000000000000000000000000000001111100011011011010100110111001 step 33 100001100000000000000000000000000001111100011011011010100110111001 step 34 100001100100000000000000000000000001111100011011011010100110111001 step 35 100001100110000000000000000000000001111100011011011010100110111001 step 36 100001100110100000000000000000000001111100011011011010100110111001 step 37 100001100110100100000000000000000001111100011011011010100110111001 step 38 100001100110100100010000000000000001111100011011011010100110111001 step 39 100001100110100100011000000000000001111100011011011010100110111001 step 40 100001100110100100011010000000000001111100011011011010100110111001 step 41 100001100110100100011011000000000001111100011011011010100110111001 step 42 100001100110100100011011010000000001111100011011011010100110111001 step 43 100001100110100100011011011000000001111100011011011010100110111001 step 44 100001100110100100011011011010000001111100011011011010100110111001 step 45 100001100110100100011011011011000001111100011011011010100110111001 step 46 100001100110100100011011011011010001111100011011011010100110111001 step 47 100001100110100100011011011011011001111100011011011010100110111001 step 48 100001100110100100011011011011011101111100011011011010100110111001 step 49 110001100110100100011011011011011100110111011011011010100110111001 step 50 100001100110100100011011011011011101111100011011011010100110111001 step 51 101001100110100100011011011011011100110111011011011010100110111001 step 52 100001100110100100011011011011011101111100011011011010100110111001 step 53 100101100110100100011011011011011100110111011011011010100110111001 step 54 100001100110100100011011011011011101111100011011011010100110111001 step 55 100011100110100100011011011011011100110111011011011010100110111001 step 56 100001100110100100011011011011011101111100011011011010100110111001 step 57 100001110110100100011011011011011100110111011011011010100110111001 step 58 100001100110100100011011011011011101111100011011011010100110111001 step 59 100001101110100100011011011011011100110111011011011010100110111001 step 60 100001100110100100011011011011011101111100011011011010100110111001 step 61 100001100111100100011011011011011100111101011011011010100110111001 step 62 100001100110100100011011011011011101111100011011011010100110111001 step 63 100001100110110100011011011011011100111101011011011010100110111001 step 64 100001100110100100011011011011011101111100011011011010100110111001 step 65 100001100110101100011011011011011101110110011011011010100110111001 step 66 100001100110100100011011011011011101111100011011011010100110111001 step 67 100001100110100110011011011011011101110110011011011010100110111001 step 68 100001100110100100011011011011011101111100011011011010100110111001 step 69 100001100110100101011011011011011101001111011011011010100110111001 step 70 100001100110100100011011011011011101111100011011011010100110111001 step 71 100001100110100100111011011011011101001111011011011010100110111001 step 72 100001100110100100011011011011011101111100011011011010100110111001 step 73 100001100110100100011111011011011101001111011011011010100110111001 step 74 100001100110100100011011011011011101111100011011011010100110111001 step 75 100001100110100100011011111011011101001111011011011010100110111001 step 76 100001100110100100011011011011011101111100011011011010100110111001 step 77 100001100110100100011011011111011101001111011011011010100110111001 step 78 100001100110100100011011011011011101111100011011011010100110111001 step 79 100001100110100100011011011011111101001111011011011010100110111001 step 80 100001100110100100011011011011011101111100011011011010100110111001 step 81 100001100110100100011011011011011111101110011011011010100110111001 step 82 100001100110100100011011011011011101111100011011011010100110111001 test 18: pass SLOT BAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBAABBAAAAAAAAAAAAAABBBBBBBBAB LETTER ALPSLFMDEEMCBFRSPKLEMFHRSCJLJKUHPNMBBNNVVRKRHUTDJUKANJHBTPDFSVDEVU SIDE 121212122121212121111111112212122222112222111221112112212112212212 DIRECTION IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIOOOOOOOIOOIOOIOOIOOOOIOOIIOOIIO this fail all fails was hi 111111111111111111111111111111111111111111111111111111111111111 1 rising ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ ^^^^^^^^^^^^^^^^^^^^ ^^ falling vvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvv vvvvvvvvvvvvvvvvvvvv vv was lo 00000000000000000000000000000000000000 00000000000000000000 0000 total fails 0, total passes 18 step 1 100000000000000000000000000000000001111100011011011010100110111001 step 2 100000000000000000000000000000000001111100100011011010100110111001 step 3 100000000000000000000000000000000001111100000011011010100110111001 step 4 100000000000000000000000000000000001111100000100011010100110111001 step 5 100000000000000000000000000000000001111100000000011010100110111001 step 6 100000000000000000000000000000000001111100000000100010100110111001 step 7 100000000000000000000000000000000001111100000000000010100110111001 step 8 100000000000000000000000000000000001111100000000000101010110111001 step 9 100000000000000000000000000000000001111100000000000001010110111001 step 10 100000000000000000000000000000000001111100000000000001011000111001 step 11 100000000000000000000000000000000001111100000000000001010000111001 step 12 100000000000000000000000000000000001111100000000000001010001100001 step 13 100000000000000000000000000000000001111100000000000001010000100001 step 14 100000000000000000000000000000000001111100000000000001010000100001 step 15 100000000000010000000000000000000000111101000000000001010000100001 step 16 100000000000010010000000000000000000110111000000000001010000100001 step 17 100000000000010010000000000000000000110111111000000001010000100001 step 18 100000000000010010000000000000000000110111011000000001010000100001 step 19 100000000000010010000000000000000000110111011111000001010000100001 step 20 100000000000010010000000000000000000110111011011000001010000100001 step 21 100000000000010010000000000000000000110111011011111001010000100001 step 22 100000000000010010000000000000000000110111011011011001010000100001 step 23 100000000000010010000000000000000000110111011011011110100000100001 step 24 100000000000010010000000000000000000110111011011011010100000100001 step 25 100000000000010010000000000000000000110111011011011010101110100001 step 26 100000000000010010000000000000000000110111011011011010100110100001 step 27 100000000000010010000000000000000000110111011011011010100111111001 step 28 100000000000010010000000000000000000110111011011011010100110111001 step 29 100000000000000010000000000000000001110110011011011010100110111001 step 30 100000000000000000000000000000000001111100011011011010100110111001 step 31 100000000000000000000000000000000001111100011011011010100110111001 step 32 100001000000000000000000000000000001111100011011011010100110111001 step 33 100001100000000000000000000000000001111100011011011010100110111001 step 34 100001100100000000000000000000000001111100011011011010100110111001 step 35 100001100110000000000000000000000001111100011011011010100110111001 step 36 100001100110100000000000000000000001111100011011011010100110111001 step 37 100001100110100100000000000000000001111100011011011010100110111001 step 38 100001100110100100010000000000000001111100011011011010100110111001 step 39 100001100110100100011000000000000001111100011011011010100110111001 step 40 100001100110100100011010000000000001111100011011011010100110111001 step 41 100001100110100100011011000000000001111100011011011010100110111001 step 42 100001100110100100011011010000000001111100011011011010100110111001 step 43 100001100110100100011011011000000001111100011011011010100110111001 step 44 100001100110100100011011011010000001111100011011011010100110111001 step 45 100001100110100100011011011011000001111100011011011010100110111001 step 46 100001100110100100011011011011010001111100011011011010100110111001 step 47 100001100110100100011011011011011001111100011011011010100110111001 step 48 100001100110100100011011011011011101111100011011011010100110111001 step 49 110001100110100100011011011011011100110111011011011010100110111001 step 50 100001100110100100011011011011011101111100011011011010100110111001 step 51 101001100110100100011011011011011100110111011011011010100110111001 step 52 100001100110100100011011011011011101111100011011011010100110111001 step 53 100101100110100100011011011011011100110111011011011010100110111001 step 54 100001100110100100011011011011011101111100011011011010100110111001 step 55 100011100110100100011011011011011100110111011011011010100110111001 step 56 100001100110100100011011011011011101111100011011011010100110111001 step 57 100001110110100100011011011011011100110111011011011010100110111001 step 58 100001100110100100011011011011011101111100011011011010100110111001 step 59 100001101110100100011011011011011100110111011011011010100110111001 step 60 100001100110100100011011011011011101111100011011011010100110111001 step 61 100001100111100100011011011011011100111101011011011010100110111001 step 62 100001100110100100011011011011011101111100011011011010100110111001 step 63 100001100110110100011011011011011100111101011011011010100110111001 step 64 100001100110100100011011011011011101111100011011011010100110111001 step 65 100001100110101100011011011011011101110110011011011010100110111001 step 66 100001100110100100011011011011011101111100011011011010100110111001 step 67 100001100110100110011011011011011101110110011011011010100110111001 step 68 100001100110100100011011011011011101111100011011011010100110111001 step 69 100001100110100101011011011011011101001111011011011010100110111001 step 70 100001100110100100011011011011011101111100011011011010100110111001 step 71 100001100110100100111011011011011101001111011011011010100110111001 step 72 100001100110100100011011011011011101111100011011011010100110111001 step 73 100001100110100100011111011011011101001111011011011010100110111001 step 74 100001100110100100011011011011011101111100011011011010100110111001 step 75 100001100110100100011011111011011101001111011011011010100110111001 step 76 100001100110100100011011011011011101111100011011011010100110111001 step 77 100001100110100100011011011111011101001111011011011010100110111001 step 78 100001100110100100011011011011011101111100011011011010100110111001 step 79 100001100110100100011011011011111101001111011011011010100110111001 step 80 100001100110100100011011011011011101111100011011011010100110111001 step 81 100001100110100100011011011011011111101110011011011010100110111001 step 82 100001100110100100011011011011011101111100011011011010100110111001 test 19: pass SLOT BAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBAABBAAAAAAAAAAAAAABBBBBBBBAB LETTER ALPSLFMDEEMCBFRSPKLEMFHRSCJLJKUHPNMBBNNVVRKRHUTDJUKANJHBTPDFSVDEVU SIDE 121212122121212121111111112212122222112222111221112112212112212212 DIRECTION IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIOOOOOOOIOOIOOIOOIOOOOIOOIIOOIIO this fail all fails was hi 111111111111111111111111111111111111111111111111111111111111111 1 rising ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ ^^^^^^^^^^^^^^^^^^^^ ^^ falling vvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvv vvvvvvvvvvvvvvvvvvvv vv was lo 00000000000000000000000000000000000000 00000000000000000000 0000 total fails 0, total passes 19 step 1 100000000000000000000000000000000001111100011011011010100110111001 step 2 100000000000000000000000000000000001111100100011011010100110111001 step 3 100000000000000000000000000000000001111100000011011010100110111001 step 4 100000000000000000000000000000000001111100000100011010100110111001 step 5 100000000000000000000000000000000001111100000000011010100110111001 step 6 100000000000000000000000000000000001111100000000100010100110111001 step 7 100000000000000000000000000000000001111100000000000010100110111001 step 8 100000000000000000000000000000000001111100000000000101010110111001 step 9 100000000000000000000000000000000001111100000000000001010110111001 step 10 100000000000000000000000000000000001111100000000000001011000111001 step 11 100000000000000000000000000000000001111100000000000001010000111001 step 12 100000000000000000000000000000000001111100000000000001010001100001 step 13 100000000000000000000000000000000001111100000000000001010000100001 step 14 100000000000000000000000000000000001111100000000000001010000100001 step 15 100000000000010000000000000000000000111101000000000001010000100001 step 16 100000000000010010000000000000000000110111000000000001010000100001 step 17 100000000000010010000000000000000000110111111000000001010000100001 step 18 100000000000010010000000000000000000110111011000000001010000100001 step 19 100000000000010010000000000000000000110111011111000001010000100001 step 20 100000000000010010000000000000000000110111011011000001010000100001 step 21 100000000000010010000000000000000000110111011011111001010000100001 step 22 100000000000010010000000000000000000110111011011011001010000100001 step 23 100000000000010010000000000000000000110111011011011110100000100001 step 24 100000000000010010000000000000000000110111011011011010100000100001 step 25 100000000000010010000000000000000000110111011011011010101110100001 step 26 100000000000010010000000000000000000110111011011011010100110100001 step 27 100000000000010010000000000000000000110111011011011010100111111001 step 28 100000000000010010000000000000000000110111011011011010100110111001 step 29 100000000000000010000000000000000001110110011011011010100110111001 step 30 100000000000000000000000000000000001111100011011011010100110111001 step 31 100000000000000000000000000000000001111100011011011010100110111001 step 32 100001000000000000000000000000000001111100011011011010100110111001 step 33 100001100000000000000000000000000001111100011011011010100110111001 step 34 100001100100000000000000000000000001111100011011011010100110111001 step 35 100001100110000000000000000000000001111100011011011010100110111001 step 36 100001100110100000000000000000000001111100011011011010100110111001 step 37 100001100110100100000000000000000001111100011011011010100110111001 step 38 100001100110100100010000000000000001111100011011011010100110111001 step 39 100001100110100100011000000000000001111100011011011010100110111001 step 40 100001100110100100011010000000000001111100011011011010100110111001 step 41 100001100110100100011011000000000001111100011011011010100110111001 step 42 100001100110100100011011010000000001111100011011011010100110111001 step 43 100001100110100100011011011000000001111100011011011010100110111001 step 44 100001100110100100011011011010000001111100011011011010100110111001 step 45 100001100110100100011011011011000001111100011011011010100110111001 step 46 100001100110100100011011011011010001111100011011011010100110111001 step 47 100001100110100100011011011011011001111100011011011010100110111001 step 48 100001100110100100011011011011011101111100011011011010100110111001 step 49 110001100110100100011011011011011100110111011011011010100110111001 step 50 100001100110100100011011011011011101111100011011011010100110111001 step 51 101001100110100100011011011011011100110111011011011010100110111001 step 52 100001100110100100011011011011011101111100011011011010100110111001 step 53 100101100110100100011011011011011100110111011011011010100110111001 step 54 100001100110100100011011011011011101111100011011011010100110111001 step 55 100011100110100100011011011011011100110111011011011010100110111001 step 56 100001100110100100011011011011011101111100011011011010100110111001 step 57 100001110110100100011011011011011100110111011011011010100110111001 step 58 100001100110100100011011011011011101111100011011011010100110111001 step 59 100001101110100100011011011011011100110111011011011010100110111001 step 60 100001100110100100011011011011011101111100011011011010100110111001 step 61 100001100111100100011011011011011100111101011011011010100110111001 step 62 100001100110100100011011011011011101111100011011011010100110111001 step 63 100001100110110100011011011011011100111101011011011010100110111001 step 64 100001100110100100011011011011011101111100011011011010100110111001 step 65 100001100110101100011011011011011101110110011011011010100110111001 step 66 100001100110100100011011011011011101111100011011011010100110111001 step 67 100001100110100110011011011011011101110110011011011010100110111001 step 68 100001100110100100011011011011011101111100011011011010100110111001 step 69 100001100110100101011011011011011101001111011011011010100110111001 step 70 100001100110100100011011011011011101111100011011011010100110111001 step 71 100001100110100100111011011011011101001111011011011010100110111001 step 72 100001100110100100011011011011011101111100011011011010100110111001 step 73 100001100110100100011111011011011101001111011011011010100110111001 step 74 100001100110100100011011011011011101111100011011011010100110111001 step 75 100001100110100100011011111011011101001111011011011010100110111001 step 76 100001100110100100011011011011011101111100011011011010100110111001 step 77 100001100110100100011011011111011101001111011011011010100110111001 step 78 100001100110100100011011011011011101111100011011011010100110111001 step 79 100001100110100100011011011011111101001111011011011010100110111001 step 80 100001100110100100011011011011011101111100011011011010100110111001 step 81 100001100110100100011011011011011111101110011011011010100110111001 step 82 100001100110100100011011011011011101111100011011011010100110111001 test 20: pass SLOT BAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBAABBAAAAAAAAAAAAAABBBBBBBBAB LETTER ALPSLFMDEEMCBFRSPKLEMFHRSCJLJKUHPNMBBNNVVRKRHUTDJUKANJHBTPDFSVDEVU SIDE 121212122121212121111111112212122222112222111221112112212112212212 DIRECTION IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIOOOOOOOIOOIOOIOOIOOOOIOOIIOOIIO this fail all fails was hi 111111111111111111111111111111111111111111111111111111111111111 1 rising ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ ^^^^^^^^^^^^^^^^^^^^ ^^ falling vvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvv vvvvvvvvvvvvvvvvvvvv vv was lo 00000000000000000000000000000000000000 00000000000000000000 0000 total fails 0, total passes 20 step 1 100000000000000000000000000000000001111100011011011010100110111001 step 2 100000000000000000000000000000000001111100100011011010100110111001 step 3 100000000000000000000000000000000001111100000011011010100110111001 step 4 100000000000000000000000000000000001111100000100011010100110111001 step 5 100000000000000000000000000000000001111100000000011010100110111001 step 6 100000000000000000000000000000000001111100000000100010100110111001 step 7 100000000000000000000000000000000001111100000000000010100110111001 step 8 100000000000000000000000000000000001111100000000000101010110111001 step 9 100000000000000000000000000000000001111100000000000001010110111001 step 10 100000000000000000000000000000000001111100000000000001011000111001 step 11 100000000000000000000000000000000001111100000000000001010000111001 step 12 100000000000000000000000000000000001111100000000000001010001100001 step 13 100000000000000000000000000000000001111100000000000001010000100001 step 14 100000000000000000000000000000000001111100000000000001010000100001 step 15 100000000000010000000000000000000000111101000000000001010000100001 step 16 100000000000010010000000000000000000110111000000000001010000100001 step 17 100000000000010010000000000000000000110111111000000001010000100001 step 18 100000000000010010000000000000000000110111011000000001010000100001 step 19 100000000000010010000000000000000000110111011111000001010000100001 step 20 100000000000010010000000000000000000110111011011000001010000100001 step 21 100000000000010010000000000000000000110111011011111001010000100001 step 22 100000000000010010000000000000000000110111011011011001010000100001 step 23 100000000000010010000000000000000000110111011011011110100000100001 step 24 100000000000010010000000000000000000110111011011011010100000100001 step 25 100000000000010010000000000000000000110111011011011010101110100001 step 26 100000000000010010000000000000000000110111011011011010100110100001 step 27 100000000000010010000000000000000000110111011011011010100111111001 step 28 100000000000010010000000000000000000110111011011011010100110111001 step 29 100000000000000010000000000000000001110110011011011010100110111001 step 30 100000000000000000000000000000000001111100011011011010100110111001 step 31 100000000000000000000000000000000001111100011011011010100110111001 step 32 100001000000000000000000000000000001111100011011011010100110111001 step 33 100001100000000000000000000000000001111100011011011010100110111001 step 34 100001100100000000000000000000000001111100011011011010100110111001 step 35 100001100110000000000000000000000001111100011011011010100110111001 step 36 100001100110100000000000000000000001111100011011011010100110111001 step 37 100001100110100100000000000000000001111100011011011010100110111001 step 38 100001100110100100010000000000000001111100011011011010100110111001 step 39 100001100110100100011000000000000001111100011011011010100110111001 step 40 100001100110100100011010000000000001111100011011011010100110111001 step 41 100001100110100100011011000000000001111100011011011010100110111001 step 42 100001100110100100011011010000000001111100011011011010100110111001 step 43 100001100110100100011011011000000001111100011011011010100110111001 step 44 100001100110100100011011011010000001111100011011011010100110111001 step 45 100001100110100100011011011011000001111100011011011010100110111001 step 46 100001100110100100011011011011010001111100011011011010100110111001 step 47 100001100110100100011011011011011001111100011011011010100110111001 step 48 100001100110100100011011011011011101111100011011011010100110111001 step 49 110001100110100100011011011011011100110111011011011010100110111001 step 50 100001100110100100011011011011011101111100011011011010100110111001 step 51 101001100110100100011011011011011100110111011011011010100110111001 step 52 100001100110100100011011011011011101111100011011011010100110111001 step 53 100101100110100100011011011011011100110111011011011010100110111001 step 54 100001100110100100011011011011011101111100011011011010100110111001 step 55 100011100110100100011011011011011100110111011011011010100110111001 step 56 100001100110100100011011011011011101111100011011011010100110111001 step 57 100001110110100100011011011011011100110111011011011010100110111001 step 58 100001100110100100011011011011011101111100011011011010100110111001 step 59 100001101110100100011011011011011100110111011011011010100110111001 step 60 100001100110100100011011011011011101111100011011011010100110111001 step 61 100001100111100100011011011011011100111101011011011010100110111001 step 62 100001100110100100011011011011011101111100011011011010100110111001 step 63 100001100110110100011011011011011100111101011011011010100110111001 step 64 100001100110100100011011011011011101111100011011011010100110111001 step 65 100001100110101100011011011011011101110110011011011010100110111001 step 66 100001100110100100011011011011011101111100011011011010100110111001 step 67 100001100110100110011011011011011101110110011011011010100110111001 step 68 100001100110100100011011011011011101111100011011011010100110111001 step 69 100001100110100101011011011011011101001111011011011010100110111001 step 70 100001100110100100011011011011011101111100011011011010100110111001 step 71 100001100110100100111011011011011101001111011011011010100110111001 step 72 100001100110100100011011011011011101111100011011011010100110111001 step 73 100001100110100100011111011011011101001111011011011010100110111001 step 74 100001100110100100011011011011011101111100011011011010100110111001 step 75 100001100110100100011011111011011101001111011011011010100110111001 step 76 100001100110100100011011011011011101111100011011011010100110111001 step 77 100001100110100100011011011111011101001111011011011010100110111001 step 78 100001100110100100011011011011011101111100011011011010100110111001 step 79 100001100110100100011011011011111101001111011011011010100110111001 step 80 100001100110100100011011011011011101111100011011011010100110111001 step 81 100001100110100100011011011011011111101110011011011010100110111001 step 82 100001100110100100011011011011011101111100011011011010100110111001 test 21: pass SLOT BAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBAABBAAAAAAAAAAAAAABBBBBBBBAB LETTER ALPSLFMDEEMCBFRSPKLEMFHRSCJLJKUHPNMBBNNVVRKRHUTDJUKANJHBTPDFSVDEVU SIDE 121212122121212121111111112212122222112222111221112112212112212212 DIRECTION IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIOOOOOOOIOOIOOIOOIOOOOIOOIIOOIIO this fail all fails was hi 111111111111111111111111111111111111111111111111111111111111111 1 rising ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ ^^^^^^^^^^^^^^^^^^^^ ^^ falling vvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvv vvvvvvvvvvvvvvvvvvvv vv was lo 00000000000000000000000000000000000000 00000000000000000000 0000 total fails 0, total passes 21 step 1 100000000000000000000000000000000001111100011011011010100110111001 step 2 100000000000000000000000000000000001111100100011011010100110111001 step 3 100000000000000000000000000000000001111100000011011010100110111001 step 4 100000000000000000000000000000000001111100000100011010100110111001 step 5 100000000000000000000000000000000001111100000000011010100110111001 step 6 100000000000000000000000000000000001111100000000100010100110111001 step 7 100000000000000000000000000000000001111100000000000010100110111001 step 8 100000000000000000000000000000000001111100000000000101010110111001 step 9 100000000000000000000000000000000001111100000000000001010110111001 step 10 100000000000000000000000000000000001111100000000000001011000111001 step 11 100000000000000000000000000000000001111100000000000001010000111001 step 12 100000000000000000000000000000000001111100000000000001010001100001 step 13 100000000000000000000000000000000001111100000000000001010000100001 step 14 100000000000000000000000000000000001111100000000000001010000100001 step 15 100000000000010000000000000000000000111101000000000001010000100001 step 16 100000000000010010000000000000000000110111000000000001010000100001 step 17 100000000000010010000000000000000000110111111000000001010000100001 step 18 100000000000010010000000000000000000110111011000000001010000100001 step 19 100000000000010010000000000000000000110111011111000001010000100001 step 20 100000000000010010000000000000000000110111011011000001010000100001 step 21 100000000000010010000000000000000000110111011011111001010000100001 step 22 100000000000010010000000000000000000110111011011011001010000100001 step 23 100000000000010010000000000000000000110111011011011110100000100001 step 24 100000000000010010000000000000000000110111011011011010100000100001 step 25 100000000000010010000000000000000000110111011011011010101110100001 step 26 100000000000010010000000000000000000110111011011011010100110100001 step 27 100000000000010010000000000000000000110111011011011010100111111001 step 28 100000000000010010000000000000000000110111011011011010100110111001 step 29 100000000000000010000000000000000001110110011011011010100110111001 step 30 100000000000000000000000000000000001111100011011011010100110111001 step 31 100000000000000000000000000000000001111100011011011010100110111001 step 32 100001000000000000000000000000000001111100011011011010100110111001 step 33 100001100000000000000000000000000001111100011011011010100110111001 step 34 100001100100000000000000000000000001111100011011011010100110111001 step 35 100001100110000000000000000000000001111100011011011010100110111001 step 36 100001100110100000000000000000000001111100011011011010100110111001 step 37 100001100110100100000000000000000001111100011011011010100110111001 step 38 100001100110100100010000000000000001111100011011011010100110111001 step 39 100001100110100100011000000000000001111100011011011010100110111001 step 40 100001100110100100011010000000000001111100011011011010100110111001 step 41 100001100110100100011011000000000001111100011011011010100110111001 step 42 100001100110100100011011010000000001111100011011011010100110111001 step 43 100001100110100100011011011000000001111100011011011010100110111001 step 44 100001100110100100011011011010000001111100011011011010100110111001 step 45 100001100110100100011011011011000001111100011011011010100110111001 step 46 100001100110100100011011011011010001111100011011011010100110111001 step 47 100001100110100100011011011011011001111100011011011010100110111001 step 48 100001100110100100011011011011011101111100011011011010100110111001 step 49 110001100110100100011011011011011100110111011011011010100110111001 step 50 100001100110100100011011011011011101111100011011011010100110111001 step 51 101001100110100100011011011011011100110111011011011010100110111001 step 52 100001100110100100011011011011011101111100011011011010100110111001 step 53 100101100110100100011011011011011100110111011011011010100110111001 step 54 100001100110100100011011011011011101111100011011011010100110111001 step 55 100011100110100100011011011011011100110111011011011010100110111001 step 56 100001100110100100011011011011011101111100011011011010100110111001 step 57 100001110110100100011011011011011100110111011011011010100110111001 step 58 100001100110100100011011011011011101111100011011011010100110111001 step 59 100001101110100100011011011011011100110111011011011010100110111001 step 60 100001100110100100011011011011011101111100011011011010100110111001 step 61 100001100111100100011011011011011100111101011011011010100110111001 step 62 100001100110100100011011011011011101111100011011011010100110111001 step 63 100001100110110100011011011011011100111101011011011010100110111001 step 64 100001100110100100011011011011011101111100011011011010100110111001 step 65 100001100110101100011011011011011101110110011011011010100110111001 step 66 100001100110100100011011011011011101111100011011011010100110111001 step 67 100001100110100110011011011011011101110110011011011010100110111001 step 68 100001100110100100011011011011011101111100011011011010100110111001 step 69 100001100110100101011011011011011101001111011011011010100110111001 step 70 100001100110100100011011011011011101111100011011011010100110111001 step 71 100001100110100100111011011011011101001111011011011010100110111001 step 72 100001100110100100011011011011011101111100011011011010100110111001 step 73 100001100110100100011111011011011101001111011011011010100110111001 step 74 100001100110100100011011011011011101111100011011011010100110111001 step 75 100001100110100100011011111011011101001111011011011010100110111001 step 76 100001100110100100011011011011011101111100011011011010100110111001 step 77 100001100110100100011011011111011101001111011011011010100110111001 step 78 100001100110100100011011011011011101111100011011011010100110111001 step 79 100001100110100100011011011011111101001111011011011010100110111001 step 80 100001100110100100011011011011011101111100011011011010100110111001 step 81 100001100110100100011011011011011111101110011011011010100110111001 step 82 100001100110100100011011011011011101111100011011011010100110111001 test 22: pass SLOT BAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBAABBAAAAAAAAAAAAAABBBBBBBBAB LETTER ALPSLFMDEEMCBFRSPKLEMFHRSCJLJKUHPNMBBNNVVRKRHUTDJUKANJHBTPDFSVDEVU SIDE 121212122121212121111111112212122222112222111221112112212112212212 DIRECTION IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIOOOOOOOIOOIOOIOOIOOOOIOOIIOOIIO this fail all fails was hi 111111111111111111111111111111111111111111111111111111111111111 1 rising ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ ^^^^^^^^^^^^^^^^^^^^ ^^ falling vvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvv vvvvvvvvvvvvvvvvvvvv vv was lo 00000000000000000000000000000000000000 00000000000000000000 0000 total fails 0, total passes 22 step 1 100000000000000000000000000000000001111100011011011010100110111001 step 2 100000000000000000000000000000000001111100100011011010100110111001 step 3 100000000000000000000000000000000001111100000011011010100110111001 step 4 100000000000000000000000000000000001111100000100011010100110111001 step 5 100000000000000000000000000000000001111100000000011010100110111001 step 6 100000000000000000000000000000000001111100000000100010100110111001 step 7 100000000000000000000000000000000001111100000000000010100110111001 step 8 100000000000000000000000000000000001111100000000000101010110111001 step 9 100000000000000000000000000000000001111100000000000001010110111001 step 10 100000000000000000000000000000000001111100000000000001011000111001 step 11 100000000000000000000000000000000001111100000000000001010000111001 step 12 100000000000000000000000000000000001111100000000000001010001100001 step 13 100000000000000000000000000000000001111100000000000001010000100001 step 14 100000000000000000000000000000000001111100000000000001010000100001 step 15 100000000000010000000000000000000000111101000000000001010000100001 step 16 100000000000010010000000000000000000110111000000000001010000100001 step 17 100000000000010010000000000000000000110111111000000001010000100001 step 18 100000000000010010000000000000000000110111011000000001010000100001 step 19 100000000000010010000000000000000000110111011111000001010000100001 step 20 100000000000010010000000000000000000110111011011000001010000100001 step 21 100000000000010010000000000000000000110111011011111001010000100001 step 22 100000000000010010000000000000000000110111011011011001010000100001 step 23 100000000000010010000000000000000000110111011011011110100000100001 step 24 100000000000010010000000000000000000110111011011011010100000100001 step 25 100000000000010010000000000000000000110111011011011010101110100001 step 26 100000000000010010000000000000000000110111011011011010100110100001 step 27 100000000000010010000000000000000000110111011011011010100111111001 step 28 100000000000010010000000000000000000110111011011011010100110111001 step 29 100000000000000010000000000000000001110110011011011010100110111001 step 30 100000000000000000000000000000000001111100011011011010100110111001 step 31 100000000000000000000000000000000001111100011011011010100110111001 step 32 100001000000000000000000000000000001111100011011011010100110111001 step 33 100001100000000000000000000000000001111100011011011010100110111001 step 34 100001100100000000000000000000000001111100011011011010100110111001 step 35 100001100110000000000000000000000001111100011011011010100110111001 step 36 100001100110100000000000000000000001111100011011011010100110111001 step 37 100001100110100100000000000000000001111100011011011010100110111001 step 38 100001100110100100010000000000000001111100011011011010100110111001 step 39 100001100110100100011000000000000001111100011011011010100110111001 step 40 100001100110100100011010000000000001111100011011011010100110111001 step 41 100001100110100100011011000000000001111100011011011010100110111001 step 42 100001100110100100011011010000000001111100011011011010100110111001 step 43 100001100110100100011011011000000001111100011011011010100110111001 step 44 100001100110100100011011011010000001111100011011011010100110111001 step 45 100001100110100100011011011011000001111100011011011010100110111001 step 46 100001100110100100011011011011010001111100011011011010100110111001 step 47 100001100110100100011011011011011001111100011011011010100110111001 step 48 100001100110100100011011011011011101111100011011011010100110111001 step 49 110001100110100100011011011011011100110111011011011010100110111001 step 50 100001100110100100011011011011011101111100011011011010100110111001 step 51 101001100110100100011011011011011100110111011011011010100110111001 step 52 100001100110100100011011011011011101111100011011011010100110111001 step 53 100101100110100100011011011011011100110111011011011010100110111001 step 54 100001100110100100011011011011011101111100011011011010100110111001 step 55 100011100110100100011011011011011100110111011011011010100110111001 step 56 100001100110100100011011011011011101111100011011011010100110111001 step 57 100001110110100100011011011011011100110111011011011010100110111001 step 58 100001100110100100011011011011011101111100011011011010100110111001 step 59 100001101110100100011011011011011100110111011011011010100110111001 step 60 100001100110100100011011011011011101111100011011011010100110111001 step 61 100001100111100100011011011011011100111101011011011010100110111001 step 62 100001100110100100011011011011011101111100011011011010100110111001 step 63 100001100110110100011011011011011100111101011011011010100110111001 step 64 100001100110100100011011011011011101111100011011011010100110111001 step 65 100001100110101100011011011011011101110110011011011010100110111001 step 66 100001100110100100011011011011011101111100011011011010100110111001 step 67 100001100110100110011011011011011101110110011011011010100110111001 step 68 100001100110100100011011011011011101111100011011011010100110111001 step 69 100001100110100101011011011011011101001111011011011010100110111001 step 70 100001100110100100011011011011011101111100011011011010100110111001 step 71 100001100110100100111011011011011101001111011011011010100110111001 step 72 100001100110100100011011011011011101111100011011011010100110111001 step 73 100001100110100100011111011011011101001111011011011010100110111001 step 74 100001100110100100011011011011011101111100011011011010100110111001 step 75 100001100110100100011011111011011101001111011011011010100110111001 step 76 100001100110100100011011011011011101111100011011011010100110111001 step 77 100001100110100100011011011111011101001111011011011010100110111001 step 78 100001100110100100011011011011011101111100011011011010100110111001 step 79 100001100110100100011011011011111101001111011011011010100110111001 step 80 100001100110100100011011011011011101111100011011011010100110111001 step 81 100001100110100100011011011011011111101110011011011010100110111001 step 82 100001100110100100011011011011011101111100011011011010100110111001 test 23: pass SLOT BAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBAABBAAAAAAAAAAAAAABBBBBBBBAB LETTER ALPSLFMDEEMCBFRSPKLEMFHRSCJLJKUHPNMBBNNVVRKRHUTDJUKANJHBTPDFSVDEVU SIDE 121212122121212121111111112212122222112222111221112112212112212212 DIRECTION IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIOOOOOOOIOOIOOIOOIOOOOIOOIIOOIIO this fail all fails was hi 111111111111111111111111111111111111111111111111111111111111111 1 rising ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ ^^^^^^^^^^^^^^^^^^^^ ^^ falling vvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvv vvvvvvvvvvvvvvvvvvvv vv was lo 00000000000000000000000000000000000000 00000000000000000000 0000 total fails 0, total passes 23 step 1 100000000000000000000000000000000001111100011011011010100110111001 step 2 100000000000000000000000000000000001111100100011011010100110111001 step 3 100000000000000000000000000000000001111100000011011010100110111001 step 4 100000000000000000000000000000000001111100000100011010100110111001 step 5 100000000000000000000000000000000001111100000000011010100110111001 step 6 100000000000000000000000000000000001111100000000100010100110111001 step 7 100000000000000000000000000000000001111100000000000010100110111001 step 8 100000000000000000000000000000000001111100000000000101010110111001 step 9 100000000000000000000000000000000001111100000000000001010110111001 step 10 100000000000000000000000000000000001111100000000000001011000111001 step 11 100000000000000000000000000000000001111100000000000001010000111001 step 12 100000000000000000000000000000000001111100000000000001010001100001 step 13 100000000000000000000000000000000001111100000000000001010000100001 step 14 100000000000000000000000000000000001111100000000000001010000100001 step 15 100000000000010000000000000000000000111101000000000001010000100001 step 16 100000000000010010000000000000000000110111000000000001010000100001 step 17 100000000000010010000000000000000000110111111000000001010000100001 step 18 100000000000010010000000000000000000110111011000000001010000100001 step 19 100000000000010010000000000000000000110111011111000001010000100001 step 20 100000000000010010000000000000000000110111011011000001010000100001 step 21 100000000000010010000000000000000000110111011011111001010000100001 step 22 100000000000010010000000000000000000110111011011011001010000100001 step 23 100000000000010010000000000000000000110111011011011110100000100001 step 24 100000000000010010000000000000000000110111011011011010100000100001 step 25 100000000000010010000000000000000000110111011011011010101110100001 step 26 100000000000010010000000000000000000110111011011011010100110100001 step 27 100000000000010010000000000000000000110111011011011010100111111001 step 28 100000000000010010000000000000000000110111011011011010100110111001 step 29 100000000000000010000000000000000001110110011011011010100110111001 step 30 100000000000000000000000000000000001111100011011011010100110111001 step 31 100000000000000000000000000000000001111100011011011010100110111001 step 32 100001000000000000000000000000000001111100011011011010100110111001 step 33 100001100000000000000000000000000001111100011011011010100110111001 step 34 100001100100000000000000000000000001111100011011011010100110111001 step 35 100001100110000000000000000000000001111100011011011010100110111001 step 36 100001100110100000000000000000000001111100011011011010100110111001 step 37 100001100110100100000000000000000001111100011011011010100110111001 step 38 100001100110100100010000000000000001111100011011011010100110111001 step 39 100001100110100100011000000000000001111100011011011010100110111001 step 40 100001100110100100011010000000000001111100011011011010100110111001 step 41 100001100110100100011011000000000001111100011011011010100110111001 step 42 100001100110100100011011010000000001111100011011011010100110111001 step 43 100001100110100100011011011000000001111100011011011010100110111001 step 44 100001100110100100011011011010000001111100011011011010100110111001 step 45 100001100110100100011011011011000001111100011011011010100110111001 step 46 100001100110100100011011011011010001111100011011011010100110111001 step 47 100001100110100100011011011011011001111100011011011010100110111001 step 48 100001100110100100011011011011011101111100011011011010100110111001 step 49 110001100110100100011011011011011100110111011011011010100110111001 step 50 100001100110100100011011011011011101111100011011011010100110111001 step 51 101001100110100100011011011011011100110111011011011010100110111001 step 52 100001100110100100011011011011011101111100011011011010100110111001 step 53 100101100110100100011011011011011100110111011011011010100110111001 step 54 100001100110100100011011011011011101111100011011011010100110111001 step 55 100011100110100100011011011011011100110111011011011010100110111001 step 56 100001100110100100011011011011011101111100011011011010100110111001 step 57 100001110110100100011011011011011100110111011011011010100110111001 step 58 100001100110100100011011011011011101111100011011011010100110111001 step 59 100001101110100100011011011011011100110111011011011010100110111001 step 60 100001100110100100011011011011011101111100011011011010100110111001 step 61 100001100111100100011011011011011100111101011011011010100110111001 step 62 100001100110100100011011011011011101111100011011011010100110111001 step 63 100001100110110100011011011011011100111101011011011010100110111001 step 64 100001100110100100011011011011011101111100011011011010100110111001 step 65 100001100110101100011011011011011101110110011011011010100110111001 step 66 100001100110100100011011011011011101111100011011011010100110111001 step 67 100001100110100110011011011011011101110110011011011010100110111001 step 68 100001100110100100011011011011011101111100011011011010100110111001 step 69 100001100110100101011011011011011101001111011011011010100110111001 step 70 100001100110100100011011011011011101111100011011011010100110111001 step 71 100001100110100100111011011011011101001111011011011010100110111001 step 72 100001100110100100011011011011011101111100011011011010100110111001 step 73 100001100110100100011111011011011101001111011011011010100110111001 step 74 100001100110100100011011011011011101111100011011011010100110111001 step 75 100001100110100100011011111011011101001111011011011010100110111001 step 76 100001100110100100011011011011011101111100011011011010100110111001 step 77 100001100110100100011011011111011101001111011011011010100110111001 step 78 100001100110100100011011011011011101111100011011011010100110111001 step 79 100001100110100100011011011011111101001111011011011010100110111001 step 80 100001100110100100011011011011011101111100011011011010100110111001 step 81 100001100110100100011011011011011111101110011011011010100110111001 step 82 100001100110100100011011011011011101111100011011011010100110111001 test 24: pass SLOT BAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBAABBAAAAAAAAAAAAAABBBBBBBBAB LETTER ALPSLFMDEEMCBFRSPKLEMFHRSCJLJKUHPNMBBNNVVRKRHUTDJUKANJHBTPDFSVDEVU SIDE 121212122121212121111111112212122222112222111221112112212112212212 DIRECTION IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIOOOOOOOIOOIOOIOOIOOOOIOOIIOOIIO this fail all fails was hi 111111111111111111111111111111111111111111111111111111111111111 1 rising ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ ^^^^^^^^^^^^^^^^^^^^ ^^ falling vvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvv vvvvvvvvvvvvvvvvvvvv vv was lo 00000000000000000000000000000000000000 00000000000000000000 0000 total fails 0, total passes 24 step 1 100000000000000000000000000000000001111100011011011010100110111001 step 2 100000000000000000000000000000000001111100100011011010100110111001 step 3 100000000000000000000000000000000001111100000011011010100110111001 step 4 100000000000000000000000000000000001111100000100011010100110111001 step 5 100000000000000000000000000000000001111100000000011010100110111001 step 6 100000000000000000000000000000000001111100000000100010100110111001 step 7 100000000000000000000000000000000001111100000000000010100110111001 step 8 100000000000000000000000000000000001111100000000000101010110111001 step 9 100000000000000000000000000000000001111100000000000001010110111001 step 10 100000000000000000000000000000000001111100000000000001011000111001 step 11 100000000000000000000000000000000001111100000000000001010000111001 step 12 100000000000000000000000000000000001111100000000000001010001100001 step 13 100000000000000000000000000000000001111100000000000001010000100001 step 14 100000000000000000000000000000000001111100000000000001010000100001 step 15 100000000000010000000000000000000000111101000000000001010000100001 step 16 100000000000010010000000000000000000110111000000000001010000100001 step 17 100000000000010010000000000000000000110111111000000001010000100001 step 18 100000000000010010000000000000000000110111011000000001010000100001 step 19 100000000000010010000000000000000000110111011111000001010000100001 step 20 100000000000010010000000000000000000110111011011000001010000100001 step 21 100000000000010010000000000000000000110111011011111001010000100001 step 22 100000000000010010000000000000000000110111011011011001010000100001 step 23 100000000000010010000000000000000000110111011011011110100000100001 step 24 100000000000010010000000000000000000110111011011011010100000100001 step 25 100000000000010010000000000000000000110111011011011010101110100001 step 26 100000000000010010000000000000000000110111011011011010100110100001 step 27 100000000000010010000000000000000000110111011011011010100111111001 step 28 100000000000010010000000000000000000110111011011011010100110111001 step 29 100000000000000010000000000000000001110110011011011010100110111001 step 30 100000000000000000000000000000000001111100011011011010100110111001 step 31 100000000000000000000000000000000001111100011011011010100110111001 step 32 100001000000000000000000000000000001111100011011011010100110111001 step 33 100001100000000000000000000000000001111100011011011010100110111001 step 34 100001100100000000000000000000000001111100011011011010100110111001 step 35 100001100110000000000000000000000001111100011011011010100110111001 step 36 100001100110100000000000000000000001111100011011011010100110111001 step 37 100001100110100100000000000000000001111100011011011010100110111001 step 38 100001100110100100010000000000000001111100011011011010100110111001 step 39 100001100110100100011000000000000001111100011011011010100110111001 step 40 100001100110100100011010000000000001111100011011011010100110111001 step 41 100001100110100100011011000000000001111100011011011010100110111001 step 42 100001100110100100011011010000000001111100011011011010100110111001 step 43 100001100110100100011011011000000001111100011011011010100110111001 step 44 100001100110100100011011011010000001111100011011011010100110111001 step 45 100001100110100100011011011011000001111100011011011010100110111001 step 46 100001100110100100011011011011010001111100011011011010100110111001 step 47 100001100110100100011011011011011001111100011011011010100110111001 step 48 100001100110100100011011011011011101111100011011011010100110111001 step 49 110001100110100100011011011011011100110111011011011010100110111001 step 50 100001100110100100011011011011011101111100011011011010100110111001 step 51 101001100110100100011011011011011100110111011011011010100110111001 step 52 100001100110100100011011011011011101111100011011011010100110111001 step 53 100101100110100100011011011011011100110111011011011010100110111001 step 54 100001100110100100011011011011011101111100011011011010100110111001 step 55 100011100110100100011011011011011100110111011011011010100110111001 step 56 100001100110100100011011011011011101111100011011011010100110111001 step 57 100001110110100100011011011011011100110111011011011010100110111001 step 58 100001100110100100011011011011011101111100011011011010100110111001 step 59 100001101110100100011011011011011100110111011011011010100110111001 step 60 100001100110100100011011011011011101111100011011011010100110111001 step 61 100001100111100100011011011011011100111101011011011010100110111001 step 62 100001100110100100011011011011011101111100011011011010100110111001 step 63 100001100110110100011011011011011100111101011011011010100110111001 step 64 100001100110100100011011011011011101111100011011011010100110111001 step 65 100001100110101100011011011011011101110110011011011010100110111001 step 66 100001100110100100011011011011011101111100011011011010100110111001 step 67 100001100110100110011011011011011101110110011011011010100110111001 step 68 100001100110100100011011011011011101111100011011011010100110111001 step 69 100001100110100101011011011011011101001111011011011010100110111001 step 70 100001100110100100011011011011011101111100011011011010100110111001 step 71 100001100110100100111011011011011101001111011011011010100110111001 step 72 100001100110100100011011011011011101111100011011011010100110111001 step 73 100001100110100100011111011011011101001111011011011010100110111001 step 74 100001100110100100011011011011011101111100011011011010100110111001 step 75 100001100110100100011011111011011101001111011011011010100110111001 step 76 100001100110100100011011011011011101111100011011011010100110111001 step 77 100001100110100100011011011111011101001111011011011010100110111001 step 78 100001100110100100011011011011011101111100011011011010100110111001 step 79 100001100110100100011011011011111101001111011011011010100110111001 step 80 100001100110100100011011011011011101111100011011011010100110111001 step 81 100001100110100100011011011011011111101110011011011010100110111001 step 82 100001100110100100011011011011011101111100011011011010100110111001 test 25: pass SLOT BAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBAABBAAAAAAAAAAAAAABBBBBBBBAB LETTER ALPSLFMDEEMCBFRSPKLEMFHRSCJLJKUHPNMBBNNVVRKRHUTDJUKANJHBTPDFSVDEVU SIDE 121212122121212121111111112212122222112222111221112112212112212212 DIRECTION IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIOOOOOOOIOOIOOIOOIOOOOIOOIIOOIIO this fail all fails was hi 111111111111111111111111111111111111111111111111111111111111111 1 rising ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ ^^^^^^^^^^^^^^^^^^^^ ^^ falling vvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvv vvvvvvvvvvvvvvvvvvvv vv was lo 00000000000000000000000000000000000000 00000000000000000000 0000 total fails 0, total passes 25 step 1 100000000000000000000000000000000001111100011011011010100110111001 step 2 100000000000000000000000000000000001111100100011011010100110111001 step 3 100000000000000000000000000000000001111100000011011010100110111001 step 4 100000000000000000000000000000000001111100000100011010100110111001 step 5 100000000000000000000000000000000001111100000000011010100110111001 step 6 100000000000000000000000000000000001111100000000100010100110111001 step 7 100000000000000000000000000000000001111100000000000010100110111001 step 8 100000000000000000000000000000000001111100000000000101010110111001 step 9 100000000000000000000000000000000001111100000000000001010110111001 step 10 100000000000000000000000000000000001111100000000000001011000111001 step 11 100000000000000000000000000000000001111100000000000001010000111001 step 12 100000000000000000000000000000000001111100000000000001010001100001 step 13 100000000000000000000000000000000001111100000000000001010000100001 step 14 100000000000000000000000000000000001111100000000000001010000100001 step 15 100000000000010000000000000000000000111101000000000001010000100001 step 16 100000000000010010000000000000000000110111000000000001010000100001 step 17 100000000000010010000000000000000000110111111000000001010000100001 step 18 100000000000010010000000000000000000110111011000000001010000100001 step 19 100000000000010010000000000000000000110111011111000001010000100001 step 20 100000000000010010000000000000000000110111011011000001010000100001 step 21 100000000000010010000000000000000000110111011011111001010000100001 step 22 100000000000010010000000000000000000110111011011011001010000100001 step 23 100000000000010010000000000000000000110111011011011110100000100001 step 24 100000000000010010000000000000000000110111011011011010100000100001 step 25 100000000000010010000000000000000000110111011011011010101110100001 step 26 100000000000010010000000000000000000110111011011011010100110100001 step 27 100000000000010010000000000000000000110111011011011010100111111001 step 28 100000000000010010000000000000000000110111011011011010100110111001 step 29 100000000000000010000000000000000001110110011011011010100110111001 step 30 100000000000000000000000000000000001111100011011011010100110111001 step 31 100000000000000000000000000000000001111100011011011010100110111001 step 32 100001000000000000000000000000000001111100011011011010100110111001 step 33 100001100000000000000000000000000001111100011011011010100110111001 step 34 100001100100000000000000000000000001111100011011011010100110111001 step 35 100001100110000000000000000000000001111100011011011010100110111001 step 36 100001100110100000000000000000000001111100011011011010100110111001 step 37 100001100110100100000000000000000001111100011011011010100110111001 step 38 100001100110100100010000000000000001111100011011011010100110111001 step 39 100001100110100100011000000000000001111100011011011010100110111001 step 40 100001100110100100011010000000000001111100011011011010100110111001 step 41 100001100110100100011011000000000001111100011011011010100110111001 step 42 100001100110100100011011010000000001111100011011011010100110111001 step 43 100001100110100100011011011000000001111100011011011010100110111001 step 44 100001100110100100011011011010000001111100011011011010100110111001 step 45 100001100110100100011011011011000001111100011011011010100110111001 step 46 100001100110100100011011011011010001111100011011011010100110111001 step 47 100001100110100100011011011011011001111100011011011010100110111001 step 48 100001100110100100011011011011011101111100011011011010100110111001 step 49 110001100110100100011011011011011100110111011011011010100110111001 step 50 100001100110100100011011011011011101111100011011011010100110111001 step 51 101001100110100100011011011011011100110111011011011010100110111001 step 52 100001100110100100011011011011011101111100011011011010100110111001 step 53 100101100110100100011011011011011100110111011011011010100110111001 step 54 100001100110100100011011011011011101111100011011011010100110111001 step 55 100011100110100100011011011011011100110111011011011010100110111001 step 56 100001100110100100011011011011011101111100011011011010100110111001 step 57 100001110110100100011011011011011100110111011011011010100110111001 step 58 100001100110100100011011011011011101111100011011011010100110111001 step 59 100001101110100100011011011011011100110111011011011010100110111001 step 60 100001100110100100011011011011011101111100011011011010100110111001 step 61 100001100111100100011011011011011100111101011011011010100110111001 step 62 100001100110100100011011011011011101111100011011011010100110111001 step 63 100001100110110100011011011011011100111101011011011010100110111001 step 64 100001100110100100011011011011011101111100011011011010100110111001 step 65 100001100110101100011011011011011101110110011011011010100110111001 step 66 100001100110100100011011011011011101111100011011011010100110111001 step 67 100001100110100110011011011011011101110110011011011010100110111001 step 68 100001100110100100011011011011011101111100011011011010100110111001 step 69 100001100110100101011011011011011101001111011011011010100110111001 step 70 100001100110100100011011011011011101111100011011011010100110111001 step 71 100001100110100100111011011011011101001111011011011010100110111001 step 72 100001100110100100011011011011011101111100011011011010100110111001 step 73 100001100110100100011111011011011101001111011011011010100110111001 step 74 100001100110100100011011011011011101111100011011011010100110111001 step 75 100001100110100100011011111011011101001111011011011010100110111001 step 76 100001100110100100011011011011011101111100011011011010100110111001 step 77 100001100110100100011011011111011101001111011011011010100110111001 step 78 100001100110100100011011011011011101111100011011011010100110111001 step 79 100001100110100100011011011011111101001111011011011010100110111001 step 80 100001100110100100011011011011011101111100011011011010100110111001 step 81 100001100110100100011011011011011111101110011011011010100110111001 step 82 100001100110100100011011011011011101111100011011011010100110111001 test 26: pass SLOT BAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBAABBAAAAAAAAAAAAAABBBBBBBBAB LETTER ALPSLFMDEEMCBFRSPKLEMFHRSCJLJKUHPNMBBNNVVRKRHUTDJUKANJHBTPDFSVDEVU SIDE 121212122121212121111111112212122222112222111221112112212112212212 DIRECTION IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIOOOOOOOIOOIOOIOOIOOOOIOOIIOOIIO this fail all fails was hi 111111111111111111111111111111111111111111111111111111111111111 1 rising ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ ^^^^^^^^^^^^^^^^^^^^ ^^ falling vvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvv vvvvvvvvvvvvvvvvvvvv vv was lo 00000000000000000000000000000000000000 00000000000000000000 0000 total fails 0, total passes 26 step 1 100000000000000000000000000000000001111100011011011010100110111001 step 2 100000000000000000000000000000000001111100100011011010100110111001 step 3 100000000000000000000000000000000001111100000011011010100110111001 step 4 100000000000000000000000000000000001111100000100011010100110111001 step 5 100000000000000000000000000000000001111100000000011010100110111001 step 6 100000000000000000000000000000000001111100000000100010100110111001 step 7 100000000000000000000000000000000001111100000000000010100110111001 step 8 100000000000000000000000000000000001111100000000000101010110111001 step 9 100000000000000000000000000000000001111100000000000001010110111001 step 10 100000000000000000000000000000000001111100000000000001011000111001 step 11 100000000000000000000000000000000001111100000000000001010000111001 step 12 100000000000000000000000000000000001111100000000000001010001100001 step 13 100000000000000000000000000000000001111100000000000001010000100001 step 14 100000000000000000000000000000000001111100000000000001010000100001 step 15 100000000000010000000000000000000000111101000000000001010000100001 step 16 100000000000010010000000000000000000110111000000000001010000100001 step 17 100000000000010010000000000000000000110111111000000001010000100001 step 18 100000000000010010000000000000000000110111011000000001010000100001 step 19 100000000000010010000000000000000000110111011111000001010000100001 step 20 100000000000010010000000000000000000110111011011000001010000100001 step 21 100000000000010010000000000000000000110111011011111001010000100001 step 22 100000000000010010000000000000000000110111011011011001010000100001 step 23 100000000000010010000000000000000000110111011011011110100000100001 step 24 100000000000010010000000000000000000110111011011011010100000100001 step 25 100000000000010010000000000000000000110111011011011010101110100001 step 26 100000000000010010000000000000000000110111011011011010100110100001 step 27 100000000000010010000000000000000000110111011011011010100111111001 step 28 100000000000010010000000000000000000110111011011011010100110111001 step 29 100000000000000010000000000000000001110110011011011010100110111001 step 30 100000000000000000000000000000000001111100011011011010100110111001 step 31 100000000000000000000000000000000001111100011011011010100110111001 step 32 100001000000000000000000000000000001111100011011011010100110111001 step 33 100001100000000000000000000000000001111100011011011010100110111001 step 34 100001100100000000000000000000000001111100011011011010100110111001 step 35 100001100110000000000000000000000001111100011011011010100110111001 step 36 100001100110100000000000000000000001111100011011011010100110111001 step 37 100001100110100100000000000000000001111100011011011010100110111001 step 38 100001100110100100010000000000000001111100011011011010100110111001 step 39 100001100110100100011000000000000001111100011011011010100110111001 step 40 100001100110100100011010000000000001111100011011011010100110111001 step 41 100001100110100100011011000000000001111100011011011010100110111001 step 42 100001100110100100011011010000000001111100011011011010100110111001 step 43 100001100110100100011011011000000001111100011011011010100110111001 step 44 100001100110100100011011011010000001111100011011011010100110111001 step 45 100001100110100100011011011011000001111100011011011010100110111001 step 46 100001100110100100011011011011010001111100011011011010100110111001 step 47 100001100110100100011011011011011001111100011011011010100110111001 step 48 100001100110100100011011011011011101111100011011011010100110111001 step 49 110001100110100100011011011011011100110111011011011010100110111001 step 50 100001100110100100011011011011011101111100011011011010100110111001 step 51 101001100110100100011011011011011100110111011011011010100110111001 step 52 100001100110100100011011011011011101111100011011011010100110111001 step 53 100101100110100100011011011011011100110111011011011010100110111001 step 54 100001100110100100011011011011011101111100011011011010100110111001 step 55 100011100110100100011011011011011100110111011011011010100110111001 step 56 100001100110100100011011011011011101111100011011011010100110111001 step 57 100001110110100100011011011011011100110111011011011010100110111001 step 58 100001100110100100011011011011011101111100011011011010100110111001 step 59 100001101110100100011011011011011100110111011011011010100110111001 step 60 100001100110100100011011011011011101111100011011011010100110111001 step 61 100001100111100100011011011011011100111101011011011010100110111001 step 62 100001100110100100011011011011011101111100011011011010100110111001 step 63 100001100110110100011011011011011100111101011011011010100110111001 step 64 100001100110100100011011011011011101111100011011011010100110111001 step 65 100001100110101100011011011011011101110110011011011010100110111001 step 66 100001100110100100011011011011011101111100011011011010100110111001 step 67 100001100110100110011011011011011101110110011011011010100110111001 step 68 100001100110100100011011011011011101111100011011011010100110111001 step 69 100001100110100101011011011011011101001111011011011010100110111001 step 70 100001100110100100011011011011011101111100011011011010100110111001 step 71 100001100110100100111011011011011101001111011011011010100110111001 step 72 100001100110100100011011011011011101111100011011011010100110111001 step 73 100001100110100100011111011011011101001111011011011010100110111001 step 74 100001100110100100011011011011011101111100011011011010100110111001 step 75 100001100110100100011011111011011101001111011011011010100110111001 step 76 100001100110100100011011011011011101111100011011011010100110111001 step 77 100001100110100100011011011111011101001111011011011010100110111001 step 78 100001100110100100011011011011011101111100011011011010100110111001 step 79 100001100110100100011011011011111101001111011011011010100110111001 step 80 100001100110100100011011011011011101111100011011011010100110111001 step 81 100001100110100100011011011011011111101110011011011010100110111001 step 82 100001100110100100011011011011011101111100011011011010100110111001 test 27: pass SLOT BAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBAABBAAAAAAAAAAAAAABBBBBBBBAB LETTER ALPSLFMDEEMCBFRSPKLEMFHRSCJLJKUHPNMBBNNVVRKRHUTDJUKANJHBTPDFSVDEVU SIDE 121212122121212121111111112212122222112222111221112112212112212212 DIRECTION IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIOOOOOOOIOOIOOIOOIOOOOIOOIIOOIIO this fail all fails was hi 111111111111111111111111111111111111111111111111111111111111111 1 rising ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ ^^^^^^^^^^^^^^^^^^^^ ^^ falling vvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvv vvvvvvvvvvvvvvvvvvvv vv was lo 00000000000000000000000000000000000000 00000000000000000000 0000 total fails 0, total passes 27 step 1 100000000000000000000000000000000001111100011011011010100110111001 step 2 100000000000000000000000000000000001111100100011011010100110111001 step 3 100000000000000000000000000000000001111100000011011010100110111001 step 4 100000000000000000000000000000000001111100000100011010100110111001 step 5 100000000000000000000000000000000001111100000000011010100110111001 step 6 100000000000000000000000000000000001111100000000100010100110111001 step 7 100000000000000000000000000000000001111100000000000010100110111001 step 8 100000000000000000000000000000000001111100000000000101010110111001 step 9 100000000000000000000000000000000001111100000000000001010110111001 step 10 100000000000000000000000000000000001111100000000000001011000111001 step 11 100000000000000000000000000000000001111100000000000001010000111001 step 12 100000000000000000000000000000000001111100000000000001010001100001 step 13 100000000000000000000000000000000001111100000000000001010000100001 step 14 100000000000000000000000000000000001111100000000000001010000100001 step 15 100000000000010000000000000000000000111101000000000001010000100001 step 16 100000000000010010000000000000000000110111000000000001010000100001 step 17 100000000000010010000000000000000000110111111000000001010000100001 step 18 100000000000010010000000000000000000110111011000000001010000100001 step 19 100000000000010010000000000000000000110111011111000001010000100001 step 20 100000000000010010000000000000000000110111011011000001010000100001 step 21 100000000000010010000000000000000000110111011011111001010000100001 step 22 100000000000010010000000000000000000110111011011011001010000100001 step 23 100000000000010010000000000000000000110111011011011110100000100001 step 24 100000000000010010000000000000000000110111011011011010100000100001 step 25 100000000000010010000000000000000000110111011011011010101110100001 step 26 100000000000010010000000000000000000110111011011011010100110100001 step 27 100000000000010010000000000000000000110111011011011010100111111001 step 28 100000000000010010000000000000000000110111011011011010100110111001 step 29 100000000000000010000000000000000001110110011011011010100110111001 step 30 100000000000000000000000000000000001111100011011011010100110111001 step 31 100000000000000000000000000000000001111100011011011010100110111001 step 32 100001000000000000000000000000000001111100011011011010100110111001 step 33 100001100000000000000000000000000001111100011011011010100110111001 step 34 100001100100000000000000000000000001111100011011011010100110111001 step 35 100001100110000000000000000000000001111100011011011010100110111001 step 36 100001100110100000000000000000000001111100011011011010100110111001 step 37 100001100110100100000000000000000001111100011011011010100110111001 step 38 100001100110100100010000000000000001111100011011011010100110111001 step 39 100001100110100100011000000000000001111100011011011010100110111001 step 40 100001100110100100011010000000000001111100011011011010100110111001 step 41 100001100110100100011011000000000001111100011011011010100110111001 step 42 100001100110100100011011010000000001111100011011011010100110111001 step 43 100001100110100100011011011000000001111100011011011010100110111001 step 44 100001100110100100011011011010000001111100011011011010100110111001 step 45 100001100110100100011011011011000001111100011011011010100110111001 step 46 100001100110100100011011011011010001111100011011011010100110111001 step 47 100001100110100100011011011011011001111100011011011010100110111001 step 48 100001100110100100011011011011011101111100011011011010100110111001 step 49 110001100110100100011011011011011100110111011011011010100110111001 step 50 100001100110100100011011011011011101111100011011011010100110111001 step 51 101001100110100100011011011011011100110111011011011010100110111001 step 52 100001100110100100011011011011011101111100011011011010100110111001 step 53 100101100110100100011011011011011100110111011011011010100110111001 step 54 100001100110100100011011011011011101111100011011011010100110111001 step 55 100011100110100100011011011011011100110111011011011010100110111001 step 56 100001100110100100011011011011011101111100011011011010100110111001 step 57 100001110110100100011011011011011100110111011011011010100110111001 step 58 100001100110100100011011011011011101111100011011011010100110111001 step 59 100001101110100100011011011011011100110111011011011010100110111001 step 60 100001100110100100011011011011011101111100011011011010100110111001 step 61 100001100111100100011011011011011100111101011011011010100110111001 step 62 100001100110100100011011011011011101111100011011011010100110111001 step 63 100001100110110100011011011011011100111101011011011010100110111001 step 64 100001100110100100011011011011011101111100011011011010100110111001 step 65 100001100110101100011011011011011101110110011011011010100110111001 step 66 100001100110100100011011011011011101111100011011011010100110111001 step 67 100001100110100110011011011011011101110110011011011010100110111001 step 68 100001100110100100011011011011011101111100011011011010100110111001 step 69 100001100110100101011011011011011101001111011011011010100110111001 step 70 100001100110100100011011011011011101111100011011011010100110111001 step 71 100001100110100100111011011011011101001111011011011010100110111001 step 72 100001100110100100011011011011011101111100011011011010100110111001 step 73 100001100110100100011111011011011101001111011011011010100110111001 step 74 100001100110100100011011011011011101111100011011011010100110111001 step 75 100001100110100100011011111011011101001111011011011010100110111001 step 76 100001100110100100011011011011011101111100011011011010100110111001 step 77 100001100110100100011011011111011101001111011011011010100110111001 step 78 100001100110100100011011011011011101111100011011011010100110111001 step 79 100001100110100100011011011011111101001111011011011010100110111001 step 80 100001100110100100011011011011011101111100011011011010100110111001 step 81 100001100110100100011011011011011111101110011011011010100110111001 step 82 100001100110100100011011011011011101111100011011011010100110111001 test 28: pass SLOT BAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBAABBAAAAAAAAAAAAAABBBBBBBBAB LETTER ALPSLFMDEEMCBFRSPKLEMFHRSCJLJKUHPNMBBNNVVRKRHUTDJUKANJHBTPDFSVDEVU SIDE 121212122121212121111111112212122222112222111221112112212112212212 DIRECTION IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIOOOOOOOIOOIOOIOOIOOOOIOOIIOOIIO this fail all fails was hi 111111111111111111111111111111111111111111111111111111111111111 1 rising ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ ^^^^^^^^^^^^^^^^^^^^ ^^ falling vvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvv vvvvvvvvvvvvvvvvvvvv vv was lo 00000000000000000000000000000000000000 00000000000000000000 0000 total fails 0, total passes 28 step 1 100000000000000000000000000000000001111100011011011010100110111001 step 2 100000000000000000000000000000000001111100100011011010100110111001 step 3 100000000000000000000000000000000001111100000011011010100110111001 step 4 100000000000000000000000000000000001111100000100011010100110111001 step 5 100000000000000000000000000000000001111100000000011010100110111001 step 6 100000000000000000000000000000000001111100000000100010100110111001 step 7 100000000000000000000000000000000001111100000000000010100110111001 step 8 100000000000000000000000000000000001111100000000000101010110111001 step 9 100000000000000000000000000000000001111100000000000001010110111001 step 10 100000000000000000000000000000000001111100000000000001011000111001 step 11 100000000000000000000000000000000001111100000000000001010000111001 step 12 100000000000000000000000000000000001111100000000000001010001100001 step 13 100000000000000000000000000000000001111100000000000001010000100001 step 14 100000000000000000000000000000000001111100000000000001010000100001 step 15 100000000000010000000000000000000000111101000000000001010000100001 step 16 100000000000010010000000000000000000110111000000000001010000100001 step 17 100000000000010010000000000000000000110111111000000001010000100001 step 18 100000000000010010000000000000000000110111011000000001010000100001 step 19 100000000000010010000000000000000000110111011111000001010000100001 step 20 100000000000010010000000000000000000110111011011000001010000100001 step 21 100000000000010010000000000000000000110111011011111001010000100001 step 22 100000000000010010000000000000000000110111011011011001010000100001 step 23 100000000000010010000000000000000000110111011011011110100000100001 step 24 100000000000010010000000000000000000110111011011011010100000100001 step 25 100000000000010010000000000000000000110111011011011010101110100001 step 26 100000000000010010000000000000000000110111011011011010100110100001 step 27 100000000000010010000000000000000000110111011011011010100111111001 step 28 100000000000010010000000000000000000110111011011011010100110111001 step 29 100000000000000010000000000000000001110110011011011010100110111001 step 30 100000000000000000000000000000000001111100011011011010100110111001 step 31 100000000000000000000000000000000001111100011011011010100110111001 step 32 100001000000000000000000000000000001111100011011011010100110111001 step 33 100001100000000000000000000000000001111100011011011010100110111001 step 34 100001100100000000000000000000000001111100011011011010100110111001 step 35 100001100110000000000000000000000001111100011011011010100110111001 step 36 100001100110100000000000000000000001111100011011011010100110111001 step 37 100001100110100100000000000000000001111100011011011010100110111001 step 38 100001100110100100010000000000000001111100011011011010100110111001 step 39 100001100110100100011000000000000001111100011011011010100110111001 step 40 100001100110100100011010000000000001111100011011011010100110111001 step 41 100001100110100100011011000000000001111100011011011010100110111001 step 42 100001100110100100011011010000000001111100011011011010100110111001 step 43 100001100110100100011011011000000001111100011011011010100110111001 step 44 100001100110100100011011011010000001111100011011011010100110111001 step 45 100001100110100100011011011011000001111100011011011010100110111001 step 46 100001100110100100011011011011010001111100011011011010100110111001 step 47 100001100110100100011011011011011001111100011011011010100110111001 step 48 100001100110100100011011011011011101111100011011011010100110111001 step 49 110001100110100100011011011011011100110111011011011010100110111001 step 50 100001100110100100011011011011011101111100011011011010100110111001 step 51 101001100110100100011011011011011100110111011011011010100110111001 step 52 100001100110100100011011011011011101111100011011011010100110111001 step 53 100101100110100100011011011011011100110111011011011010100110111001 step 54 100001100110100100011011011011011101111100011011011010100110111001 step 55 100011100110100100011011011011011100110111011011011010100110111001 step 56 100001100110100100011011011011011101111100011011011010100110111001 step 57 100001110110100100011011011011011100110111011011011010100110111001 step 58 100001100110100100011011011011011101111100011011011010100110111001 step 59 100001101110100100011011011011011100110111011011011010100110111001 step 60 100001100110100100011011011011011101111100011011011010100110111001 step 61 100001100111100100011011011011011100111101011011011010100110111001 step 62 100001100110100100011011011011011101111100011011011010100110111001 step 63 100001100110110100011011011011011100111101011011011010100110111001 step 64 100001100110100100011011011011011101111100011011011010100110111001 step 65 100001100110101100011011011011011101110110011011011010100110111001 step 66 100001100110100100011011011011011101111100011011011010100110111001 step 67 100001100110100110011011011011011101110110011011011010100110111001 step 68 100001100110100100011011011011011101111100011011011010100110111001 step 69 100001100110100101011011011011011101001111011011011010100110111001 step 70 100001100110100100011011011011011101111100011011011010100110111001 step 71 100001100110100100111011011011011101001111011011011010100110111001 step 72 100001100110100100011011011011011101111100011011011010100110111001 step 73 100001100110100100011111011011011101001111011011011010100110111001 step 74 100001100110100100011011011011011101111100011011011010100110111001 step 75 100001100110100100011011111011011101001111011011011010100110111001 step 76 100001100110100100011011011011011101111100011011011010100110111001 step 77 100001100110100100011011011111011101001111011011011010100110111001 step 78 100001100110100100011011011011011101111100011011011010100110111001 step 79 100001100110100100011011011011111101001111011011011010100110111001 step 80 100001100110100100011011011011011101111100011011011010100110111001 step 81 100001100110100100011011011011011111101110011011011010100110111001 step 82 100001100110100100011011011011011101111100011011011010100110111001 test 29: pass SLOT BAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBAABBAAAAAAAAAAAAAABBBBBBBBAB LETTER ALPSLFMDEEMCBFRSPKLEMFHRSCJLJKUHPNMBBNNVVRKRHUTDJUKANJHBTPDFSVDEVU SIDE 121212122121212121111111112212122222112222111221112112212112212212 DIRECTION IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIOOOOOOOIOOIOOIOOIOOOOIOOIIOOIIO this fail all fails was hi 111111111111111111111111111111111111111111111111111111111111111 1 rising ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ ^^^^^^^^^^^^^^^^^^^^ ^^ falling vvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvv vvvvvvvvvvvvvvvvvvvv vv was lo 00000000000000000000000000000000000000 00000000000000000000 0000 total fails 0, total passes 29 step 1 100000000000000000000000000000000001111100011011011010100110111001 step 2 100000000000000000000000000000000001111100100011011010100110111001 step 3 100000000000000000000000000000000001111100000011011010100110111001 step 4 100000000000000000000000000000000001111100000100011010100110111001 step 5 100000000000000000000000000000000001111100000000011010100110111001 step 6 100000000000000000000000000000000001111100000000100010100110111001 step 7 100000000000000000000000000000000001111100000000000010100110111001 step 8 100000000000000000000000000000000001111100000000000101010110111001 step 9 100000000000000000000000000000000001111100000000000001010110111001 step 10 100000000000000000000000000000000001111100000000000001011000111001 step 11 100000000000000000000000000000000001111100000000000001010000111001 step 12 100000000000000000000000000000000001111100000000000001010001100001 step 13 100000000000000000000000000000000001111100000000000001010000100001 step 14 100000000000000000000000000000000001111100000000000001010000100001 step 15 100000000000010000000000000000000000111101000000000001010000100001 step 16 100000000000010010000000000000000000110111000000000001010000100001 step 17 100000000000010010000000000000000000110111111000000001010000100001 step 18 100000000000010010000000000000000000110111011000000001010000100001 step 19 100000000000010010000000000000000000110111011111000001010000100001 step 20 100000000000010010000000000000000000110111011011000001010000100001 step 21 100000000000010010000000000000000000110111011011111001010000100001 step 22 100000000000010010000000000000000000110111011011011001010000100001 step 23 100000000000010010000000000000000000110111011011011110100000100001 step 24 100000000000010010000000000000000000110111011011011010100000100001 step 25 100000000000010010000000000000000000110111011011011010101110100001 step 26 100000000000010010000000000000000000110111011011011010100110100001 step 27 100000000000010010000000000000000000110111011011011010100111111001 step 28 100000000000010010000000000000000000110111011011011010100110111001 step 29 100000000000000010000000000000000001110110011011011010100110111001 step 30 100000000000000000000000000000000001111100011011011010100110111001 step 31 100000000000000000000000000000000001111100011011011010100110111001 step 32 100001000000000000000000000000000001111100011011011010100110111001 step 33 100001100000000000000000000000000001111100011011011010100110111001 step 34 100001100100000000000000000000000001111100011011011010100110111001 step 35 100001100110000000000000000000000001111100011011011010100110111001 step 36 100001100110100000000000000000000001111100011011011010100110111001 step 37 100001100110100100000000000000000001111100011011011010100110111001 step 38 100001100110100100010000000000000001111100011011011010100110111001 step 39 100001100110100100011000000000000001111100011011011010100110111001 step 40 100001100110100100011010000000000001111100011011011010100110111001 step 41 100001100110100100011011000000000001111100011011011010100110111001 step 42 100001100110100100011011010000000001111100011011011010100110111001 step 43 100001100110100100011011011000000001111100011011011010100110111001 step 44 100001100110100100011011011010000001111100011011011010100110111001 step 45 100001100110100100011011011011000001111100011011011010100110111001 step 46 100001100110100100011011011011010001111100011011011010100110111001 step 47 100001100110100100011011011011011001111100011011011010100110111001 step 48 100001100110100100011011011011011101111100011011011010100110111001 step 49 110001100110100100011011011011011100110111011011011010100110111001 step 50 100001100110100100011011011011011101111100011011011010100110111001 step 51 101001100110100100011011011011011100110111011011011010100110111001 step 52 100001100110100100011011011011011101111100011011011010100110111001 step 53 100101100110100100011011011011011100110111011011011010100110111001 step 54 100001100110100100011011011011011101111100011011011010100110111001 step 55 100011100110100100011011011011011100110111011011011010100110111001 step 56 100001100110100100011011011011011101111100011011011010100110111001 step 57 100001110110100100011011011011011100110111011011011010100110111001 step 58 100001100110100100011011011011011101111100011011011010100110111001 step 59 100001101110100100011011011011011100110111011011011010100110111001 step 60 100001100110100100011011011011011101111100011011011010100110111001 step 61 100001100111100100011011011011011100111101011011011010100110111001 step 62 100001100110100100011011011011011101111100011011011010100110111001 step 63 100001100110110100011011011011011100111101011011011010100110111001 step 64 100001100110100100011011011011011101111100011011011010100110111001 step 65 100001100110101100011011011011011101110110011011011010100110111001 step 66 100001100110100100011011011011011101111100011011011010100110111001 step 67 100001100110100110011011011011011101110110011011011010100110111001 step 68 100001100110100100011011011011011101111100011011011010100110111001 step 69 100001100110100101011011011011011101001111011011011010100110111001 step 70 100001100110100100011011011011011101111100011011011010100110111001 step 71 100001100110100100111011011011011101001111011011011010100110111001 step 72 100001100110100100011011011011011101111100011011011010100110111001 step 73 100001100110100100011111011011011101001111011011011010100110111001 step 74 100001100110100100011011011011011101111100011011011010100110111001 step 75 100001100110100100011011111011011101001111011011011010100110111001 step 76 100001100110100100011011011011011101111100011011011010100110111001 step 77 100001100110100100011011011111011101001111011011011010100110111001 step 78 100001100110100100011011011011011101111100011011011010100110111001 step 79 100001100110100100011011011011111101001111011011011010100110111001 step 80 100001100110100100011011011011011101111100011011011010100110111001 step 81 100001100110100100011011011011011111101110011011011010100110111001 step 82 100001100110100100011011011011011101111100011011011010100110111001 test 30: pass SLOT BAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBAABBAAAAAAAAAAAAAABBBBBBBBAB LETTER ALPSLFMDEEMCBFRSPKLEMFHRSCJLJKUHPNMBBNNVVRKRHUTDJUKANJHBTPDFSVDEVU SIDE 121212122121212121111111112212122222112222111221112112212112212212 DIRECTION IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIOOOOOOOIOOIOOIOOIOOOOIOOIIOOIIO this fail all fails was hi 111111111111111111111111111111111111111111111111111111111111111 1 rising ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ ^^^^^^^^^^^^^^^^^^^^ ^^ falling vvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvv vvvvvvvvvvvvvvvvvvvv vv was lo 00000000000000000000000000000000000000 00000000000000000000 0000 total fails 0, total passes 30 step 1 100000000000000000000000000000000001111100011011011010100110111001 step 2 100000000000000000000000000000000001111100100011011010100110111001 step 3 100000000000000000000000000000000001111100000011011010100110111001 step 4 100000000000000000000000000000000001111100000100011010100110111001 step 5 100000000000000000000000000000000001111100000000011010100110111001 step 6 100000000000000000000000000000000001111100000000100010100110111001 step 7 100000000000000000000000000000000001111100000000000010100110111001 step 8 100000000000000000000000000000000001111100000000000101010110111001 step 9 100000000000000000000000000000000001111100000000000001010110111001 step 10 100000000000000000000000000000000001111100000000000001011000111001 step 11 100000000000000000000000000000000001111100000000000001010000111001 step 12 100000000000000000000000000000000001111100000000000001010001100001 step 13 100000000000000000000000000000000001111100000000000001010000100001 step 14 100000000000000000000000000000000001111100000000000001010000100001 step 15 100000000000010000000000000000000000111101000000000001010000100001 step 16 100000000000010010000000000000000000110111000000000001010000100001 step 17 100000000000010010000000000000000000110111111000000001010000100001 step 18 100000000000010010000000000000000000110111011000000001010000100001 step 19 100000000000010010000000000000000000110111011111000001010000100001 step 20 100000000000010010000000000000000000110111011011000001010000100001 step 21 100000000000010010000000000000000000110111011011111001010000100001 step 22 100000000000010010000000000000000000110111011011011001010000100001 step 23 100000000000010010000000000000000000110111011011011110100000100001 step 24 100000000000010010000000000000000000110111011011011010100000100001 step 25 100000000000010010000000000000000000110111011011011010101110100001 step 26 100000000000010010000000000000000000110111011011011010100110100001 step 27 100000000000010010000000000000000000110111011011011010100111111001 step 28 100000000000010010000000000000000000110111011011011010100110111001 step 29 100000000000000010000000000000000001110110011011011010100110111001 step 30 100000000000000000000000000000000001111100011011011010100110111001 step 31 100000000000000000000000000000000001111100011011011010100110111001 step 32 100001000000000000000000000000000001111100011011011010100110111001 step 33 100001100000000000000000000000000001111100011011011010100110111001 step 34 100001100100000000000000000000000001111100011011011010100110111001 step 35 100001100110000000000000000000000001111100011011011010100110111001 step 36 100001100110100000000000000000000001111100011011011010100110111001 step 37 100001100110100100000000000000000001111100011011011010100110111001 step 38 100001100110100100010000000000000001111100011011011010100110111001 step 39 100001100110100100011000000000000001111100011011011010100110111001 step 40 100001100110100100011010000000000001111100011011011010100110111001 step 41 100001100110100100011011000000000001111100011011011010100110111001 step 42 100001100110100100011011010000000001111100011011011010100110111001 step 43 100001100110100100011011011000000001111100011011011010100110111001 step 44 100001100110100100011011011010000001111100011011011010100110111001 step 45 100001100110100100011011011011000001111100011011011010100110111001 step 46 100001100110100100011011011011010001111100011011011010100110111001 step 47 100001100110100100011011011011011001111100011011011010100110111001 step 48 100001100110100100011011011011011101111100011011011010100110111001 step 49 110001100110100100011011011011011100110111011011011010100110111001 step 50 100001100110100100011011011011011101111100011011011010100110111001 step 51 101001100110100100011011011011011100110111011011011010100110111001 step 52 100001100110100100011011011011011101111100011011011010100110111001 step 53 100101100110100100011011011011011100110111011011011010100110111001 step 54 100001100110100100011011011011011101111100011011011010100110111001 step 55 100011100110100100011011011011011100110111011011011010100110111001 step 56 100001100110100100011011011011011101111100011011011010100110111001 step 57 100001110110100100011011011011011100110111011011011010100110111001 step 58 100001100110100100011011011011011101111100011011011010100110111001 step 59 100001101110100100011011011011011100110111011011011010100110111001 step 60 100001100110100100011011011011011101111100011011011010100110111001 step 61 100001100111100100011011011011011100111101011011011010100110111001 step 62 100001100110100100011011011011011101111100011011011010100110111001 step 63 100001100110110100011011011011011100111101011011011010100110111001 step 64 100001100110100100011011011011011101111100011011011010100110111001 step 65 100001100110101100011011011011011101110110011011011010100110111001 step 66 100001100110100100011011011011011101111100011011011010100110111001 step 67 100001100110100110011011011011011101110110011011011010100110111001 step 68 100001100110100100011011011011011101111100011011011010100110111001 step 69 100001100110100101011011011011011101001111011011011010100110111001 step 70 100001100110100100011011011011011101111100011011011010100110111001 step 71 100001100110100100111011011011011101001111011011011010100110111001 step 72 100001100110100100011011011011011101111100011011011010100110111001 step 73 100001100110100100011111011011011101001111011011011010100110111001 step 74 100001100110100100011011011011011101111100011011011010100110111001 step 75 100001100110100100011011111011011101001111011011011010100110111001 step 76 100001100110100100011011011011011101111100011011011010100110111001 step 77 100001100110100100011011011111011101001111011011011010100110111001 step 78 100001100110100100011011011011011101111100011011011010100110111001 step 79 100001100110100100011011011011111101001111011011011010100110111001 step 80 100001100110100100011011011011011101111100011011011010100110111001 step 81 100001100110100100011011011011011111101110011011011010100110111001 step 82 100001100110100100011011011011011101111100011011011010100110111001 test 31: pass SLOT BAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBAABBAAAAAAAAAAAAAABBBBBBBBAB LETTER ALPSLFMDEEMCBFRSPKLEMFHRSCJLJKUHPNMBBNNVVRKRHUTDJUKANJHBTPDFSVDEVU SIDE 121212122121212121111111112212122222112222111221112112212112212212 DIRECTION IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIOOOOOOOIOOIOOIOOIOOOOIOOIIOOIIO this fail all fails was hi 111111111111111111111111111111111111111111111111111111111111111 1 rising ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ ^^^^^^^^^^^^^^^^^^^^ ^^ falling vvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvv vvvvvvvvvvvvvvvvvvvv vv was lo 00000000000000000000000000000000000000 00000000000000000000 0000 total fails 0, total passes 31 step 1 100000000000000000000000000000000001111100011011011010100110111001 step 2 100000000000000000000000000000000001111100100011011010100110111001 step 3 100000000000000000000000000000000001111100000011011010100110111001 step 4 100000000000000000000000000000000001111100000100011010100110111001 step 5 100000000000000000000000000000000001111100000000011010100110111001 step 6 100000000000000000000000000000000001111100000000100010100110111001 step 7 100000000000000000000000000000000001111100000000000010100110111001 step 8 100000000000000000000000000000000001111100000000000101010110111001 step 9 100000000000000000000000000000000001111100000000000001010110111001 step 10 100000000000000000000000000000000001111100000000000001011000111001 step 11 100000000000000000000000000000000001111100000000000001010000111001 step 12 100000000000000000000000000000000001111100000000000001010001100001 step 13 100000000000000000000000000000000001111100000000000001010000100001 step 14 100000000000000000000000000000000001111100000000000001010000100001 step 15 100000000000010000000000000000000000111101000000000001010000100001 step 16 100000000000010010000000000000000000110111000000000001010000100001 step 17 100000000000010010000000000000000000110111111000000001010000100001 step 18 100000000000010010000000000000000000110111011000000001010000100001 step 19 100000000000010010000000000000000000110111011111000001010000100001 step 20 100000000000010010000000000000000000110111011011000001010000100001 step 21 100000000000010010000000000000000000110111011011111001010000100001 step 22 100000000000010010000000000000000000110111011011011001010000100001 step 23 100000000000010010000000000000000000110111011011011110100000100001 step 24 100000000000010010000000000000000000110111011011011010100000100001 step 25 100000000000010010000000000000000000110111011011011010101110100001 step 26 100000000000010010000000000000000000110111011011011010100110100001 step 27 100000000000010010000000000000000000110111011011011010100111111001 step 28 100000000000010010000000000000000000110111011011011010100110111001 step 29 100000000000000010000000000000000001110110011011011010100110111001 step 30 100000000000000000000000000000000001111100011011011010100110111001 step 31 100000000000000000000000000000000001111100011011011010100110111001 step 32 100001000000000000000000000000000001111100011011011010100110111001 step 33 100001100000000000000000000000000001111100011011011010100110111001 step 34 100001100100000000000000000000000001111100011011011010100110111001 step 35 100001100110000000000000000000000001111100011011011010100110111001 step 36 100001100110100000000000000000000001111100011011011010100110111001 step 37 100001100110100100000000000000000001111100011011011010100110111001 step 38 100001100110100100010000000000000001111100011011011010100110111001 step 39 100001100110100100011000000000000001111100011011011010100110111001 step 40 100001100110100100011010000000000001111100011011011010100110111001 step 41 100001100110100100011011000000000001111100011011011010100110111001 step 42 100001100110100100011011010000000001111100011011011010100110111001 step 43 100001100110100100011011011000000001111100011011011010100110111001 step 44 100001100110100100011011011010000001111100011011011010100110111001 step 45 100001100110100100011011011011000001111100011011011010100110111001 step 46 100001100110100100011011011011010001111100011011011010100110111001 step 47 100001100110100100011011011011011001111100011011011010100110111001 step 48 100001100110100100011011011011011101111100011011011010100110111001 step 49 110001100110100100011011011011011100110111011011011010100110111001 step 50 100001100110100100011011011011011101111100011011011010100110111001 step 51 101001100110100100011011011011011100110111011011011010100110111001 step 52 100001100110100100011011011011011101111100011011011010100110111001 step 53 100101100110100100011011011011011100110111011011011010100110111001 step 54 100001100110100100011011011011011101111100011011011010100110111001 step 55 100011100110100100011011011011011100110111011011011010100110111001 step 56 100001100110100100011011011011011101111100011011011010100110111001 step 57 100001110110100100011011011011011100110111011011011010100110111001 step 58 100001100110100100011011011011011101111100011011011010100110111001 step 59 100001101110100100011011011011011100110111011011011010100110111001 step 60 100001100110100100011011011011011101111100011011011010100110111001 step 61 100001100111100100011011011011011100111101011011011010100110111001 step 62 100001100110100100011011011011011101111100011011011010100110111001 step 63 100001100110110100011011011011011100111101011011011010100110111001 step 64 100001100110100100011011011011011101111100011011011010100110111001 step 65 100001100110101100011011011011011101110110011011011010100110111001 step 66 100001100110100100011011011011011101111100011011011010100110111001 step 67 100001100110100110011011011011011101110110011011011010100110111001 step 68 100001100110100100011011011011011101111100011011011010100110111001 step 69 100001100110100101011011011011011101001111011011011010100110111001 step 70 100001100110100100011011011011011101111100011011011010100110111001 step 71 100001100110100100111011011011011101001111011011011010100110111001 step 72 100001100110100100011011011011011101111100011011011010100110111001 step 73 100001100110100100011111011011011101001111011011011010100110111001 step 74 100001100110100100011011011011011101111100011011011010100110111001 step 75 100001100110100100011011111011011101001111011011011010100110111001 step 76 100001100110100100011011011011011101111100011011011010100110111001 step 77 100001100110100100011011011111011101001111011011011010100110111001 step 78 100001100110100100011011011011011101111100011011011010100110111001 step 79 100001100110100100011011011011111101001111011011011010100110111001 step 80 100001100110100100011011011011011101111100011011011010100110111001 step 81 100001100110100100011011011011011111101110011011011010100110111001 step 82 100001100110100100011011011011011101111100011011011010100110111001 test 32: pass SLOT BAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBAABBAAAAAAAAAAAAAABBBBBBBBAB LETTER ALPSLFMDEEMCBFRSPKLEMFHRSCJLJKUHPNMBBNNVVRKRHUTDJUKANJHBTPDFSVDEVU SIDE 121212122121212121111111112212122222112222111221112112212112212212 DIRECTION IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIOOOOOOOIOOIOOIOOIOOOOIOOIIOOIIO this fail all fails was hi 111111111111111111111111111111111111111111111111111111111111111 1 rising ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ ^^^^^^^^^^^^^^^^^^^^ ^^ falling vvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvv vvvvvvvvvvvvvvvvvvvv vv was lo 00000000000000000000000000000000000000 00000000000000000000 0000 total fails 0, total passes 32 step 1 100000000000000000000000000000000001111100011011011010100110111001 step 2 100000000000000000000000000000000001111100100011011010100110111001 step 3 100000000000000000000000000000000001111100000011011010100110111001 step 4 100000000000000000000000000000000001111100000100011010100110111001 step 5 100000000000000000000000000000000001111100000000011010100110111001 step 6 100000000000000000000000000000000001111100000000100010100110111001 step 7 100000000000000000000000000000000001111100000000000010100110111001 step 8 100000000000000000000000000000000001111100000000000101010110111001 step 9 100000000000000000000000000000000001111100000000000001010110111001 step 10 100000000000000000000000000000000001111100000000000001011000111001 step 11 100000000000000000000000000000000001111100000000000001010000111001 step 12 100000000000000000000000000000000001111100000000000001010001100001 step 13 100000000000000000000000000000000001111100000000000001010000100001 step 14 100000000000000000000000000000000001111100000000000001010000100001 step 15 100000000000010000000000000000000000111101000000000001010000100001 step 16 100000000000010010000000000000000000110111000000000001010000100001 step 17 100000000000010010000000000000000000110111111000000001010000100001 step 18 100000000000010010000000000000000000110111011000000001010000100001 step 19 100000000000010010000000000000000000110111011111000001010000100001 step 20 100000000000010010000000000000000000110111011011000001010000100001 step 21 100000000000010010000000000000000000110111011011111001010000100001 step 22 100000000000010010000000000000000000110111011011011001010000100001 step 23 100000000000010010000000000000000000110111011011011110100000100001 step 24 100000000000010010000000000000000000110111011011011010100000100001 step 25 100000000000010010000000000000000000110111011011011010101110100001 step 26 100000000000010010000000000000000000110111011011011010100110100001 step 27 100000000000010010000000000000000000110111011011011010100111111001 step 28 100000000000010010000000000000000000110111011011011010100110111001 step 29 100000000000000010000000000000000001110110011011011010100110111001 step 30 100000000000000000000000000000000001111100011011011010100110111001 step 31 100000000000000000000000000000000001111100011011011010100110111001 step 32 100001000000000000000000000000000001111100011011011010100110111001 step 33 100001100000000000000000000000000001111100011011011010100110111001 step 34 100001100100000000000000000000000001111100011011011010100110111001 step 35 100001100110000000000000000000000001111100011011011010100110111001 step 36 100001100110100000000000000000000001111100011011011010100110111001 step 37 100001100110100100000000000000000001111100011011011010100110111001 step 38 100001100110100100010000000000000001111100011011011010100110111001 step 39 100001100110100100011000000000000001111100011011011010100110111001 step 40 100001100110100100011010000000000001111100011011011010100110111001 step 41 100001100110100100011011000000000001111100011011011010100110111001 step 42 100001100110100100011011010000000001111100011011011010100110111001 step 43 100001100110100100011011011000000001111100011011011010100110111001 step 44 100001100110100100011011011010000001111100011011011010100110111001 step 45 100001100110100100011011011011000001111100011011011010100110111001 step 46 100001100110100100011011011011010001111100011011011010100110111001 step 47 100001100110100100011011011011011001111100011011011010100110111001 step 48 100001100110100100011011011011011101111100011011011010100110111001 step 49 110001100110100100011011011011011100110111011011011010100110111001 step 50 100001100110100100011011011011011101111100011011011010100110111001 step 51 101001100110100100011011011011011100110111011011011010100110111001 step 52 100001100110100100011011011011011101111100011011011010100110111001 step 53 100101100110100100011011011011011100110111011011011010100110111001 step 54 100001100110100100011011011011011101111100011011011010100110111001 step 55 100011100110100100011011011011011100110111011011011010100110111001 step 56 100001100110100100011011011011011101111100011011011010100110111001 step 57 100001110110100100011011011011011100110111011011011010100110111001 step 58 100001100110100100011011011011011101111100011011011010100110111001 step 59 100001101110100100011011011011011100110111011011011010100110111001 step 60 100001100110100100011011011011011101111100011011011010100110111001 step 61 100001100111100100011011011011011100111101011011011010100110111001 step 62 100001100110100100011011011011011101111100011011011010100110111001 step 63 100001100110110100011011011011011100111101011011011010100110111001 step 64 100001100110100100011011011011011101111100011011011010100110111001 step 65 100001100110101100011011011011011101110110011011011010100110111001 step 66 100001100110100100011011011011011101111100011011011010100110111001 step 67 100001100110100110011011011011011101110110011011011010100110111001 step 68 100001100110100100011011011011011101111100011011011010100110111001 step 69 100001100110100101011011011011011101001111011011011010100110111001 step 70 100001100110100100011011011011011101111100011011011010100110111001 step 71 100001100110100100111011011011011101001111011011011010100110111001 step 72 100001100110100100011011011011011101111100011011011010100110111001 step 73 100001100110100100011111011011011101001111011011011010100110111001 step 74 100001100110100100011011011011011101111100011011011010100110111001 step 75 100001100110100100011011111011011101001111011011011010100110111001 step 76 100001100110100100011011011011011101111100011011011010100110111001 step 77 100001100110100100011011011111011101001111011011011010100110111001 step 78 100001100110100100011011011011011101111100011011011010100110111001 step 79 100001100110100100011011011011111101001111011011011010100110111001 step 80 100001100110100100011011011011011101111100011011011010100110111001 step 81 100001100110100100011011011011011111101110011011011010100110111001 step 82 100001100110100100011011011011011101111100011011011010100110111001 test 33: pass SLOT BAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBAABBAAAAAAAAAAAAAABBBBBBBBAB LETTER ALPSLFMDEEMCBFRSPKLEMFHRSCJLJKUHPNMBBNNVVRKRHUTDJUKANJHBTPDFSVDEVU SIDE 121212122121212121111111112212122222112222111221112112212112212212 DIRECTION IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIOOOOOOOIOOIOOIOOIOOOOIOOIIOOIIO this fail all fails was hi 111111111111111111111111111111111111111111111111111111111111111 1 rising ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ ^^^^^^^^^^^^^^^^^^^^ ^^ falling vvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvv vvvvvvvvvvvvvvvvvvvv vv was lo 00000000000000000000000000000000000000 00000000000000000000 0000 total fails 0, total passes 33 step 1 100000000000000000000000000000000001111100011011011010100110111001 step 2 100000000000000000000000000000000001111100100011011010100110111001 step 3 100000000000000000000000000000000001111100000011011010100110111001 step 4 100000000000000000000000000000000001111100000100011010100110111001 step 5 100000000000000000000000000000000001111100000000011010100110111001 step 6 100000000000000000000000000000000001111100000000100010100110111001 step 7 100000000000000000000000000000000001111100000000000010100110111001 step 8 100000000000000000000000000000000001111100000000000101010110111001 step 9 100000000000000000000000000000000001111100000000000001010110111001 step 10 100000000000000000000000000000000001111100000000000001011000111001 step 11 100000000000000000000000000000000001111100000000000001010000111001 step 12 100000000000000000000000000000000001111100000000000001010001100001 step 13 100000000000000000000000000000000001111100000000000001010000100001 step 14 100000000000000000000000000000000001111100000000000001010000100001 step 15 100000000000010000000000000000000000111101000000000001010000100001 step 16 100000000000010010000000000000000000110111000000000001010000100001 step 17 100000000000010010000000000000000000110111111000000001010000100001 step 18 100000000000010010000000000000000000110111011000000001010000100001 step 19 100000000000010010000000000000000000110111011111000001010000100001 step 20 100000000000010010000000000000000000110111011011000001010000100001 step 21 100000000000010010000000000000000000110111011011111001010000100001 step 22 100000000000010010000000000000000000110111011011011001010000100001 step 23 100000000000010010000000000000000000110111011011011110100000100001 step 24 100000000000010010000000000000000000110111011011011010100000100001 step 25 100000000000010010000000000000000000110111011011011010101110100001 step 26 100000000000010010000000000000000000110111011011011010100110100001 step 27 100000000000010010000000000000000000110111011011011010100111111001 step 28 100000000000010010000000000000000000110111011011011010100110111001 step 29 100000000000000010000000000000000001110110011011011010100110111001 step 30 100000000000000000000000000000000001111100011011011010100110111001 step 31 100000000000000000000000000000000001111100011011011010100110111001 step 32 100001000000000000000000000000000001111100011011011010100110111001 step 33 100001100000000000000000000000000001111100011011011010100110111001 step 34 100001100100000000000000000000000001111100011011011010100110111001 step 35 100001100110000000000000000000000001111100011011011010100110111001 step 36 100001100110100000000000000000000001111100011011011010100110111001 step 37 100001100110100100000000000000000001111100011011011010100110111001 step 38 100001100110100100010000000000000001111100011011011010100110111001 step 39 100001100110100100011000000000000001111100011011011010100110111001 step 40 100001100110100100011010000000000001111100011011011010100110111001 step 41 100001100110100100011011000000000001111100011011011010100110111001 step 42 100001100110100100011011010000000001111100011011011010100110111001 step 43 100001100110100100011011011000000001111100011011011010100110111001 step 44 100001100110100100011011011010000001111100011011011010100110111001 step 45 100001100110100100011011011011000001111100011011011010100110111001 step 46 100001100110100100011011011011010001111100011011011010100110111001 step 47 100001100110100100011011011011011001111100011011011010100110111001 step 48 100001100110100100011011011011011101111100011011011010100110111001 step 49 110001100110100100011011011011011100110111011011011010100110111001 step 50 100001100110100100011011011011011101111100011011011010100110111001 step 51 101001100110100100011011011011011100110111011011011010100110111001 step 52 100001100110100100011011011011011101111100011011011010100110111001 step 53 100101100110100100011011011011011100110111011011011010100110111001 step 54 100001100110100100011011011011011101111100011011011010100110111001 step 55 100011100110100100011011011011011100110111011011011010100110111001 step 56 100001100110100100011011011011011101111100011011011010100110111001 step 57 100001110110100100011011011011011100110111011011011010100110111001 step 58 100001100110100100011011011011011101111100011011011010100110111001 step 59 100001101110100100011011011011011100110111011011011010100110111001 step 60 100001100110100100011011011011011101111100011011011010100110111001 step 61 100001100111100100011011011011011100111101011011011010100110111001 step 62 100001100110100100011011011011011101111100011011011010100110111001 step 63 100001100110110100011011011011011100111101011011011010100110111001 step 64 100001100110100100011011011011011101111100011011011010100110111001 step 65 100001100110101100011011011011011101110110011011011010100110111001 step 66 100001100110100100011011011011011101111100011011011010100110111001 step 67 100001100110100110011011011011011101110110011011011010100110111001 step 68 100001100110100100011011011011011101111100011011011010100110111001 step 69 100001100110100101011011011011011101001111011011011010100110111001 step 70 100001100110100100011011011011011101111100011011011010100110111001 step 71 100001100110100100111011011011011101001111011011011010100110111001 step 72 100001100110100100011011011011011101111100011011011010100110111001 step 73 100001100110100100011111011011011101001111011011011010100110111001 step 74 100001100110100100011011011011011101111100011011011010100110111001 step 75 100001100110100100011011111011011101001111011011011010100110111001 step 76 100001100110100100011011011011011101111100011011011010100110111001 step 77 100001100110100100011011011111011101001111011011011010100110111001 step 78 100001100110100100011011011011011101111100011011011010100110111001 step 79 100001100110100100011011011011111101001111011011011010100110111001 step 80 100001100110100100011011011011011101111100011011011010100110111001 step 81 100001100110100100011011011011011111101110011011011010100110111001 step 82 100001100110100100011011011011011101111100011011011010100110111001 test 34: pass SLOT BAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBAABBAAAAAAAAAAAAAABBBBBBBBAB LETTER ALPSLFMDEEMCBFRSPKLEMFHRSCJLJKUHPNMBBNNVVRKRHUTDJUKANJHBTPDFSVDEVU SIDE 121212122121212121111111112212122222112222111221112112212112212212 DIRECTION IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIOOOOOOOIOOIOOIOOIOOOOIOOIIOOIIO this fail all fails was hi 111111111111111111111111111111111111111111111111111111111111111 1 rising ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ ^^^^^^^^^^^^^^^^^^^^ ^^ falling vvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvv vvvvvvvvvvvvvvvvvvvv vv was lo 00000000000000000000000000000000000000 00000000000000000000 0000 total fails 0, total passes 34 step 1 100000000000000000000000000000000001111100011011011010100110111001 step 2 100000000000000000000000000000000001111100100011011010100110111001 step 3 100000000000000000000000000000000001111100000011011010100110111001 step 4 100000000000000000000000000000000001111100000100011010100110111001 step 5 100000000000000000000000000000000001111100000000011010100110111001 step 6 100000000000000000000000000000000001111100000000100010100110111001 step 7 100000000000000000000000000000000001111100000000000010100110111001 step 8 100000000000000000000000000000000001111100000000000101010110111001 step 9 100000000000000000000000000000000001111100000000000001010110111001 step 10 100000000000000000000000000000000001111100000000000001011000111001 step 11 100000000000000000000000000000000001111100000000000001010000111001 step 12 100000000000000000000000000000000001111100000000000001010001100001 step 13 100000000000000000000000000000000001111100000000000001010000100001 step 14 100000000000000000000000000000000001111100000000000001010000100001 step 15 100000000000010000000000000000000000111101000000000001010000100001 step 16 100000000000010010000000000000000000110111000000000001010000100001 step 17 100000000000010010000000000000000000110111111000000001010000100001 step 18 100000000000010010000000000000000000110111011000000001010000100001 step 19 100000000000010010000000000000000000110111011111000001010000100001 step 20 100000000000010010000000000000000000110111011011000001010000100001 step 21 100000000000010010000000000000000000110111011011111001010000100001 step 22 100000000000010010000000000000000000110111011011011001010000100001 step 23 100000000000010010000000000000000000110111011011011110100000100001 step 24 100000000000010010000000000000000000110111011011011010100000100001 step 25 100000000000010010000000000000000000110111011011011010101110100001 step 26 100000000000010010000000000000000000110111011011011010100110100001 step 27 100000000000010010000000000000000000110111011011011010100111111001 step 28 100000000000010010000000000000000000110111011011011010100110111001 step 29 100000000000000010000000000000000001110110011011011010100110111001 step 30 100000000000000000000000000000000001111100011011011010100110111001 step 31 100000000000000000000000000000000001111100011011011010100110111001 step 32 100001000000000000000000000000000001111100011011011010100110111001 step 33 100001100000000000000000000000000001111100011011011010100110111001 step 34 100001100100000000000000000000000001111100011011011010100110111001 step 35 100001100110000000000000000000000001111100011011011010100110111001 step 36 100001100110100000000000000000000001111100011011011010100110111001 step 37 100001100110100100000000000000000001111100011011011010100110111001 step 38 100001100110100100010000000000000001111100011011011010100110111001 step 39 100001100110100100011000000000000001111100011011011010100110111001 step 40 100001100110100100011010000000000001111100011011011010100110111001 step 41 100001100110100100011011000000000001111100011011011010100110111001 step 42 100001100110100100011011010000000001111100011011011010100110111001 step 43 100001100110100100011011011000000001111100011011011010100110111001 step 44 100001100110100100011011011010000001111100011011011010100110111001 step 45 100001100110100100011011011011000001111100011011011010100110111001 step 46 100001100110100100011011011011010001111100011011011010100110111001 step 47 100001100110100100011011011011011001111100011011011010100110111001 step 48 100001100110100100011011011011011101111100011011011010100110111001 step 49 110001100110100100011011011011011100110111011011011010100110111001 step 50 100001100110100100011011011011011101111100011011011010100110111001 step 51 101001100110100100011011011011011100110111011011011010100110111001 step 52 100001100110100100011011011011011101111100011011011010100110111001 step 53 100101100110100100011011011011011100110111011011011010100110111001 step 54 100001100110100100011011011011011101111100011011011010100110111001 step 55 100011100110100100011011011011011100110111011011011010100110111001 step 56 100001100110100100011011011011011101111100011011011010100110111001 step 57 100001110110100100011011011011011100110111011011011010100110111001 step 58 100001100110100100011011011011011101111100011011011010100110111001 step 59 100001101110100100011011011011011100110111011011011010100110111001 step 60 100001100110100100011011011011011101111100011011011010100110111001 step 61 100001100111100100011011011011011100111101011011011010100110111001 step 62 100001100110100100011011011011011101111100011011011010100110111001 step 63 100001100110110100011011011011011100111101011011011010100110111001 step 64 100001100110100100011011011011011101111100011011011010100110111001 step 65 100001100110101100011011011011011101110110011011011010100110111001 step 66 100001100110100100011011011011011101111100011011011010100110111001 step 67 100001100110100110011011011011011101110110011011011010100110111001 step 68 100001100110100100011011011011011101111100011011011010100110111001 step 69 100001100110100101011011011011011101001111011011011010100110111001 step 70 100001100110100100011011011011011101111100011011011010100110111001 step 71 100001100110100100111011011011011101001111011011011010100110111001 step 72 100001100110100100011011011011011101111100011011011010100110111001 step 73 100001100110100100011111011011011101001111011011011010100110111001 step 74 100001100110100100011011011011011101111100011011011010100110111001 step 75 100001100110100100011011111011011101001111011011011010100110111001 step 76 100001100110100100011011011011011101111100011011011010100110111001 step 77 100001100110100100011011011111011101001111011011011010100110111001 step 78 100001100110100100011011011011011101111100011011011010100110111001 step 79 100001100110100100011011011011111101001111011011011010100110111001 step 80 100001100110100100011011011011011101111100011011011010100110111001 step 81 100001100110100100011011011011011111101110011011011010100110111001 step 82 100001100110100100011011011011011101111100011011011010100110111001 test 35: pass SLOT BAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBAABBAAAAAAAAAAAAAABBBBBBBBAB LETTER ALPSLFMDEEMCBFRSPKLEMFHRSCJLJKUHPNMBBNNVVRKRHUTDJUKANJHBTPDFSVDEVU SIDE 121212122121212121111111112212122222112222111221112112212112212212 DIRECTION IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIOOOOOOOIOOIOOIOOIOOOOIOOIIOOIIO this fail all fails was hi 111111111111111111111111111111111111111111111111111111111111111 1 rising ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ ^^^^^^^^^^^^^^^^^^^^ ^^ falling vvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvv vvvvvvvvvvvvvvvvvvvv vv was lo 00000000000000000000000000000000000000 00000000000000000000 0000 total fails 0, total passes 35 step 1 100000000000000000000000000000000001111100011011011010100110111001 step 2 100000000000000000000000000000000001111100100011011010100110111001 step 3 100000000000000000000000000000000001111100000011011010100110111001 step 4 100000000000000000000000000000000001111100000100011010100110111001 step 5 100000000000000000000000000000000001111100000000011010100110111001 step 6 100000000000000000000000000000000001111100000000100010100110111001 step 7 100000000000000000000000000000000001111100000000000010100110111001 step 8 100000000000000000000000000000000001111100000000000101010110111001 step 9 100000000000000000000000000000000001111100000000000001010110111001 step 10 100000000000000000000000000000000001111100000000000001011000111001 step 11 100000000000000000000000000000000001111100000000000001010000111001 step 12 100000000000000000000000000000000001111100000000000001010001100001 step 13 100000000000000000000000000000000001111100000000000001010000100001 step 14 100000000000000000000000000000000001111100000000000001010000100001 step 15 100000000000010000000000000000000000111101000000000001010000100001 step 16 100000000000010010000000000000000000110111000000000001010000100001 step 17 100000000000010010000000000000000000110111111000000001010000100001 step 18 100000000000010010000000000000000000110111011000000001010000100001 step 19 100000000000010010000000000000000000110111011111000001010000100001 step 20 100000000000010010000000000000000000110111011011000001010000100001 step 21 100000000000010010000000000000000000110111011011111001010000100001 step 22 100000000000010010000000000000000000110111011011011001010000100001 step 23 100000000000010010000000000000000000110111011011011110100000100001 step 24 100000000000010010000000000000000000110111011011011010100000100001 step 25 100000000000010010000000000000000000110111011011011010101110100001 step 26 100000000000010010000000000000000000110111011011011010100110100001 step 27 100000000000010010000000000000000000110111011011011010100111111001 step 28 100000000000010010000000000000000000110111011011011010100110111001 step 29 100000000000000010000000000000000001110110011011011010100110111001 step 30 100000000000000000000000000000000001111100011011011010100110111001 step 31 100000000000000000000000000000000001111100011011011010100110111001 step 32 100001000000000000000000000000000001111100011011011010100110111001 step 33 100001100000000000000000000000000001111100011011011010100110111001 step 34 100001100100000000000000000000000001111100011011011010100110111001 step 35 100001100110000000000000000000000001111100011011011010100110111001 step 36 100001100110100000000000000000000001111100011011011010100110111001 step 37 100001100110100100000000000000000001111100011011011010100110111001 step 38 100001100110100100010000000000000001111100011011011010100110111001 step 39 100001100110100100011000000000000001111100011011011010100110111001 step 40 100001100110100100011010000000000001111100011011011010100110111001 step 41 100001100110100100011011000000000001111100011011011010100110111001 step 42 100001100110100100011011010000000001111100011011011010100110111001 step 43 100001100110100100011011011000000001111100011011011010100110111001 step 44 100001100110100100011011011010000001111100011011011010100110111001 step 45 100001100110100100011011011011000001111100011011011010100110111001 step 46 100001100110100100011011011011010001111100011011011010100110111001 step 47 100001100110100100011011011011011001111100011011011010100110111001 step 48 100001100110100100011011011011011101111100011011011010100110111001 step 49 110001100110100100011011011011011100110111011011011010100110111001 step 50 100001100110100100011011011011011101111100011011011010100110111001 step 51 101001100110100100011011011011011100110111011011011010100110111001 step 52 100001100110100100011011011011011101111100011011011010100110111001 step 53 100101100110100100011011011011011100110111011011011010100110111001 step 54 100001100110100100011011011011011101111100011011011010100110111001 step 55 100011100110100100011011011011011100110111011011011010100110111001 step 56 100001100110100100011011011011011101111100011011011010100110111001 step 57 100001110110100100011011011011011100110111011011011010100110111001 step 58 100001100110100100011011011011011101111100011011011010100110111001 step 59 100001101110100100011011011011011100110111011011011010100110111001 step 60 100001100110100100011011011011011101111100011011011010100110111001 step 61 100001100111100100011011011011011100111101011011011010100110111001 step 62 100001100110100100011011011011011101111100011011011010100110111001 step 63 100001100110110100011011011011011100111101011011011010100110111001 step 64 100001100110100100011011011011011101111100011011011010100110111001 step 65 100001100110101100011011011011011101110110011011011010100110111001 step 66 100001100110100100011011011011011101111100011011011010100110111001 step 67 100001100110100110011011011011011101110110011011011010100110111001 step 68 100001100110100100011011011011011101111100011011011010100110111001 step 69 100001100110100101011011011011011101001111011011011010100110111001 step 70 100001100110100100011011011011011101111100011011011010100110111001 step 71 100001100110100100111011011011011101001111011011011010100110111001 step 72 100001100110100100011011011011011101111100011011011010100110111001 step 73 100001100110100100011111011011011101001111011011011010100110111001 step 74 100001100110100100011011011011011101111100011011011010100110111001 step 75 100001100110100100011011111011011101001111011011011010100110111001 step 76 100001100110100100011011011011011101111100011011011010100110111001 step 77 100001100110100100011011011111011101001111011011011010100110111001 step 78 100001100110100100011011011011011101111100011011011010100110111001 step 79 100001100110100100011011011011111101001111011011011010100110111001 step 80 100001100110100100011011011011011101111100011011011010100110111001 step 81 100001100110100100011011011011011111101110011011011010100110111001 step 82 100001100110100100011011011011011101111100011011011010100110111001 test 36: pass SLOT BAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBAABBAAAAAAAAAAAAAABBBBBBBBAB LETTER ALPSLFMDEEMCBFRSPKLEMFHRSCJLJKUHPNMBBNNVVRKRHUTDJUKANJHBTPDFSVDEVU SIDE 121212122121212121111111112212122222112222111221112112212112212212 DIRECTION IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIOOOOOOOIOOIOOIOOIOOOOIOOIIOOIIO this fail all fails was hi 111111111111111111111111111111111111111111111111111111111111111 1 rising ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ ^^^^^^^^^^^^^^^^^^^^ ^^ falling vvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvv vvvvvvvvvvvvvvvvvvvv vv was lo 00000000000000000000000000000000000000 00000000000000000000 0000 total fails 0, total passes 36 step 1 100000000000000000000000000000000001111100011011011010100110111001 step 2 100000000000000000000000000000000001111100100011011010100110111001 step 3 100000000000000000000000000000000001111100000011011010100110111001 step 4 100000000000000000000000000000000001111100000100011010100110111001 step 5 100000000000000000000000000000000001111100000000011010100110111001 step 6 100000000000000000000000000000000001111100000000100010100110111001 step 7 100000000000000000000000000000000001111100000000000010100110111001 step 8 100000000000000000000000000000000001111100000000000101010110111001 step 9 100000000000000000000000000000000001111100000000000001010110111001 step 10 100000000000000000000000000000000001111100000000000001011000111001 step 11 100000000000000000000000000000000001111100000000000001010000111001 step 12 100000000000000000000000000000000001111100000000000001010001100001 step 13 100000000000000000000000000000000001111100000000000001010000100001 step 14 100000000000000000000000000000000001111100000000000001010000100001 step 15 100000000000010000000000000000000000111101000000000001010000100001 step 16 100000000000010010000000000000000000110111000000000001010000100001 step 17 100000000000010010000000000000000000110111111000000001010000100001 step 18 100000000000010010000000000000000000110111011000000001010000100001 step 19 100000000000010010000000000000000000110111011111000001010000100001 step 20 100000000000010010000000000000000000110111011011000001010000100001 step 21 100000000000010010000000000000000000110111011011111001010000100001 step 22 100000000000010010000000000000000000110111011011011001010000100001 step 23 100000000000010010000000000000000000110111011011011110100000100001 step 24 100000000000010010000000000000000000110111011011011010100000100001 step 25 100000000000010010000000000000000000110111011011011010101110100001 step 26 100000000000010010000000000000000000110111011011011010100110100001 step 27 100000000000010010000000000000000000110111011011011010100111111001 step 28 100000000000010010000000000000000000110111011011011010100110111001 step 29 100000000000000010000000000000000001110110011011011010100110111001 step 30 100000000000000000000000000000000001111100011011011010100110111001 step 31 100000000000000000000000000000000001111100011011011010100110111001 step 32 100001000000000000000000000000000001111100011011011010100110111001 step 33 100001100000000000000000000000000001111100011011011010100110111001 step 34 100001100100000000000000000000000001111100011011011010100110111001 step 35 100001100110000000000000000000000001111100011011011010100110111001 step 36 100001100110100000000000000000000001111100011011011010100110111001 step 37 100001100110100100000000000000000001111100011011011010100110111001 step 38 100001100110100100010000000000000001111100011011011010100110111001 step 39 100001100110100100011000000000000001111100011011011010100110111001 step 40 100001100110100100011010000000000001111100011011011010100110111001 step 41 100001100110100100011011000000000001111100011011011010100110111001 step 42 100001100110100100011011010000000001111100011011011010100110111001 step 43 100001100110100100011011011000000001111100011011011010100110111001 step 44 100001100110100100011011011010000001111100011011011010100110111001 step 45 100001100110100100011011011011000001111100011011011010100110111001 step 46 100001100110100100011011011011010001111100011011011010100110111001 step 47 100001100110100100011011011011011001111100011011011010100110111001 step 48 100001100110100100011011011011011101111100011011011010100110111001 step 49 110001100110100100011011011011011100110111011011011010100110111001 step 50 100001100110100100011011011011011101111100011011011010100110111001 step 51 101001100110100100011011011011011100110111011011011010100110111001 step 52 100001100110100100011011011011011101111100011011011010100110111001 step 53 100101100110100100011011011011011100110111011011011010100110111001 step 54 100001100110100100011011011011011101111100011011011010100110111001 step 55 100011100110100100011011011011011100110111011011011010100110111001 step 56 100001100110100100011011011011011101111100011011011010100110111001 step 57 100001110110100100011011011011011100110111011011011010100110111001 step 58 100001100110100100011011011011011101111100011011011010100110111001 step 59 100001101110100100011011011011011100110111011011011010100110111001 step 60 100001100110100100011011011011011101111100011011011010100110111001 step 61 100001100111100100011011011011011100111101011011011010100110111001 step 62 100001100110100100011011011011011101111100011011011010100110111001 step 63 100001100110110100011011011011011100111101011011011010100110111001 step 64 100001100110100100011011011011011101111100011011011010100110111001 step 65 100001100110101100011011011011011101110110011011011010100110111001 step 66 100001100110100100011011011011011101111100011011011010100110111001 step 67 100001100110100110011011011011011101110110011011011010100110111001 step 68 100001100110100100011011011011011101111100011011011010100110111001 step 69 100001100110100101011011011011011101001111011011011010100110111001 step 70 100001100110100100011011011011011101111100011011011010100110111001 step 71 100001100110100100111011011011011101001111011011011010100110111001 step 72 100001100110100100011011011011011101111100011011011010100110111001 step 73 100001100110100100011111011011011101001111011011011010100110111001 step 74 100001100110100100011011011011011101111100011011011010100110111001 step 75 100001100110100100011011111011011101001111011011011010100110111001 step 76 100001100110100100011011011011011101111100011011011010100110111001 step 77 100001100110100100011011011111011101001111011011011010100110111001 step 78 100001100110100100011011011011011101111100011011011010100110111001 step 79 100001100110100100011011011011111101001111011011011010100110111001 step 80 100001100110100100011011011011011101111100011011011010100110111001 step 81 100001100110100100011011011011011111101110011011011010100110111001 step 82 100001100110100100011011011011011101111100011011011010100110111001 test 37: pass SLOT BAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBAABBAAAAAAAAAAAAAABBBBBBBBAB LETTER ALPSLFMDEEMCBFRSPKLEMFHRSCJLJKUHPNMBBNNVVRKRHUTDJUKANJHBTPDFSVDEVU SIDE 121212122121212121111111112212122222112222111221112112212112212212 DIRECTION IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIOOOOOOOIOOIOOIOOIOOOOIOOIIOOIIO this fail all fails was hi 111111111111111111111111111111111111111111111111111111111111111 1 rising ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ ^^^^^^^^^^^^^^^^^^^^ ^^ falling vvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvv vvvvvvvvvvvvvvvvvvvv vv was lo 00000000000000000000000000000000000000 00000000000000000000 0000 total fails 0, total passes 37 step 1 100000000000000000000000000000000001111100011011011010100110111001 step 2 100000000000000000000000000000000001111100100011011010100110111001 step 3 100000000000000000000000000000000001111100000011011010100110111001 step 4 100000000000000000000000000000000001111100000100011010100110111001 step 5 100000000000000000000000000000000001111100000000011010100110111001 step 6 100000000000000000000000000000000001111100000000100010100110111001 step 7 100000000000000000000000000000000001111100000000000010100110111001 step 8 100000000000000000000000000000000001111100000000000101010110111001 step 9 100000000000000000000000000000000001111100000000000001010110111001 step 10 100000000000000000000000000000000001111100000000000001011000111001 step 11 100000000000000000000000000000000001111100000000000001010000111001 step 12 100000000000000000000000000000000001111100000000000001010001100001 step 13 100000000000000000000000000000000001111100000000000001010000100001 step 14 100000000000000000000000000000000001111100000000000001010000100001 step 15 100000000000010000000000000000000000111101000000000001010000100001 step 16 100000000000010010000000000000000000110111000000000001010000100001 step 17 100000000000010010000000000000000000110111111000000001010000100001 step 18 100000000000010010000000000000000000110111011000000001010000100001 step 19 100000000000010010000000000000000000110111011111000001010000100001 step 20 100000000000010010000000000000000000110111011011000001010000100001 step 21 100000000000010010000000000000000000110111011011111001010000100001 step 22 100000000000010010000000000000000000110111011011011001010000100001 step 23 100000000000010010000000000000000000110111011011011110100000100001 step 24 100000000000010010000000000000000000110111011011011010100000100001 step 25 100000000000010010000000000000000000110111011011011010101110100001 step 26 100000000000010010000000000000000000110111011011011010100110100001 step 27 100000000000010010000000000000000000110111011011011010100111111001 step 28 100000000000010010000000000000000000110111011011011010100110111001 step 29 100000000000000010000000000000000001110110011011011010100110111001 step 30 100000000000000000000000000000000001111100011011011010100110111001 step 31 100000000000000000000000000000000001111100011011011010100110111001 step 32 100001000000000000000000000000000001111100011011011010100110111001 step 33 100001100000000000000000000000000001111100011011011010100110111001 step 34 100001100100000000000000000000000001111100011011011010100110111001 step 35 100001100110000000000000000000000001111100011011011010100110111001 step 36 100001100110100000000000000000000001111100011011011010100110111001 step 37 100001100110100100000000000000000001111100011011011010100110111001 step 38 100001100110100100010000000000000001111100011011011010100110111001 step 39 100001100110100100011000000000000001111100011011011010100110111001 step 40 100001100110100100011010000000000001111100011011011010100110111001 step 41 100001100110100100011011000000000001111100011011011010100110111001 step 42 100001100110100100011011010000000001111100011011011010100110111001 step 43 100001100110100100011011011000000001111100011011011010100110111001 step 44 100001100110100100011011011010000001111100011011011010100110111001 step 45 100001100110100100011011011011000001111100011011011010100110111001 step 46 100001100110100100011011011011010001111100011011011010100110111001 step 47 100001100110100100011011011011011001111100011011011010100110111001 step 48 100001100110100100011011011011011101111100011011011010100110111001 step 49 110001100110100100011011011011011100110111011011011010100110111001 step 50 100001100110100100011011011011011101111100011011011010100110111001 step 51 101001100110100100011011011011011100110111011011011010100110111001 step 52 100001100110100100011011011011011101111100011011011010100110111001 step 53 100101100110100100011011011011011100110111011011011010100110111001 step 54 100001100110100100011011011011011101111100011011011010100110111001 step 55 100011100110100100011011011011011100110111011011011010100110111001 step 56 100001100110100100011011011011011101111100011011011010100110111001 step 57 100001110110100100011011011011011100110111011011011010100110111001 step 58 100001100110100100011011011011011101111100011011011010100110111001 step 59 100001101110100100011011011011011100110111011011011010100110111001 step 60 100001100110100100011011011011011101111100011011011010100110111001 step 61 100001100111100100011011011011011100111101011011011010100110111001 step 62 100001100110100100011011011011011101111100011011011010100110111001 step 63 100001100110110100011011011011011100111101011011011010100110111001 step 64 100001100110100100011011011011011101111100011011011010100110111001 step 65 100001100110101100011011011011011101110110011011011010100110111001 step 66 100001100110100100011011011011011101111100011011011010100110111001 step 67 100001100110100110011011011011011101110110011011011010100110111001 step 68 100001100110100100011011011011011101111100011011011010100110111001 step 69 100001100110100101011011011011011101001111011011011010100110111001 step 70 100001100110100100011011011011011101111100011011011010100110111001 step 71 100001100110100100111011011011011101001111011011011010100110111001 step 72 100001100110100100011011011011011101111100011011011010100110111001 step 73 100001100110100100011111011011011101001111011011011010100110111001 step 74 100001100110100100011011011011011101111100011011011010100110111001 step 75 100001100110100100011011111011011101001111011011011010100110111001 step 76 100001100110100100011011011011011101111100011011011010100110111001 step 77 100001100110100100011011011111011101001111011011011010100110111001 step 78 100001100110100100011011011011011101111100011011011010100110111001 space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C toggle comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit scope (run, no print) ppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppp ppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppp ppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppp pppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppp space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C toggle comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT BAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBAABBAAAAAAAAAAAAAABBBBBBBBAB LETTER ALPSLFMDEEMCBFRSPKLEMFHRSCJLJKUHPNMBBNNVVRKRHUTDJUKANJHBTPDFSVDEVU SIDE 121212122121212121111111112212122222112222111221112112212112212212 DIRECTION IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIOOOOOOOIOOIOOIOOIOOOOIOOIIOOIIO all fails was lo 00000000000000000000000000000000000000 00000000000000000000 0000 falling vvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvv vvvvvvvvvvvvvvvvvvvv vv rising ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ ^^^^^^^^^^^^^^^^^^^^ ^^ was hi 111111111111111111111111111111111111111111111111111111111111111 1 total fails 0, total passes 350 Main menu Sat Jul 11 15:55:38 2015 test file is: tests\m222.new delay is: 0 trigger is: 1 1 read test file 2 set test delay 3 set test trigger 4 run test 5 output loading test 8 diags 9 exit UUT power is okay Sat Jul 11 15:55:41 2015 space single step O run once (one test, all steps) F run, stop on fail G go (run tests N run, stop on fail, no print S scope (run, no print) C toggle comment printout + increase speed (less delay) - decrease speed (more delay)(slower) Q quit test step 1 100000000000000000000000000000000001111100010011011010100110111001 step 2 100000000000000000000000000000000001111100100011011010100110111001 step 3 100000000000000000000000000000000001111100000011011010100110111001 step 4 100000000000000000000000000000000001111100000100011010100110111001 step 5 100000000000000000000000000000000001111100000000011010100110111001 step 6 100000000000000000000000000000000001111100000000100010100110111001 step 7 100000000000000000000000000000000001111100000000000010100110111001 step 8 100000000000000000000000000000000001111100000000000101010110111001 step 9 100000000000000000000000000000000001111100000000000001010110111001 step 10 100000000000000000000000000000000001111100000000000001011000111001 step 11 100000000000000000000000000000000001111100000000000001010000111001 step 12 100000000000000000000000000000000001111100000000000001010001100001 step 13 100000000000000000000000000000000001111100000000000001010000100001 step 14 100000000000000000000000000000000001111100000000000001010000100001 step 15 100000000000010000000000000000000000111101000000000001010000100001 step 16 100000000000010010000000000000000000110111000000000001010000100001 step 17 100000000000010010000000000000000000110111111000000001010000100001 step 18 100000000000010010000000000000000000110111011000000001010000100001 step 19 100000000000010010000000000000000000110111011111000001010000100001 step 20 100000000000010010000000000000000000110111011011000001010000100001 step 21 100000000000010010000000000000000000110111011011111001010000100001 step 22 100000000000010010000000000000000000110111011011011001010000100001 step 23 100000000000010010000000000000000000110111011011011110100000100001 step 24 100000000000010010000000000000000000110111011011011010100000100001 step 25 100000000000010010000000000000000000110111011011011010101110100001 step 26 100000000000010010000000000000000000110111011011011010100110100001 step 27 100000000000010010000000000000000000110111011011011010100111111001 step 28 100000000000010010000000000000000000110111011011011010100110111001 step 29 100000000000000010000000000000000001110110011011011010100110111001 step 30 100000000000000000000000000000000001111100011011011010100110111001 step 31 100000000000000000000000000000000001111100011011011010100110111001 step 32 100001000000000000000000000000000001111100011011011010100110111001 step 33 100001100000000000000000000000000001111100011011011010100110111001 step 34 100001100100000000000000000000000001111100011011011010100110111001 step 35 100001100110000000000000000000000001111100011011011010100110111001 step 36 100001100110100000000000000000000001111100011011011010100110111001 step 37 100001100110100100000000000000000001111100011011011010100110111001 step 38 100001100110100100010000000000000001111100011011011010100110111001 step 39 100001100110100100011000000000000001111100011011011010100110111001 step 40 100001100110100100011010000000000001111100011011011010100110111001 step 41 100001100110100100011011000000000001111100011011011010100110111001 step 42 100001100110100100011011010000000001111100011011011010100110111001 step 43 100001100110100100011011011000000001111100011011011010100110111001 step 44 100001100110100100011011011010000001111100011011011010100110111001 step 45 100001100110100100011011011011000001111100011011011010100110111001 step 46 100001100110100100011011011011010001111100011011011010100110111001 step 47 100001100110100100011011011011011001111100011011011010100110111001 step 48 100001100110100100011011011011011101111100011011011010100110111001 step 49 110001100110100100011011011011011100110111011011011010100110111001 step 50 100001100110100100011011011011011101111100011011011010100110111001 step 51 101001100110100100011011011011011100110111011011011010100110111001 step 52 100001100110100100011011011011011101111100011011011010100110111001 step 53 100101100110100100011011011011011100110111011011011010100110111001 step 54 100001100110100100011011011011011101111100011011011010100110111001 step 55 100011100110100100011011011011011100110111011011011010100110111001 step 56 100001100110100100011011011011011101111100011011011010100110111001 step 57 100001110110100100011011011011011100110111011011011010100110111001 step 58 100001100110100100011011011011011101111100011011011010100110111001 step 59 100001101110100100011011011011011100110111011011011010100110111001 step 60 100001100110100100011011011011011101111100011011011010100110111001 step 61 100001100111100100011011011011011100111101011011011010100110111001 step 62 100001100110100100011011011011011101111100011011011010100110111001 step 63 100001100110110100011011011011011100111101011011011010100110111001 step 64 100001100110100100011011011011011101111100011011011010100110111001 step 65 100001100110101100011011011011011101110110011011011010100110111001 step 66 100001100110100100011011011011011101111100011011011010100110111001 step 67 100001100110100110011011011011011101110110011011011010100110111001 step 68 100001100110100100011011011011011101111100011011011010100110111001 step 69 100001100110100101011011011011011101001111011011011010100110111001 step 70 100001100110100100011011011011011101111100011011011010100110111001 step 71 100001100110100100111011011011011101001111011011011010100110111001 step 72 100001100110100100011011011011011101111100011011011010100110111001 step 73 100001100110100100011111011011011101001111011011011010100110111001 step 74 100001100110100100011011011011011101111100011011011010100110111001 step 75 100001100110100100011011111011011101001111011011011010100110111001 step 76 100001100110100100011011011011011101111100011011011010100110111001 step 77 100001100110100100011011011111011101001111011011011010100110111001 step 78 100001100110100100011011011011011101111100011011011010100110111001 step 79 100001100110100100011011011011111101001111011011011010100110111001 step 80 100001100110100100011011011011011101111100011011011010100110111001 step 81 100001100110100100011011011011011111101110011011011010100110111001 step 82 100001100110100100011011011011011101111100011011011010100110111001 test 1: pass SLOT BAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBAABBAAAAAAAAAAAAAABBBBBBBBAB LETTER ALPSLFMDEEMCBFRSPKLEMFHRSCJLJKUHPNMBBNNVVRKRHUTDJUKANJHBTPDFSVDEVU SIDE 121212122121212121111111112212122222112222111221112112212112212212 DIRECTION IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIOOOOOOOIOOIOOIOOIOOOOIOOIIOOIIO this fail all fails was hi 111111111111111111111111111111111111111111111111111111111111111 1 rising ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ ^^^^^^^^^^^^^^^^^^^^ ^^ falling vvvv vv v vv vvv v v v v vvvvv vvvv vvvvvvvvvvvvvvv vv was lo 00000000000000000000000000000000000000 00000000000000000000 0000 total fails 0, total passes 1 step 1 100000000000000000000000000000000001111100011011011010100110111001 step 2 100000000000000000000000000000000001111100100011011010100110111001 step 3 100000000000000000000000000000000001111100000011011010100110111001 step 4 100000000000000000000000000000000001111100000100011010100110111001 step 5 100000000000000000000000000000000001111100000000011010100110111001 step 6 100000000000000000000000000000000001111100000000100010100110111001 step 7 100000000000000000000000000000000001111100000000000010100110111001 step 8 100000000000000000000000000000000001111100000000000101010110111001 step 9 100000000000000000000000000000000001111100000000000001010110111001 step 10 100000000000000000000000000000000001111100000000000001011000111001 step 11 100000000000000000000000000000000001111100000000000001010000111001 step 12 100000000000000000000000000000000001111100000000000001010001100001 step 13 100000000000000000000000000000000001111100000000000001010000100001 step 14 100000000000000000000000000000000001111100000000000001010000100001 step 15 100000000000010000000000000000000000111101000000000001010000100001 step 16 100000000000010010000000000000000000110111000000000001010000100001 step 17 100000000000010010000000000000000000110111111000000001010000100001 step 18 100000000000010010000000000000000000110111011000000001010000100001 step 19 100000000000010010000000000000000000110111011111000001010000100001 step 20 100000000000010010000000000000000000110111011011000001010000100001 step 21 100000000000010010000000000000000000110111011011111001010000100001 step 22 100000000000010010000000000000000000110111011011011001010000100001 step 23 100000000000010010000000000000000000110111011011011110100000100001 step 24 100000000000010010000000000000000000110111011011011010100000100001 step 25 100000000000010010000000000000000000110111011011011010101110100001 step 26 100000000000010010000000000000000000110111011011011010100110100001 step 27 100000000000010010000000000000000000110111011011011010100111111001 step 28 100000000000010010000000000000000000110111011011011010100110111001 step 29 100000000000000010000000000000000001110110011011011010100110111001 step 30 100000000000000000000000000000000001111100011011011010100110111001 step 31 100000000000000000000000000000000001111100011011011010100110111001 step 32 100001000000000000000000000000000001111100011011011010100110111001 step 33 100001100000000000000000000000000001111100011011011010100110111001 step 34 100001100100000000000000000000000001111100011011011010100110111001 step 35 100001100110000000000000000000000001111100011011011010100110111001 step 36 100001100110100000000000000000000001111100011011011010100110111001 step 37 100001100110100100000000000000000001111100011011011010100110111001 step 38 100001100110100100010000000000000001111100011011011010100110111001 step 39 100001100110100100011000000000000001111100011011011010100110111001 step 40 100001100110100100011010000000000001111100011011011010100110111001 step 41 100001100110100100011011000000000001111100011011011010100110111001 step 42 100001100110100100011011010000000001111100011011011010100110111001 step 43 100001100110100100011011011000000001111100011011011010100110111001 step 44 100001100110100100011011011010000001111100011011011010100110111001 step 45 100001100110100100011011011011000001111100011011011010100110111001 step 46 100001100110100100011011011011010001111100011011011010100110111001 step 47 100001100110100100011011011011011001111100011011011010100110111001 step 48 100001100110100100011011011011011101111100011011011010100110111001 step 49 110001100110100100011011011011011100110111011011011010100110111001 step 50 100001100110100100011011011011011101111100011011011010100110111001 step 51 101001100110100100011011011011011100110111011011011010100110111001 step 52 100001100110100100011011011011011101111100011011011010100110111001 step 53 100101100110100100011011011011011100110111011011011010100110111001 step 54 100001100110100100011011011011011101111100011011011010100110111001 step 55 100011100110100100011011011011011100110111011011011010100110111001 step 56 100001100110100100011011011011011101111100011011011010100110111001 step 57 100001110110100100011011011011011100110111011011011010100110111001 step 58 100001100110100100011011011011011101111100011011011010100110111001 step 59 100001101110100100011011011011011100110111011011011010100110111001 step 60 100001100110100100011011011011011101111100011011011010100110111001 step 61 100001100111100100011011011011011100111101011011011010100110111001 step 62 100001100110100100011011011011011101111100011011011010100110111001 step 63 100001100110110100011011011011011100111101011011011010100110111001 step 64 100001100110100100011011011011011101111100011011011010100110111001 step 65 100001100110101100011011011011011101110110011011011010100110111001 step 66 100001100110100100011011011011011101111100011011011010100110111001 step 67 100001100110100110011011011011011101110110011011011010100110111001 step 68 100001100110100100011011011011011101111100011011011010100110111001 step 69 100001100110100101011011011011011101001111011011011010100110111001 step 70 100001100110100100011011011011011101111100011011011010100110111001 step 71 100001100110100100111011011011011101001111011011011010100110111001 step 72 100001100110100100011011011011011101111100011011011010100110111001 step 73 100001100110100100011111011011011101001111011011011010100110111001 step 74 100001100110100100011011011011011101111100011011011010100110111001 step 75 100001100110100100011011111011011101001111011011011010100110111001 step 76 100001100110100100011011011011011101111100011011011010100110111001 step 77 100001100110100100011011011111011101001111011011011010100110111001 step 78 100001100110100100011011011011011101111100011011011010100110111001 step 79 100001100110100100011011011011111101001111011011011010100110111001 step 80 100001100110100100011011011011011101111100011011011010100110111001 step 81 100001100110100100011011011011011111101110011011011010100110111001 step 82 100001100110100100011011011011011101111100011011011010100110111001 test 2: pass SLOT BAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBAABBAAAAAAAAAAAAAABBBBBBBBAB LETTER ALPSLFMDEEMCBFRSPKLEMFHRSCJLJKUHPNMBBNNVVRKRHUTDJUKANJHBTPDFSVDEVU SIDE 121212122121212121111111112212122222112222111221112112212112212212 DIRECTION IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIOOOOOOOIOOIOOIOOIOOOOIOOIIOOIIO this fail all fails was hi 111111111111111111111111111111111111111111111111111111111111111 1 rising ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ ^^^^^^^^^^^^^^^^^^^^ ^^ falling vvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvv vvvvvvvvvvvvvvvvvvvv vv was lo 00000000000000000000000000000000000000 00000000000000000000 0000 total fails 0, total passes 2 step 1 100000000000000000000000000000000001111100011011011010100110111001 step 2 100000000000000000000000000000000001111100100011011010100110111001 step 3 100000000000000000000000000000000001111100000011011010100110111001 step 4 100000000000000000000000000000000001111100000100011010100110111001 step 5 100000000000000000000000000000000001111100000000011010100110111001 step 6 100000000000000000000000000000000001111100000000100010100110111001 step 7 100000000000000000000000000000000001111100000000000010100110111001 step 8 100000000000000000000000000000000001111100000000000101010110111001 step 9 100000000000000000000000000000000001111100000000000001010110111001 step 10 100000000000000000000000000000000001111100000000000001011000111001 step 11 100000000000000000000000000000000001111100000000000001010000111001 step 12 100000000000000000000000000000000001111100000000000001010001100001 step 13 100000000000000000000000000000000001111100000000000001010000100001 step 14 100000000000000000000000000000000001111100000000000001010000100001 step 15 100000000000010000000000000000000000111101000000000001010000100001 step 16 100000000000010010000000000000000000110111000000000001010000100001 step 17 100000000000010010000000000000000000110111111000000001010000100001 step 18 100000000000010010000000000000000000110111011000000001010000100001 step 19 100000000000010010000000000000000000110111011111000001010000100001 step 20 100000000000010010000000000000000000110111011011000001010000100001 step 21 100000000000010010000000000000000000110111011011111001010000100001 step 22 100000000000010010000000000000000000110111011011011001010000100001 step 23 100000000000010010000000000000000000110111011011011110100000100001 step 24 100000000000010010000000000000000000110111011011011010100000100001 step 25 100000000000010010000000000000000000110111011011011010101110100001 step 26 100000000000010010000000000000000000110111011011011010100110100001 step 27 100000000000010010000000000000000000110111011011011010100111111001 step 28 100000000000010010000000000000000000110111011011011010100110111001 step 29 100000000000000010000000000000000001110110011011011010100110111001 step 30 100000000000000000000000000000000001111100011011011010100110111001 step 31 100000000000000000000000000000000001111100011011011010100110111001 step 32 100001000000000000000000000000000001111100011011011010100110111001 step 33 100001100000000000000000000000000001111100011011011010100110111001 step 34 100001100100000000000000000000000001111100011011011010100110111001 step 35 100001100110000000000000000000000001111100011011011010100110111001 step 36 100001100110100000000000000000000001111100011011011010100110111001 step 37 100001100110100100000000000000000001111100011011011010100110111001 step 38 100001100110100100010000000000000001111100011011011010100110111001 step 39 100001100110100100011000000000000001111100011011011010100110111001 step 40 100001100110100100011010000000000001111100011011011010100110111001 step 41 100001100110100100011011000000000001111100011011011010100110111001 step 42 100001100110100100011011010000000001111100011011011010100110111001 step 43 100001100110100100011011011000000001111100011011011010100110111001 step 44 100001100110100100011011011010000001111100011011011010100110111001 step 45 100001100110100100011011011011000001111100011011011010100110111001 step 46 100001100110100100011011011011010001111100011011011010100110111001 step 47 100001100110100100011011011011011001111100011011011010100110111001 step 48 100001100110100100011011011011011101111100011011011010100110111001 step 49 110001100110100100011011011011011100110111011011011010100110111001 step 50 100001100110100100011011011011011101111100011011011010100110111001 step 51 101001100110100100011011011011011100110111011011011010100110111001 step 52 100001100110100100011011011011011101111100011011011010100110111001 step 53 100101100110100100011011011011011100110111011011011010100110111001 step 54 100001100110100100011011011011011101111100011011011010100110111001 step 55 100011100110100100011011011011011100110111011011011010100110111001 step 56 100001100110100100011011011011011101111100011011011010100110111001 step 57 100001110110100100011011011011011100110111011011011010100110111001 step 58 100001100110100100011011011011011101111100011011011010100110111001 step 59 100001101110100100011011011011011100110111011011011010100110111001 step 60 100001100110100100011011011011011101111100011011011010100110111001 step 61 100001100111100100011011011011011100111101011011011010100110111001 step 62 100001100110100100011011011011011101111100011011011010100110111001 step 63 100001100110110100011011011011011100111101011011011010100110111001 step 64 100001100110100100011011011011011101111100011011011010100110111001 step 65 100001100110101100011011011011011101110110011011011010100110111001 step 66 100001100110100100011011011011011101111100011011011010100110111001 step 67 100001100110100110011011011011011101110110011011011010100110111001 step 68 100001100110100100011011011011011101111100011011011010100110111001 step 69 100001100110100101011011011011011101001111011011011010100110111001 step 70 100001100110100100011011011011011101111100011011011010100110111001 step 71 100001100110100100111011011011011101001111011011011010100110111001 step 72 100001100110100100011011011011011101111100011011011010100110111001 step 73 100001100110100100011111011011011101001111011011011010100110111001 step 74 100001100110100100011011011011011101111100011011011010100110111001 step 75 100001100110100100011011111011011101001111011011011010100110111001 step 76 100001100110100100011011011011011101111100011011011010100110111001 step 77 100001100110100100011011011111011101001111011011011010100110111001 step 78 100001100110100100011011011011011101111100011011011010100110111001 step 79 100001100110100100011011011011111101001111011011011010100110111001 step 80 100001100110100100011011011011011101111100011011011010100110111001 step 81 100001100110100100011011011011011111101110011011011010100110111001 step 82 100001100110100100011011011011011101111100011011011010100110111001 test 3: pass SLOT BAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBAABBAAAAAAAAAAAAAABBBBBBBBAB LETTER ALPSLFMDEEMCBFRSPKLEMFHRSCJLJKUHPNMBBNNVVRKRHUTDJUKANJHBTPDFSVDEVU SIDE 121212122121212121111111112212122222112222111221112112212112212212 DIRECTION IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIOOOOOOOIOOIOOIOOIOOOOIOOIIOOIIO this fail all fails was hi 111111111111111111111111111111111111111111111111111111111111111 1 rising ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ ^^^^^^^^^^^^^^^^^^^^ ^^ falling vvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvv vvvvvvvvvvvvvvvvvvvv vv was lo 00000000000000000000000000000000000000 00000000000000000000 0000 total fails 0, total passes 3 step 1 100000000000000000000000000000000001111100011011011010100110111001 step 2 100000000000000000000000000000000001111100100011011010100110111001 step 3 100000000000000000000000000000000001111100000011011010100110111001 step 4 100000000000000000000000000000000001111100000100011010100110111001 step 5 100000000000000000000000000000000001111100000000011010100110111001 step 6 100000000000000000000000000000000001111100000000100010100110111001 step 7 100000000000000000000000000000000001111100000000000010100110111001 step 8 100000000000000000000000000000000001111100000000000101010110111001 step 9 100000000000000000000000000000000001111100000000000001010110111001 step 10 100000000000000000000000000000000001111100000000000001011000111001 step 11 100000000000000000000000000000000001111100000000000001010000111001 step 12 100000000000000000000000000000000001111100000000000001010001100001 step 13 100000000000000000000000000000000001111100000000000001010000100001 step 14 100000000000000000000000000000000001111100000000000001010000100001 step 15 100000000000010000000000000000000000111101000000000001010000100001 step 16 100000000000010010000000000000000000110111000000000001010000100001 step 17 100000000000010010000000000000000000110111111000000001010000100001 step 18 100000000000010010000000000000000000110111011000000001010000100001 step 19 100000000000010010000000000000000000110111011111000001010000100001 step 20 100000000000010010000000000000000000110111011011000001010000100001 step 21 100000000000010010000000000000000000110111011011111001010000100001 step 22 100000000000010010000000000000000000110111011011011001010000100001 step 23 100000000000010010000000000000000000110111011011011110100000100001 step 24 100000000000010010000000000000000000110111011011011010100000100001 step 25 100000000000010010000000000000000000110111011011011010101110100001 step 26 100000000000010010000000000000000000110111011011011010100110100001 step 27 100000000000010010000000000000000000110111011011011010100111111001 step 28 100000000000010010000000000000000000110111011011011010100110111001 step 29 100000000000000010000000000000000001110110011011011010100110111001 step 30 100000000000000000000000000000000001111100011011011010100110111001 step 31 100000000000000000000000000000000001111100011011011010100110111001 step 32 100001000000000000000000000000000001111100011011011010100110111001 step 33 100001100000000000000000000000000001111100011011011010100110111001 step 34 100001100100000000000000000000000001111100011011011010100110111001 step 35 100001100110000000000000000000000001111100011011011010100110111001 step 36 100001100110100000000000000000000001111100011011011010100110111001 step 37 100001100110100100000000000000000001111100011011011010100110111001 step 38 100001100110100100010000000000000001111100011011011010100110111001 step 39 100001100110100100011000000000000001111100011011011010100110111001 step 40 100001100110100100011010000000000001111100011011011010100110111001 step 41 100001100110100100011011000000000001111100011011011010100110111001 step 42 100001100110100100011011010000000001111100011011011010100110111001 step 43 100001100110100100011011011000000001111100011011011010100110111001 step 44 100001100110100100011011011010000001111100011011011010100110111001 step 45 100001100110100100011011011011000001111100011011011010100110111001 step 46 100001100110100100011011011011010001111100011011011010100110111001 step 47 100001100110100100011011011011011001111100011011011010100110111001 step 48 100001100110100100011011011011011101111100011011011010100110111001 step 49 110001100110100100011011011011011100110111011011011010100110111001 step 50 100001100110100100011011011011011101111100011011011010100110111001 step 51 101001100110100100011011011011011100110111011011011010100110111001 step 52 100001100110100100011011011011011101111100011011011010100110111001 step 53 100101100110100100011011011011011100110111011011011010100110111001 step 54 100001100110100100011011011011011101111100011011011010100110111001 step 55 100011100110100100011011011011011100110111011011011010100110111001 step 56 100001100110100100011011011011011101111100011011011010100110111001 step 57 100001110110100100011011011011011100110111011011011010100110111001 step 58 100001100110100100011011011011011101111100011011011010100110111001 step 59 100001101110100100011011011011011100110111011011011010100110111001 step 60 100001100110100100011011011011011101111100011011011010100110111001 step 61 100001100111100100011011011011011100111101011011011010100110111001 step 62 100001100110100100011011011011011101111100011011011010100110111001 step 63 100001100110110100011011011011011100111101011011011010100110111001 step 64 100001100110100100011011011011011101111100011011011010100110111001 step 65 100001100110101100011011011011011101110110011011011010100110111001 step 66 100001100110100100011011011011011101111100011011011010100110111001 step 67 100001100110100110011011011011011101110110011011011010100110111001 step 68 100001100110100100011011011011011101111100011011011010100110111001 step 69 100001100110100101011011011011011101001111011011011010100110111001 step 70 100001100110100100011011011011011101111100011011011010100110111001 step 71 100001100110100100111011011011011101001111011011011010100110111001 step 72 100001100110100100011011011011011101111100011011011010100110111001 step 73 100001100110100100011111011011011101001111011011011010100110111001 step 74 100001100110100100011011011011011101111100011011011010100110111001 step 75 100001100110100100011011111011011101001111011011011010100110111001 step 76 100001100110100100011011011011011101111100011011011010100110111001 step 77 100001100110100100011011011111011101001111011011011010100110111001 step 78 100001100110100100011011011011011101111100011011011010100110111001 step 79 100001100110100100011011011011111101001111011011011010100110111001 step 80 100001100110100100011011011011011101111100011011011010100110111001 step 81 100001100110100100011011011011011111101110011011011010100110111001 step 82 100001100110100100011011011011011101111100011011011010100110111001 test 4: pass SLOT BAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBAABBAAAAAAAAAAAAAABBBBBBBBAB LETTER ALPSLFMDEEMCBFRSPKLEMFHRSCJLJKUHPNMBBNNVVRKRHUTDJUKANJHBTPDFSVDEVU SIDE 121212122121212121111111112212122222112222111221112112212112212212 DIRECTION IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIOOOOOOOIOOIOOIOOIOOOOIOOIIOOIIO this fail all fails was hi 111111111111111111111111111111111111111111111111111111111111111 1 rising ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ ^^^^^^^^^^^^^^^^^^^^ ^^ falling vvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvv vvvvvvvvvvvvvvvvvvvv vv was lo 00000000000000000000000000000000000000 00000000000000000000 0000 total fails 0, total passes 4 step 1 100000000000000000000000000000000001111100011011011010100110111001 step 2 100000000000000000000000000000000001111100100011011010100110111001 step 3 100000000000000000000000000000000001111100000011011010100110111001 step 4 100000000000000000000000000000000001111100000100011010100110111001 step 5 100000000000000000000000000000000001111100000000011010100110111001 step 6 100000000000000000000000000000000001111100000000100010100110111001 step 7 100000000000000000000000000000000001111100000000000010100110111001 step 8 100000000000000000000000000000000001111100000000000101010110111001 step 9 100000000000000000000000000000000001111100000000000001010110111001 step 10 100000000000000000000000000000000001111100000000000001011000111001 step 11 100000000000000000000000000000000001111100000000000001010000111001 step 12 100000000000000000000000000000000001111100000000000001010001100001 step 13 100000000000000000000000000000000001111100000000000001010000100001 step 14 100000000000000000000000000000000001111100000000000001010000100001 step 15 100000000000010000000000000000000000111101000000000001010000100001 step 16 100000000000010010000000000000000000110111000000000001010000100001 step 17 100000000000010010000000000000000000110111111000000001010000100001 step 18 100000000000010010000000000000000000110111011000000001010000100001 step 19 100000000000010010000000000000000000110111011111000001010000100001 step 20 100000000000010010000000000000000000110111011011000001010000100001 step 21 100000000000010010000000000000000000110111011011111001010000100001 step 22 100000000000010010000000000000000000110111011011011001010000100001 step 23 100000000000010010000000000000000000110111011011011110100000100001 step 24 100000000000010010000000000000000000110111011011011010100000100001 step 25 100000000000010010000000000000000000110111011011011010101110100001 step 26 100000000000010010000000000000000000110111011011011010100110100001 step 27 100000000000010010000000000000000000110111011011011010100111111001 step 28 100000000000010010000000000000000000110111011011011010100110111001 step 29 100000000000000010000000000000000001110110011011011010100110111001 step 30 100000000000000000000000000000000001111100011011011010100110111001 step 31 100000000000000000000000000000000001111100011011011010100110111001 step 32 100001000000000000000000000000000001111100011011011010100110111001 step 33 100001100000000000000000000000000001111100011011011010100110111001 step 34 100001100100000000000000000000000001111100011011011010100110111001 step 35 100001100110000000000000000000000001111100011011011010100110111001 step 36 100001100110100000000000000000000001111100011011011010100110111001 step 37 100001100110100100000000000000000001111100011011011010100110111001 step 38 100001100110100100010000000000000001111100011011011010100110111001 step 39 100001100110100100011000000000000001111100011011011010100110111001 step 40 100001100110100100011010000000000001111100011011011010100110111001 step 41 100001100110100100011011000000000001111100011011011010100110111001 step 42 100001100110100100011011010000000001111100011011011010100110111001 step 43 100001100110100100011011011000000001111100011011011010100110111001 step 44 100001100110100100011011011010000001111100011011011010100110111001 step 45 100001100110100100011011011011000001111100011011011010100110111001 step 46 100001100110100100011011011011010001111100011011011010100110111001 step 47 100001100110100100011011011011011001111100011011011010100110111001 step 48 100001100110100100011011011011011101111100011011011010100110111001 step 49 110001100110100100011011011011011100110111011011011010100110111001 step 50 100001100110100100011011011011011101111100011011011010100110111001 step 51 101001100110100100011011011011011100110111011011011010100110111001 step 52 100001100110100100011011011011011101111100011011011010100110111001 step 53 100101100110100100011011011011011100110111011011011010100110111001 step 54 100001100110100100011011011011011101111100011011011010100110111001 step 55 100011100110100100011011011011011100110111011011011010100110111001 step 56 100001100110100100011011011011011101111100011011011010100110111001 step 57 100001110110100100011011011011011100110111011011011010100110111001 step 58 100001100110100100011011011011011101111100011011011010100110111001 step 59 100001101110100100011011011011011100110111011011011010100110111001 step 60 100001100110100100011011011011011101111100011011011010100110111001 step 61 100001100111100100011011011011011100111101011011011010100110111001 step 62 100001100110100100011011011011011101111100011011011010100110111001 step 63 100001100110110100011011011011011100111101011011011010100110111001 step 64 100001100110100100011011011011011101111100011011011010100110111001 step 65 100001100110101100011011011011011101110110011011011010100110111001 step 66 100001100110100100011011011011011101111100011011011010100110111001 step 67 100001100110100110011011011011011101110110011011011010100110111001 step 68 100001100110100100011011011011011101111100011011011010100110111001 step 69 100001100110100101011011011011011101001111011011011010100110111001 step 70 100001100110100100011011011011011101111100011011011010100110111001 step 71 100001100110100100111011011011011101001111011011011010100110111001 step 72 100001100110100100011011011011011101111100011011011010100110111001 step 73 100001100110100100011111011011011101001111011011011010100110111001 step 74 100001100110100100011011011011011101111100011011011010100110111001 step 75 100001100110100100011011111011011101001111011011011010100110111001 step 76 100001100110100100011011011011011101111100011011011010100110111001 step 77 100001100110100100011011011111011101001111011011011010100110111001 step 78 100001100110100100011011011011011101111100011011011010100110111001 step 79 100001100110100100011011011011111101001111011011011010100110111001 step 80 100001100110100100011011011011011101111100011011011010100110111001 step 81 100001100110100100011011011011011111101110011011011010100110111001 step 82 100001100110100100011011011011011101111100011011011010100110111001 test 5: pass SLOT BAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBAABBAAAAAAAAAAAAAABBBBBBBBAB LETTER ALPSLFMDEEMCBFRSPKLEMFHRSCJLJKUHPNMBBNNVVRKRHUTDJUKANJHBTPDFSVDEVU SIDE 121212122121212121111111112212122222112222111221112112212112212212 DIRECTION IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIOOOOOOOIOOIOOIOOIOOOOIOOIIOOIIO this fail all fails was hi 111111111111111111111111111111111111111111111111111111111111111 1 rising ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ ^^^^^^^^^^^^^^^^^^^^ ^^ falling vvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvv vvvvvvvvvvvvvvvvvvvv vv was lo 00000000000000000000000000000000000000 00000000000000000000 0000 total fails 0, total passes 5 step 1 100000000000000000000000000000000001111100011011011010100110111001 step 2 100000000000000000000000000000000001111100100011011010100110111001 step 3 100000000000000000000000000000000001111100000011011010100110111001 step 4 100000000000000000000000000000000001111100000100011010100110111001 step 5 100000000000000000000000000000000001111100000000011010100110111001 step 6 100000000000000000000000000000000001111100000000100010100110111001 step 7 100000000000000000000000000000000001111100000000000010100110111001 step 8 100000000000000000000000000000000001111100000000000101010110111001 step 9 100000000000000000000000000000000001111100000000000001010110111001 step 10 100000000000000000000000000000000001111100000000000001011000111001 step 11 100000000000000000000000000000000001111100000000000001010000111001 step 12 100000000000000000000000000000000001111100000000000001010001100001 step 13 100000000000000000000000000000000001111100000000000001010000100001 step 14 100000000000000000000000000000000001111100000000000001010000100001 step 15 100000000000010000000000000000000000111101000000000001010000100001 step 16 100000000000010010000000000000000000110111000000000001010000100001 step 17 100000000000010010000000000000000000110111111000000001010000100001 step 18 100000000000010010000000000000000000110111011000000001010000100001 step 19 100000000000010010000000000000000000110111011111000001010000100001 step 20 100000000000010010000000000000000000110111011011000001010000100001 step 21 100000000000010010000000000000000000110111011011111001010000100001 step 22 100000000000010010000000000000000000110111011011011001010000100001 step 23 100000000000010010000000000000000000110111011011011110100000100001 step 24 100000000000010010000000000000000000110111011011011010100000100001 step 25 100000000000010010000000000000000000110111011011011010101110100001 step 26 100000000000010010000000000000000000110111011011011010100110100001 step 27 100000000000010010000000000000000000110111011011011010100111111001 step 28 100000000000010010000000000000000000110111011011011010100110111001 step 29 100000000000000010000000000000000001110110011011011010100110111001 step 30 100000000000000000000000000000000001111100011011011010100110111001 step 31 100000000000000000000000000000000001111100011011011010100110111001 step 32 100001000000000000000000000000000001111100011011011010100110111001 step 33 100001100000000000000000000000000001111100011011011010100110111001 step 34 100001100100000000000000000000000001111100011011011010100110111001 step 35 100001100110000000000000000000000001111100011011011010100110111001 step 36 100001100110100000000000000000000001111100011011011010100110111001 step 37 100001100110100100000000000000000001111100011011011010100110111001 step 38 100001100110100100010000000000000001111100011011011010100110111001 step 39 100001100110100100011000000000000001111100011011011010100110111001 step 40 100001100110100100011010000000000001111100011011011010100110111001 step 41 100001100110100100011011000000000001111100011011011010100110111001 step 42 100001100110100100011011010000000001111100011011011010100110111001 step 43 100001100110100100011011011000000001111100011011011010100110111001 step 44 100001100110100100011011011010000001111100011011011010100110111001 step 45 100001100110100100011011011011000001111100011011011010100110111001 step 46 100001100110100100011011011011010001111100011011011010100110111001 step 47 100001100110100100011011011011011001111100011011011010100110111001 step 48 100001100110100100011011011011011101111100011011011010100110111001 step 49 110001100110100100011011011011011100110111011011011010100110111001 step 50 100001100110100100011011011011011101111100011011011010100110111001 step 51 101001100110100100011011011011011100110111011011011010100110111001 step 52 100001100110100100011011011011011101111100011011011010100110111001 step 53 100101100110100100011011011011011100110111011011011010100110111001 step 54 100001100110100100011011011011011101111100011011011010100110111001 step 55 100011100110100100011011011011011100110111011011011010100110111001 step 56 100001100110100100011011011011011101111100011011011010100110111001 step 57 100001110110100100011011011011011100110111011011011010100110111001 step 58 100001100110100100011011011011011101111100011011011010100110111001 step 59 100001101110100100011011011011011100110111011011011010100110111001 step 60 100001100110100100011011011011011101111100011011011010100110111001 step 61 100001100111100100011011011011011100111101011011011010100110111001 step 62 100001100110100100011011011011011101111100011011011010100110111001 step 63 100001100110110100011011011011011100111101011011011010100110111001 step 64 100001100110100100011011011011011101111100011011011010100110111001 step 65 100001100110101100011011011011011101110110011011011010100110111001 step 66 100001100110100100011011011011011101111100011011011010100110111001 step 67 100001100110100110011011011011011101110110011011011010100110111001 step 68 100001100110100100011011011011011101111100011011011010100110111001 step 69 100001100110100101011011011011011101001111011011011010100110111001 step 70 100001100110100100011011011011011101111100011011011010100110111001 step 71 100001100110100100111011011011011101001111011011011010100110111001 step 72 100001100110100100011011011011011101111100011011011010100110111001 step 73 100001100110100100011111011011011101001111011011011010100110111001 step 74 100001100110100100011011011011011101111100011011011010100110111001 step 75 100001100110100100011011111011011101001111011011011010100110111001 step 76 100001100110100100011011011011011101111100011011011010100110111001 step 77 100001100110100100011011011111011101001111011011011010100110111001 step 78 100001100110100100011011011011011101111100011011011010100110111001 step 79 100001100110100100011011011011111101001111011011011010100110111001 step 80 100001100110100100011011011011011101111100011011011010100110111001 step 81 100001100110100100011011011011011111101110011011011010100110111001 step 82 100001100110100100011011011011011101111100011011011010100110111001 test 6: pass SLOT BAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBAABBAAAAAAAAAAAAAABBBBBBBBAB LETTER ALPSLFMDEEMCBFRSPKLEMFHRSCJLJKUHPNMBBNNVVRKRHUTDJUKANJHBTPDFSVDEVU SIDE 121212122121212121111111112212122222112222111221112112212112212212 DIRECTION IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIOOOOOOOIOOIOOIOOIOOOOIOOIIOOIIO this fail all fails was hi 111111111111111111111111111111111111111111111111111111111111111 1 rising ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ ^^^^^^^^^^^^^^^^^^^^ ^^ falling vvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvv vvvvvvvvvvvvvvvvvvvv vv was lo 00000000000000000000000000000000000000 00000000000000000000 0000 total fails 0, total passes 6 step 1 100000000000000000000000000000000001111100011011011010100110111001 step 2 100000000000000000000000000000000001111100100011011010100110111001 step 3 100000000000000000000000000000000001111100000011011010100110111001 step 4 100000000000000000000000000000000001111100000100011010100110111001 step 5 100000000000000000000000000000000001111100000000011010100110111001 step 6 100000000000000000000000000000000001111100000000100010100110111001 step 7 100000000000000000000000000000000001111100000000000010100110111001 step 8 100000000000000000000000000000000001111100000000000101010110111001 step 9 100000000000000000000000000000000001111100000000000001010110111001 step 10 100000000000000000000000000000000001111100000000000001011000111001 step 11 100000000000000000000000000000000001111100000000000001010000111001 step 12 100000000000000000000000000000000001111100000000000001010001100001 step 13 100000000000000000000000000000000001111100000000000001010000100001 step 14 100000000000000000000000000000000001111100000000000001010000100001 step 15 100000000000010000000000000000000000111101000000000001010000100001 step 16 100000000000010010000000000000000000110111000000000001010000100001 step 17 100000000000010010000000000000000000110111111000000001010000100001 step 18 100000000000010010000000000000000000110111011000000001010000100001 step 19 100000000000010010000000000000000000110111011111000001010000100001 step 20 100000000000010010000000000000000000110111011011000001010000100001 step 21 100000000000010010000000000000000000110111011011111001010000100001 step 22 100000000000010010000000000000000000110111011011011001010000100001 step 23 100000000000010010000000000000000000110111011011011110100000100001 step 24 100000000000010010000000000000000000110111011011011010100000100001 step 25 100000000000010010000000000000000000110111011011011010101110100001 step 26 100000000000010010000000000000000000110111011011011010100110100001 step 27 100000000000010010000000000000000000110111011011011010100111111001 step 28 100000000000010010000000000000000000110111011011011010100110111001 step 29 100000000000000010000000000000000001110110011011011010100110111001 step 30 100000000000000000000000000000000001111100011011011010100110111001 step 31 100000000000000000000000000000000001111100011011011010100110111001 step 32 100001000000000000000000000000000001111100011011011010100110111001 step 33 100001100000000000000000000000000001111100011011011010100110111001 step 34 100001100100000000000000000000000001111100011011011010100110111001 step 35 100001100110000000000000000000000001111100011011011010100110111001 step 36 100001100110100000000000000000000001111100011011011010100110111001 step 37 100001100110100100000000000000000001111100011011011010100110111001 step 38 100001100110100100010000000000000001111100011011011010100110111001 step 39 100001100110100100011000000000000001111100011011011010100110111001 step 40 100001100110100100011010000000000001111100011011011010100110111001 step 41 100001100110100100011011000000000001111100011011011010100110111001 step 42 100001100110100100011011010000000001111100011011011010100110111001 step 43 100001100110100100011011011000000001111100011011011010100110111001 step 44 100001100110100100011011011010000001111100011011011010100110111001 step 45 100001100110100100011011011011000001111100011011011010100110111001 step 46 100001100110100100011011011011010001111100011011011010100110111001 step 47 100001100110100100011011011011011001111100011011011010100110111001 step 48 100001100110100100011011011011011101111100011011011010100110111001 step 49 110001100110100100011011011011011100110111011011011010100110111001 step 50 100001100110100100011011011011011101111100011011011010100110111001 step 51 101001100110100100011011011011011100110111011011011010100110111001 step 52 100001100110100100011011011011011101111100011011011010100110111001 step 53 100101100110100100011011011011011100110111011011011010100110111001 step 54 100001100110100100011011011011011101111100011011011010100110111001 step 55 100011100110100100011011011011011100110111011011011010100110111001 step 56 100001100110100100011011011011011101111100011011011010100110111001 step 57 100001110110100100011011011011011100110111011011011010100110111001 step 58 100001100110100100011011011011011101111100011011011010100110111001 step 59 100001101110100100011011011011011100110111011011011010100110111001 step 60 100001100110100100011011011011011101111100011011011010100110111001 step 61 100001100111100100011011011011011100111101011011011010100110111001 step 62 100001100110100100011011011011011101111100011011011010100110111001 step 63 100001100110110100011011011011011100111101011011011010100110111001 step 64 100001100110100100011011011011011101111100011011011010100110111001 step 65 100001100110101100011011011011011101110110011011011010100110111001 step 66 100001100110100100011011011011011101111100011011011010100110111001 step 67 100001100110100110011011011011011101110110011011011010100110111001 step 68 100001100110100100011011011011011101111100011011011010100110111001 step 69 100001100110100101011011011011011101001111011011011010100110111001 step 70 100001100110100100011011011011011101111100011011011010100110111001 step 71 100001100110100100111011011011011101001111011011011010100110111001 step 72 100001100110100100011011011011011101111100011011011010100110111001 step 73 100001100110100100011111011011011101001111011011011010100110111001 step 74 100001100110100100011011011011011101111100011011011010100110111001 step 75 100001100110100100011011111011011101001111011011011010100110111001 step 76 100001100110100100011011011011011101111100011011011010100110111001 step 77 100001100110100100011011011111011101001111011011011010100110111001 step 78 100001100110100100011011011011011101111100011011011010100110111001 step 79 100001100110100100011011011011111101001111011011011010100110111001 step 80 100001100110100100011011011011011101111100011011011010100110111001 step 81 100001100110100100011011011011011111101110011011011010100110111001 step 82 100001100110100100011011011011011101111100011011011010100110111001 test 7: pass SLOT BAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBAABBAAAAAAAAAAAAAABBBBBBBBAB LETTER ALPSLFMDEEMCBFRSPKLEMFHRSCJLJKUHPNMBBNNVVRKRHUTDJUKANJHBTPDFSVDEVU SIDE 121212122121212121111111112212122222112222111221112112212112212212 DIRECTION IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIOOOOOOOIOOIOOIOOIOOOOIOOIIOOIIO this fail all fails was hi 111111111111111111111111111111111111111111111111111111111111111 1 rising ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ ^^^^^^^^^^^^^^^^^^^^ ^^ falling vvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvv vvvvvvvvvvvvvvvvvvvv vv was lo 00000000000000000000000000000000000000 00000000000000000000 0000 total fails 0, total passes 7 step 1 100000000000000000000000000000000001111100011011011010100110111001 step 2 100000000000000000000000000000000001111100100011011010100110111001 step 3 100000000000000000000000000000000001111100000011011010100110111001 step 4 100000000000000000000000000000000001111100000100011010100110111001 step 5 100000000000000000000000000000000001111100000000011010100110111001 step 6 100000000000000000000000000000000001111100000000100010100110111001 step 7 100000000000000000000000000000000001111100000000000010100110111001 step 8 100000000000000000000000000000000001111100000000000101010110111001 step 9 100000000000000000000000000000000001111100000000000001010110111001 step 10 100000000000000000000000000000000001111100000000000001011000111001 step 11 100000000000000000000000000000000001111100000000000001010000111001 step 12 100000000000000000000000000000000001111100000000000001010001100001 step 13 100000000000000000000000000000000001111100000000000001010000100001 step 14 100000000000000000000000000000000001111100000000000001010000100001 step 15 100000000000010000000000000000000000111101000000000001010000100001 step 16 100000000000010010000000000000000000110111000000000001010000100001 step 17 100000000000010010000000000000000000110111111000000001010000100001 step 18 100000000000010010000000000000000000110111011000000001010000100001 step 19 100000000000010010000000000000000000110111011111000001010000100001 step 20 100000000000010010000000000000000000110111011011000001010000100001 step 21 100000000000010010000000000000000000110111011011111001010000100001 step 22 100000000000010010000000000000000000110111011011011001010000100001 step 23 100000000000010010000000000000000000110111011011011110100000100001 step 24 100000000000010010000000000000000000110111011011011010100000100001 step 25 100000000000010010000000000000000000110111011011011010101110100001 step 26 100000000000010010000000000000000000110111011011011010100110100001 step 27 100000000000010010000000000000000000110111011011011010100111111001 step 28 100000000000010010000000000000000000110111011011011010100110111001 step 29 100000000000000010000000000000000001110110011011011010100110111001 step 30 100000000000000000000000000000000001111100011011011010100110111001 step 31 100000000000000000000000000000000001111100011011011010100110111001 step 32 100001000000000000000000000000000001111100011011011010100110111001 step 33 100001100000000000000000000000000001111100011011011010100110111001 step 34 100001100100000000000000000000000001111100011011011010100110111001 step 35 100001100110000000000000000000000001111100011011011010100110111001 step 36 100001100110100000000000000000000001111100011011011010100110111001 step 37 100001100110100100000000000000000001111100011011011010100110111001 step 38 100001100110100100010000000000000001111100011011011010100110111001 step 39 100001100110100100011000000000000001111100011011011010100110111001 step 40 100001100110100100011010000000000001111100011011011010100110111001 step 41 100001100110100100011011000000000001111100011011011010100110111001 step 42 100001100110100100011011010000000001111100011011011010100110111001 step 43 100001100110100100011011011000000001111100011011011010100110111001 step 44 100001100110100100011011011010000001111100011011011010100110111001 step 45 100001100110100100011011011011000001111100011011011010100110111001 step 46 100001100110100100011011011011010001111100011011011010100110111001 step 47 100001100110100100011011011011011001111100011011011010100110111001 step 48 100001100110100100011011011011011101111100011011011010100110111001 step 49 110001100110100100011011011011011100110111011011011010100110111001 step 50 100001100110100100011011011011011101111100011011011010100110111001 step 51 101001100110100100011011011011011100110111011011011010100110111001 step 52 100001100110100100011011011011011101111100011011011010100110111001 step 53 100101100110100100011011011011011100110111011011011010100110111001 step 54 100001100110100100011011011011011101111100011011011010100110111001 step 55 100011100110100100011011011011011100110111011011011010100110111001 step 56 100001100110100100011011011011011101111100011011011010100110111001 step 57 100001110110100100011011011011011100110111011011011010100110111001 step 58 100001100110100100011011011011011101111100011011011010100110111001 step 59 100001101110100100011011011011011100110111011011011010100110111001 step 60 100001100110100100011011011011011101111100011011011010100110111001 step 61 100001100111100100011011011011011100111101011011011010100110111001 step 62 100001100110100100011011011011011101111100011011011010100110111001 step 63 100001100110110100011011011011011100111101011011011010100110111001 step 64 100001100110100100011011011011011101111100011011011010100110111001 step 65 100001100110101100011011011011011101110110011011011010100110111001 step 66 100001100110100100011011011011011101111100011011011010100110111001 step 67 100001100110100110011011011011011101110110011011011010100110111001 step 68 100001100110100100011011011011011101111100011011011010100110111001 step 69 100001100110100101011011011011011101001111011011011010100110111001 step 70 100001100110100100011011011011011101111100011011011010100110111001 step 71 100001100110100100111011011011011101001111011011011010100110111001 step 72 100001100110100100011011011011011101111100011011011010100110111001 step 73 100001100110100100011111011011011101001111011011011010100110111001 step 74 100001100110100100011011011011011101111100011011011010100110111001 step 75 100001100110100100011011111011011101001111011011011010100110111001 step 76 100001100110100100011011011011011101111100011011011010100110111001 step 77 100001100110100100011011011111011101001111011011011010100110111001 step 78 100001100110100100011011011011011101111100011011011010100110111001 step 79 100001100110100100011011011011111101001111011011011010100110111001 step 80 100001100110100100011011011011011101111100011011011010100110111001 step 81 100001100110100100011011011011011111101110011011011010100110111001 step 82 100001100110100100011011011011011101111100011011011010100110111001 test 8: pass SLOT BAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBAABBAAAAAAAAAAAAAABBBBBBBBAB LETTER ALPSLFMDEEMCBFRSPKLEMFHRSCJLJKUHPNMBBNNVVRKRHUTDJUKANJHBTPDFSVDEVU SIDE 121212122121212121111111112212122222112222111221112112212112212212 DIRECTION IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIOOOOOOOIOOIOOIOOIOOOOIOOIIOOIIO this fail all fails was hi 111111111111111111111111111111111111111111111111111111111111111 1 rising ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ ^^^^^^^^^^^^^^^^^^^^ ^^ falling vvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvv vvvvvvvvvvvvvvvvvvvv vv was lo 00000000000000000000000000000000000000 00000000000000000000 0000 total fails 0, total passes 8 step 1 100000000000000000000000000000000001111100011011011010100110111001 step 2 100000000000000000000000000000000001111100100011011010100110111001 step 3 100000000000000000000000000000000001111100000011011010100110111001 step 4 100000000000000000000000000000000001111100000100011010100110111001 step 5 100000000000000000000000000000000001111100000000011010100110111001 step 6 100000000000000000000000000000000001111100000000100010100110111001 step 7 100000000000000000000000000000000001111100000000000010100110111001 step 8 100000000000000000000000000000000001111100000000000101010110111001 step 9 100000000000000000000000000000000001111100000000000001010110111001 step 10 100000000000000000000000000000000001111100000000000001011000111001 step 11 100000000000000000000000000000000001111100000000000001010000111001 step 12 100000000000000000000000000000000001111100000000000001010001100001 step 13 100000000000000000000000000000000001111100000000000001010000100001 step 14 100000000000000000000000000000000001111100000000000001010000100001 step 15 100000000000010000000000000000000000111101000000000001010000100001 step 16 100000000000010010000000000000000000110111000000000001010000100001 step 17 100000000000010010000000000000000000110111111000000001010000100001 step 18 100000000000010010000000000000000000110111011000000001010000100001 step 19 100000000000010010000000000000000000110111011111000001010000100001 step 20 100000000000010010000000000000000000110111011011000001010000100001 step 21 100000000000010010000000000000000000110111011011111001010000100001 step 22 100000000000010010000000000000000000110111011011011001010000100001 step 23 100000000000010010000000000000000000110111011011011110100000100001 step 24 100000000000010010000000000000000000110111011011011010100000100001 step 25 100000000000010010000000000000000000110111011011011010101110100001 step 26 100000000000010010000000000000000000110111011011011010100110100001 step 27 100000000000010010000000000000000000110111011011011010100111111001 step 28 100000000000010010000000000000000000110111011011011010100110111001 step 29 100000000000000010000000000000000001110110011011011010100110111001 step 30 100000000000000000000000000000000001111100011011011010100110111001 step 31 100000000000000000000000000000000001111100011011011010100110111001 step 32 100001000000000000000000000000000001111100011011011010100110111001 step 33 100001100000000000000000000000000001111100011011011010100110111001 step 34 100001100100000000000000000000000001111100011011011010100110111001 step 35 100001100110000000000000000000000001111100011011011010100110111001 step 36 100001100110100000000000000000000001111100011011011010100110111001 step 37 100001100110100100000000000000000001111100011011011010100110111001 step 38 100001100110100100010000000000000001111100011011011010100110111001 step 39 100001100110100100011000000000000001111100011011011010100110111001 step 40 100001100110100100011010000000000001111100011011011010100110111001 step 41 100001100110100100011011000000000001111100011011011010100110111001 step 42 100001100110100100011011010000000001111100011011011010100110111001 step 43 100001100110100100011011011000000001111100011011011010100110111001 step 44 100001100110100100011011011010000001111100011011011010100110111001 step 45 100001100110100100011011011011000001111100011011011010100110111001 step 46 100001100110100100011011011011010001111100011011011010100110111001 step 47 100001100110100100011011011011011001111100011011011010100110111001 step 48 100001100110100100011011011011011101111100011011011010100110111001 step 49 110001100110100100011011011011011100110111011011011010100110111001 step 50 100001100110100100011011011011011101111100011011011010100110111001 step 51 101001100110100100011011011011011100110111011011011010100110111001 step 52 100001100110100100011011011011011101111100011011011010100110111001 step 53 100101100110100100011011011011011100110111011011011010100110111001 step 54 100001100110100100011011011011011101111100011011011010100110111001 step 55 100011100110100100011011011011011100110111011011011010100110111001 step 56 100001100110100100011011011011011101111100011011011010100110111001 step 57 100001110110100100011011011011011100110111011011011010100110111001 step 58 100001100110100100011011011011011101111100011011011010100110111001 step 59 100001101110100100011011011011011100110111011011011010100110111001 step 60 100001100110100100011011011011011101111100011011011010100110111001 step 61 100001100111100100011011011011011100111101011011011010100110111001 step 62 100001100110100100011011011011011101111100011011011010100110111001 step 63 100001100110110100011011011011011100111101011011011010100110111001 step 64 100001100110100100011011011011011101111100011011011010100110111001 step 65 100001100110101100011011011011011101110110011011011010100110111001 step 66 100001100110100100011011011011011101111100011011011010100110111001 step 67 100001100110100110011011011011011101110110011011011010100110111001 step 68 100001100110100100011011011011011101111100011011011010100110111001 step 69 100001100110100101011011011011011101001111011011011010100110111001 step 70 100001100110100100011011011011011101111100011011011010100110111001 step 71 100001100110100100111011011011011101001111011011011010100110111001 step 72 100001100110100100011011011011011101111100011011011010100110111001 step 73 100001100110100100011111011011011101001111011011011010100110111001 step 74 100001100110100100011011011011011101111100011011011010100110111001 step 75 100001100110100100011011111011011101001111011011011010100110111001 step 76 100001100110100100011011011011011101111100011011011010100110111001 step 77 100001100110100100011011011111011101001111011011011010100110111001 step 78 100001100110100100011011011011011101111100011011011010100110111001 step 79 100001100110100100011011011011111101001111011011011010100110111001 step 80 100001100110100100011011011011011101111100011011011010100110111001 step 81 100001100110100100011011011011011111101110011011011010100110111001 step 82 100001100110100100011011011011011101111100011011011010100110111001 test 9: pass SLOT BAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBAABBAAAAAAAAAAAAAABBBBBBBBAB LETTER ALPSLFMDEEMCBFRSPKLEMFHRSCJLJKUHPNMBBNNVVRKRHUTDJUKANJHBTPDFSVDEVU SIDE 121212122121212121111111112212122222112222111221112112212112212212 DIRECTION IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIOOOOOOOIOOIOOIOOIOOOOIOOIIOOIIO this fail all fails was hi 111111111111111111111111111111111111111111111111111111111111111 1 rising ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ ^^^^^^^^^^^^^^^^^^^^ ^^ falling vvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvv vvvvvvvvvvvvvvvvvvvv vv was lo 00000000000000000000000000000000000000 00000000000000000000 0000 total fails 0, total passes 9 step 1 100000000000000000000000000000000001111100011011011010100110111001 step 2 100000000000000000000000000000000001111100100011011010100110111001 step 3 100000000000000000000000000000000001111100000011011010100110111001 step 4 100000000000000000000000000000000001111100000100011010100110111001 step 5 100000000000000000000000000000000001111100000000011010100110111001 step 6 100000000000000000000000000000000001111100000000100010100110111001 step 7 100000000000000000000000000000000001111100000000000010100110111001 step 8 100000000000000000000000000000000001111100000000000101010110111001 step 9 100000000000000000000000000000000001111100000000000001010110111001 step 10 100000000000000000000000000000000001111100000000000001011000111001 step 11 100000000000000000000000000000000001111100000000000001010000111001 step 12 100000000000000000000000000000000001111100000000000001010001100001 step 13 100000000000000000000000000000000001111100000000000001010000100001 step 14 100000000000000000000000000000000001111100000000000001010000100001 step 15 100000000000010000000000000000000000111101000000000001010000100001 step 16 100000000000010010000000000000000000110111000000000001010000100001 step 17 100000000000010010000000000000000000110111111000000001010000100001 step 18 100000000000010010000000000000000000110111011000000001010000100001 step 19 100000000000010010000000000000000000110111011111000001010000100001 step 20 100000000000010010000000000000000000110111011011000001010000100001 step 21 100000000000010010000000000000000000110111011011111001010000100001 step 22 100000000000010010000000000000000000110111011011011001010000100001 step 23 100000000000010010000000000000000000110111011011011110100000100001 step 24 100000000000010010000000000000000000110111011011011010100000100001 step 25 100000000000010010000000000000000000110111011011011010101110100001 step 26 100000000000010010000000000000000000110111011011011010100110100001 step 27 100000000000010010000000000000000000110111011011011010100111111001 step 28 100000000000010010000000000000000000110111011011011010100110111001 step 29 100000000000000010000000000000000001110110011011011010100110111001 step 30 100000000000000000000000000000000001111100011011011010100110111001 step 31 100000000000000000000000000000000001111100011011011010100110111001 step 32 100001000000000000000000000000000001111100011011011010100110111001 step 33 100001100000000000000000000000000001111100011011011010100110111001 step 34 100001100100000000000000000000000001111100011011011010100110111001 step 35 100001100110000000000000000000000001111100011011011010100110111001 step 36 100001100110100000000000000000000001111100011011011010100110111001 step 37 100001100110100100000000000000000001111100011011011010100110111001 step 38 100001100110100100010000000000000001111100011011011010100110111001 step 39 100001100110100100011000000000000001111100011011011010100110111001 step 40 100001100110100100011010000000000001111100011011011010100110111001 step 41 100001100110100100011011000000000001111100011011011010100110111001 step 42 100001100110100100011011010000000001111100011011011010100110111001 step 43 100001100110100100011011011000000001111100011011011010100110111001 step 44 100001100110100100011011011010000001111100011011011010100110111001 step 45 100001100110100100011011011011000001111100011011011010100110111001 step 46 100001100110100100011011011011010001111100011011011010100110111001 step 47 100001100110100100011011011011011001111100011011011010100110111001 step 48 100001100110100100011011011011011101111100011011011010100110111001 step 49 110001100110100100011011011011011100110111011011011010100110111001 step 50 100001100110100100011011011011011101111100011011011010100110111001 step 51 101001100110100100011011011011011100110111011011011010100110111001 step 52 100001100110100100011011011011011101111100011011011010100110111001 step 53 100101100110100100011011011011011100110111011011011010100110111001 step 54 100001100110100100011011011011011101111100011011011010100110111001 step 55 100011100110100100011011011011011100110111011011011010100110111001 step 56 100001100110100100011011011011011101111100011011011010100110111001 step 57 100001110110100100011011011011011100110111011011011010100110111001 step 58 100001100110100100011011011011011101111100011011011010100110111001 step 59 100001101110100100011011011011011100110111011011011010100110111001 step 60 100001100110100100011011011011011101111100011011011010100110111001 step 61 100001100111100100011011011011011100111101011011011010100110111001 step 62 100001100110100100011011011011011101111100011011011010100110111001 step 63 100001100110110100011011011011011100111101011011011010100110111001 step 64 100001100110100100011011011011011101111100011011011010100110111001 step 65 100001100110101100011011011011011101110110011011011010100110111001 step 66 100001100110100100011011011011011101111100011011011010100110111001 step 67 100001100110100110011011011011011101110110011011011010100110111001 step 68 100001100110100100011011011011011101111100011011011010100110111001 step 69 100001100110100101011011011011011101001111011011011010100110111001 step 70 100001100110100100011011011011011101111100011011011010100110111001 step 71 100001100110100100111011011011011101001111011011011010100110111001 step 72 100001100110100100011011011011011101111100011011011010100110111001 step 73 100001100110100100011111011011011101001111011011011010100110111001 step 74 100001100110100100011011011011011101111100011011011010100110111001 step 75 100001100110100100011011111011011101001111011011011010100110111001 step 76 100001100110100100011011011011011101111100011011011010100110111001 step 77 100001100110100100011011011111011101001111011011011010100110111001 step 78 100001100110100100011011011011011101111100011011011010100110111001 step 79 100001100110100100011011011011111101001111011011011010100110111001 step 80 100001100110100100011011011011011101111100011011011010100110111001 step 81 100001100110100100011011011011011111101110011011011010100110111001 step 82 100001100110100100011011011011011101111100011011011010100110111001 test 10: pass SLOT BAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBAABBAAAAAAAAAAAAAABBBBBBBBAB LETTER ALPSLFMDEEMCBFRSPKLEMFHRSCJLJKUHPNMBBNNVVRKRHUTDJUKANJHBTPDFSVDEVU SIDE 121212122121212121111111112212122222112222111221112112212112212212 DIRECTION IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIOOOOOOOIOOIOOIOOIOOOOIOOIIOOIIO this fail all fails was hi 111111111111111111111111111111111111111111111111111111111111111 1 rising ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ ^^^^^^^^^^^^^^^^^^^^ ^^ falling vvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvv vvvvvvvvvvvvvvvvvvvv vv was lo 00000000000000000000000000000000000000 00000000000000000000 0000 total fails 0, total passes 10 step 1 100000000000000000000000000000000001111100011011011010100110111001 step 2 100000000000000000000000000000000001111100100011011010100110111001 step 3 100000000000000000000000000000000001111100000011011010100110111001 step 4 100000000000000000000000000000000001111100000100011010100110111001 step 5 100000000000000000000000000000000001111100000000011010100110111001 step 6 100000000000000000000000000000000001111100000000100010100110111001 step 7 100000000000000000000000000000000001111100000000000010100110111001 step 8 100000000000000000000000000000000001111100000000000101010110111001 step 9 100000000000000000000000000000000001111100000000000001010110111001 step 10 100000000000000000000000000000000001111100000000000001011000111001 step 11 100000000000000000000000000000000001111100000000000001010000111001 step 12 100000000000000000000000000000000001111100000000000001010001100001 step 13 100000000000000000000000000000000001111100000000000001010000100001 step 14 100000000000000000000000000000000001111100000000000001010000100001 step 15 100000000000010000000000000000000000111101000000000001010000100001 step 16 100000000000010010000000000000000000110111000000000001010000100001 step 17 100000000000010010000000000000000000110111111000000001010000100001 step 18 100000000000010010000000000000000000110111011000000001010000100001 step 19 100000000000010010000000000000000000110111011111000001010000100001 step 20 100000000000010010000000000000000000110111011011000001010000100001 step 21 100000000000010010000000000000000000110111011011111001010000100001 step 22 100000000000010010000000000000000000110111011011011001010000100001 step 23 100000000000010010000000000000000000110111011011011110100000100001 step 24 100000000000010010000000000000000000110111011011011010100000100001 step 25 100000000000010010000000000000000000110111011011011010101110100001 step 26 100000000000010010000000000000000000110111011011011010100110100001 step 27 100000000000010010000000000000000000110111011011011010100111111001 step 28 100000000000010010000000000000000000110111011011011010100110111001 step 29 100000000000000010000000000000000001110110011011011010100110111001 step 30 100000000000000000000000000000000001111100011011011010100110111001 step 31 100000000000000000000000000000000001111100011011011010100110111001 step 32 100001000000000000000000000000000001111100011011011010100110111001 step 33 100001100000000000000000000000000001111100011011011010100110111001 step 34 100001100100000000000000000000000001111100011011011010100110111001 step 35 100001100110000000000000000000000001111100011011011010100110111001 step 36 100001100110100000000000000000000001111100011011011010100110111001 step 37 100001100110100100000000000000000001111100011011011010100110111001 step 38 100001100110100100010000000000000001111100011011011010100110111001 step 39 100001100110100100011000000000000001111100011011011010100110111001 step 40 100001100110100100011010000000000001111100011011011010100110111001 step 41 100001100110100100011011000000000001111100011011011010100110111001 step 42 100001100110100100011011010000000001111100011011011010100110111001 step 43 100001100110100100011011011000000001111100011011011010100110111001 step 44 100001100110100100011011011010000001111100011011011010100110111001 step 45 100001100110100100011011011011000001111100011011011010100110111001 step 46 100001100110100100011011011011010001111100011011011010100110111001 step 47 100001100110100100011011011011011001111100011011011010100110111001 step 48 100001100110100100011011011011011101111100011011011010100110111001 step 49 110001100110100100011011011011011100110111011011011010100110111001 step 50 100001100110100100011011011011011101111100011011011010100110111001 step 51 101001100110100100011011011011011100110111011011011010100110111001 step 52 100001100110100100011011011011011101111100011011011010100110111001 step 53 100101100110100100011011011011011100110111011011011010100110111001 step 54 100001100110100100011011011011011101111100011011011010100110111001 step 55 100011100110100100011011011011011100110111011011011010100110111001 step 56 100001100110100100011011011011011101111100011011011010100110111001 step 57 100001110110100100011011011011011100110111011011011010100110111001 step 58 100001100110100100011011011011011101111100011011011010100110111001 step 59 100001101110100100011011011011011100110111011011011010100110111001 step 60 100001100110100100011011011011011101111100011011011010100110111001 step 61 100001100111100100011011011011011100111101011011011010100110111001 step 62 100001100110100100011011011011011101111100011011011010100110111001 step 63 100001100110110100011011011011011100111101011011011010100110111001 step 64 100001100110100100011011011011011101111100011011011010100110111001 step 65 100001100110101100011011011011011101110110011011011010100110111001 step 66 100001100110100100011011011011011101111100011011011010100110111001 step 67 100001100110100110011011011011011101110110011011011010100110111001 step 68 100001100110100100011011011011011101111100011011011010100110111001 step 69 100001100110100101011011011011011101001111011011011010100110111001 step 70 100001100110100100011011011011011101111100011011011010100110111001 step 71 100001100110100100111011011011011101001111011011011010100110111001 step 72 100001100110100100011011011011011101111100011011011010100110111001 step 73 100001100110100100011111011011011101001111011011011010100110111001 step 74 100001100110100100011011011011011101111100011011011010100110111001 step 75 100001100110100100011011111011011101001111011011011010100110111001 step 76 100001100110100100011011011011011101111100011011011010100110111001 step 77 100001100110100100011011011111011101001111011011011010100110111001 step 78 100001100110100100011011011011011101111100011011011010100110111001 step 79 100001100110100100011011011011111101001111011011011010100110111001 step 80 100001100110100100011011011011011101111100011011011010100110111001 step 81 100001100110100100011011011011011111101110011011011010100110111001 step 82 100001100110100100011011011011011101111100011011011010100110111001 test 11: pass SLOT BAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBAABBAAAAAAAAAAAAAABBBBBBBBAB LETTER ALPSLFMDEEMCBFRSPKLEMFHRSCJLJKUHPNMBBNNVVRKRHUTDJUKANJHBTPDFSVDEVU SIDE 121212122121212121111111112212122222112222111221112112212112212212 DIRECTION IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIOOOOOOOIOOIOOIOOIOOOOIOOIIOOIIO this fail all fails was hi 111111111111111111111111111111111111111111111111111111111111111 1 rising ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ ^^^^^^^^^^^^^^^^^^^^ ^^ falling vvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvv vvvvvvvvvvvvvvvvvvvv vv was lo 00000000000000000000000000000000000000 00000000000000000000 0000 total fails 0, total passes 11 step 1 100000000000000000000000000000000001111100011011011010100110111001 step 2 100000000000000000000000000000000001111100100011011010100110111001 step 3 100000000000000000000000000000000001111100000011011010100110111001 step 4 100000000000000000000000000000000001111100000100011010100110111001 step 5 100000000000000000000000000000000001111100000000011010100110111001 step 6 100000000000000000000000000000000001111100000000100010100110111001 step 7 100000000000000000000000000000000001111100000000000010100110111001 step 8 100000000000000000000000000000000001111100000000000101010110111001 step 9 100000000000000000000000000000000001111100000000000001010110111001 step 10 100000000000000000000000000000000001111100000000000001011000111001 step 11 100000000000000000000000000000000001111100000000000001010000111001 step 12 100000000000000000000000000000000001111100000000000001010001100001 step 13 100000000000000000000000000000000001111100000000000001010000100001 step 14 100000000000000000000000000000000001111100000000000001010000100001 step 15 100000000000010000000000000000000000111101000000000001010000100001 step 16 100000000000010010000000000000000000110111000000000001010000100001 step 17 100000000000010010000000000000000000110111111000000001010000100001 step 18 100000000000010010000000000000000000110111011000000001010000100001 step 19 100000000000010010000000000000000000110111011111000001010000100001 step 20 100000000000010010000000000000000000110111011011000001010000100001 step 21 100000000000010010000000000000000000110111011011111001010000100001 step 22 100000000000010010000000000000000000110111011011011001010000100001 step 23 100000000000010010000000000000000000110111011011011110100000100001 step 24 100000000000010010000000000000000000110111011011011010100000100001 step 25 100000000000010010000000000000000000110111011011011010101110100001 step 26 100000000000010010000000000000000000110111011011011010100110100001 step 27 100000000000010010000000000000000000110111011011011010100111111001 step 28 100000000000010010000000000000000000110111011011011010100110111001 step 29 100000000000000010000000000000000001110110011011011010100110111001 step 30 100000000000000000000000000000000001111100011011011010100110111001 step 31 100000000000000000000000000000000001111100011011011010100110111001 step 32 100001000000000000000000000000000001111100011011011010100110111001 step 33 100001100000000000000000000000000001111100011011011010100110111001 step 34 100001100100000000000000000000000001111100011011011010100110111001 step 35 100001100110000000000000000000000001111100011011011010100110111001 step 36 100001100110100000000000000000000001111100011011011010100110111001 step 37 100001100110100100000000000000000001111100011011011010100110111001 step 38 100001100110100100010000000000000001111100011011011010100110111001 step 39 100001100110100100011000000000000001111100011011011010100110111001 step 40 100001100110100100011010000000000001111100011011011010100110111001 step 41 100001100110100100011011000000000001111100011011011010100110111001 step 42 100001100110100100011011010000000001111100011011011010100110111001 step 43 100001100110100100011011011000000001111100011011011010100110111001 step 44 100001100110100100011011011010000001111100011011011010100110111001 step 45 100001100110100100011011011011000001111100011011011010100110111001 step 46 100001100110100100011011011011010001111100011011011010100110111001 step 47 100001100110100100011011011011011001111100011011011010100110111001 step 48 100001100110100100011011011011011101111100011011011010100110111001 step 49 110001100110100100011011011011011100110111011011011010100110111001 step 50 100001100110100100011011011011011101111100011011011010100110111001 step 51 101001100110100100011011011011011100110111011011011010100110111001 step 52 100001100110100100011011011011011101111100011011011010100110111001 step 53 100101100110100100011011011011011100110111011011011010100110111001 step 54 100001100110100100011011011011011101111100011011011010100110111001 step 55 100011100110100100011011011011011100110111011011011010100110111001 step 56 100001100110100100011011011011011101111100011011011010100110111001 step 57 100001110110100100011011011011011100110111011011011010100110111001 step 58 100001100110100100011011011011011101111100011011011010100110111001 step 59 100001101110100100011011011011011100110111011011011010100110111001 step 60 100001100110100100011011011011011101111100011011011010100110111001 step 61 100001100111100100011011011011011100111101011011011010100110111001 step 62 100001100110100100011011011011011101111100011011011010100110111001 step 63 100001100110110100011011011011011100111101011011011010100110111001 step 64 100001100110100100011011011011011101111100011011011010100110111001 step 65 100001100110101100011011011011011101110110011011011010100110111001 step 66 100001100110100100011011011011011101111100011011011010100110111001 step 67 100001100110100110011011011011011101110110011011011010100110111001 step 68 100001100110100100011011011011011101111100011011011010100110111001 step 69 100001100110100101011011011011011101001111011011011010100110111001 step 70 100001100110100100011011011011011101111100011011011010100110111001 step 71 100001100110100100111011011011011101001111011011011010100110111001 step 72 100001100110100100011011011011011101111100011011011010100110111001 step 73 100001100110100100011111011011011101001111011011011010100110111001 step 74 100001100110100100011011011011011101111100011011011010100110111001 step 75 100001100110100100011011111011011101001111011011011010100110111001 step 76 100001100110100100011011011011011101111100011011011010100110111001 step 77 100001100110100100011011011111011101001111011011011010100110111001 step 78 100001100110100100011011011011011101111100011011011010100110111001 step 79 100001100110100100011011011011111101001111011011011010100110111001 step 80 100001100110100100011011011011011101111100011011011010100110111001 step 81 100001100110100100011011011011011111101110011011011010100110111001 step 82 100001100110100100011011011011011101111100011011011010100110111001 test 12: pass SLOT BAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBAABBAAAAAAAAAAAAAABBBBBBBBAB LETTER ALPSLFMDEEMCBFRSPKLEMFHRSCJLJKUHPNMBBNNVVRKRHUTDJUKANJHBTPDFSVDEVU SIDE 121212122121212121111111112212122222112222111221112112212112212212 DIRECTION IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIOOOOOOOIOOIOOIOOIOOOOIOOIIOOIIO this fail all fails was hi 111111111111111111111111111111111111111111111111111111111111111 1 rising ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ ^^^^^^^^^^^^^^^^^^^^ ^^ falling vvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvv vvvvvvvvvvvvvvvvvvvv vv was lo 00000000000000000000000000000000000000 00000000000000000000 0000 total fails 0, total passes 12 step 1 100000000000000000000000000000000001111100011011011010100110111001 step 2 100000000000000000000000000000000001111100100011011010100110111001 step 3 100000000000000000000000000000000001111100000011011010100110111001 step 4 100000000000000000000000000000000001111100000100011010100110111001 step 5 100000000000000000000000000000000001111100000000011010100110111001 step 6 100000000000000000000000000000000001111100000000100010100110111001 step 7 100000000000000000000000000000000001111100000000000010100110111001 step 8 100000000000000000000000000000000001111100000000000101010110111001 step 9 100000000000000000000000000000000001111100000000000001010110111001 step 10 100000000000000000000000000000000001111100000000000001011000111001 step 11 100000000000000000000000000000000001111100000000000001010000111001 step 12 100000000000000000000000000000000001111100000000000001010001100001 step 13 100000000000000000000000000000000001111100000000000001010000100001 step 14 100000000000000000000000000000000001111100000000000001010000100001 step 15 100000000000010000000000000000000000111101000000000001010000100001 step 16 100000000000010010000000000000000000110111000000000001010000100001 step 17 100000000000010010000000000000000000110111111000000001010000100001 step 18 100000000000010010000000000000000000110111011000000001010000100001 step 19 100000000000010010000000000000000000110111011111000001010000100001 step 20 100000000000010010000000000000000000110111011011000001010000100001 step 21 100000000000010010000000000000000000110111011011111001010000100001 step 22 100000000000010010000000000000000000110111011011011001010000100001 step 23 100000000000010010000000000000000000110111011011011110100000100001 step 24 100000000000010010000000000000000000110111011011011010100000100001 step 25 100000000000010010000000000000000000110111011011011010101110100001 step 26 100000000000010010000000000000000000110111011011011010100110100001 step 27 100000000000010010000000000000000000110111011011011010100111111001 step 28 100000000000010010000000000000000000110111011011011010100110111001 step 29 100000000000000010000000000000000001110110011011011010100110111001 step 30 100000000000000000000000000000000001111100011011011010100110111001 step 31 100000000000000000000000000000000001111100011011011010100110111001 step 32 100001000000000000000000000000000001111100011011011010100110111001 step 33 100001100000000000000000000000000001111100011011011010100110111001 step 34 100001100100000000000000000000000001111100011011011010100110111001 step 35 100001100110000000000000000000000001111100011011011010100110111001 step 36 100001100110100000000000000000000001111100011011011010100110111001 step 37 100001100110100100000000000000000001111100011011011010100110111001 step 38 100001100110100100010000000000000001111100011011011010100110111001 step 39 100001100110100100011000000000000001111100011011011010100110111001 step 40 100001100110100100011010000000000001111100011011011010100110111001 step 41 100001100110100100011011000000000001111100011011011010100110111001 step 42 100001100110100100011011010000000001111100011011011010100110111001 step 43 100001100110100100011011011000000001111100011011011010100110111001 step 44 100001100110100100011011011010000001111100011011011010100110111001 step 45 100001100110100100011011011011000001111100011011011010100110111001 step 46 100001100110100100011011011011010001111100011011011010100110111001 step 47 100001100110100100011011011011011001111100011011011010100110111001 step 48 100001100110100100011011011011011101111100011011011010100110111001 step 49 110001100110100100011011011011011100110111011011011010100110111001 step 50 100001100110100100011011011011011101111100011011011010100110111001 step 51 101001100110100100011011011011011100110111011011011010100110111001 step 52 100001100110100100011011011011011101111100011011011010100110111001 step 53 100101100110100100011011011011011100110111011011011010100110111001 step 54 100001100110100100011011011011011101111100011011011010100110111001 step 55 100011100110100100011011011011011100110111011011011010100110111001 step 56 100001100110100100011011011011011101111100011011011010100110111001 step 57 100001110110100100011011011011011100110111011011011010100110111001 step 58 100001100110100100011011011011011101111100011011011010100110111001 step 59 100001101110100100011011011011011100110111011011011010100110111001 step 60 100001100110100100011011011011011101111100011011011010100110111001 step 61 100001100111100100011011011011011100111101011011011010100110111001 step 62 100001100110100100011011011011011101111100011011011010100110111001 step 63 100001100110110100011011011011011100111101011011011010100110111001 step 64 100001100110100100011011011011011101111100011011011010100110111001 step 65 100001100110101100011011011011011101110110011011011010100110111001 step 66 100001100110100100011011011011011101111100011011011010100110111001 step 67 100001100110100110011011011011011101110110011011011010100110111001 step 68 100001100110100100011011011011011101111100011011011010100110111001 step 69 100001100110100101011011011011011101001111011011011010100110111001 step 70 100001100110100100011011011011011101111100011011011010100110111001 step 71 100001100110100100111011011011011101001111011011011010100110111001 step 72 100001100110100100011011011011011101111100011011011010100110111001 step 73 100001100110100100011111011011011101001111011011011010100110111001 step 74 100001100110100100011011011011011101111100011011011010100110111001 step 75 100001100110100100011011111011011101001111011011011010100110111001 step 76 100001100110100100011011011011011101111100011011011010100110111001 step 77 100001100110100100011011011111011101001111011011011010100110111001 step 78 100001100110100100011011011011011101111100011011011010100110111001 step 79 100001100110100100011011011011111101001111011011011010100110111001 step 80 100001100110100100011011011011011101111100011011011010100110111001 step 81 100001100110100100011011011011011111101110011011011010100110111001 step 82 100001100110100100011011011011011101111100011011011010100110111001 test 13: pass SLOT BAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBAABBAAAAAAAAAAAAAABBBBBBBBAB LETTER ALPSLFMDEEMCBFRSPKLEMFHRSCJLJKUHPNMBBNNVVRKRHUTDJUKANJHBTPDFSVDEVU SIDE 121212122121212121111111112212122222112222111221112112212112212212 DIRECTION IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIOOOOOOOIOOIOOIOOIOOOOIOOIIOOIIO this fail all fails was hi 111111111111111111111111111111111111111111111111111111111111111 1 rising ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ ^^^^^^^^^^^^^^^^^^^^ ^^ falling vvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvv vvvvvvvvvvvvvvvvvvvv vv was lo 00000000000000000000000000000000000000 00000000000000000000 0000 total fails 0, total passes 13 step 1 100000000000000000000000000000000001111100011011011010100110111001 step 2 100000000000000000000000000000000001111100100011011010100110111001 step 3 100000000000000000000000000000000001111100000011011010100110111001 step 4 100000000000000000000000000000000001111100000100011010100110111001 step 5 100000000000000000000000000000000001111100000000011010100110111001 step 6 100000000000000000000000000000000001111100000000100010100110111001 step 7 100000000000000000000000000000000001111100000000000010100110111001 step 8 100000000000000000000000000000000001111100000000000101010110111001 step 9 100000000000000000000000000000000001111100000000000001010110111001 step 10 100000000000000000000000000000000001111100000000000001011000111001 step 11 100000000000000000000000000000000001111100000000000001010000111001 step 12 100000000000000000000000000000000001111100000000000001010001100001 step 13 100000000000000000000000000000000001111100000000000001010000100001 step 14 100000000000000000000000000000000001111100000000000001010000100001 step 15 100000000000010000000000000000000000111101000000000001010000100001 step 16 100000000000010010000000000000000000110111000000000001010000100001 step 17 100000000000010010000000000000000000110111111000000001010000100001 step 18 100000000000010010000000000000000000110111011000000001010000100001 step 19 100000000000010010000000000000000000110111011111000001010000100001 step 20 100000000000010010000000000000000000110111011011000001010000100001 step 21 100000000000010010000000000000000000110111011011111001010000100001 step 22 100000000000010010000000000000000000110111011011011001010000100001 step 23 100000000000010010000000000000000000110111011011011110100000100001 step 24 100000000000010010000000000000000000110111011011011010100000100001 step 25 100000000000010010000000000000000000110111011011011010101110100001 step 26 100000000000010010000000000000000000110111011011011010100110100001 step 27 100000000000010010000000000000000000110111011011011010100111111001 step 28 100000000000010010000000000000000000110111011011011010100110111001 step 29 100000000000000010000000000000000001110110011011011010100110111001 step 30 100000000000000000000000000000000001111100011011011010100110111001 step 31 100000000000000000000000000000000001111100011011011010100110111001 step 32 100001000000000000000000000000000001111100011011011010100110111001 step 33 100001100000000000000000000000000001111100011011011010100110111001 step 34 100001100100000000000000000000000001111100011011011010100110111001 step 35 100001100110000000000000000000000001111100011011011010100110111001 step 36 100001100110100000000000000000000001111100011011011010100110111001 step 37 100001100110100100000000000000000001111100011011011010100110111001 step 38 100001100110100100010000000000000001111100011011011010100110111001 step 39 100001100110100100011000000000000001111100011011011010100110111001 step 40 100001100110100100011010000000000001111100011011011010100110111001 step 41 100001100110100100011011000000000001111100011011011010100110111001 step 42 100001100110100100011011010000000001111100011011011010100110111001 step 43 100001100110100100011011011000000001111100011011011010100110111001 step 44 100001100110100100011011011010000001111100011011011010100110111001 step 45 100001100110100100011011011011000001111100011011011010100110111001 step 46 100001100110100100011011011011010001111100011011011010100110111001 step 47 100001100110100100011011011011011001111100011011011010100110111001 step 48 100001100110100100011011011011011101111100011011011010100110111001 step 49 110001100110100100011011011011011100110111011011011010100110111001 step 50 100001100110100100011011011011011101111100011011011010100110111001 step 51 101001100110100100011011011011011100110111011011011010100110111001 step 52 100001100110100100011011011011011101111100011011011010100110111001 step 53 100101100110100100011011011011011100110111011011011010100110111001 step 54 100001100110100100011011011011011101111100011011011010100110111001 step 55 100011100110100100011011011011011100110111011011011010100110111001 step 56 100001100110100100011011011011011101111100011011011010100110111001 step 57 100001110110100100011011011011011100110111011011011010100110111001 step 58 100001100110100100011011011011011101111100011011011010100110111001 step 59 100001101110100100011011011011011100110111011011011010100110111001 step 60 100001100110100100011011011011011101111100011011011010100110111001 step 61 100001100111100100011011011011011100111101011011011010100110111001 step 62 100001100110100100011011011011011101111100011011011010100110111001 step 63 100001100110110100011011011011011100111101011011011010100110111001 step 64 100001100110100100011011011011011101111100011011011010100110111001 step 65 100001100110101100011011011011011101110110011011011010100110111001 step 66 100001100110100100011011011011011101111100011011011010100110111001 step 67 100001100110100110011011011011011101110110011011011010100110111001 step 68 100001100110100100011011011011011101111100011011011010100110111001 step 69 100001100110100101011011011011011101001111011011011010100110111001 step 70 100001100110100100011011011011011101111100011011011010100110111001 step 71 100001100110100100111011011011011101001111011011011010100110111001 step 72 100001100110100100011011011011011101111100011011011010100110111001 step 73 100001100110100100011111011011011101001111011011011010100110111001 step 74 100001100110100100011011011011011101111100011011011010100110111001 step 75 100001100110100100011011111011011101001111011011011010100110111001 step 76 100001100110100100011011011011011101111100011011011010100110111001 step 77 100001100110100100011011011111011101001111011011011010100110111001 step 78 100001100110100100011011011011011101111100011011011010100110111001 step 79 100001100110100100011011011011111101001111011011011010100110111001 step 80 100001100110100100011011011011011101111100011011011010100110111001 step 81 100001100110100100011011011011011111101110011011011010100110111001 step 82 100001100110100100011011011011011101111100011011011010100110111001 test 14: pass SLOT BAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBAABBAAAAAAAAAAAAAABBBBBBBBAB LETTER ALPSLFMDEEMCBFRSPKLEMFHRSCJLJKUHPNMBBNNVVRKRHUTDJUKANJHBTPDFSVDEVU SIDE 121212122121212121111111112212122222112222111221112112212112212212 DIRECTION IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIOOOOOOOIOOIOOIOOIOOOOIOOIIOOIIO this fail all fails was hi 111111111111111111111111111111111111111111111111111111111111111 1 rising ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ ^^^^^^^^^^^^^^^^^^^^ ^^ falling vvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvv vvvvvvvvvvvvvvvvvvvv vv was lo 00000000000000000000000000000000000000 00000000000000000000 0000 total fails 0, total passes 14 step 1 100000000000000000000000000000000001111100011011011010100110111001 step 2 100000000000000000000000000000000001111100100011011010100110111001 step 3 100000000000000000000000000000000001111100000011011010100110111001 step 4 100000000000000000000000000000000001111100000100011010100110111001 step 5 100000000000000000000000000000000001111100000000011010100110111001 step 6 100000000000000000000000000000000001111100000000100010100110111001 step 7 100000000000000000000000000000000001111100000000000010100110111001 step 8 100000000000000000000000000000000001111100000000000101010110111001 step 9 100000000000000000000000000000000001111100000000000001010110111001 step 10 100000000000000000000000000000000001111100000000000001011000111001 step 11 100000000000000000000000000000000001111100000000000001010000111001 step 12 100000000000000000000000000000000001111100000000000001010001100001 step 13 100000000000000000000000000000000001111100000000000001010000100001 step 14 100000000000000000000000000000000001111100000000000001010000100001 step 15 100000000000010000000000000000000000111101000000000001010000100001 step 16 100000000000010010000000000000000000110111000000000001010000100001 step 17 100000000000010010000000000000000000110111111000000001010000100001 step 18 100000000000010010000000000000000000110111011000000001010000100001 step 19 100000000000010010000000000000000000110111011111000001010000100001 step 20 100000000000010010000000000000000000110111011011000001010000100001 step 21 100000000000010010000000000000000000110111011011111001010000100001 step 22 100000000000010010000000000000000000110111011011011001010000100001 step 23 100000000000010010000000000000000000110111011011011110100000100001 step 24 100000000000010010000000000000000000110111011011011010100000100001 step 25 100000000000010010000000000000000000110111011011011010101110100001 step 26 100000000000010010000000000000000000110111011011011010100110100001 step 27 100000000000010010000000000000000000110111011011011010100111111001 step 28 100000000000010010000000000000000000110111011011011010100110111001 step 29 100000000000000010000000000000000001110110011011011010100110111001 step 30 100000000000000000000000000000000001111100011011011010100110111001 step 31 100000000000000000000000000000000001111100011011011010100110111001 step 32 100001000000000000000000000000000001111100011011011010100110111001 step 33 100001100000000000000000000000000001111100011011011010100110111001 step 34 100001100100000000000000000000000001111100011011011010100110111001 step 35 100001100110000000000000000000000001111100011011011010100110111001 step 36 100001100110100000000000000000000001111100011011011010100110111001 step 37 100001100110100100000000000000000001111100011011011010100110111001 step 38 100001100110100100010000000000000001111100011011011010100110111001 step 39 100001100110100100011000000000000001111100011011011010100110111001 step 40 100001100110100100011010000000000001111100011011011010100110111001 step 41 100001100110100100011011000000000001111100011011011010100110111001 step 42 100001100110100100011011010000000001111100011011011010100110111001 step 43 100001100110100100011011011000000001111100011011011010100110111001 step 44 100001100110100100011011011010000001111100011011011010100110111001 step 45 100001100110100100011011011011000001111100011011011010100110111001 step 46 100001100110100100011011011011010001111100011011011010100110111001 step 47 100001100110100100011011011011011001111100011011011010100110111001 step 48 100001100110100100011011011011011101111100011011011010100110111001 step 49 110001100110100100011011011011011100110111011011011010100110111001 step 50 100001100110100100011011011011011101111100011011011010100110111001 step 51 101001100110100100011011011011011100110111011011011010100110111001 step 52 100001100110100100011011011011011101111100011011011010100110111001 step 53 100101100110100100011011011011011100110111011011011010100110111001 step 54 100001100110100100011011011011011101111100011011011010100110111001 step 55 100011100110100100011011011011011100110111011011011010100110111001 step 56 100001100110100100011011011011011101111100011011011010100110111001 step 57 100001110110100100011011011011011100110111011011011010100110111001 step 58 100001100110100100011011011011011101111100011011011010100110111001 step 59 100001101110100100011011011011011100110111011011011010100110111001 step 60 100001100110100100011011011011011101111100011011011010100110111001 step 61 100001100111100100011011011011011100111101011011011010100110111001 step 62 100001100110100100011011011011011101111100011011011010100110111001 step 63 100001100110110100011011011011011100111101011011011010100110111001 step 64 100001100110100100011011011011011101111100011011011010100110111001 step 65 100001100110101100011011011011011101110110011011011010100110111001 step 66 100001100110100100011011011011011101111100011011011010100110111001 step 67 100001100110100110011011011011011101110110011011011010100110111001 step 68 100001100110100100011011011011011101111100011011011010100110111001 step 69 100001100110100101011011011011011101001111011011011010100110111001 step 70 100001100110100100011011011011011101111100011011011010100110111001 step 71 100001100110100100111011011011011101001111011011011010100110111001 step 72 100001100110100100011011011011011101111100011011011010100110111001 step 73 100001100110100100011111011011011101001111011011011010100110111001 step 74 100001100110100100011011011011011101111100011011011010100110111001 step 75 100001100110100100011011111011011101001111011011011010100110111001 step 76 100001100110100100011011011011011101111100011011011010100110111001 step 77 100001100110100100011011011111011101001111011011011010100110111001 step 78 100001100110100100011011011011011101111100011011011010100110111001 step 79 100001100110100100011011011011111101001111011011011010100110111001 step 80 100001100110100100011011011011011101111100011011011010100110111001 step 81 100001100110100100011011011011011111101110011011011010100110111001 step 82 100001100110100100011011011011011101111100011011011010100110111001 test 15: pass SLOT BAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBAABBAAAAAAAAAAAAAABBBBBBBBAB LETTER ALPSLFMDEEMCBFRSPKLEMFHRSCJLJKUHPNMBBNNVVRKRHUTDJUKANJHBTPDFSVDEVU SIDE 121212122121212121111111112212122222112222111221112112212112212212 DIRECTION IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIOOOOOOOIOOIOOIOOIOOOOIOOIIOOIIO this fail all fails was hi 111111111111111111111111111111111111111111111111111111111111111 1 rising ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ ^^^^^^^^^^^^^^^^^^^^ ^^ falling vvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvv vvvvvvvvvvvvvvvvvvvv vv was lo 00000000000000000000000000000000000000 00000000000000000000 0000 total fails 0, total passes 15 step 1 100000000000000000000000000000000001111100011011011010100110111001 step 2 100000000000000000000000000000000001111100100011011010100110111001 step 3 100000000000000000000000000000000001111100000011011010100110111001 step 4 100000000000000000000000000000000001111100000100011010100110111001 step 5 100000000000000000000000000000000001111100000000011010100110111001 step 6 100000000000000000000000000000000001111100000000100010100110111001 step 7 100000000000000000000000000000000001111100000000000010100110111001 step 8 100000000000000000000000000000000001111100000000000101010110111001 step 9 100000000000000000000000000000000001111100000000000001010110111001 step 10 100000000000000000000000000000000001111100000000000001011000111001 step 11 100000000000000000000000000000000001111100000000000001010000111001 step 12 100000000000000000000000000000000001111100000000000001010001100001 step 13 100000000000000000000000000000000001111100000000000001010000100001 step 14 100000000000000000000000000000000001111100000000000001010000100001 step 15 100000000000010000000000000000000000111101000000000001010000100001 step 16 100000000000010010000000000000000000110111000000000001010000100001 step 17 100000000000010010000000000000000000110111111000000001010000100001 step 18 100000000000010010000000000000000000110111011000000001010000100001 step 19 100000000000010010000000000000000000110111011111000001010000100001 step 20 100000000000010010000000000000000000110111011011000001010000100001 step 21 100000000000010010000000000000000000110111011011111001010000100001 step 22 100000000000010010000000000000000000110111011011011001010000100001 step 23 100000000000010010000000000000000000110111011011011110100000100001 step 24 100000000000010010000000000000000000110111011011011010100000100001 step 25 100000000000010010000000000000000000110111011011011010101110100001 step 26 100000000000010010000000000000000000110111011011011010100110100001 step 27 100000000000010010000000000000000000110111011011011010100111111001 step 28 100000000000010010000000000000000000110111011011011010100110111001 step 29 100000000000000010000000000000000001110110011011011010100110111001 step 30 100000000000000000000000000000000001111100011011011010100110111001 step 31 100000000000000000000000000000000001111100011011011010100110111001 step 32 100001000000000000000000000000000001111100011011011010100110111001 step 33 100001100000000000000000000000000001111100011011011010100110111001 step 34 100001100100000000000000000000000001111100011011011010100110111001 step 35 100001100110000000000000000000000001111100011011011010100110111001 step 36 100001100110100000000000000000000001111100011011011010100110111001 step 37 100001100110100100000000000000000001111100011011011010100110111001 step 38 100001100110100100010000000000000001111100011011011010100110111001 step 39 100001100110100100011000000000000001111100011011011010100110111001 step 40 100001100110100100011010000000000001111100011011011010100110111001 step 41 100001100110100100011011000000000001111100011011011010100110111001 step 42 100001100110100100011011010000000001111100011011011010100110111001 step 43 100001100110100100011011011000000001111100011011011010100110111001 step 44 100001100110100100011011011010000001111100011011011010100110111001 step 45 100001100110100100011011011011000001111100011011011010100110111001 step 46 100001100110100100011011011011010001111100011011011010100110111001 step 47 100001100110100100011011011011011001111100011011011010100110111001 step 48 100001100110100100011011011011011101111100011011011010100110111001 step 49 110001100110100100011011011011011100110111011011011010100110111001 step 50 100001100110100100011011011011011101111100011011011010100110111001 step 51 101001100110100100011011011011011100110111011011011010100110111001 step 52 100001100110100100011011011011011101111100011011011010100110111001 step 53 100101100110100100011011011011011100110111011011011010100110111001 step 54 100001100110100100011011011011011101111100011011011010100110111001 step 55 100011100110100100011011011011011100110111011011011010100110111001 step 56 100001100110100100011011011011011101111100011011011010100110111001 step 57 100001110110100100011011011011011100110111011011011010100110111001 step 58 100001100110100100011011011011011101111100011011011010100110111001 step 59 100001101110100100011011011011011100110111011011011010100110111001 step 60 100001100110100100011011011011011101111100011011011010100110111001 step 61 100001100111100100011011011011011100111101011011011010100110111001 step 62 100001100110100100011011011011011101111100011011011010100110111001 step 63 100001100110110100011011011011011100111101011011011010100110111001 step 64 100001100110100100011011011011011101111100011011011010100110111001 step 65 100001100110101100011011011011011101110110011011011010100110111001 step 66 100001100110100100011011011011011101111100011011011010100110111001 step 67 100001100110100110011011011011011101110110011011011010100110111001 step 68 100001100110100100011011011011011101111100011011011010100110111001 step 69 100001100110100101011011011011011101001111011011011010100110111001 step 70 100001100110100100011011011011011101111100011011011010100110111001 step 71 100001100110100100111011011011011101001111011011011010100110111001 step 72 100001100110100100011011011011011101111100011011011010100110111001 step 73 100001100110100100011111011011011101001111011011011010100110111001 step 74 100001100110100100011011011011011101111100011011011010100110111001 step 75 100001100110100100011011111011011101001111011011011010100110111001 step 76 100001100110100100011011011011011101111100011011011010100110111001 step 77 100001100110100100011011011111011101001111011011011010100110111001 step 78 100001100110100100011011011011011101111100011011011010100110111001 step 79 100001100110100100011011011011111101001111011011011010100110111001 step 80 100001100110100100011011011011011101111100011011011010100110111001 step 81 100001100110100100011011011011011111101110011011011010100110111001 step 82 100001100110100100011011011011011101111100011011011010100110111001 test 16: pass SLOT BAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBAABBAAAAAAAAAAAAAABBBBBBBBAB LETTER ALPSLFMDEEMCBFRSPKLEMFHRSCJLJKUHPNMBBNNVVRKRHUTDJUKANJHBTPDFSVDEVU SIDE 121212122121212121111111112212122222112222111221112112212112212212 DIRECTION IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIOOOOOOOIOOIOOIOOIOOOOIOOIIOOIIO this fail all fails was hi 111111111111111111111111111111111111111111111111111111111111111 1 rising ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ ^^^^^^^^^^^^^^^^^^^^ ^^ falling vvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvv vvvvvvvvvvvvvvvvvvvv vv was lo 00000000000000000000000000000000000000 00000000000000000000 0000 total fails 0, total passes 16 step 1 100000000000000000000000000000000001111100011011011010100110111001 step 2 100000000000000000000000000000000001111100100011011010100110111001 step 3 100000000000000000000000000000000001111100000011011010100110111001 step 4 100000000000000000000000000000000001111100000100011010100110111001 step 5 100000000000000000000000000000000001111100000000011010100110111001 step 6 100000000000000000000000000000000001111100000000100010100110111001 step 7 100000000000000000000000000000000001111100000000000010100110111001 step 8 100000000000000000000000000000000001111100000000000101010110111001 step 9 100000000000000000000000000000000001111100000000000001010110111001 step 10 100000000000000000000000000000000001111100000000000001011000111001 step 11 100000000000000000000000000000000001111100000000000001010000111001 step 12 100000000000000000000000000000000001111100000000000001010001100001 step 13 100000000000000000000000000000000001111100000000000001010000100001 step 14 100000000000000000000000000000000001111100000000000001010000100001 step 15 100000000000010000000000000000000000111101000000000001010000100001 step 16 100000000000010010000000000000000000110111000000000001010000100001 step 17 100000000000010010000000000000000000110111111000000001010000100001 step 18 100000000000010010000000000000000000110111011000000001010000100001 step 19 100000000000010010000000000000000000110111011111000001010000100001 step 20 100000000000010010000000000000000000110111011011000001010000100001 step 21 100000000000010010000000000000000000110111011011111001010000100001 step 22 100000000000010010000000000000000000110111011011011001010000100001 step 23 100000000000010010000000000000000000110111011011011110100000100001 step 24 100000000000010010000000000000000000110111011011011010100000100001 step 25 100000000000010010000000000000000000110111011011011010101110100001 step 26 100000000000010010000000000000000000110111011011011010100110100001 step 27 100000000000010010000000000000000000110111011011011010100111111001 step 28 100000000000010010000000000000000000110111011011011010100110111001 step 29 100000000000000010000000000000000001110110011011011010100110111001 step 30 100000000000000000000000000000000001111100011011011010100110111001 step 31 100000000000000000000000000000000001111100011011011010100110111001 step 32 100001000000000000000000000000000001111100011011011010100110111001 step 33 100001100000000000000000000000000001111100011011011010100110111001 step 34 100001100100000000000000000000000001111100011011011010100110111001 step 35 100001100110000000000000000000000001111100011011011010100110111001 step 36 100001100110100000000000000000000001111100011011011010100110111001 step 37 100001100110100100000000000000000001111100011011011010100110111001 step 38 100001100110100100010000000000000001111100011011011010100110111001 step 39 100001100110100100011000000000000001111100011011011010100110111001 step 40 100001100110100100011010000000000001111100011011011010100110111001 step 41 100001100110100100011011000000000001111100011011011010100110111001 step 42 100001100110100100011011010000000001111100011011011010100110111001 step 43 100001100110100100011011011000000001111100011011011010100110111001 step 44 100001100110100100011011011010000001111100011011011010100110111001 step 45 100001100110100100011011011011000001111100011011011010100110111001 step 46 100001100110100100011011011011010001111100011011011010100110111001 step 47 100001100110100100011011011011011001111100011011011010100110111001 step 48 100001100110100100011011011011011101111100011011011010100110111001 step 49 110001100110100100011011011011011100110111011011011010100110111001 step 50 100001100110100100011011011011011101111100011011011010100110111001 step 51 101001100110100100011011011011011100110111011011011010100110111001 step 52 100001100110100100011011011011011101111100011011011010100110111001 step 53 100101100110100100011011011011011100110111011011011010100110111001 step 54 100001100110100100011011011011011101111100011011011010100110111001 step 55 100011100110100100011011011011011100110111011011011010100110111001 step 56 100001100110100100011011011011011101111100011011011010100110111001 step 57 100001110110100100011011011011011100110111011011011010100110111001 step 58 100001100110100100011011011011011101111100011011011010100110111001 step 59 100001101110100100011011011011011100110111011011011010100110111001 step 60 100001100110100100011011011011011101111100011011011010100110111001 step 61 100001100111100100011011011011011100111101011011011010100110111001 step 62 100001100110100100011011011011011101111100011011011010100110111001 step 63 100001100110110100011011011011011100111101011011011010100110111001 step 64 100001100110100100011011011011011101111100011011011010100110111001 step 65 100001100110101100011011011011011101110110011011011010100110111001 step 66 100001100110100100011011011011011101111100011011011010100110111001 step 67 100001100110100110011011011011011101110110011011011010100110111001 step 68 100001100110100100011011011011011101111100011011011010100110111001 step 69 100001100110100101011011011011011101001111011011011010100110111001 step 70 100001100110100100011011011011011101111100011011011010100110111001 step 71 100001100110100100111011011011011101001111011011011010100110111001 step 72 100001100110100100011011011011011101111100011011011010100110111001 step 73 100001100110100100011111011011011101001111011011011010100110111001 step 74 100001100110100100011011011011011101111100011011011010100110111001 step 75 100001100110100100011011111011011101001111011011011010100110111001 step 76 100001100110100100011011011011011101111100011011011010100110111001 step 77 100001100110100100011011011111011101001111011011011010100110111001 step 78 100001100110100100011011011011011101111100011011011010100110111001 step 79 100001100110100100011011011011111101001111011011011010100110111001 step 80 100001100110100100011011011011011101111100011011011010100110111001 step 81 100001100110100100011011011011011111101110011011011010100110111001 step 82 100001100110100100011011011011011101111100011011011010100110111001 test 17: pass SLOT BAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBAABBAAAAAAAAAAAAAABBBBBBBBAB LETTER ALPSLFMDEEMCBFRSPKLEMFHRSCJLJKUHPNMBBNNVVRKRHUTDJUKANJHBTPDFSVDEVU SIDE 121212122121212121111111112212122222112222111221112112212112212212 DIRECTION IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIOOOOOOOIOOIOOIOOIOOOOIOOIIOOIIO this fail all fails was hi 111111111111111111111111111111111111111111111111111111111111111 1 rising ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ ^^^^^^^^^^^^^^^^^^^^ ^^ falling vvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvv vvvvvvvvvvvvvvvvvvvv vv was lo 00000000000000000000000000000000000000 00000000000000000000 0000 total fails 0, total passes 17 step 1 100000000000000000000000000000000001111100011011011010100110111001 step 2 100000000000000000000000000000000001111100100011011010100110111001 step 3 100000000000000000000000000000000001111100000011011010100110111001 step 4 100000000000000000000000000000000001111100000100011010100110111001 step 5 100000000000000000000000000000000001111100000000011010100110111001 step 6 100000000000000000000000000000000001111100000000100010100110111001 step 7 100000000000000000000000000000000001111100000000000010100110111001 step 8 100000000000000000000000000000000001111100000000000101010110111001 step 9 100000000000000000000000000000000001111100000000000001010110111001 step 10 100000000000000000000000000000000001111100000000000001011000111001 step 11 100000000000000000000000000000000001111100000000000001010000111001 step 12 100000000000000000000000000000000001111100000000000001010001100001 step 13 100000000000000000000000000000000001111100000000000001010000100001 step 14 100000000000000000000000000000000001111100000000000001010000100001 step 15 100000000000010000000000000000000000111101000000000001010000100001 step 16 100000000000010010000000000000000000110111000000000001010000100001 step 17 100000000000010010000000000000000000110111111000000001010000100001 step 18 100000000000010010000000000000000000110111011000000001010000100001 step 19 100000000000010010000000000000000000110111011111000001010000100001 step 20 100000000000010010000000000000000000110111011011000001010000100001 step 21 100000000000010010000000000000000000110111011011111001010000100001 step 22 100000000000010010000000000000000000110111011011011001010000100001 step 23 100000000000010010000000000000000000110111011011011110100000100001 step 24 100000000000010010000000000000000000110111011011011010100000100001 step 25 100000000000010010000000000000000000110111011011011010101110100001 step 26 100000000000010010000000000000000000110111011011011010100110100001 step 27 100000000000010010000000000000000000110111011011011010100111111001 step 28 100000000000010010000000000000000000110111011011011010100110111001 step 29 100000000000000010000000000000000001110110011011011010100110111001 step 30 100000000000000000000000000000000001111100011011011010100110111001 step 31 100000000000000000000000000000000001111100011011011010100110111001 step 32 100001000000000000000000000000000001111100011011011010100110111001 step 33 100001100000000000000000000000000001111100011011011010100110111001 step 34 100001100100000000000000000000000001111100011011011010100110111001 step 35 100001100110000000000000000000000001111100011011011010100110111001 step 36 100001100110100000000000000000000001111100011011011010100110111001 step 37 100001100110100100000000000000000001111100011011011010100110111001 step 38 100001100110100100010000000000000001111100011011011010100110111001 step 39 100001100110100100011000000000000001111100011011011010100110111001 step 40 100001100110100100011010000000000001111100011011011010100110111001 step 41 100001100110100100011011000000000001111100011011011010100110111001 step 42 100001100110100100011011010000000001111100011011011010100110111001 step 43 100001100110100100011011011000000001111100011011011010100110111001 step 44 100001100110100100011011011010000001111100011011011010100110111001 step 45 100001100110100100011011011011000001111100011011011010100110111001 step 46 100001100110100100011011011011010001111100011011011010100110111001 step 47 100001100110100100011011011011011001111100011011011010100110111001 step 48 100001100110100100011011011011011101111100011011011010100110111001 step 49 110001100110100100011011011011011100110111011011011010100110111001 step 50 100001100110100100011011011011011101111100011011011010100110111001 step 51 101001100110100100011011011011011100110111011011011010100110111001 step 52 100001100110100100011011011011011101111100011011011010100110111001 step 53 100101100110100100011011011011011100110111011011011010100110111001 step 54 100001100110100100011011011011011101111100011011011010100110111001 step 55 100011100110100100011011011011011100110111011011011010100110111001 step 56 100001100110100100011011011011011101111100011011011010100110111001 step 57 100001110110100100011011011011011100110111011011011010100110111001 step 58 100001100110100100011011011011011101111100011011011010100110111001 step 59 100001101110100100011011011011011100110111011011011010100110111001 step 60 100001100110100100011011011011011101111100011011011010100110111001 step 61 100001100111100100011011011011011100111101011011011010100110111001 step 62 100001100110100100011011011011011101111100011011011010100110111001 step 63 100001100110110100011011011011011100111101011011011010100110111001 step 64 100001100110100100011011011011011101111100011011011010100110111001 step 65 100001100110101100011011011011011101110110011011011010100110111001 step 66 100001100110100100011011011011011101111100011011011010100110111001 step 67 100001100110100110011011011011011101110110011011011010100110111001 step 68 100001100110100100011011011011011101111100011011011010100110111001 step 69 100001100110100101011011011011011101001111011011011010100110111001 step 70 100001100110100100011011011011011101111100011011011010100110111001 step 71 100001100110100100111011011011011101001111011011011010100110111001 step 72 100001100110100100011011011011011101111100011011011010100110111001 step 73 100001100110100100011111011011011101001111011011011010100110111001 step 74 100001100110100100011011011011011101111100011011011010100110111001 step 75 100001100110100100011011111011011101001111011011011010100110111001 step 76 100001100110100100011011011011011101111100011011011010100110111001 step 77 100001100110100100011011011111011101001111011011011010100110111001 step 78 100001100110100100011011011011011101111100011011011010100110111001 step 79 100001100110100100011011011011111101001111011011011010100110111001 step 80 100001100110100100011011011011011101111100011011011010100110111001 step 81 100001100110100100011011011011011111101110011011011010100110111001 step 82 100001100110100100011011011011011101111100011011011010100110111001 test 18: pass SLOT BAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBAABBAAAAAAAAAAAAAABBBBBBBBAB LETTER ALPSLFMDEEMCBFRSPKLEMFHRSCJLJKUHPNMBBNNVVRKRHUTDJUKANJHBTPDFSVDEVU SIDE 121212122121212121111111112212122222112222111221112112212112212212 DIRECTION IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIOOOOOOOIOOIOOIOOIOOOOIOOIIOOIIO this fail all fails was hi 111111111111111111111111111111111111111111111111111111111111111 1 rising ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ ^^^^^^^^^^^^^^^^^^^^ ^^ falling vvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvv vvvvvvvvvvvvvvvvvvvv vv was lo 00000000000000000000000000000000000000 00000000000000000000 0000 total fails 0, total passes 18 step 1 100000000000000000000000000000000001111100011011011010100110111001 step 2 100000000000000000000000000000000001111100100011011010100110111001 step 3 100000000000000000000000000000000001111100000011011010100110111001 step 4 100000000000000000000000000000000001111100000100011010100110111001 step 5 100000000000000000000000000000000001111100000000011010100110111001 step 6 100000000000000000000000000000000001111100000000100010100110111001 step 7 100000000000000000000000000000000001111100000000000010100110111001 step 8 100000000000000000000000000000000001111100000000000101010110111001 step 9 100000000000000000000000000000000001111100000000000001010110111001 step 10 100000000000000000000000000000000001111100000000000001011000111001 step 11 100000000000000000000000000000000001111100000000000001010000111001 step 12 100000000000000000000000000000000001111100000000000001010001100001 step 13 100000000000000000000000000000000001111100000000000001010000100001 step 14 100000000000000000000000000000000001111100000000000001010000100001 step 15 100000000000010000000000000000000000111101000000000001010000100001 step 16 100000000000010010000000000000000000110111000000000001010000100001 step 17 100000000000010010000000000000000000110111111000000001010000100001 step 18 100000000000010010000000000000000000110111011000000001010000100001 step 19 100000000000010010000000000000000000110111011111000001010000100001 step 20 100000000000010010000000000000000000110111011011000001010000100001 step 21 100000000000010010000000000000000000110111011011111001010000100001 step 22 100000000000010010000000000000000000110111011011011001010000100001 step 23 100000000000010010000000000000000000110111011011011110100000100001 step 24 100000000000010010000000000000000000110111011011011010100000100001 step 25 100000000000010010000000000000000000110111011011011010101110100001 step 26 100000000000010010000000000000000000110111011011011010100110100001 step 27 100000000000010010000000000000000000110111011011011010100111111001 step 28 100000000000010010000000000000000000110111011011011010100110111001 step 29 100000000000000010000000000000000001110110011011011010100110111001 step 30 100000000000000000000000000000000001111100011011011010100110111001 step 31 100000000000000000000000000000000001111100011011011010100110111001 step 32 100001000000000000000000000000000001111100011011011010100110111001 step 33 100001100000000000000000000000000001111100011011011010100110111001 step 34 100001100100000000000000000000000001111100011011011010100110111001 step 35 100001100110000000000000000000000001111100011011011010100110111001 step 36 100001100110100000000000000000000001111100011011011010100110111001 step 37 100001100110100100000000000000000001111100011011011010100110111001 step 38 100001100110100100010000000000000001111100011011011010100110111001 step 39 100001100110100100011000000000000001111100011011011010100110111001 step 40 100001100110100100011010000000000001111100011011011010100110111001 step 41 100001100110100100011011000000000001111100011011011010100110111001 step 42 100001100110100100011011010000000001111100011011011010100110111001 step 43 100001100110100100011011011000000001111100011011011010100110111001 step 44 100001100110100100011011011010000001111100011011011010100110111001 step 45 100001100110100100011011011011000001111100011011011010100110111001 step 46 100001100110100100011011011011010001111100011011011010100110111001 step 47 100001100110100100011011011011011001111100011011011010100110111001 step 48 100001100110100100011011011011011101111100011011011010100110111001 step 49 110001100110100100011011011011011100110111011011011010100110111001 step 50 100001100110100100011011011011011101111100011011011010100110111001 step 51 101001100110100100011011011011011100110111011011011010100110111001 step 52 100001100110100100011011011011011101111100011011011010100110111001 step 53 100101100110100100011011011011011100110111011011011010100110111001 step 54 100001100110100100011011011011011101111100011011011010100110111001 step 55 100011100110100100011011011011011100110111011011011010100110111001 step 56 100001100110100100011011011011011101111100011011011010100110111001 step 57 100001110110100100011011011011011100110111011011011010100110111001 step 58 100001100110100100011011011011011101111100011011011010100110111001 step 59 100001101110100100011011011011011100110111011011011010100110111001 step 60 100001100110100100011011011011011101111100011011011010100110111001 step 61 100001100111100100011011011011011100111101011011011010100110111001 step 62 100001100110100100011011011011011101111100011011011010100110111001 step 63 100001100110110100011011011011011100111101011011011010100110111001 step 64 100001100110100100011011011011011101111100011011011010100110111001 step 65 100001100110101100011011011011011101110110011011011010100110111001 step 66 100001100110100100011011011011011101111100011011011010100110111001 step 67 100001100110100110011011011011011101110110011011011010100110111001 step 68 100001100110100100011011011011011101111100011011011010100110111001 step 69 100001100110100101011011011011011101001111011011011010100110111001 step 70 100001100110100100011011011011011101111100011011011010100110111001 step 71 100001100110100100111011011011011101001111011011011010100110111001 step 72 100001100110100100011011011011011101111100011011011010100110111001 step 73 100001100110100100011111011011011101001111011011011010100110111001 step 74 100001100110100100011011011011011101111100011011011010100110111001 step 75 100001100110100100011011111011011101001111011011011010100110111001 step 76 100001100110100100011011011011011101111100011011011010100110111001 step 77 100001100110100100011011011111011101001111011011011010100110111001 step 78 100001100110100100011011011011011101111100011011011010100110111001 step 79 100001100110100100011011011011111101001111011011011010100110111001 step 80 100001100110100100011011011011011101111100011011011010100110111001 step 81 100001100110100100011011011011011111101110011011011010100110111001 step 82 100001100110100100011011011011011101111100011011011010100110111001 test 19: pass SLOT BAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBAABBAAAAAAAAAAAAAABBBBBBBBAB LETTER ALPSLFMDEEMCBFRSPKLEMFHRSCJLJKUHPNMBBNNVVRKRHUTDJUKANJHBTPDFSVDEVU SIDE 121212122121212121111111112212122222112222111221112112212112212212 DIRECTION IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIOOOOOOOIOOIOOIOOIOOOOIOOIIOOIIO this fail all fails was hi 111111111111111111111111111111111111111111111111111111111111111 1 rising ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ ^^^^^^^^^^^^^^^^^^^^ ^^ falling vvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvv vvvvvvvvvvvvvvvvvvvv vv was lo 00000000000000000000000000000000000000 00000000000000000000 0000 total fails 0, total passes 19 step 1 100000000000000000000000000000000001111100011011011010100110111001 step 2 100000000000000000000000000000000001111100100011011010100110111001 step 3 100000000000000000000000000000000001111100000011011010100110111001 step 4 100000000000000000000000000000000001111100000100011010100110111001 step 5 100000000000000000000000000000000001111100000000011010100110111001 step 6 100000000000000000000000000000000001111100000000100010100110111001 step 7 100000000000000000000000000000000001111100000000000010100110111001 step 8 100000000000000000000000000000000001111100000000000101010110111001 step 9 100000000000000000000000000000000001111100000000000001010110111001 step 10 100000000000000000000000000000000001111100000000000001011000111001 step 11 100000000000000000000000000000000001111100000000000001010000111001 step 12 100000000000000000000000000000000001111100000000000001010001100001 step 13 100000000000000000000000000000000001111100000000000001010000100001 step 14 100000000000000000000000000000000001111100000000000001010000100001 step 15 100000000000010000000000000000000000111101000000000001010000100001 step 16 100000000000010010000000000000000000110111000000000001010000100001 step 17 100000000000010010000000000000000000110111111000000001010000100001 step 18 100000000000010010000000000000000000110111011000000001010000100001 step 19 100000000000010010000000000000000000110111011111000001010000100001 step 20 100000000000010010000000000000000000110111011011000001010000100001 step 21 100000000000010010000000000000000000110111011011111001010000100001 step 22 100000000000010010000000000000000000110111011011011001010000100001 step 23 100000000000010010000000000000000000110111011011011110100000100001 step 24 100000000000010010000000000000000000110111011011011010100000100001 step 25 100000000000010010000000000000000000110111011011011010101110100001 step 26 100000000000010010000000000000000000110111011011011010100110100001 step 27 100000000000010010000000000000000000110111011011011010100111111001 step 28 100000000000010010000000000000000000110111011011011010100110111001 step 29 100000000000000010000000000000000001110110011011011010100110111001 step 30 100000000000000000000000000000000001111100011011011010100110111001 step 31 100000000000000000000000000000000001111100011011011010100110111001 step 32 100001000000000000000000000000000001111100011011011010100110111001 step 33 100001100000000000000000000000000001111100011011011010100110111001 step 34 100001100100000000000000000000000001111100011011011010100110111001 step 35 100001100110000000000000000000000001111100011011011010100110111001 step 36 100001100110100000000000000000000001111100011011011010100110111001 step 37 100001100110100100000000000000000001111100011011011010100110111001 step 38 100001100110100100010000000000000001111100011011011010100110111001 step 39 100001100110100100011000000000000001111100011011011010100110111001 step 40 100001100110100100011010000000000001111100011011011010100110111001 step 41 100001100110100100011011000000000001111100011011011010100110111001 step 42 100001100110100100011011010000000001111100011011011010100110111001 step 43 100001100110100100011011011000000001111100011011011010100110111001 step 44 100001100110100100011011011010000001111100011011011010100110111001 step 45 100001100110100100011011011011000001111100011011011010100110111001 step 46 100001100110100100011011011011010001111100011011011010100110111001 step 47 100001100110100100011011011011011001111100011011011010100110111001 step 48 100001100110100100011011011011011101111100011011011010100110111001 step 49 110001100110100100011011011011011100110111011011011010100110111001 step 50 100001100110100100011011011011011101111100011011011010100110111001 step 51 101001100110100100011011011011011100110111011011011010100110111001 step 52 100001100110100100011011011011011101111100011011011010100110111001 step 53 100101100110100100011011011011011100110111011011011010100110111001 step 54 100001100110100100011011011011011101111100011011011010100110111001 step 55 100011100110100100011011011011011100110111011011011010100110111001 step 56 100001100110100100011011011011011101111100011011011010100110111001 step 57 100001110110100100011011011011011100110111011011011010100110111001 step 58 100001100110100100011011011011011101111100011011011010100110111001 step 59 100001101110100100011011011011011100110111011011011010100110111001 step 60 100001100110100100011011011011011101111100011011011010100110111001 step 61 100001100111100100011011011011011100111101011011011010100110111001 step 62 100001100110100100011011011011011101111100011011011010100110111001 step 63 100001100110110100011011011011011100111101011011011010100110111001 step 64 100001100110100100011011011011011101111100011011011010100110111001 step 65 100001100110101100011011011011011101110110011011011010100110111001 step 66 100001100110100100011011011011011101111100011011011010100110111001 step 67 100001100110100110011011011011011101110110011011011010100110111001 step 68 100001100110100100011011011011011101111100011011011010100110111001 step 69 100001100110100101011011011011011101001111011011011010100110111001 step 70 100001100110100100011011011011011101111100011011011010100110111001 step 71 100001100110100100111011011011011101001111011011011010100110111001 step 72 100001100110100100011011011011011101111100011011011010100110111001 step 73 100001100110100100011111011011011101001111011011011010100110111001 step 74 100001100110100100011011011011011101111100011011011010100110111001 step 75 100001100110100100011011111011011101001111011011011010100110111001 step 76 100001100110100100011011011011011101111100011011011010100110111001 step 77 100001100110100100011011011111011101001111011011011010100110111001 step 78 100001100110100100011011011011011101111100011011011010100110111001 step 79 100001100110100100011011011011111101001111011011011010100110111001 step 80 100001100110100100011011011011011101111100011011011010100110111001 step 81 100001100110100100011011011011011111101110011011011010100110111001 step 82 100001100110100100011011011011011101111100011011011010100110111001 test 20: pass SLOT BAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBAABBAAAAAAAAAAAAAABBBBBBBBAB LETTER ALPSLFMDEEMCBFRSPKLEMFHRSCJLJKUHPNMBBNNVVRKRHUTDJUKANJHBTPDFSVDEVU SIDE 121212122121212121111111112212122222112222111221112112212112212212 DIRECTION IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIOOOOOOOIOOIOOIOOIOOOOIOOIIOOIIO this fail all fails was hi 111111111111111111111111111111111111111111111111111111111111111 1 rising ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ ^^^^^^^^^^^^^^^^^^^^ ^^ falling vvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvv vvvvvvvvvvvvvvvvvvvv vv was lo 00000000000000000000000000000000000000 00000000000000000000 0000 total fails 0, total passes 20 step 1 100000000000000000000000000000000001111100011011011010100110111001 step 2 100000000000000000000000000000000001111100100011011010100110111001 step 3 100000000000000000000000000000000001111100000011011010100110111001 step 4 100000000000000000000000000000000001111100000100011010100110111001 step 5 100000000000000000000000000000000001111100000000011010100110111001 step 6 100000000000000000000000000000000001111100000000100010100110111001 step 7 100000000000000000000000000000000001111100000000000010100110111001 step 8 100000000000000000000000000000000001111100000000000101010110111001 step 9 100000000000000000000000000000000001111100000000000001010110111001 step 10 100000000000000000000000000000000001111100000000000001011000111001 step 11 100000000000000000000000000000000001111100000000000001010000111001 step 12 100000000000000000000000000000000001111100000000000001010001100001 step 13 100000000000000000000000000000000001111100000000000001010000100001 step 14 100000000000000000000000000000000001111100000000000001010000100001 step 15 100000000000010000000000000000000000111101000000000001010000100001 step 16 100000000000010010000000000000000000110111000000000001010000100001 step 17 100000000000010010000000000000000000110111111000000001010000100001 step 18 100000000000010010000000000000000000110111011000000001010000100001 step 19 100000000000010010000000000000000000110111011111000001010000100001 step 20 100000000000010010000000000000000000110111011011000001010000100001 step 21 100000000000010010000000000000000000110111011011111001010000100001 step 22 100000000000010010000000000000000000110111011011011001010000100001 step 23 100000000000010010000000000000000000110111011011011110100000100001 step 24 100000000000010010000000000000000000110111011011011010100000100001 step 25 100000000000010010000000000000000000110111011011011010101110100001 step 26 100000000000010010000000000000000000110111011011011010100110100001 step 27 100000000000010010000000000000000000110111011011011010100111111001 step 28 100000000000010010000000000000000000110111011011011010100110111001 step 29 100000000000000010000000000000000001110110011011011010100110111001 step 30 100000000000000000000000000000000001111100011011011010100110111001 step 31 100000000000000000000000000000000001111100011011011010100110111001 step 32 100001000000000000000000000000000001111100011011011010100110111001 step 33 100001100000000000000000000000000001111100011011011010100110111001 step 34 100001100100000000000000000000000001111100011011011010100110111001 step 35 100001100110000000000000000000000001111100011011011010100110111001 step 36 100001100110100000000000000000000001111100011011011010100110111001 step 37 100001100110100100000000000000000001111100011011011010100110111001 step 38 100001100110100100010000000000000001111100011011011010100110111001 step 39 100001100110100100011000000000000001111100011011011010100110111001 step 40 100001100110100100011010000000000001111100011011011010100110111001 step 41 100001100110100100011011000000000001111100011011011010100110111001 step 42 100001100110100100011011010000000001111100011011011010100110111001 step 43 100001100110100100011011011000000001111100011011011010100110111001 step 44 100001100110100100011011011010000001111100011011011010100110111001 step 45 100001100110100100011011011011000001111100011011011010100110111001 step 46 100001100110100100011011011011010001111100011011011010100110111001 step 47 100001100110100100011011011011011001111100011011011010100110111001 step 48 100001100110100100011011011011011101111100011011011010100110111001 step 49 110001100110100100011011011011011100110111011011011010100110111001 step 50 100001100110100100011011011011011101111100011011011010100110111001 step 51 101001100110100100011011011011011100110111011011011010100110111001 step 52 100001100110100100011011011011011101111100011011011010100110111001 step 53 100101100110100100011011011011011100110111011011011010100110111001 step 54 100001100110100100011011011011011101111100011011011010100110111001 step 55 100011100110100100011011011011011100110111011011011010100110111001 step 56 100001100110100100011011011011011101111100011011011010100110111001 step 57 100001110110100100011011011011011100110111011011011010100110111001 step 58 100001100110100100011011011011011101111100011011011010100110111001 step 59 100001101110100100011011011011011100110111011011011010100110111001 step 60 100001100110100100011011011011011101111100011011011010100110111001 step 61 100001100111100100011011011011011100111101011011011010100110111001 step 62 100001100110100100011011011011011101111100011011011010100110111001 step 63 100001100110110100011011011011011100111101011011011010100110111001 step 64 100001100110100100011011011011011101111100011011011010100110111001 step 65 100001100110101100011011011011011101110110011011011010100110111001 step 66 100001100110100100011011011011011101111100011011011010100110111001 step 67 100001100110100110011011011011011101110110011011011010100110111001 step 68 100001100110100100011011011011011101111100011011011010100110111001 step 69 100001100110100101011011011011011101001111011011011010100110111001 step 70 100001100110100100011011011011011101111100011011011010100110111001 step 71 100001100110100100111011011011011101001111011011011010100110111001 step 72 100001100110100100011011011011011101111100011011011010100110111001 step 73 100001100110100100011111011011011101001111011011011010100110111001 step 74 100001100110100100011011011011011101111100011011011010100110111001 step 75 100001100110100100011011111011011101001111011011011010100110111001 step 76 100001100110100100011011011011011101111100011011011010100110111001 step 77 100001100110100100011011011111011101001111011011011010100110111001 step 78 100001100110100100011011011011011101111100011011011010100110111001 step 79 100001100110100100011011011011111101001111011011011010100110111001 step 80 100001100110100100011011011011011101111100011011011010100110111001 step 81 100001100110100100011011011011011111101110011011011010100110111001 step 82 100001100110100100011011011011011101111100011011011010100110111001 test 21: pass SLOT BAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBAABBAAAAAAAAAAAAAABBBBBBBBAB LETTER ALPSLFMDEEMCBFRSPKLEMFHRSCJLJKUHPNMBBNNVVRKRHUTDJUKANJHBTPDFSVDEVU SIDE 121212122121212121111111112212122222112222111221112112212112212212 DIRECTION IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIOOOOOOOIOOIOOIOOIOOOOIOOIIOOIIO this fail all fails was hi 111111111111111111111111111111111111111111111111111111111111111 1 rising ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ ^^^^^^^^^^^^^^^^^^^^ ^^ falling vvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvv vvvvvvvvvvvvvvvvvvvv vv was lo 00000000000000000000000000000000000000 00000000000000000000 0000 total fails 0, total passes 21 step 1 100000000000000000000000000000000001111100011011011010100110111001 step 2 100000000000000000000000000000000001111100100011011010100110111001 step 3 100000000000000000000000000000000001111100000011011010100110111001 step 4 100000000000000000000000000000000001111100000100011010100110111001 step 5 100000000000000000000000000000000001111100000000011010100110111001 step 6 100000000000000000000000000000000001111100000000100010100110111001 step 7 100000000000000000000000000000000001111100000000000010100110111001 step 8 100000000000000000000000000000000001111100000000000101010110111001 step 9 100000000000000000000000000000000001111100000000000001010110111001 step 10 100000000000000000000000000000000001111100000000000001011000111001 step 11 100000000000000000000000000000000001111100000000000001010000111001 step 12 100000000000000000000000000000000001111100000000000001010001100001 step 13 100000000000000000000000000000000001111100000000000001010000100001 step 14 100000000000000000000000000000000001111100000000000001010000100001 step 15 100000000000010000000000000000000000111101000000000001010000100001 step 16 100000000000010010000000000000000000110111000000000001010000100001 step 17 100000000000010010000000000000000000110111111000000001010000100001 step 18 100000000000010010000000000000000000110111011000000001010000100001 step 19 100000000000010010000000000000000000110111011111000001010000100001 step 20 100000000000010010000000000000000000110111011011000001010000100001 step 21 100000000000010010000000000000000000110111011011111001010000100001 step 22 100000000000010010000000000000000000110111011011011001010000100001 step 23 100000000000010010000000000000000000110111011011011110100000100001 step 24 100000000000010010000000000000000000110111011011011010100000100001 step 25 100000000000010010000000000000000000110111011011011010101110100001 step 26 100000000000010010000000000000000000110111011011011010100110100001 step 27 100000000000010010000000000000000000110111011011011010100111111001 step 28 100000000000010010000000000000000000110111011011011010100110111001 step 29 100000000000000010000000000000000001110110011011011010100110111001 step 30 100000000000000000000000000000000001111100011011011010100110111001 step 31 100000000000000000000000000000000001111100011011011010100110111001 step 32 100001000000000000000000000000000001111100011011011010100110111001 step 33 100001100000000000000000000000000001111100011011011010100110111001 step 34 100001100100000000000000000000000001111100011011011010100110111001 step 35 100001100110000000000000000000000001111100011011011010100110111001 step 36 100001100110100000000000000000000001111100011011011010100110111001 step 37 100001100110100100000000000000000001111100011011011010100110111001 step 38 100001100110100100010000000000000001111100011011011010100110111001 step 39 100001100110100100011000000000000001111100011011011010100110111001 step 40 100001100110100100011010000000000001111100011011011010100110111001 step 41 100001100110100100011011000000000001111100011011011010100110111001 step 42 100001100110100100011011010000000001111100011011011010100110111001 step 43 100001100110100100011011011000000001111100011011011010100110111001 step 44 100001100110100100011011011010000001111100011011011010100110111001 step 45 100001100110100100011011011011000001111100011011011010100110111001 step 46 100001100110100100011011011011010001111100011011011010100110111001 step 47 100001100110100100011011011011011001111100011011011010100110111001 step 48 100001100110100100011011011011011101111100011011011010100110111001 step 49 110001100110100100011011011011011100110111011011011010100110111001 step 50 100001100110100100011011011011011101111100011011011010100110111001 step 51 101001100110100100011011011011011100110111011011011010100110111001 step 52 100001100110100100011011011011011101111100011011011010100110111001 step 53 100101100110100100011011011011011100110111011011011010100110111001 step 54 100001100110100100011011011011011101111100011011011010100110111001 step 55 100011100110100100011011011011011100110111011011011010100110111001 step 56 100001100110100100011011011011011101111100011011011010100110111001 step 57 100001110110100100011011011011011100110111011011011010100110111001 step 58 100001100110100100011011011011011101111100011011011010100110111001 step 59 100001101110100100011011011011011100110111011011011010100110111001 step 60 100001100110100100011011011011011101111100011011011010100110111001 step 61 100001100111100100011011011011011100111101011011011010100110111001 step 62 100001100110100100011011011011011101111100011011011010100110111001 step 63 100001100110110100011011011011011100111101011011011010100110111001 step 64 100001100110100100011011011011011101111100011011011010100110111001 step 65 100001100110101100011011011011011101110110011011011010100110111001 step 66 100001100110100100011011011011011101111100011011011010100110111001 step 67 100001100110100110011011011011011101110110011011011010100110111001 step 68 100001100110100100011011011011011101111100011011011010100110111001 step 69 100001100110100101011011011011011101001111011011011010100110111001 step 70 100001100110100100011011011011011101111100011011011010100110111001 step 71 100001100110100100111011011011011101001111011011011010100110111001 step 72 100001100110100100011011011011011101111100011011011010100110111001 step 73 100001100110100100011111011011011101001111011011011010100110111001 step 74 100001100110100100011011011011011101111100011011011010100110111001 step 75 100001100110100100011011111011011101001111011011011010100110111001 step 76 100001100110100100011011011011011101111100011011011010100110111001 step 77 100001100110100100011011011111011101001111011011011010100110111001 step 78 100001100110100100011011011011011101111100011011011010100110111001 step 79 100001100110100100011011011011111101001111011011011010100110111001 step 80 100001100110100100011011011011011101111100011011011010100110111001 step 81 100001100110100100011011011011011111101110011011011010100110111001 step 82 100001100110100100011011011011011101111100011011011010100110111001 test 22: pass SLOT BAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBAABBAAAAAAAAAAAAAABBBBBBBBAB LETTER ALPSLFMDEEMCBFRSPKLEMFHRSCJLJKUHPNMBBNNVVRKRHUTDJUKANJHBTPDFSVDEVU SIDE 121212122121212121111111112212122222112222111221112112212112212212 DIRECTION IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIOOOOOOOIOOIOOIOOIOOOOIOOIIOOIIO this fail all fails was hi 111111111111111111111111111111111111111111111111111111111111111 1 rising ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ ^^^^^^^^^^^^^^^^^^^^ ^^ falling vvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvv vvvvvvvvvvvvvvvvvvvv vv was lo 00000000000000000000000000000000000000 00000000000000000000 0000 total fails 0, total passes 22 step 1 100000000000000000000000000000000001111100011011011010100110111001 step 2 100000000000000000000000000000000001111100100011011010100110111001 step 3 100000000000000000000000000000000001111100000011011010100110111001 step 4 100000000000000000000000000000000001111100000100011010100110111001 step 5 100000000000000000000000000000000001111100000000011010100110111001 step 6 100000000000000000000000000000000001111100000000100010100110111001 step 7 100000000000000000000000000000000001111100000000000010100110111001 step 8 100000000000000000000000000000000001111100000000000101010110111001 step 9 100000000000000000000000000000000001111100000000000001010110111001 step 10 100000000000000000000000000000000001111100000000000001011000111001 step 11 100000000000000000000000000000000001111100000000000001010000111001 step 12 100000000000000000000000000000000001111100000000000001010001100001 step 13 100000000000000000000000000000000001111100000000000001010000100001 step 14 100000000000000000000000000000000001111100000000000001010000100001 step 15 100000000000010000000000000000000000111101000000000001010000100001 step 16 100000000000010010000000000000000000110111000000000001010000100001 step 17 100000000000010010000000000000000000110111111000000001010000100001 step 18 100000000000010010000000000000000000110111011000000001010000100001 step 19 100000000000010010000000000000000000110111011111000001010000100001 step 20 100000000000010010000000000000000000110111011011000001010000100001 step 21 100000000000010010000000000000000000110111011011111001010000100001 step 22 100000000000010010000000000000000000110111011011011001010000100001 step 23 100000000000010010000000000000000000110111011011011110100000100001 step 24 100000000000010010000000000000000000110111011011011010100000100001 step 25 100000000000010010000000000000000000110111011011011010101110100001 step 26 100000000000010010000000000000000000110111011011011010100110100001 step 27 100000000000010010000000000000000000110111011011011010100111111001 step 28 100000000000010010000000000000000000110111011011011010100110111001 step 29 100000000000000010000000000000000001110110011011011010100110111001 step 30 100000000000000000000000000000000001111100011011011010100110111001 step 31 100000000000000000000000000000000001111100011011011010100110111001 step 32 100001000000000000000000000000000001111100011011011010100110111001 step 33 100001100000000000000000000000000001111100011011011010100110111001 step 34 100001100100000000000000000000000001111100011011011010100110111001 step 35 100001100110000000000000000000000001111100011011011010100110111001 step 36 100001100110100000000000000000000001111100011011011010100110111001 step 37 100001100110100100000000000000000001111100011011011010100110111001 step 38 100001100110100100010000000000000001111100011011011010100110111001 step 39 100001100110100100011000000000000001111100011011011010100110111001 step 40 100001100110100100011010000000000001111100011011011010100110111001 step 41 100001100110100100011011000000000001111100011011011010100110111001 step 42 100001100110100100011011010000000001111100011011011010100110111001 step 43 100001100110100100011011011000000001111100011011011010100110111001 step 44 100001100110100100011011011010000001111100011011011010100110111001 step 45 100001100110100100011011011011000001111100011011011010100110111001 step 46 100001100110100100011011011011010001111100011011011010100110111001 step 47 100001100110100100011011011011011001111100011011011010100110111001 step 48 100001100110100100011011011011011101111100011011011010100110111001 step 49 110001100110100100011011011011011100110111011011011010100110111001 step 50 100001100110100100011011011011011101111100011011011010100110111001 step 51 101001100110100100011011011011011100110111011011011010100110111001 step 52 100001100110100100011011011011011101111100011011011010100110111001 step 53 100101100110100100011011011011011100110111011011011010100110111001 step 54 100001100110100100011011011011011101111100011011011010100110111001 step 55 100011100110100100011011011011011100110111011011011010100110111001 step 56 100001100110100100011011011011011101111100011011011010100110111001 step 57 100001110110100100011011011011011100110111011011011010100110111001 step 58 100001100110100100011011011011011101111100011011011010100110111001 step 59 100001101110100100011011011011011100110111011011011010100110111001 step 60 100001100110100100011011011011011101111100011011011010100110111001 step 61 100001100111100100011011011011011100111101011011011010100110111001 step 62 100001100110100100011011011011011101111100011011011010100110111001 step 63 100001100110110100011011011011011100111101011011011010100110111001 step 64 100001100110100100011011011011011101111100011011011010100110111001 step 65 100001100110101100011011011011011101110110011011011010100110111001 step 66 100001100110100100011011011011011101111100011011011010100110111001 step 67 100001100110100110011011011011011101110110011011011010100110111001 step 68 100001100110100100011011011011011101111100011011011010100110111001 step 69 100001100110100101011011011011011101001111011011011010100110111001 step 70 100001100110100100011011011011011101111100011011011010100110111001 step 71 100001100110100100111011011011011101001111011011011010100110111001 step 72 100001100110100100011011011011011101111100011011011010100110111001 step 73 100001100110100100011111011011011101001111011011011010100110111001 step 74 100001100110100100011011011011011101111100011011011010100110111001 step 75 100001100110100100011011111011011101001111011011011010100110111001 step 76 100001100110100100011011011011011101111100011011011010100110111001 step 77 100001100110100100011011011111011101001111011011011010100110111001 step 78 100001100110100100011011011011011101111100011011011010100110111001 step 79 100001100110100100011011011011111101001111011011011010100110111001 step 80 100001100110100100011011011011011101111100011011011010100110111001 step 81 100001100110100100011011011011011111101110011011011010100110111001 step 82 100001100110100100011011011011011101111100011011011010100110111001 test 23: pass SLOT BAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBAABBAAAAAAAAAAAAAABBBBBBBBAB LETTER ALPSLFMDEEMCBFRSPKLEMFHRSCJLJKUHPNMBBNNVVRKRHUTDJUKANJHBTPDFSVDEVU SIDE 121212122121212121111111112212122222112222111221112112212112212212 DIRECTION IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIOOOOOOOIOOIOOIOOIOOOOIOOIIOOIIO this fail all fails was hi 111111111111111111111111111111111111111111111111111111111111111 1 rising ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ ^^^^^^^^^^^^^^^^^^^^ ^^ falling vvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvv vvvvvvvvvvvvvvvvvvvv vv was lo 00000000000000000000000000000000000000 00000000000000000000 0000 total fails 0, total passes 23 step 1 100000000000000000000000000000000001111100011011011010100110111001 step 2 100000000000000000000000000000000001111100100011011010100110111001 step 3 100000000000000000000000000000000001111100000011011010100110111001 step 4 100000000000000000000000000000000001111100000100011010100110111001 step 5 100000000000000000000000000000000001111100000000011010100110111001 step 6 100000000000000000000000000000000001111100000000100010100110111001 step 7 100000000000000000000000000000000001111100000000000010100110111001 step 8 100000000000000000000000000000000001111100000000000101010110111001 step 9 100000000000000000000000000000000001111100000000000001010110111001 step 10 100000000000000000000000000000000001111100000000000001011000111001 step 11 100000000000000000000000000000000001111100000000000001010000111001 step 12 100000000000000000000000000000000001111100000000000001010001100001 step 13 100000000000000000000000000000000001111100000000000001010000100001 step 14 100000000000000000000000000000000001111100000000000001010000100001 step 15 100000000000010000000000000000000000111101000000000001010000100001 step 16 100000000000010010000000000000000000110111000000000001010000100001 step 17 100000000000010010000000000000000000110111111000000001010000100001 step 18 100000000000010010000000000000000000110111011000000001010000100001 step 19 100000000000010010000000000000000000110111011111000001010000100001 step 20 100000000000010010000000000000000000110111011011000001010000100001 step 21 100000000000010010000000000000000000110111011011111001010000100001 step 22 100000000000010010000000000000000000110111011011011001010000100001 step 23 100000000000010010000000000000000000110111011011011110100000100001 step 24 100000000000010010000000000000000000110111011011011010100000100001 step 25 100000000000010010000000000000000000110111011011011010101110100001 step 26 100000000000010010000000000000000000110111011011011010100110100001 step 27 100000000000010010000000000000000000110111011011011010100111111001 step 28 100000000000010010000000000000000000110111011011011010100110111001 step 29 100000000000000010000000000000000001110110011011011010100110111001 step 30 100000000000000000000000000000000001111100011011011010100110111001 step 31 100000000000000000000000000000000001111100011011011010100110111001 step 32 100001000000000000000000000000000001111100011011011010100110111001 step 33 100001100000000000000000000000000001111100011011011010100110111001 step 34 100001100100000000000000000000000001111100011011011010100110111001 step 35 100001100110000000000000000000000001111100011011011010100110111001 step 36 100001100110100000000000000000000001111100011011011010100110111001 step 37 100001100110100100000000000000000001111100011011011010100110111001 space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C toggle comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit scope (run, no print) ppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppp ppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppp ppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppFpppppp ppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppp ppppppppppppppppppppppppppppppFpppppppppppppppppppppppppppppppppppppppppppppppp pppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppp space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C toggle comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT BAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBAABBAAAAAAAAAAAAAABBBBBBBBAB LETTER ALPSLFMDEEMCBFRSPKLEMFHRSCJLJKUHPNMBBNNVVRKRHUTDJUKANJHBTPDFSVDEVU SIDE 121212122121212121111111112212122222112222111221112112212112212212 DIRECTION IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIOOOOOOOIOOIOOIOOIOOOOIOOIIOOIIO all fails I I III I II O O O O IO was lo 00000000000000000000000000000000000000 00000000000000000000 00000 falling vvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvv vvvvvvvvvvvvvvvvvvvv vv vv rising ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ ^^^^^^^^^^^^^^^^^^^^ ^^ ^^ was hi 111111111111111111111111111111111111111111111111111111111111111 11 total fails 2, total passes 488 Main menu Sat Jul 11 15:56:34 2015 test file is: tests\m222.new delay is: 0 trigger is: 1 1 read test file 2 set test delay 3 set test trigger 4 run test 5 output loading test 8 diags 9 exit UUT power is okay Sat Jul 11 15:56:36 2015 space single step O run once (one test, all steps) F run, stop on fail G go (run tests N run, stop on fail, no print S scope (run, no print) C toggle comment printout + increase speed (less delay) - decrease speed (more delay)(slower) Q quit test scope (run, no print) FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C toggle comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit step 72 100001100110100100011011011011011101111100011011011010100110111001 step 73 100001100110100100011111011011011101001111011011011010100110111001 step 74 100001100110100100011011011011011101111100011011011010100110111001 step 75 100001100110100100011011111011011101001111011011011010100110111001 step 76 100001100110100100011011011011011101111100011011011010100110111001 step 77 100001100110100100011011011111011101001111011011011010100110111001 step 78 100001100110100100011011011011011101111100011011011010100110111001 step 79 100001100110100100011011011011111101001111011011011010100110111001 step 80 100001100110100100011011011011011101111100011011011010100110111001 step 81 100001100110100100011011011011011111101110011011011010100110111001 step 82 100001100110100100011011011011011101111100011011011010100110111001 test 41: *** FAIL *************************** 15 steps failed SLOT BAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBAABBAAAAAAAAAAAAAABBBBBBBBAB LETTER ALPSLFMDEEMCBFRSPKLEMFHRSCJLJKUHPNMBBNNVVRKRHUTDJUKANJHBTPDFSVDEVU SIDE 121212122121212121111111112212122222112222111221112112212112212212 DIRECTION IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIOOOOOOOIOOIOOIOOIOOOOIOOIIOOIIO this fail OOOO all fails OOOO was hi 11111111111111111111111111111111111111111111111111111 1 1111111 1 rising ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ ^^^^^^^^^^^^ ^^^^ ^^ falling vvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvv vvvvvvvvvvvv vvvv vv was lo 00000000000000000000000000000000000000 000000000000 0 00000 0000 total fails 41, total passes 0 space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C toggle comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT BAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBAABBAAAAAAAAAAAAAABBBBBBBBAB LETTER ALPSLFMDEEMCBFRSPKLEMFHRSCJLJKUHPNMBBNNVVRKRHUTDJUKANJHBTPDFSVDEVU SIDE 121212122121212121111111112212122222112222111221112112212112212212 DIRECTION IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIOOOOOOOIOOIOOIOOIOOOOIOOIIOOIIO all fails OOOO was lo 00000000000000000000000000000000000000 000000000000 0 00000 0000 falling vvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvv vvvvvvvvvvvv vvvv vv rising ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ ^^^^^^^^^^^^ ^^^^ ^^ was hi 11111111111111111111111111111111111111111111111111111 1 1111111 1 total fails 41, total passes 0 Main menu Sat Jul 11 15:57:04 2015 test file is: tests\m222.new delay is: 0 trigger is: 1 1 read test file 2 set test delay 3 set test trigger 4 run test 5 output loading test 8 diags 9 exit UUT power is okay Sat Jul 11 15:57:11 2015 space single step O run once (one test, all steps) F run, stop on fail G go (run tests N run, stop on fail, no print S scope (run, no print) C toggle comment printout + increase speed (less delay) - decrease speed (more delay)(slower) Q quit test step 1 100000000000000000000000000000000001111100010011011010100110111001 step 2 100000000000000000000000000000000001111100100011011010100110111001 step 3 100000000000000000000000000000000001111100000011011010100110111001 step 4 100000000000000000000000000000000001111100000100011010100110111001 step 5 100000000000000000000000000000000001111100000000011010100110111001 step 6 100000000000000000000000000000000001111100000000100010100110111001 step 7 100000000000000000000000000000000001111100000000000010100110111001 SLOT BAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBAABBAAAAAAAAAAAAAABBBBBBBBAB LETTER ALPSLFMDEEMCBFRSPKLEMFHRSCJLJKUHPNMBBNNVVRKRHUTDJUKANJHBTPDFSVDEVU SIDE 121212122121212121111111112212122222112222111221112112212112212212 DIRECTION IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIOOOOOOOIOOIOOIOOIOOOOIOOIIOOIIO changed: 1 step 8 100000000000000000000000000000000001111100000000000110100110111001 fail ^^^^ space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C toggle comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT BAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBAABBAAAAAAAAAAAAAABBBBBBBBAB LETTER ALPSLFMDEEMCBFRSPKLEMFHRSCJLJKUHPNMBBNNVVRKRHUTDJUKANJHBTPDFSVDEVU SIDE 121212122121212121111111112212122222112222111221112112212112212212 DIRECTION IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIOOOOOOOIOOIOOIOOIOOOOIOOIIOOIIO changed: 0 step 9 100000000000000000000000000000000001111100000000000010100110111001 fail ^^^^ space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C toggle comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT BAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBAABBAAAAAAAAAAAAAABBBBBBBBAB LETTER ALPSLFMDEEMCBFRSPKLEMFHRSCJLJKUHPNMBBNNVVRKRHUTDJUKANJHBTPDFSVDEVU SIDE 121212122121212121111111112212122222112222111221112112212112212212 DIRECTION IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIOOOOOOOIOOIOOIOOIOOOOIOOIIOOIIO changed: 100 step 10 100000000000000000000000000000000001111100000000000010101000111001 fail ^^^^ space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C toggle comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT BAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBAABBAAAAAAAAAAAAAABBBBBBBBAB LETTER ALPSLFMDEEMCBFRSPKLEMFHRSCJLJKUHPNMBBNNVVRKRHUTDJUKANJHBTPDFSVDEVU SIDE 121212122121212121111111112212122222112222111221112112212112212212 DIRECTION IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIOOOOOOOIOOIOOIOOIOOOOIOOIIOOIIO changed: 0 step 11 100000000000000000000000000000000001111100000000000010100000111001 fail ^^^^ space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C toggle comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT BAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBAABBAAAAAAAAAAAAAABBBBBBBBAB LETTER ALPSLFMDEEMCBFRSPKLEMFHRSCJLJKUHPNMBBNNVVRKRHUTDJUKANJHBTPDFSVDEVU SIDE 121212122121212121111111112212122222112222111221112112212112212212 DIRECTION IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIOOOOOOOIOOIOOIOOIOOOOIOOIIOOIIO changed: 1 00 step 12 100000000000000000000000000000000001111100000000000010100001100001 fail ^^^^ space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C toggle comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT BAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBAABBAAAAAAAAAAAAAABBBBBBBBAB LETTER ALPSLFMDEEMCBFRSPKLEMFHRSCJLJKUHPNMBBNNVVRKRHUTDJUKANJHBTPDFSVDEVU SIDE 121212122121212121111111112212122222112222111221112112212112212212 DIRECTION IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIOOOOOOOIOOIOOIOOIOOOOIOOIIOOIIO changed: 0 step 13 100000000000000000000000000000000001111100000000000010100000100001 fail ^^^^ space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C toggle comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT BAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBAABBAAAAAAAAAAAAAABBBBBBBBAB LETTER ALPSLFMDEEMCBFRSPKLEMFHRSCJLJKUHPNMBBNNVVRKRHUTDJUKANJHBTPDFSVDEVU SIDE 121212122121212121111111112212122222112222111221112112212112212212 DIRECTION IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIOOOOOOOIOOIOOIOOIOOOOIOOIIOOIIO changed: step 14 100000000000000000000000000000000001111100000000000010100000100001 fail ^^^^ space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C toggle comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT BAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBAABBAAAAAAAAAAAAAABBBBBBBBAB LETTER ALPSLFMDEEMCBFRSPKLEMFHRSCJLJKUHPNMBBNNVVRKRHUTDJUKANJHBTPDFSVDEVU SIDE 121212122121212121111111112212122222112222111221112112212112212212 DIRECTION IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIOOOOOOOIOOIOOIOOIOOOOIOOIIOOIIO changed: 1 0 1 step 15 100000000000010000000000000000000000111101000000000010100000100001 fail ^^^^ space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C toggle comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT BAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBAABBAAAAAAAAAAAAAABBBBBBBBAB LETTER ALPSLFMDEEMCBFRSPKLEMFHRSCJLJKUHPNMBBNNVVRKRHUTDJUKANJHBTPDFSVDEVU SIDE 121212122121212121111111112212122222112222111221112112212112212212 DIRECTION IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIOOOOOOOIOOIOOIOOIOOOOIOOIIOOIIO changed: 1 0 1 step 16 100000000000010010000000000000000000110111000000000010100000100001 fail ^^^^ space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C toggle comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT BAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBAABBAAAAAAAAAAAAAABBBBBBBBAB LETTER ALPSLFMDEEMCBFRSPKLEMFHRSCJLJKUHPNMBBNNVVRKRHUTDJUKANJHBTPDFSVDEVU SIDE 121212122121212121111111112212122222112222111221112112212112212212 DIRECTION IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIOOOOOOOIOOIOOIOOIOOOOIOOIIOOIIO changed: 111 step 17 100000000000010010000000000000000000110111111000000010100000100001 fail ^^^^ space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C toggle comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT BAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBAABBAAAAAAAAAAAAAABBBBBBBBAB LETTER ALPSLFMDEEMCBFRSPKLEMFHRSCJLJKUHPNMBBNNVVRKRHUTDJUKANJHBTPDFSVDEVU SIDE 121212122121212121111111112212122222112222111221112112212112212212 DIRECTION IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIOOOOOOOIOOIOOIOOIOOOOIOOIIOOIIO changed: 0 step 18 100000000000010010000000000000000000110111011000000010100000100001 fail ^^^^ SLOT BAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBAABBAAAAAAAAAAAAAABBBBBBBBAB LETTER ALPSLFMDEEMCBFRSPKLEMFHRSCJLJKUHPNMBBNNVVRKRHUTDJUKANJHBTPDFSVDEVU SIDE 121212122121212121111111112212122222112222111221112112212112212212 DIRECTION IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIOOOOOOOIOOIOOIOOIOOOOIOOIIOOIIO changed: 111 step 19 100000000000010010000000000000000000110111011111000010100000100001 fail ^^^^ SLOT BAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBAABBAAAAAAAAAAAAAABBBBBBBBAB LETTER ALPSLFMDEEMCBFRSPKLEMFHRSCJLJKUHPNMBBNNVVRKRHUTDJUKANJHBTPDFSVDEVU SIDE 121212122121212121111111112212122222112222111221112112212112212212 DIRECTION IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIOOOOOOOIOOIOOIOOIOOOOIOOIIOOIIO changed: 0 step 20 100000000000010010000000000000000000110111011011000010100000100001 fail ^^^^ SLOT BAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBAABBAAAAAAAAAAAAAABBBBBBBBAB LETTER ALPSLFMDEEMCBFRSPKLEMFHRSCJLJKUHPNMBBNNVVRKRHUTDJUKANJHBTPDFSVDEVU SIDE 121212122121212121111111112212122222112222111221112112212112212212 DIRECTION IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIOOOOOOOIOOIOOIOOIOOOOIOOIIOOIIO changed: 111 step 21 100000000000010010000000000000000000110111011011111010100000100001 fail ^^^^ SLOT BAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBAABBAAAAAAAAAAAAAABBBBBBBBAB LETTER ALPSLFMDEEMCBFRSPKLEMFHRSCJLJKUHPNMBBNNVVRKRHUTDJUKANJHBTPDFSVDEVU SIDE 121212122121212121111111112212122222112222111221112112212112212212 DIRECTION IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIOOOOOOOIOOIOOIOOIOOOOIOOIIOOIIO changed: 0 step 22 100000000000010010000000000000000000110111011011011010100000100001 fail ^^^^ step 23 100000000000010010000000000000000000110111011011011110100000100001 step 24 100000000000010010000000000000000000110111011011011010100000100001 step 25 100000000000010010000000000000000000110111011011011010101110100001 step 26 100000000000010010000000000000000000110111011011011010100110100001 step 27 100000000000010010000000000000000000110111011011011010100111111001 step 28 100000000000010010000000000000000000110111011011011010100110111001 step 29 100000000000000010000000000000000001110110011011011010100110111001 step 30 100000000000000000000000000000000001111100011011011010100110111001 step 31 100000000000000000000000000000000001111100011011011010100110111001 step 32 100001000000000000000000000000000001111100011011011010100110111001 step 33 100001100000000000000000000000000001111100011011011010100110111001 step 34 100001100100000000000000000000000001111100011011011010100110111001 step 35 100001100110000000000000000000000001111100011011011010100110111001 step 36 100001100110100000000000000000000001111100011011011010100110111001 step 37 100001100110100100000000000000000001111100011011011010100110111001 step 38 100001100110100100010000000000000001111100011011011010100110111001 step 39 100001100110100100011000000000000001111100011011011010100110111001 step 40 100001100110100100011010000000000001111100011011011010100110111001 step 41 100001100110100100011011000000000001111100011011011010100110111001 step 42 100001100110100100011011010000000001111100011011011010100110111001 step 43 100001100110100100011011011000000001111100011011011010100110111001 step 44 100001100110100100011011011010000001111100011011011010100110111001 step 45 100001100110100100011011011011000001111100011011011010100110111001 step 46 100001100110100100011011011011010001111100011011011010100110111001 step 47 100001100110100100011011011011011001111100011011011010100110111001 step 48 100001100110100100011011011011011101111100011011011010100110111001 step 49 110001100110100100011011011011011100110111011011011010100110111001 step 50 100001100110100100011011011011011101111100011011011010100110111001 step 51 101001100110100100011011011011011100110111011011011010100110111001 step 52 100001100110100100011011011011011101111100011011011010100110111001 step 53 100101100110100100011011011011011100110111011011011010100110111001 step 54 100001100110100100011011011011011101111100011011011010100110111001 step 55 100011100110100100011011011011011100110111011011011010100110111001 step 56 100001100110100100011011011011011101111100011011011010100110111001 step 57 100001110110100100011011011011011100110111011011011010100110111001 step 58 100001100110100100011011011011011101111100011011011010100110111001 step 59 100001101110100100011011011011011100110111011011011010100110111001 step 60 100001100110100100011011011011011101111100011011011010100110111001 step 61 100001100111100100011011011011011100111101011011011010100110111001 step 62 100001100110100100011011011011011101111100011011011010100110111001 step 63 100001100110110100011011011011011100111101011011011010100110111001 step 64 100001100110100100011011011011011101111100011011011010100110111001 step 65 100001100110101100011011011011011101110110011011011010100110111001 step 66 100001100110100100011011011011011101111100011011011010100110111001 step 67 100001100110100110011011011011011101110110011011011010100110111001 step 68 100001100110100100011011011011011101111100011011011010100110111001 step 69 100001100110100101011011011011011101001111011011011010100110111001 step 70 100001100110100100011011011011011101111100011011011010100110111001 step 71 100001100110100100111011011011011101001111011011011010100110111001 step 72 100001100110100100011011011011011101111100011011011010100110111001 step 73 100001100110100100011111011011011101001111011011011010100110111001 step 74 100001100110100100011011011011011101111100011011011010100110111001 step 75 100001100110100100011011111011011101001111011011011010100110111001 step 76 100001100110100100011011011011011101111100011011011010100110111001 step 77 100001100110100100011011011111011101001111011011011010100110111001 step 78 100001100110100100011011011011011101111100011011011010100110111001 step 79 100001100110100100011011011011111101001111011011011010100110111001 step 80 100001100110100100011011011011011101111100011011011010100110111001 step 81 100001100110100100011011011011011111101110011011011010100110111001 step 82 100001100110100100011011011011011101111100011011011010100110111001 test 1: *** FAIL *************************** 15 steps failed SLOT BAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBAABBAAAAAAAAAAAAAABBBBBBBBAB LETTER ALPSLFMDEEMCBFRSPKLEMFHRSCJLJKUHPNMBBNNVVRKRHUTDJUKANJHBTPDFSVDEVU SIDE 121212122121212121111111112212122222112222111221112112212112212212 DIRECTION IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIOOOOOOOIOOIOOIOOIOOOOIOOIIOOIIO this fail OOOO all fails OOOO was hi 11111111111111111111111111111111111111111111111111111 1 1111111 1 rising ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ ^^^^^^^^^^^^ ^^^^ ^^ falling vvvv vv v vv vvv v v v v vvvvv vvvv vvvvvvv vvvv vv was lo 00000000000000000000000000000000000000 000000000000 0 00000 0000 total fails 1, total passes 0 space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C toggle comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C toggle comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT BAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBAABBAAAAAAAAAAAAAABBBBBBBBAB LETTER ALPSLFMDEEMCBFRSPKLEMFHRSCJLJKUHPNMBBNNVVRKRHUTDJUKANJHBTPDFSVDEVU SIDE 121212122121212121111111112212122222112222111221112112212112212212 DIRECTION IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIOOOOOOOIOOIOOIOOIOOOOIOOIIOOIIO all fails OOOO was lo 00000000000000000000000000000000000000 000000000000 0 00000 0000 falling vvvv vv v vv vvv v v v v vvvvv vvvv vvvvvvv vvvv vv rising ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ ^^^^^^^^^^^^ ^^^^ ^^ was hi 11111111111111111111111111111111111111111111111111111 1 1111111 1 total fails 1, total passes 0 Main menu Sat Jul 11 15:57:45 2015 test file is: tests\m222.new delay is: 0 trigger is: 1 1 read test file 2 set test delay 3 set test trigger 4 run test 5 output loading test 8 diags 9 exit UUT power is okay Sat Jul 11 15:59:10 2015 space single step O run once (one test, all steps) F run, stop on fail G go (run tests N run, stop on fail, no print S scope (run, no print) C toggle comment printout + increase speed (less delay) - decrease speed (more delay)(slower) Q quit test step 1 100000000000000000000000000000000001111100010010011010010100110001 step 2 100000000000000000000000000000000001111100100010011010010100110001 step 3 100000000000000000000000000000000001111100000010011010010100110001 step 4 100000000000000000000000000000000001111100000100011010010100110001 step 5 100000000000000000000000000000000001111100000000011010010100110001 step 6 100000000000000000000000000000000001111100000000100010010100110001 step 7 100000000000000000000000000000000001111100000000000010010100110001 step 8 100000000000000000000000000000000001111100000000000101010100110001 step 9 100000000000000000000000000000000001111100000000000001010100110001 step 10 100000000000000000000000000000000001111100000000000001011000110001 step 11 100000000000000000000000000000000001111100000000000001010000110001 step 12 100000000000000000000000000000000001111100000000000001010001100001 step 13 100000000000000000000000000000000001111100000000000001010000100001 step 14 100000000000000000000000000000000001111100000000000001010000100001 step 15 100000000000010000000000000000000000111101000000000001010000100001 step 16 100000000000010010000000000000000000110111000000000001010000100001 step 17 100000000000010010000000000000000000110111111000000001010000100001 step 18 100000000000010010000000000000000000110111011000000001010000100001 step 19 100000000000010010000000000000000000110111011111000001010000100001 step 20 100000000000010010000000000000000000110111011011000001010000100001 step 21 100000000000010010000000000000000000110111011011111001010000100001 step 22 100000000000010010000000000000000000110111011011011001010000100001 step 23 100000000000010010000000000000000000110111011011011110100000100001 step 24 100000000000010010000000000000000000110111011011011010100000100001 step 25 100000000000010010000000000000000000110111011011011010101110100001 step 26 100000000000010010000000000000000000110111011011011010100110100001 step 27 100000000000010010000000000000000000110111011011011010100111111001 step 28 100000000000010010000000000000000000110111011011011010100110111001 step 29 100000000000000010000000000000000001110110011011011010100110111001 step 30 100000000000000000000000000000000001111100011011011010100110111001 step 31 100000000000000000000000000000000001111100011011011010100110111001 step 32 100001000000000000000000000000000001111100011011011010100110111001 step 33 100001100000000000000000000000000001111100011011011010100110111001 step 34 100001100100000000000000000000000001111100011011011010100110111001 step 35 100001100110000000000000000000000001111100011011011010100110111001 step 36 100001100110100000000000000000000001111100011011011010100110111001 step 37 100001100110100100000000000000000001111100011011011010100110111001 step 38 100001100110100100010000000000000001111100011011011010100110111001 step 39 100001100110100100011000000000000001111100011011011010100110111001 step 40 100001100110100100011010000000000001111100011011011010100110111001 step 41 100001100110100100011011000000000001111100011011011010100110111001 step 42 100001100110100100011011010000000001111100011011011010100110111001 step 43 100001100110100100011011011000000001111100011011011010100110111001 step 44 100001100110100100011011011010000001111100011011011010100110111001 step 45 100001100110100100011011011011000001111100011011011010100110111001 step 46 100001100110100100011011011011010001111100011011011010100110111001 step 47 100001100110100100011011011011011001111100011011011010100110111001 step 48 100001100110100100011011011011011101111100011011011010100110111001 step 49 110001100110100100011011011011011100110111011011011010100110111001 step 50 100001100110100100011011011011011101111100011011011010100110111001 step 51 101001100110100100011011011011011100110111011011011010100110111001 step 52 100001100110100100011011011011011101111100011011011010100110111001 step 53 100101100110100100011011011011011100110111011011011010100110111001 step 54 100001100110100100011011011011011101111100011011011010100110111001 step 55 100011100110100100011011011011011100110111011011011010100110111001 step 56 100001100110100100011011011011011101111100011011011010100110111001 step 57 100001110110100100011011011011011100110111011011011010100110111001 step 58 100001100110100100011011011011011101111100011011011010100110111001 step 59 100001101110100100011011011011011100110111011011011010100110111001 step 60 100001100110100100011011011011011101111100011011011010100110111001 step 61 100001100111100100011011011011011100111101011011011010100110111001 step 62 100001100110100100011011011011011101111100011011011010100110111001 step 63 100001100110110100011011011011011100111101011011011010100110111001 step 64 100001100110100100011011011011011101111100011011011010100110111001 step 65 100001100110101100011011011011011101110110011011011010100110111001 step 66 100001100110100100011011011011011101111100011011011010100110111001 step 67 100001100110100110011011011011011101110110011011011010100110111001 step 68 100001100110100100011011011011011101111100011011011010100110111001 step 69 100001100110100101011011011011011101001111011011011010100110111001 step 70 100001100110100100011011011011011101111100011011011010100110111001 step 71 100001100110100100111011011011011101001111011011011010100110111001 step 72 100001100110100100011011011011011101111100011011011010100110111001 step 73 100001100110100100011111011011011101001111011011011010100110111001 step 74 100001100110100100011011011011011101111100011011011010100110111001 step 75 100001100110100100011011111011011101001111011011011010100110111001 step 76 100001100110100100011011011011011101111100011011011010100110111001 step 77 100001100110100100011011011111011101001111011011011010100110111001 step 78 100001100110100100011011011011011101111100011011011010100110111001 step 79 100001100110100100011011011011111101001111011011011010100110111001 step 80 100001100110100100011011011011011101111100011011011010100110111001 step 81 100001100110100100011011011011011111101110011011011010100110111001 step 82 100001100110100100011011011011011101111100011011011010100110111001 test 1: pass SLOT BAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBAABBAAAAAAAAAAAAAABBBBBBBBAB LETTER ALPSLFMDEEMCBFRSPKLEMFHRSCJLJKUHPNMBBNNVVRKRHUTDJUKANJHBTPDFSVDEVU SIDE 121212122121212121111111112212122222112222111221112112212112212212 DIRECTION IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIOOOOOOOIOOIOOIOOIOOOOIOOIIOOIIO this fail all fails was hi 111111111111111111111111111111111111111111111111111111111111111 1 rising ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ ^^^^^^^^^^^^^^^ ^^^^ ^^ falling vvvv vv v vv vvv v v v v vvvvv vvvv vv vvvvvv vvv v v was lo 00000000000000000000000000000000000000 00000000000000000000 0000 total fails 0, total passes 1 step 1 100000000000000000000000000000000001111100011011011010100110111001 step 2 100000000000000000000000000000000001111100100011011010100110111001 step 3 100000000000000000000000000000000001111100000011011010100110111001 step 4 100000000000000000000000000000000001111100000100011010100110111001 step 5 100000000000000000000000000000000001111100000000011010100110111001 step 6 100000000000000000000000000000000001111100000000100010100110111001 step 7 100000000000000000000000000000000001111100000000000010100110111001 step 8 100000000000000000000000000000000001111100000000000101010110111001 step 9 100000000000000000000000000000000001111100000000000001010110111001 step 10 100000000000000000000000000000000001111100000000000001011000111001 step 11 100000000000000000000000000000000001111100000000000001010000111001 step 12 100000000000000000000000000000000001111100000000000001010001100001 step 13 100000000000000000000000000000000001111100000000000001010000100001 step 14 100000000000000000000000000000000001111100000000000001010000100001 step 15 100000000000010000000000000000000000111101000000000001010000100001 step 16 100000000000010010000000000000000000110111000000000001010000100001 step 17 100000000000010010000000000000000000110111111000000001010000100001 step 18 100000000000010010000000000000000000110111011000000001010000100001 step 19 100000000000010010000000000000000000110111011111000001010000100001 step 20 100000000000010010000000000000000000110111011011000001010000100001 step 21 100000000000010010000000000000000000110111011011111001010000100001 step 22 100000000000010010000000000000000000110111011011011001010000100001 step 23 100000000000010010000000000000000000110111011011011110100000100001 step 24 100000000000010010000000000000000000110111011011011010100000100001 step 25 100000000000010010000000000000000000110111011011011010101110100001 step 26 100000000000010010000000000000000000110111011011011010100110100001 step 27 100000000000010010000000000000000000110111011011011010100111111001 step 28 100000000000010010000000000000000000110111011011011010100110111001 step 29 100000000000000010000000000000000001110110011011011010100110111001 step 30 100000000000000000000000000000000001111100011011011010100110111001 step 31 100000000000000000000000000000000001111100011011011010100110111001 step 32 100001000000000000000000000000000001111100011011011010100110111001 step 33 100001100000000000000000000000000001111100011011011010100110111001 step 34 100001100100000000000000000000000001111100011011011010100110111001 step 35 100001100110000000000000000000000001111100011011011010100110111001 step 36 100001100110100000000000000000000001111100011011011010100110111001 step 37 100001100110100100000000000000000001111100011011011010100110111001 step 38 100001100110100100010000000000000001111100011011011010100110111001 step 39 100001100110100100011000000000000001111100011011011010100110111001 step 40 100001100110100100011010000000000001111100011011011010100110111001 step 41 100001100110100100011011000000000001111100011011011010100110111001 step 42 100001100110100100011011010000000001111100011011011010100110111001 step 43 100001100110100100011011011000000001111100011011011010100110111001 step 44 100001100110100100011011011010000001111100011011011010100110111001 step 45 100001100110100100011011011011000001111100011011011010100110111001 step 46 100001100110100100011011011011010001111100011011011010100110111001 step 47 100001100110100100011011011011011001111100011011011010100110111001 step 48 100001100110100100011011011011011101111100011011011010100110111001 step 49 110001100110100100011011011011011100110111011011011010100110111001 step 50 100001100110100100011011011011011101111100011011011010100110111001 step 51 101001100110100100011011011011011100110111011011011010100110111001 step 52 100001100110100100011011011011011101111100011011011010100110111001 step 53 100101100110100100011011011011011100110111011011011010100110111001 step 54 100001100110100100011011011011011101111100011011011010100110111001 step 55 100011100110100100011011011011011100110111011011011010100110111001 step 56 100001100110100100011011011011011101111100011011011010100110111001 step 57 100001110110100100011011011011011100110111011011011010100110111001 step 58 100001100110100100011011011011011101111100011011011010100110111001 step 59 100001101110100100011011011011011100110111011011011010100110111001 step 60 100001100110100100011011011011011101111100011011011010100110111001 step 61 100001100111100100011011011011011100111101011011011010100110111001 step 62 100001100110100100011011011011011101111100011011011010100110111001 step 63 100001100110110100011011011011011100111101011011011010100110111001 step 64 100001100110100100011011011011011101111100011011011010100110111001 step 65 100001100110101100011011011011011101110110011011011010100110111001 step 66 100001100110100100011011011011011101111100011011011010100110111001 step 67 100001100110100110011011011011011101110110011011011010100110111001 step 68 100001100110100100011011011011011101111100011011011010100110111001 step 69 100001100110100101011011011011011101001111011011011010100110111001 step 70 100001100110100100011011011011011101111100011011011010100110111001 step 71 100001100110100100111011011011011101001111011011011010100110111001 step 72 100001100110100100011011011011011101111100011011011010100110111001 step 73 100001100110100100011111011011011101001111011011011010100110111001 step 74 100001100110100100011011011011011101111100011011011010100110111001 step 75 100001100110100100011011111011011101001111011011011010100110111001 step 76 100001100110100100011011011011011101111100011011011010100110111001 step 77 100001100110100100011011011111011101001111011011011010100110111001 step 78 100001100110100100011011011011011101111100011011011010100110111001 step 79 100001100110100100011011011011111101001111011011011010100110111001 step 80 100001100110100100011011011011011101111100011011011010100110111001 step 81 100001100110100100011011011011011111101110011011011010100110111001 step 82 100001100110100100011011011011011101111100011011011010100110111001 test 2: pass SLOT BAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBAABBAAAAAAAAAAAAAABBBBBBBBAB LETTER ALPSLFMDEEMCBFRSPKLEMFHRSCJLJKUHPNMBBNNVVRKRHUTDJUKANJHBTPDFSVDEVU SIDE 121212122121212121111111112212122222112222111221112112212112212212 DIRECTION IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIOOOOOOOIOOIOOIOOIOOOOIOOIIOOIIO this fail all fails was hi 111111111111111111111111111111111111111111111111111111111111111 1 rising ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ ^^^^^^^^^^^^^^^^^^^^ ^^ falling vvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvv vvvvvvvvvvvvvvvvvvvv vv was lo 00000000000000000000000000000000000000 00000000000000000000 0000 total fails 0, total passes 2 step 1 100000000000000000000000000000000001111100011011011010100110111001 step 2 100000000000000000000000000000000001111100100011011010100110111001 step 3 100000000000000000000000000000000001111100000011011010100110111001 step 4 100000000000000000000000000000000001111100000100011010100110111001 step 5 100000000000000000000000000000000001111100000000011010100110111001 step 6 100000000000000000000000000000000001111100000000100010100110111001 step 7 100000000000000000000000000000000001111100000000000010100110111001 step 8 100000000000000000000000000000000001111100000000000101010110111001 step 9 100000000000000000000000000000000001111100000000000001010110111001 step 10 100000000000000000000000000000000001111100000000000001011000111001 step 11 100000000000000000000000000000000001111100000000000001010000111001 step 12 100000000000000000000000000000000001111100000000000001010001100001 step 13 100000000000000000000000000000000001111100000000000001010000100001 step 14 100000000000000000000000000000000001111100000000000001010000100001 step 15 100000000000010000000000000000000000111101000000000001010000100001 step 16 100000000000010010000000000000000000110111000000000001010000100001 step 17 100000000000010010000000000000000000110111111000000001010000100001 step 18 100000000000010010000000000000000000110111011000000001010000100001 step 19 100000000000010010000000000000000000110111011111000001010000100001 step 20 100000000000010010000000000000000000110111011011000001010000100001 step 21 100000000000010010000000000000000000110111011011111001010000100001 step 22 100000000000010010000000000000000000110111011011011001010000100001 step 23 100000000000010010000000000000000000110111011011011110100000100001 step 24 100000000000010010000000000000000000110111011011011010100000100001 step 25 100000000000010010000000000000000000110111011011011010101110100001 step 26 100000000000010010000000000000000000110111011011011010100110100001 step 27 100000000000010010000000000000000000110111011011011010100111111001 step 28 100000000000010010000000000000000000110111011011011010100110111001 step 29 100000000000000010000000000000000001110110011011011010100110111001 step 30 100000000000000000000000000000000001111100011011011010100110111001 step 31 100000000000000000000000000000000001111100011011011010100110111001 step 32 100001000000000000000000000000000001111100011011011010100110111001 step 33 100001100000000000000000000000000001111100011011011010100110111001 step 34 100001100100000000000000000000000001111100011011011010100110111001 step 35 100001100110000000000000000000000001111100011011011010100110111001 step 36 100001100110100000000000000000000001111100011011011010100110111001 step 37 100001100110100100000000000000000001111100011011011010100110111001 step 38 100001100110100100010000000000000001111100011011011010100110111001 step 39 100001100110100100011000000000000001111100011011011010100110111001 step 40 100001100110100100011010000000000001111100011011011010100110111001 step 41 100001100110100100011011000000000001111100011011011010100110111001 step 42 100001100110100100011011010000000001111100011011011010100110111001 step 43 100001100110100100011011011000000001111100011011011010100110111001 step 44 100001100110100100011011011010000001111100011011011010100110111001 step 45 100001100110100100011011011011000001111100011011011010100110111001 step 46 100001100110100100011011011011010001111100011011011010100110111001 step 47 100001100110100100011011011011011001111100011011011010100110111001 step 48 100001100110100100011011011011011101111100011011011010100110111001 step 49 110001100110100100011011011011011100110111011011011010100110111001 step 50 100001100110100100011011011011011101111100011011011010100110111001 step 51 101001100110100100011011011011011100110111011011011010100110111001 step 52 100001100110100100011011011011011101111100011011011010100110111001 step 53 100101100110100100011011011011011100110111011011011010100110111001 step 54 100001100110100100011011011011011101111100011011011010100110111001 step 55 100011100110100100011011011011011100110111011011011010100110111001 step 56 100001100110100100011011011011011101111100011011011010100110111001 step 57 100001110110100100011011011011011100110111011011011010100110111001 step 58 100001100110100100011011011011011101111100011011011010100110111001 step 59 100001101110100100011011011011011100110111011011011010100110111001 step 60 100001100110100100011011011011011101111100011011011010100110111001 step 61 100001100111100100011011011011011100111101011011011010100110111001 step 62 100001100110100100011011011011011101111100011011011010100110111001 step 63 100001100110110100011011011011011100111101011011011010100110111001 step 64 100001100110100100011011011011011101111100011011011010100110111001 step 65 100001100110101100011011011011011101110110011011011010100110111001 step 66 100001100110100100011011011011011101111100011011011010100110111001 step 67 100001100110100110011011011011011101110110011011011010100110111001 step 68 100001100110100100011011011011011101111100011011011010100110111001 step 69 100001100110100101011011011011011101001111011011011010100110111001 step 70 100001100110100100011011011011011101111100011011011010100110111001 step 71 100001100110100100111011011011011101001111011011011010100110111001 step 72 100001100110100100011011011011011101111100011011011010100110111001 step 73 100001100110100100011111011011011101001111011011011010100110111001 step 74 100001100110100100011011011011011101111100011011011010100110111001 step 75 100001100110100100011011111011011101001111011011011010100110111001 step 76 100001100110100100011011011011011101111100011011011010100110111001 step 77 100001100110100100011011011111011101001111011011011010100110111001 step 78 100001100110100100011011011011011101111100011011011010100110111001 step 79 100001100110100100011011011011111101001111011011011010100110111001 step 80 100001100110100100011011011011011101111100011011011010100110111001 step 81 100001100110100100011011011011011111101110011011011010100110111001 step 82 100001100110100100011011011011011101111100011011011010100110111001 test 3: pass SLOT BAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBAABBAAAAAAAAAAAAAABBBBBBBBAB LETTER ALPSLFMDEEMCBFRSPKLEMFHRSCJLJKUHPNMBBNNVVRKRHUTDJUKANJHBTPDFSVDEVU SIDE 121212122121212121111111112212122222112222111221112112212112212212 DIRECTION IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIOOOOOOOIOOIOOIOOIOOOOIOOIIOOIIO this fail all fails was hi 111111111111111111111111111111111111111111111111111111111111111 1 rising ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ ^^^^^^^^^^^^^^^^^^^^ ^^ falling vvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvv vvvvvvvvvvvvvvvvvvvv vv was lo 00000000000000000000000000000000000000 00000000000000000000 0000 total fails 0, total passes 3 step 1 100000000000000000000000000000000001111100011011011010100110111001 step 2 100000000000000000000000000000000001111100100011011010100110111001 step 3 100000000000000000000000000000000001111100000011011010100110111001 step 4 100000000000000000000000000000000001111100000100011010100110111001 step 5 100000000000000000000000000000000001111100000000011010100110111001 step 6 100000000000000000000000000000000001111100000000100010100110111001 step 7 100000000000000000000000000000000001111100000000000010100110111001 step 8 100000000000000000000000000000000001111100000000000101010110111001 step 9 100000000000000000000000000000000001111100000000000001010110111001 step 10 100000000000000000000000000000000001111100000000000001011000111001 step 11 100000000000000000000000000000000001111100000000000001010000111001 step 12 100000000000000000000000000000000001111100000000000001010001100001 step 13 100000000000000000000000000000000001111100000000000001010000100001 step 14 100000000000000000000000000000000001111100000000000001010000100001 step 15 100000000000010000000000000000000000111101000000000001010000100001 step 16 100000000000010010000000000000000000110111000000000001010000100001 step 17 100000000000010010000000000000000000110111111000000001010000100001 step 18 100000000000010010000000000000000000110111011000000001010000100001 step 19 100000000000010010000000000000000000110111011111000001010000100001 step 20 100000000000010010000000000000000000110111011011000001010000100001 step 21 100000000000010010000000000000000000110111011011111001010000100001 step 22 100000000000010010000000000000000000110111011011011001010000100001 step 23 100000000000010010000000000000000000110111011011011110100000100001 step 24 100000000000010010000000000000000000110111011011011010100000100001 step 25 100000000000010010000000000000000000110111011011011010101110100001 step 26 100000000000010010000000000000000000110111011011011010100110100001 step 27 100000000000010010000000000000000000110111011011011010100111111001 step 28 100000000000010010000000000000000000110111011011011010100110111001 step 29 100000000000000010000000000000000001110110011011011010100110111001 step 30 100000000000000000000000000000000001111100011011011010100110111001 step 31 100000000000000000000000000000000001111100011011011010100110111001 step 32 100001000000000000000000000000000001111100011011011010100110111001 step 33 100001100000000000000000000000000001111100011011011010100110111001 step 34 100001100100000000000000000000000001111100011011011010100110111001 step 35 100001100110000000000000000000000001111100011011011010100110111001 step 36 100001100110100000000000000000000001111100011011011010100110111001 step 37 100001100110100100000000000000000001111100011011011010100110111001 step 38 100001100110100100010000000000000001111100011011011010100110111001 step 39 100001100110100100011000000000000001111100011011011010100110111001 step 40 100001100110100100011010000000000001111100011011011010100110111001 step 41 100001100110100100011011000000000001111100011011011010100110111001 step 42 100001100110100100011011010000000001111100011011011010100110111001 step 43 100001100110100100011011011000000001111100011011011010100110111001 step 44 100001100110100100011011011010000001111100011011011010100110111001 step 45 100001100110100100011011011011000001111100011011011010100110111001 step 46 100001100110100100011011011011010001111100011011011010100110111001 step 47 100001100110100100011011011011011001111100011011011010100110111001 step 48 100001100110100100011011011011011101111100011011011010100110111001 step 49 110001100110100100011011011011011100110111011011011010100110111001 step 50 100001100110100100011011011011011101111100011011011010100110111001 step 51 101001100110100100011011011011011100110111011011011010100110111001 step 52 100001100110100100011011011011011101111100011011011010100110111001 step 53 100101100110100100011011011011011100110111011011011010100110111001 step 54 100001100110100100011011011011011101111100011011011010100110111001 step 55 100011100110100100011011011011011100110111011011011010100110111001 step 56 100001100110100100011011011011011101111100011011011010100110111001 step 57 100001110110100100011011011011011100110111011011011010100110111001 step 58 100001100110100100011011011011011101111100011011011010100110111001 step 59 100001101110100100011011011011011100110111011011011010100110111001 step 60 100001100110100100011011011011011101111100011011011010100110111001 step 61 100001100111100100011011011011011100111101011011011010100110111001 step 62 100001100110100100011011011011011101111100011011011010100110111001 step 63 100001100110110100011011011011011100111101011011011010100110111001 step 64 100001100110100100011011011011011101111100011011011010100110111001 step 65 100001100110101100011011011011011101110110011011011010100110111001 step 66 100001100110100100011011011011011101111100011011011010100110111001 step 67 100001100110100110011011011011011101110110011011011010100110111001 step 68 100001100110100100011011011011011101111100011011011010100110111001 step 69 100001100110100101011011011011011101001111011011011010100110111001 step 70 100001100110100100011011011011011101111100011011011010100110111001 step 71 100001100110100100111011011011011101001111011011011010100110111001 step 72 100001100110100100011011011011011101111100011011011010100110111001 step 73 100001100110100100011111011011011101001111011011011010100110111001 step 74 100001100110100100011011011011011101111100011011011010100110111001 step 75 100001100110100100011011111011011101001111011011011010100110111001 step 76 100001100110100100011011011011011101111100011011011010100110111001 step 77 100001100110100100011011011111011101001111011011011010100110111001 step 78 100001100110100100011011011011011101111100011011011010100110111001 step 79 100001100110100100011011011011111101001111011011011010100110111001 step 80 100001100110100100011011011011011101111100011011011010100110111001 step 81 100001100110100100011011011011011111101110011011011010100110111001 step 82 100001100110100100011011011011011101111100011011011010100110111001 test 4: pass SLOT BAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBAABBAAAAAAAAAAAAAABBBBBBBBAB LETTER ALPSLFMDEEMCBFRSPKLEMFHRSCJLJKUHPNMBBNNVVRKRHUTDJUKANJHBTPDFSVDEVU SIDE 121212122121212121111111112212122222112222111221112112212112212212 DIRECTION IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIOOOOOOOIOOIOOIOOIOOOOIOOIIOOIIO this fail all fails was hi 111111111111111111111111111111111111111111111111111111111111111 1 rising ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ ^^^^^^^^^^^^^^^^^^^^ ^^ falling vvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvv vvvvvvvvvvvvvvvvvvvv vv was lo 00000000000000000000000000000000000000 00000000000000000000 0000 total fails 0, total passes 4 step 1 100000000000000000000000000000000001111100011011011010100110111001 step 2 100000000000000000000000000000000001111100100011011010100110111001 step 3 100000000000000000000000000000000001111100000011011010100110111001 step 4 100000000000000000000000000000000001111100000100011010100110111001 step 5 100000000000000000000000000000000001111100000000011010100110111001 step 6 100000000000000000000000000000000001111100000000100010100110111001 step 7 100000000000000000000000000000000001111100000000000010100110111001 step 8 100000000000000000000000000000000001111100000000000101010110111001 step 9 100000000000000000000000000000000001111100000000000001010110111001 step 10 100000000000000000000000000000000001111100000000000001011000111001 step 11 100000000000000000000000000000000001111100000000000001010000111001 step 12 100000000000000000000000000000000001111100000000000001010001100001 step 13 100000000000000000000000000000000001111100000000000001010000100001 step 14 100000000000000000000000000000000001111100000000000001010000100001 step 15 100000000000010000000000000000000000111101000000000001010000100001 step 16 100000000000010010000000000000000000110111000000000001010000100001 step 17 100000000000010010000000000000000000110111111000000001010000100001 step 18 100000000000010010000000000000000000110111011000000001010000100001 step 19 100000000000010010000000000000000000110111011111000001010000100001 step 20 100000000000010010000000000000000000110111011011000001010000100001 step 21 100000000000010010000000000000000000110111011011111001010000100001 step 22 100000000000010010000000000000000000110111011011011001010000100001 step 23 100000000000010010000000000000000000110111011011011110100000100001 step 24 100000000000010010000000000000000000110111011011011010100000100001 step 25 100000000000010010000000000000000000110111011011011010101110100001 step 26 100000000000010010000000000000000000110111011011011010100110100001 step 27 100000000000010010000000000000000000110111011011011010100111111001 step 28 100000000000010010000000000000000000110111011011011010100110111001 step 29 100000000000000010000000000000000001110110011011011010100110111001 step 30 100000000000000000000000000000000001111100011011011010100110111001 step 31 100000000000000000000000000000000001111100011011011010100110111001 step 32 100001000000000000000000000000000001111100011011011010100110111001 step 33 100001100000000000000000000000000001111100011011011010100110111001 step 34 100001100100000000000000000000000001111100011011011010100110111001 step 35 100001100110000000000000000000000001111100011011011010100110111001 step 36 100001100110100000000000000000000001111100011011011010100110111001 step 37 100001100110100100000000000000000001111100011011011010100110111001 step 38 100001100110100100010000000000000001111100011011011010100110111001 step 39 100001100110100100011000000000000001111100011011011010100110111001 step 40 100001100110100100011010000000000001111100011011011010100110111001 step 41 100001100110100100011011000000000001111100011011011010100110111001 step 42 100001100110100100011011010000000001111100011011011010100110111001 step 43 100001100110100100011011011000000001111100011011011010100110111001 step 44 100001100110100100011011011010000001111100011011011010100110111001 step 45 100001100110100100011011011011000001111100011011011010100110111001 step 46 100001100110100100011011011011010001111100011011011010100110111001 step 47 100001100110100100011011011011011001111100011011011010100110111001 step 48 100001100110100100011011011011011101111100011011011010100110111001 step 49 110001100110100100011011011011011100110111011011011010100110111001 step 50 100001100110100100011011011011011101111100011011011010100110111001 step 51 101001100110100100011011011011011100110111011011011010100110111001 step 52 100001100110100100011011011011011101111100011011011010100110111001 step 53 100101100110100100011011011011011100110111011011011010100110111001 step 54 100001100110100100011011011011011101111100011011011010100110111001 step 55 100011100110100100011011011011011100110111011011011010100110111001 step 56 100001100110100100011011011011011101111100011011011010100110111001 step 57 100001110110100100011011011011011100110111011011011010100110111001 step 58 100001100110100100011011011011011101111100011011011010100110111001 step 59 100001101110100100011011011011011100110111011011011010100110111001 step 60 100001100110100100011011011011011101111100011011011010100110111001 step 61 100001100111100100011011011011011100111101011011011010100110111001 step 62 100001100110100100011011011011011101111100011011011010100110111001 step 63 100001100110110100011011011011011100111101011011011010100110111001 step 64 100001100110100100011011011011011101111100011011011010100110111001 step 65 100001100110101100011011011011011101110110011011011010100110111001 step 66 100001100110100100011011011011011101111100011011011010100110111001 step 67 100001100110100110011011011011011101110110011011011010100110111001 step 68 100001100110100100011011011011011101111100011011011010100110111001 step 69 100001100110100101011011011011011101001111011011011010100110111001 step 70 100001100110100100011011011011011101111100011011011010100110111001 step 71 100001100110100100111011011011011101001111011011011010100110111001 step 72 100001100110100100011011011011011101111100011011011010100110111001 step 73 100001100110100100011111011011011101001111011011011010100110111001 step 74 100001100110100100011011011011011101111100011011011010100110111001 step 75 100001100110100100011011111011011101001111011011011010100110111001 step 76 100001100110100100011011011011011101111100011011011010100110111001 step 77 100001100110100100011011011111011101001111011011011010100110111001 step 78 100001100110100100011011011011011101111100011011011010100110111001 step 79 100001100110100100011011011011111101001111011011011010100110111001 step 80 100001100110100100011011011011011101111100011011011010100110111001 step 81 100001100110100100011011011011011111101110011011011010100110111001 step 82 100001100110100100011011011011011101111100011011011010100110111001 test 5: pass SLOT BAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBAABBAAAAAAAAAAAAAABBBBBBBBAB LETTER ALPSLFMDEEMCBFRSPKLEMFHRSCJLJKUHPNMBBNNVVRKRHUTDJUKANJHBTPDFSVDEVU SIDE 121212122121212121111111112212122222112222111221112112212112212212 DIRECTION IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIOOOOOOOIOOIOOIOOIOOOOIOOIIOOIIO this fail all fails was hi 111111111111111111111111111111111111111111111111111111111111111 1 rising ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ ^^^^^^^^^^^^^^^^^^^^ ^^ falling vvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvv vvvvvvvvvvvvvvvvvvvv vv was lo 00000000000000000000000000000000000000 00000000000000000000 0000 total fails 0, total passes 5 step 1 100000000000000000000000000000000001111100011011011010100110111001 step 2 100000000000000000000000000000000001111100100011011010100110111001 step 3 100000000000000000000000000000000001111100000011011010100110111001 step 4 100000000000000000000000000000000001111100000100011010100110111001 step 5 100000000000000000000000000000000001111100000000011010100110111001 step 6 100000000000000000000000000000000001111100000000100010100110111001 step 7 100000000000000000000000000000000001111100000000000010100110111001 step 8 100000000000000000000000000000000001111100000000000101010110111001 step 9 100000000000000000000000000000000001111100000000000001010110111001 step 10 100000000000000000000000000000000001111100000000000001011000111001 step 11 100000000000000000000000000000000001111100000000000001010000111001 step 12 100000000000000000000000000000000001111100000000000001010001100001 step 13 100000000000000000000000000000000001111100000000000001010000100001 step 14 100000000000000000000000000000000001111100000000000001010000100001 step 15 100000000000010000000000000000000000111101000000000001010000100001 step 16 100000000000010010000000000000000000110111000000000001010000100001 step 17 100000000000010010000000000000000000110111111000000001010000100001 step 18 100000000000010010000000000000000000110111011000000001010000100001 step 19 100000000000010010000000000000000000110111011111000001010000100001 step 20 100000000000010010000000000000000000110111011011000001010000100001 step 21 100000000000010010000000000000000000110111011011111001010000100001 step 22 100000000000010010000000000000000000110111011011011001010000100001 step 23 100000000000010010000000000000000000110111011011011110100000100001 step 24 100000000000010010000000000000000000110111011011011010100000100001 step 25 100000000000010010000000000000000000110111011011011010101110100001 step 26 100000000000010010000000000000000000110111011011011010100110100001 step 27 100000000000010010000000000000000000110111011011011010100111111001 step 28 100000000000010010000000000000000000110111011011011010100110111001 step 29 100000000000000010000000000000000001110110011011011010100110111001 step 30 100000000000000000000000000000000001111100011011011010100110111001 step 31 100000000000000000000000000000000001111100011011011010100110111001 step 32 100001000000000000000000000000000001111100011011011010100110111001 step 33 100001100000000000000000000000000001111100011011011010100110111001 step 34 100001100100000000000000000000000001111100011011011010100110111001 step 35 100001100110000000000000000000000001111100011011011010100110111001 step 36 100001100110100000000000000000000001111100011011011010100110111001 step 37 100001100110100100000000000000000001111100011011011010100110111001 step 38 100001100110100100010000000000000001111100011011011010100110111001 step 39 100001100110100100011000000000000001111100011011011010100110111001 step 40 100001100110100100011010000000000001111100011011011010100110111001 step 41 100001100110100100011011000000000001111100011011011010100110111001 step 42 100001100110100100011011010000000001111100011011011010100110111001 step 43 100001100110100100011011011000000001111100011011011010100110111001 step 44 100001100110100100011011011010000001111100011011011010100110111001 step 45 100001100110100100011011011011000001111100011011011010100110111001 step 46 100001100110100100011011011011010001111100011011011010100110111001 step 47 100001100110100100011011011011011001111100011011011010100110111001 step 48 100001100110100100011011011011011101111100011011011010100110111001 step 49 110001100110100100011011011011011100110111011011011010100110111001 step 50 100001100110100100011011011011011101111100011011011010100110111001 step 51 101001100110100100011011011011011100110111011011011010100110111001 step 52 100001100110100100011011011011011101111100011011011010100110111001 step 53 100101100110100100011011011011011100110111011011011010100110111001 step 54 100001100110100100011011011011011101111100011011011010100110111001 step 55 100011100110100100011011011011011100110111011011011010100110111001 step 56 100001100110100100011011011011011101111100011011011010100110111001 step 57 100001110110100100011011011011011100110111011011011010100110111001 step 58 100001100110100100011011011011011101111100011011011010100110111001 step 59 100001101110100100011011011011011100110111011011011010100110111001 step 60 100001100110100100011011011011011101111100011011011010100110111001 step 61 100001100111100100011011011011011100111101011011011010100110111001 step 62 100001100110100100011011011011011101111100011011011010100110111001 step 63 100001100110110100011011011011011100111101011011011010100110111001 step 64 100001100110100100011011011011011101111100011011011010100110111001 step 65 100001100110101100011011011011011101110110011011011010100110111001 step 66 100001100110100100011011011011011101111100011011011010100110111001 step 67 100001100110100110011011011011011101110110011011011010100110111001 step 68 100001100110100100011011011011011101111100011011011010100110111001 step 69 100001100110100101011011011011011101001111011011011010100110111001 step 70 100001100110100100011011011011011101111100011011011010100110111001 step 71 100001100110100100111011011011011101001111011011011010100110111001 step 72 100001100110100100011011011011011101111100011011011010100110111001 step 73 100001100110100100011111011011011101001111011011011010100110111001 step 74 100001100110100100011011011011011101111100011011011010100110111001 step 75 100001100110100100011011111011011101001111011011011010100110111001 step 76 100001100110100100011011011011011101111100011011011010100110111001 step 77 100001100110100100011011011111011101001111011011011010100110111001 step 78 100001100110100100011011011011011101111100011011011010100110111001 step 79 100001100110100100011011011011111101001111011011011010100110111001 step 80 100001100110100100011011011011011101111100011011011010100110111001 step 81 100001100110100100011011011011011111101110011011011010100110111001 step 82 100001100110100100011011011011011101111100011011011010100110111001 test 6: pass SLOT BAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBAABBAAAAAAAAAAAAAABBBBBBBBAB LETTER ALPSLFMDEEMCBFRSPKLEMFHRSCJLJKUHPNMBBNNVVRKRHUTDJUKANJHBTPDFSVDEVU SIDE 121212122121212121111111112212122222112222111221112112212112212212 DIRECTION IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIOOOOOOOIOOIOOIOOIOOOOIOOIIOOIIO this fail all fails was hi 111111111111111111111111111111111111111111111111111111111111111 1 rising ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ ^^^^^^^^^^^^^^^^^^^^ ^^ falling vvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvv vvvvvvvvvvvvvvvvvvvv vv was lo 00000000000000000000000000000000000000 00000000000000000000 0000 total fails 0, total passes 6 step 1 100000000000000000000000000000000001111100011011011010100110111001 step 2 100000000000000000000000000000000001111100100011011010100110111001 step 3 100000000000000000000000000000000001111100000011011010100110111001 step 4 100000000000000000000000000000000001111100000100011010100110111001 step 5 100000000000000000000000000000000001111100000000011010100110111001 step 6 100000000000000000000000000000000001111100000000100010100110111001 step 7 100000000000000000000000000000000001111100000000000010100110111001 step 8 100000000000000000000000000000000001111100000000000101010110111001 step 9 100000000000000000000000000000000001111100000000000001010110111001 step 10 100000000000000000000000000000000001111100000000000001011000111001 step 11 100000000000000000000000000000000001111100000000000001010000111001 step 12 100000000000000000000000000000000001111100000000000001010001100001 step 13 100000000000000000000000000000000001111100000000000001010000100001 step 14 100000000000000000000000000000000001111100000000000001010000100001 step 15 100000000000010000000000000000000000111101000000000001010000100001 step 16 100000000000010010000000000000000000110111000000000001010000100001 step 17 100000000000010010000000000000000000110111111000000001010000100001 step 18 100000000000010010000000000000000000110111011000000001010000100001 step 19 100000000000010010000000000000000000110111011111000001010000100001 step 20 100000000000010010000000000000000000110111011011000001010000100001 step 21 100000000000010010000000000000000000110111011011111001010000100001 step 22 100000000000010010000000000000000000110111011011011001010000100001 step 23 100000000000010010000000000000000000110111011011011110100000100001 step 24 100000000000010010000000000000000000110111011011011010100000100001 step 25 100000000000010010000000000000000000110111011011011010101110100001 step 26 100000000000010010000000000000000000110111011011011010100110100001 step 27 100000000000010010000000000000000000110111011011011010100111111001 step 28 100000000000010010000000000000000000110111011011011010100110111001 step 29 100000000000000010000000000000000001110110011011011010100110111001 step 30 100000000000000000000000000000000001111100011011011010100110111001 step 31 100000000000000000000000000000000001111100011011011010100110111001 step 32 100001000000000000000000000000000001111100011011011010100110111001 step 33 100001100000000000000000000000000001111100011011011010100110111001 step 34 100001100100000000000000000000000001111100011011011010100110111001 step 35 100001100110000000000000000000000001111100011011011010100110111001 step 36 100001100110100000000000000000000001111100011011011010100110111001 step 37 100001100110100100000000000000000001111100011011011010100110111001 step 38 100001100110100100010000000000000001111100011011011010100110111001 step 39 100001100110100100011000000000000001111100011011011010100110111001 step 40 100001100110100100011010000000000001111100011011011010100110111001 step 41 100001100110100100011011000000000001111100011011011010100110111001 step 42 100001100110100100011011010000000001111100011011011010100110111001 step 43 100001100110100100011011011000000001111100011011011010100110111001 step 44 100001100110100100011011011010000001111100011011011010100110111001 step 45 100001100110100100011011011011000001111100011011011010100110111001 step 46 100001100110100100011011011011010001111100011011011010100110111001 step 47 100001100110100100011011011011011001111100011011011010100110111001 step 48 100001100110100100011011011011011101111100011011011010100110111001 step 49 110001100110100100011011011011011100110111011011011010100110111001 step 50 100001100110100100011011011011011101111100011011011010100110111001 step 51 101001100110100100011011011011011100110111011011011010100110111001 step 52 100001100110100100011011011011011101111100011011011010100110111001 step 53 100101100110100100011011011011011100110111011011011010100110111001 step 54 100001100110100100011011011011011101111100011011011010100110111001 step 55 100011100110100100011011011011011100110111011011011010100110111001 step 56 100001100110100100011011011011011101111100011011011010100110111001 step 57 100001110110100100011011011011011100110111011011011010100110111001 step 58 100001100110100100011011011011011101111100011011011010100110111001 step 59 100001101110100100011011011011011100110111011011011010100110111001 step 60 100001100110100100011011011011011101111100011011011010100110111001 step 61 100001100111100100011011011011011100111101011011011010100110111001 step 62 100001100110100100011011011011011101111100011011011010100110111001 step 63 100001100110110100011011011011011100111101011011011010100110111001 step 64 100001100110100100011011011011011101111100011011011010100110111001 step 65 100001100110101100011011011011011101110110011011011010100110111001 step 66 100001100110100100011011011011011101111100011011011010100110111001 step 67 100001100110100110011011011011011101110110011011011010100110111001 step 68 100001100110100100011011011011011101111100011011011010100110111001 step 69 100001100110100101011011011011011101001111011011011010100110111001 step 70 100001100110100100011011011011011101111100011011011010100110111001 step 71 100001100110100100111011011011011101001111011011011010100110111001 step 72 100001100110100100011011011011011101111100011011011010100110111001 step 73 100001100110100100011111011011011101001111011011011010100110111001 step 74 100001100110100100011011011011011101111100011011011010100110111001 step 75 100001100110100100011011111011011101001111011011011010100110111001 step 76 100001100110100100011011011011011101111100011011011010100110111001 step 77 100001100110100100011011011111011101001111011011011010100110111001 step 78 100001100110100100011011011011011101111100011011011010100110111001 step 79 100001100110100100011011011011111101001111011011011010100110111001 step 80 100001100110100100011011011011011101111100011011011010100110111001 step 81 100001100110100100011011011011011111101110011011011010100110111001 step 82 100001100110100100011011011011011101111100011011011010100110111001 test 7: pass SLOT BAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBAABBAAAAAAAAAAAAAABBBBBBBBAB LETTER ALPSLFMDEEMCBFRSPKLEMFHRSCJLJKUHPNMBBNNVVRKRHUTDJUKANJHBTPDFSVDEVU SIDE 121212122121212121111111112212122222112222111221112112212112212212 DIRECTION IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIOOOOOOOIOOIOOIOOIOOOOIOOIIOOIIO this fail all fails was hi 111111111111111111111111111111111111111111111111111111111111111 1 rising ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ ^^^^^^^^^^^^^^^^^^^^ ^^ falling vvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvv vvvvvvvvvvvvvvvvvvvv vv was lo 00000000000000000000000000000000000000 00000000000000000000 0000 total fails 0, total passes 7 step 1 100000000000000000000000000000000001111100011011011010100110111001 step 2 100000000000000000000000000000000001111100100011011010100110111001 step 3 100000000000000000000000000000000001111100000011011010100110111001 step 4 100000000000000000000000000000000001111100000100011010100110111001 step 5 100000000000000000000000000000000001111100000000011010100110111001 step 6 100000000000000000000000000000000001111100000000100010100110111001 step 7 100000000000000000000000000000000001111100000000000010100110111001 step 8 100000000000000000000000000000000001111100000000000101010110111001 step 9 100000000000000000000000000000000001111100000000000001010110111001 step 10 100000000000000000000000000000000001111100000000000001011000111001 step 11 100000000000000000000000000000000001111100000000000001010000111001 step 12 100000000000000000000000000000000001111100000000000001010001100001 step 13 100000000000000000000000000000000001111100000000000001010000100001 step 14 100000000000000000000000000000000001111100000000000001010000100001 step 15 100000000000010000000000000000000000111101000000000001010000100001 step 16 100000000000010010000000000000000000110111000000000001010000100001 step 17 100000000000010010000000000000000000110111111000000001010000100001 step 18 100000000000010010000000000000000000110111011000000001010000100001 step 19 100000000000010010000000000000000000110111011111000001010000100001 step 20 100000000000010010000000000000000000110111011011000001010000100001 step 21 100000000000010010000000000000000000110111011011111001010000100001 step 22 100000000000010010000000000000000000110111011011011001010000100001 step 23 100000000000010010000000000000000000110111011011011110100000100001 step 24 100000000000010010000000000000000000110111011011011010100000100001 step 25 100000000000010010000000000000000000110111011011011010101110100001 step 26 100000000000010010000000000000000000110111011011011010100110100001 step 27 100000000000010010000000000000000000110111011011011010100111111001 step 28 100000000000010010000000000000000000110111011011011010100110111001 step 29 100000000000000010000000000000000001110110011011011010100110111001 step 30 100000000000000000000000000000000001111100011011011010100110111001 step 31 100000000000000000000000000000000001111100011011011010100110111001 step 32 100001000000000000000000000000000001111100011011011010100110111001 step 33 100001100000000000000000000000000001111100011011011010100110111001 step 34 100001100100000000000000000000000001111100011011011010100110111001 step 35 100001100110000000000000000000000001111100011011011010100110111001 step 36 100001100110100000000000000000000001111100011011011010100110111001 step 37 100001100110100100000000000000000001111100011011011010100110111001 step 38 100001100110100100010000000000000001111100011011011010100110111001 step 39 100001100110100100011000000000000001111100011011011010100110111001 step 40 100001100110100100011010000000000001111100011011011010100110111001 step 41 100001100110100100011011000000000001111100011011011010100110111001 step 42 100001100110100100011011010000000001111100011011011010100110111001 step 43 100001100110100100011011011000000001111100011011011010100110111001 step 44 100001100110100100011011011010000001111100011011011010100110111001 step 45 100001100110100100011011011011000001111100011011011010100110111001 step 46 100001100110100100011011011011010001111100011011011010100110111001 step 47 100001100110100100011011011011011001111100011011011010100110111001 step 48 100001100110100100011011011011011101111100011011011010100110111001 step 49 110001100110100100011011011011011100110111011011011010100110111001 step 50 100001100110100100011011011011011101111100011011011010100110111001 step 51 101001100110100100011011011011011100110111011011011010100110111001 step 52 100001100110100100011011011011011101111100011011011010100110111001 step 53 100101100110100100011011011011011100110111011011011010100110111001 step 54 100001100110100100011011011011011101111100011011011010100110111001 step 55 100011100110100100011011011011011100110111011011011010100110111001 step 56 100001100110100100011011011011011101111100011011011010100110111001 step 57 100001110110100100011011011011011100110111011011011010100110111001 step 58 100001100110100100011011011011011101111100011011011010100110111001 step 59 100001101110100100011011011011011100110111011011011010100110111001 step 60 100001100110100100011011011011011101111100011011011010100110111001 step 61 100001100111100100011011011011011100111101011011011010100110111001 step 62 100001100110100100011011011011011101111100011011011010100110111001 step 63 100001100110110100011011011011011100111101011011011010100110111001 step 64 100001100110100100011011011011011101111100011011011010100110111001 step 65 100001100110101100011011011011011101110110011011011010100110111001 step 66 100001100110100100011011011011011101111100011011011010100110111001 step 67 100001100110100110011011011011011101110110011011011010100110111001 step 68 100001100110100100011011011011011101111100011011011010100110111001 step 69 100001100110100101011011011011011101001111011011011010100110111001 step 70 100001100110100100011011011011011101111100011011011010100110111001 step 71 100001100110100100111011011011011101001111011011011010100110111001 step 72 100001100110100100011011011011011101111100011011011010100110111001 step 73 100001100110100100011111011011011101001111011011011010100110111001 step 74 100001100110100100011011011011011101111100011011011010100110111001 step 75 100001100110100100011011111011011101001111011011011010100110111001 step 76 100001100110100100011011011011011101111100011011011010100110111001 step 77 100001100110100100011011011111011101001111011011011010100110111001 step 78 100001100110100100011011011011011101111100011011011010100110111001 step 79 100001100110100100011011011011111101001111011011011010100110111001 step 80 100001100110100100011011011011011101111100011011011010100110111001 step 81 100001100110100100011011011011011111101110011011011010100110111001 step 82 100001100110100100011011011011011101111100011011011010100110111001 test 8: pass SLOT BAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBAABBAAAAAAAAAAAAAABBBBBBBBAB LETTER ALPSLFMDEEMCBFRSPKLEMFHRSCJLJKUHPNMBBNNVVRKRHUTDJUKANJHBTPDFSVDEVU SIDE 121212122121212121111111112212122222112222111221112112212112212212 DIRECTION IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIOOOOOOOIOOIOOIOOIOOOOIOOIIOOIIO this fail all fails was hi 111111111111111111111111111111111111111111111111111111111111111 1 rising ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ ^^^^^^^^^^^^^^^^^^^^ ^^ falling vvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvv vvvvvvvvvvvvvvvvvvvv vv was lo 00000000000000000000000000000000000000 00000000000000000000 0000 total fails 0, total passes 8 step 1 100000000000000000000000000000000001111100011011011010100110111001 step 2 100000000000000000000000000000000001111100100011011010100110111001 step 3 100000000000000000000000000000000001111100000011011010100110111001 step 4 100000000000000000000000000000000001111100000100011010100110111001 step 5 100000000000000000000000000000000001111100000000011010100110111001 step 6 100000000000000000000000000000000001111100000000100010100110111001 step 7 100000000000000000000000000000000001111100000000000010100110111001 step 8 100000000000000000000000000000000001111100000000000101010110111001 step 9 100000000000000000000000000000000001111100000000000001010110111001 step 10 100000000000000000000000000000000001111100000000000001011000111001 step 11 100000000000000000000000000000000001111100000000000001010000111001 step 12 100000000000000000000000000000000001111100000000000001010001100001 step 13 100000000000000000000000000000000001111100000000000001010000100001 step 14 100000000000000000000000000000000001111100000000000001010000100001 step 15 100000000000010000000000000000000000111101000000000001010000100001 step 16 100000000000010010000000000000000000110111000000000001010000100001 step 17 100000000000010010000000000000000000110111111000000001010000100001 step 18 100000000000010010000000000000000000110111011000000001010000100001 step 19 100000000000010010000000000000000000110111011111000001010000100001 step 20 100000000000010010000000000000000000110111011011000001010000100001 step 21 100000000000010010000000000000000000110111011011111001010000100001 step 22 100000000000010010000000000000000000110111011011011001010000100001 step 23 100000000000010010000000000000000000110111011011011110100000100001 step 24 100000000000010010000000000000000000110111011011011010100000100001 step 25 100000000000010010000000000000000000110111011011011010101110100001 step 26 100000000000010010000000000000000000110111011011011010100110100001 step 27 100000000000010010000000000000000000110111011011011010100111111001 step 28 100000000000010010000000000000000000110111011011011010100110111001 step 29 100000000000000010000000000000000001110110011011011010100110111001 step 30 100000000000000000000000000000000001111100011011011010100110111001 step 31 100000000000000000000000000000000001111100011011011010100110111001 step 32 100001000000000000000000000000000001111100011011011010100110111001 step 33 100001100000000000000000000000000001111100011011011010100110111001 step 34 100001100100000000000000000000000001111100011011011010100110111001 step 35 100001100110000000000000000000000001111100011011011010100110111001 step 36 100001100110100000000000000000000001111100011011011010100110111001 step 37 100001100110100100000000000000000001111100011011011010100110111001 step 38 100001100110100100010000000000000001111100011011011010100110111001 step 39 100001100110100100011000000000000001111100011011011010100110111001 step 40 100001100110100100011010000000000001111100011011011010100110111001 step 41 100001100110100100011011000000000001111100011011011010100110111001 step 42 100001100110100100011011010000000001111100011011011010100110111001 step 43 100001100110100100011011011000000001111100011011011010100110111001 step 44 100001100110100100011011011010000001111100011011011010100110111001 step 45 100001100110100100011011011011000001111100011011011010100110111001 step 46 100001100110100100011011011011010001111100011011011010100110111001 step 47 100001100110100100011011011011011001111100011011011010100110111001 step 48 100001100110100100011011011011011101111100011011011010100110111001 step 49 110001100110100100011011011011011100110111011011011010100110111001 step 50 100001100110100100011011011011011101111100011011011010100110111001 step 51 101001100110100100011011011011011100110111011011011010100110111001 step 52 100001100110100100011011011011011101111100011011011010100110111001 step 53 100101100110100100011011011011011100110111011011011010100110111001 step 54 100001100110100100011011011011011101111100011011011010100110111001 step 55 100011100110100100011011011011011100110111011011011010100110111001 step 56 100001100110100100011011011011011101111100011011011010100110111001 step 57 100001110110100100011011011011011100110111011011011010100110111001 step 58 100001100110100100011011011011011101111100011011011010100110111001 step 59 100001101110100100011011011011011100110111011011011010100110111001 step 60 100001100110100100011011011011011101111100011011011010100110111001 step 61 100001100111100100011011011011011100111101011011011010100110111001 step 62 100001100110100100011011011011011101111100011011011010100110111001 step 63 100001100110110100011011011011011100111101011011011010100110111001 step 64 100001100110100100011011011011011101111100011011011010100110111001 step 65 100001100110101100011011011011011101110110011011011010100110111001 step 66 100001100110100100011011011011011101111100011011011010100110111001 step 67 100001100110100110011011011011011101110110011011011010100110111001 step 68 100001100110100100011011011011011101111100011011011010100110111001 step 69 100001100110100101011011011011011101001111011011011010100110111001 step 70 100001100110100100011011011011011101111100011011011010100110111001 step 71 100001100110100100111011011011011101001111011011011010100110111001 step 72 100001100110100100011011011011011101111100011011011010100110111001 step 73 100001100110100100011111011011011101001111011011011010100110111001 step 74 100001100110100100011011011011011101111100011011011010100110111001 step 75 100001100110100100011011111011011101001111011011011010100110111001 step 76 100001100110100100011011011011011101111100011011011010100110111001 step 77 100001100110100100011011011111011101001111011011011010100110111001 step 78 100001100110100100011011011011011101111100011011011010100110111001 step 79 100001100110100100011011011011111101001111011011011010100110111001 step 80 100001100110100100011011011011011101111100011011011010100110111001 step 81 100001100110100100011011011011011111101110011011011010100110111001 step 82 100001100110100100011011011011011101111100011011011010100110111001 test 9: pass SLOT BAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBAABBAAAAAAAAAAAAAABBBBBBBBAB LETTER ALPSLFMDEEMCBFRSPKLEMFHRSCJLJKUHPNMBBNNVVRKRHUTDJUKANJHBTPDFSVDEVU SIDE 121212122121212121111111112212122222112222111221112112212112212212 DIRECTION IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIOOOOOOOIOOIOOIOOIOOOOIOOIIOOIIO this fail all fails was hi 111111111111111111111111111111111111111111111111111111111111111 1 rising ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ ^^^^^^^^^^^^^^^^^^^^ ^^ falling vvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvv vvvvvvvvvvvvvvvvvvvv vv was lo 00000000000000000000000000000000000000 00000000000000000000 0000 total fails 0, total passes 9 step 1 100000000000000000000000000000000001111100011011011010100110111001 step 2 100000000000000000000000000000000001111100100011011010100110111001 step 3 100000000000000000000000000000000001111100000011011010100110111001 step 4 100000000000000000000000000000000001111100000100011010100110111001 step 5 100000000000000000000000000000000001111100000000011010100110111001 step 6 100000000000000000000000000000000001111100000000100010100110111001 step 7 100000000000000000000000000000000001111100000000000010100110111001 step 8 100000000000000000000000000000000001111100000000000101010110111001 step 9 100000000000000000000000000000000001111100000000000001010110111001 step 10 100000000000000000000000000000000001111100000000000001011000111001 step 11 100000000000000000000000000000000001111100000000000001010000111001 step 12 100000000000000000000000000000000001111100000000000001010001100001 step 13 100000000000000000000000000000000001111100000000000001010000100001 step 14 100000000000000000000000000000000001111100000000000001010000100001 step 15 100000000000010000000000000000000000111101000000000001010000100001 step 16 100000000000010010000000000000000000110111000000000001010000100001 step 17 100000000000010010000000000000000000110111111000000001010000100001 step 18 100000000000010010000000000000000000110111011000000001010000100001 step 19 100000000000010010000000000000000000110111011111000001010000100001 step 20 100000000000010010000000000000000000110111011011000001010000100001 step 21 100000000000010010000000000000000000110111011011111001010000100001 step 22 100000000000010010000000000000000000110111011011011001010000100001 step 23 100000000000010010000000000000000000110111011011011110100000100001 step 24 100000000000010010000000000000000000110111011011011010100000100001 step 25 100000000000010010000000000000000000110111011011011010101110100001 step 26 100000000000010010000000000000000000110111011011011010100110100001 step 27 100000000000010010000000000000000000110111011011011010100111111001 step 28 100000000000010010000000000000000000110111011011011010100110111001 step 29 100000000000000010000000000000000001110110011011011010100110111001 step 30 100000000000000000000000000000000001111100011011011010100110111001 step 31 100000000000000000000000000000000001111100011011011010100110111001 step 32 100001000000000000000000000000000001111100011011011010100110111001 step 33 100001100000000000000000000000000001111100011011011010100110111001 step 34 100001100100000000000000000000000001111100011011011010100110111001 step 35 100001100110000000000000000000000001111100011011011010100110111001 step 36 100001100110100000000000000000000001111100011011011010100110111001 step 37 100001100110100100000000000000000001111100011011011010100110111001 step 38 100001100110100100010000000000000001111100011011011010100110111001 step 39 100001100110100100011000000000000001111100011011011010100110111001 step 40 100001100110100100011010000000000001111100011011011010100110111001 step 41 100001100110100100011011000000000001111100011011011010100110111001 step 42 100001100110100100011011010000000001111100011011011010100110111001 step 43 100001100110100100011011011000000001111100011011011010100110111001 step 44 100001100110100100011011011010000001111100011011011010100110111001 step 45 100001100110100100011011011011000001111100011011011010100110111001 step 46 100001100110100100011011011011010001111100011011011010100110111001 step 47 100001100110100100011011011011011001111100011011011010100110111001 step 48 100001100110100100011011011011011101111100011011011010100110111001 step 49 110001100110100100011011011011011100110111011011011010100110111001 step 50 100001100110100100011011011011011101111100011011011010100110111001 step 51 101001100110100100011011011011011100110111011011011010100110111001 step 52 100001100110100100011011011011011101111100011011011010100110111001 step 53 100101100110100100011011011011011100110111011011011010100110111001 step 54 100001100110100100011011011011011101111100011011011010100110111001 step 55 100011100110100100011011011011011100110111011011011010100110111001 step 56 100001100110100100011011011011011101111100011011011010100110111001 step 57 100001110110100100011011011011011100110111011011011010100110111001 step 58 100001100110100100011011011011011101111100011011011010100110111001 step 59 100001101110100100011011011011011100110111011011011010100110111001 step 60 100001100110100100011011011011011101111100011011011010100110111001 step 61 100001100111100100011011011011011100111101011011011010100110111001 step 62 100001100110100100011011011011011101111100011011011010100110111001 step 63 100001100110110100011011011011011100111101011011011010100110111001 step 64 100001100110100100011011011011011101111100011011011010100110111001 step 65 100001100110101100011011011011011101110110011011011010100110111001 step 66 100001100110100100011011011011011101111100011011011010100110111001 step 67 100001100110100110011011011011011101110110011011011010100110111001 step 68 100001100110100100011011011011011101111100011011011010100110111001 step 69 100001100110100101011011011011011101001111011011011010100110111001 step 70 100001100110100100011011011011011101111100011011011010100110111001 step 71 100001100110100100111011011011011101001111011011011010100110111001 step 72 100001100110100100011011011011011101111100011011011010100110111001 step 73 100001100110100100011111011011011101001111011011011010100110111001 step 74 100001100110100100011011011011011101111100011011011010100110111001 step 75 100001100110100100011011111011011101001111011011011010100110111001 step 76 100001100110100100011011011011011101111100011011011010100110111001 step 77 100001100110100100011011011111011101001111011011011010100110111001 step 78 100001100110100100011011011011011101111100011011011010100110111001 step 79 100001100110100100011011011011111101001111011011011010100110111001 step 80 100001100110100100011011011011011101111100011011011010100110111001 step 81 100001100110100100011011011011011111101110011011011010100110111001 step 82 100001100110100100011011011011011101111100011011011010100110111001 test 10: pass SLOT BAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBAABBAAAAAAAAAAAAAABBBBBBBBAB LETTER ALPSLFMDEEMCBFRSPKLEMFHRSCJLJKUHPNMBBNNVVRKRHUTDJUKANJHBTPDFSVDEVU SIDE 121212122121212121111111112212122222112222111221112112212112212212 DIRECTION IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIOOOOOOOIOOIOOIOOIOOOOIOOIIOOIIO this fail all fails was hi 111111111111111111111111111111111111111111111111111111111111111 1 rising ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ ^^^^^^^^^^^^^^^^^^^^ ^^ falling vvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvv vvvvvvvvvvvvvvvvvvvv vv was lo 00000000000000000000000000000000000000 00000000000000000000 0000 total fails 0, total passes 10 step 1 100000000000000000000000000000000001111100011011011010100110111001 step 2 100000000000000000000000000000000001111100100011011010100110111001 step 3 100000000000000000000000000000000001111100000011011010100110111001 step 4 100000000000000000000000000000000001111100000100011010100110111001 step 5 100000000000000000000000000000000001111100000000011010100110111001 step 6 100000000000000000000000000000000001111100000000100010100110111001 step 7 100000000000000000000000000000000001111100000000000010100110111001 step 8 100000000000000000000000000000000001111100000000000101010110111001 step 9 100000000000000000000000000000000001111100000000000001010110111001 step 10 100000000000000000000000000000000001111100000000000001011000111001 step 11 100000000000000000000000000000000001111100000000000001010000111001 step 12 100000000000000000000000000000000001111100000000000001010001100001 step 13 100000000000000000000000000000000001111100000000000001010000100001 step 14 100000000000000000000000000000000001111100000000000001010000100001 step 15 100000000000010000000000000000000000111101000000000001010000100001 step 16 100000000000010010000000000000000000110111000000000001010000100001 step 17 100000000000010010000000000000000000110111111000000001010000100001 step 18 100000000000010010000000000000000000110111011000000001010000100001 step 19 100000000000010010000000000000000000110111011111000001010000100001 step 20 100000000000010010000000000000000000110111011011000001010000100001 step 21 100000000000010010000000000000000000110111011011111001010000100001 step 22 100000000000010010000000000000000000110111011011011001010000100001 step 23 100000000000010010000000000000000000110111011011011110100000100001 step 24 100000000000010010000000000000000000110111011011011010100000100001 step 25 100000000000010010000000000000000000110111011011011010101110100001 step 26 100000000000010010000000000000000000110111011011011010100110100001 step 27 100000000000010010000000000000000000110111011011011010100111111001 step 28 100000000000010010000000000000000000110111011011011010100110111001 step 29 100000000000000010000000000000000001110110011011011010100110111001 step 30 100000000000000000000000000000000001111100011011011010100110111001 step 31 100000000000000000000000000000000001111100011011011010100110111001 step 32 100001000000000000000000000000000001111100011011011010100110111001 step 33 100001100000000000000000000000000001111100011011011010100110111001 step 34 100001100100000000000000000000000001111100011011011010100110111001 step 35 100001100110000000000000000000000001111100011011011010100110111001 step 36 100001100110100000000000000000000001111100011011011010100110111001 step 37 100001100110100100000000000000000001111100011011011010100110111001 step 38 100001100110100100010000000000000001111100011011011010100110111001 step 39 100001100110100100011000000000000001111100011011011010100110111001 step 40 100001100110100100011010000000000001111100011011011010100110111001 step 41 100001100110100100011011000000000001111100011011011010100110111001 step 42 100001100110100100011011010000000001111100011011011010100110111001 step 43 100001100110100100011011011000000001111100011011011010100110111001 step 44 100001100110100100011011011010000001111100011011011010100110111001 step 45 100001100110100100011011011011000001111100011011011010100110111001 step 46 100001100110100100011011011011010001111100011011011010100110111001 step 47 100001100110100100011011011011011001111100011011011010100110111001 step 48 100001100110100100011011011011011101111100011011011010100110111001 step 49 110001100110100100011011011011011100110111011011011010100110111001 step 50 100001100110100100011011011011011101111100011011011010100110111001 step 51 101001100110100100011011011011011100110111011011011010100110111001 step 52 100001100110100100011011011011011101111100011011011010100110111001 step 53 100101100110100100011011011011011100110111011011011010100110111001 step 54 100001100110100100011011011011011101111100011011011010100110111001 step 55 100011100110100100011011011011011100110111011011011010100110111001 step 56 100001100110100100011011011011011101111100011011011010100110111001 step 57 100001110110100100011011011011011100110111011011011010100110111001 step 58 100001100110100100011011011011011101111100011011011010100110111001 step 59 100001101110100100011011011011011100110111011011011010100110111001 step 60 100001100110100100011011011011011101111100011011011010100110111001 step 61 100001100111100100011011011011011100111101011011011010100110111001 step 62 100001100110100100011011011011011101111100011011011010100110111001 step 63 100001100110110100011011011011011100111101011011011010100110111001 step 64 100001100110100100011011011011011101111100011011011010100110111001 step 65 100001100110101100011011011011011101110110011011011010100110111001 step 66 100001100110100100011011011011011101111100011011011010100110111001 step 67 100001100110100110011011011011011101110110011011011010100110111001 step 68 100001100110100100011011011011011101111100011011011010100110111001 step 69 100001100110100101011011011011011101001111011011011010100110111001 step 70 100001100110100100011011011011011101111100011011011010100110111001 step 71 100001100110100100111011011011011101001111011011011010100110111001 step 72 100001100110100100011011011011011101111100011011011010100110111001 step 73 100001100110100100011111011011011101001111011011011010100110111001 step 74 100001100110100100011011011011011101111100011011011010100110111001 step 75 100001100110100100011011111011011101001111011011011010100110111001 step 76 100001100110100100011011011011011101111100011011011010100110111001 step 77 100001100110100100011011011111011101001111011011011010100110111001 step 78 100001100110100100011011011011011101111100011011011010100110111001 step 79 100001100110100100011011011011111101001111011011011010100110111001 step 80 100001100110100100011011011011011101111100011011011010100110111001 step 81 100001100110100100011011011011011111101110011011011010100110111001 step 82 100001100110100100011011011011011101111100011011011010100110111001 test 11: pass SLOT BAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBAABBAAAAAAAAAAAAAABBBBBBBBAB LETTER ALPSLFMDEEMCBFRSPKLEMFHRSCJLJKUHPNMBBNNVVRKRHUTDJUKANJHBTPDFSVDEVU SIDE 121212122121212121111111112212122222112222111221112112212112212212 DIRECTION IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIOOOOOOOIOOIOOIOOIOOOOIOOIIOOIIO this fail all fails was hi 111111111111111111111111111111111111111111111111111111111111111 1 rising ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ ^^^^^^^^^^^^^^^^^^^^ ^^ falling vvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvv vvvvvvvvvvvvvvvvvvvv vv was lo 00000000000000000000000000000000000000 00000000000000000000 0000 total fails 0, total passes 11 step 1 100000000000000000000000000000000001111100011011011010100110111001 step 2 100000000000000000000000000000000001111100100011011010100110111001 step 3 100000000000000000000000000000000001111100000011011010100110111001 step 4 100000000000000000000000000000000001111100000100011010100110111001 step 5 100000000000000000000000000000000001111100000000011010100110111001 step 6 100000000000000000000000000000000001111100000000100010100110111001 step 7 100000000000000000000000000000000001111100000000000010100110111001 step 8 100000000000000000000000000000000001111100000000000101010110111001 step 9 100000000000000000000000000000000001111100000000000001010110111001 step 10 100000000000000000000000000000000001111100000000000001011000111001 step 11 100000000000000000000000000000000001111100000000000001010000111001 step 12 100000000000000000000000000000000001111100000000000001010001100001 step 13 100000000000000000000000000000000001111100000000000001010000100001 step 14 100000000000000000000000000000000001111100000000000001010000100001 step 15 100000000000010000000000000000000000111101000000000001010000100001 step 16 100000000000010010000000000000000000110111000000000001010000100001 step 17 100000000000010010000000000000000000110111111000000001010000100001 step 18 100000000000010010000000000000000000110111011000000001010000100001 step 19 100000000000010010000000000000000000110111011111000001010000100001 step 20 100000000000010010000000000000000000110111011011000001010000100001 step 21 100000000000010010000000000000000000110111011011111001010000100001 step 22 100000000000010010000000000000000000110111011011011001010000100001 step 23 100000000000010010000000000000000000110111011011011110100000100001 step 24 100000000000010010000000000000000000110111011011011010100000100001 step 25 100000000000010010000000000000000000110111011011011010101110100001 step 26 100000000000010010000000000000000000110111011011011010100110100001 step 27 100000000000010010000000000000000000110111011011011010100111111001 step 28 100000000000010010000000000000000000110111011011011010100110111001 step 29 100000000000000010000000000000000001110110011011011010100110111001 step 30 100000000000000000000000000000000001111100011011011010100110111001 step 31 100000000000000000000000000000000001111100011011011010100110111001 step 32 100001000000000000000000000000000001111100011011011010100110111001 step 33 100001100000000000000000000000000001111100011011011010100110111001 step 34 100001100100000000000000000000000001111100011011011010100110111001 step 35 100001100110000000000000000000000001111100011011011010100110111001 step 36 100001100110100000000000000000000001111100011011011010100110111001 step 37 100001100110100100000000000000000001111100011011011010100110111001 step 38 100001100110100100010000000000000001111100011011011010100110111001 step 39 100001100110100100011000000000000001111100011011011010100110111001 step 40 100001100110100100011010000000000001111100011011011010100110111001 step 41 100001100110100100011011000000000001111100011011011010100110111001 step 42 100001100110100100011011010000000001111100011011011010100110111001 step 43 100001100110100100011011011000000001111100011011011010100110111001 step 44 100001100110100100011011011010000001111100011011011010100110111001 step 45 100001100110100100011011011011000001111100011011011010100110111001 step 46 100001100110100100011011011011010001111100011011011010100110111001 step 47 100001100110100100011011011011011001111100011011011010100110111001 step 48 100001100110100100011011011011011101111100011011011010100110111001 step 49 110001100110100100011011011011011100110111011011011010100110111001 step 50 100001100110100100011011011011011101111100011011011010100110111001 step 51 101001100110100100011011011011011100110111011011011010100110111001 step 52 100001100110100100011011011011011101111100011011011010100110111001 step 53 100101100110100100011011011011011100110111011011011010100110111001 step 54 100001100110100100011011011011011101111100011011011010100110111001 step 55 100011100110100100011011011011011100110111011011011010100110111001 step 56 100001100110100100011011011011011101111100011011011010100110111001 step 57 100001110110100100011011011011011100110111011011011010100110111001 step 58 100001100110100100011011011011011101111100011011011010100110111001 step 59 100001101110100100011011011011011100110111011011011010100110111001 step 60 100001100110100100011011011011011101111100011011011010100110111001 step 61 100001100111100100011011011011011100111101011011011010100110111001 step 62 100001100110100100011011011011011101111100011011011010100110111001 step 63 100001100110110100011011011011011100111101011011011010100110111001 step 64 100001100110100100011011011011011101111100011011011010100110111001 step 65 100001100110101100011011011011011101110110011011011010100110111001 step 66 100001100110100100011011011011011101111100011011011010100110111001 step 67 100001100110100110011011011011011101110110011011011010100110111001 step 68 100001100110100100011011011011011101111100011011011010100110111001 step 69 100001100110100101011011011011011101001111011011011010100110111001 step 70 100001100110100100011011011011011101111100011011011010100110111001 step 71 100001100110100100111011011011011101001111011011011010100110111001 step 72 100001100110100100011011011011011101111100011011011010100110111001 step 73 100001100110100100011111011011011101001111011011011010100110111001 step 74 100001100110100100011011011011011101111100011011011010100110111001 step 75 100001100110100100011011111011011101001111011011011010100110111001 step 76 100001100110100100011011011011011101111100011011011010100110111001 step 77 100001100110100100011011011111011101001111011011011010100110111001 step 78 100001100110100100011011011011011101111100011011011010100110111001 step 79 100001100110100100011011011011111101001111011011011010100110111001 step 80 100001100110100100011011011011011101111100011011011010100110111001 step 81 100001100110100100011011011011011111101110011011011010100110111001 step 82 100001100110100100011011011011011101111100011011011010100110111001 test 12: pass SLOT BAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBAABBAAAAAAAAAAAAAABBBBBBBBAB LETTER ALPSLFMDEEMCBFRSPKLEMFHRSCJLJKUHPNMBBNNVVRKRHUTDJUKANJHBTPDFSVDEVU SIDE 121212122121212121111111112212122222112222111221112112212112212212 DIRECTION IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIOOOOOOOIOOIOOIOOIOOOOIOOIIOOIIO this fail all fails was hi 111111111111111111111111111111111111111111111111111111111111111 1 rising ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ ^^^^^^^^^^^^^^^^^^^^ ^^ falling vvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvv vvvvvvvvvvvvvvvvvvvv vv was lo 00000000000000000000000000000000000000 00000000000000000000 0000 total fails 0, total passes 12 step 1 100000000000000000000000000000000001111100011011011010100110111001 step 2 100000000000000000000000000000000001111100100011011010100110111001 step 3 100000000000000000000000000000000001111100000011011010100110111001 step 4 100000000000000000000000000000000001111100000100011010100110111001 step 5 100000000000000000000000000000000001111100000000011010100110111001 step 6 100000000000000000000000000000000001111100000000100010100110111001 step 7 100000000000000000000000000000000001111100000000000010100110111001 step 8 100000000000000000000000000000000001111100000000000101010110111001 step 9 100000000000000000000000000000000001111100000000000001010110111001 step 10 100000000000000000000000000000000001111100000000000001011000111001 step 11 100000000000000000000000000000000001111100000000000001010000111001 step 12 100000000000000000000000000000000001111100000000000001010001100001 step 13 100000000000000000000000000000000001111100000000000001010000100001 step 14 100000000000000000000000000000000001111100000000000001010000100001 step 15 100000000000010000000000000000000000111101000000000001010000100001 step 16 100000000000010010000000000000000000110111000000000001010000100001 step 17 100000000000010010000000000000000000110111111000000001010000100001 step 18 100000000000010010000000000000000000110111011000000001010000100001 step 19 100000000000010010000000000000000000110111011111000001010000100001 step 20 100000000000010010000000000000000000110111011011000001010000100001 step 21 100000000000010010000000000000000000110111011011111001010000100001 step 22 100000000000010010000000000000000000110111011011011001010000100001 step 23 100000000000010010000000000000000000110111011011011110100000100001 step 24 100000000000010010000000000000000000110111011011011010100000100001 step 25 100000000000010010000000000000000000110111011011011010101110100001 step 26 100000000000010010000000000000000000110111011011011010100110100001 step 27 100000000000010010000000000000000000110111011011011010100111111001 step 28 100000000000010010000000000000000000110111011011011010100110111001 step 29 100000000000000010000000000000000001110110011011011010100110111001 step 30 100000000000000000000000000000000001111100011011011010100110111001 step 31 100000000000000000000000000000000001111100011011011010100110111001 step 32 100001000000000000000000000000000001111100011011011010100110111001 step 33 100001100000000000000000000000000001111100011011011010100110111001 step 34 100001100100000000000000000000000001111100011011011010100110111001 step 35 100001100110000000000000000000000001111100011011011010100110111001 step 36 100001100110100000000000000000000001111100011011011010100110111001 step 37 100001100110100100000000000000000001111100011011011010100110111001 step 38 100001100110100100010000000000000001111100011011011010100110111001 step 39 100001100110100100011000000000000001111100011011011010100110111001 step 40 100001100110100100011010000000000001111100011011011010100110111001 step 41 100001100110100100011011000000000001111100011011011010100110111001 step 42 100001100110100100011011010000000001111100011011011010100110111001 step 43 100001100110100100011011011000000001111100011011011010100110111001 step 44 100001100110100100011011011010000001111100011011011010100110111001 step 45 100001100110100100011011011011000001111100011011011010100110111001 step 46 100001100110100100011011011011010001111100011011011010100110111001 step 47 100001100110100100011011011011011001111100011011011010100110111001 step 48 100001100110100100011011011011011101111100011011011010100110111001 step 49 110001100110100100011011011011011100110111011011011010100110111001 step 50 100001100110100100011011011011011101111100011011011010100110111001 step 51 101001100110100100011011011011011100110111011011011010100110111001 step 52 100001100110100100011011011011011101111100011011011010100110111001 step 53 100101100110100100011011011011011100110111011011011010100110111001 step 54 100001100110100100011011011011011101111100011011011010100110111001 step 55 100011100110100100011011011011011100110111011011011010100110111001 step 56 100001100110100100011011011011011101111100011011011010100110111001 step 57 100001110110100100011011011011011100110111011011011010100110111001 step 58 100001100110100100011011011011011101111100011011011010100110111001 step 59 100001101110100100011011011011011100110111011011011010100110111001 step 60 100001100110100100011011011011011101111100011011011010100110111001 step 61 100001100111100100011011011011011100111101011011011010100110111001 step 62 100001100110100100011011011011011101111100011011011010100110111001 step 63 100001100110110100011011011011011100111101011011011010100110111001 step 64 100001100110100100011011011011011101111100011011011010100110111001 step 65 100001100110101100011011011011011101110110011011011010100110111001 step 66 100001100110100100011011011011011101111100011011011010100110111001 step 67 100001100110100110011011011011011101110110011011011010100110111001 step 68 100001100110100100011011011011011101111100011011011010100110111001 step 69 100001100110100101011011011011011101001111011011011010100110111001 step 70 100001100110100100011011011011011101111100011011011010100110111001 step 71 100001100110100100111011011011011101001111011011011010100110111001 step 72 100001100110100100011011011011011101111100011011011010100110111001 step 73 100001100110100100011111011011011101001111011011011010100110111001 step 74 100001100110100100011011011011011101111100011011011010100110111001 step 75 100001100110100100011011111011011101001111011011011010100110111001 step 76 100001100110100100011011011011011101111100011011011010100110111001 step 77 100001100110100100011011011111011101001111011011011010100110111001 step 78 100001100110100100011011011011011101111100011011011010100110111001 step 79 100001100110100100011011011011111101001111011011011010100110111001 step 80 100001100110100100011011011011011101111100011011011010100110111001 step 81 100001100110100100011011011011011111101110011011011010100110111001 step 82 100001100110100100011011011011011101111100011011011010100110111001 test 13: pass SLOT BAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBAABBAAAAAAAAAAAAAABBBBBBBBAB LETTER ALPSLFMDEEMCBFRSPKLEMFHRSCJLJKUHPNMBBNNVVRKRHUTDJUKANJHBTPDFSVDEVU SIDE 121212122121212121111111112212122222112222111221112112212112212212 DIRECTION IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIOOOOOOOIOOIOOIOOIOOOOIOOIIOOIIO this fail all fails was hi 111111111111111111111111111111111111111111111111111111111111111 1 rising ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ ^^^^^^^^^^^^^^^^^^^^ ^^ falling vvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvv vvvvvvvvvvvvvvvvvvvv vv was lo 00000000000000000000000000000000000000 00000000000000000000 0000 total fails 0, total passes 13 step 1 100000000000000000000000000000000001111100011011011010100110111001 step 2 100000000000000000000000000000000001111100100011011010100110111001 step 3 100000000000000000000000000000000001111100000011011010100110111001 step 4 100000000000000000000000000000000001111100000100011010100110111001 step 5 100000000000000000000000000000000001111100000000011010100110111001 step 6 100000000000000000000000000000000001111100000000100010100110111001 step 7 100000000000000000000000000000000001111100000000000010100110111001 step 8 100000000000000000000000000000000001111100000000000101010110111001 step 9 100000000000000000000000000000000001111100000000000001010110111001 step 10 100000000000000000000000000000000001111100000000000001011000111001 step 11 100000000000000000000000000000000001111100000000000001010000111001 step 12 100000000000000000000000000000000001111100000000000001010001100001 step 13 100000000000000000000000000000000001111100000000000001010000100001 step 14 100000000000000000000000000000000001111100000000000001010000100001 step 15 100000000000010000000000000000000000111101000000000001010000100001 step 16 100000000000010010000000000000000000110111000000000001010000100001 step 17 100000000000010010000000000000000000110111111000000001010000100001 step 18 100000000000010010000000000000000000110111011000000001010000100001 step 19 100000000000010010000000000000000000110111011111000001010000100001 step 20 100000000000010010000000000000000000110111011011000001010000100001 step 21 100000000000010010000000000000000000110111011011111001010000100001 step 22 100000000000010010000000000000000000110111011011011001010000100001 step 23 100000000000010010000000000000000000110111011011011110100000100001 step 24 100000000000010010000000000000000000110111011011011010100000100001 step 25 100000000000010010000000000000000000110111011011011010101110100001 step 26 100000000000010010000000000000000000110111011011011010100110100001 step 27 100000000000010010000000000000000000110111011011011010100111111001 step 28 100000000000010010000000000000000000110111011011011010100110111001 step 29 100000000000000010000000000000000001110110011011011010100110111001 step 30 100000000000000000000000000000000001111100011011011010100110111001 step 31 100000000000000000000000000000000001111100011011011010100110111001 step 32 100001000000000000000000000000000001111100011011011010100110111001 step 33 100001100000000000000000000000000001111100011011011010100110111001 step 34 100001100100000000000000000000000001111100011011011010100110111001 step 35 100001100110000000000000000000000001111100011011011010100110111001 step 36 100001100110100000000000000000000001111100011011011010100110111001 step 37 100001100110100100000000000000000001111100011011011010100110111001 step 38 100001100110100100010000000000000001111100011011011010100110111001 step 39 100001100110100100011000000000000001111100011011011010100110111001 step 40 100001100110100100011010000000000001111100011011011010100110111001 step 41 100001100110100100011011000000000001111100011011011010100110111001 step 42 100001100110100100011011010000000001111100011011011010100110111001 step 43 100001100110100100011011011000000001111100011011011010100110111001 step 44 100001100110100100011011011010000001111100011011011010100110111001 step 45 100001100110100100011011011011000001111100011011011010100110111001 step 46 100001100110100100011011011011010001111100011011011010100110111001 step 47 100001100110100100011011011011011001111100011011011010100110111001 step 48 100001100110100100011011011011011101111100011011011010100110111001 step 49 110001100110100100011011011011011100110111011011011010100110111001 step 50 100001100110100100011011011011011101111100011011011010100110111001 step 51 101001100110100100011011011011011100110111011011011010100110111001 step 52 100001100110100100011011011011011101111100011011011010100110111001 step 53 100101100110100100011011011011011100110111011011011010100110111001 step 54 100001100110100100011011011011011101111100011011011010100110111001 step 55 100011100110100100011011011011011100110111011011011010100110111001 step 56 100001100110100100011011011011011101111100011011011010100110111001 step 57 100001110110100100011011011011011100110111011011011010100110111001 step 58 100001100110100100011011011011011101111100011011011010100110111001 step 59 100001101110100100011011011011011100110111011011011010100110111001 step 60 100001100110100100011011011011011101111100011011011010100110111001 step 61 100001100111100100011011011011011100111101011011011010100110111001 step 62 100001100110100100011011011011011101111100011011011010100110111001 step 63 100001100110110100011011011011011100111101011011011010100110111001 step 64 100001100110100100011011011011011101111100011011011010100110111001 step 65 100001100110101100011011011011011101110110011011011010100110111001 step 66 100001100110100100011011011011011101111100011011011010100110111001 step 67 100001100110100110011011011011011101110110011011011010100110111001 step 68 100001100110100100011011011011011101111100011011011010100110111001 step 69 100001100110100101011011011011011101001111011011011010100110111001 step 70 100001100110100100011011011011011101111100011011011010100110111001 step 71 100001100110100100111011011011011101001111011011011010100110111001 step 72 100001100110100100011011011011011101111100011011011010100110111001 step 73 100001100110100100011111011011011101001111011011011010100110111001 step 74 100001100110100100011011011011011101111100011011011010100110111001 step 75 100001100110100100011011111011011101001111011011011010100110111001 step 76 100001100110100100011011011011011101111100011011011010100110111001 step 77 100001100110100100011011011111011101001111011011011010100110111001 step 78 100001100110100100011011011011011101111100011011011010100110111001 step 79 100001100110100100011011011011111101001111011011011010100110111001 step 80 100001100110100100011011011011011101111100011011011010100110111001 step 81 100001100110100100011011011011011111101110011011011010100110111001 step 82 100001100110100100011011011011011101111100011011011010100110111001 test 14: pass SLOT BAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBAABBAAAAAAAAAAAAAABBBBBBBBAB LETTER ALPSLFMDEEMCBFRSPKLEMFHRSCJLJKUHPNMBBNNVVRKRHUTDJUKANJHBTPDFSVDEVU SIDE 121212122121212121111111112212122222112222111221112112212112212212 DIRECTION IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIOOOOOOOIOOIOOIOOIOOOOIOOIIOOIIO this fail all fails was hi 111111111111111111111111111111111111111111111111111111111111111 1 rising ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ ^^^^^^^^^^^^^^^^^^^^ ^^ falling vvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvv vvvvvvvvvvvvvvvvvvvv vv was lo 00000000000000000000000000000000000000 00000000000000000000 0000 total fails 0, total passes 14 step 1 100000000000000000000000000000000001111100011011011010100110111001 step 2 100000000000000000000000000000000001111100100011011010100110111001 step 3 100000000000000000000000000000000001111100000011011010100110111001 step 4 100000000000000000000000000000000001111100000100011010100110111001 step 5 100000000000000000000000000000000001111100000000011010100110111001 step 6 100000000000000000000000000000000001111100000000100010100110111001 step 7 100000000000000000000000000000000001111100000000000010100110111001 step 8 100000000000000000000000000000000001111100000000000101010110111001 step 9 100000000000000000000000000000000001111100000000000001010110111001 step 10 100000000000000000000000000000000001111100000000000001011000111001 step 11 100000000000000000000000000000000001111100000000000001010000111001 step 12 100000000000000000000000000000000001111100000000000001010001100001 step 13 100000000000000000000000000000000001111100000000000001010000100001 step 14 100000000000000000000000000000000001111100000000000001010000100001 step 15 100000000000010000000000000000000000111101000000000001010000100001 step 16 100000000000010010000000000000000000110111000000000001010000100001 step 17 100000000000010010000000000000000000110111111000000001010000100001 step 18 100000000000010010000000000000000000110111011000000001010000100001 step 19 100000000000010010000000000000000000110111011111000001010000100001 step 20 100000000000010010000000000000000000110111011011000001010000100001 step 21 100000000000010010000000000000000000110111011011111001010000100001 step 22 100000000000010010000000000000000000110111011011011001010000100001 step 23 100000000000010010000000000000000000110111011011011110100000100001 step 24 100000000000010010000000000000000000110111011011011010100000100001 step 25 100000000000010010000000000000000000110111011011011010101110100001 step 26 100000000000010010000000000000000000110111011011011010100110100001 step 27 100000000000010010000000000000000000110111011011011010100111111001 step 28 100000000000010010000000000000000000110111011011011010100110111001 step 29 100000000000000010000000000000000001110110011011011010100110111001 step 30 100000000000000000000000000000000001111100011011011010100110111001 step 31 100000000000000000000000000000000001111100011011011010100110111001 step 32 100001000000000000000000000000000001111100011011011010100110111001 step 33 100001100000000000000000000000000001111100011011011010100110111001 step 34 100001100100000000000000000000000001111100011011011010100110111001 step 35 100001100110000000000000000000000001111100011011011010100110111001 step 36 100001100110100000000000000000000001111100011011011010100110111001 step 37 100001100110100100000000000000000001111100011011011010100110111001 step 38 100001100110100100010000000000000001111100011011011010100110111001 step 39 100001100110100100011000000000000001111100011011011010100110111001 step 40 100001100110100100011010000000000001111100011011011010100110111001 step 41 100001100110100100011011000000000001111100011011011010100110111001 step 42 100001100110100100011011010000000001111100011011011010100110111001 step 43 100001100110100100011011011000000001111100011011011010100110111001 step 44 100001100110100100011011011010000001111100011011011010100110111001 step 45 100001100110100100011011011011000001111100011011011010100110111001 step 46 100001100110100100011011011011010001111100011011011010100110111001 step 47 100001100110100100011011011011011001111100011011011010100110111001 step 48 100001100110100100011011011011011101111100011011011010100110111001 step 49 110001100110100100011011011011011100110111011011011010100110111001 step 50 100001100110100100011011011011011101111100011011011010100110111001 step 51 101001100110100100011011011011011100110111011011011010100110111001 step 52 100001100110100100011011011011011101111100011011011010100110111001 step 53 100101100110100100011011011011011100110111011011011010100110111001 step 54 100001100110100100011011011011011101111100011011011010100110111001 step 55 100011100110100100011011011011011100110111011011011010100110111001 step 56 100001100110100100011011011011011101111100011011011010100110111001 step 57 100001110110100100011011011011011100110111011011011010100110111001 step 58 100001100110100100011011011011011101111100011011011010100110111001 step 59 100001101110100100011011011011011100110111011011011010100110111001 step 60 100001100110100100011011011011011101111100011011011010100110111001 step 61 100001100111100100011011011011011100111101011011011010100110111001 step 62 100001100110100100011011011011011101111100011011011010100110111001 step 63 100001100110110100011011011011011100111101011011011010100110111001 step 64 100001100110100100011011011011011101111100011011011010100110111001 step 65 100001100110101100011011011011011101110110011011011010100110111001 step 66 100001100110100100011011011011011101111100011011011010100110111001 step 67 100001100110100110011011011011011101110110011011011010100110111001 step 68 100001100110100100011011011011011101111100011011011010100110111001 step 69 100001100110100101011011011011011101001111011011011010100110111001 step 70 100001100110100100011011011011011101111100011011011010100110111001 step 71 100001100110100100111011011011011101001111011011011010100110111001 step 72 100001100110100100011011011011011101111100011011011010100110111001 step 73 100001100110100100011111011011011101001111011011011010100110111001 step 74 100001100110100100011011011011011101111100011011011010100110111001 step 75 100001100110100100011011111011011101001111011011011010100110111001 step 76 100001100110100100011011011011011101111100011011011010100110111001 step 77 100001100110100100011011011111011101001111011011011010100110111001 step 78 100001100110100100011011011011011101111100011011011010100110111001 step 79 100001100110100100011011011011111101001111011011011010100110111001 step 80 100001100110100100011011011011011101111100011011011010100110111001 step 81 100001100110100100011011011011011111101110011011011010100110111001 step 82 100001100110100100011011011011011101111100011011011010100110111001 test 15: pass SLOT BAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBAABBAAAAAAAAAAAAAABBBBBBBBAB LETTER ALPSLFMDEEMCBFRSPKLEMFHRSCJLJKUHPNMBBNNVVRKRHUTDJUKANJHBTPDFSVDEVU SIDE 121212122121212121111111112212122222112222111221112112212112212212 DIRECTION IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIOOOOOOOIOOIOOIOOIOOOOIOOIIOOIIO this fail all fails was hi 111111111111111111111111111111111111111111111111111111111111111 1 rising ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ ^^^^^^^^^^^^^^^^^^^^ ^^ falling vvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvv vvvvvvvvvvvvvvvvvvvv vv was lo 00000000000000000000000000000000000000 00000000000000000000 0000 total fails 0, total passes 15 step 1 100000000000000000000000000000000001111100011011011010100110111001 step 2 100000000000000000000000000000000001111100100011011010100110111001 step 3 100000000000000000000000000000000001111100000011011010100110111001 step 4 100000000000000000000000000000000001111100000100011010100110111001 step 5 100000000000000000000000000000000001111100000000011010100110111001 step 6 100000000000000000000000000000000001111100000000100010100110111001 step 7 100000000000000000000000000000000001111100000000000010100110111001 step 8 100000000000000000000000000000000001111100000000000101010110111001 step 9 100000000000000000000000000000000001111100000000000001010110111001 step 10 100000000000000000000000000000000001111100000000000001011000111001 step 11 100000000000000000000000000000000001111100000000000001010000111001 step 12 100000000000000000000000000000000001111100000000000001010001100001 step 13 100000000000000000000000000000000001111100000000000001010000100001 step 14 100000000000000000000000000000000001111100000000000001010000100001 step 15 100000000000010000000000000000000000111101000000000001010000100001 step 16 100000000000010010000000000000000000110111000000000001010000100001 step 17 100000000000010010000000000000000000110111111000000001010000100001 step 18 100000000000010010000000000000000000110111011000000001010000100001 step 19 100000000000010010000000000000000000110111011111000001010000100001 step 20 100000000000010010000000000000000000110111011011000001010000100001 step 21 100000000000010010000000000000000000110111011011111001010000100001 step 22 100000000000010010000000000000000000110111011011011001010000100001 step 23 100000000000010010000000000000000000110111011011011110100000100001 step 24 100000000000010010000000000000000000110111011011011010100000100001 step 25 100000000000010010000000000000000000110111011011011010101110100001 step 26 100000000000010010000000000000000000110111011011011010100110100001 step 27 100000000000010010000000000000000000110111011011011010100111111001 step 28 100000000000010010000000000000000000110111011011011010100110111001 step 29 100000000000000010000000000000000001110110011011011010100110111001 step 30 100000000000000000000000000000000001111100011011011010100110111001 step 31 100000000000000000000000000000000001111100011011011010100110111001 step 32 100001000000000000000000000000000001111100011011011010100110111001 step 33 100001100000000000000000000000000001111100011011011010100110111001 step 34 100001100100000000000000000000000001111100011011011010100110111001 step 35 100001100110000000000000000000000001111100011011011010100110111001 step 36 100001100110100000000000000000000001111100011011011010100110111001 step 37 100001100110100100000000000000000001111100011011011010100110111001 step 38 100001100110100100010000000000000001111100011011011010100110111001 step 39 100001100110100100011000000000000001111100011011011010100110111001 step 40 100001100110100100011010000000000001111100011011011010100110111001 step 41 100001100110100100011011000000000001111100011011011010100110111001 step 42 100001100110100100011011010000000001111100011011011010100110111001 step 43 100001100110100100011011011000000001111100011011011010100110111001 step 44 100001100110100100011011011010000001111100011011011010100110111001 step 45 100001100110100100011011011011000001111100011011011010100110111001 step 46 100001100110100100011011011011010001111100011011011010100110111001 step 47 100001100110100100011011011011011001111100011011011010100110111001 step 48 100001100110100100011011011011011101111100011011011010100110111001 step 49 110001100110100100011011011011011100110111011011011010100110111001 step 50 100001100110100100011011011011011101111100011011011010100110111001 step 51 101001100110100100011011011011011100110111011011011010100110111001 step 52 100001100110100100011011011011011101111100011011011010100110111001 step 53 100101100110100100011011011011011100110111011011011010100110111001 step 54 100001100110100100011011011011011101111100011011011010100110111001 step 55 100011100110100100011011011011011100110111011011011010100110111001 step 56 100001100110100100011011011011011101111100011011011010100110111001 step 57 100001110110100100011011011011011100110111011011011010100110111001 step 58 100001100110100100011011011011011101111100011011011010100110111001 step 59 100001101110100100011011011011011100110111011011011010100110111001 step 60 100001100110100100011011011011011101111100011011011010100110111001 step 61 100001100111100100011011011011011100111101011011011010100110111001 step 62 100001100110100100011011011011011101111100011011011010100110111001 step 63 100001100110110100011011011011011100111101011011011010100110111001 step 64 100001100110100100011011011011011101111100011011011010100110111001 step 65 100001100110101100011011011011011101110110011011011010100110111001 step 66 100001100110100100011011011011011101111100011011011010100110111001 step 67 100001100110100110011011011011011101110110011011011010100110111001 step 68 100001100110100100011011011011011101111100011011011010100110111001 step 69 100001100110100101011011011011011101001111011011011010100110111001 step 70 100001100110100100011011011011011101111100011011011010100110111001 step 71 100001100110100100111011011011011101001111011011011010100110111001 step 72 100001100110100100011011011011011101111100011011011010100110111001 step 73 100001100110100100011111011011011101001111011011011010100110111001 step 74 100001100110100100011011011011011101111100011011011010100110111001 step 75 100001100110100100011011111011011101001111011011011010100110111001 step 76 100001100110100100011011011011011101111100011011011010100110111001 step 77 100001100110100100011011011111011101001111011011011010100110111001 step 78 100001100110100100011011011011011101111100011011011010100110111001 step 79 100001100110100100011011011011111101001111011011011010100110111001 step 80 100001100110100100011011011011011101111100011011011010100110111001 step 81 100001100110100100011011011011011111101110011011011010100110111001 step 82 100001100110100100011011011011011101111100011011011010100110111001 test 16: pass SLOT BAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBAABBAAAAAAAAAAAAAABBBBBBBBAB LETTER ALPSLFMDEEMCBFRSPKLEMFHRSCJLJKUHPNMBBNNVVRKRHUTDJUKANJHBTPDFSVDEVU SIDE 121212122121212121111111112212122222112222111221112112212112212212 DIRECTION IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIOOOOOOOIOOIOOIOOIOOOOIOOIIOOIIO this fail all fails was hi 111111111111111111111111111111111111111111111111111111111111111 1 rising ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ ^^^^^^^^^^^^^^^^^^^^ ^^ falling vvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvv vvvvvvvvvvvvvvvvvvvv vv was lo 00000000000000000000000000000000000000 00000000000000000000 0000 total fails 0, total passes 16 step 1 100000000000000000000000000000000001111100011011011010100110111001 step 2 100000000000000000000000000000000001111100100011011010100110111001 step 3 100000000000000000000000000000000001111100000011011010100110111001 step 4 100000000000000000000000000000000001111100000100011010100110111001 step 5 100000000000000000000000000000000001111100000000011010100110111001 step 6 100000000000000000000000000000000001111100000000100010100110111001 step 7 100000000000000000000000000000000001111100000000000010100110111001 step 8 100000000000000000000000000000000001111100000000000101010110111001 step 9 100000000000000000000000000000000001111100000000000001010110111001 step 10 100000000000000000000000000000000001111100000000000001011000111001 step 11 100000000000000000000000000000000001111100000000000001010000111001 step 12 100000000000000000000000000000000001111100000000000001010001100001 step 13 100000000000000000000000000000000001111100000000000001010000100001 step 14 100000000000000000000000000000000001111100000000000001010000100001 step 15 100000000000010000000000000000000000111101000000000001010000100001 step 16 100000000000010010000000000000000000110111000000000001010000100001 step 17 100000000000010010000000000000000000110111111000000001010000100001 step 18 100000000000010010000000000000000000110111011000000001010000100001 step 19 100000000000010010000000000000000000110111011111000001010000100001 step 20 100000000000010010000000000000000000110111011011000001010000100001 step 21 100000000000010010000000000000000000110111011011111001010000100001 step 22 100000000000010010000000000000000000110111011011011001010000100001 step 23 100000000000010010000000000000000000110111011011011110100000100001 step 24 100000000000010010000000000000000000110111011011011010100000100001 step 25 100000000000010010000000000000000000110111011011011010101110100001 step 26 100000000000010010000000000000000000110111011011011010100110100001 step 27 100000000000010010000000000000000000110111011011011010100111111001 step 28 100000000000010010000000000000000000110111011011011010100110111001 step 29 100000000000000010000000000000000001110110011011011010100110111001 step 30 100000000000000000000000000000000001111100011011011010100110111001 step 31 100000000000000000000000000000000001111100011011011010100110111001 step 32 100001000000000000000000000000000001111100011011011010100110111001 step 33 100001100000000000000000000000000001111100011011011010100110111001 step 34 100001100100000000000000000000000001111100011011011010100110111001 step 35 100001100110000000000000000000000001111100011011011010100110111001 step 36 100001100110100000000000000000000001111100011011011010100110111001 step 37 100001100110100100000000000000000001111100011011011010100110111001 step 38 100001100110100100010000000000000001111100011011011010100110111001 step 39 100001100110100100011000000000000001111100011011011010100110111001 step 40 100001100110100100011010000000000001111100011011011010100110111001 step 41 100001100110100100011011000000000001111100011011011010100110111001 step 42 100001100110100100011011010000000001111100011011011010100110111001 step 43 100001100110100100011011011000000001111100011011011010100110111001 step 44 100001100110100100011011011010000001111100011011011010100110111001 step 45 100001100110100100011011011011000001111100011011011010100110111001 step 46 100001100110100100011011011011010001111100011011011010100110111001 step 47 100001100110100100011011011011011001111100011011011010100110111001 step 48 100001100110100100011011011011011101111100011011011010100110111001 step 49 110001100110100100011011011011011100110111011011011010100110111001 step 50 100001100110100100011011011011011101111100011011011010100110111001 step 51 101001100110100100011011011011011100110111011011011010100110111001 step 52 100001100110100100011011011011011101111100011011011010100110111001 step 53 100101100110100100011011011011011100110111011011011010100110111001 step 54 100001100110100100011011011011011101111100011011011010100110111001 step 55 100011100110100100011011011011011100110111011011011010100110111001 step 56 100001100110100100011011011011011101111100011011011010100110111001 step 57 100001110110100100011011011011011100110111011011011010100110111001 step 58 100001100110100100011011011011011101111100011011011010100110111001 step 59 100001101110100100011011011011011100110111011011011010100110111001 step 60 100001100110100100011011011011011101111100011011011010100110111001 step 61 100001100111100100011011011011011100111101011011011010100110111001 step 62 100001100110100100011011011011011101111100011011011010100110111001 step 63 100001100110110100011011011011011100111101011011011010100110111001 step 64 100001100110100100011011011011011101111100011011011010100110111001 space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C toggle comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit scope (run, no print) ppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppp pppppppppppppppppppppppppppppppppppppppFFFFFFFFFFFFFFFFFFFFFFFFFFF space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C toggle comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT BAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBAABBAAAAAAAAAAAAAABBBBBBBBAB LETTER ALPSLFMDEEMCBFRSPKLEMFHRSCJLJKUHPNMBBNNVVRKRHUTDJUKANJHBTPDFSVDEVU SIDE 121212122121212121111111112212122222112222111221112112212112212212 DIRECTION IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIOOOOOOOIOOIOOIOOIOOOOIOOIIOOIIO all fails OOOOOOO OO OO OO OOOO OO OO O was lo 00000000000000000000000000000000000000000000000000000000000 00000 falling vvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvv vv v rising ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ ^^^^^^^^^^^^^^^^^^^^ ^^ was hi 111111111111111111111111111111111111111111111111111111111111111 1 total fails 27, total passes 134 Main menu Sat Jul 11 15:59:28 2015 test file is: tests\m222.new delay is: 0 trigger is: 1 1 read test file 2 set test delay 3 set test trigger 4 run test 5 output loading test 8 diags 9 exit exiting tester- PDP8 card tester via printer port version 0.85 June 4, 2015 mapping[] is verified Main menu Sun Jul 12 17:13:49 2015 test file is: delay is: 0 trigger is: 1 1 read test file 2 set test delay 3 set test trigger 4 run test 5 output loading test 8 diags 9 exit Enter test file name? trying to open test file: tests\m119.tst reading test file: tests\m119.tst comment: M119 REV B 3 8-input NAND comment: pins: PINS pins: 1 I AA1 E1-12 pins: 2 I AB1 E1-11 pins: 3 I AC1 E1-5 pins: 4 I AD1 E1-6 pins: 5 I AD2 E1-4 pins: 6 I AE2 E1-3 pins: 7 I AF2 E1-2 pins: 8 I AH2 E1-1 pins: 9 O AJ2 E1-8 pins: 10 I AF1 E2-12 pins: 11 I AH1 E2-11 pins: 12 I AJ1 E2-5 pins: 13 I AK1 E2-6 pins: 14 I AK2 E2-4 pins: 15 I AL2 E2-3 pins: 16 I AM2 E2-2 pins: 17 I AN2 E2-1 pins: 18 O AP2 E2-8 pins: 19 I AM1 E3-12 pins: 20 I AN1 E3-11 pins: 21 I AP1 E3-5 pins: 22 I AR1 E3-6 pins: 23 I AR2 E3-4 pins: 24 I AS2 E3-3 pins: 25 I AT2 E3-2 pins: 26 I AU2 E3-1 pins: 27 O AV2 E3-8 pins: direction: IIIIIIIIOIIIIIIIIOIIIIIIIIO test 1: 000000001000000001000000001 test 2: 000000001 test 3: 000000011 test 4: 000000101 test 5: 000000111 test 6: 000001001 test 7: 000001011 test 8: 000001101 test 9: 000001111 test 10: 000010001 test 11: 000010011 test 12: 000010101 test 13: 000010111 test 14: 000011001 test 15: 000011011 test 16: 000011101 test 17: 000011111 test 18: 000100001 test 19: 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test 72: 010001101 test 73: 010001111 test 74: 010010001 test 75: 010010011 test 76: 010010101 test 77: 010010111 test 78: 010011001 test 79: 010011011 test 80: 010011101 test 81: 010011111 test 82: 010100001 test 83: 010100011 test 84: 010100101 test 85: 010100111 test 86: 010101001 test 87: 010101011 test 88: 010101101 test 89: 010101111 test 90: 010110001 test 91: 010110011 test 92: 010110101 test 93: 010110111 test 94: 010111001 test 95: 010111011 test 96: 010111101 test 97: 010111111 test 98: 011000001 test 99: 011000011 test 100: 011000101 test 101: 011000111 test 102: 011001001 test 103: 011001011 test 104: 011001101 test 105: 011001111 test 106: 011010001 test 107: 011010011 test 108: 011010101 test 109: 011010111 test 110: 011011001 test 111: 011011011 test 112: 011011101 test 113: 011011111 test 114: 011100001 test 115: 011100011 test 116: 011100101 test 117: 011100111 test 118: 011101001 test 119: 011101011 test 120: 011101101 test 121: 011101111 test 122: 011110001 test 123: 011110011 test 124: 011110101 test 125: 011110111 test 126: 011111001 test 127: 011111011 test 128: 011111101 test 129: 011111111 test 130: 100000001 test 131: 100000011 test 132: 100000101 test 133: 100000111 test 134: 100001001 test 135: 100001011 test 136: 100001101 test 137: 100001111 test 138: 100010001 test 139: 100010011 test 140: 100010101 test 141: 100010111 test 142: 100011001 test 143: 100011011 test 144: 100011101 test 145: 100011111 test 146: 100100001 test 147: 100100011 test 148: 100100101 test 149: 100100111 test 150: 100101001 test 151: 100101011 test 152: 100101101 test 153: 100101111 test 154: 100110001 test 155: 100110011 test 156: 100110101 test 157: 100110111 test 158: 100111001 test 159: 100111011 test 160: 100111101 test 161: 100111111 test 162: 101000001 test 163: 101000011 test 164: 101000101 test 165: 101000111 test 166: 101001001 test 167: 101001011 test 168: 101001101 test 169: 101001111 test 170: 101010001 test 171: 101010011 test 172: 101010101 test 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223: 110111011 test 224: 110111101 test 225: 110111111 test 226: 111000001 test 227: 111000011 test 228: 111000101 test 229: 111000111 test 230: 111001001 test 231: 111001011 test 232: 111001101 test 233: 111001111 test 234: 111010001 test 235: 111010011 test 236: 111010101 test 237: 111010111 test 238: 111011001 test 239: 111011011 test 240: 111011101 test 241: 111011111 test 242: 111100001 test 243: 111100011 test 244: 111100101 test 245: 111100111 test 246: 111101001 test 247: 111101011 test 248: 111101101 test 249: 111101111 test 250: 111110001 test 251: 111110011 test 252: 111110101 test 253: 111110111 test 254: 111111001 test 255: 111111011 test 256: 111111101 test 257: 111111110 test 258: 000000001 test 259: 000000001 test 260: 000000011 test 261: 000000101 test 262: 000000111 test 263: 000001001 test 264: 000001011 test 265: 000001101 test 266: 000001111 test 267: 000010001 test 268: 000010011 test 269: 000010101 test 270: 000010111 test 271: 000011001 test 272: 000011011 test 273: 000011101 test 274: 000011111 test 275: 000100001 test 276: 000100011 test 277: 000100101 test 278: 000100111 test 279: 000101001 test 280: 000101011 test 281: 000101101 test 282: 000101111 test 283: 000110001 test 284: 000110011 test 285: 000110101 test 286: 000110111 test 287: 000111001 test 288: 000111011 test 289: 000111101 test 290: 000111111 test 291: 001000001 test 292: 001000011 test 293: 001000101 test 294: 001000111 test 295: 001001001 test 296: 001001011 test 297: 001001101 test 298: 001001111 test 299: 001010001 test 300: 001010011 test 301: 001010101 test 302: 001010111 test 303: 001011001 test 304: 001011011 test 305: 001011101 test 306: 001011111 test 307: 001100001 test 308: 001100011 test 309: 001100101 test 310: 001100111 test 311: 001101001 test 312: 001101011 test 313: 001101101 test 314: 001101111 test 315: 001110001 test 316: 001110011 test 317: 001110101 test 318: 001110111 test 319: 001111001 test 320: 001111011 test 321: 001111101 test 322: 001111111 test 323: 010000001 test 324: 010000011 test 325: 010000101 test 326: 010000111 test 327: 010001001 test 328: 010001011 test 329: 010001101 test 330: 010001111 test 331: 010010001 test 332: 010010011 test 333: 010010101 test 334: 010010111 test 335: 010011001 test 336: 010011011 test 337: 010011101 test 338: 010011111 test 339: 010100001 test 340: 010100011 test 341: 010100101 test 342: 010100111 test 343: 010101001 test 344: 010101011 test 345: 010101101 test 346: 010101111 test 347: 010110001 test 348: 010110011 test 349: 010110101 test 350: 010110111 test 351: 010111001 test 352: 010111011 test 353: 010111101 test 354: 010111111 test 355: 011000001 test 356: 011000011 test 357: 011000101 test 358: 011000111 test 359: 011001001 test 360: 011001011 test 361: 011001101 test 362: 011001111 test 363: 011010001 test 364: 011010011 test 365: 011010101 test 366: 011010111 test 367: 011011001 test 368: 011011011 test 369: 011011101 test 370: 011011111 test 371: 011100001 test 372: 011100011 test 373: 011100101 test 374: 011100111 test 375: 011101001 test 376: 011101011 test 377: 011101101 test 378: 011101111 test 379: 011110001 test 380: 011110011 test 381: 011110101 test 382: 011110111 test 383: 011111001 test 384: 011111011 test 385: 011111101 test 386: 011111111 test 387: 100000001 test 388: 100000011 test 389: 100000101 test 390: 100000111 test 391: 100001001 test 392: 100001011 test 393: 100001101 test 394: 100001111 test 395: 100010001 test 396: 100010011 test 397: 100010101 test 398: 100010111 test 399: 100011001 test 400: 100011011 test 401: 100011101 test 402: 100011111 test 403: 100100001 test 404: 100100011 test 405: 100100101 test 406: 100100111 test 407: 100101001 test 408: 100101011 test 409: 100101101 test 410: 100101111 test 411: 100110001 test 412: 100110011 test 413: 100110101 test 414: 100110111 test 415: 100111001 test 416: 100111011 test 417: 100111101 test 418: 100111111 test 419: 101000001 test 420: 101000011 test 421: 101000101 test 422: 101000111 test 423: 101001001 test 424: 101001011 test 425: 101001101 test 426: 101001111 test 427: 101010001 test 428: 101010011 test 429: 101010101 test 430: 101010111 test 431: 101011001 test 432: 101011011 test 433: 101011101 test 434: 101011111 test 435: 101100001 test 436: 101100011 test 437: 101100101 test 438: 101100111 test 439: 101101001 test 440: 101101011 test 441: 101101101 test 442: 101101111 test 443: 101110001 test 444: 101110011 test 445: 101110101 test 446: 101110111 test 447: 101111001 test 448: 101111011 test 449: 101111101 test 450: 101111111 test 451: 110000001 test 452: 110000011 test 453: 110000101 test 454: 110000111 test 455: 110001001 test 456: 110001011 test 457: 110001101 test 458: 110001111 test 459: 110010001 test 460: 110010011 test 461: 110010101 test 462: 110010111 test 463: 110011001 test 464: 110011011 test 465: 110011101 test 466: 110011111 test 467: 110100001 test 468: 110100011 test 469: 110100101 test 470: 110100111 test 471: 110101001 test 472: 110101011 test 473: 110101101 test 474: 110101111 test 475: 110110001 test 476: 110110011 test 477: 110110101 test 478: 110110111 test 479: 110111001 test 480: 110111011 test 481: 110111101 test 482: 110111111 test 483: 111000001 test 484: 111000011 test 485: 111000101 test 486: 111000111 test 487: 111001001 test 488: 111001011 test 489: 111001101 test 490: 111001111 test 491: 111010001 test 492: 111010011 test 493: 111010101 test 494: 111010111 test 495: 111011001 test 496: 111011011 test 497: 111011101 test 498: 111011111 test 499: 111100001 test 500: 111100011 test 501: 111100101 test 502: 111100111 test 503: 111101001 test 504: 111101011 test 505: 111101101 test 506: 111101111 test 507: 111110001 test 508: 111110011 test 509: 111110101 test 510: 111110111 test 511: 111111001 test 512: 111111011 test 513: 111111101 test 514: 111111110 test 515: 000000001 test 516: 000000001 test 517: 000000011 test 518: 000000101 test 519: 000000111 test 520: 000001001 test 521: 000001011 test 522: 000001101 test 523: 000001111 test 524: 000010001 test 525: 000010011 test 526: 000010101 test 527: 000010111 test 528: 000011001 test 529: 000011011 test 530: 000011101 test 531: 000011111 test 532: 000100001 test 533: 000100011 test 534: 000100101 test 535: 000100111 test 536: 000101001 test 537: 000101011 test 538: 000101101 test 539: 000101111 test 540: 000110001 test 541: 000110011 test 542: 000110101 test 543: 000110111 test 544: 000111001 test 545: 000111011 test 546: 000111101 test 547: 000111111 test 548: 001000001 test 549: 001000011 test 550: 001000101 test 551: 001000111 test 552: 001001001 test 553: 001001011 test 554: 001001101 test 555: 001001111 test 556: 001010001 test 557: 001010011 test 558: 001010101 test 559: 001010111 test 560: 001011001 test 561: 001011011 test 562: 001011101 test 563: 001011111 test 564: 001100001 test 565: 001100011 test 566: 001100101 test 567: 001100111 test 568: 001101001 test 569: 001101011 test 570: 001101101 test 571: 001101111 test 572: 001110001 test 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test 1448: 101000011 test 1449: 101000101 test 1450: 101000111 test 1451: 101001001 test 1452: 101001011 test 1453: 101001101 test 1454: 101001111 test 1455: 101010001 test 1456: 101010011 test 1457: 101010101 test 1458: 101010111 test 1459: 101011001 test 1460: 101011011 test 1461: 101011101 test 1462: 101011111 test 1463: 101100001 test 1464: 101100011 test 1465: 101100101 test 1466: 101100111 test 1467: 101101001 test 1468: 101101011 test 1469: 101101101 test 1470: 101101111 test 1471: 101110001 test 1472: 101110011 test 1473: 101110101 test 1474: 101110111 test 1475: 101111001 test 1476: 101111011 test 1477: 101111101 test 1478: 101111111 test 1479: 110000001 test 1480: 110000011 test 1481: 110000101 test 1482: 110000111 test 1483: 110001001 test 1484: 110001011 test 1485: 110001101 test 1486: 110001111 test 1487: 110010001 test 1488: 110010011 test 1489: 110010101 test 1490: 110010111 test 1491: 110011001 test 1492: 110011011 test 1493: 110011101 test 1494: 110011111 test 1495: 110100001 test 1496: 110100011 test 1497: 110100101 test 1498: 110100111 test 1499: 110101001 test 1500: 110101011 test 1501: 110101101 test 1502: 110101111 test 1503: 110110001 test 1504: 110110011 test 1505: 110110101 test 1506: 110110111 test 1507: 110111001 test 1508: 110111011 test 1509: 110111101 test 1510: 110111111 test 1511: 111000001 test 1512: 111000011 test 1513: 111000101 test 1514: 111000111 test 1515: 111001001 test 1516: 111001011 test 1517: 111001101 test 1518: 111001111 test 1519: 111010001 test 1520: 111010011 test 1521: 111010101 test 1522: 111010111 test 1523: 111011001 test 1524: 111011011 test 1525: 111011101 test 1526: 111011111 test 1527: 111100001 test 1528: 111100011 test 1529: 111100101 test 1530: 111100111 test 1531: 111101001 test 1532: 111101011 test 1533: 111101101 test 1534: 111101111 test 1535: 111110001 test 1536: 111110011 test 1537: 111110101 test 1538: 111110111 test 1539: 111111001 test 1540: 111111011 test 1541: 111111101 test 1542: 111111110 test 1543: 111111110111111110111111110 end: END summary column 1: offset 0, mask 0x8000 column 2: offset 0, mask 0x4000 column 3: offset 0, mask 0x2000 column 4: offset 0, mask 0x1000 column 5: offset 0, mask 0x0010 column 6: offset 0, mask 0x0008 column 7: offset 0, mask 0x0004 column 8: offset 0, mask 0x0002 column 9: offset 0, mask 0x0001 column 10: offset 0, mask 0x0400 column 11: offset 0, mask 0x0200 column 12: offset 0, mask 0x0100 column 13: offset 1, mask 0x8000 column 14: offset 1, mask 0x0001 column 15: offset 1, mask 0x0002 column 16: offset 1, mask 0x0004 column 17: offset 1, mask 0x0008 column 18: offset 1, mask 0x0010 column 19: offset 1, mask 0x2000 column 20: offset 1, mask 0x1000 column 21: offset 1, mask 0x0800 column 22: offset 1, mask 0x0400 column 23: offset 1, mask 0x0020 column 24: offset 1, mask 0x0040 column 25: offset 1, mask 0x0080 column 26: offset 2, mask 0x0001 column 27: offset 2, mask 0x0002 direction bits (1=input) 0x08E1 0x4310 0xFFFA 0xFFFF 0xF0FF pullup bits (1=pullup) 0x0000 0x0000 0x0000 0x0000 0x0000 test step out_data dont care 1: 0x0001 0x0010 0x0002 0x0000 0x0000 2: 0x0001 0x0010 0x0002 0x0000 0x0000 3: 0x0003 0x0010 0x0002 0x0000 0x0000 4: 0x0005 0x0010 0x0002 0x0000 0x0000 5: 0x0007 0x0010 0x0002 0x0000 0x0000 6: 0x0009 0x0010 0x0002 0x0000 0x0000 7: 0x000B 0x0010 0x0002 0x0000 0x0000 8: 0x000D 0x0010 0x0002 0x0000 0x0000 9: 0x000F 0x0010 0x0002 0x0000 0x0000 10: 0x0011 0x0010 0x0002 0x0000 0x0000 11: 0x0013 0x0010 0x0002 0x0000 0x0000 12: 0x0015 0x0010 0x0002 0x0000 0x0000 13: 0x0017 0x0010 0x0002 0x0000 0x0000 14: 0x0019 0x0010 0x0002 0x0000 0x0000 15: 0x001B 0x0010 0x0002 0x0000 0x0000 16: 0x001D 0x0010 0x0002 0x0000 0x0000 17: 0x001F 0x0010 0x0002 0x0000 0x0000 18: 0x1001 0x0010 0x0002 0x0000 0x0000 19: 0x1003 0x0010 0x0002 0x0000 0x0000 20: 0x1005 0x0010 0x0002 0x0000 0x0000 21: 0x1007 0x0010 0x0002 0x0000 0x0000 22: 0x1009 0x0010 0x0002 0x0000 0x0000 23: 0x100B 0x0010 0x0002 0x0000 0x0000 24: 0x100D 0x0010 0x0002 0x0000 0x0000 25: 0x100F 0x0010 0x0002 0x0000 0x0000 26: 0x1011 0x0010 0x0002 0x0000 0x0000 27: 0x1013 0x0010 0x0002 0x0000 0x0000 28: 0x1015 0x0010 0x0002 0x0000 0x0000 29: 0x1017 0x0010 0x0002 0x0000 0x0000 30: 0x1019 0x0010 0x0002 0x0000 0x0000 31: 0x101B 0x0010 0x0002 0x0000 0x0000 32: 0x101D 0x0010 0x0002 0x0000 0x0000 33: 0x101F 0x0010 0x0002 0x0000 0x0000 34: 0x2001 0x0010 0x0002 0x0000 0x0000 35: 0x2003 0x0010 0x0002 0x0000 0x0000 36: 0x2005 0x0010 0x0002 0x0000 0x0000 37: 0x2007 0x0010 0x0002 0x0000 0x0000 38: 0x2009 0x0010 0x0002 0x0000 0x0000 39: 0x200B 0x0010 0x0002 0x0000 0x0000 40: 0x200D 0x0010 0x0002 0x0000 0x0000 41: 0x200F 0x0010 0x0002 0x0000 0x0000 42: 0x2011 0x0010 0x0002 0x0000 0x0000 43: 0x2013 0x0010 0x0002 0x0000 0x0000 44: 0x2015 0x0010 0x0002 0x0000 0x0000 45: 0x2017 0x0010 0x0002 0x0000 0x0000 46: 0x2019 0x0010 0x0002 0x0000 0x0000 47: 0x201B 0x0010 0x0002 0x0000 0x0000 48: 0x201D 0x0010 0x0002 0x0000 0x0000 49: 0x201F 0x0010 0x0002 0x0000 0x0000 50: 0x3001 0x0010 0x0002 0x0000 0x0000 51: 0x3003 0x0010 0x0002 0x0000 0x0000 52: 0x3005 0x0010 0x0002 0x0000 0x0000 53: 0x3007 0x0010 0x0002 0x0000 0x0000 54: 0x3009 0x0010 0x0002 0x0000 0x0000 55: 0x300B 0x0010 0x0002 0x0000 0x0000 56: 0x300D 0x0010 0x0002 0x0000 0x0000 57: 0x300F 0x0010 0x0002 0x0000 0x0000 58: 0x3011 0x0010 0x0002 0x0000 0x0000 59: 0x3013 0x0010 0x0002 0x0000 0x0000 60: 0x3015 0x0010 0x0002 0x0000 0x0000 61: 0x3017 0x0010 0x0002 0x0000 0x0000 62: 0x3019 0x0010 0x0002 0x0000 0x0000 63: 0x301B 0x0010 0x0002 0x0000 0x0000 64: 0x301D 0x0010 0x0002 0x0000 0x0000 65: 0x301F 0x0010 0x0002 0x0000 0x0000 66: 0x4001 0x0010 0x0002 0x0000 0x0000 67: 0x4003 0x0010 0x0002 0x0000 0x0000 68: 0x4005 0x0010 0x0002 0x0000 0x0000 69: 0x4007 0x0010 0x0002 0x0000 0x0000 70: 0x4009 0x0010 0x0002 0x0000 0x0000 71: 0x400B 0x0010 0x0002 0x0000 0x0000 72: 0x400D 0x0010 0x0002 0x0000 0x0000 73: 0x400F 0x0010 0x0002 0x0000 0x0000 74: 0x4011 0x0010 0x0002 0x0000 0x0000 75: 0x4013 0x0010 0x0002 0x0000 0x0000 76: 0x4015 0x0010 0x0002 0x0000 0x0000 77: 0x4017 0x0010 0x0002 0x0000 0x0000 78: 0x4019 0x0010 0x0002 0x0000 0x0000 79: 0x401B 0x0010 0x0002 0x0000 0x0000 80: 0x401D 0x0010 0x0002 0x0000 0x0000 81: 0x401F 0x0010 0x0002 0x0000 0x0000 82: 0x5001 0x0010 0x0002 0x0000 0x0000 83: 0x5003 0x0010 0x0002 0x0000 0x0000 84: 0x5005 0x0010 0x0002 0x0000 0x0000 85: 0x5007 0x0010 0x0002 0x0000 0x0000 86: 0x5009 0x0010 0x0002 0x0000 0x0000 87: 0x500B 0x0010 0x0002 0x0000 0x0000 88: 0x500D 0x0010 0x0002 0x0000 0x0000 89: 0x500F 0x0010 0x0002 0x0000 0x0000 90: 0x5011 0x0010 0x0002 0x0000 0x0000 91: 0x5013 0x0010 0x0002 0x0000 0x0000 92: 0x5015 0x0010 0x0002 0x0000 0x0000 93: 0x5017 0x0010 0x0002 0x0000 0x0000 94: 0x5019 0x0010 0x0002 0x0000 0x0000 95: 0x501B 0x0010 0x0002 0x0000 0x0000 96: 0x501D 0x0010 0x0002 0x0000 0x0000 97: 0x501F 0x0010 0x0002 0x0000 0x0000 98: 0x6001 0x0010 0x0002 0x0000 0x0000 99: 0x6003 0x0010 0x0002 0x0000 0x0000 100: 0x6005 0x0010 0x0002 0x0000 0x0000 101: 0x6007 0x0010 0x0002 0x0000 0x0000 102: 0x6009 0x0010 0x0002 0x0000 0x0000 103: 0x600B 0x0010 0x0002 0x0000 0x0000 104: 0x600D 0x0010 0x0002 0x0000 0x0000 105: 0x600F 0x0010 0x0002 0x0000 0x0000 106: 0x6011 0x0010 0x0002 0x0000 0x0000 107: 0x6013 0x0010 0x0002 0x0000 0x0000 108: 0x6015 0x0010 0x0002 0x0000 0x0000 109: 0x6017 0x0010 0x0002 0x0000 0x0000 110: 0x6019 0x0010 0x0002 0x0000 0x0000 111: 0x601B 0x0010 0x0002 0x0000 0x0000 112: 0x601D 0x0010 0x0002 0x0000 0x0000 113: 0x601F 0x0010 0x0002 0x0000 0x0000 114: 0x7001 0x0010 0x0002 0x0000 0x0000 115: 0x7003 0x0010 0x0002 0x0000 0x0000 116: 0x7005 0x0010 0x0002 0x0000 0x0000 117: 0x7007 0x0010 0x0002 0x0000 0x0000 118: 0x7009 0x0010 0x0002 0x0000 0x0000 119: 0x700B 0x0010 0x0002 0x0000 0x0000 120: 0x700D 0x0010 0x0002 0x0000 0x0000 121: 0x700F 0x0010 0x0002 0x0000 0x0000 122: 0x7011 0x0010 0x0002 0x0000 0x0000 123: 0x7013 0x0010 0x0002 0x0000 0x0000 124: 0x7015 0x0010 0x0002 0x0000 0x0000 125: 0x7017 0x0010 0x0002 0x0000 0x0000 126: 0x7019 0x0010 0x0002 0x0000 0x0000 127: 0x701B 0x0010 0x0002 0x0000 0x0000 128: 0x701D 0x0010 0x0002 0x0000 0x0000 129: 0x701F 0x0010 0x0002 0x0000 0x0000 130: 0x8001 0x0010 0x0002 0x0000 0x0000 131: 0x8003 0x0010 0x0002 0x0000 0x0000 132: 0x8005 0x0010 0x0002 0x0000 0x0000 133: 0x8007 0x0010 0x0002 0x0000 0x0000 134: 0x8009 0x0010 0x0002 0x0000 0x0000 135: 0x800B 0x0010 0x0002 0x0000 0x0000 136: 0x800D 0x0010 0x0002 0x0000 0x0000 137: 0x800F 0x0010 0x0002 0x0000 0x0000 138: 0x8011 0x0010 0x0002 0x0000 0x0000 139: 0x8013 0x0010 0x0002 0x0000 0x0000 140: 0x8015 0x0010 0x0002 0x0000 0x0000 141: 0x8017 0x0010 0x0002 0x0000 0x0000 142: 0x8019 0x0010 0x0002 0x0000 0x0000 143: 0x801B 0x0010 0x0002 0x0000 0x0000 144: 0x801D 0x0010 0x0002 0x0000 0x0000 145: 0x801F 0x0010 0x0002 0x0000 0x0000 146: 0x9001 0x0010 0x0002 0x0000 0x0000 147: 0x9003 0x0010 0x0002 0x0000 0x0000 148: 0x9005 0x0010 0x0002 0x0000 0x0000 149: 0x9007 0x0010 0x0002 0x0000 0x0000 150: 0x9009 0x0010 0x0002 0x0000 0x0000 151: 0x900B 0x0010 0x0002 0x0000 0x0000 152: 0x900D 0x0010 0x0002 0x0000 0x0000 153: 0x900F 0x0010 0x0002 0x0000 0x0000 154: 0x9011 0x0010 0x0002 0x0000 0x0000 155: 0x9013 0x0010 0x0002 0x0000 0x0000 156: 0x9015 0x0010 0x0002 0x0000 0x0000 157: 0x9017 0x0010 0x0002 0x0000 0x0000 158: 0x9019 0x0010 0x0002 0x0000 0x0000 159: 0x901B 0x0010 0x0002 0x0000 0x0000 160: 0x901D 0x0010 0x0002 0x0000 0x0000 161: 0x901F 0x0010 0x0002 0x0000 0x0000 162: 0xA001 0x0010 0x0002 0x0000 0x0000 163: 0xA003 0x0010 0x0002 0x0000 0x0000 164: 0xA005 0x0010 0x0002 0x0000 0x0000 165: 0xA007 0x0010 0x0002 0x0000 0x0000 166: 0xA009 0x0010 0x0002 0x0000 0x0000 167: 0xA00B 0x0010 0x0002 0x0000 0x0000 168: 0xA00D 0x0010 0x0002 0x0000 0x0000 169: 0xA00F 0x0010 0x0002 0x0000 0x0000 170: 0xA011 0x0010 0x0002 0x0000 0x0000 171: 0xA013 0x0010 0x0002 0x0000 0x0000 172: 0xA015 0x0010 0x0002 0x0000 0x0000 173: 0xA017 0x0010 0x0002 0x0000 0x0000 174: 0xA019 0x0010 0x0002 0x0000 0x0000 175: 0xA01B 0x0010 0x0002 0x0000 0x0000 176: 0xA01D 0x0010 0x0002 0x0000 0x0000 177: 0xA01F 0x0010 0x0002 0x0000 0x0000 178: 0xB001 0x0010 0x0002 0x0000 0x0000 179: 0xB003 0x0010 0x0002 0x0000 0x0000 180: 0xB005 0x0010 0x0002 0x0000 0x0000 181: 0xB007 0x0010 0x0002 0x0000 0x0000 182: 0xB009 0x0010 0x0002 0x0000 0x0000 183: 0xB00B 0x0010 0x0002 0x0000 0x0000 184: 0xB00D 0x0010 0x0002 0x0000 0x0000 185: 0xB00F 0x0010 0x0002 0x0000 0x0000 186: 0xB011 0x0010 0x0002 0x0000 0x0000 187: 0xB013 0x0010 0x0002 0x0000 0x0000 188: 0xB015 0x0010 0x0002 0x0000 0x0000 189: 0xB017 0x0010 0x0002 0x0000 0x0000 190: 0xB019 0x0010 0x0002 0x0000 0x0000 191: 0xB01B 0x0010 0x0002 0x0000 0x0000 192: 0xB01D 0x0010 0x0002 0x0000 0x0000 193: 0xB01F 0x0010 0x0002 0x0000 0x0000 194: 0xC001 0x0010 0x0002 0x0000 0x0000 195: 0xC003 0x0010 0x0002 0x0000 0x0000 196: 0xC005 0x0010 0x0002 0x0000 0x0000 197: 0xC007 0x0010 0x0002 0x0000 0x0000 198: 0xC009 0x0010 0x0002 0x0000 0x0000 199: 0xC00B 0x0010 0x0002 0x0000 0x0000 200: 0xC00D 0x0010 0x0002 0x0000 0x0000 201: 0xC00F 0x0010 0x0002 0x0000 0x0000 202: 0xC011 0x0010 0x0002 0x0000 0x0000 203: 0xC013 0x0010 0x0002 0x0000 0x0000 204: 0xC015 0x0010 0x0002 0x0000 0x0000 205: 0xC017 0x0010 0x0002 0x0000 0x0000 206: 0xC019 0x0010 0x0002 0x0000 0x0000 207: 0xC01B 0x0010 0x0002 0x0000 0x0000 208: 0xC01D 0x0010 0x0002 0x0000 0x0000 209: 0xC01F 0x0010 0x0002 0x0000 0x0000 210: 0xD001 0x0010 0x0002 0x0000 0x0000 211: 0xD003 0x0010 0x0002 0x0000 0x0000 212: 0xD005 0x0010 0x0002 0x0000 0x0000 213: 0xD007 0x0010 0x0002 0x0000 0x0000 214: 0xD009 0x0010 0x0002 0x0000 0x0000 215: 0xD00B 0x0010 0x0002 0x0000 0x0000 216: 0xD00D 0x0010 0x0002 0x0000 0x0000 217: 0xD00F 0x0010 0x0002 0x0000 0x0000 218: 0xD011 0x0010 0x0002 0x0000 0x0000 219: 0xD013 0x0010 0x0002 0x0000 0x0000 220: 0xD015 0x0010 0x0002 0x0000 0x0000 221: 0xD017 0x0010 0x0002 0x0000 0x0000 222: 0xD019 0x0010 0x0002 0x0000 0x0000 223: 0xD01B 0x0010 0x0002 0x0000 0x0000 224: 0xD01D 0x0010 0x0002 0x0000 0x0000 225: 0xD01F 0x0010 0x0002 0x0000 0x0000 226: 0xE001 0x0010 0x0002 0x0000 0x0000 227: 0xE003 0x0010 0x0002 0x0000 0x0000 228: 0xE005 0x0010 0x0002 0x0000 0x0000 229: 0xE007 0x0010 0x0002 0x0000 0x0000 230: 0xE009 0x0010 0x0002 0x0000 0x0000 231: 0xE00B 0x0010 0x0002 0x0000 0x0000 232: 0xE00D 0x0010 0x0002 0x0000 0x0000 233: 0xE00F 0x0010 0x0002 0x0000 0x0000 234: 0xE011 0x0010 0x0002 0x0000 0x0000 235: 0xE013 0x0010 0x0002 0x0000 0x0000 236: 0xE015 0x0010 0x0002 0x0000 0x0000 237: 0xE017 0x0010 0x0002 0x0000 0x0000 238: 0xE019 0x0010 0x0002 0x0000 0x0000 239: 0xE01B 0x0010 0x0002 0x0000 0x0000 240: 0xE01D 0x0010 0x0002 0x0000 0x0000 241: 0xE01F 0x0010 0x0002 0x0000 0x0000 242: 0xF001 0x0010 0x0002 0x0000 0x0000 243: 0xF003 0x0010 0x0002 0x0000 0x0000 244: 0xF005 0x0010 0x0002 0x0000 0x0000 245: 0xF007 0x0010 0x0002 0x0000 0x0000 246: 0xF009 0x0010 0x0002 0x0000 0x0000 247: 0xF00B 0x0010 0x0002 0x0000 0x0000 248: 0xF00D 0x0010 0x0002 0x0000 0x0000 249: 0xF00F 0x0010 0x0002 0x0000 0x0000 250: 0xF011 0x0010 0x0002 0x0000 0x0000 251: 0xF013 0x0010 0x0002 0x0000 0x0000 252: 0xF015 0x0010 0x0002 0x0000 0x0000 253: 0xF017 0x0010 0x0002 0x0000 0x0000 254: 0xF019 0x0010 0x0002 0x0000 0x0000 255: 0xF01B 0x0010 0x0002 0x0000 0x0000 256: 0xF01D 0x0010 0x0002 0x0000 0x0000 257: 0xF01E 0x0010 0x0002 0x0000 0x0000 258: 0x0001 0x0010 0x0002 0x0000 0x0000 259: 0x0001 0x0010 0x0002 0x0000 0x0000 260: 0x0001 0x0018 0x0002 0x0000 0x0000 261: 0x0001 0x0014 0x0002 0x0000 0x0000 262: 0x0001 0x001C 0x0002 0x0000 0x0000 263: 0x0001 0x0012 0x0002 0x0000 0x0000 264: 0x0001 0x001A 0x0002 0x0000 0x0000 265: 0x0001 0x0016 0x0002 0x0000 0x0000 266: 0x0001 0x001E 0x0002 0x0000 0x0000 267: 0x0001 0x0011 0x0002 0x0000 0x0000 268: 0x0001 0x0019 0x0002 0x0000 0x0000 269: 0x0001 0x0015 0x0002 0x0000 0x0000 270: 0x0001 0x001D 0x0002 0x0000 0x0000 271: 0x0001 0x0013 0x0002 0x0000 0x0000 272: 0x0001 0x001B 0x0002 0x0000 0x0000 273: 0x0001 0x0017 0x0002 0x0000 0x0000 274: 0x0001 0x001F 0x0002 0x0000 0x0000 275: 0x0001 0x8010 0x0002 0x0000 0x0000 276: 0x0001 0x8018 0x0002 0x0000 0x0000 277: 0x0001 0x8014 0x0002 0x0000 0x0000 278: 0x0001 0x801C 0x0002 0x0000 0x0000 279: 0x0001 0x8012 0x0002 0x0000 0x0000 280: 0x0001 0x801A 0x0002 0x0000 0x0000 281: 0x0001 0x8016 0x0002 0x0000 0x0000 282: 0x0001 0x801E 0x0002 0x0000 0x0000 283: 0x0001 0x8011 0x0002 0x0000 0x0000 284: 0x0001 0x8019 0x0002 0x0000 0x0000 285: 0x0001 0x8015 0x0002 0x0000 0x0000 286: 0x0001 0x801D 0x0002 0x0000 0x0000 287: 0x0001 0x8013 0x0002 0x0000 0x0000 288: 0x0001 0x801B 0x0002 0x0000 0x0000 289: 0x0001 0x8017 0x0002 0x0000 0x0000 290: 0x0001 0x801F 0x0002 0x0000 0x0000 291: 0x0101 0x0010 0x0002 0x0000 0x0000 292: 0x0101 0x0018 0x0002 0x0000 0x0000 293: 0x0101 0x0014 0x0002 0x0000 0x0000 294: 0x0101 0x001C 0x0002 0x0000 0x0000 295: 0x0101 0x0012 0x0002 0x0000 0x0000 296: 0x0101 0x001A 0x0002 0x0000 0x0000 297: 0x0101 0x0016 0x0002 0x0000 0x0000 298: 0x0101 0x001E 0x0002 0x0000 0x0000 299: 0x0101 0x0011 0x0002 0x0000 0x0000 300: 0x0101 0x0019 0x0002 0x0000 0x0000 301: 0x0101 0x0015 0x0002 0x0000 0x0000 302: 0x0101 0x001D 0x0002 0x0000 0x0000 303: 0x0101 0x0013 0x0002 0x0000 0x0000 304: 0x0101 0x001B 0x0002 0x0000 0x0000 305: 0x0101 0x0017 0x0002 0x0000 0x0000 306: 0x0101 0x001F 0x0002 0x0000 0x0000 307: 0x0101 0x8010 0x0002 0x0000 0x0000 308: 0x0101 0x8018 0x0002 0x0000 0x0000 309: 0x0101 0x8014 0x0002 0x0000 0x0000 310: 0x0101 0x801C 0x0002 0x0000 0x0000 311: 0x0101 0x8012 0x0002 0x0000 0x0000 312: 0x0101 0x801A 0x0002 0x0000 0x0000 313: 0x0101 0x8016 0x0002 0x0000 0x0000 314: 0x0101 0x801E 0x0002 0x0000 0x0000 315: 0x0101 0x8011 0x0002 0x0000 0x0000 316: 0x0101 0x8019 0x0002 0x0000 0x0000 317: 0x0101 0x8015 0x0002 0x0000 0x0000 318: 0x0101 0x801D 0x0002 0x0000 0x0000 319: 0x0101 0x8013 0x0002 0x0000 0x0000 320: 0x0101 0x801B 0x0002 0x0000 0x0000 321: 0x0101 0x8017 0x0002 0x0000 0x0000 322: 0x0101 0x801F 0x0002 0x0000 0x0000 323: 0x0201 0x0010 0x0002 0x0000 0x0000 324: 0x0201 0x0018 0x0002 0x0000 0x0000 325: 0x0201 0x0014 0x0002 0x0000 0x0000 326: 0x0201 0x001C 0x0002 0x0000 0x0000 327: 0x0201 0x0012 0x0002 0x0000 0x0000 328: 0x0201 0x001A 0x0002 0x0000 0x0000 329: 0x0201 0x0016 0x0002 0x0000 0x0000 330: 0x0201 0x001E 0x0002 0x0000 0x0000 331: 0x0201 0x0011 0x0002 0x0000 0x0000 332: 0x0201 0x0019 0x0002 0x0000 0x0000 333: 0x0201 0x0015 0x0002 0x0000 0x0000 334: 0x0201 0x001D 0x0002 0x0000 0x0000 335: 0x0201 0x0013 0x0002 0x0000 0x0000 336: 0x0201 0x001B 0x0002 0x0000 0x0000 337: 0x0201 0x0017 0x0002 0x0000 0x0000 338: 0x0201 0x001F 0x0002 0x0000 0x0000 339: 0x0201 0x8010 0x0002 0x0000 0x0000 340: 0x0201 0x8018 0x0002 0x0000 0x0000 341: 0x0201 0x8014 0x0002 0x0000 0x0000 342: 0x0201 0x801C 0x0002 0x0000 0x0000 343: 0x0201 0x8012 0x0002 0x0000 0x0000 344: 0x0201 0x801A 0x0002 0x0000 0x0000 345: 0x0201 0x8016 0x0002 0x0000 0x0000 346: 0x0201 0x801E 0x0002 0x0000 0x0000 347: 0x0201 0x8011 0x0002 0x0000 0x0000 348: 0x0201 0x8019 0x0002 0x0000 0x0000 349: 0x0201 0x8015 0x0002 0x0000 0x0000 350: 0x0201 0x801D 0x0002 0x0000 0x0000 351: 0x0201 0x8013 0x0002 0x0000 0x0000 352: 0x0201 0x801B 0x0002 0x0000 0x0000 353: 0x0201 0x8017 0x0002 0x0000 0x0000 354: 0x0201 0x801F 0x0002 0x0000 0x0000 355: 0x0301 0x0010 0x0002 0x0000 0x0000 356: 0x0301 0x0018 0x0002 0x0000 0x0000 357: 0x0301 0x0014 0x0002 0x0000 0x0000 358: 0x0301 0x001C 0x0002 0x0000 0x0000 359: 0x0301 0x0012 0x0002 0x0000 0x0000 360: 0x0301 0x001A 0x0002 0x0000 0x0000 361: 0x0301 0x0016 0x0002 0x0000 0x0000 362: 0x0301 0x001E 0x0002 0x0000 0x0000 363: 0x0301 0x0011 0x0002 0x0000 0x0000 364: 0x0301 0x0019 0x0002 0x0000 0x0000 365: 0x0301 0x0015 0x0002 0x0000 0x0000 366: 0x0301 0x001D 0x0002 0x0000 0x0000 367: 0x0301 0x0013 0x0002 0x0000 0x0000 368: 0x0301 0x001B 0x0002 0x0000 0x0000 369: 0x0301 0x0017 0x0002 0x0000 0x0000 370: 0x0301 0x001F 0x0002 0x0000 0x0000 371: 0x0301 0x8010 0x0002 0x0000 0x0000 372: 0x0301 0x8018 0x0002 0x0000 0x0000 373: 0x0301 0x8014 0x0002 0x0000 0x0000 374: 0x0301 0x801C 0x0002 0x0000 0x0000 375: 0x0301 0x8012 0x0002 0x0000 0x0000 376: 0x0301 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0xF71E 0xA42F 0x0002 0x0000 0x0000 1440: 0xF71E 0xA42F 0x0003 0x0000 0x0000 1441: 0xF71E 0xA4AF 0x0002 0x0000 0x0000 1442: 0xF71E 0xA4AF 0x0003 0x0000 0x0000 1443: 0xF71E 0xA46F 0x0002 0x0000 0x0000 1444: 0xF71E 0xA46F 0x0003 0x0000 0x0000 1445: 0xF71E 0xA4EF 0x0002 0x0000 0x0000 1446: 0xF71E 0xA4EF 0x0003 0x0000 0x0000 1447: 0xF71E 0xA80F 0x0002 0x0000 0x0000 1448: 0xF71E 0xA80F 0x0003 0x0000 0x0000 1449: 0xF71E 0xA88F 0x0002 0x0000 0x0000 1450: 0xF71E 0xA88F 0x0003 0x0000 0x0000 1451: 0xF71E 0xA84F 0x0002 0x0000 0x0000 1452: 0xF71E 0xA84F 0x0003 0x0000 0x0000 1453: 0xF71E 0xA8CF 0x0002 0x0000 0x0000 1454: 0xF71E 0xA8CF 0x0003 0x0000 0x0000 1455: 0xF71E 0xA82F 0x0002 0x0000 0x0000 1456: 0xF71E 0xA82F 0x0003 0x0000 0x0000 1457: 0xF71E 0xA8AF 0x0002 0x0000 0x0000 1458: 0xF71E 0xA8AF 0x0003 0x0000 0x0000 1459: 0xF71E 0xA86F 0x0002 0x0000 0x0000 1460: 0xF71E 0xA86F 0x0003 0x0000 0x0000 1461: 0xF71E 0xA8EF 0x0002 0x0000 0x0000 1462: 0xF71E 0xA8EF 0x0003 0x0000 0x0000 1463: 0xF71E 0xAC0F 0x0002 0x0000 0x0000 1464: 0xF71E 0xAC0F 0x0003 0x0000 0x0000 1465: 0xF71E 0xAC8F 0x0002 0x0000 0x0000 1466: 0xF71E 0xAC8F 0x0003 0x0000 0x0000 1467: 0xF71E 0xAC4F 0x0002 0x0000 0x0000 1468: 0xF71E 0xAC4F 0x0003 0x0000 0x0000 1469: 0xF71E 0xACCF 0x0002 0x0000 0x0000 1470: 0xF71E 0xACCF 0x0003 0x0000 0x0000 1471: 0xF71E 0xAC2F 0x0002 0x0000 0x0000 1472: 0xF71E 0xAC2F 0x0003 0x0000 0x0000 1473: 0xF71E 0xACAF 0x0002 0x0000 0x0000 1474: 0xF71E 0xACAF 0x0003 0x0000 0x0000 1475: 0xF71E 0xAC6F 0x0002 0x0000 0x0000 1476: 0xF71E 0xAC6F 0x0003 0x0000 0x0000 1477: 0xF71E 0xACEF 0x0002 0x0000 0x0000 1478: 0xF71E 0xACEF 0x0003 0x0000 0x0000 1479: 0xF71E 0xB00F 0x0002 0x0000 0x0000 1480: 0xF71E 0xB00F 0x0003 0x0000 0x0000 1481: 0xF71E 0xB08F 0x0002 0x0000 0x0000 1482: 0xF71E 0xB08F 0x0003 0x0000 0x0000 1483: 0xF71E 0xB04F 0x0002 0x0000 0x0000 1484: 0xF71E 0xB04F 0x0003 0x0000 0x0000 1485: 0xF71E 0xB0CF 0x0002 0x0000 0x0000 1486: 0xF71E 0xB0CF 0x0003 0x0000 0x0000 1487: 0xF71E 0xB02F 0x0002 0x0000 0x0000 1488: 0xF71E 0xB02F 0x0003 0x0000 0x0000 1489: 0xF71E 0xB0AF 0x0002 0x0000 0x0000 1490: 0xF71E 0xB0AF 0x0003 0x0000 0x0000 1491: 0xF71E 0xB06F 0x0002 0x0000 0x0000 1492: 0xF71E 0xB06F 0x0003 0x0000 0x0000 1493: 0xF71E 0xB0EF 0x0002 0x0000 0x0000 1494: 0xF71E 0xB0EF 0x0003 0x0000 0x0000 1495: 0xF71E 0xB40F 0x0002 0x0000 0x0000 1496: 0xF71E 0xB40F 0x0003 0x0000 0x0000 1497: 0xF71E 0xB48F 0x0002 0x0000 0x0000 1498: 0xF71E 0xB48F 0x0003 0x0000 0x0000 1499: 0xF71E 0xB44F 0x0002 0x0000 0x0000 1500: 0xF71E 0xB44F 0x0003 0x0000 0x0000 1501: 0xF71E 0xB4CF 0x0002 0x0000 0x0000 1502: 0xF71E 0xB4CF 0x0003 0x0000 0x0000 1503: 0xF71E 0xB42F 0x0002 0x0000 0x0000 1504: 0xF71E 0xB42F 0x0003 0x0000 0x0000 1505: 0xF71E 0xB4AF 0x0002 0x0000 0x0000 1506: 0xF71E 0xB4AF 0x0003 0x0000 0x0000 1507: 0xF71E 0xB46F 0x0002 0x0000 0x0000 1508: 0xF71E 0xB46F 0x0003 0x0000 0x0000 1509: 0xF71E 0xB4EF 0x0002 0x0000 0x0000 1510: 0xF71E 0xB4EF 0x0003 0x0000 0x0000 1511: 0xF71E 0xB80F 0x0002 0x0000 0x0000 1512: 0xF71E 0xB80F 0x0003 0x0000 0x0000 1513: 0xF71E 0xB88F 0x0002 0x0000 0x0000 1514: 0xF71E 0xB88F 0x0003 0x0000 0x0000 1515: 0xF71E 0xB84F 0x0002 0x0000 0x0000 1516: 0xF71E 0xB84F 0x0003 0x0000 0x0000 1517: 0xF71E 0xB8CF 0x0002 0x0000 0x0000 1518: 0xF71E 0xB8CF 0x0003 0x0000 0x0000 1519: 0xF71E 0xB82F 0x0002 0x0000 0x0000 1520: 0xF71E 0xB82F 0x0003 0x0000 0x0000 1521: 0xF71E 0xB8AF 0x0002 0x0000 0x0000 1522: 0xF71E 0xB8AF 0x0003 0x0000 0x0000 1523: 0xF71E 0xB86F 0x0002 0x0000 0x0000 1524: 0xF71E 0xB86F 0x0003 0x0000 0x0000 1525: 0xF71E 0xB8EF 0x0002 0x0000 0x0000 1526: 0xF71E 0xB8EF 0x0003 0x0000 0x0000 1527: 0xF71E 0xBC0F 0x0002 0x0000 0x0000 1528: 0xF71E 0xBC0F 0x0003 0x0000 0x0000 1529: 0xF71E 0xBC8F 0x0002 0x0000 0x0000 1530: 0xF71E 0xBC8F 0x0003 0x0000 0x0000 1531: 0xF71E 0xBC4F 0x0002 0x0000 0x0000 1532: 0xF71E 0xBC4F 0x0003 0x0000 0x0000 1533: 0xF71E 0xBCCF 0x0002 0x0000 0x0000 1534: 0xF71E 0xBCCF 0x0003 0x0000 0x0000 1535: 0xF71E 0xBC2F 0x0002 0x0000 0x0000 1536: 0xF71E 0xBC2F 0x0003 0x0000 0x0000 1537: 0xF71E 0xBCAF 0x0002 0x0000 0x0000 1538: 0xF71E 0xBCAF 0x0003 0x0000 0x0000 1539: 0xF71E 0xBC6F 0x0002 0x0000 0x0000 1540: 0xF71E 0xBC6F 0x0003 0x0000 0x0000 1541: 0xF71E 0xBCEF 0x0002 0x0000 0x0000 1542: 0xF71E 0xBCEF 0x0001 0x0000 0x0000 1543: 0xF71E 0xBCEF 0x0001 0x0000 0x0000 PINs used (in edge connector order) (G=ground,P=power) SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBB LETTER ABCDEFHJKLMNPRSTUVABCDEFHJKLMNPRSTUVABCDEFHJKLMNPRSTUVABCDEFHJKLMNPRSTUV SIDE 111111111111111111222222222222222222111111111111111111222222222222222222 USAGE IIII IIII IIII G P GIIIIOIIIIOIIIIO G P G UUT has 24 inputs UUT has 3 outputs contains 27 pins/columns 39 pins are not used contains 1543 'test steps' M119 REV B 3 8-input NAND PINS Main menu Sun Jul 12 17:14:21 2015 test file is: tests\m119.tst delay is: 0 trigger is: 1 1 read test file 2 set test delay 3 set test trigger 4 run test 5 output loading test 8 diags 9 exit ***************************** UUT power is OFF * ***************************** Main menu Sun Jul 12 17:14:25 2015 test file is: tests\m119.tst delay is: 0 trigger is: 1 1 read test file 2 set test delay 3 set test trigger 4 run test 5 output loading test 8 diags 9 exit UUT power is okay Sun Jul 12 17:14:29 2015 space single step O run once (one test, all steps) F run, stop on fail G go (run tests N run, stop on fail, no print S scope (run, no print) C toggle comment printout + increase speed (less delay) - decrease speed (more delay)(slower) Q quit test scope (run, no print) ppppppppppppppppppppFpppppppppppppppppppppppppppppppFFFFFFFF space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C toggle comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDDEFHJFHJKKLMNPMNPRRSTUV SIDE 111122222111122222111122222 DIRECTION IIIIIIIIOIIIIIIIIOIIIIIIIIO all fails O IIIIIIOIIIIIIIIO was lo 000000000000000000000000000 falling vvvvvvvvvvvvvvvvvvvvvvvvvvv rising ^^^^^^^^^^^^^^^^^^^^^^^^^^^ was hi 111111111111111111111111111 total fails 9, total passes 51 Main menu Sun Jul 12 17:15:53 2015 test file is: tests\m119.tst delay is: 0 trigger is: 1 1 read test file 2 set test delay 3 set test trigger 4 run test 5 output loading test 8 diags 9 exit exiting tester- PDP8 card tester via printer port version 0.85 June 4, 2015 mapping[] is verified Main menu Sun Jul 12 17:16:00 2015 test file is: delay is: 0 trigger is: 1 1 read test file 2 set test delay 3 set test trigger 4 run test 5 output loading test 8 diags 9 exit Enter test file name? trying to open test file: tests\m216.tst reading test file: tests\m216.tst comment: M216 6 FLIP FLOPS comment: pins: PINS pins: 1 I AA1 E1-1 CLEAR-N E1-5/6 E1-8/9 E2-5/6 pins: 2 I AB1 E1-3 CLOCK E1-5/6 pins: 3 I AC1 E1-2 DATA E1-5/6 pins: 4 I AD1 E1-4 SET-N E1-5/6 pins: 5 O AE1 E1-5 Q E1-5/6 pins: 6 O AF1 E1-5 Q-N E1-5/6 pins: 7 I AD2 E1-11 CLOCK E1-8/9 pins: 8 I AE2 E1-12 DATA E1-8/9 pins: 9 I AF2 E1-10 SET-N E1-8/9 pins: 10 O AH2 E1-9 Q E1-8/9 pins: 11 O AJ2 E1-8 Q-N E1-8/9 pins: 12 I AH1 E2-3 CLOCK E2-5/6 pins: 13 I AJ1 E2-2 DATA E2-5/6 pins: 14 I AK1 E2-4 SET-N E2-5/6 pins: 15 O AL1 E2-5 Q E2-5/6 pins: 16 O AM1 E2-6 Q-N E2-5/6 pins: 17 I AK2 E3-13 CLEAR-N E3-8/9 E3-5/6 E2-8/9 pins: 18 I AL2 E3-11 CLOCK E3-8/9 pins: 19 I AM2 E3-12 DATA E3-8/9 pins: 20 I AN2 E3-10 SET-N E3-8/9 pins: 21 O AP2 E3-9 Q E3-8/9 pins: 22 O AR2 E3-8 Q-N E3-8/9 pins: 23 I AN1 E3-3 CLOCK E3-5/6 pins: 24 I AP1 E3-2 DATA E3-5/6 pins: 25 I AR1 E3-4 SET-N E3-5/6 pins: 26 O AS1 E3-5 Q E3-5/6 pins: 27 O AU1 E3-6 Q-N E3-5/6 pins: 28 I AS2 E2-11 CLOCK E2-8/9 pins: 29 I AT2 E2-12 DATA E2-8/9 pins: 30 I AU2 E2-10 SET-N E2-8/9 pins: 31 O AV2 E2-9 Q E2-8/9 pins: 32 O AV1 E2-8 Q-N E2-8/9 pins: direction: IIIIOOIIIOOIIIOOIIIIOOIIIOOIIIOO test 1: 00001100011000110000110001100011 test 2: 100010 10 10 test 3: 100110 test 4: 110101 test 5: 111101 test 6: 101101 test 7: 111110 test 8: 110110 test 9: 100110 test 10: 000101 11 11 test 11: 100101 10 10 test 12: 100010 test 13: 00001100011000110000110001100011 test 14: 1 1000010 10 test 15: 1 00110 test 16: 1 10101 test 17: 1 11101 test 18: 1 01101 test 19: 1 11110 test 20: 1 10110 test 21: 1 00110 test 22: 0 1100101 11 test 23: 1 1000101 10 test 24: 1 00010 test 25: 00001100011000110000110001100011 test 26: 1 10 1000010 test 27: 1 00110 test 28: 1 10101 test 29: 1 11101 test 30: 1 01101 test 31: 1 11110 test 32: 1 10110 test 33: 1 00110 test 34: 0 11 1100101 test 35: 1 10 1000101 test 36: 1 00010 test 37: 00001100011000110000110001100011 test 38: 100010 10 10 test 39: 100110 test 40: 110101 test 41: 111101 test 42: 101101 test 43: 111110 test 44: 110110 test 45: 100110 test 46: 000101 11 11 test 47: 100101 10 10 test 48: 100010 test 49: 00001100011000110000110001100011 test 50: 1 1000010 10 test 51: 1 00110 test 52: 1 10101 test 53: 1 11101 test 54: 1 01101 test 55: 1 11110 test 56: 1 10110 test 57: 1 00110 test 58: 0 1100101 11 test 59: 1 1000101 10 test 60: 1 00010 test 61: 00001100011000110000110001100011 test 62: 1 10 1000010 test 63: 1 00110 test 64: 1 10101 test 65: 1 11101 test 66: 1 01101 test 67: 1 11110 test 68: 1 10110 test 69: 1 00110 test 70: 0 11 1100101 test 71: 1 10 1000101 test 72: 1 00010 test 73: 00001100011000110000110001100011 end: END summary column 1: offset 0, mask 0x8000 column 2: offset 0, mask 0x4000 column 3: offset 0, mask 0x2000 column 4: offset 0, mask 0x1000 column 5: offset 0, mask 0x0800 column 6: offset 0, mask 0x0400 column 7: offset 0, mask 0x0010 column 8: offset 0, mask 0x0008 column 9: offset 0, mask 0x0004 column 10: offset 0, mask 0x0002 column 11: offset 0, mask 0x0001 column 12: offset 0, mask 0x0200 column 13: offset 0, mask 0x0100 column 14: offset 1, mask 0x8000 column 15: offset 1, mask 0x4000 column 16: offset 1, mask 0x2000 column 17: offset 1, mask 0x0001 column 18: offset 1, mask 0x0002 column 19: offset 1, mask 0x0004 column 20: offset 1, mask 0x0008 column 21: offset 1, mask 0x0010 column 22: offset 1, mask 0x0020 column 23: offset 1, mask 0x1000 column 24: offset 1, mask 0x0800 column 25: offset 1, mask 0x0400 column 26: offset 1, mask 0x0200 column 27: offset 2, mask 0x8000 column 28: offset 1, mask 0x0040 column 29: offset 1, mask 0x0080 column 30: offset 2, mask 0x0001 column 31: offset 2, mask 0x0002 column 32: offset 2, mask 0x4000 direction bits (1=input) 0x0CE3 0x6330 0xFFFA 0xFFFF 0xF0FF pullup bits (1=pullup) 0x0000 0x0000 0x0000 0x0000 0x0000 test step out_data dont care 1: 0x0C03 0x6230 0xC002 0x0000 0x0000 2: 0x8802 0x4230 0xC002 0x0000 0x0000 3: 0x9802 0x4230 0xC002 0x0000 0x0000 4: 0xD402 0x4230 0xC002 0x0000 0x0000 5: 0xF402 0x4230 0xC002 0x0000 0x0000 6: 0xB402 0x4230 0xC002 0x0000 0x0000 7: 0xF802 0x4230 0xC002 0x0000 0x0000 8: 0xD802 0x4230 0xC002 0x0000 0x0000 9: 0x9802 0x4230 0xC002 0x0000 0x0000 10: 0x1403 0x6230 0xC002 0x0000 0x0000 11: 0x9402 0x4230 0xC002 0x0000 0x0000 12: 0x8802 0x4230 0xC002 0x0000 0x0000 13: 0x0C03 0x6230 0xC002 0x0000 0x0000 14: 0x8802 0x4230 0xC002 0x0000 0x0000 15: 0x8806 0x4230 0xC002 0x0000 0x0000 16: 0x8815 0x4230 0xC002 0x0000 0x0000 17: 0x881D 0x4230 0xC002 0x0000 0x0000 18: 0x880D 0x4230 0xC002 0x0000 0x0000 19: 0x881E 0x4230 0xC002 0x0000 0x0000 20: 0x8816 0x4230 0xC002 0x0000 0x0000 21: 0x8806 0x4230 0xC002 0x0000 0x0000 22: 0x0C05 0x6230 0xC002 0x0000 0x0000 23: 0x8805 0x4230 0xC002 0x0000 0x0000 24: 0x8802 0x4230 0xC002 0x0000 0x0000 25: 0x0C03 0x6230 0xC002 0x0000 0x0000 26: 0x8802 0x4230 0xC002 0x0000 0x0000 27: 0x8802 0xC230 0xC002 0x0000 0x0000 28: 0x8A02 0xA230 0xC002 0x0000 0x0000 29: 0x8B02 0xA230 0xC002 0x0000 0x0000 30: 0x8902 0xA230 0xC002 0x0000 0x0000 31: 0x8B02 0xC230 0xC002 0x0000 0x0000 32: 0x8A02 0xC230 0xC002 0x0000 0x0000 33: 0x8802 0xC230 0xC002 0x0000 0x0000 34: 0x0C03 0xA230 0xC002 0x0000 0x0000 35: 0x8802 0xA230 0xC002 0x0000 0x0000 36: 0x8802 0x4230 0xC002 0x0000 0x0000 37: 0x0C03 0x6230 0xC002 0x0000 0x0000 38: 0x0C03 0x6211 0x0002 0x0000 0x0000 39: 0x0C03 0x6219 0x0002 0x0000 0x0000 40: 0x0C03 0x622B 0x0002 0x0000 0x0000 41: 0x0C03 0x622F 0x0002 0x0000 0x0000 42: 0x0C03 0x622D 0x0002 0x0000 0x0000 43: 0x0C03 0x621F 0x0002 0x0000 0x0000 44: 0x0C03 0x621B 0x0002 0x0000 0x0000 45: 0x0C03 0x6219 0x0002 0x0000 0x0000 46: 0x0C03 0x6228 0xC002 0x0000 0x0000 47: 0x0C03 0x6229 0x0002 0x0000 0x0000 48: 0x0C03 0x6211 0x0002 0x0000 0x0000 49: 0x0C03 0x6230 0xC002 0x0000 0x0000 50: 0x0C03 0x6211 0x0002 0x0000 0x0000 51: 0x0C03 0x6611 0x0002 0x0000 0x0000 52: 0x0C03 0x7411 0x8002 0x0000 0x0000 53: 0x0C03 0x7C11 0x8002 0x0000 0x0000 54: 0x0C03 0x6C11 0x8002 0x0000 0x0000 55: 0x0C03 0x7E11 0x0002 0x0000 0x0000 56: 0x0C03 0x7611 0x0002 0x0000 0x0000 57: 0x0C03 0x6611 0x0002 0x0000 0x0000 58: 0x0C03 0x6430 0xC002 0x0000 0x0000 59: 0x0C03 0x6411 0x8002 0x0000 0x0000 60: 0x0C03 0x6211 0x0002 0x0000 0x0000 61: 0x0C03 0x6230 0xC002 0x0000 0x0000 62: 0x0C03 0x6211 0x0002 0x0000 0x0000 63: 0x0C03 0x6211 0x0003 0x0000 0x0000 64: 0x0C03 0x6251 0x4001 0x0000 0x0000 65: 0x0C03 0x62D1 0x4001 0x0000 0x0000 66: 0x0C03 0x6291 0x4001 0x0000 0x0000 67: 0x0C03 0x62D1 0x0003 0x0000 0x0000 68: 0x0C03 0x6251 0x0003 0x0000 0x0000 69: 0x0C03 0x6211 0x0003 0x0000 0x0000 70: 0x0C03 0x6230 0xC001 0x0000 0x0000 71: 0x0C03 0x6211 0x4001 0x0000 0x0000 72: 0x0C03 0x6211 0x0002 0x0000 0x0000 73: 0x0C03 0x6230 0xC002 0x0000 0x0000 PINs used (in edge connector order) (G=ground,P=power) SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBB LETTER ABCDEFHJKLMNPRSTUVABCDEFHJKLMNPRSTUVABCDEFHJKLMNPRSTUVABCDEFHJKLMNPRSTUV SIDE 111111111111111111222222222222222222111111111111111111222222222222222222 USAGE IIIIOOIIIOOIIIOGOOP GIIIOOIIIIOOIIIO G P G UUT has 20 inputs UUT has 12 outputs contains 32 pins/columns 34 pins are not used contains 73 'test steps' M216 6 FLIP FLOPS PINS Main menu Sun Jul 12 17:16:04 2015 test file is: tests\m216.tst delay is: 0 trigger is: 1 1 read test file 2 set test delay 3 set test trigger 4 run test 5 output loading test 8 diags 9 exit UUT power is okay Sun Jul 12 17:16:06 2015 space single step O run once (one test, all steps) F run, stop on fail G go (run tests N run, stop on fail, no print S scope (run, no print) C toggle comment printout + increase speed (less delay) - decrease speed (more delay)(slower) Q quit test scope (run, no print) ppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppp ppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppp ppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppp ppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppp ppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppp ppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppp ppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppp ppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppp ppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppp ppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppp ppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppp ppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppp ppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppp ppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppFFFFFFFFFFFFFFF FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF FFFFFFFFFFFFFFFFFFF space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C toggle comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFDEFHJHJKLMKLMNPRNPRSUSTUVV SIDE 11111122222111112222221111122221 DIRECTION IIIIOOIIIOOIIIOOIIIIOOIIIOOIIIOO all fails IIIIOO OOIIIOO OOIIIOO OO was lo 00000000000000000000000000000000 falling vvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvv rising ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ was hi 11111111111111111111111111111111 total fails 3352, total passes 1091 Main menu Sun Jul 12 17:19:03 2015 test file is: tests\m216.tst delay is: 0 trigger is: 1 1 read test file 2 set test delay 3 set test trigger 4 run test 5 output loading test 8 diags 9 exit exiting tester- PDP8 card tester via printer port version 0.85 June 4, 2015 mapping[] is verified Main menu Sat Jul 18 09:59:31 2015 test file is: delay is: 0 trigger is: 1 1 read test file 2 set test delay 3 set test trigger 4 run test 5 output loading test 8 diags 9 exit Enter test file name? trying to open test file: tests\m119.tst reading test file: tests\m119.tst comment: M119 REV B 3 8-input NAND comment: pins: PINS pins: 1 I AA1 E1-12 pins: 2 I AB1 E1-11 pins: 3 I AC1 E1-5 pins: 4 I AD1 E1-6 pins: 5 I AD2 E1-4 pins: 6 I AE2 E1-3 pins: 7 I AF2 E1-2 pins: 8 I AH2 E1-1 pins: 9 O AJ2 E1-8 pins: 10 I AF1 E2-12 pins: 11 I AH1 E2-11 pins: 12 I AJ1 E2-5 pins: 13 I AK1 E2-6 pins: 14 I AK2 E2-4 pins: 15 I AL2 E2-3 pins: 16 I AM2 E2-2 pins: 17 I AN2 E2-1 pins: 18 O AP2 E2-8 pins: 19 I AM1 E3-12 pins: 20 I AN1 E3-11 pins: 21 I AP1 E3-5 pins: 22 I AR1 E3-6 pins: 23 I AR2 E3-4 pins: 24 I AS2 E3-3 pins: 25 I AT2 E3-2 pins: 26 I AU2 E3-1 pins: 27 O AV2 E3-8 pins: direction: IIIIIIIIOIIIIIIIIOIIIIIIIIO test 1: 000000001000000001000000001 test 2: 000000001 test 3: 000000011 test 4: 000000101 test 5: 000000111 test 6: 000001001 test 7: 000001011 test 8: 000001101 test 9: 000001111 test 10: 000010001 test 11: 000010011 test 12: 000010101 test 13: 000010111 test 14: 000011001 test 15: 000011011 test 16: 000011101 test 17: 000011111 test 18: 000100001 test 19: 000100011 test 20: 000100101 test 21: 000100111 test 22: 000101001 test 23: 000101011 test 24: 000101101 test 25: 000101111 test 26: 000110001 test 27: 000110011 test 28: 000110101 test 29: 000110111 test 30: 000111001 test 31: 000111011 test 32: 000111101 test 33: 000111111 test 34: 001000001 test 35: 001000011 test 36: 001000101 test 37: 001000111 test 38: 001001001 test 39: 001001011 test 40: 001001101 test 41: 001001111 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test 1088: 001110011 test 1089: 001110101 test 1090: 001110111 test 1091: 001111001 test 1092: 001111011 test 1093: 001111101 test 1094: 001111111 test 1095: 010000001 test 1096: 010000011 test 1097: 010000101 test 1098: 010000111 test 1099: 010001001 test 1100: 010001011 test 1101: 010001101 test 1102: 010001111 test 1103: 010010001 test 1104: 010010011 test 1105: 010010101 test 1106: 010010111 test 1107: 010011001 test 1108: 010011011 test 1109: 010011101 test 1110: 010011111 test 1111: 010100001 test 1112: 010100011 test 1113: 010100101 test 1114: 010100111 test 1115: 010101001 test 1116: 010101011 test 1117: 010101101 test 1118: 010101111 test 1119: 010110001 test 1120: 010110011 test 1121: 010110101 test 1122: 010110111 test 1123: 010111001 test 1124: 010111011 test 1125: 010111101 test 1126: 010111111 test 1127: 011000001 test 1128: 011000011 test 1129: 011000101 test 1130: 011000111 test 1131: 011001001 test 1132: 011001011 test 1133: 011001101 test 1134: 011001111 test 1135: 011010001 test 1136: 011010011 test 1137: 011010101 test 1138: 011010111 test 1139: 011011001 test 1140: 011011011 test 1141: 011011101 test 1142: 011011111 test 1143: 011100001 test 1144: 011100011 test 1145: 011100101 test 1146: 011100111 test 1147: 011101001 test 1148: 011101011 test 1149: 011101101 test 1150: 011101111 test 1151: 011110001 test 1152: 011110011 test 1153: 011110101 test 1154: 011110111 test 1155: 011111001 test 1156: 011111011 test 1157: 011111101 test 1158: 011111111 test 1159: 100000001 test 1160: 100000011 test 1161: 100000101 test 1162: 100000111 test 1163: 100001001 test 1164: 100001011 test 1165: 100001101 test 1166: 100001111 test 1167: 100010001 test 1168: 100010011 test 1169: 100010101 test 1170: 100010111 test 1171: 100011001 test 1172: 100011011 test 1173: 100011101 test 1174: 100011111 test 1175: 100100001 test 1176: 100100011 test 1177: 100100101 test 1178: 100100111 test 1179: 100101001 test 1180: 100101011 test 1181: 100101101 test 1182: 100101111 test 1183: 100110001 test 1184: 100110011 test 1185: 100110101 test 1186: 100110111 test 1187: 100111001 test 1188: 100111011 test 1189: 100111101 test 1190: 100111111 test 1191: 101000001 test 1192: 101000011 test 1193: 101000101 test 1194: 101000111 test 1195: 101001001 test 1196: 101001011 test 1197: 101001101 test 1198: 101001111 test 1199: 101010001 test 1200: 101010011 test 1201: 101010101 test 1202: 101010111 test 1203: 101011001 test 1204: 101011011 test 1205: 101011101 test 1206: 101011111 test 1207: 101100001 test 1208: 101100011 test 1209: 101100101 test 1210: 101100111 test 1211: 101101001 test 1212: 101101011 test 1213: 101101101 test 1214: 101101111 test 1215: 101110001 test 1216: 101110011 test 1217: 101110101 test 1218: 101110111 test 1219: 101111001 test 1220: 101111011 test 1221: 101111101 test 1222: 101111111 test 1223: 110000001 test 1224: 110000011 test 1225: 110000101 test 1226: 110000111 test 1227: 110001001 test 1228: 110001011 test 1229: 110001101 test 1230: 110001111 test 1231: 110010001 test 1232: 110010011 test 1233: 110010101 test 1234: 110010111 test 1235: 110011001 test 1236: 110011011 test 1237: 110011101 test 1238: 110011111 test 1239: 110100001 test 1240: 110100011 test 1241: 110100101 test 1242: 110100111 test 1243: 110101001 test 1244: 110101011 test 1245: 110101101 test 1246: 110101111 test 1247: 110110001 test 1248: 110110011 test 1249: 110110101 test 1250: 110110111 test 1251: 110111001 test 1252: 110111011 test 1253: 110111101 test 1254: 110111111 test 1255: 111000001 test 1256: 111000011 test 1257: 111000101 test 1258: 111000111 test 1259: 111001001 test 1260: 111001011 test 1261: 111001101 test 1262: 111001111 test 1263: 111010001 test 1264: 111010011 test 1265: 111010101 test 1266: 111010111 test 1267: 111011001 test 1268: 111011011 test 1269: 111011101 test 1270: 111011111 test 1271: 111100001 test 1272: 111100011 test 1273: 111100101 test 1274: 111100111 test 1275: 111101001 test 1276: 111101011 test 1277: 111101101 test 1278: 111101111 test 1279: 111110001 test 1280: 111110011 test 1281: 111110101 test 1282: 111110111 test 1283: 111111001 test 1284: 111111011 test 1285: 111111101 test 1286: 111111110 test 1287: 000000001 test 1288: 000000011 test 1289: 000000101 test 1290: 000000111 test 1291: 000001001 test 1292: 000001011 test 1293: 000001101 test 1294: 000001111 test 1295: 000010001 test 1296: 000010011 test 1297: 000010101 test 1298: 000010111 test 1299: 000011001 test 1300: 000011011 test 1301: 000011101 test 1302: 000011111 test 1303: 000100001 test 1304: 000100011 test 1305: 000100101 test 1306: 000100111 test 1307: 000101001 test 1308: 000101011 test 1309: 000101101 test 1310: 000101111 test 1311: 000110001 test 1312: 000110011 test 1313: 000110101 test 1314: 000110111 test 1315: 000111001 test 1316: 000111011 test 1317: 000111101 test 1318: 000111111 test 1319: 001000001 test 1320: 001000011 test 1321: 001000101 test 1322: 001000111 test 1323: 001001001 test 1324: 001001011 test 1325: 001001101 test 1326: 001001111 test 1327: 001010001 test 1328: 001010011 test 1329: 001010101 test 1330: 001010111 test 1331: 001011001 test 1332: 001011011 test 1333: 001011101 test 1334: 001011111 test 1335: 001100001 test 1336: 001100011 test 1337: 001100101 test 1338: 001100111 test 1339: 001101001 test 1340: 001101011 test 1341: 001101101 test 1342: 001101111 test 1343: 001110001 test 1344: 001110011 test 1345: 001110101 test 1346: 001110111 test 1347: 001111001 test 1348: 001111011 test 1349: 001111101 test 1350: 001111111 test 1351: 010000001 test 1352: 010000011 test 1353: 010000101 test 1354: 010000111 test 1355: 010001001 test 1356: 010001011 test 1357: 010001101 test 1358: 010001111 test 1359: 010010001 test 1360: 010010011 test 1361: 010010101 test 1362: 010010111 test 1363: 010011001 test 1364: 010011011 test 1365: 010011101 test 1366: 010011111 test 1367: 010100001 test 1368: 010100011 test 1369: 010100101 test 1370: 010100111 test 1371: 010101001 test 1372: 010101011 test 1373: 010101101 test 1374: 010101111 test 1375: 010110001 test 1376: 010110011 test 1377: 010110101 test 1378: 010110111 test 1379: 010111001 test 1380: 010111011 test 1381: 010111101 test 1382: 010111111 test 1383: 011000001 test 1384: 011000011 test 1385: 011000101 test 1386: 011000111 test 1387: 011001001 test 1388: 011001011 test 1389: 011001101 test 1390: 011001111 test 1391: 011010001 test 1392: 011010011 test 1393: 011010101 test 1394: 011010111 test 1395: 011011001 test 1396: 011011011 test 1397: 011011101 test 1398: 011011111 test 1399: 011100001 test 1400: 011100011 test 1401: 011100101 test 1402: 011100111 test 1403: 011101001 test 1404: 011101011 test 1405: 011101101 test 1406: 011101111 test 1407: 011110001 test 1408: 011110011 test 1409: 011110101 test 1410: 011110111 test 1411: 011111001 test 1412: 011111011 test 1413: 011111101 test 1414: 011111111 test 1415: 100000001 test 1416: 100000011 test 1417: 100000101 test 1418: 100000111 test 1419: 100001001 test 1420: 100001011 test 1421: 100001101 test 1422: 100001111 test 1423: 100010001 test 1424: 100010011 test 1425: 100010101 test 1426: 100010111 test 1427: 100011001 test 1428: 100011011 test 1429: 100011101 test 1430: 100011111 test 1431: 100100001 test 1432: 100100011 test 1433: 100100101 test 1434: 100100111 test 1435: 100101001 test 1436: 100101011 test 1437: 100101101 test 1438: 100101111 test 1439: 100110001 test 1440: 100110011 test 1441: 100110101 test 1442: 100110111 test 1443: 100111001 test 1444: 100111011 test 1445: 100111101 test 1446: 100111111 test 1447: 101000001 test 1448: 101000011 test 1449: 101000101 test 1450: 101000111 test 1451: 101001001 test 1452: 101001011 test 1453: 101001101 test 1454: 101001111 test 1455: 101010001 test 1456: 101010011 test 1457: 101010101 test 1458: 101010111 test 1459: 101011001 test 1460: 101011011 test 1461: 101011101 test 1462: 101011111 test 1463: 101100001 test 1464: 101100011 test 1465: 101100101 test 1466: 101100111 test 1467: 101101001 test 1468: 101101011 test 1469: 101101101 test 1470: 101101111 test 1471: 101110001 test 1472: 101110011 test 1473: 101110101 test 1474: 101110111 test 1475: 101111001 test 1476: 101111011 test 1477: 101111101 test 1478: 101111111 test 1479: 110000001 test 1480: 110000011 test 1481: 110000101 test 1482: 110000111 test 1483: 110001001 test 1484: 110001011 test 1485: 110001101 test 1486: 110001111 test 1487: 110010001 test 1488: 110010011 test 1489: 110010101 test 1490: 110010111 test 1491: 110011001 test 1492: 110011011 test 1493: 110011101 test 1494: 110011111 test 1495: 110100001 test 1496: 110100011 test 1497: 110100101 test 1498: 110100111 test 1499: 110101001 test 1500: 110101011 test 1501: 110101101 test 1502: 110101111 test 1503: 110110001 test 1504: 110110011 test 1505: 110110101 test 1506: 110110111 test 1507: 110111001 test 1508: 110111011 test 1509: 110111101 test 1510: 110111111 test 1511: 111000001 test 1512: 111000011 test 1513: 111000101 test 1514: 111000111 test 1515: 111001001 test 1516: 111001011 test 1517: 111001101 test 1518: 111001111 test 1519: 111010001 test 1520: 111010011 test 1521: 111010101 test 1522: 111010111 test 1523: 111011001 test 1524: 111011011 test 1525: 111011101 test 1526: 111011111 test 1527: 111100001 test 1528: 111100011 test 1529: 111100101 test 1530: 111100111 test 1531: 111101001 test 1532: 111101011 test 1533: 111101101 test 1534: 111101111 test 1535: 111110001 test 1536: 111110011 test 1537: 111110101 test 1538: 111110111 test 1539: 111111001 test 1540: 111111011 test 1541: 111111101 test 1542: 111111110 test 1543: 111111110111111110111111110 end: END summary column 1: offset 0, mask 0x8000 column 2: offset 0, mask 0x4000 column 3: offset 0, mask 0x2000 column 4: offset 0, mask 0x1000 column 5: offset 0, mask 0x0010 column 6: offset 0, mask 0x0008 column 7: offset 0, mask 0x0004 column 8: offset 0, mask 0x0002 column 9: offset 0, mask 0x0001 column 10: offset 0, mask 0x0400 column 11: offset 0, mask 0x0200 column 12: offset 0, mask 0x0100 column 13: offset 1, mask 0x8000 column 14: offset 1, mask 0x0001 column 15: offset 1, mask 0x0002 column 16: offset 1, mask 0x0004 column 17: offset 1, mask 0x0008 column 18: offset 1, mask 0x0010 column 19: offset 1, mask 0x2000 column 20: offset 1, mask 0x1000 column 21: offset 1, mask 0x0800 column 22: offset 1, mask 0x0400 column 23: offset 1, mask 0x0020 column 24: offset 1, mask 0x0040 column 25: offset 1, mask 0x0080 column 26: offset 2, mask 0x0001 column 27: offset 2, mask 0x0002 direction bits (1=input) 0x08E1 0x4310 0xFFFA 0xFFFF 0xF0FF pullup bits (1=pullup) 0x0000 0x0000 0x0000 0x0000 0x0000 test step out_data dont care 1: 0x0001 0x0010 0x0002 0x0000 0x0000 2: 0x0001 0x0010 0x0002 0x0000 0x0000 3: 0x0003 0x0010 0x0002 0x0000 0x0000 4: 0x0005 0x0010 0x0002 0x0000 0x0000 5: 0x0007 0x0010 0x0002 0x0000 0x0000 6: 0x0009 0x0010 0x0002 0x0000 0x0000 7: 0x000B 0x0010 0x0002 0x0000 0x0000 8: 0x000D 0x0010 0x0002 0x0000 0x0000 9: 0x000F 0x0010 0x0002 0x0000 0x0000 10: 0x0011 0x0010 0x0002 0x0000 0x0000 11: 0x0013 0x0010 0x0002 0x0000 0x0000 12: 0x0015 0x0010 0x0002 0x0000 0x0000 13: 0x0017 0x0010 0x0002 0x0000 0x0000 14: 0x0019 0x0010 0x0002 0x0000 0x0000 15: 0x001B 0x0010 0x0002 0x0000 0x0000 16: 0x001D 0x0010 0x0002 0x0000 0x0000 17: 0x001F 0x0010 0x0002 0x0000 0x0000 18: 0x1001 0x0010 0x0002 0x0000 0x0000 19: 0x1003 0x0010 0x0002 0x0000 0x0000 20: 0x1005 0x0010 0x0002 0x0000 0x0000 21: 0x1007 0x0010 0x0002 0x0000 0x0000 22: 0x1009 0x0010 0x0002 0x0000 0x0000 23: 0x100B 0x0010 0x0002 0x0000 0x0000 24: 0x100D 0x0010 0x0002 0x0000 0x0000 25: 0x100F 0x0010 0x0002 0x0000 0x0000 26: 0x1011 0x0010 0x0002 0x0000 0x0000 27: 0x1013 0x0010 0x0002 0x0000 0x0000 28: 0x1015 0x0010 0x0002 0x0000 0x0000 29: 0x1017 0x0010 0x0002 0x0000 0x0000 30: 0x1019 0x0010 0x0002 0x0000 0x0000 31: 0x101B 0x0010 0x0002 0x0000 0x0000 32: 0x101D 0x0010 0x0002 0x0000 0x0000 33: 0x101F 0x0010 0x0002 0x0000 0x0000 34: 0x2001 0x0010 0x0002 0x0000 0x0000 35: 0x2003 0x0010 0x0002 0x0000 0x0000 36: 0x2005 0x0010 0x0002 0x0000 0x0000 37: 0x2007 0x0010 0x0002 0x0000 0x0000 38: 0x2009 0x0010 0x0002 0x0000 0x0000 39: 0x200B 0x0010 0x0002 0x0000 0x0000 40: 0x200D 0x0010 0x0002 0x0000 0x0000 41: 0x200F 0x0010 0x0002 0x0000 0x0000 42: 0x2011 0x0010 0x0002 0x0000 0x0000 43: 0x2013 0x0010 0x0002 0x0000 0x0000 44: 0x2015 0x0010 0x0002 0x0000 0x0000 45: 0x2017 0x0010 0x0002 0x0000 0x0000 46: 0x2019 0x0010 0x0002 0x0000 0x0000 47: 0x201B 0x0010 0x0002 0x0000 0x0000 48: 0x201D 0x0010 0x0002 0x0000 0x0000 49: 0x201F 0x0010 0x0002 0x0000 0x0000 50: 0x3001 0x0010 0x0002 0x0000 0x0000 51: 0x3003 0x0010 0x0002 0x0000 0x0000 52: 0x3005 0x0010 0x0002 0x0000 0x0000 53: 0x3007 0x0010 0x0002 0x0000 0x0000 54: 0x3009 0x0010 0x0002 0x0000 0x0000 55: 0x300B 0x0010 0x0002 0x0000 0x0000 56: 0x300D 0x0010 0x0002 0x0000 0x0000 57: 0x300F 0x0010 0x0002 0x0000 0x0000 58: 0x3011 0x0010 0x0002 0x0000 0x0000 59: 0x3013 0x0010 0x0002 0x0000 0x0000 60: 0x3015 0x0010 0x0002 0x0000 0x0000 61: 0x3017 0x0010 0x0002 0x0000 0x0000 62: 0x3019 0x0010 0x0002 0x0000 0x0000 63: 0x301B 0x0010 0x0002 0x0000 0x0000 64: 0x301D 0x0010 0x0002 0x0000 0x0000 65: 0x301F 0x0010 0x0002 0x0000 0x0000 66: 0x4001 0x0010 0x0002 0x0000 0x0000 67: 0x4003 0x0010 0x0002 0x0000 0x0000 68: 0x4005 0x0010 0x0002 0x0000 0x0000 69: 0x4007 0x0010 0x0002 0x0000 0x0000 70: 0x4009 0x0010 0x0002 0x0000 0x0000 71: 0x400B 0x0010 0x0002 0x0000 0x0000 72: 0x400D 0x0010 0x0002 0x0000 0x0000 73: 0x400F 0x0010 0x0002 0x0000 0x0000 74: 0x4011 0x0010 0x0002 0x0000 0x0000 75: 0x4013 0x0010 0x0002 0x0000 0x0000 76: 0x4015 0x0010 0x0002 0x0000 0x0000 77: 0x4017 0x0010 0x0002 0x0000 0x0000 78: 0x4019 0x0010 0x0002 0x0000 0x0000 79: 0x401B 0x0010 0x0002 0x0000 0x0000 80: 0x401D 0x0010 0x0002 0x0000 0x0000 81: 0x401F 0x0010 0x0002 0x0000 0x0000 82: 0x5001 0x0010 0x0002 0x0000 0x0000 83: 0x5003 0x0010 0x0002 0x0000 0x0000 84: 0x5005 0x0010 0x0002 0x0000 0x0000 85: 0x5007 0x0010 0x0002 0x0000 0x0000 86: 0x5009 0x0010 0x0002 0x0000 0x0000 87: 0x500B 0x0010 0x0002 0x0000 0x0000 88: 0x500D 0x0010 0x0002 0x0000 0x0000 89: 0x500F 0x0010 0x0002 0x0000 0x0000 90: 0x5011 0x0010 0x0002 0x0000 0x0000 91: 0x5013 0x0010 0x0002 0x0000 0x0000 92: 0x5015 0x0010 0x0002 0x0000 0x0000 93: 0x5017 0x0010 0x0002 0x0000 0x0000 94: 0x5019 0x0010 0x0002 0x0000 0x0000 95: 0x501B 0x0010 0x0002 0x0000 0x0000 96: 0x501D 0x0010 0x0002 0x0000 0x0000 97: 0x501F 0x0010 0x0002 0x0000 0x0000 98: 0x6001 0x0010 0x0002 0x0000 0x0000 99: 0x6003 0x0010 0x0002 0x0000 0x0000 100: 0x6005 0x0010 0x0002 0x0000 0x0000 101: 0x6007 0x0010 0x0002 0x0000 0x0000 102: 0x6009 0x0010 0x0002 0x0000 0x0000 103: 0x600B 0x0010 0x0002 0x0000 0x0000 104: 0x600D 0x0010 0x0002 0x0000 0x0000 105: 0x600F 0x0010 0x0002 0x0000 0x0000 106: 0x6011 0x0010 0x0002 0x0000 0x0000 107: 0x6013 0x0010 0x0002 0x0000 0x0000 108: 0x6015 0x0010 0x0002 0x0000 0x0000 109: 0x6017 0x0010 0x0002 0x0000 0x0000 110: 0x6019 0x0010 0x0002 0x0000 0x0000 111: 0x601B 0x0010 0x0002 0x0000 0x0000 112: 0x601D 0x0010 0x0002 0x0000 0x0000 113: 0x601F 0x0010 0x0002 0x0000 0x0000 114: 0x7001 0x0010 0x0002 0x0000 0x0000 115: 0x7003 0x0010 0x0002 0x0000 0x0000 116: 0x7005 0x0010 0x0002 0x0000 0x0000 117: 0x7007 0x0010 0x0002 0x0000 0x0000 118: 0x7009 0x0010 0x0002 0x0000 0x0000 119: 0x700B 0x0010 0x0002 0x0000 0x0000 120: 0x700D 0x0010 0x0002 0x0000 0x0000 121: 0x700F 0x0010 0x0002 0x0000 0x0000 122: 0x7011 0x0010 0x0002 0x0000 0x0000 123: 0x7013 0x0010 0x0002 0x0000 0x0000 124: 0x7015 0x0010 0x0002 0x0000 0x0000 125: 0x7017 0x0010 0x0002 0x0000 0x0000 126: 0x7019 0x0010 0x0002 0x0000 0x0000 127: 0x701B 0x0010 0x0002 0x0000 0x0000 128: 0x701D 0x0010 0x0002 0x0000 0x0000 129: 0x701F 0x0010 0x0002 0x0000 0x0000 130: 0x8001 0x0010 0x0002 0x0000 0x0000 131: 0x8003 0x0010 0x0002 0x0000 0x0000 132: 0x8005 0x0010 0x0002 0x0000 0x0000 133: 0x8007 0x0010 0x0002 0x0000 0x0000 134: 0x8009 0x0010 0x0002 0x0000 0x0000 135: 0x800B 0x0010 0x0002 0x0000 0x0000 136: 0x800D 0x0010 0x0002 0x0000 0x0000 137: 0x800F 0x0010 0x0002 0x0000 0x0000 138: 0x8011 0x0010 0x0002 0x0000 0x0000 139: 0x8013 0x0010 0x0002 0x0000 0x0000 140: 0x8015 0x0010 0x0002 0x0000 0x0000 141: 0x8017 0x0010 0x0002 0x0000 0x0000 142: 0x8019 0x0010 0x0002 0x0000 0x0000 143: 0x801B 0x0010 0x0002 0x0000 0x0000 144: 0x801D 0x0010 0x0002 0x0000 0x0000 145: 0x801F 0x0010 0x0002 0x0000 0x0000 146: 0x9001 0x0010 0x0002 0x0000 0x0000 147: 0x9003 0x0010 0x0002 0x0000 0x0000 148: 0x9005 0x0010 0x0002 0x0000 0x0000 149: 0x9007 0x0010 0x0002 0x0000 0x0000 150: 0x9009 0x0010 0x0002 0x0000 0x0000 151: 0x900B 0x0010 0x0002 0x0000 0x0000 152: 0x900D 0x0010 0x0002 0x0000 0x0000 153: 0x900F 0x0010 0x0002 0x0000 0x0000 154: 0x9011 0x0010 0x0002 0x0000 0x0000 155: 0x9013 0x0010 0x0002 0x0000 0x0000 156: 0x9015 0x0010 0x0002 0x0000 0x0000 157: 0x9017 0x0010 0x0002 0x0000 0x0000 158: 0x9019 0x0010 0x0002 0x0000 0x0000 159: 0x901B 0x0010 0x0002 0x0000 0x0000 160: 0x901D 0x0010 0x0002 0x0000 0x0000 161: 0x901F 0x0010 0x0002 0x0000 0x0000 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0xBCF1 0x0001 0x0000 0x0000 1280: 0xF71E 0xBCF9 0x0001 0x0000 0x0000 1281: 0xF71E 0xBCF5 0x0001 0x0000 0x0000 1282: 0xF71E 0xBCFD 0x0001 0x0000 0x0000 1283: 0xF71E 0xBCF3 0x0001 0x0000 0x0000 1284: 0xF71E 0xBCFB 0x0001 0x0000 0x0000 1285: 0xF71E 0xBCF7 0x0001 0x0000 0x0000 1286: 0xF71E 0xBCEF 0x0001 0x0000 0x0000 1287: 0xF71E 0x800F 0x0002 0x0000 0x0000 1288: 0xF71E 0x800F 0x0003 0x0000 0x0000 1289: 0xF71E 0x808F 0x0002 0x0000 0x0000 1290: 0xF71E 0x808F 0x0003 0x0000 0x0000 1291: 0xF71E 0x804F 0x0002 0x0000 0x0000 1292: 0xF71E 0x804F 0x0003 0x0000 0x0000 1293: 0xF71E 0x80CF 0x0002 0x0000 0x0000 1294: 0xF71E 0x80CF 0x0003 0x0000 0x0000 1295: 0xF71E 0x802F 0x0002 0x0000 0x0000 1296: 0xF71E 0x802F 0x0003 0x0000 0x0000 1297: 0xF71E 0x80AF 0x0002 0x0000 0x0000 1298: 0xF71E 0x80AF 0x0003 0x0000 0x0000 1299: 0xF71E 0x806F 0x0002 0x0000 0x0000 1300: 0xF71E 0x806F 0x0003 0x0000 0x0000 1301: 0xF71E 0x80EF 0x0002 0x0000 0x0000 1302: 0xF71E 0x80EF 0x0003 0x0000 0x0000 1303: 0xF71E 0x840F 0x0002 0x0000 0x0000 1304: 0xF71E 0x840F 0x0003 0x0000 0x0000 1305: 0xF71E 0x848F 0x0002 0x0000 0x0000 1306: 0xF71E 0x848F 0x0003 0x0000 0x0000 1307: 0xF71E 0x844F 0x0002 0x0000 0x0000 1308: 0xF71E 0x844F 0x0003 0x0000 0x0000 1309: 0xF71E 0x84CF 0x0002 0x0000 0x0000 1310: 0xF71E 0x84CF 0x0003 0x0000 0x0000 1311: 0xF71E 0x842F 0x0002 0x0000 0x0000 1312: 0xF71E 0x842F 0x0003 0x0000 0x0000 1313: 0xF71E 0x84AF 0x0002 0x0000 0x0000 1314: 0xF71E 0x84AF 0x0003 0x0000 0x0000 1315: 0xF71E 0x846F 0x0002 0x0000 0x0000 1316: 0xF71E 0x846F 0x0003 0x0000 0x0000 1317: 0xF71E 0x84EF 0x0002 0x0000 0x0000 1318: 0xF71E 0x84EF 0x0003 0x0000 0x0000 1319: 0xF71E 0x880F 0x0002 0x0000 0x0000 1320: 0xF71E 0x880F 0x0003 0x0000 0x0000 1321: 0xF71E 0x888F 0x0002 0x0000 0x0000 1322: 0xF71E 0x888F 0x0003 0x0000 0x0000 1323: 0xF71E 0x884F 0x0002 0x0000 0x0000 1324: 0xF71E 0x884F 0x0003 0x0000 0x0000 1325: 0xF71E 0x88CF 0x0002 0x0000 0x0000 1326: 0xF71E 0x88CF 0x0003 0x0000 0x0000 1327: 0xF71E 0x882F 0x0002 0x0000 0x0000 1328: 0xF71E 0x882F 0x0003 0x0000 0x0000 1329: 0xF71E 0x88AF 0x0002 0x0000 0x0000 1330: 0xF71E 0x88AF 0x0003 0x0000 0x0000 1331: 0xF71E 0x886F 0x0002 0x0000 0x0000 1332: 0xF71E 0x886F 0x0003 0x0000 0x0000 1333: 0xF71E 0x88EF 0x0002 0x0000 0x0000 1334: 0xF71E 0x88EF 0x0003 0x0000 0x0000 1335: 0xF71E 0x8C0F 0x0002 0x0000 0x0000 1336: 0xF71E 0x8C0F 0x0003 0x0000 0x0000 1337: 0xF71E 0x8C8F 0x0002 0x0000 0x0000 1338: 0xF71E 0x8C8F 0x0003 0x0000 0x0000 1339: 0xF71E 0x8C4F 0x0002 0x0000 0x0000 1340: 0xF71E 0x8C4F 0x0003 0x0000 0x0000 1341: 0xF71E 0x8CCF 0x0002 0x0000 0x0000 1342: 0xF71E 0x8CCF 0x0003 0x0000 0x0000 1343: 0xF71E 0x8C2F 0x0002 0x0000 0x0000 1344: 0xF71E 0x8C2F 0x0003 0x0000 0x0000 1345: 0xF71E 0x8CAF 0x0002 0x0000 0x0000 1346: 0xF71E 0x8CAF 0x0003 0x0000 0x0000 1347: 0xF71E 0x8C6F 0x0002 0x0000 0x0000 1348: 0xF71E 0x8C6F 0x0003 0x0000 0x0000 1349: 0xF71E 0x8CEF 0x0002 0x0000 0x0000 1350: 0xF71E 0x8CEF 0x0003 0x0000 0x0000 1351: 0xF71E 0x900F 0x0002 0x0000 0x0000 1352: 0xF71E 0x900F 0x0003 0x0000 0x0000 1353: 0xF71E 0x908F 0x0002 0x0000 0x0000 1354: 0xF71E 0x908F 0x0003 0x0000 0x0000 1355: 0xF71E 0x904F 0x0002 0x0000 0x0000 1356: 0xF71E 0x904F 0x0003 0x0000 0x0000 1357: 0xF71E 0x90CF 0x0002 0x0000 0x0000 1358: 0xF71E 0x90CF 0x0003 0x0000 0x0000 1359: 0xF71E 0x902F 0x0002 0x0000 0x0000 1360: 0xF71E 0x902F 0x0003 0x0000 0x0000 1361: 0xF71E 0x90AF 0x0002 0x0000 0x0000 1362: 0xF71E 0x90AF 0x0003 0x0000 0x0000 1363: 0xF71E 0x906F 0x0002 0x0000 0x0000 1364: 0xF71E 0x906F 0x0003 0x0000 0x0000 1365: 0xF71E 0x90EF 0x0002 0x0000 0x0000 1366: 0xF71E 0x90EF 0x0003 0x0000 0x0000 1367: 0xF71E 0x940F 0x0002 0x0000 0x0000 1368: 0xF71E 0x940F 0x0003 0x0000 0x0000 1369: 0xF71E 0x948F 0x0002 0x0000 0x0000 1370: 0xF71E 0x948F 0x0003 0x0000 0x0000 1371: 0xF71E 0x944F 0x0002 0x0000 0x0000 1372: 0xF71E 0x944F 0x0003 0x0000 0x0000 1373: 0xF71E 0x94CF 0x0002 0x0000 0x0000 1374: 0xF71E 0x94CF 0x0003 0x0000 0x0000 1375: 0xF71E 0x942F 0x0002 0x0000 0x0000 1376: 0xF71E 0x942F 0x0003 0x0000 0x0000 1377: 0xF71E 0x94AF 0x0002 0x0000 0x0000 1378: 0xF71E 0x94AF 0x0003 0x0000 0x0000 1379: 0xF71E 0x946F 0x0002 0x0000 0x0000 1380: 0xF71E 0x946F 0x0003 0x0000 0x0000 1381: 0xF71E 0x94EF 0x0002 0x0000 0x0000 1382: 0xF71E 0x94EF 0x0003 0x0000 0x0000 1383: 0xF71E 0x980F 0x0002 0x0000 0x0000 1384: 0xF71E 0x980F 0x0003 0x0000 0x0000 1385: 0xF71E 0x988F 0x0002 0x0000 0x0000 1386: 0xF71E 0x988F 0x0003 0x0000 0x0000 1387: 0xF71E 0x984F 0x0002 0x0000 0x0000 1388: 0xF71E 0x984F 0x0003 0x0000 0x0000 1389: 0xF71E 0x98CF 0x0002 0x0000 0x0000 1390: 0xF71E 0x98CF 0x0003 0x0000 0x0000 1391: 0xF71E 0x982F 0x0002 0x0000 0x0000 1392: 0xF71E 0x982F 0x0003 0x0000 0x0000 1393: 0xF71E 0x98AF 0x0002 0x0000 0x0000 1394: 0xF71E 0x98AF 0x0003 0x0000 0x0000 1395: 0xF71E 0x986F 0x0002 0x0000 0x0000 1396: 0xF71E 0x986F 0x0003 0x0000 0x0000 1397: 0xF71E 0x98EF 0x0002 0x0000 0x0000 1398: 0xF71E 0x98EF 0x0003 0x0000 0x0000 1399: 0xF71E 0x9C0F 0x0002 0x0000 0x0000 1400: 0xF71E 0x9C0F 0x0003 0x0000 0x0000 1401: 0xF71E 0x9C8F 0x0002 0x0000 0x0000 1402: 0xF71E 0x9C8F 0x0003 0x0000 0x0000 1403: 0xF71E 0x9C4F 0x0002 0x0000 0x0000 1404: 0xF71E 0x9C4F 0x0003 0x0000 0x0000 1405: 0xF71E 0x9CCF 0x0002 0x0000 0x0000 1406: 0xF71E 0x9CCF 0x0003 0x0000 0x0000 1407: 0xF71E 0x9C2F 0x0002 0x0000 0x0000 1408: 0xF71E 0x9C2F 0x0003 0x0000 0x0000 1409: 0xF71E 0x9CAF 0x0002 0x0000 0x0000 1410: 0xF71E 0x9CAF 0x0003 0x0000 0x0000 1411: 0xF71E 0x9C6F 0x0002 0x0000 0x0000 1412: 0xF71E 0x9C6F 0x0003 0x0000 0x0000 1413: 0xF71E 0x9CEF 0x0002 0x0000 0x0000 1414: 0xF71E 0x9CEF 0x0003 0x0000 0x0000 1415: 0xF71E 0xA00F 0x0002 0x0000 0x0000 1416: 0xF71E 0xA00F 0x0003 0x0000 0x0000 1417: 0xF71E 0xA08F 0x0002 0x0000 0x0000 1418: 0xF71E 0xA08F 0x0003 0x0000 0x0000 1419: 0xF71E 0xA04F 0x0002 0x0000 0x0000 1420: 0xF71E 0xA04F 0x0003 0x0000 0x0000 1421: 0xF71E 0xA0CF 0x0002 0x0000 0x0000 1422: 0xF71E 0xA0CF 0x0003 0x0000 0x0000 1423: 0xF71E 0xA02F 0x0002 0x0000 0x0000 1424: 0xF71E 0xA02F 0x0003 0x0000 0x0000 1425: 0xF71E 0xA0AF 0x0002 0x0000 0x0000 1426: 0xF71E 0xA0AF 0x0003 0x0000 0x0000 1427: 0xF71E 0xA06F 0x0002 0x0000 0x0000 1428: 0xF71E 0xA06F 0x0003 0x0000 0x0000 1429: 0xF71E 0xA0EF 0x0002 0x0000 0x0000 1430: 0xF71E 0xA0EF 0x0003 0x0000 0x0000 1431: 0xF71E 0xA40F 0x0002 0x0000 0x0000 1432: 0xF71E 0xA40F 0x0003 0x0000 0x0000 1433: 0xF71E 0xA48F 0x0002 0x0000 0x0000 1434: 0xF71E 0xA48F 0x0003 0x0000 0x0000 1435: 0xF71E 0xA44F 0x0002 0x0000 0x0000 1436: 0xF71E 0xA44F 0x0003 0x0000 0x0000 1437: 0xF71E 0xA4CF 0x0002 0x0000 0x0000 1438: 0xF71E 0xA4CF 0x0003 0x0000 0x0000 1439: 0xF71E 0xA42F 0x0002 0x0000 0x0000 1440: 0xF71E 0xA42F 0x0003 0x0000 0x0000 1441: 0xF71E 0xA4AF 0x0002 0x0000 0x0000 1442: 0xF71E 0xA4AF 0x0003 0x0000 0x0000 1443: 0xF71E 0xA46F 0x0002 0x0000 0x0000 1444: 0xF71E 0xA46F 0x0003 0x0000 0x0000 1445: 0xF71E 0xA4EF 0x0002 0x0000 0x0000 1446: 0xF71E 0xA4EF 0x0003 0x0000 0x0000 1447: 0xF71E 0xA80F 0x0002 0x0000 0x0000 1448: 0xF71E 0xA80F 0x0003 0x0000 0x0000 1449: 0xF71E 0xA88F 0x0002 0x0000 0x0000 1450: 0xF71E 0xA88F 0x0003 0x0000 0x0000 1451: 0xF71E 0xA84F 0x0002 0x0000 0x0000 1452: 0xF71E 0xA84F 0x0003 0x0000 0x0000 1453: 0xF71E 0xA8CF 0x0002 0x0000 0x0000 1454: 0xF71E 0xA8CF 0x0003 0x0000 0x0000 1455: 0xF71E 0xA82F 0x0002 0x0000 0x0000 1456: 0xF71E 0xA82F 0x0003 0x0000 0x0000 1457: 0xF71E 0xA8AF 0x0002 0x0000 0x0000 1458: 0xF71E 0xA8AF 0x0003 0x0000 0x0000 1459: 0xF71E 0xA86F 0x0002 0x0000 0x0000 1460: 0xF71E 0xA86F 0x0003 0x0000 0x0000 1461: 0xF71E 0xA8EF 0x0002 0x0000 0x0000 1462: 0xF71E 0xA8EF 0x0003 0x0000 0x0000 1463: 0xF71E 0xAC0F 0x0002 0x0000 0x0000 1464: 0xF71E 0xAC0F 0x0003 0x0000 0x0000 1465: 0xF71E 0xAC8F 0x0002 0x0000 0x0000 1466: 0xF71E 0xAC8F 0x0003 0x0000 0x0000 1467: 0xF71E 0xAC4F 0x0002 0x0000 0x0000 1468: 0xF71E 0xAC4F 0x0003 0x0000 0x0000 1469: 0xF71E 0xACCF 0x0002 0x0000 0x0000 1470: 0xF71E 0xACCF 0x0003 0x0000 0x0000 1471: 0xF71E 0xAC2F 0x0002 0x0000 0x0000 1472: 0xF71E 0xAC2F 0x0003 0x0000 0x0000 1473: 0xF71E 0xACAF 0x0002 0x0000 0x0000 1474: 0xF71E 0xACAF 0x0003 0x0000 0x0000 1475: 0xF71E 0xAC6F 0x0002 0x0000 0x0000 1476: 0xF71E 0xAC6F 0x0003 0x0000 0x0000 1477: 0xF71E 0xACEF 0x0002 0x0000 0x0000 1478: 0xF71E 0xACEF 0x0003 0x0000 0x0000 1479: 0xF71E 0xB00F 0x0002 0x0000 0x0000 1480: 0xF71E 0xB00F 0x0003 0x0000 0x0000 1481: 0xF71E 0xB08F 0x0002 0x0000 0x0000 1482: 0xF71E 0xB08F 0x0003 0x0000 0x0000 1483: 0xF71E 0xB04F 0x0002 0x0000 0x0000 1484: 0xF71E 0xB04F 0x0003 0x0000 0x0000 1485: 0xF71E 0xB0CF 0x0002 0x0000 0x0000 1486: 0xF71E 0xB0CF 0x0003 0x0000 0x0000 1487: 0xF71E 0xB02F 0x0002 0x0000 0x0000 1488: 0xF71E 0xB02F 0x0003 0x0000 0x0000 1489: 0xF71E 0xB0AF 0x0002 0x0000 0x0000 1490: 0xF71E 0xB0AF 0x0003 0x0000 0x0000 1491: 0xF71E 0xB06F 0x0002 0x0000 0x0000 1492: 0xF71E 0xB06F 0x0003 0x0000 0x0000 1493: 0xF71E 0xB0EF 0x0002 0x0000 0x0000 1494: 0xF71E 0xB0EF 0x0003 0x0000 0x0000 1495: 0xF71E 0xB40F 0x0002 0x0000 0x0000 1496: 0xF71E 0xB40F 0x0003 0x0000 0x0000 1497: 0xF71E 0xB48F 0x0002 0x0000 0x0000 1498: 0xF71E 0xB48F 0x0003 0x0000 0x0000 1499: 0xF71E 0xB44F 0x0002 0x0000 0x0000 1500: 0xF71E 0xB44F 0x0003 0x0000 0x0000 1501: 0xF71E 0xB4CF 0x0002 0x0000 0x0000 1502: 0xF71E 0xB4CF 0x0003 0x0000 0x0000 1503: 0xF71E 0xB42F 0x0002 0x0000 0x0000 1504: 0xF71E 0xB42F 0x0003 0x0000 0x0000 1505: 0xF71E 0xB4AF 0x0002 0x0000 0x0000 1506: 0xF71E 0xB4AF 0x0003 0x0000 0x0000 1507: 0xF71E 0xB46F 0x0002 0x0000 0x0000 1508: 0xF71E 0xB46F 0x0003 0x0000 0x0000 1509: 0xF71E 0xB4EF 0x0002 0x0000 0x0000 1510: 0xF71E 0xB4EF 0x0003 0x0000 0x0000 1511: 0xF71E 0xB80F 0x0002 0x0000 0x0000 1512: 0xF71E 0xB80F 0x0003 0x0000 0x0000 1513: 0xF71E 0xB88F 0x0002 0x0000 0x0000 1514: 0xF71E 0xB88F 0x0003 0x0000 0x0000 1515: 0xF71E 0xB84F 0x0002 0x0000 0x0000 1516: 0xF71E 0xB84F 0x0003 0x0000 0x0000 1517: 0xF71E 0xB8CF 0x0002 0x0000 0x0000 1518: 0xF71E 0xB8CF 0x0003 0x0000 0x0000 1519: 0xF71E 0xB82F 0x0002 0x0000 0x0000 1520: 0xF71E 0xB82F 0x0003 0x0000 0x0000 1521: 0xF71E 0xB8AF 0x0002 0x0000 0x0000 1522: 0xF71E 0xB8AF 0x0003 0x0000 0x0000 1523: 0xF71E 0xB86F 0x0002 0x0000 0x0000 1524: 0xF71E 0xB86F 0x0003 0x0000 0x0000 1525: 0xF71E 0xB8EF 0x0002 0x0000 0x0000 1526: 0xF71E 0xB8EF 0x0003 0x0000 0x0000 1527: 0xF71E 0xBC0F 0x0002 0x0000 0x0000 1528: 0xF71E 0xBC0F 0x0003 0x0000 0x0000 1529: 0xF71E 0xBC8F 0x0002 0x0000 0x0000 1530: 0xF71E 0xBC8F 0x0003 0x0000 0x0000 1531: 0xF71E 0xBC4F 0x0002 0x0000 0x0000 1532: 0xF71E 0xBC4F 0x0003 0x0000 0x0000 1533: 0xF71E 0xBCCF 0x0002 0x0000 0x0000 1534: 0xF71E 0xBCCF 0x0003 0x0000 0x0000 1535: 0xF71E 0xBC2F 0x0002 0x0000 0x0000 1536: 0xF71E 0xBC2F 0x0003 0x0000 0x0000 1537: 0xF71E 0xBCAF 0x0002 0x0000 0x0000 1538: 0xF71E 0xBCAF 0x0003 0x0000 0x0000 1539: 0xF71E 0xBC6F 0x0002 0x0000 0x0000 1540: 0xF71E 0xBC6F 0x0003 0x0000 0x0000 1541: 0xF71E 0xBCEF 0x0002 0x0000 0x0000 1542: 0xF71E 0xBCEF 0x0001 0x0000 0x0000 1543: 0xF71E 0xBCEF 0x0001 0x0000 0x0000 PINs used (in edge connector order) (G=ground,P=power) SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBB LETTER ABCDEFHJKLMNPRSTUVABCDEFHJKLMNPRSTUVABCDEFHJKLMNPRSTUVABCDEFHJKLMNPRSTUV SIDE 111111111111111111222222222222222222111111111111111111222222222222222222 USAGE IIII IIII IIII G P GIIIIOIIIIOIIIIO G P G UUT has 24 inputs UUT has 3 outputs contains 27 pins/columns 39 pins are not used contains 1543 'test steps' M119 REV B 3 8-input NAND PINS Main menu Sat Jul 18 09:59:41 2015 test file is: tests\m119.tst delay is: 0 trigger is: 1 1 read test file 2 set test delay 3 set test trigger 4 run test 5 output loading test 8 diags 9 exit UUT power is okay Sat Jul 18 09:59:43 2015 space single step O run once (one test, all steps) F run, stop on fail G go (run tests N run, stop on fail, no print S scope (run, no print) C toggle comment printout + increase speed (less delay) - decrease speed (more delay)(slower) Q quit test scope (run, no print) ppppppppppppppFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C toggle comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDDEFHJFHJKKLMNPMNPRRSTUV SIDE 111122222111122222111122222 DIRECTION IIIIIIIIOIIIIIIIIOIIIIIIIIO all fails I O O IIIIIIO was lo 000000000000000000000000000 falling vvvvvvvvvvvvvvvvvvvvvvvvvvv rising ^^^^^^^^^^^^^^^^^^^^^^^^^^^ was hi 111111111111111111111111111 total fails 127, total passes 14 Main menu Sat Jul 18 10:01:39 2015 test file is: tests\m119.tst delay is: 0 trigger is: 1 1 read test file 2 set test delay 3 set test trigger 4 run test 5 output loading test 8 diags 9 exit key is 0x006D Main menu Sat Jul 18 10:01:41 2015 test file is: tests\m119.tst delay is: 0 trigger is: 1 1 read test file 2 set test delay 3 set test trigger 4 run test 5 output loading test 8 diags 9 exit Enter test file name? trying to open test file: tests\m111.tst reading test file: tests\m111.tst comment: M111 PCB REV C SCHEMATIC REV A 16 INVERTERS USING 7400s pins: PINS pins: 1 I AV1 E4-9 pins: 2 O AU1 E4-8 pins: 3 I AR1 E4-12 pins: 4 O AS1 E4-11 pins: 5 I AN1 E3-10 pins: 6 O AP1 E3-8 pins: 7 I AL1 E3-12 pins: 8 O AM1 E3-11 pins: 9 I AJ1 E1-9 pins: 10 O AK1 E1-8 pins: 11 I AF1 E1-12 pins: 12 O AH1 E1-11 pins: 13 I AD1 E2-9 pins: 14 O AE1 E2-8 pins: 15 I AC1 E2-5 pins: 16 O AD2 E2-6 pins: 17 I AA1 E2-12 pins: 18 O AB1 E2-11 pins: 19 I AU2 E4-1 pins: 20 O AV2 E4-2 pins: 21 I AS2 E4-5 pins: 22 O AT2 E4-6 pins: 23 I AP2 E3-1 pins: 24 O AR2 E3-2 pins: 25 I AM2 E3-5 pins: 26 O AN2 E3-6 pins: 27 I AK2 E1-1 pins: 28 O AL2 E1-3 pins: 29 I AH2 E1-5 pins: 30 O AJ2 E1-6 pins: 31 I AE2 E2-1 pins: 32 O AF2 E2-3 pins: direction: IOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIO test 1: 01010101010101010101010101010101 test 2: 01 test 3: 10 test 4: 01 test 5: 01 test 6: 10 test 7: 01 test 8: 01 test 9: 10 test 10: 01 test 11: 01 test 12: 10 test 13: 01 test 14: 01 test 15: 10 test 16: 01 test 17: 01 test 18: 10 test 19: 01 test 20: 01 test 21: 10 test 22: 01 test 23: 01 test 24: 10 test 25: 01 test 26: 01 test 27: 10 test 28: 01 test 29: 01 test 30: 10 test 31: 01 test 32: 01 test 33: 10 test 34: 01 test 35: 01 test 36: 10 test 37: 01 test 38: 01 test 39: 10 test 40: 01 test 41: 01 test 42: 10 test 43: 01 test 44: 01 test 45: 10 test 46: 01 test 47: 01 test 48: 10 test 49: 01 test 50: 01010101010101010101010101010101 test 51: 10101010101010101010101010101010 test 52: 01 test 53: 10 test 54: 01 test 55: 10 test 56: 01 test 57: 10 test 58: 01 test 59: 10 test 60: 01 test 61: 10 test 62: 01 test 63: 10 test 64: 01 test 65: 10 test 66: 01 test 67: 10 test 68: 01 test 69: 10 test 70: 01 test 71: 10 test 72: 01 test 73: 10 test 74: 01 test 75: 10 test 76: 01 test 77: 10 test 78: 01 test 79: 10 test 80: 01 test 81: 10 test 82: 01 test 83: 10 test 84: 10101010101010101010101010101010 end: END summary column 1: offset 2, mask 0x4000 column 2: offset 2, mask 0x8000 column 3: offset 1, mask 0x0400 column 4: offset 1, mask 0x0200 column 5: offset 1, mask 0x1000 column 6: offset 1, mask 0x0800 column 7: offset 1, mask 0x4000 column 8: offset 1, mask 0x2000 column 9: offset 0, mask 0x0100 column 10: offset 1, mask 0x8000 column 11: offset 0, mask 0x0400 column 12: offset 0, mask 0x0200 column 13: offset 0, mask 0x1000 column 14: offset 0, mask 0x0800 column 15: offset 0, mask 0x2000 column 16: offset 0, mask 0x0010 column 17: offset 0, mask 0x8000 column 18: offset 0, mask 0x4000 column 19: offset 2, mask 0x0001 column 20: offset 2, mask 0x0002 column 21: offset 1, mask 0x0040 column 22: offset 1, mask 0x0080 column 23: offset 1, mask 0x0010 column 24: offset 1, mask 0x0020 column 25: offset 1, mask 0x0004 column 26: offset 1, mask 0x0008 column 27: offset 1, mask 0x0001 column 28: offset 1, mask 0x0002 column 29: offset 0, mask 0x0002 column 30: offset 0, mask 0x0001 column 31: offset 0, mask 0x0008 column 32: offset 0, mask 0x0004 direction bits (1=input) 0x4AF5 0xABAA 0xBFFA 0xFFFF 0xF0FF pullup bits (1=pullup) 0x0000 0x0000 0x0000 0x0000 0x0000 test step out_data dont care 1: 0x4A15 0xAAAA 0x8002 0x0000 0x0000 2: 0x4A15 0xAAAA 0x8002 0x0000 0x0000 3: 0x4A15 0xAAAA 0x4002 0x0000 0x0000 4: 0x4A15 0xAAAA 0x8002 0x0000 0x0000 5: 0x4A15 0xAAAA 0x8002 0x0000 0x0000 6: 0x4A15 0xACAA 0x8002 0x0000 0x0000 7: 0x4A15 0xAAAA 0x8002 0x0000 0x0000 8: 0x4A15 0xAAAA 0x8002 0x0000 0x0000 9: 0x4A15 0xB2AA 0x8002 0x0000 0x0000 10: 0x4A15 0xAAAA 0x8002 0x0000 0x0000 11: 0x4A15 0xAAAA 0x8002 0x0000 0x0000 12: 0x4A15 0xCAAA 0x8002 0x0000 0x0000 13: 0x4A15 0xAAAA 0x8002 0x0000 0x0000 14: 0x4A15 0xAAAA 0x8002 0x0000 0x0000 15: 0x4B15 0x2AAA 0x8002 0x0000 0x0000 16: 0x4A15 0xAAAA 0x8002 0x0000 0x0000 17: 0x4A15 0xAAAA 0x8002 0x0000 0x0000 18: 0x4C15 0xAAAA 0x8002 0x0000 0x0000 19: 0x4A15 0xAAAA 0x8002 0x0000 0x0000 20: 0x4A15 0xAAAA 0x8002 0x0000 0x0000 21: 0x5215 0xAAAA 0x8002 0x0000 0x0000 22: 0x4A15 0xAAAA 0x8002 0x0000 0x0000 23: 0x4A15 0xAAAA 0x8002 0x0000 0x0000 24: 0x6A05 0xAAAA 0x8002 0x0000 0x0000 25: 0x4A15 0xAAAA 0x8002 0x0000 0x0000 26: 0x4A15 0xAAAA 0x8002 0x0000 0x0000 27: 0x8A15 0xAAAA 0x8002 0x0000 0x0000 28: 0x4A15 0xAAAA 0x8002 0x0000 0x0000 29: 0x4A15 0xAAAA 0x8002 0x0000 0x0000 30: 0x4A15 0xAAAA 0x8001 0x0000 0x0000 31: 0x4A15 0xAAAA 0x8002 0x0000 0x0000 32: 0x4A15 0xAAAA 0x8002 0x0000 0x0000 33: 0x4A15 0xAA6A 0x8002 0x0000 0x0000 34: 0x4A15 0xAAAA 0x8002 0x0000 0x0000 35: 0x4A15 0xAAAA 0x8002 0x0000 0x0000 36: 0x4A15 0xAA9A 0x8002 0x0000 0x0000 37: 0x4A15 0xAAAA 0x8002 0x0000 0x0000 38: 0x4A15 0xAAAA 0x8002 0x0000 0x0000 39: 0x4A15 0xAAA6 0x8002 0x0000 0x0000 40: 0x4A15 0xAAAA 0x8002 0x0000 0x0000 41: 0x4A15 0xAAAA 0x8002 0x0000 0x0000 42: 0x4A15 0xAAA9 0x8002 0x0000 0x0000 43: 0x4A15 0xAAAA 0x8002 0x0000 0x0000 44: 0x4A15 0xAAAA 0x8002 0x0000 0x0000 45: 0x4A16 0xAAAA 0x8002 0x0000 0x0000 46: 0x4A15 0xAAAA 0x8002 0x0000 0x0000 47: 0x4A15 0xAAAA 0x8002 0x0000 0x0000 48: 0x4A19 0xAAAA 0x8002 0x0000 0x0000 49: 0x4A15 0xAAAA 0x8002 0x0000 0x0000 50: 0x4A15 0xAAAA 0x8002 0x0000 0x0000 51: 0xB50A 0x5455 0x4001 0x0000 0x0000 52: 0xB50A 0x5455 0x8001 0x0000 0x0000 53: 0xB50A 0x5455 0x4001 0x0000 0x0000 54: 0xB50A 0x5255 0x4001 0x0000 0x0000 55: 0xB50A 0x5455 0x4001 0x0000 0x0000 56: 0xB50A 0x4C55 0x4001 0x0000 0x0000 57: 0xB50A 0x5455 0x4001 0x0000 0x0000 58: 0xB50A 0x3455 0x4001 0x0000 0x0000 59: 0xB50A 0x5455 0x4001 0x0000 0x0000 60: 0xB40A 0xD455 0x4001 0x0000 0x0000 61: 0xB50A 0x5455 0x4001 0x0000 0x0000 62: 0xB30A 0x5455 0x4001 0x0000 0x0000 63: 0xB50A 0x5455 0x4001 0x0000 0x0000 64: 0xAD0A 0x5455 0x4001 0x0000 0x0000 65: 0xB50A 0x5455 0x4001 0x0000 0x0000 66: 0x951A 0x5455 0x4001 0x0000 0x0000 67: 0xB50A 0x5455 0x4001 0x0000 0x0000 68: 0x750A 0x5455 0x4001 0x0000 0x0000 69: 0xB50A 0x5455 0x4001 0x0000 0x0000 70: 0xB50A 0x5455 0x4002 0x0000 0x0000 71: 0xB50A 0x5455 0x4001 0x0000 0x0000 72: 0xB50A 0x5495 0x4001 0x0000 0x0000 73: 0xB50A 0x5455 0x4001 0x0000 0x0000 74: 0xB50A 0x5465 0x4001 0x0000 0x0000 75: 0xB50A 0x5455 0x4001 0x0000 0x0000 76: 0xB50A 0x5459 0x4001 0x0000 0x0000 77: 0xB50A 0x5455 0x4001 0x0000 0x0000 78: 0xB50A 0x5456 0x4001 0x0000 0x0000 79: 0xB50A 0x5455 0x4001 0x0000 0x0000 80: 0xB509 0x5455 0x4001 0x0000 0x0000 81: 0xB50A 0x5455 0x4001 0x0000 0x0000 82: 0xB506 0x5455 0x4001 0x0000 0x0000 83: 0xB50A 0x5455 0x4001 0x0000 0x0000 84: 0xB50A 0x5455 0x4001 0x0000 0x0000 PINs used (in edge connector order) (G=ground,P=power) SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBB LETTER ABCDEFHJKLMNPRSTUVABCDEFHJKLMNPRSTUVABCDEFHJKLMNPRSTUVABCDEFHJKLMNPRSTUV SIDE 111111111111111111222222222222222222111111111111111111222222222222222222 USAGE IOIIOIOIOIOIOIOGOIP GOIOIOIOIOIOIOIO G P G UUT has 16 inputs UUT has 16 outputs contains 32 pins/columns 34 pins are not used contains 84 'test steps' M111 PCB REV C SCHEMATIC REV A 16 INVERTERS USING 7400s PINS Main menu Sat Jul 18 10:03:07 2015 test file is: tests\m111.tst delay is: 0 trigger is: 1 1 read test file 2 set test delay 3 set test trigger 4 run test 5 output loading test 8 diags 9 exit UUT power is okay Sat Jul 18 10:03:09 2015 space single step O run once (one test, all steps) F run, stop on fail G go (run tests N run, stop on fail, no print S scope (run, no print) C toggle comment printout + increase speed (less delay) - decrease speed (more delay)(slower) Q quit test scope (run, no print) ppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppp ppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppp pppppFFFFFF space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C toggle comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER VURSNPLMJKFHDECDABUVSTPRMNKLHJEF SIDE 11111111111111121122222222222222 DIRECTION IOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIO all fails O O O O O O O O O O O O O O O O was lo 00000000000000000000000000000000 falling vvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvv rising ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ was hi 11111111111111111111111111111111 total fails 6, total passes 163 Main menu Sat Jul 18 10:03:19 2015 test file is: tests\m111.tst delay is: 0 trigger is: 1 1 read test file 2 set test delay 3 set test trigger 4 run test 5 output loading test 8 diags 9 exit Enter test file name? trying to open test file: tests\m160.tst reading test file: tests\m160.tst comment: M160 3 AND-OR TREES (4-2-2-2-3;4-2-2-4;2-2) comment: pins: PINS pins: 1 I AA1 E2-1 4-X-X-X-X pins: 2 I AB1 E2-2 4-X-X-X-X pins: 3 I AC1 E2-3 4-X-X-X-X pins: 4 I AD1 E2-13 4-X-X-X-X pins: 5 I AE1 E1-13 X-2-X-X-X pins: 6 I AF1 E1-1 X-2-X-X-X pins: 7 I AH1 E1-2 X-X-2-X-X pins: 8 I AJ1 E1-3 X-X-2-X-X pins: 9 I AK1 E1-5 X-X-X-2-X pins: 10 I AL1 E1-4 X-X-X-2-X pins: 11 I AM1 E2-6 X-X-X-X-3 pins: 12 I AN1 E2-5 X-X-X-X-3 pins: 13 I AP1 E2-4 X-X-X-X-3 pins: 14 O AR1 E1-8 OUPUT pins: 15 I AD2 E4-3 4-X-X-X pins: 16 I AE2 E4-2 4-X-X-X pins: 17 I AF2 E4-1 4-X-X-X pins: 18 I AH2 E4-13 4-X-X-X pins: 19 I AJ2 E3-1 X-2-X-X pins: 20 I AK2 E3-13 X-2-X-X pins: 21 I AL2 E3-10 X-X-2-X pins: 22 I AM2 E3-9 X-X-2-X pins: 23 I AN2 E4-8 X-X-X-4 pins: 24 I AP2 E4-5 X-X-X-4 pins: 25 I AR2 E4-6 X-X-X-4 pins: 26 I AS2 E4-4 X-X-X-4 pins: 27 O AT2 E3-8 OUTPUT pins: 28 I AS1 E3-5 2-X pins: 29 I AU1 E3-4 2-X pins: 30 I AV1 E3-2 X-2 pins: 31 I AU2 E3-3 X-2 pins: 32 O AV2 E3-6 OUTPUT pins: direction: IIIIIIIIIIIIIOIIIIIIIIIIIIOIIIIO test 1: 00000000000001000000000000100001 test 2: 0001 1 test 3: 0011 1 test 4: 0010 1 test 5: 0110 1 test 6: 0111 1 test 7: 0101 1 test 8: 0100 1 test 9: 1100 1 test 10: 1101 1 test 11: 1111 0 test 12: 1110 1 test 13: 1010 1 test 14: 1011 1 test 15: 1001 1 test 16: 1000 1 test 17: 00000000000001000000000000100001 test 18: 01 1 test 19: 10 1 test 20: 11 0 test 21: 01 1 test 22: 00000000000001000000000000100001 test 23: 01 1 test 24: 10 1 test 25: 11 0 test 26: 01 1 test 27: 00000000000001000000000000100001 test 28: 01 1 test 29: 10 1 test 30: 11 0 test 31: 01 1 test 32: 00000000000001000000000000100001 test 33: 0011 test 34: 0111 test 35: 0101 test 36: 0101 test 37: 1110 test 38: 1011 test 39: 1001 test 40: 00000000000001000000000000100001 test 41: 0001 1 test 42: 0011 1 test 43: 0010 1 test 44: 0110 1 test 45: 0111 1 test 46: 0101 1 test 47: 0100 1 test 48: 1100 1 test 49: 1101 1 test 50: 1111 0 test 51: 1110 1 test 52: 1010 1 test 53: 1011 1 test 54: 1001 1 test 55: 1000 1 test 56: 00000000000001000000000000100001 test 57: 01 1 test 58: 10 1 test 59: 11 0 test 60: 01 1 test 61: 00000000000001000000000000100001 test 62: 01 1 test 63: 10 1 test 64: 11 0 test 65: 01 1 test 66: 00000000000001000000000000100001 test 67: 00011 test 68: 00111 test 69: 00101 test 70: 01101 test 71: 01111 test 72: 01011 test 73: 01001 test 74: 11001 test 75: 11011 test 76: 11110 test 77: 11101 test 78: 10101 test 79: 10111 test 80: 10011 test 81: 10001 test 82: 00000000000001000000000000100001 test 83: 01 1 test 84: 10 1 test 85: 11 0 test 86: 01 1 test 87: 00000000000001000000000000100001 test 88: 011 test 89: 101 test 90: 110 test 91: 011 test 92: 00000000000001000000000000100001 end: END summary column 1: offset 0, mask 0x8000 column 2: offset 0, mask 0x4000 column 3: offset 0, mask 0x2000 column 4: offset 0, mask 0x1000 column 5: offset 0, mask 0x0800 column 6: offset 0, mask 0x0400 column 7: offset 0, mask 0x0200 column 8: offset 0, mask 0x0100 column 9: offset 1, mask 0x8000 column 10: offset 1, mask 0x4000 column 11: offset 1, mask 0x2000 column 12: offset 1, mask 0x1000 column 13: offset 1, mask 0x0800 column 14: offset 1, mask 0x0400 column 15: offset 0, mask 0x0010 column 16: offset 0, mask 0x0008 column 17: offset 0, mask 0x0004 column 18: offset 0, mask 0x0002 column 19: offset 0, mask 0x0001 column 20: offset 1, mask 0x0001 column 21: offset 1, mask 0x0002 column 22: offset 1, mask 0x0004 column 23: offset 1, mask 0x0008 column 24: offset 1, mask 0x0010 column 25: offset 1, mask 0x0020 column 26: offset 1, mask 0x0040 column 27: offset 1, mask 0x0080 column 28: offset 1, mask 0x0200 column 29: offset 2, mask 0x8000 column 30: offset 2, mask 0x4000 column 31: offset 2, mask 0x0001 column 32: offset 2, mask 0x0002 direction bits (1=input) 0x00E0 0x0580 0x3FFA 0xFFFF 0xF0FF pullup bits (1=pullup) 0x0000 0x0000 0x0000 0x0000 0x0000 test step out_data dont care 1: 0x0000 0x0480 0x0002 0x0000 0x0000 2: 0x1000 0x0480 0x0002 0x0000 0x0000 3: 0x3000 0x0480 0x0002 0x0000 0x0000 4: 0x2000 0x0480 0x0002 0x0000 0x0000 5: 0x6000 0x0480 0x0002 0x0000 0x0000 6: 0x7000 0x0480 0x0002 0x0000 0x0000 7: 0x5000 0x0480 0x0002 0x0000 0x0000 8: 0x4000 0x0480 0x0002 0x0000 0x0000 9: 0xC000 0x0480 0x0002 0x0000 0x0000 10: 0xD000 0x0480 0x0002 0x0000 0x0000 11: 0xF000 0x0080 0x0002 0x0000 0x0000 12: 0xE000 0x0480 0x0002 0x0000 0x0000 13: 0xA000 0x0480 0x0002 0x0000 0x0000 14: 0xB000 0x0480 0x0002 0x0000 0x0000 15: 0x9000 0x0480 0x0002 0x0000 0x0000 16: 0x8000 0x0480 0x0002 0x0000 0x0000 17: 0x0000 0x0480 0x0002 0x0000 0x0000 18: 0x0400 0x0480 0x0002 0x0000 0x0000 19: 0x0800 0x0480 0x0002 0x0000 0x0000 20: 0x0C00 0x0080 0x0002 0x0000 0x0000 21: 0x0400 0x0480 0x0002 0x0000 0x0000 22: 0x0000 0x0480 0x0002 0x0000 0x0000 23: 0x0100 0x0480 0x0002 0x0000 0x0000 24: 0x0200 0x0480 0x0002 0x0000 0x0000 25: 0x0300 0x0080 0x0002 0x0000 0x0000 26: 0x0100 0x0480 0x0002 0x0000 0x0000 27: 0x0000 0x0480 0x0002 0x0000 0x0000 28: 0x0000 0x4480 0x0002 0x0000 0x0000 29: 0x0000 0x8480 0x0002 0x0000 0x0000 30: 0x0000 0xC080 0x0002 0x0000 0x0000 31: 0x0000 0x4480 0x0002 0x0000 0x0000 32: 0x0000 0x0480 0x0002 0x0000 0x0000 33: 0x0000 0x0C80 0x0002 0x0000 0x0000 34: 0x0000 0x1C80 0x0002 0x0000 0x0000 35: 0x0000 0x1480 0x0002 0x0000 0x0000 36: 0x0000 0x1480 0x0002 0x0000 0x0000 37: 0x0000 0x3880 0x0002 0x0000 0x0000 38: 0x0000 0x2C80 0x0002 0x0000 0x0000 39: 0x0000 0x2480 0x0002 0x0000 0x0000 40: 0x0000 0x0480 0x0002 0x0000 0x0000 41: 0x0002 0x0480 0x0002 0x0000 0x0000 42: 0x0006 0x0480 0x0002 0x0000 0x0000 43: 0x0004 0x0480 0x0002 0x0000 0x0000 44: 0x000C 0x0480 0x0002 0x0000 0x0000 45: 0x000E 0x0480 0x0002 0x0000 0x0000 46: 0x000A 0x0480 0x0002 0x0000 0x0000 47: 0x0008 0x0480 0x0002 0x0000 0x0000 48: 0x0018 0x0480 0x0002 0x0000 0x0000 49: 0x001A 0x0480 0x0002 0x0000 0x0000 50: 0x001E 0x0400 0x0002 0x0000 0x0000 51: 0x001C 0x0480 0x0002 0x0000 0x0000 52: 0x0014 0x0480 0x0002 0x0000 0x0000 53: 0x0016 0x0480 0x0002 0x0000 0x0000 54: 0x0012 0x0480 0x0002 0x0000 0x0000 55: 0x0010 0x0480 0x0002 0x0000 0x0000 56: 0x0000 0x0480 0x0002 0x0000 0x0000 57: 0x0000 0x0481 0x0002 0x0000 0x0000 58: 0x0001 0x0480 0x0002 0x0000 0x0000 59: 0x0001 0x0401 0x0002 0x0000 0x0000 60: 0x0000 0x0481 0x0002 0x0000 0x0000 61: 0x0000 0x0480 0x0002 0x0000 0x0000 62: 0x0000 0x0484 0x0002 0x0000 0x0000 63: 0x0000 0x0482 0x0002 0x0000 0x0000 64: 0x0000 0x0406 0x0002 0x0000 0x0000 65: 0x0000 0x0484 0x0002 0x0000 0x0000 66: 0x0000 0x0480 0x0002 0x0000 0x0000 67: 0x0000 0x04C0 0x0002 0x0000 0x0000 68: 0x0000 0x04E0 0x0002 0x0000 0x0000 69: 0x0000 0x04A0 0x0002 0x0000 0x0000 70: 0x0000 0x04B0 0x0002 0x0000 0x0000 71: 0x0000 0x04F0 0x0002 0x0000 0x0000 72: 0x0000 0x04D0 0x0002 0x0000 0x0000 73: 0x0000 0x0490 0x0002 0x0000 0x0000 74: 0x0000 0x0498 0x0002 0x0000 0x0000 75: 0x0000 0x04D8 0x0002 0x0000 0x0000 76: 0x0000 0x0478 0x0002 0x0000 0x0000 77: 0x0000 0x04B8 0x0002 0x0000 0x0000 78: 0x0000 0x04A8 0x0002 0x0000 0x0000 79: 0x0000 0x04E8 0x0002 0x0000 0x0000 80: 0x0000 0x04C8 0x0002 0x0000 0x0000 81: 0x0000 0x0488 0x0002 0x0000 0x0000 82: 0x0000 0x0480 0x0002 0x0000 0x0000 83: 0x0000 0x0480 0x8002 0x0000 0x0000 84: 0x0000 0x0680 0x0002 0x0000 0x0000 85: 0x0000 0x0680 0x8000 0x0000 0x0000 86: 0x0000 0x0480 0x8002 0x0000 0x0000 87: 0x0000 0x0480 0x0002 0x0000 0x0000 88: 0x0000 0x0480 0x0003 0x0000 0x0000 89: 0x0000 0x0480 0x4002 0x0000 0x0000 90: 0x0000 0x0480 0x4001 0x0000 0x0000 91: 0x0000 0x0480 0x0003 0x0000 0x0000 92: 0x0000 0x0480 0x0002 0x0000 0x0000 PINs used (in edge connector order) (G=ground,P=power) SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBB LETTER ABCDEFHJKLMNPRSTUVABCDEFHJKLMNPRSTUVABCDEFHJKLMNPRSTUVABCDEFHJKLMNPRSTUV SIDE 111111111111111111222222222222222222111111111111111111222222222222222222 USAGE IIIIIIIIIIIIIOIGIIP GIIIIIIIIIIIIOIO G P G UUT has 29 inputs UUT has 3 outputs contains 32 pins/columns 34 pins are not used contains 92 'test steps' M160 3 AND-OR TREES (4-2-2-2-3;4-2-2-4;2-2) PINS Main menu Sat Jul 18 11:51:52 2015 test file is: tests\m160.tst delay is: 0 trigger is: 1 1 read test file 2 set test delay 3 set test trigger 4 run test 5 output loading test 8 diags 9 exit UUT power is okay Sat Jul 18 11:51:58 2015 space single step O run once (one test, all steps) F run, stop on fail G go (run tests N run, stop on fail, no print S scope (run, no print) C toggle comment printout + increase speed (less delay) - decrease speed (more delay)(slower) Q quit test scope (run, no print) FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF FFFFFFFFFFFFFFFFFFFFFFFFFFFF space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C toggle comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit step 31 00000000010001000000000000100001 step 32 00000000000001000000000000100001 step 33 00000000000011000000000000100001 step 34 00000000000111000000000000100001 step 35 00000000000101000000000000100001 step 36 00000000000101000000000000100001 SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFHJKLMNPRDEFHJKLMNPRSTSUVUV SIDE 11111111111111222222222222211122 DIRECTION IIIIIIIIIIIIIOIIIIIIIIIIIIOIIIIO changed: 1 1 step 37 00000000001111000000000000100001 fail ^ space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C toggle comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit step 38 00000000001011000000000000100001 step 39 00000000001001000000000000100001 step 40 00000000000001000000000000100001 step 41 00000000000001000100000000100001 step 42 00000000000001001100000000100001 step 43 00000000000001001000000000100001 step 44 00000000000001011000000000100001 step 45 00000000000001011100000000100001 step 46 00000000000001010100000000100001 step 47 00000000000001010000000000100001 step 48 00000000000001110000000000100001 step 49 00000000000001110100000000100001 step 50 00000000000001111100000000000001 step 51 00000000000001111000000000100001 step 52 00000000000001101000000000100001 step 53 00000000000001101100000000100001 step 54 00000000000001100100000000100001 step 55 00000000000001100000000000100001 step 56 00000000000001000000000000100001 step 57 00000000000001000001000000100001 step 58 00000000000001000010000000100001 step 59 00000000000001000011000000000001 step 60 00000000000001000001000000100001 step 61 00000000000001000000000000100001 step 62 00000000000001000000010000100001 step 63 00000000000001000000100000100001 step 64 00000000000001000000110000000001 step 65 00000000000001000000010000100001 step 66 00000000000001000000000000100001 step 67 00000000000001000000000001100001 step 68 00000000000001000000000011100001 step 69 00000000000001000000000010100001 step 70 00000000000001000000000110100001 step 71 00000000000001000000000111100001 step 72 00000000000001000000000101100001 step 73 00000000000001000000000100100001 step 74 00000000000001000000001100100001 step 75 00000000000001000000001101100001 step 76 00000000000001000000001111000001 step 77 00000000000001000000001110100001 step 78 00000000000001000000001010100001 step 79 00000000000001000000001011100001 step 80 00000000000001000000001001100001 step 81 00000000000001000000001000100001 step 82 00000000000001000000000000100001 step 83 00000000000001000000000000101001 step 84 00000000000001000000000000110001 step 85 00000000000001000000000000111000 step 86 00000000000001000000000000101001 step 87 00000000000001000000000000100001 step 88 00000000000001000000000000100011 step 89 00000000000001000000000000100101 step 90 00000000000001000000000000100110 step 91 00000000000001000000000000100011 step 92 00000000000001000000000000100001 test 266: *** FAIL *************************** 1 steps failed SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFHJKLMNPRDEFHJKLMNPRSTSUVUV SIDE 11111111111111222222222222211122 DIRECTION IIIIIIIIIIIIIOIIIIIIIIIIIIOIIIIO this fail O all fails O was hi 11111111111111111111111111111111 rising ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ falling vvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvv was lo 00000000000000000000000000000000 total fails 266, total passes 0 space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C toggle comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit step 1 00000000000001000000000000100001 step 2 00010000000001000000000000100001 step 3 00110000000001000000000000100001 step 4 00100000000001000000000000100001 step 5 01100000000001000000000000100001 step 6 01110000000001000000000000100001 step 7 01010000000001000000000000100001 step 8 01000000000001000000000000100001 step 9 11000000000001000000000000100001 step 10 11010000000001000000000000100001 step 11 11110000000000000000000000100001 step 12 11100000000001000000000000100001 step 13 10100000000001000000000000100001 step 14 10110000000001000000000000100001 step 15 10010000000001000000000000100001 step 16 10000000000001000000000000100001 step 17 00000000000001000000000000100001 step 18 00000100000001000000000000100001 step 19 00001000000001000000000000100001 step 20 00001100000000000000000000100001 step 21 00000100000001000000000000100001 step 22 00000000000001000000000000100001 step 23 00000001000001000000000000100001 step 24 00000010000001000000000000100001 step 25 00000011000000000000000000100001 step 26 00000001000001000000000000100001 step 27 00000000000001000000000000100001 step 28 00000000010001000000000000100001 step 29 00000000100001000000000000100001 step 30 00000000110000000000000000100001 step 31 00000000010001000000000000100001 step 32 00000000000001000000000000100001 step 33 00000000000011000000000000100001 step 34 00000000000111000000000000100001 step 35 00000000000101000000000000100001 step 36 00000000000101000000000000100001 SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFHJKLMNPRDEFHJKLMNPRSTSUVUV SIDE 11111111111111222222222222211122 DIRECTION IIIIIIIIIIIIIOIIIIIIIIIIIIOIIIIO changed: 1 1 step 37 00000000001111000000000000100001 fail ^ step 38 00000000001011000000000000100001 step 39 00000000001001000000000000100001 step 40 00000000000001000000000000100001 step 41 00000000000001000100000000100001 step 42 00000000000001001100000000100001 step 43 00000000000001001000000000100001 step 44 00000000000001011000000000100001 step 45 00000000000001011100000000100001 step 46 00000000000001010100000000100001 step 47 00000000000001010000000000100001 step 48 00000000000001110000000000100001 step 49 00000000000001110100000000100001 step 50 00000000000001111100000000000001 step 51 00000000000001111000000000100001 step 52 00000000000001101000000000100001 step 53 00000000000001101100000000100001 step 54 00000000000001100100000000100001 step 55 00000000000001100000000000100001 step 56 00000000000001000000000000100001 step 57 00000000000001000001000000100001 step 58 00000000000001000010000000100001 step 59 00000000000001000011000000000001 step 60 00000000000001000001000000100001 step 61 00000000000001000000000000100001 step 62 00000000000001000000010000100001 step 63 00000000000001000000100000100001 step 64 00000000000001000000110000000001 step 65 00000000000001000000010000100001 step 66 00000000000001000000000000100001 step 67 00000000000001000000000001100001 step 68 00000000000001000000000011100001 step 69 00000000000001000000000010100001 step 70 00000000000001000000000110100001 step 71 00000000000001000000000111100001 step 72 00000000000001000000000101100001 step 73 00000000000001000000000100100001 step 74 00000000000001000000001100100001 step 75 00000000000001000000001101100001 step 76 00000000000001000000001111000001 step 77 00000000000001000000001110100001 step 78 00000000000001000000001010100001 step 79 00000000000001000000001011100001 step 80 00000000000001000000001001100001 step 81 00000000000001000000001000100001 step 82 00000000000001000000000000100001 step 83 00000000000001000000000000101001 step 84 00000000000001000000000000110001 step 85 00000000000001000000000000111000 step 86 00000000000001000000000000101001 step 87 00000000000001000000000000100001 step 88 00000000000001000000000000100011 step 89 00000000000001000000000000100101 step 90 00000000000001000000000000100110 step 91 00000000000001000000000000100011 step 92 00000000000001000000000000100001 test 267: *** FAIL *************************** 1 steps failed SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFHJKLMNPRDEFHJKLMNPRSTSUVUV SIDE 11111111111111222222222222211122 DIRECTION IIIIIIIIIIIIIOIIIIIIIIIIIIOIIIIO this fail O all fails O was hi 11111111111111111111111111111111 rising ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ falling vvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvv was lo 00000000000000000000000000000000 total fails 267, total passes 0 space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C toggle comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit step 1 00000000000001000000000000100001 step 2 00010000000001000000000000100001 step 3 00110000000001000000000000100001 step 4 00100000000001000000000000100001 step 5 01100000000001000000000000100001 step 6 01110000000001000000000000100001 step 7 01010000000001000000000000100001 step 8 01000000000001000000000000100001 step 9 11000000000001000000000000100001 step 10 11010000000001000000000000100001 step 11 11110000000000000000000000100001 step 12 11100000000001000000000000100001 step 13 10100000000001000000000000100001 step 14 10110000000001000000000000100001 step 15 10010000000001000000000000100001 step 16 10000000000001000000000000100001 step 17 00000000000001000000000000100001 step 18 00000100000001000000000000100001 step 19 00001000000001000000000000100001 step 20 00001100000000000000000000100001 step 21 00000100000001000000000000100001 step 22 00000000000001000000000000100001 step 23 00000001000001000000000000100001 step 24 00000010000001000000000000100001 step 25 00000011000000000000000000100001 step 26 00000001000001000000000000100001 step 27 00000000000001000000000000100001 step 28 00000000010001000000000000100001 step 29 00000000100001000000000000100001 step 30 00000000110000000000000000100001 step 31 00000000010001000000000000100001 step 32 00000000000001000000000000100001 step 33 00000000000011000000000000100001 step 34 00000000000111000000000000100001 step 35 00000000000101000000000000100001 step 36 00000000000101000000000000100001 SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFHJKLMNPRDEFHJKLMNPRSTSUVUV SIDE 11111111111111222222222222211122 DIRECTION IIIIIIIIIIIIIOIIIIIIIIIIIIOIIIIO changed: 1 1 step 37 00000000001111000000000000100001 fail ^ step 38 00000000001011000000000000100001 step 39 00000000001001000000000000100001 step 40 00000000000001000000000000100001 step 41 00000000000001000100000000100001 step 42 00000000000001001100000000100001 step 43 00000000000001001000000000100001 step 44 00000000000001011000000000100001 step 45 00000000000001011100000000100001 step 46 00000000000001010100000000100001 step 47 00000000000001010000000000100001 step 48 00000000000001110000000000100001 step 49 00000000000001110100000000100001 step 50 00000000000001111100000000000001 step 51 00000000000001111000000000100001 step 52 00000000000001101000000000100001 step 53 00000000000001101100000000100001 step 54 00000000000001100100000000100001 step 55 00000000000001100000000000100001 step 56 00000000000001000000000000100001 step 57 00000000000001000001000000100001 step 58 00000000000001000010000000100001 step 59 00000000000001000011000000000001 step 60 00000000000001000001000000100001 step 61 00000000000001000000000000100001 step 62 00000000000001000000010000100001 step 63 00000000000001000000100000100001 step 64 00000000000001000000110000000001 step 65 00000000000001000000010000100001 step 66 00000000000001000000000000100001 step 67 00000000000001000000000001100001 step 68 00000000000001000000000011100001 step 69 00000000000001000000000010100001 step 70 00000000000001000000000110100001 step 71 00000000000001000000000111100001 step 72 00000000000001000000000101100001 step 73 00000000000001000000000100100001 step 74 00000000000001000000001100100001 step 75 00000000000001000000001101100001 step 76 00000000000001000000001111000001 step 77 00000000000001000000001110100001 step 78 00000000000001000000001010100001 step 79 00000000000001000000001011100001 step 80 00000000000001000000001001100001 step 81 00000000000001000000001000100001 step 82 00000000000001000000000000100001 step 83 00000000000001000000000000101001 step 84 00000000000001000000000000110001 step 85 00000000000001000000000000111000 step 86 00000000000001000000000000101001 step 87 00000000000001000000000000100001 step 88 00000000000001000000000000100011 step 89 00000000000001000000000000100101 step 90 00000000000001000000000000100110 step 91 00000000000001000000000000100011 step 92 00000000000001000000000000100001 test 268: *** FAIL *************************** 1 steps failed SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFHJKLMNPRDEFHJKLMNPRSTSUVUV SIDE 11111111111111222222222222211122 DIRECTION IIIIIIIIIIIIIOIIIIIIIIIIIIOIIIIO this fail O all fails O was hi 11111111111111111111111111111111 rising ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ falling vvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvv was lo 00000000000000000000000000000000 total fails 268, total passes 0 space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C toggle comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C toggle comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFHJKLMNPRDEFHJKLMNPRSTSUVUV SIDE 11111111111111222222222222211122 DIRECTION IIIIIIIIIIIIIOIIIIIIIIIIIIOIIIIO all fails O was lo 00000000000000000000000000000000 falling vvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvv rising ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ was hi 11111111111111111111111111111111 total fails 268, total passes 0 Main menu Sat Jul 18 11:54:45 2015 test file is: tests\m160.tst delay is: 0 trigger is: 1 1 read test file 2 set test delay 3 set test trigger 4 run test 5 output loading test 8 diags 9 exit UUT power is okay Sat Jul 18 11:54:46 2015 space single step O run once (one test, all steps) F run, stop on fail G go (run tests N run, stop on fail, no print S scope (run, no print) C toggle comment printout + increase speed (less delay) - decrease speed (more delay)(slower) Q quit test scope (run, no print) FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C toggle comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit step 74 00000000000001000000001100100001 step 75 00000000000001000000001101100001 step 76 00000000000001000000001111000001 step 77 00000000000001000000001110100001 step 78 00000000000001000000001010100001 step 79 00000000000001000000001011100001 step 80 00000000000001000000001001100001 step 81 00000000000001000000001000100001 step 82 00000000000001000000000000100001 step 83 00000000000001000000000000101001 step 84 00000000000001000000000000110001 step 85 00000000000001000000000000111000 step 86 00000000000001000000000000101001 step 87 00000000000001000000000000100001 step 88 00000000000001000000000000100011 step 89 00000000000001000000000000100101 step 90 00000000000001000000000000100110 step 91 00000000000001000000000000100011 step 92 00000000000001000000000000100001 test 126: *** FAIL *************************** 1 steps failed SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFHJKLMNPRDEFHJKLMNPRSTSUVUV SIDE 11111111111111222222222222211122 DIRECTION IIIIIIIIIIIIIOIIIIIIIIIIIIOIIIIO this fail O all fails O was hi 11111111111111111111111111111111 rising ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ falling vvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvv was lo 00000000000000000000000000000000 total fails 126, total passes 0 space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C toggle comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit step 1 00000000000001000000000000100001 step 2 00010000000001000000000000100001 step 3 00110000000001000000000000100001 step 4 00100000000001000000000000100001 step 5 01100000000001000000000000100001 step 6 01110000000001000000000000100001 step 7 01010000000001000000000000100001 step 8 01000000000001000000000000100001 step 9 11000000000001000000000000100001 step 10 11010000000001000000000000100001 step 11 11110000000000000000000000100001 step 12 11100000000001000000000000100001 step 13 10100000000001000000000000100001 step 14 10110000000001000000000000100001 step 15 10010000000001000000000000100001 step 16 10000000000001000000000000100001 step 17 00000000000001000000000000100001 step 18 00000100000001000000000000100001 step 19 00001000000001000000000000100001 step 20 00001100000000000000000000100001 step 21 00000100000001000000000000100001 step 22 00000000000001000000000000100001 step 23 00000001000001000000000000100001 step 24 00000010000001000000000000100001 step 25 00000011000000000000000000100001 step 26 00000001000001000000000000100001 step 27 00000000000001000000000000100001 step 28 00000000010001000000000000100001 step 29 00000000100001000000000000100001 step 30 00000000110000000000000000100001 step 31 00000000010001000000000000100001 step 32 00000000000001000000000000100001 step 33 00000000000011000000000000100001 step 34 00000000000111000000000000100001 step 35 00000000000101000000000000100001 step 36 00000000000101000000000000100001 step 37 00000000001110000000000000100001 step 38 00000000001011000000000000100001 step 39 00000000001001000000000000100001 step 40 00000000000001000000000000100001 step 41 00000000000001000100000000100001 step 42 00000000000001001100000000100001 step 43 00000000000001001000000000100001 step 44 00000000000001011000000000100001 step 45 00000000000001011100000000100001 step 46 00000000000001010100000000100001 step 47 00000000000001010000000000100001 step 48 00000000000001110000000000100001 step 49 00000000000001110100000000100001 step 50 00000000000001111100000000000001 step 51 00000000000001111000000000100001 step 52 00000000000001101000000000100001 step 53 00000000000001101100000000100001 step 54 00000000000001100100000000100001 step 55 00000000000001100000000000100001 step 56 00000000000001000000000000100001 step 57 00000000000001000001000000100001 step 58 00000000000001000010000000100001 step 59 00000000000001000011000000000001 step 60 00000000000001000001000000100001 step 61 00000000000001000000000000100001 step 62 00000000000001000000010000100001 step 63 00000000000001000000100000100001 step 64 00000000000001000000110000000001 step 65 00000000000001000000010000100001 step 66 00000000000001000000000000100001 step 67 00000000000001000000000001100001 step 68 00000000000001000000000011100001 step 69 00000000000001000000000010100001 step 70 00000000000001000000000110100001 SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFHJKLMNPRDEFHJKLMNPRSTSUVUV SIDE 11111111111111222222222222211122 DIRECTION IIIIIIIIIIIIIOIIIIIIIIIIIIOIIIIO changed: 10 step 71 00000000000001000000000111000001 fail ^ step 72 00000000000001000000000101100001 step 73 00000000000001000000000100100001 step 74 00000000000001000000001100100001 step 75 00000000000001000000001101100001 step 76 00000000000001000000001111000001 step 77 00000000000001000000001110100001 step 78 00000000000001000000001010100001 step 79 00000000000001000000001011100001 step 80 00000000000001000000001001100001 step 81 00000000000001000000001000100001 step 82 00000000000001000000000000100001 step 83 00000000000001000000000000101001 step 84 00000000000001000000000000110001 step 85 00000000000001000000000000111000 step 86 00000000000001000000000000101001 step 87 00000000000001000000000000100001 step 88 00000000000001000000000000100011 step 89 00000000000001000000000000100101 step 90 00000000000001000000000000100110 step 91 00000000000001000000000000100011 step 92 00000000000001000000000000100001 test 127: *** FAIL *************************** 1 steps failed SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFHJKLMNPRDEFHJKLMNPRSTSUVUV SIDE 11111111111111222222222222211122 DIRECTION IIIIIIIIIIIIIOIIIIIIIIIIIIOIIIIO this fail O all fails O was hi 11111111111111111111111111111111 rising ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ falling vvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvv was lo 00000000000000000000000000000000 total fails 127, total passes 0 space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C toggle comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFHJKLMNPRDEFHJKLMNPRSTSUVUV SIDE 11111111111111222222222222211122 DIRECTION IIIIIIIIIIIIIOIIIIIIIIIIIIOIIIIO all fails O was lo 00000000000000000000000000000000 falling vvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvv rising ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ was hi 11111111111111111111111111111111 total fails 127, total passes 0 Main menu Sat Jul 18 11:55:39 2015 test file is: tests\m160.tst delay is: 0 trigger is: 1 1 read test file 2 set test delay 3 set test trigger 4 run test 5 output loading test 8 diags 9 exit Enter test trigger (1 to 92)? could not 'sscanf(..."10608"..) Main menu Sat Jul 18 11:55:45 2015 test file is: tests\m160.tst delay is: 0 trigger is: 1 1 read test file 2 set test delay 3 set test trigger 4 run test 5 output loading test 8 diags 9 exit UUT power is okay Sat Jul 18 11:55:49 2015 space single step O run once (one test, all steps) F run, stop on fail G go (run tests N run, stop on fail, no print S scope (run, no print) C toggle comment printout + increase speed (less delay) - decrease speed (more delay)(slower) Q quit test scope (run, no print) ppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppp ppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppp ppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppp ppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppp ppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppp ppppppppppppppppppppppppppppppppppppppppppFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C toggle comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFHJKLMNPRDEFHJKLMNPRSTSUVUV SIDE 11111111111111222222222222211122 DIRECTION IIIIIIIIIIIIIOIIIIIIIIIIIIOIIIIO all fails O O O was lo 00000000000000000000000000000000 falling vvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvv rising ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ was hi 11111111111111111111111111111111 total fails 353, total passes 437 Main menu Sat Jul 18 11:59:33 2015 test file is: tests\m160.tst delay is: 0 trigger is: 1 1 read test file 2 set test delay 3 set test trigger 4 run test 5 output loading test 8 diags 9 exit exiting tester- PDP8 card tester via printer port version 0.85 June 4, 2015 mapping[] is verified Main menu Mon Jul 27 14:39:51 2015 test file is: delay is: 0 trigger is: 1 1 read test file 2 set test delay 3 set test trigger 4 run test 5 output loading test 8 diags 9 exit Enter test file name? trying to open test file: tests\m111.tst reading test file: tests\m111.tst comment: M111 PCB REV C SCHEMATIC REV A 16 INVERTERS USING 7400s pins: PINS pins: 1 I AV1 E4-9 pins: 2 O AU1 E4-8 pins: 3 I AR1 E4-12 pins: 4 O AS1 E4-11 pins: 5 I AN1 E3-10 pins: 6 O AP1 E3-8 pins: 7 I AL1 E3-12 pins: 8 O AM1 E3-11 pins: 9 I AJ1 E1-9 pins: 10 O AK1 E1-8 pins: 11 I AF1 E1-12 pins: 12 O AH1 E1-11 pins: 13 I AD1 E2-9 pins: 14 O AE1 E2-8 pins: 15 I AC1 E2-5 pins: 16 O AD2 E2-6 pins: 17 I AA1 E2-12 pins: 18 O AB1 E2-11 pins: 19 I AU2 E4-1 pins: 20 O AV2 E4-2 pins: 21 I AS2 E4-5 pins: 22 O AT2 E4-6 pins: 23 I AP2 E3-1 pins: 24 O AR2 E3-2 pins: 25 I AM2 E3-5 pins: 26 O AN2 E3-6 pins: 27 I AK2 E1-1 pins: 28 O AL2 E1-3 pins: 29 I AH2 E1-5 pins: 30 O AJ2 E1-6 pins: 31 I AE2 E2-1 pins: 32 O AF2 E2-3 pins: direction: IOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIO test 1: 01010101010101010101010101010101 test 2: 01 test 3: 10 test 4: 01 test 5: 01 test 6: 10 test 7: 01 test 8: 01 test 9: 10 test 10: 01 test 11: 01 test 12: 10 test 13: 01 test 14: 01 test 15: 10 test 16: 01 test 17: 01 test 18: 10 test 19: 01 test 20: 01 test 21: 10 test 22: 01 test 23: 01 test 24: 10 test 25: 01 test 26: 01 test 27: 10 test 28: 01 test 29: 01 test 30: 10 test 31: 01 test 32: 01 test 33: 10 test 34: 01 test 35: 01 test 36: 10 test 37: 01 test 38: 01 test 39: 10 test 40: 01 test 41: 01 test 42: 10 test 43: 01 test 44: 01 test 45: 10 test 46: 01 test 47: 01 test 48: 10 test 49: 01 test 50: 01010101010101010101010101010101 test 51: 10101010101010101010101010101010 test 52: 01 test 53: 10 test 54: 01 test 55: 10 test 56: 01 test 57: 10 test 58: 01 test 59: 10 test 60: 01 test 61: 10 test 62: 01 test 63: 10 test 64: 01 test 65: 10 test 66: 01 test 67: 10 test 68: 01 test 69: 10 test 70: 01 test 71: 10 test 72: 01 test 73: 10 test 74: 01 test 75: 10 test 76: 01 test 77: 10 test 78: 01 test 79: 10 test 80: 01 test 81: 10 test 82: 01 test 83: 10 test 84: 10101010101010101010101010101010 end: END summary column 1: offset 2, mask 0x4000 column 2: offset 2, mask 0x8000 column 3: offset 1, mask 0x0400 column 4: offset 1, mask 0x0200 column 5: offset 1, mask 0x1000 column 6: offset 1, mask 0x0800 column 7: offset 1, mask 0x4000 column 8: offset 1, mask 0x2000 column 9: offset 0, mask 0x0100 column 10: offset 1, mask 0x8000 column 11: offset 0, mask 0x0400 column 12: offset 0, mask 0x0200 column 13: offset 0, mask 0x1000 column 14: offset 0, mask 0x0800 column 15: offset 0, mask 0x2000 column 16: offset 0, mask 0x0010 column 17: offset 0, mask 0x8000 column 18: offset 0, mask 0x4000 column 19: offset 2, mask 0x0001 column 20: offset 2, mask 0x0002 column 21: offset 1, mask 0x0040 column 22: offset 1, mask 0x0080 column 23: offset 1, mask 0x0010 column 24: offset 1, mask 0x0020 column 25: offset 1, mask 0x0004 column 26: offset 1, mask 0x0008 column 27: offset 1, mask 0x0001 column 28: offset 1, mask 0x0002 column 29: offset 0, mask 0x0002 column 30: offset 0, mask 0x0001 column 31: offset 0, mask 0x0008 column 32: offset 0, mask 0x0004 direction bits (1=input) 0x4AF5 0xABAA 0xBFFA 0xFFFF 0xF0FF pullup bits (1=pullup) 0x0000 0x0000 0x0000 0x0000 0x0000 test step out_data dont care 1: 0x4A15 0xAAAA 0x8002 0x0000 0x0000 2: 0x4A15 0xAAAA 0x8002 0x0000 0x0000 3: 0x4A15 0xAAAA 0x4002 0x0000 0x0000 4: 0x4A15 0xAAAA 0x8002 0x0000 0x0000 5: 0x4A15 0xAAAA 0x8002 0x0000 0x0000 6: 0x4A15 0xACAA 0x8002 0x0000 0x0000 7: 0x4A15 0xAAAA 0x8002 0x0000 0x0000 8: 0x4A15 0xAAAA 0x8002 0x0000 0x0000 9: 0x4A15 0xB2AA 0x8002 0x0000 0x0000 10: 0x4A15 0xAAAA 0x8002 0x0000 0x0000 11: 0x4A15 0xAAAA 0x8002 0x0000 0x0000 12: 0x4A15 0xCAAA 0x8002 0x0000 0x0000 13: 0x4A15 0xAAAA 0x8002 0x0000 0x0000 14: 0x4A15 0xAAAA 0x8002 0x0000 0x0000 15: 0x4B15 0x2AAA 0x8002 0x0000 0x0000 16: 0x4A15 0xAAAA 0x8002 0x0000 0x0000 17: 0x4A15 0xAAAA 0x8002 0x0000 0x0000 18: 0x4C15 0xAAAA 0x8002 0x0000 0x0000 19: 0x4A15 0xAAAA 0x8002 0x0000 0x0000 20: 0x4A15 0xAAAA 0x8002 0x0000 0x0000 21: 0x5215 0xAAAA 0x8002 0x0000 0x0000 22: 0x4A15 0xAAAA 0x8002 0x0000 0x0000 23: 0x4A15 0xAAAA 0x8002 0x0000 0x0000 24: 0x6A05 0xAAAA 0x8002 0x0000 0x0000 25: 0x4A15 0xAAAA 0x8002 0x0000 0x0000 26: 0x4A15 0xAAAA 0x8002 0x0000 0x0000 27: 0x8A15 0xAAAA 0x8002 0x0000 0x0000 28: 0x4A15 0xAAAA 0x8002 0x0000 0x0000 29: 0x4A15 0xAAAA 0x8002 0x0000 0x0000 30: 0x4A15 0xAAAA 0x8001 0x0000 0x0000 31: 0x4A15 0xAAAA 0x8002 0x0000 0x0000 32: 0x4A15 0xAAAA 0x8002 0x0000 0x0000 33: 0x4A15 0xAA6A 0x8002 0x0000 0x0000 34: 0x4A15 0xAAAA 0x8002 0x0000 0x0000 35: 0x4A15 0xAAAA 0x8002 0x0000 0x0000 36: 0x4A15 0xAA9A 0x8002 0x0000 0x0000 37: 0x4A15 0xAAAA 0x8002 0x0000 0x0000 38: 0x4A15 0xAAAA 0x8002 0x0000 0x0000 39: 0x4A15 0xAAA6 0x8002 0x0000 0x0000 40: 0x4A15 0xAAAA 0x8002 0x0000 0x0000 41: 0x4A15 0xAAAA 0x8002 0x0000 0x0000 42: 0x4A15 0xAAA9 0x8002 0x0000 0x0000 43: 0x4A15 0xAAAA 0x8002 0x0000 0x0000 44: 0x4A15 0xAAAA 0x8002 0x0000 0x0000 45: 0x4A16 0xAAAA 0x8002 0x0000 0x0000 46: 0x4A15 0xAAAA 0x8002 0x0000 0x0000 47: 0x4A15 0xAAAA 0x8002 0x0000 0x0000 48: 0x4A19 0xAAAA 0x8002 0x0000 0x0000 49: 0x4A15 0xAAAA 0x8002 0x0000 0x0000 50: 0x4A15 0xAAAA 0x8002 0x0000 0x0000 51: 0xB50A 0x5455 0x4001 0x0000 0x0000 52: 0xB50A 0x5455 0x8001 0x0000 0x0000 53: 0xB50A 0x5455 0x4001 0x0000 0x0000 54: 0xB50A 0x5255 0x4001 0x0000 0x0000 55: 0xB50A 0x5455 0x4001 0x0000 0x0000 56: 0xB50A 0x4C55 0x4001 0x0000 0x0000 57: 0xB50A 0x5455 0x4001 0x0000 0x0000 58: 0xB50A 0x3455 0x4001 0x0000 0x0000 59: 0xB50A 0x5455 0x4001 0x0000 0x0000 60: 0xB40A 0xD455 0x4001 0x0000 0x0000 61: 0xB50A 0x5455 0x4001 0x0000 0x0000 62: 0xB30A 0x5455 0x4001 0x0000 0x0000 63: 0xB50A 0x5455 0x4001 0x0000 0x0000 64: 0xAD0A 0x5455 0x4001 0x0000 0x0000 65: 0xB50A 0x5455 0x4001 0x0000 0x0000 66: 0x951A 0x5455 0x4001 0x0000 0x0000 67: 0xB50A 0x5455 0x4001 0x0000 0x0000 68: 0x750A 0x5455 0x4001 0x0000 0x0000 69: 0xB50A 0x5455 0x4001 0x0000 0x0000 70: 0xB50A 0x5455 0x4002 0x0000 0x0000 71: 0xB50A 0x5455 0x4001 0x0000 0x0000 72: 0xB50A 0x5495 0x4001 0x0000 0x0000 73: 0xB50A 0x5455 0x4001 0x0000 0x0000 74: 0xB50A 0x5465 0x4001 0x0000 0x0000 75: 0xB50A 0x5455 0x4001 0x0000 0x0000 76: 0xB50A 0x5459 0x4001 0x0000 0x0000 77: 0xB50A 0x5455 0x4001 0x0000 0x0000 78: 0xB50A 0x5456 0x4001 0x0000 0x0000 79: 0xB50A 0x5455 0x4001 0x0000 0x0000 80: 0xB509 0x5455 0x4001 0x0000 0x0000 81: 0xB50A 0x5455 0x4001 0x0000 0x0000 82: 0xB506 0x5455 0x4001 0x0000 0x0000 83: 0xB50A 0x5455 0x4001 0x0000 0x0000 84: 0xB50A 0x5455 0x4001 0x0000 0x0000 PINs used (in edge connector order) (G=ground,P=power) SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBB LETTER ABCDEFHJKLMNPRSTUVABCDEFHJKLMNPRSTUVABCDEFHJKLMNPRSTUVABCDEFHJKLMNPRSTUV SIDE 111111111111111111222222222222222222111111111111111111222222222222222222 USAGE IOIIOIOIOIOIOIOGOIP GOIOIOIOIOIOIOIO G P G UUT has 16 inputs UUT has 16 outputs contains 32 pins/columns 34 pins are not used contains 84 'test steps' M111 PCB REV C SCHEMATIC REV A 16 INVERTERS USING 7400s PINS Main menu Mon Jul 27 14:40:00 2015 test file is: tests\m111.tst delay is: 0 trigger is: 1 1 read test file 2 set test delay 3 set test trigger 4 run test 5 output loading test 8 diags 9 exit UUT power is okay Mon Jul 27 14:40:03 2015 space single step O run once (one test, all steps) F run, stop on fail G go (run tests N run, stop on fail, no print S scope (run, no print) C toggle comment printout + increase speed (less delay) - decrease speed (more delay)(slower) Q quit test scope (run, no print) ppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppp pppppppppppppppppppppppppppppppppppppppppppppppFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF FFFFFFFFFFFFFFFFFpppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppp ppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppp pppppp space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C toggle comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER VURSNPLMJKFHDECDABUVSTPRMNKLHJEF SIDE 11111111111111121122222222222222 DIRECTION IOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIO all fails OIO O O O O O O O O O O O O O O was lo 00000000000000000000000000000000 falling vvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvv rising ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ was hi 11111111111111111111111111111111 total fails 1629, total passes 273 Main menu Mon Jul 27 14:41:27 2015 test file is: tests\m111.tst delay is: 0 trigger is: 1 1 read test file 2 set test delay 3 set test trigger 4 run test 5 output loading test 8 diags 9 exit UUT power is okay Mon Jul 27 14:41:28 2015 space single step O run once (one test, all steps) F run, stop on fail G go (run tests N run, stop on fail, no print S scope (run, no print) C toggle comment printout + increase speed (less delay) - decrease speed (more delay)(slower) Q quit test scope (run, no print) ppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppp ppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppp p space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C toggle comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER VURSNPLMJKFHDECDABUVSTPRMNKLHJEF SIDE 11111111111111121122222222222222 DIRECTION IOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIO all fails was lo 00000000000000000000000000000000 falling vvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvv rising ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ was hi 11111111111111111111111111111111 total fails 0, total passes 159 Main menu Mon Jul 27 14:41:36 2015 test file is: tests\m111.tst delay is: 0 trigger is: 1 1 read test file 2 set test delay 3 set test trigger 4 run test 5 output loading test 8 diags 9 exit UUT power is okay Mon Jul 27 14:42:58 2015 space single step O run once (one test, all steps) F run, stop on fail G go (run tests N run, stop on fail, no print S scope (run, no print) C toggle comment printout + increase speed (less delay) - decrease speed (more delay)(slower) Q quit test scope (run, no print) ppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppp pppppppppppppppppppppppppppppppp space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C toggle comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER VURSNPLMJKFHDECDABUVSTPRMNKLHJEF SIDE 11111111111111121122222222222222 DIRECTION IOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIO all fails was lo 00000000000000000000000000000000 falling vvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvv rising ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ was hi 11111111111111111111111111111111 total fails 0, total passes 111 Main menu Mon Jul 27 14:43:04 2015 test file is: tests\m111.tst delay is: 0 trigger is: 1 1 read test file 2 set test delay 3 set test trigger 4 run test 5 output loading test 8 diags 9 exit UUT power is okay Mon Jul 27 14:44:54 2015 space single step O run once (one test, all steps) F run, stop on fail G go (run tests N run, stop on fail, no print S scope (run, no print) C toggle comment printout + increase speed (less delay) - decrease speed (more delay)(slower) Q quit test scope (run, no print) FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF FFFFFFFFFFFFFFFF space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C toggle comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER VURSNPLMJKFHDECDABUVSTPRMNKLHJEF SIDE 11111111111111121122222222222222 DIRECTION IOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIO all fails O OIO O IO OIO O IO O IO O was lo 0 000000000000000000000000000000 falling v vvvvvvvvvvvvvvvvvvvvvvvvvvvvvv rising ^ ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ was hi 11111111111111111111111111111111 total fails 174, total passes 0 Main menu Mon Jul 27 14:45:05 2015 test file is: tests\m111.tst delay is: 0 trigger is: 1 1 read test file 2 set test delay 3 set test trigger 4 run test 5 output loading test 8 diags 9 exit UUT power is okay Mon Jul 27 14:45:09 2015 space single step O run once (one test, all steps) F run, stop on fail G go (run tests N run, stop on fail, no print S scope (run, no print) C toggle comment printout + increase speed (less delay) - decrease speed (more delay)(slower) Q quit test scope (run, no print) FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C toggle comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER VURSNPLMJKFHDECDABUVSTPRMNKLHJEF SIDE 11111111111111121122222222222222 DIRECTION IOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIO changed: step 67 11100111100111011110011110011110 fail ^ ^^ ^ ^^ ^^^ ^ ^^ ^ ^^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER VURSNPLMJKFHDECDABUVSTPRMNKLHJEF SIDE 11111111111111121122222222222222 DIRECTION IOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIO changed: 1 00 step 68 11100111100111110010011110011110 fail ^ ^^ ^ ^^ ^ ^ ^ ^^ ^ ^^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER VURSNPLMJKFHDECDABUVSTPRMNKLHJEF SIDE 11111111111111121122222222222222 DIRECTION IOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIO changed: 0 11 step 69 11100111100111011110011110011110 fail ^ ^^ ^ ^^ ^^^ ^ ^^ ^ ^^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER VURSNPLMJKFHDECDABUVSTPRMNKLHJEF SIDE 11111111111111121122222222222222 DIRECTION IOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIO changed: 01 0 step 70 11100111100111011101001110011110 fail ^ ^^ ^ ^^ ^^^ ^ ^ ^ ^^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER VURSNPLMJKFHDECDABUVSTPRMNKLHJEF SIDE 11111111111111121122222222222222 DIRECTION IOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIO changed: 10 1 step 71 11100111100111011110011110011110 fail ^ ^^ ^ ^^ ^^^ ^ ^^ ^ ^^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER VURSNPLMJKFHDECDABUVSTPRMNKLHJEF SIDE 11111111111111121122222222222222 DIRECTION IOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIO changed: step 72 11100111100111011110011110011110 fail ^ ^^ ^ ^^ ^^^ ^ ^ ^^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER VURSNPLMJKFHDECDABUVSTPRMNKLHJEF SIDE 11111111111111121122222222222222 DIRECTION IOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIO changed: step 73 11100111100111011110011110011110 fail ^ ^^ ^ ^^ ^^^ ^ ^^ ^ ^^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER VURSNPLMJKFHDECDABUVSTPRMNKLHJEF SIDE 11111111111111121122222222222222 DIRECTION IOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIO changed: 1 00 step 74 11100111100111011110110010011110 fail ^ ^^ ^ ^^ ^^^ ^ ^ ^ ^^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER VURSNPLMJKFHDECDABUVSTPRMNKLHJEF SIDE 11111111111111121122222222222222 DIRECTION IOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIO changed: 0 11 step 75 11100111100111011110011110011110 fail ^ ^^ ^ ^^ ^^^ ^ ^^ ^ ^^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER VURSNPLMJKFHDECDABUVSTPRMNKLHJEF SIDE 11111111111111121122222222222222 DIRECTION IOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIO changed: 01 0 step 76 11100111100111011110011101001110 fail ^ ^^ ^ ^^ ^^^ ^ ^^ ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER VURSNPLMJKFHDECDABUVSTPRMNKLHJEF SIDE 11111111111111121122222222222222 DIRECTION IOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIO changed: 10 1 step 77 11100111100111011110011110011110 fail ^ ^^ ^ ^^ ^^^ ^ ^^ ^ ^^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER VURSNPLMJKFHDECDABUVSTPRMNKLHJEF SIDE 11111111111111121122222222222222 DIRECTION IOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIO changed: step 78 11100111100111011110011110011110 fail ^ ^^ ^ ^^ ^^^ ^ ^^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER VURSNPLMJKFHDECDABUVSTPRMNKLHJEF SIDE 11111111111111121122222222222222 DIRECTION IOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIO changed: step 79 11100111100111011110011110011110 fail ^ ^^ ^ ^^ ^^^ ^ ^^ ^ ^^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER VURSNPLMJKFHDECDABUVSTPRMNKLHJEF SIDE 11111111111111121122222222222222 DIRECTION IOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIO changed: 1 00 step 80 11100111100111011110011110110010 fail ^ ^^ ^ ^^ ^^^ ^ ^^ ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER VURSNPLMJKFHDECDABUVSTPRMNKLHJEF SIDE 11111111111111121122222222222222 DIRECTION IOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIO changed: 0 11 step 81 11100111100111011110011110011110 fail ^ ^^ ^ ^^ ^^^ ^ ^^ ^ ^^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER VURSNPLMJKFHDECDABUVSTPRMNKLHJEF SIDE 11111111111111121122222222222222 DIRECTION IOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIO changed: 0 01 step 82 11100111100111001110011110011101 fail ^ ^^ ^ ^^ ^^ ^ ^^ ^ ^^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER VURSNPLMJKFHDECDABUVSTPRMNKLHJEF SIDE 11111111111111121122222222222222 DIRECTION IOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIO changed: 1 10 step 83 11100111100111011110011110011110 fail ^ ^^ ^ ^^ ^^^ ^ ^^ ^ ^^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER VURSNPLMJKFHDECDABUVSTPRMNKLHJEF SIDE 11111111111111121122222222222222 DIRECTION IOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIO changed: step 84 11100111100111011110011110011110 fail ^ ^^ ^ ^^ ^^^ ^ ^^ ^ ^^ ^ test 43: *** FAIL *************************** 84 steps failed SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER VURSNPLMJKFHDECDABUVSTPRMNKLHJEF SIDE 11111111111111121122222222222222 DIRECTION IOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIO this fail O OIO O IO OIO O IO O IO O all fails O OIO O IO OIO O IO O IO O was hi 11111111111111111111111111111111 rising ^ ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ falling v vvvvvvvvvvvvvvvvvvvvvvvvvvvvvv was lo 0 000000000000000000000000000000 total fails 43, total passes 0 space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C toggle comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER VURSNPLMJKFHDECDABUVSTPRMNKLHJEF SIDE 11111111111111121122222222222222 DIRECTION IOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIO changed: 0 011000011000100001100001100001 step 1 01011000011000100001100001100001 fail ^^ ^ ^^ ^^^ ^ ^^ ^ ^^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER VURSNPLMJKFHDECDABUVSTPRMNKLHJEF SIDE 11111111111111121122222222222222 DIRECTION IOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIO changed: 0 0 0 step 2 01010000011000100001000001000001 fail ^ ^ ^^ ^^^ ^ ^ ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER VURSNPLMJKFHDECDABUVSTPRMNKLHJEF SIDE 11111111111111121122222222222222 DIRECTION IOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIO changed: 1 step 3 11010000011000100001000001000001 fail ^ ^ ^ ^^ ^^^ ^ ^ ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER VURSNPLMJKFHDECDABUVSTPRMNKLHJEF SIDE 11111111111111121122222222222222 DIRECTION IOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIO changed: 0 0 0 step 4 01010000010000000001000001000001 fail ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER VURSNPLMJKFHDECDABUVSTPRMNKLHJEF SIDE 11111111111111121122222222222222 DIRECTION IOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIO changed: step 5 01010000010000000001000001000001 fail ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER VURSNPLMJKFHDECDABUVSTPRMNKLHJEF SIDE 11111111111111121122222222222222 DIRECTION IOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIO changed: 10 1 step 6 01100100010000000001000001000001 fail ^ ^ ^ ^ ^ ^ ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER VURSNPLMJKFHDECDABUVSTPRMNKLHJEF SIDE 11111111111111121122222222222222 DIRECTION IOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIO changed: 01 0 step 7 01010000010000000001000001000001 fail ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER VURSNPLMJKFHDECDABUVSTPRMNKLHJEF SIDE 11111111111111121122222222222222 DIRECTION IOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIO changed: step 8 01010000010000000001000001000001 fail ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER VURSNPLMJKFHDECDABUVSTPRMNKLHJEF SIDE 11111111111111121122222222222222 DIRECTION IOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIO changed: 1 step 9 01011000010000000001000001000001 fail ^ ^ ^ ^ ^ ^ ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER VURSNPLMJKFHDECDABUVSTPRMNKLHJEF SIDE 11111111111111121122222222222222 DIRECTION IOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIO changed: 0 step 10 01010000010000000001000001000001 fail ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER VURSNPLMJKFHDECDABUVSTPRMNKLHJEF SIDE 11111111111111121122222222222222 DIRECTION IOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIO changed: step 11 01010000010000000001000001000001 fail ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER VURSNPLMJKFHDECDABUVSTPRMNKLHJEF SIDE 11111111111111121122222222222222 DIRECTION IOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIO changed: 11 step 12 01010011010000000001000001000001 fail ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER VURSNPLMJKFHDECDABUVSTPRMNKLHJEF SIDE 11111111111111121122222222222222 DIRECTION IOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIO changed: 00 step 13 01010000010000000001000001000001 fail ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER VURSNPLMJKFHDECDABUVSTPRMNKLHJEF SIDE 11111111111111121122222222222222 DIRECTION IOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIO changed: step 14 01010000010000000001000001000001 fail ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER VURSNPLMJKFHDECDABUVSTPRMNKLHJEF SIDE 11111111111111121122222222222222 DIRECTION IOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIO changed: 10 step 15 01010000100000000001000001000001 fail ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER VURSNPLMJKFHDECDABUVSTPRMNKLHJEF SIDE 11111111111111121122222222222222 DIRECTION IOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIO changed: 01 step 16 01010000010000000001000001000001 fail ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER VURSNPLMJKFHDECDABUVSTPRMNKLHJEF SIDE 11111111111111121122222222222222 DIRECTION IOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIO changed: step 17 01010000010000000001000001000001 fail ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER VURSNPLMJKFHDECDABUVSTPRMNKLHJEF SIDE 11111111111111121122222222222222 DIRECTION IOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIO changed: 1 step 18 01010000011000000001000001000001 fail ^ ^ ^ ^ ^ ^ ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER VURSNPLMJKFHDECDABUVSTPRMNKLHJEF SIDE 11111111111111121122222222222222 DIRECTION IOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIO changed: 0 step 19 01010000010000000001000001000001 fail ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER VURSNPLMJKFHDECDABUVSTPRMNKLHJEF SIDE 11111111111111121122222222222222 DIRECTION IOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIO changed: step 20 01010000010000000001000001000001 fail ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER VURSNPLMJKFHDECDABUVSTPRMNKLHJEF SIDE 11111111111111121122222222222222 DIRECTION IOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIO changed: 1 step 21 01010000010010000001000001000001 fail ^ ^ ^ ^ ^ ^ ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER VURSNPLMJKFHDECDABUVSTPRMNKLHJEF SIDE 11111111111111121122222222222222 DIRECTION IOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIO changed: 0 step 22 01010000010000000001000001000001 fail ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER VURSNPLMJKFHDECDABUVSTPRMNKLHJEF SIDE 11111111111111121122222222222222 DIRECTION IOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIO changed: step 23 01010000010000000001000001000001 fail ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER VURSNPLMJKFHDECDABUVSTPRMNKLHJEF SIDE 11111111111111121122222222222222 DIRECTION IOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIO changed: 1 step 24 01010000010000100001000001000001 fail ^ ^ ^ ^ ^ ^ ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER VURSNPLMJKFHDECDABUVSTPRMNKLHJEF SIDE 11111111111111121122222222222222 DIRECTION IOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIO changed: 0 step 25 01010000010000000001000001000001 fail ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER VURSNPLMJKFHDECDABUVSTPRMNKLHJEF SIDE 11111111111111121122222222222222 DIRECTION IOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIO changed: step 26 01010000010000000001000001000001 fail ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER VURSNPLMJKFHDECDABUVSTPRMNKLHJEF SIDE 11111111111111121122222222222222 DIRECTION IOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIO changed: 1 step 27 01010000010000001001000001000001 fail ^ ^ ^ ^ ^ ^ ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER VURSNPLMJKFHDECDABUVSTPRMNKLHJEF SIDE 11111111111111121122222222222222 DIRECTION IOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIO changed: 0 step 28 01010000010000000001000001000001 fail ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER VURSNPLMJKFHDECDABUVSTPRMNKLHJEF SIDE 11111111111111121122222222222222 DIRECTION IOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIO changed: step 29 01010000010000000001000001000001 fail ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER VURSNPLMJKFHDECDABUVSTPRMNKLHJEF SIDE 11111111111111121122222222222222 DIRECTION IOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIO changed: 10 1 step 30 01010000010000000010010001000001 fail ^ ^ ^ ^ ^ ^ ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER VURSNPLMJKFHDECDABUVSTPRMNKLHJEF SIDE 11111111111111121122222222222222 DIRECTION IOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIO changed: 01 0 step 31 01010000010000000001000001000001 fail ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER VURSNPLMJKFHDECDABUVSTPRMNKLHJEF SIDE 11111111111111121122222222222222 DIRECTION IOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIO changed: step 32 01010000010000000001000001000001 fail ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER VURSNPLMJKFHDECDABUVSTPRMNKLHJEF SIDE 11111111111111121122222222222222 DIRECTION IOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIO changed: 1 step 33 01010000010000000001100001000001 fail ^ ^ ^ ^ ^ ^ ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER VURSNPLMJKFHDECDABUVSTPRMNKLHJEF SIDE 11111111111111121122222222222222 DIRECTION IOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIO changed: 0 step 34 01010000010000000001000001000001 fail ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER VURSNPLMJKFHDECDABUVSTPRMNKLHJEF SIDE 11111111111111121122222222222222 DIRECTION IOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIO changed: step 35 01010000010000000001000001000001 fail ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER VURSNPLMJKFHDECDABUVSTPRMNKLHJEF SIDE 11111111111111121122222222222222 DIRECTION IOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIO changed: 11 step 36 01010000010000000001001101000001 fail ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER VURSNPLMJKFHDECDABUVSTPRMNKLHJEF SIDE 11111111111111121122222222222222 DIRECTION IOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIO changed: 00 step 37 01010000010000000001000001000001 fail ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER VURSNPLMJKFHDECDABUVSTPRMNKLHJEF SIDE 11111111111111121122222222222222 DIRECTION IOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIO changed: step 38 01010000010000000001000001000001 fail ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER VURSNPLMJKFHDECDABUVSTPRMNKLHJEF SIDE 11111111111111121122222222222222 DIRECTION IOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIO changed: 10 step 39 01010000010000000001000010000001 fail ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER VURSNPLMJKFHDECDABUVSTPRMNKLHJEF SIDE 11111111111111121122222222222222 DIRECTION IOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIO changed: 01 step 40 01010000010000000001000001000001 fail ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER VURSNPLMJKFHDECDABUVSTPRMNKLHJEF SIDE 11111111111111121122222222222222 DIRECTION IOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIO changed: step 41 01010000010000000001000001000001 fail ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER VURSNPLMJKFHDECDABUVSTPRMNKLHJEF SIDE 11111111111111121122222222222222 DIRECTION IOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIO changed: 1 step 42 01010000010000000001000001100001 fail ^ ^ ^ ^ ^ ^ ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER VURSNPLMJKFHDECDABUVSTPRMNKLHJEF SIDE 11111111111111121122222222222222 DIRECTION IOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIO changed: 0 step 43 01010000010000000001000001000001 fail ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER VURSNPLMJKFHDECDABUVSTPRMNKLHJEF SIDE 11111111111111121122222222222222 DIRECTION IOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIO changed: step 44 01010000010000000001000001000001 fail ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER VURSNPLMJKFHDECDABUVSTPRMNKLHJEF SIDE 11111111111111121122222222222222 DIRECTION IOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIO changed: 1 step 45 01010000010000000001000001001001 fail ^ ^ ^ ^ ^ ^ ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER VURSNPLMJKFHDECDABUVSTPRMNKLHJEF SIDE 11111111111111121122222222222222 DIRECTION IOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIO changed: 0 step 46 01010000010000000001000001000001 fail ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER VURSNPLMJKFHDECDABUVSTPRMNKLHJEF SIDE 11111111111111121122222222222222 DIRECTION IOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIO changed: step 47 01010000010000000001000001000001 fail ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER VURSNPLMJKFHDECDABUVSTPRMNKLHJEF SIDE 11111111111111121122222222222222 DIRECTION IOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIO changed: 10 step 48 01010000010000000001000001000010 fail ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER VURSNPLMJKFHDECDABUVSTPRMNKLHJEF SIDE 11111111111111121122222222222222 DIRECTION IOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIO changed: 01 step 49 01010000010000000001000001000001 fail ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER VURSNPLMJKFHDECDABUVSTPRMNKLHJEF SIDE 11111111111111121122222222222222 DIRECTION IOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIO changed: step 50 01010000010000000001000001000001 fail ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER VURSNPLMJKFHDECDABUVSTPRMNKLHJEF SIDE 11111111111111121122222222222222 DIRECTION IOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIO changed: 1 10 11110 111 11110 11110 11110 step 51 11100111100111011110011110011110 fail ^ ^^ ^ ^^ ^^^ ^ ^^ ^ ^^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER VURSNPLMJKFHDECDABUVSTPRMNKLHJEF SIDE 11111111111111121122222222222222 DIRECTION IOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIO changed: 0 step 52 01100111100111011110011110011110 fail ^^ ^ ^^ ^^^ ^ ^^ ^ ^^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER VURSNPLMJKFHDECDABUVSTPRMNKLHJEF SIDE 11111111111111121122222222222222 DIRECTION IOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIO changed: 1 step 53 11100111100111011110011110011110 fail ^ ^^ ^ ^^ ^^^ ^ ^^ ^ ^^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER VURSNPLMJKFHDECDABUVSTPRMNKLHJEF SIDE 11111111111111121122222222222222 DIRECTION IOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIO changed: 0 0 step 54 11000011100111011110011110011110 fail ^ ^^ ^ ^^ ^^^ ^ ^^ ^ ^^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER VURSNPLMJKFHDECDABUVSTPRMNKLHJEF SIDE 11111111111111121122222222222222 DIRECTION IOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIO changed: 1 1 step 55 11100111100111011110011110011110 fail ^ ^^ ^ ^^ ^^^ ^ ^^ ^ ^^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER VURSNPLMJKFHDECDABUVSTPRMNKLHJEF SIDE 11111111111111121122222222222222 DIRECTION IOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIO changed: step 56 11100111100111011110011110011110 fail ^ ^ ^^ ^^^ ^ ^^ ^ ^^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER VURSNPLMJKFHDECDABUVSTPRMNKLHJEF SIDE 11111111111111121122222222222222 DIRECTION IOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIO changed: step 57 11100111100111011110011110011110 fail ^ ^^ ^ ^^ ^^^ ^ ^^ ^ ^^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER VURSNPLMJKFHDECDABUVSTPRMNKLHJEF SIDE 11111111111111121122222222222222 DIRECTION IOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIO changed: 1 00 step 58 11101100100111011110011110011110 fail ^ ^ ^ ^^ ^^^ ^ ^^ ^ ^^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER VURSNPLMJKFHDECDABUVSTPRMNKLHJEF SIDE 11111111111111121122222222222222 DIRECTION IOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIO changed: 0 11 step 59 11100111100111011110011110011110 fail ^ ^^ ^ ^^ ^^^ ^ ^^ ^ ^^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER VURSNPLMJKFHDECDABUVSTPRMNKLHJEF SIDE 11111111111111121122222222222222 DIRECTION IOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIO changed: 01 0 step 60 11100111010011011110011110011110 fail ^ ^^ ^ ^ ^^^ ^ ^^ ^ ^^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER VURSNPLMJKFHDECDABUVSTPRMNKLHJEF SIDE 11111111111111121122222222222222 DIRECTION IOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIO changed: 10 1 step 61 11100111100111011110011110011110 fail ^ ^^ ^ ^^ ^^^ ^ ^^ ^ ^^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER VURSNPLMJKFHDECDABUVSTPRMNKLHJEF SIDE 11111111111111121122222222222222 DIRECTION IOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIO changed: step 62 11100111100111011110011110011110 fail ^ ^^ ^ ^^^ ^ ^^ ^ ^^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER VURSNPLMJKFHDECDABUVSTPRMNKLHJEF SIDE 11111111111111121122222222222222 DIRECTION IOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIO changed: step 63 11100111100111011110011110011110 fail ^ ^^ ^ ^^ ^^^ ^ ^^ ^ ^^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER VURSNPLMJKFHDECDABUVSTPRMNKLHJEF SIDE 11111111111111121122222222222222 DIRECTION IOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIO changed: 1 00 step 64 11100111101100011110011110011110 fail ^ ^^ ^ ^ ^^^ ^ ^^ ^ ^^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER VURSNPLMJKFHDECDABUVSTPRMNKLHJEF SIDE 11111111111111121122222222222222 DIRECTION IOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIO changed: 0 11 step 65 11100111100111011110011110011110 fail ^ ^^ ^ ^^ ^^^ ^ ^^ ^ ^^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER VURSNPLMJKFHDECDABUVSTPRMNKLHJEF SIDE 11111111111111121122222222222222 DIRECTION IOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIO changed: step 66 11100111100111011110011110011110 fail ^ ^^ ^ ^^ ^ ^ ^^ ^ ^^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER VURSNPLMJKFHDECDABUVSTPRMNKLHJEF SIDE 11111111111111121122222222222222 DIRECTION IOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIO changed: step 67 11100111100111011110011110011110 fail ^ ^^ ^ ^^ ^^^ ^ ^^ ^ ^^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER VURSNPLMJKFHDECDABUVSTPRMNKLHJEF SIDE 11111111111111121122222222222222 DIRECTION IOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIO changed: 1 00 step 68 11100111100111110010011110011110 fail ^ ^^ ^ ^^ ^ ^ ^ ^^ ^ ^^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER VURSNPLMJKFHDECDABUVSTPRMNKLHJEF SIDE 11111111111111121122222222222222 DIRECTION IOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIO changed: 0 11 step 69 11100111100111011110011110011110 fail ^ ^^ ^ ^^ ^^^ ^ ^^ ^ ^^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER VURSNPLMJKFHDECDABUVSTPRMNKLHJEF SIDE 11111111111111121122222222222222 DIRECTION IOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIO changed: 01 0 step 70 11100111100111011101001110011110 fail ^ ^^ ^ ^^ ^^^ ^ ^ ^ ^^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER VURSNPLMJKFHDECDABUVSTPRMNKLHJEF SIDE 11111111111111121122222222222222 DIRECTION IOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIO changed: 10 1 step 71 11100111100111011110011110011110 fail ^ ^^ ^ ^^ ^^^ ^ ^^ ^ ^^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER VURSNPLMJKFHDECDABUVSTPRMNKLHJEF SIDE 11111111111111121122222222222222 DIRECTION IOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIO changed: step 72 11100111100111011110011110011110 fail ^ ^^ ^ ^^ ^^^ ^ ^ ^^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER VURSNPLMJKFHDECDABUVSTPRMNKLHJEF SIDE 11111111111111121122222222222222 DIRECTION IOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIO changed: step 73 11100111100111011110011110011110 fail ^ ^^ ^ ^^ ^^^ ^ ^^ ^ ^^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER VURSNPLMJKFHDECDABUVSTPRMNKLHJEF SIDE 11111111111111121122222222222222 DIRECTION IOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIO changed: 1 00 step 74 11100111100111011110110010011110 fail ^ ^^ ^ ^^ ^^^ ^ ^ ^ ^^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER VURSNPLMJKFHDECDABUVSTPRMNKLHJEF SIDE 11111111111111121122222222222222 DIRECTION IOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIO changed: 0 11 step 75 11100111100111011110011110011110 fail ^ ^^ ^ ^^ ^^^ ^ ^^ ^ ^^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER VURSNPLMJKFHDECDABUVSTPRMNKLHJEF SIDE 11111111111111121122222222222222 DIRECTION IOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIO changed: 01 0 step 76 11100111100111011110011101001110 fail ^ ^^ ^ ^^ ^^^ ^ ^^ ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER VURSNPLMJKFHDECDABUVSTPRMNKLHJEF SIDE 11111111111111121122222222222222 DIRECTION IOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIO changed: 10 1 step 77 11100111100111011110011110011110 fail ^ ^^ ^ ^^ ^^^ ^ ^^ ^ ^^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER VURSNPLMJKFHDECDABUVSTPRMNKLHJEF SIDE 11111111111111121122222222222222 DIRECTION IOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIO changed: step 78 11100111100111011110011110011110 fail ^ ^^ ^ ^^ ^^^ ^ ^^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER VURSNPLMJKFHDECDABUVSTPRMNKLHJEF SIDE 11111111111111121122222222222222 DIRECTION IOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIO changed: step 79 11100111100111011110011110011110 fail ^ ^^ ^ ^^ ^^^ ^ ^^ ^ ^^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER VURSNPLMJKFHDECDABUVSTPRMNKLHJEF SIDE 11111111111111121122222222222222 DIRECTION IOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIO changed: 1 00 step 80 11100111100111011110011110110010 fail ^ ^^ ^ ^^ ^^^ ^ ^^ ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER VURSNPLMJKFHDECDABUVSTPRMNKLHJEF SIDE 11111111111111121122222222222222 DIRECTION IOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIO changed: 0 11 step 81 11100111100111011110011110011110 fail ^ ^^ ^ ^^ ^^^ ^ ^^ ^ ^^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER VURSNPLMJKFHDECDABUVSTPRMNKLHJEF SIDE 11111111111111121122222222222222 DIRECTION IOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIO changed: 0 01 step 82 11100111100111001110011110011101 fail ^ ^^ ^ ^^ ^^ ^ ^^ ^ ^^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER VURSNPLMJKFHDECDABUVSTPRMNKLHJEF SIDE 11111111111111121122222222222222 DIRECTION IOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIO changed: 1 10 step 83 11100111100111011110011110011110 fail ^ ^^ ^ ^^ ^^^ ^ ^^ ^ ^^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER VURSNPLMJKFHDECDABUVSTPRMNKLHJEF SIDE 11111111111111121122222222222222 DIRECTION IOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIO changed: step 84 11100111100111011110011110011110 fail ^ ^^ ^ ^^ ^^^ ^ ^^ ^ ^^ ^ test 44: *** FAIL *************************** 84 steps failed SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER VURSNPLMJKFHDECDABUVSTPRMNKLHJEF SIDE 11111111111111121122222222222222 DIRECTION IOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIO this fail O OIO O IO OIO O IO O IO O all fails O OIO O IO OIO O IO O IO O was hi 11111111111111111111111111111111 rising ^ ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ falling v vvvvvvvvvvvvvvvvvvvvvvvvvvvvvv was lo 0 000000000000000000000000000000 total fails 44, total passes 0 space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C toggle comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER VURSNPLMJKFHDECDABUVSTPRMNKLHJEF SIDE 11111111111111121122222222222222 DIRECTION IOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIO all fails O OIO O IO OIO O IO O IO O was lo 0 000000000000000000000000000000 falling v vvvvvvvvvvvvvvvvvvvvvvvvvvvvvv rising ^ ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ was hi 11111111111111111111111111111111 total fails 44, total passes 0 Main menu Mon Jul 27 14:46:10 2015 test file is: tests\m111.tst delay is: 0 trigger is: 1 1 read test file 2 set test delay 3 set test trigger 4 run test 5 output loading test 8 diags 9 exit exiting tester- PDP8 card tester via printer port version 0.85 June 4, 2015 mapping[] is verified Main menu Mon Jul 27 14:46:18 2015 test file is: delay is: 0 trigger is: 1 1 read test file 2 set test delay 3 set test trigger 4 run test 5 output loading test 8 diags 9 exit Enter test file name? trying to open test file: tests\m111.tst reading test file: tests\m111.tst comment: M111 PCB REV C SCHEMATIC REV A 16 INVERTERS USING 7400s pins: PINS pins: 1 I AV1 E4-9 pins: 2 O AU1 E4-8 pins: 3 I AR1 E4-12 pins: 4 O AS1 E4-11 pins: 5 I AN1 E3-10 pins: 6 O AP1 E3-8 pins: 7 I AL1 E3-12 pins: 8 O AM1 E3-11 pins: 9 I AJ1 E1-9 pins: 10 O AK1 E1-8 pins: 11 I AF1 E1-12 pins: 12 O AH1 E1-11 pins: 13 I AD1 E2-9 pins: 14 O AE1 E2-8 pins: 15 I AC1 E2-5 pins: 16 O AD2 E2-6 pins: 17 I AA1 E2-12 pins: 18 O AB1 E2-11 pins: 19 I AU2 E4-1 pins: 20 O AV2 E4-2 pins: 21 I AS2 E4-5 pins: 22 O AT2 E4-6 pins: 23 I AP2 E3-1 pins: 24 O AR2 E3-2 pins: 25 I AM2 E3-5 pins: 26 O AN2 E3-6 pins: 27 I AK2 E1-1 pins: 28 O AL2 E1-3 pins: 29 I AH2 E1-5 pins: 30 O AJ2 E1-6 pins: 31 I AE2 E2-1 pins: 32 O AF2 E2-3 pins: direction: IOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIO test 1: 01010101010101010101010101010101 test 2: 01 test 3: 10 test 4: 01 test 5: 01 test 6: 10 test 7: 01 test 8: 01 test 9: 10 test 10: 01 test 11: 01 test 12: 10 test 13: 01 test 14: 01 test 15: 10 test 16: 01 test 17: 01 test 18: 10 test 19: 01 test 20: 01 test 21: 10 test 22: 01 test 23: 01 test 24: 10 test 25: 01 test 26: 01 test 27: 10 test 28: 01 test 29: 01 test 30: 10 test 31: 01 test 32: 01 test 33: 10 test 34: 01 test 35: 01 test 36: 10 test 37: 01 test 38: 01 test 39: 10 test 40: 01 test 41: 01 test 42: 10 test 43: 01 test 44: 01 test 45: 10 test 46: 01 test 47: 01 test 48: 10 test 49: 01 test 50: 01010101010101010101010101010101 test 51: 10101010101010101010101010101010 test 52: 01 test 53: 10 test 54: 01 test 55: 10 test 56: 01 test 57: 10 test 58: 01 test 59: 10 test 60: 01 test 61: 10 test 62: 01 test 63: 10 test 64: 01 test 65: 10 test 66: 01 test 67: 10 test 68: 01 test 69: 10 test 70: 01 test 71: 10 test 72: 01 test 73: 10 test 74: 01 test 75: 10 test 76: 01 test 77: 10 test 78: 01 test 79: 10 test 80: 01 test 81: 10 test 82: 01 test 83: 10 test 84: 10101010101010101010101010101010 end: END summary column 1: offset 2, mask 0x4000 column 2: offset 2, mask 0x8000 column 3: offset 1, mask 0x0400 column 4: offset 1, mask 0x0200 column 5: offset 1, mask 0x1000 column 6: offset 1, mask 0x0800 column 7: offset 1, mask 0x4000 column 8: offset 1, mask 0x2000 column 9: offset 0, mask 0x0100 column 10: offset 1, mask 0x8000 column 11: offset 0, mask 0x0400 column 12: offset 0, mask 0x0200 column 13: offset 0, mask 0x1000 column 14: offset 0, mask 0x0800 column 15: offset 0, mask 0x2000 column 16: offset 0, mask 0x0010 column 17: offset 0, mask 0x8000 column 18: offset 0, mask 0x4000 column 19: offset 2, mask 0x0001 column 20: offset 2, mask 0x0002 column 21: offset 1, mask 0x0040 column 22: offset 1, mask 0x0080 column 23: offset 1, mask 0x0010 column 24: offset 1, mask 0x0020 column 25: offset 1, mask 0x0004 column 26: offset 1, mask 0x0008 column 27: offset 1, mask 0x0001 column 28: offset 1, mask 0x0002 column 29: offset 0, mask 0x0002 column 30: offset 0, mask 0x0001 column 31: offset 0, mask 0x0008 column 32: offset 0, mask 0x0004 direction bits (1=input) 0x4AF5 0xABAA 0xBFFA 0xFFFF 0xF0FF pullup bits (1=pullup) 0x0000 0x0000 0x0000 0x0000 0x0000 test step out_data dont care 1: 0x4A15 0xAAAA 0x8002 0x0000 0x0000 2: 0x4A15 0xAAAA 0x8002 0x0000 0x0000 3: 0x4A15 0xAAAA 0x4002 0x0000 0x0000 4: 0x4A15 0xAAAA 0x8002 0x0000 0x0000 5: 0x4A15 0xAAAA 0x8002 0x0000 0x0000 6: 0x4A15 0xACAA 0x8002 0x0000 0x0000 7: 0x4A15 0xAAAA 0x8002 0x0000 0x0000 8: 0x4A15 0xAAAA 0x8002 0x0000 0x0000 9: 0x4A15 0xB2AA 0x8002 0x0000 0x0000 10: 0x4A15 0xAAAA 0x8002 0x0000 0x0000 11: 0x4A15 0xAAAA 0x8002 0x0000 0x0000 12: 0x4A15 0xCAAA 0x8002 0x0000 0x0000 13: 0x4A15 0xAAAA 0x8002 0x0000 0x0000 14: 0x4A15 0xAAAA 0x8002 0x0000 0x0000 15: 0x4B15 0x2AAA 0x8002 0x0000 0x0000 16: 0x4A15 0xAAAA 0x8002 0x0000 0x0000 17: 0x4A15 0xAAAA 0x8002 0x0000 0x0000 18: 0x4C15 0xAAAA 0x8002 0x0000 0x0000 19: 0x4A15 0xAAAA 0x8002 0x0000 0x0000 20: 0x4A15 0xAAAA 0x8002 0x0000 0x0000 21: 0x5215 0xAAAA 0x8002 0x0000 0x0000 22: 0x4A15 0xAAAA 0x8002 0x0000 0x0000 23: 0x4A15 0xAAAA 0x8002 0x0000 0x0000 24: 0x6A05 0xAAAA 0x8002 0x0000 0x0000 25: 0x4A15 0xAAAA 0x8002 0x0000 0x0000 26: 0x4A15 0xAAAA 0x8002 0x0000 0x0000 27: 0x8A15 0xAAAA 0x8002 0x0000 0x0000 28: 0x4A15 0xAAAA 0x8002 0x0000 0x0000 29: 0x4A15 0xAAAA 0x8002 0x0000 0x0000 30: 0x4A15 0xAAAA 0x8001 0x0000 0x0000 31: 0x4A15 0xAAAA 0x8002 0x0000 0x0000 32: 0x4A15 0xAAAA 0x8002 0x0000 0x0000 33: 0x4A15 0xAA6A 0x8002 0x0000 0x0000 34: 0x4A15 0xAAAA 0x8002 0x0000 0x0000 35: 0x4A15 0xAAAA 0x8002 0x0000 0x0000 36: 0x4A15 0xAA9A 0x8002 0x0000 0x0000 37: 0x4A15 0xAAAA 0x8002 0x0000 0x0000 38: 0x4A15 0xAAAA 0x8002 0x0000 0x0000 39: 0x4A15 0xAAA6 0x8002 0x0000 0x0000 40: 0x4A15 0xAAAA 0x8002 0x0000 0x0000 41: 0x4A15 0xAAAA 0x8002 0x0000 0x0000 42: 0x4A15 0xAAA9 0x8002 0x0000 0x0000 43: 0x4A15 0xAAAA 0x8002 0x0000 0x0000 44: 0x4A15 0xAAAA 0x8002 0x0000 0x0000 45: 0x4A16 0xAAAA 0x8002 0x0000 0x0000 46: 0x4A15 0xAAAA 0x8002 0x0000 0x0000 47: 0x4A15 0xAAAA 0x8002 0x0000 0x0000 48: 0x4A19 0xAAAA 0x8002 0x0000 0x0000 49: 0x4A15 0xAAAA 0x8002 0x0000 0x0000 50: 0x4A15 0xAAAA 0x8002 0x0000 0x0000 51: 0xB50A 0x5455 0x4001 0x0000 0x0000 52: 0xB50A 0x5455 0x8001 0x0000 0x0000 53: 0xB50A 0x5455 0x4001 0x0000 0x0000 54: 0xB50A 0x5255 0x4001 0x0000 0x0000 55: 0xB50A 0x5455 0x4001 0x0000 0x0000 56: 0xB50A 0x4C55 0x4001 0x0000 0x0000 57: 0xB50A 0x5455 0x4001 0x0000 0x0000 58: 0xB50A 0x3455 0x4001 0x0000 0x0000 59: 0xB50A 0x5455 0x4001 0x0000 0x0000 60: 0xB40A 0xD455 0x4001 0x0000 0x0000 61: 0xB50A 0x5455 0x4001 0x0000 0x0000 62: 0xB30A 0x5455 0x4001 0x0000 0x0000 63: 0xB50A 0x5455 0x4001 0x0000 0x0000 64: 0xAD0A 0x5455 0x4001 0x0000 0x0000 65: 0xB50A 0x5455 0x4001 0x0000 0x0000 66: 0x951A 0x5455 0x4001 0x0000 0x0000 67: 0xB50A 0x5455 0x4001 0x0000 0x0000 68: 0x750A 0x5455 0x4001 0x0000 0x0000 69: 0xB50A 0x5455 0x4001 0x0000 0x0000 70: 0xB50A 0x5455 0x4002 0x0000 0x0000 71: 0xB50A 0x5455 0x4001 0x0000 0x0000 72: 0xB50A 0x5495 0x4001 0x0000 0x0000 73: 0xB50A 0x5455 0x4001 0x0000 0x0000 74: 0xB50A 0x5465 0x4001 0x0000 0x0000 75: 0xB50A 0x5455 0x4001 0x0000 0x0000 76: 0xB50A 0x5459 0x4001 0x0000 0x0000 77: 0xB50A 0x5455 0x4001 0x0000 0x0000 78: 0xB50A 0x5456 0x4001 0x0000 0x0000 79: 0xB50A 0x5455 0x4001 0x0000 0x0000 80: 0xB509 0x5455 0x4001 0x0000 0x0000 81: 0xB50A 0x5455 0x4001 0x0000 0x0000 82: 0xB506 0x5455 0x4001 0x0000 0x0000 83: 0xB50A 0x5455 0x4001 0x0000 0x0000 84: 0xB50A 0x5455 0x4001 0x0000 0x0000 PINs used (in edge connector order) (G=ground,P=power) SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBB LETTER ABCDEFHJKLMNPRSTUVABCDEFHJKLMNPRSTUVABCDEFHJKLMNPRSTUVABCDEFHJKLMNPRSTUV SIDE 111111111111111111222222222222222222111111111111111111222222222222222222 USAGE IOIIOIOIOIOIOIOGOIP GOIOIOIOIOIOIOIO G P G UUT has 16 inputs UUT has 16 outputs contains 32 pins/columns 34 pins are not used contains 84 'test steps' M111 PCB REV C SCHEMATIC REV A 16 INVERTERS USING 7400s PINS Main menu Mon Jul 27 14:46:23 2015 test file is: tests\m111.tst delay is: 0 trigger is: 1 1 read test file 2 set test delay 3 set test trigger 4 run test 5 output loading test 8 diags 9 exit UUT power is okay Mon Jul 27 14:46:26 2015 space single step O run once (one test, all steps) F run, stop on fail G go (run tests N run, stop on fail, no print S scope (run, no print) C toggle comment printout + increase speed (less delay) - decrease speed (more delay)(slower) Q quit test scope (run, no print) FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C toggle comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER VURSNPLMJKFHDECDABUVSTPRMNKLHJEF SIDE 11111111111111121122222222222222 DIRECTION IOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIO changed: 0 step 19 01010000010000000001000001000001 fail ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER VURSNPLMJKFHDECDABUVSTPRMNKLHJEF SIDE 11111111111111121122222222222222 DIRECTION IOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIO changed: step 20 01010000010000000001000001000001 fail ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER VURSNPLMJKFHDECDABUVSTPRMNKLHJEF SIDE 11111111111111121122222222222222 DIRECTION IOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIO changed: 1 step 21 01010000010010000001000001000001 fail ^ ^ ^ ^ ^ ^ ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER VURSNPLMJKFHDECDABUVSTPRMNKLHJEF SIDE 11111111111111121122222222222222 DIRECTION IOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIO changed: 0 step 22 01010000010000000001000001000001 fail ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER VURSNPLMJKFHDECDABUVSTPRMNKLHJEF SIDE 11111111111111121122222222222222 DIRECTION IOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIO changed: step 23 01010000010000000001000001000001 fail ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER VURSNPLMJKFHDECDABUVSTPRMNKLHJEF SIDE 11111111111111121122222222222222 DIRECTION IOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIO changed: 1 step 24 01010000010000100001000001000001 fail ^ ^ ^ ^ ^ ^ ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER VURSNPLMJKFHDECDABUVSTPRMNKLHJEF SIDE 11111111111111121122222222222222 DIRECTION IOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIO changed: 0 step 25 01010000010000000001000001000001 fail ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER VURSNPLMJKFHDECDABUVSTPRMNKLHJEF SIDE 11111111111111121122222222222222 DIRECTION IOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIO changed: step 26 01010000010000000001000001000001 fail ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER VURSNPLMJKFHDECDABUVSTPRMNKLHJEF SIDE 11111111111111121122222222222222 DIRECTION IOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIO changed: 1 step 27 01010000010000001001000001000001 fail ^ ^ ^ ^ ^ ^ ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER VURSNPLMJKFHDECDABUVSTPRMNKLHJEF SIDE 11111111111111121122222222222222 DIRECTION IOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIO changed: 0 step 28 01010000010000000001000001000001 fail ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER VURSNPLMJKFHDECDABUVSTPRMNKLHJEF SIDE 11111111111111121122222222222222 DIRECTION IOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIO changed: step 29 01010000010000000001000001000001 fail ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER VURSNPLMJKFHDECDABUVSTPRMNKLHJEF SIDE 11111111111111121122222222222222 DIRECTION IOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIO changed: 10 1 step 30 01010000010000000010010001000001 fail ^ ^ ^ ^ ^ ^ ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER VURSNPLMJKFHDECDABUVSTPRMNKLHJEF SIDE 11111111111111121122222222222222 DIRECTION IOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIO changed: 01 0 step 31 01010000010000000001000001000001 fail ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER VURSNPLMJKFHDECDABUVSTPRMNKLHJEF SIDE 11111111111111121122222222222222 DIRECTION IOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIO changed: step 32 01010000010000000001000001000001 fail ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER VURSNPLMJKFHDECDABUVSTPRMNKLHJEF SIDE 11111111111111121122222222222222 DIRECTION IOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIO changed: 1 step 33 01010000010000000001100001000001 fail ^ ^ ^ ^ ^ ^ ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER VURSNPLMJKFHDECDABUVSTPRMNKLHJEF SIDE 11111111111111121122222222222222 DIRECTION IOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIO changed: 0 step 34 01010000010000000001000001000001 fail ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER VURSNPLMJKFHDECDABUVSTPRMNKLHJEF SIDE 11111111111111121122222222222222 DIRECTION IOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIO changed: step 35 01010000010000000001000001000001 fail ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER VURSNPLMJKFHDECDABUVSTPRMNKLHJEF SIDE 11111111111111121122222222222222 DIRECTION IOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIO changed: 11 step 36 01010000010000000001001101000001 fail ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER VURSNPLMJKFHDECDABUVSTPRMNKLHJEF SIDE 11111111111111121122222222222222 DIRECTION IOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIO changed: 00 step 37 01010000010000000001000001000001 fail ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER VURSNPLMJKFHDECDABUVSTPRMNKLHJEF SIDE 11111111111111121122222222222222 DIRECTION IOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIO changed: step 38 01010000010000000001000001000001 fail ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER VURSNPLMJKFHDECDABUVSTPRMNKLHJEF SIDE 11111111111111121122222222222222 DIRECTION IOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIO changed: 10 step 39 01010000010000000001000010000001 fail ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER VURSNPLMJKFHDECDABUVSTPRMNKLHJEF SIDE 11111111111111121122222222222222 DIRECTION IOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIO changed: 01 step 40 01010000010000000001000001000001 fail ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER VURSNPLMJKFHDECDABUVSTPRMNKLHJEF SIDE 11111111111111121122222222222222 DIRECTION IOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIO changed: step 41 01010000010000000001000001000001 fail ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER VURSNPLMJKFHDECDABUVSTPRMNKLHJEF SIDE 11111111111111121122222222222222 DIRECTION IOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIO changed: 1 step 42 01010000010000000001000001100001 fail ^ ^ ^ ^ ^ ^ ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER VURSNPLMJKFHDECDABUVSTPRMNKLHJEF SIDE 11111111111111121122222222222222 DIRECTION IOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIO changed: 0 step 43 01010000010000000001000001000001 fail ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER VURSNPLMJKFHDECDABUVSTPRMNKLHJEF SIDE 11111111111111121122222222222222 DIRECTION IOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIO changed: step 44 01010000010000000001000001000001 fail ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER VURSNPLMJKFHDECDABUVSTPRMNKLHJEF SIDE 11111111111111121122222222222222 DIRECTION IOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIO changed: 1 step 45 01010000010000000001000001001001 fail ^ ^ ^ ^ ^ ^ ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER VURSNPLMJKFHDECDABUVSTPRMNKLHJEF SIDE 11111111111111121122222222222222 DIRECTION IOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIO changed: 0 step 46 01010000010000000001000001000001 fail ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER VURSNPLMJKFHDECDABUVSTPRMNKLHJEF SIDE 11111111111111121122222222222222 DIRECTION IOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIO changed: step 47 01010000010000000001000001000001 fail ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER VURSNPLMJKFHDECDABUVSTPRMNKLHJEF SIDE 11111111111111121122222222222222 DIRECTION IOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIO changed: 10 step 48 01010000010000000001000001000010 fail ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER VURSNPLMJKFHDECDABUVSTPRMNKLHJEF SIDE 11111111111111121122222222222222 DIRECTION IOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIO changed: 01 step 49 01010000010000000001000001000001 fail ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER VURSNPLMJKFHDECDABUVSTPRMNKLHJEF SIDE 11111111111111121122222222222222 DIRECTION IOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIO changed: step 50 01010000010000000001000001000001 fail ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER VURSNPLMJKFHDECDABUVSTPRMNKLHJEF SIDE 11111111111111121122222222222222 DIRECTION IOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIO changed: 1 10 11110 111 11110 11110 11110 step 51 11100111100111011110011110011110 fail ^ ^^ ^ ^^ ^^^ ^ ^^ ^ ^^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER VURSNPLMJKFHDECDABUVSTPRMNKLHJEF SIDE 11111111111111121122222222222222 DIRECTION IOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIO changed: 0 step 52 01100111100111011110011110011110 fail ^^ ^ ^^ ^^^ ^ ^^ ^ ^^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER VURSNPLMJKFHDECDABUVSTPRMNKLHJEF SIDE 11111111111111121122222222222222 DIRECTION IOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIO changed: 1 step 53 11100111100111011110011110011110 fail ^ ^^ ^ ^^ ^^^ ^ ^^ ^ ^^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER VURSNPLMJKFHDECDABUVSTPRMNKLHJEF SIDE 11111111111111121122222222222222 DIRECTION IOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIO changed: 0 0 step 54 11000011100111011110011110011110 fail ^ ^^ ^ ^^ ^^^ ^ ^^ ^ ^^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER VURSNPLMJKFHDECDABUVSTPRMNKLHJEF SIDE 11111111111111121122222222222222 DIRECTION IOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIO changed: 1 1 step 55 11100111100111011110011110011110 fail ^ ^^ ^ ^^ ^^^ ^ ^^ ^ ^^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER VURSNPLMJKFHDECDABUVSTPRMNKLHJEF SIDE 11111111111111121122222222222222 DIRECTION IOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIO changed: step 56 11100111100111011110011110011110 fail ^ ^ ^^ ^^^ ^ ^^ ^ ^^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER VURSNPLMJKFHDECDABUVSTPRMNKLHJEF SIDE 11111111111111121122222222222222 DIRECTION IOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIO changed: step 57 11100111100111011110011110011110 fail ^ ^^ ^ ^^ ^^^ ^ ^^ ^ ^^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER VURSNPLMJKFHDECDABUVSTPRMNKLHJEF SIDE 11111111111111121122222222222222 DIRECTION IOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIO changed: 1 00 step 58 11101100100111011110011110011110 fail ^ ^ ^ ^^ ^^^ ^ ^^ ^ ^^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER VURSNPLMJKFHDECDABUVSTPRMNKLHJEF SIDE 11111111111111121122222222222222 DIRECTION IOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIO changed: 0 11 step 59 11100111100111011110011110011110 fail ^ ^^ ^ ^^ ^^^ ^ ^^ ^ ^^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER VURSNPLMJKFHDECDABUVSTPRMNKLHJEF SIDE 11111111111111121122222222222222 DIRECTION IOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIO changed: 01 0 step 60 11100111010011011110011110011110 fail ^ ^^ ^ ^ ^^^ ^ ^^ ^ ^^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER VURSNPLMJKFHDECDABUVSTPRMNKLHJEF SIDE 11111111111111121122222222222222 DIRECTION IOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIO changed: 10 1 step 61 11100111100111011110011110011110 fail ^ ^^ ^ ^^ ^^^ ^ ^^ ^ ^^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER VURSNPLMJKFHDECDABUVSTPRMNKLHJEF SIDE 11111111111111121122222222222222 DIRECTION IOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIO changed: step 62 11100111100111011110011110011110 fail ^ ^^ ^ ^^^ ^ ^^ ^ ^^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER VURSNPLMJKFHDECDABUVSTPRMNKLHJEF SIDE 11111111111111121122222222222222 DIRECTION IOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIO changed: step 63 11100111100111011110011110011110 fail ^ ^^ ^ ^^ ^^^ ^ ^^ ^ ^^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER VURSNPLMJKFHDECDABUVSTPRMNKLHJEF SIDE 11111111111111121122222222222222 DIRECTION IOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIO changed: 1 00 step 64 11100111101100011110011110011110 fail ^ ^^ ^ ^ ^^^ ^ ^^ ^ ^^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER VURSNPLMJKFHDECDABUVSTPRMNKLHJEF SIDE 11111111111111121122222222222222 DIRECTION IOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIO changed: 0 11 step 65 11100111100111011110011110011110 fail ^ ^^ ^ ^^ ^^^ ^ ^^ ^ ^^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER VURSNPLMJKFHDECDABUVSTPRMNKLHJEF SIDE 11111111111111121122222222222222 DIRECTION IOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIO changed: step 66 11100111100111011110011110011110 fail ^ ^^ ^ ^^ ^ ^ ^^ ^ ^^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER VURSNPLMJKFHDECDABUVSTPRMNKLHJEF SIDE 11111111111111121122222222222222 DIRECTION IOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIO changed: step 67 11100111100111011110011110011110 fail ^ ^^ ^ ^^ ^^^ ^ ^^ ^ ^^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER VURSNPLMJKFHDECDABUVSTPRMNKLHJEF SIDE 11111111111111121122222222222222 DIRECTION IOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIO changed: 1 00 step 68 11100111100111110010011110011110 fail ^ ^^ ^ ^^ ^ ^ ^ ^^ ^ ^^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER VURSNPLMJKFHDECDABUVSTPRMNKLHJEF SIDE 11111111111111121122222222222222 DIRECTION IOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIO changed: 0 11 step 69 11100111100111011110011110011110 fail ^ ^^ ^ ^^ ^^^ ^ ^^ ^ ^^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER VURSNPLMJKFHDECDABUVSTPRMNKLHJEF SIDE 11111111111111121122222222222222 DIRECTION IOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIO changed: 01 0 step 70 11100111100111011101001110011110 fail ^ ^^ ^ ^^ ^^^ ^ ^ ^ ^^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER VURSNPLMJKFHDECDABUVSTPRMNKLHJEF SIDE 11111111111111121122222222222222 DIRECTION IOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIO changed: 10 1 step 71 11100111100111011110011110011110 fail ^ ^^ ^ ^^ ^^^ ^ ^^ ^ ^^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER VURSNPLMJKFHDECDABUVSTPRMNKLHJEF SIDE 11111111111111121122222222222222 DIRECTION IOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIO changed: step 72 11100111100111011110011110011110 fail ^ ^^ ^ ^^ ^^^ ^ ^ ^^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER VURSNPLMJKFHDECDABUVSTPRMNKLHJEF SIDE 11111111111111121122222222222222 DIRECTION IOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIO changed: step 73 11100111100111011110011110011110 fail ^ ^^ ^ ^^ ^^^ ^ ^^ ^ ^^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER VURSNPLMJKFHDECDABUVSTPRMNKLHJEF SIDE 11111111111111121122222222222222 DIRECTION IOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIO changed: 1 00 step 74 11100111100111011110110010011110 fail ^ ^^ ^ ^^ ^^^ ^ ^ ^ ^^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER VURSNPLMJKFHDECDABUVSTPRMNKLHJEF SIDE 11111111111111121122222222222222 DIRECTION IOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIO changed: 0 11 step 75 11100111100111011110011110011110 fail ^ ^^ ^ ^^ ^^^ ^ ^^ ^ ^^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER VURSNPLMJKFHDECDABUVSTPRMNKLHJEF SIDE 11111111111111121122222222222222 DIRECTION IOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIO changed: 01 0 step 76 11100111100111011110011101001110 fail ^ ^^ ^ ^^ ^^^ ^ ^^ ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER VURSNPLMJKFHDECDABUVSTPRMNKLHJEF SIDE 11111111111111121122222222222222 DIRECTION IOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIO changed: 10 1 step 77 11100111100111011110011110011110 fail ^ ^^ ^ ^^ ^^^ ^ ^^ ^ ^^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER VURSNPLMJKFHDECDABUVSTPRMNKLHJEF SIDE 11111111111111121122222222222222 DIRECTION IOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIO changed: step 78 11100111100111011110011110011110 fail ^ ^^ ^ ^^ ^^^ ^ ^^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER VURSNPLMJKFHDECDABUVSTPRMNKLHJEF SIDE 11111111111111121122222222222222 DIRECTION IOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIO changed: step 79 11100111100111011110011110011110 fail ^ ^^ ^ ^^ ^^^ ^ ^^ ^ ^^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER VURSNPLMJKFHDECDABUVSTPRMNKLHJEF SIDE 11111111111111121122222222222222 DIRECTION IOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIO changed: 1 00 step 80 11100111100111011110011110110010 fail ^ ^^ ^ ^^ ^^^ ^ ^^ ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER VURSNPLMJKFHDECDABUVSTPRMNKLHJEF SIDE 11111111111111121122222222222222 DIRECTION IOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIO changed: 0 11 step 81 11100111100111011110011110011110 fail ^ ^^ ^ ^^ ^^^ ^ ^^ ^ ^^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER VURSNPLMJKFHDECDABUVSTPRMNKLHJEF SIDE 11111111111111121122222222222222 DIRECTION IOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIO changed: 0 01 step 82 11100111100111001110011110011101 fail ^ ^^ ^ ^^ ^^ ^ ^^ ^ ^^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER VURSNPLMJKFHDECDABUVSTPRMNKLHJEF SIDE 11111111111111121122222222222222 DIRECTION IOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIO changed: 1 10 step 83 11100111100111011110011110011110 fail ^ ^^ ^ ^^ ^^^ ^ ^^ ^ ^^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER VURSNPLMJKFHDECDABUVSTPRMNKLHJEF SIDE 11111111111111121122222222222222 DIRECTION IOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIO changed: step 84 11100111100111011110011110011110 fail ^ ^^ ^ ^^ ^^^ ^ ^^ ^ ^^ ^ test 45: *** FAIL *************************** 84 steps failed SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER VURSNPLMJKFHDECDABUVSTPRMNKLHJEF SIDE 11111111111111121122222222222222 DIRECTION IOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIO this fail O OIO O IO OIO O IO O IO O all fails O OIO O IO OIO O IO O IO O was hi 11111111111111111111111111111111 rising ^ ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ falling v vvvvvvvvvvvvvvvvvvvvvvvvvvvvvv was lo 0 000000000000000000000000000000 total fails 45, total passes 0 space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C toggle comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER VURSNPLMJKFHDECDABUVSTPRMNKLHJEF SIDE 11111111111111121122222222222222 DIRECTION IOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIO changed: 0 011000011000100001100001100001 step 1 01011000011000100001100001100001 fail ^^ ^ ^^ ^^^ ^ ^^ ^ ^^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER VURSNPLMJKFHDECDABUVSTPRMNKLHJEF SIDE 11111111111111121122222222222222 DIRECTION IOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIO changed: 0 0 0 step 2 01010000011000100001000001000001 fail ^ ^ ^^ ^^^ ^ ^ ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER VURSNPLMJKFHDECDABUVSTPRMNKLHJEF SIDE 11111111111111121122222222222222 DIRECTION IOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIO changed: 1 step 3 11010000011000100001000001000001 fail ^ ^ ^ ^^ ^^^ ^ ^ ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER VURSNPLMJKFHDECDABUVSTPRMNKLHJEF SIDE 11111111111111121122222222222222 DIRECTION IOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIO changed: 0 0 0 step 4 01010000010000000001000001000001 fail ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER VURSNPLMJKFHDECDABUVSTPRMNKLHJEF SIDE 11111111111111121122222222222222 DIRECTION IOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIO changed: step 5 01010000010000000001000001000001 fail ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER VURSNPLMJKFHDECDABUVSTPRMNKLHJEF SIDE 11111111111111121122222222222222 DIRECTION IOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIO changed: 10 1 step 6 01100100010000000001000001000001 fail ^ ^ ^ ^ ^ ^ ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER VURSNPLMJKFHDECDABUVSTPRMNKLHJEF SIDE 11111111111111121122222222222222 DIRECTION IOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIO changed: 01 0 step 7 01010000010000000001000001000001 fail ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER VURSNPLMJKFHDECDABUVSTPRMNKLHJEF SIDE 11111111111111121122222222222222 DIRECTION IOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIO changed: step 8 01010000010000000001000001000001 fail ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER VURSNPLMJKFHDECDABUVSTPRMNKLHJEF SIDE 11111111111111121122222222222222 DIRECTION IOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIO changed: 1 step 9 01011000010000000001000001000001 fail ^ ^ ^ ^ ^ ^ ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER VURSNPLMJKFHDECDABUVSTPRMNKLHJEF SIDE 11111111111111121122222222222222 DIRECTION IOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIO changed: 0 step 10 01010000010000000001000001000001 fail ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER VURSNPLMJKFHDECDABUVSTPRMNKLHJEF SIDE 11111111111111121122222222222222 DIRECTION IOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIO changed: step 11 01010000010000000001000001000001 fail ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER VURSNPLMJKFHDECDABUVSTPRMNKLHJEF SIDE 11111111111111121122222222222222 DIRECTION IOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIO changed: 11 step 12 01010011010000000001000001000001 fail ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER VURSNPLMJKFHDECDABUVSTPRMNKLHJEF SIDE 11111111111111121122222222222222 DIRECTION IOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIO changed: 00 step 13 01010000010000000001000001000001 fail ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER VURSNPLMJKFHDECDABUVSTPRMNKLHJEF SIDE 11111111111111121122222222222222 DIRECTION IOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIO changed: step 14 01010000010000000001000001000001 fail ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER VURSNPLMJKFHDECDABUVSTPRMNKLHJEF SIDE 11111111111111121122222222222222 DIRECTION IOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIO changed: 10 step 15 01010000100000000001000001000001 fail ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER VURSNPLMJKFHDECDABUVSTPRMNKLHJEF SIDE 11111111111111121122222222222222 DIRECTION IOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIO changed: 01 step 16 01010000010000000001000001000001 fail ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER VURSNPLMJKFHDECDABUVSTPRMNKLHJEF SIDE 11111111111111121122222222222222 DIRECTION IOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIO changed: step 17 01010000010000000001000001000001 fail ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER VURSNPLMJKFHDECDABUVSTPRMNKLHJEF SIDE 11111111111111121122222222222222 DIRECTION IOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIO changed: 1 step 18 01010000011000000001000001000001 fail ^ ^ ^ ^ ^ ^ ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER VURSNPLMJKFHDECDABUVSTPRMNKLHJEF SIDE 11111111111111121122222222222222 DIRECTION IOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIO changed: 0 step 19 01010000010000000001000001000001 fail ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER VURSNPLMJKFHDECDABUVSTPRMNKLHJEF SIDE 11111111111111121122222222222222 DIRECTION IOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIO changed: step 20 01010000010000000001000001000001 fail ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER VURSNPLMJKFHDECDABUVSTPRMNKLHJEF SIDE 11111111111111121122222222222222 DIRECTION IOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIO changed: 1 step 21 01010000010010000001000001000001 fail ^ ^ ^ ^ ^ ^ ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER VURSNPLMJKFHDECDABUVSTPRMNKLHJEF SIDE 11111111111111121122222222222222 DIRECTION IOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIO changed: 0 step 22 01010000010000000001000001000001 fail ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER VURSNPLMJKFHDECDABUVSTPRMNKLHJEF SIDE 11111111111111121122222222222222 DIRECTION IOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIO changed: step 23 01010000010000000001000001000001 fail ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER VURSNPLMJKFHDECDABUVSTPRMNKLHJEF SIDE 11111111111111121122222222222222 DIRECTION IOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIO changed: 1 step 24 01010000010000100001000001000001 fail ^ ^ ^ ^ ^ ^ ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER VURSNPLMJKFHDECDABUVSTPRMNKLHJEF SIDE 11111111111111121122222222222222 DIRECTION IOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIO changed: 0 step 25 01010000010000000001000001000001 fail ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER VURSNPLMJKFHDECDABUVSTPRMNKLHJEF SIDE 11111111111111121122222222222222 DIRECTION IOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIO changed: step 26 01010000010000000001000001000001 fail ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER VURSNPLMJKFHDECDABUVSTPRMNKLHJEF SIDE 11111111111111121122222222222222 DIRECTION IOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIO changed: 1 step 27 01010000010000001001000001000001 fail ^ ^ ^ ^ ^ ^ ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER VURSNPLMJKFHDECDABUVSTPRMNKLHJEF SIDE 11111111111111121122222222222222 DIRECTION IOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIO changed: 0 step 28 01010000010000000001000001000001 fail ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER VURSNPLMJKFHDECDABUVSTPRMNKLHJEF SIDE 11111111111111121122222222222222 DIRECTION IOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIO changed: step 29 01010000010000000001000001000001 fail ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER VURSNPLMJKFHDECDABUVSTPRMNKLHJEF SIDE 11111111111111121122222222222222 DIRECTION IOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIO changed: 10 1 step 30 01010000010000000010010001000001 fail ^ ^ ^ ^ ^ ^ ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER VURSNPLMJKFHDECDABUVSTPRMNKLHJEF SIDE 11111111111111121122222222222222 DIRECTION IOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIO changed: 01 0 step 31 01010000010000000001000001000001 fail ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER VURSNPLMJKFHDECDABUVSTPRMNKLHJEF SIDE 11111111111111121122222222222222 DIRECTION IOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIO changed: step 32 01010000010000000001000001000001 fail ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER VURSNPLMJKFHDECDABUVSTPRMNKLHJEF SIDE 11111111111111121122222222222222 DIRECTION IOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIO changed: 1 step 33 01010000010000000001100001000001 fail ^ ^ ^ ^ ^ ^ ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER VURSNPLMJKFHDECDABUVSTPRMNKLHJEF SIDE 11111111111111121122222222222222 DIRECTION IOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIO changed: 0 step 34 01010000010000000001000001000001 fail ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER VURSNPLMJKFHDECDABUVSTPRMNKLHJEF SIDE 11111111111111121122222222222222 DIRECTION IOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIO changed: step 35 01010000010000000001000001000001 fail ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER VURSNPLMJKFHDECDABUVSTPRMNKLHJEF SIDE 11111111111111121122222222222222 DIRECTION IOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIO changed: 11 step 36 01010000010000000001001101000001 fail ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER VURSNPLMJKFHDECDABUVSTPRMNKLHJEF SIDE 11111111111111121122222222222222 DIRECTION IOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIO changed: 00 step 37 01010000010000000001000001000001 fail ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER VURSNPLMJKFHDECDABUVSTPRMNKLHJEF SIDE 11111111111111121122222222222222 DIRECTION IOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIO changed: step 38 01010000010000000001000001000001 fail ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER VURSNPLMJKFHDECDABUVSTPRMNKLHJEF SIDE 11111111111111121122222222222222 DIRECTION IOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIO changed: 10 step 39 01010000010000000001000010000001 fail ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER VURSNPLMJKFHDECDABUVSTPRMNKLHJEF SIDE 11111111111111121122222222222222 DIRECTION IOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIO changed: 01 step 40 01010000010000000001000001000001 fail ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER VURSNPLMJKFHDECDABUVSTPRMNKLHJEF SIDE 11111111111111121122222222222222 DIRECTION IOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIO changed: step 41 01010000010000000001000001000001 fail ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER VURSNPLMJKFHDECDABUVSTPRMNKLHJEF SIDE 11111111111111121122222222222222 DIRECTION IOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIO changed: 1 step 42 01010000010000000001000001100001 fail ^ ^ ^ ^ ^ ^ ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER VURSNPLMJKFHDECDABUVSTPRMNKLHJEF SIDE 11111111111111121122222222222222 DIRECTION IOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIO changed: 0 step 43 01010000010000000001000001000001 fail ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER VURSNPLMJKFHDECDABUVSTPRMNKLHJEF SIDE 11111111111111121122222222222222 DIRECTION IOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIO changed: step 44 01010000010000000001000001000001 fail ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER VURSNPLMJKFHDECDABUVSTPRMNKLHJEF SIDE 11111111111111121122222222222222 DIRECTION IOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIO changed: 1 step 45 01010000010000000001000001001001 fail ^ ^ ^ ^ ^ ^ ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER VURSNPLMJKFHDECDABUVSTPRMNKLHJEF SIDE 11111111111111121122222222222222 DIRECTION IOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIO changed: 0 step 46 01010000010000000001000001000001 fail ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER VURSNPLMJKFHDECDABUVSTPRMNKLHJEF SIDE 11111111111111121122222222222222 DIRECTION IOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIO changed: step 47 01010000010000000001000001000001 fail ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER VURSNPLMJKFHDECDABUVSTPRMNKLHJEF SIDE 11111111111111121122222222222222 DIRECTION IOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIO changed: 10 step 48 01010000010000000001000001000010 fail ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER VURSNPLMJKFHDECDABUVSTPRMNKLHJEF SIDE 11111111111111121122222222222222 DIRECTION IOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIO changed: 01 step 49 01010000010000000001000001000001 fail ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER VURSNPLMJKFHDECDABUVSTPRMNKLHJEF SIDE 11111111111111121122222222222222 DIRECTION IOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIO changed: step 50 01010000010000000001000001000001 fail ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER VURSNPLMJKFHDECDABUVSTPRMNKLHJEF SIDE 11111111111111121122222222222222 DIRECTION IOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIO changed: 1 10 11110 111 11110 11110 11110 step 51 11100111100111011110011110011110 fail ^ ^^ ^ ^^ ^^^ ^ ^^ ^ ^^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER VURSNPLMJKFHDECDABUVSTPRMNKLHJEF SIDE 11111111111111121122222222222222 DIRECTION IOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIO changed: 0 step 52 01100111100111011110011110011110 fail ^^ ^ ^^ ^^^ ^ ^^ ^ ^^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER VURSNPLMJKFHDECDABUVSTPRMNKLHJEF SIDE 11111111111111121122222222222222 DIRECTION IOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIO changed: 1 step 53 11100111100111011110011110011110 fail ^ ^^ ^ ^^ ^^^ ^ ^^ ^ ^^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER VURSNPLMJKFHDECDABUVSTPRMNKLHJEF SIDE 11111111111111121122222222222222 DIRECTION IOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIO changed: 0 0 step 54 11000011100111011110011110011110 fail ^ ^^ ^ ^^ ^^^ ^ ^^ ^ ^^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER VURSNPLMJKFHDECDABUVSTPRMNKLHJEF SIDE 11111111111111121122222222222222 DIRECTION IOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIO changed: 1 1 step 55 11100111100111011110011110011110 fail ^ ^^ ^ ^^ ^^^ ^ ^^ ^ ^^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER VURSNPLMJKFHDECDABUVSTPRMNKLHJEF SIDE 11111111111111121122222222222222 DIRECTION IOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIO changed: step 56 11100111100111011110011110011110 fail ^ ^ ^^ ^^^ ^ ^^ ^ ^^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER VURSNPLMJKFHDECDABUVSTPRMNKLHJEF SIDE 11111111111111121122222222222222 DIRECTION IOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIO changed: step 57 11100111100111011110011110011110 fail ^ ^^ ^ ^^ ^^^ ^ ^^ ^ ^^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER VURSNPLMJKFHDECDABUVSTPRMNKLHJEF SIDE 11111111111111121122222222222222 DIRECTION IOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIO changed: 1 00 step 58 11101100100111011110011110011110 fail ^ ^ ^ ^^ ^^^ ^ ^^ ^ ^^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER VURSNPLMJKFHDECDABUVSTPRMNKLHJEF SIDE 11111111111111121122222222222222 DIRECTION IOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIO changed: 0 11 step 59 11100111100111011110011110011110 fail ^ ^^ ^ ^^ ^^^ ^ ^^ ^ ^^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER VURSNPLMJKFHDECDABUVSTPRMNKLHJEF SIDE 11111111111111121122222222222222 DIRECTION IOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIO changed: 01 0 step 60 11100111010011011110011110011110 fail ^ ^^ ^ ^ ^^^ ^ ^^ ^ ^^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER VURSNPLMJKFHDECDABUVSTPRMNKLHJEF SIDE 11111111111111121122222222222222 DIRECTION IOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIO changed: 10 1 step 61 11100111100111011110011110011110 fail ^ ^^ ^ ^^ ^^^ ^ ^^ ^ ^^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER VURSNPLMJKFHDECDABUVSTPRMNKLHJEF SIDE 11111111111111121122222222222222 DIRECTION IOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIO changed: step 62 11100111100111011110011110011110 fail ^ ^^ ^ ^^^ ^ ^^ ^ ^^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER VURSNPLMJKFHDECDABUVSTPRMNKLHJEF SIDE 11111111111111121122222222222222 DIRECTION IOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIO changed: step 63 11100111100111011110011110011110 fail ^ ^^ ^ ^^ ^^^ ^ ^^ ^ ^^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER VURSNPLMJKFHDECDABUVSTPRMNKLHJEF SIDE 11111111111111121122222222222222 DIRECTION IOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIO changed: 1 00 step 64 11100111101100011110011110011110 fail ^ ^^ ^ ^ ^^^ ^ ^^ ^ ^^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER VURSNPLMJKFHDECDABUVSTPRMNKLHJEF SIDE 11111111111111121122222222222222 DIRECTION IOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIO changed: 0 11 step 65 11100111100111011110011110011110 fail ^ ^^ ^ ^^ ^^^ ^ ^^ ^ ^^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER VURSNPLMJKFHDECDABUVSTPRMNKLHJEF SIDE 11111111111111121122222222222222 DIRECTION IOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIO changed: step 66 11100111100111011110011110011110 fail ^ ^^ ^ ^^ ^ ^ ^^ ^ ^^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER VURSNPLMJKFHDECDABUVSTPRMNKLHJEF SIDE 11111111111111121122222222222222 DIRECTION IOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIO changed: step 67 11100111100111011110011110011110 fail ^ ^^ ^ ^^ ^^^ ^ ^^ ^ ^^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER VURSNPLMJKFHDECDABUVSTPRMNKLHJEF SIDE 11111111111111121122222222222222 DIRECTION IOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIO changed: 1 00 step 68 11100111100111110010011110011110 fail ^ ^^ ^ ^^ ^ ^ ^ ^^ ^ ^^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER VURSNPLMJKFHDECDABUVSTPRMNKLHJEF SIDE 11111111111111121122222222222222 DIRECTION IOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIO changed: 0 11 step 69 11100111100111011110011110011110 fail ^ ^^ ^ ^^ ^^^ ^ ^^ ^ ^^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER VURSNPLMJKFHDECDABUVSTPRMNKLHJEF SIDE 11111111111111121122222222222222 DIRECTION IOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIO changed: 01 0 step 70 11100111100111011101001110011110 fail ^ ^^ ^ ^^ ^^^ ^ ^ ^ ^^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER VURSNPLMJKFHDECDABUVSTPRMNKLHJEF SIDE 11111111111111121122222222222222 DIRECTION IOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIO changed: 10 1 step 71 11100111100111011110011110011110 fail ^ ^^ ^ ^^ ^^^ ^ ^^ ^ ^^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER VURSNPLMJKFHDECDABUVSTPRMNKLHJEF SIDE 11111111111111121122222222222222 DIRECTION IOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIO changed: step 72 11100111100111011110011110011110 fail ^ ^^ ^ ^^ ^^^ ^ ^ ^^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER VURSNPLMJKFHDECDABUVSTPRMNKLHJEF SIDE 11111111111111121122222222222222 DIRECTION IOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIO changed: step 73 11100111100111011110011110011110 fail ^ ^^ ^ ^^ ^^^ ^ ^^ ^ ^^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER VURSNPLMJKFHDECDABUVSTPRMNKLHJEF SIDE 11111111111111121122222222222222 DIRECTION IOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIO changed: 1 00 step 74 11100111100111011110110010011110 fail ^ ^^ ^ ^^ ^^^ ^ ^ ^ ^^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER VURSNPLMJKFHDECDABUVSTPRMNKLHJEF SIDE 11111111111111121122222222222222 DIRECTION IOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIO changed: 0 11 step 75 11100111100111011110011110011110 fail ^ ^^ ^ ^^ ^^^ ^ ^^ ^ ^^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER VURSNPLMJKFHDECDABUVSTPRMNKLHJEF SIDE 11111111111111121122222222222222 DIRECTION IOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIO changed: 01 0 step 76 11100111100111011110011101001110 fail ^ ^^ ^ ^^ ^^^ ^ ^^ ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER VURSNPLMJKFHDECDABUVSTPRMNKLHJEF SIDE 11111111111111121122222222222222 DIRECTION IOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIO changed: 10 1 step 77 11100111100111011110011110011110 fail ^ ^^ ^ ^^ ^^^ ^ ^^ ^ ^^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER VURSNPLMJKFHDECDABUVSTPRMNKLHJEF SIDE 11111111111111121122222222222222 DIRECTION IOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIO changed: step 78 11100111100111011110011110011110 fail ^ ^^ ^ ^^ ^^^ ^ ^^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER VURSNPLMJKFHDECDABUVSTPRMNKLHJEF SIDE 11111111111111121122222222222222 DIRECTION IOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIO changed: step 79 11100111100111011110011110011110 fail ^ ^^ ^ ^^ ^^^ ^ ^^ ^ ^^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER VURSNPLMJKFHDECDABUVSTPRMNKLHJEF SIDE 11111111111111121122222222222222 DIRECTION IOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIO changed: 1 00 step 80 11100111100111011110011110110010 fail ^ ^^ ^ ^^ ^^^ ^ ^^ ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER VURSNPLMJKFHDECDABUVSTPRMNKLHJEF SIDE 11111111111111121122222222222222 DIRECTION IOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIO changed: 0 11 step 81 11100111100111011110011110011110 fail ^ ^^ ^ ^^ ^^^ ^ ^^ ^ ^^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER VURSNPLMJKFHDECDABUVSTPRMNKLHJEF SIDE 11111111111111121122222222222222 DIRECTION IOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIO changed: 0 01 step 82 11100111100111001110011110011101 fail ^ ^^ ^ ^^ ^^ ^ ^^ ^ ^^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER VURSNPLMJKFHDECDABUVSTPRMNKLHJEF SIDE 11111111111111121122222222222222 DIRECTION IOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIO changed: 1 10 step 83 11100111100111011110011110011110 fail ^ ^^ ^ ^^ ^^^ ^ ^^ ^ ^^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER VURSNPLMJKFHDECDABUVSTPRMNKLHJEF SIDE 11111111111111121122222222222222 DIRECTION IOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIO changed: step 84 11100111100111011110011110011110 fail ^ ^^ ^ ^^ ^^^ ^ ^^ ^ ^^ ^ test 46: *** FAIL *************************** 84 steps failed SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER VURSNPLMJKFHDECDABUVSTPRMNKLHJEF SIDE 11111111111111121122222222222222 DIRECTION IOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIO this fail O OIO O IO OIO O IO O IO O all fails O OIO O IO OIO O IO O IO O was hi 11111111111111111111111111111111 rising ^ ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ falling v vvvvvvvvvvvvvvvvvvvvvvvvvvvvvv was lo 0 000000000000000000000000000000 total fails 46, total passes 0 SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER VURSNPLMJKFHDECDABUVSTPRMNKLHJEF SIDE 11111111111111121122222222222222 DIRECTION IOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIO changed: 0 011000011000100001100001100001 step 1 01011000011000100001100001100001 fail ^^ ^ ^^ ^^^ ^ ^^ ^ ^^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER VURSNPLMJKFHDECDABUVSTPRMNKLHJEF SIDE 11111111111111121122222222222222 DIRECTION IOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIO changed: 0 0 0 step 2 01010000011000100001000001000001 fail ^ ^ ^^ ^^^ ^ ^ ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER VURSNPLMJKFHDECDABUVSTPRMNKLHJEF SIDE 11111111111111121122222222222222 DIRECTION IOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIO changed: 1 step 3 11010000011000100001000001000001 fail ^ ^ ^ ^^ ^^^ ^ ^ ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER VURSNPLMJKFHDECDABUVSTPRMNKLHJEF SIDE 11111111111111121122222222222222 DIRECTION IOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIO changed: 0 0 0 step 4 01010000010000000001000001000001 fail ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER VURSNPLMJKFHDECDABUVSTPRMNKLHJEF SIDE 11111111111111121122222222222222 DIRECTION IOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIO changed: step 5 01010000010000000001000001000001 fail ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER VURSNPLMJKFHDECDABUVSTPRMNKLHJEF SIDE 11111111111111121122222222222222 DIRECTION IOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIO changed: 10 1 step 6 01100100010000000001000001000001 fail ^ ^ ^ ^ ^ ^ ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER VURSNPLMJKFHDECDABUVSTPRMNKLHJEF SIDE 11111111111111121122222222222222 DIRECTION IOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIO changed: 01 0 step 7 01010000010000000001000001000001 fail ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER VURSNPLMJKFHDECDABUVSTPRMNKLHJEF SIDE 11111111111111121122222222222222 DIRECTION IOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIO changed: step 8 01010000010000000001000001000001 fail ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER VURSNPLMJKFHDECDABUVSTPRMNKLHJEF SIDE 11111111111111121122222222222222 DIRECTION IOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIO changed: 1 step 9 01011000010000000001000001000001 fail ^ ^ ^ ^ ^ ^ ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER VURSNPLMJKFHDECDABUVSTPRMNKLHJEF SIDE 11111111111111121122222222222222 DIRECTION IOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIO changed: 0 step 10 01010000010000000001000001000001 fail ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER VURSNPLMJKFHDECDABUVSTPRMNKLHJEF SIDE 11111111111111121122222222222222 DIRECTION IOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIO changed: step 11 01010000010000000001000001000001 fail ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER VURSNPLMJKFHDECDABUVSTPRMNKLHJEF SIDE 11111111111111121122222222222222 DIRECTION IOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIO changed: 11 step 12 01010011010000000001000001000001 fail ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER VURSNPLMJKFHDECDABUVSTPRMNKLHJEF SIDE 11111111111111121122222222222222 DIRECTION IOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIO changed: 00 step 13 01010000010000000001000001000001 fail ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER VURSNPLMJKFHDECDABUVSTPRMNKLHJEF SIDE 11111111111111121122222222222222 DIRECTION IOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIO changed: step 14 01010000010000000001000001000001 fail ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER VURSNPLMJKFHDECDABUVSTPRMNKLHJEF SIDE 11111111111111121122222222222222 DIRECTION IOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIO changed: 10 step 15 01010000100000000001000001000001 fail ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER VURSNPLMJKFHDECDABUVSTPRMNKLHJEF SIDE 11111111111111121122222222222222 DIRECTION IOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIO changed: 01 step 16 01010000010000000001000001000001 fail ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER VURSNPLMJKFHDECDABUVSTPRMNKLHJEF SIDE 11111111111111121122222222222222 DIRECTION IOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIO changed: step 17 01010000010000000001000001000001 fail ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER VURSNPLMJKFHDECDABUVSTPRMNKLHJEF SIDE 11111111111111121122222222222222 DIRECTION IOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIO changed: 1 step 18 01010000011000000001000001000001 fail ^ ^ ^ ^ ^ ^ ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER VURSNPLMJKFHDECDABUVSTPRMNKLHJEF SIDE 11111111111111121122222222222222 DIRECTION IOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIO changed: 0 step 19 01010000010000000001000001000001 fail ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER VURSNPLMJKFHDECDABUVSTPRMNKLHJEF SIDE 11111111111111121122222222222222 DIRECTION IOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIO changed: step 20 01010000010000000001000001000001 fail ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER VURSNPLMJKFHDECDABUVSTPRMNKLHJEF SIDE 11111111111111121122222222222222 DIRECTION IOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIO changed: 1 step 21 01010000010010000001000001000001 fail ^ ^ ^ ^ ^ ^ ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER VURSNPLMJKFHDECDABUVSTPRMNKLHJEF SIDE 11111111111111121122222222222222 DIRECTION IOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIO changed: 0 step 22 01010000010000000001000001000001 fail ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER VURSNPLMJKFHDECDABUVSTPRMNKLHJEF SIDE 11111111111111121122222222222222 DIRECTION IOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIO changed: step 23 01010000010000000001000001000001 fail ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER VURSNPLMJKFHDECDABUVSTPRMNKLHJEF SIDE 11111111111111121122222222222222 DIRECTION IOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIO changed: 1 step 24 01010000010000100001000001000001 fail ^ ^ ^ ^ ^ ^ ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER VURSNPLMJKFHDECDABUVSTPRMNKLHJEF SIDE 11111111111111121122222222222222 DIRECTION IOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIO changed: 0 step 25 01010000010000000001000001000001 fail ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER VURSNPLMJKFHDECDABUVSTPRMNKLHJEF SIDE 11111111111111121122222222222222 DIRECTION IOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIO changed: step 26 01010000010000000001000001000001 fail ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER VURSNPLMJKFHDECDABUVSTPRMNKLHJEF SIDE 11111111111111121122222222222222 DIRECTION IOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIO changed: 1 step 27 01010000010000001001000001000001 fail ^ ^ ^ ^ ^ ^ ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER VURSNPLMJKFHDECDABUVSTPRMNKLHJEF SIDE 11111111111111121122222222222222 DIRECTION IOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIO changed: 0 step 28 01010000010000000001000001000001 fail ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER VURSNPLMJKFHDECDABUVSTPRMNKLHJEF SIDE 11111111111111121122222222222222 DIRECTION IOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIO changed: step 29 01010000010000000001000001000001 fail ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER VURSNPLMJKFHDECDABUVSTPRMNKLHJEF SIDE 11111111111111121122222222222222 DIRECTION IOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIO changed: 10 1 step 30 01010000010000000010010001000001 fail ^ ^ ^ ^ ^ ^ ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER VURSNPLMJKFHDECDABUVSTPRMNKLHJEF SIDE 11111111111111121122222222222222 DIRECTION IOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIO changed: 01 0 step 31 01010000010000000001000001000001 fail ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER VURSNPLMJKFHDECDABUVSTPRMNKLHJEF SIDE 11111111111111121122222222222222 DIRECTION IOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIO changed: step 32 01010000010000000001000001000001 fail ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER VURSNPLMJKFHDECDABUVSTPRMNKLHJEF SIDE 11111111111111121122222222222222 DIRECTION IOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIO changed: 1 step 33 01010000010000000001100001000001 fail ^ ^ ^ ^ ^ ^ ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER VURSNPLMJKFHDECDABUVSTPRMNKLHJEF SIDE 11111111111111121122222222222222 DIRECTION IOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIO changed: 0 step 34 01010000010000000001000001000001 fail ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER VURSNPLMJKFHDECDABUVSTPRMNKLHJEF SIDE 11111111111111121122222222222222 DIRECTION IOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIO changed: step 35 01010000010000000001000001000001 fail ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER VURSNPLMJKFHDECDABUVSTPRMNKLHJEF SIDE 11111111111111121122222222222222 DIRECTION IOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIO changed: 11 step 36 01010000010000000001001101000001 fail ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER VURSNPLMJKFHDECDABUVSTPRMNKLHJEF SIDE 11111111111111121122222222222222 DIRECTION IOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIO changed: 00 step 37 01010000010000000001000001000001 fail ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER VURSNPLMJKFHDECDABUVSTPRMNKLHJEF SIDE 11111111111111121122222222222222 DIRECTION IOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIO changed: step 38 01010000010000000001000001000001 fail ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER VURSNPLMJKFHDECDABUVSTPRMNKLHJEF SIDE 11111111111111121122222222222222 DIRECTION IOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIO changed: 10 step 39 01010000010000000001000010000001 fail ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER VURSNPLMJKFHDECDABUVSTPRMNKLHJEF SIDE 11111111111111121122222222222222 DIRECTION IOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIO changed: 01 step 40 01010000010000000001000001000001 fail ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER VURSNPLMJKFHDECDABUVSTPRMNKLHJEF SIDE 11111111111111121122222222222222 DIRECTION IOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIO changed: step 41 01010000010000000001000001000001 fail ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER VURSNPLMJKFHDECDABUVSTPRMNKLHJEF SIDE 11111111111111121122222222222222 DIRECTION IOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIO changed: 1 step 42 01010000010000000001000001100001 fail ^ ^ ^ ^ ^ ^ ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER VURSNPLMJKFHDECDABUVSTPRMNKLHJEF SIDE 11111111111111121122222222222222 DIRECTION IOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIO changed: 0 step 43 01010000010000000001000001000001 fail ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER VURSNPLMJKFHDECDABUVSTPRMNKLHJEF SIDE 11111111111111121122222222222222 DIRECTION IOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIO changed: step 44 01010000010000000001000001000001 fail ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER VURSNPLMJKFHDECDABUVSTPRMNKLHJEF SIDE 11111111111111121122222222222222 DIRECTION IOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIO changed: 1 step 45 01010000010000000001000001001001 fail ^ ^ ^ ^ ^ ^ ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER VURSNPLMJKFHDECDABUVSTPRMNKLHJEF SIDE 11111111111111121122222222222222 DIRECTION IOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIO changed: 0 step 46 01010000010000000001000001000001 fail ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER VURSNPLMJKFHDECDABUVSTPRMNKLHJEF SIDE 11111111111111121122222222222222 DIRECTION IOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIO changed: step 47 01010000010000000001000001000001 fail ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER VURSNPLMJKFHDECDABUVSTPRMNKLHJEF SIDE 11111111111111121122222222222222 DIRECTION IOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIO changed: 10 step 48 01010000010000000001000001000010 fail ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER VURSNPLMJKFHDECDABUVSTPRMNKLHJEF SIDE 11111111111111121122222222222222 DIRECTION IOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIO changed: 01 step 49 01010000010000000001000001000001 fail ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER VURSNPLMJKFHDECDABUVSTPRMNKLHJEF SIDE 11111111111111121122222222222222 DIRECTION IOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIO changed: step 50 01010000010000000001000001000001 fail ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER VURSNPLMJKFHDECDABUVSTPRMNKLHJEF SIDE 11111111111111121122222222222222 DIRECTION IOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIO changed: 1 10 11110 111 11110 11110 11110 step 51 11100111100111011110011110011110 fail ^ ^^ ^ ^^ ^^^ ^ ^^ ^ ^^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER VURSNPLMJKFHDECDABUVSTPRMNKLHJEF SIDE 11111111111111121122222222222222 DIRECTION IOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIO changed: 0 step 52 01100111100111011110011110011110 fail ^^ ^ ^^ ^^^ ^ ^^ ^ ^^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER VURSNPLMJKFHDECDABUVSTPRMNKLHJEF SIDE 11111111111111121122222222222222 DIRECTION IOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIO changed: 1 step 53 11100111100111011110011110011110 fail ^ ^^ ^ ^^ ^^^ ^ ^^ ^ ^^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER VURSNPLMJKFHDECDABUVSTPRMNKLHJEF SIDE 11111111111111121122222222222222 DIRECTION IOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIO changed: 0 0 step 54 11000011100111011110011110011110 fail ^ ^^ ^ ^^ ^^^ ^ ^^ ^ ^^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER VURSNPLMJKFHDECDABUVSTPRMNKLHJEF SIDE 11111111111111121122222222222222 DIRECTION IOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIO changed: 1 1 step 55 11100111100111011110011110011110 fail ^ ^^ ^ ^^ ^^^ ^ ^^ ^ ^^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER VURSNPLMJKFHDECDABUVSTPRMNKLHJEF SIDE 11111111111111121122222222222222 DIRECTION IOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIO changed: step 56 11100111100111011110011110011110 fail ^ ^ ^^ ^^^ ^ ^^ ^ ^^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER VURSNPLMJKFHDECDABUVSTPRMNKLHJEF SIDE 11111111111111121122222222222222 DIRECTION IOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIO changed: step 57 11100111100111011110011110011110 fail ^ ^^ ^ ^^ ^^^ ^ ^^ ^ ^^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER VURSNPLMJKFHDECDABUVSTPRMNKLHJEF SIDE 11111111111111121122222222222222 DIRECTION IOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIO changed: 1 00 step 58 11101100100111011110011110011110 fail ^ ^ ^ ^^ ^^^ ^ ^^ ^ ^^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER VURSNPLMJKFHDECDABUVSTPRMNKLHJEF SIDE 11111111111111121122222222222222 DIRECTION IOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIO changed: 0 11 step 59 11100111100111011110011110011110 fail ^ ^^ ^ ^^ ^^^ ^ ^^ ^ ^^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER VURSNPLMJKFHDECDABUVSTPRMNKLHJEF SIDE 11111111111111121122222222222222 DIRECTION IOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIO changed: 01 0 step 60 11100111010011011110011110011110 fail ^ ^^ ^ ^ ^^^ ^ ^^ ^ ^^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER VURSNPLMJKFHDECDABUVSTPRMNKLHJEF SIDE 11111111111111121122222222222222 DIRECTION IOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIO changed: 10 1 step 61 11100111100111011110011110011110 fail ^ ^^ ^ ^^ ^^^ ^ ^^ ^ ^^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER VURSNPLMJKFHDECDABUVSTPRMNKLHJEF SIDE 11111111111111121122222222222222 DIRECTION IOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIO changed: step 62 11100111100111011110011110011110 fail ^ ^^ ^ ^^^ ^ ^^ ^ ^^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER VURSNPLMJKFHDECDABUVSTPRMNKLHJEF SIDE 11111111111111121122222222222222 DIRECTION IOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIO changed: step 63 11100111100111011110011110011110 fail ^ ^^ ^ ^^ ^^^ ^ ^^ ^ ^^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER VURSNPLMJKFHDECDABUVSTPRMNKLHJEF SIDE 11111111111111121122222222222222 DIRECTION IOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIO changed: 1 00 step 64 11100111101100011110011110011110 fail ^ ^^ ^ ^ ^^^ ^ ^^ ^ ^^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER VURSNPLMJKFHDECDABUVSTPRMNKLHJEF SIDE 11111111111111121122222222222222 DIRECTION IOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIO changed: 0 11 step 65 11100111100111011110011110011110 fail ^ ^^ ^ ^^ ^^^ ^ ^^ ^ ^^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER VURSNPLMJKFHDECDABUVSTPRMNKLHJEF SIDE 11111111111111121122222222222222 DIRECTION IOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIO changed: step 66 11100111100111011110011110011110 fail ^ ^^ ^ ^^ ^ ^ ^^ ^ ^^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER VURSNPLMJKFHDECDABUVSTPRMNKLHJEF SIDE 11111111111111121122222222222222 DIRECTION IOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIO changed: step 67 11100111100111011110011110011110 fail ^ ^^ ^ ^^ ^^^ ^ ^^ ^ ^^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER VURSNPLMJKFHDECDABUVSTPRMNKLHJEF SIDE 11111111111111121122222222222222 DIRECTION IOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIO changed: 1 00 step 68 11100111100111110010011110011110 fail ^ ^^ ^ ^^ ^ ^ ^ ^^ ^ ^^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER VURSNPLMJKFHDECDABUVSTPRMNKLHJEF SIDE 11111111111111121122222222222222 DIRECTION IOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIO changed: 0 11 step 69 11100111100111011110011110011110 fail ^ ^^ ^ ^^ ^^^ ^ ^^ ^ ^^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER VURSNPLMJKFHDECDABUVSTPRMNKLHJEF SIDE 11111111111111121122222222222222 DIRECTION IOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIO changed: 01 0 step 70 11100111100111011101001110011110 fail ^ ^^ ^ ^^ ^^^ ^ ^ ^ ^^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER VURSNPLMJKFHDECDABUVSTPRMNKLHJEF SIDE 11111111111111121122222222222222 DIRECTION IOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIO changed: 10 1 step 71 11100111100111011110011110011110 fail ^ ^^ ^ ^^ ^^^ ^ ^^ ^ ^^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER VURSNPLMJKFHDECDABUVSTPRMNKLHJEF SIDE 11111111111111121122222222222222 DIRECTION IOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIO changed: step 72 11100111100111011110011110011110 fail ^ ^^ ^ ^^ ^^^ ^ ^ ^^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER VURSNPLMJKFHDECDABUVSTPRMNKLHJEF SIDE 11111111111111121122222222222222 DIRECTION IOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIO changed: step 73 11100111100111011110011110011110 fail ^ ^^ ^ ^^ ^^^ ^ ^^ ^ ^^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER VURSNPLMJKFHDECDABUVSTPRMNKLHJEF SIDE 11111111111111121122222222222222 DIRECTION IOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIO changed: 1 00 step 74 11100111100111011110110010011110 fail ^ ^^ ^ ^^ ^^^ ^ ^ ^ ^^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER VURSNPLMJKFHDECDABUVSTPRMNKLHJEF SIDE 11111111111111121122222222222222 DIRECTION IOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIO changed: 0 11 step 75 11100111100111011110011110011110 fail ^ ^^ ^ ^^ ^^^ ^ ^^ ^ ^^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER VURSNPLMJKFHDECDABUVSTPRMNKLHJEF SIDE 11111111111111121122222222222222 DIRECTION IOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIO changed: 01 0 step 76 11100111100111011110011101001110 fail ^ ^^ ^ ^^ ^^^ ^ ^^ ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER VURSNPLMJKFHDECDABUVSTPRMNKLHJEF SIDE 11111111111111121122222222222222 DIRECTION IOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIO changed: 10 1 step 77 11100111100111011110011110011110 fail ^ ^^ ^ ^^ ^^^ ^ ^^ ^ ^^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER VURSNPLMJKFHDECDABUVSTPRMNKLHJEF SIDE 11111111111111121122222222222222 DIRECTION IOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIO changed: step 78 11100111100111011110011110011110 fail ^ ^^ ^ ^^ ^^^ ^ ^^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER VURSNPLMJKFHDECDABUVSTPRMNKLHJEF SIDE 11111111111111121122222222222222 DIRECTION IOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIO changed: step 79 11100111100111011110011110011110 fail ^ ^^ ^ ^^ ^^^ ^ ^^ ^ ^^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER VURSNPLMJKFHDECDABUVSTPRMNKLHJEF SIDE 11111111111111121122222222222222 DIRECTION IOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIO changed: 1 00 step 80 11100111100111011110011110110010 fail ^ ^^ ^ ^^ ^^^ ^ ^^ ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER VURSNPLMJKFHDECDABUVSTPRMNKLHJEF SIDE 11111111111111121122222222222222 DIRECTION IOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIO changed: 0 11 step 81 11100111100111011110011110011110 fail ^ ^^ ^ ^^ ^^^ ^ ^^ ^ ^^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER VURSNPLMJKFHDECDABUVSTPRMNKLHJEF SIDE 11111111111111121122222222222222 DIRECTION IOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIO changed: 0 01 step 82 11100111100111001110011110011101 fail ^ ^^ ^ ^^ ^^ ^ ^^ ^ ^^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER VURSNPLMJKFHDECDABUVSTPRMNKLHJEF SIDE 11111111111111121122222222222222 DIRECTION IOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIO changed: 1 10 step 83 11100111100111011110011110011110 fail ^ ^^ ^ ^^ ^^^ ^ ^^ ^ ^^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER VURSNPLMJKFHDECDABUVSTPRMNKLHJEF SIDE 11111111111111121122222222222222 DIRECTION IOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIO changed: step 84 11100111100111011110011110011110 fail ^ ^^ ^ ^^ ^^^ ^ ^^ ^ ^^ ^ test 47: *** FAIL *************************** 84 steps failed SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER VURSNPLMJKFHDECDABUVSTPRMNKLHJEF SIDE 11111111111111121122222222222222 DIRECTION IOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIO this fail O OIO O IO OIO O IO O IO O all fails O OIO O IO OIO O IO O IO O was hi 11111111111111111111111111111111 rising ^ ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ falling v vvvvvvvvvvvvvvvvvvvvvvvvvvvvvv was lo 0 000000000000000000000000000000 total fails 47, total passes 0 SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER VURSNPLMJKFHDECDABUVSTPRMNKLHJEF SIDE 11111111111111121122222222222222 DIRECTION IOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIO changed: 0 011000011000100001100001100001 step 1 01011000011000100001100001100001 fail ^^ ^ ^^ ^^^ ^ ^^ ^ ^^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER VURSNPLMJKFHDECDABUVSTPRMNKLHJEF SIDE 11111111111111121122222222222222 DIRECTION IOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIO changed: 0 0 0 step 2 01010000011000100001000001000001 fail ^ ^ ^^ ^^^ ^ ^ ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER VURSNPLMJKFHDECDABUVSTPRMNKLHJEF SIDE 11111111111111121122222222222222 DIRECTION IOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIO changed: 1 0 0 step 3 11010000010000000001000001000001 fail ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER VURSNPLMJKFHDECDABUVSTPRMNKLHJEF SIDE 11111111111111121122222222222222 DIRECTION IOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIO changed: 0 step 4 01010000010000000001000001000001 fail ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER VURSNPLMJKFHDECDABUVSTPRMNKLHJEF SIDE 11111111111111121122222222222222 DIRECTION IOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIO changed: step 5 01010000010000000001000001000001 fail ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER VURSNPLMJKFHDECDABUVSTPRMNKLHJEF SIDE 11111111111111121122222222222222 DIRECTION IOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIO changed: 10 1 step 6 01100100010000000001000001000001 fail ^ ^ ^ ^ ^ ^ ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER VURSNPLMJKFHDECDABUVSTPRMNKLHJEF SIDE 11111111111111121122222222222222 DIRECTION IOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIO changed: 01 0 step 7 01010000010000000001000001000001 fail ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER VURSNPLMJKFHDECDABUVSTPRMNKLHJEF SIDE 11111111111111121122222222222222 DIRECTION IOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIO changed: step 8 01010000010000000001000001000001 fail ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER VURSNPLMJKFHDECDABUVSTPRMNKLHJEF SIDE 11111111111111121122222222222222 DIRECTION IOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIO changed: 1 step 9 01011000010000000001000001000001 fail ^ ^ ^ ^ ^ ^ ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER VURSNPLMJKFHDECDABUVSTPRMNKLHJEF SIDE 11111111111111121122222222222222 DIRECTION IOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIO changed: 0 step 10 01010000010000000001000001000001 fail ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER VURSNPLMJKFHDECDABUVSTPRMNKLHJEF SIDE 11111111111111121122222222222222 DIRECTION IOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIO changed: step 11 01010000010000000001000001000001 fail ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER VURSNPLMJKFHDECDABUVSTPRMNKLHJEF SIDE 11111111111111121122222222222222 DIRECTION IOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIO changed: 11 step 12 01010011010000000001000001000001 fail ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER VURSNPLMJKFHDECDABUVSTPRMNKLHJEF SIDE 11111111111111121122222222222222 DIRECTION IOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIO changed: 00 step 13 01010000010000000001000001000001 fail ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER VURSNPLMJKFHDECDABUVSTPRMNKLHJEF SIDE 11111111111111121122222222222222 DIRECTION IOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIO changed: step 14 01010000010000000001000001000001 fail ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER VURSNPLMJKFHDECDABUVSTPRMNKLHJEF SIDE 11111111111111121122222222222222 DIRECTION IOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIO changed: 10 step 15 01010000100000000001000001000001 fail ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER VURSNPLMJKFHDECDABUVSTPRMNKLHJEF SIDE 11111111111111121122222222222222 DIRECTION IOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIO changed: 01 step 16 01010000010000000001000001000001 fail ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER VURSNPLMJKFHDECDABUVSTPRMNKLHJEF SIDE 11111111111111121122222222222222 DIRECTION IOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIO changed: step 17 01010000010000000001000001000001 fail ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER VURSNPLMJKFHDECDABUVSTPRMNKLHJEF SIDE 11111111111111121122222222222222 DIRECTION IOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIO changed: 1 step 18 01010000011000000001000001000001 fail ^ ^ ^ ^ ^ ^ ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER VURSNPLMJKFHDECDABUVSTPRMNKLHJEF SIDE 11111111111111121122222222222222 DIRECTION IOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIO changed: 0 step 19 01010000010000000001000001000001 fail ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER VURSNPLMJKFHDECDABUVSTPRMNKLHJEF SIDE 11111111111111121122222222222222 DIRECTION IOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIO changed: step 20 01010000010000000001000001000001 fail ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER VURSNPLMJKFHDECDABUVSTPRMNKLHJEF SIDE 11111111111111121122222222222222 DIRECTION IOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIO changed: 1 step 21 01010000010010000001000001000001 fail ^ ^ ^ ^ ^ ^ ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER VURSNPLMJKFHDECDABUVSTPRMNKLHJEF SIDE 11111111111111121122222222222222 DIRECTION IOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIO changed: 0 step 22 01010000010000000001000001000001 fail ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER VURSNPLMJKFHDECDABUVSTPRMNKLHJEF SIDE 11111111111111121122222222222222 DIRECTION IOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIO changed: step 23 01010000010000000001000001000001 fail ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER VURSNPLMJKFHDECDABUVSTPRMNKLHJEF SIDE 11111111111111121122222222222222 DIRECTION IOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIO changed: 1 step 24 01010000010000100001000001000001 fail ^ ^ ^ ^ ^ ^ ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER VURSNPLMJKFHDECDABUVSTPRMNKLHJEF SIDE 11111111111111121122222222222222 DIRECTION IOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIO changed: 0 step 25 01010000010000000001000001000001 fail ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER VURSNPLMJKFHDECDABUVSTPRMNKLHJEF SIDE 11111111111111121122222222222222 DIRECTION IOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIO changed: step 26 01010000010000000001000001000001 fail ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER VURSNPLMJKFHDECDABUVSTPRMNKLHJEF SIDE 11111111111111121122222222222222 DIRECTION IOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIO changed: 1 step 27 01010000010000001001000001000001 fail ^ ^ ^ ^ ^ ^ ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER VURSNPLMJKFHDECDABUVSTPRMNKLHJEF SIDE 11111111111111121122222222222222 DIRECTION IOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIO changed: 0 step 28 01010000010000000001000001000001 fail ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER VURSNPLMJKFHDECDABUVSTPRMNKLHJEF SIDE 11111111111111121122222222222222 DIRECTION IOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIO changed: step 29 01010000010000000001000001000001 fail ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER VURSNPLMJKFHDECDABUVSTPRMNKLHJEF SIDE 11111111111111121122222222222222 DIRECTION IOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIO changed: 10 1 step 30 01010000010000000010010001000001 fail ^ ^ ^ ^ ^ ^ ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER VURSNPLMJKFHDECDABUVSTPRMNKLHJEF SIDE 11111111111111121122222222222222 DIRECTION IOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIO changed: 01 0 step 31 01010000010000000001000001000001 fail ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER VURSNPLMJKFHDECDABUVSTPRMNKLHJEF SIDE 11111111111111121122222222222222 DIRECTION IOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIO changed: step 32 01010000010000000001000001000001 fail ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER VURSNPLMJKFHDECDABUVSTPRMNKLHJEF SIDE 11111111111111121122222222222222 DIRECTION IOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIO changed: 1 step 33 01010000010000000001100001000001 fail ^ ^ ^ ^ ^ ^ ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER VURSNPLMJKFHDECDABUVSTPRMNKLHJEF SIDE 11111111111111121122222222222222 DIRECTION IOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIO changed: 0 step 34 01010000010000000001000001000001 fail ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER VURSNPLMJKFHDECDABUVSTPRMNKLHJEF SIDE 11111111111111121122222222222222 DIRECTION IOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIO changed: step 35 01010000010000000001000001000001 fail ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER VURSNPLMJKFHDECDABUVSTPRMNKLHJEF SIDE 11111111111111121122222222222222 DIRECTION IOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIO changed: 11 step 36 01010000010000000001001101000001 fail ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER VURSNPLMJKFHDECDABUVSTPRMNKLHJEF SIDE 11111111111111121122222222222222 DIRECTION IOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIO changed: 00 step 37 01010000010000000001000001000001 fail ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER VURSNPLMJKFHDECDABUVSTPRMNKLHJEF SIDE 11111111111111121122222222222222 DIRECTION IOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIO changed: step 38 01010000010000000001000001000001 fail ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER VURSNPLMJKFHDECDABUVSTPRMNKLHJEF SIDE 11111111111111121122222222222222 DIRECTION IOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIO changed: 10 step 39 01010000010000000001000010000001 fail ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER VURSNPLMJKFHDECDABUVSTPRMNKLHJEF SIDE 11111111111111121122222222222222 DIRECTION IOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIO changed: 01 step 40 01010000010000000001000001000001 fail ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER VURSNPLMJKFHDECDABUVSTPRMNKLHJEF SIDE 11111111111111121122222222222222 DIRECTION IOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIO changed: step 41 01010000010000000001000001000001 fail ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER VURSNPLMJKFHDECDABUVSTPRMNKLHJEF SIDE 11111111111111121122222222222222 DIRECTION IOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIO changed: 1 step 42 01010000010000000001000001100001 fail ^ ^ ^ ^ ^ ^ ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER VURSNPLMJKFHDECDABUVSTPRMNKLHJEF SIDE 11111111111111121122222222222222 DIRECTION IOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIO changed: 0 step 43 01010000010000000001000001000001 fail ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER VURSNPLMJKFHDECDABUVSTPRMNKLHJEF SIDE 11111111111111121122222222222222 DIRECTION IOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIO changed: step 44 01010000010000000001000001000001 fail ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER VURSNPLMJKFHDECDABUVSTPRMNKLHJEF SIDE 11111111111111121122222222222222 DIRECTION IOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIO changed: 1 step 45 01010000010000000001000001001001 fail ^ ^ ^ ^ ^ ^ ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER VURSNPLMJKFHDECDABUVSTPRMNKLHJEF SIDE 11111111111111121122222222222222 DIRECTION IOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIO changed: 0 step 46 01010000010000000001000001000001 fail ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER VURSNPLMJKFHDECDABUVSTPRMNKLHJEF SIDE 11111111111111121122222222222222 DIRECTION IOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIO changed: step 47 01010000010000000001000001000001 fail ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER VURSNPLMJKFHDECDABUVSTPRMNKLHJEF SIDE 11111111111111121122222222222222 DIRECTION IOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIO changed: 10 step 48 01010000010000000001000001000010 fail ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER VURSNPLMJKFHDECDABUVSTPRMNKLHJEF SIDE 11111111111111121122222222222222 DIRECTION IOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIO changed: 01 step 49 01010000010000000001000001000001 fail ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER VURSNPLMJKFHDECDABUVSTPRMNKLHJEF SIDE 11111111111111121122222222222222 DIRECTION IOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIO changed: step 50 01010000010000000001000001000001 fail ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER VURSNPLMJKFHDECDABUVSTPRMNKLHJEF SIDE 11111111111111121122222222222222 DIRECTION IOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIO changed: 1 10 11110 111 11110 11110 11110 step 51 11100111100111011110011110011110 fail ^ ^^ ^ ^^ ^^^ ^ ^^ ^ ^^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER VURSNPLMJKFHDECDABUVSTPRMNKLHJEF SIDE 11111111111111121122222222222222 DIRECTION IOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIO changed: 0 step 52 01100111100111011110011110011110 fail ^^ ^ ^^ ^^^ ^ ^^ ^ ^^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER VURSNPLMJKFHDECDABUVSTPRMNKLHJEF SIDE 11111111111111121122222222222222 DIRECTION IOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIO changed: 1 step 53 11100111100111011110011110011110 fail ^ ^^ ^ ^^ ^^^ ^ ^^ ^ ^^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER VURSNPLMJKFHDECDABUVSTPRMNKLHJEF SIDE 11111111111111121122222222222222 DIRECTION IOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIO changed: 0 0 step 54 11000011100111011110011110011110 fail ^ ^^ ^ ^^ ^^^ ^ ^^ ^ ^^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER VURSNPLMJKFHDECDABUVSTPRMNKLHJEF SIDE 11111111111111121122222222222222 DIRECTION IOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIO changed: 1 1 step 55 11100111100111011110011110011110 fail ^ ^^ ^ ^^ ^^^ ^ ^^ ^ ^^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER VURSNPLMJKFHDECDABUVSTPRMNKLHJEF SIDE 11111111111111121122222222222222 DIRECTION IOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIO changed: step 56 11100111100111011110011110011110 fail ^ ^ ^^ ^^^ ^ ^^ ^ ^^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER VURSNPLMJKFHDECDABUVSTPRMNKLHJEF SIDE 11111111111111121122222222222222 DIRECTION IOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIO changed: step 57 11100111100111011110011110011110 fail ^ ^^ ^ ^^ ^^^ ^ ^^ ^ ^^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER VURSNPLMJKFHDECDABUVSTPRMNKLHJEF SIDE 11111111111111121122222222222222 DIRECTION IOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIO changed: 1 00 step 58 11101100100111011110011110011110 fail ^ ^ ^ ^^ ^^^ ^ ^^ ^ ^^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER VURSNPLMJKFHDECDABUVSTPRMNKLHJEF SIDE 11111111111111121122222222222222 DIRECTION IOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIO changed: 0 11 step 59 11100111100111011110011110011110 fail ^ ^^ ^ ^^ ^^^ ^ ^^ ^ ^^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER VURSNPLMJKFHDECDABUVSTPRMNKLHJEF SIDE 11111111111111121122222222222222 DIRECTION IOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIO changed: 01 0 step 60 11100111010011011110011110011110 fail ^ ^^ ^ ^ ^^^ ^ ^^ ^ ^^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER VURSNPLMJKFHDECDABUVSTPRMNKLHJEF SIDE 11111111111111121122222222222222 DIRECTION IOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIO changed: 10 1 step 61 11100111100111011110011110011110 fail ^ ^^ ^ ^^ ^^^ ^ ^^ ^ ^^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER VURSNPLMJKFHDECDABUVSTPRMNKLHJEF SIDE 11111111111111121122222222222222 DIRECTION IOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIO changed: step 62 11100111100111011110011110011110 fail ^ ^^ ^ ^^^ ^ ^^ ^ ^^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER VURSNPLMJKFHDECDABUVSTPRMNKLHJEF SIDE 11111111111111121122222222222222 DIRECTION IOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIO changed: step 63 11100111100111011110011110011110 fail ^ ^^ ^ ^^ ^^^ ^ ^^ ^ ^^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER VURSNPLMJKFHDECDABUVSTPRMNKLHJEF SIDE 11111111111111121122222222222222 DIRECTION IOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIO changed: 1 00 step 64 11100111101100011110011110011110 fail ^ ^^ ^ ^ ^^^ ^ ^^ ^ ^^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER VURSNPLMJKFHDECDABUVSTPRMNKLHJEF SIDE 11111111111111121122222222222222 DIRECTION IOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIO changed: 0 11 step 65 11100111100111011110011110011110 fail ^ ^^ ^ ^^ ^^^ ^ ^^ ^ ^^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER VURSNPLMJKFHDECDABUVSTPRMNKLHJEF SIDE 11111111111111121122222222222222 DIRECTION IOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIO changed: step 66 11100111100111011110011110011110 fail ^ ^^ ^ ^^ ^ ^ ^^ ^ ^^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER VURSNPLMJKFHDECDABUVSTPRMNKLHJEF SIDE 11111111111111121122222222222222 DIRECTION IOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIO changed: step 67 11100111100111011110011110011110 fail ^ ^^ ^ ^^ ^^^ ^ ^^ ^ ^^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER VURSNPLMJKFHDECDABUVSTPRMNKLHJEF SIDE 11111111111111121122222222222222 DIRECTION IOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIO changed: 1 00 step 68 11100111100111110010011110011110 fail ^ ^^ ^ ^^ ^ ^ ^ ^^ ^ ^^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER VURSNPLMJKFHDECDABUVSTPRMNKLHJEF SIDE 11111111111111121122222222222222 DIRECTION IOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIO changed: 0 11 step 69 11100111100111011110011110011110 fail ^ ^^ ^ ^^ ^^^ ^ ^^ ^ ^^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER VURSNPLMJKFHDECDABUVSTPRMNKLHJEF SIDE 11111111111111121122222222222222 DIRECTION IOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIO changed: 01 0 step 70 11100111100111011101001110011110 fail ^ ^^ ^ ^^ ^^^ ^ ^ ^ ^^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER VURSNPLMJKFHDECDABUVSTPRMNKLHJEF SIDE 11111111111111121122222222222222 DIRECTION IOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIO changed: 10 1 step 71 11100111100111011110011110011110 fail ^ ^^ ^ ^^ ^^^ ^ ^^ ^ ^^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER VURSNPLMJKFHDECDABUVSTPRMNKLHJEF SIDE 11111111111111121122222222222222 DIRECTION IOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIO changed: step 72 11100111100111011110011110011110 fail ^ ^^ ^ ^^ ^^^ ^ ^ ^^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER VURSNPLMJKFHDECDABUVSTPRMNKLHJEF SIDE 11111111111111121122222222222222 DIRECTION IOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIO changed: step 73 11100111100111011110011110011110 fail ^ ^^ ^ ^^ ^^^ ^ ^^ ^ ^^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER VURSNPLMJKFHDECDABUVSTPRMNKLHJEF SIDE 11111111111111121122222222222222 DIRECTION IOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIO changed: 1 00 step 74 11100111100111011110110010011110 fail ^ ^^ ^ ^^ ^^^ ^ ^ ^ ^^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER VURSNPLMJKFHDECDABUVSTPRMNKLHJEF SIDE 11111111111111121122222222222222 DIRECTION IOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIO changed: 0 11 step 75 11100111100111011110011110011110 fail ^ ^^ ^ ^^ ^^^ ^ ^^ ^ ^^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER VURSNPLMJKFHDECDABUVSTPRMNKLHJEF SIDE 11111111111111121122222222222222 DIRECTION IOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIO changed: 01 0 step 76 11100111100111011110011101001110 fail ^ ^^ ^ ^^ ^^^ ^ ^^ ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER VURSNPLMJKFHDECDABUVSTPRMNKLHJEF SIDE 11111111111111121122222222222222 DIRECTION IOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIO changed: 10 1 step 77 11100111100111011110011110011110 fail ^ ^^ ^ ^^ ^^^ ^ ^^ ^ ^^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER VURSNPLMJKFHDECDABUVSTPRMNKLHJEF SIDE 11111111111111121122222222222222 DIRECTION IOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIO changed: step 78 11100111100111011110011110011110 fail ^ ^^ ^ ^^ ^^^ ^ ^^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER VURSNPLMJKFHDECDABUVSTPRMNKLHJEF SIDE 11111111111111121122222222222222 DIRECTION IOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIO changed: step 79 11100111100111011110011110011110 fail ^ ^^ ^ ^^ ^^^ ^ ^^ ^ ^^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER VURSNPLMJKFHDECDABUVSTPRMNKLHJEF SIDE 11111111111111121122222222222222 DIRECTION IOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIO changed: 1 00 step 80 11100111100111011110011110110010 fail ^ ^^ ^ ^^ ^^^ ^ ^^ ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER VURSNPLMJKFHDECDABUVSTPRMNKLHJEF SIDE 11111111111111121122222222222222 DIRECTION IOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIO changed: 0 11 step 81 11100111100111011110011110011110 fail ^ ^^ ^ ^^ ^^^ ^ ^^ ^ ^^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER VURSNPLMJKFHDECDABUVSTPRMNKLHJEF SIDE 11111111111111121122222222222222 DIRECTION IOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIO changed: 0 01 step 82 11100111100111001110011110011101 fail ^ ^^ ^ ^^ ^^ ^ ^^ ^ ^^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER VURSNPLMJKFHDECDABUVSTPRMNKLHJEF SIDE 11111111111111121122222222222222 DIRECTION IOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIO changed: 1 10 step 83 11100111100111011110011110011110 fail ^ ^^ ^ ^^ ^^^ ^ ^^ ^ ^^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER VURSNPLMJKFHDECDABUVSTPRMNKLHJEF SIDE 11111111111111121122222222222222 DIRECTION IOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIO changed: step 84 11100111100111011110011110011110 fail ^ ^^ ^ ^^ ^^^ ^ ^^ ^ ^^ ^ test 48: *** FAIL *************************** 84 steps failed SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER VURSNPLMJKFHDECDABUVSTPRMNKLHJEF SIDE 11111111111111121122222222222222 DIRECTION IOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIO this fail O OIO O IO OIO O IO O IO O all fails O OIO O IO OIO O IO O IO O was hi 11111111111111111111111111111111 rising ^ ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ falling v vvvvvvvvvvvvvvvvvvvvvvvvvvvvvv was lo 0 000000000000000000000000000000 total fails 48, total passes 0 SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER VURSNPLMJKFHDECDABUVSTPRMNKLHJEF SIDE 11111111111111121122222222222222 DIRECTION IOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIO changed: 0 011000011000100001100001100001 step 1 01011000011000100001100001100001 fail ^^ ^ ^^ ^^^ ^ ^^ ^ ^^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER VURSNPLMJKFHDECDABUVSTPRMNKLHJEF SIDE 11111111111111121122222222222222 DIRECTION IOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIO changed: 0 0 0 step 2 01010000011000100001000001000001 fail ^ ^ ^^ ^^^ ^ ^ ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER VURSNPLMJKFHDECDABUVSTPRMNKLHJEF SIDE 11111111111111121122222222222222 DIRECTION IOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIO changed: 1 step 3 11010000011000100001000001000001 fail ^ ^ ^ ^^ ^^^ ^ ^ ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER VURSNPLMJKFHDECDABUVSTPRMNKLHJEF SIDE 11111111111111121122222222222222 DIRECTION IOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIO changed: 0 0 0 step 4 01010000010000000001000001000001 fail ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER VURSNPLMJKFHDECDABUVSTPRMNKLHJEF SIDE 11111111111111121122222222222222 DIRECTION IOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIO changed: step 5 01010000010000000001000001000001 fail ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER VURSNPLMJKFHDECDABUVSTPRMNKLHJEF SIDE 11111111111111121122222222222222 DIRECTION IOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIO changed: 10 1 step 6 01100100010000000001000001000001 fail ^ ^ ^ ^ ^ ^ ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER VURSNPLMJKFHDECDABUVSTPRMNKLHJEF SIDE 11111111111111121122222222222222 DIRECTION IOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIO changed: 01 0 step 7 01010000010000000001000001000001 fail ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER VURSNPLMJKFHDECDABUVSTPRMNKLHJEF SIDE 11111111111111121122222222222222 DIRECTION IOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIO changed: step 8 01010000010000000001000001000001 fail ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER VURSNPLMJKFHDECDABUVSTPRMNKLHJEF SIDE 11111111111111121122222222222222 DIRECTION IOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIO changed: 1 step 9 01011000010000000001000001000001 fail ^ ^ ^ ^ ^ ^ ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER VURSNPLMJKFHDECDABUVSTPRMNKLHJEF SIDE 11111111111111121122222222222222 DIRECTION IOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIO changed: 0 step 10 01010000010000000001000001000001 fail ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER VURSNPLMJKFHDECDABUVSTPRMNKLHJEF SIDE 11111111111111121122222222222222 DIRECTION IOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIO changed: step 11 01010000010000000001000001000001 fail ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER VURSNPLMJKFHDECDABUVSTPRMNKLHJEF SIDE 11111111111111121122222222222222 DIRECTION IOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIO changed: 11 step 12 01010011010000000001000001000001 fail ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER VURSNPLMJKFHDECDABUVSTPRMNKLHJEF SIDE 11111111111111121122222222222222 DIRECTION IOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIO changed: 00 step 13 01010000010000000001000001000001 fail ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER VURSNPLMJKFHDECDABUVSTPRMNKLHJEF SIDE 11111111111111121122222222222222 DIRECTION IOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIO changed: step 14 01010000010000000001000001000001 fail ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER VURSNPLMJKFHDECDABUVSTPRMNKLHJEF SIDE 11111111111111121122222222222222 DIRECTION IOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIO changed: 10 step 15 01010000100000000001000001000001 fail ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER VURSNPLMJKFHDECDABUVSTPRMNKLHJEF SIDE 11111111111111121122222222222222 DIRECTION IOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIO changed: 01 step 16 01010000010000000001000001000001 fail ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER VURSNPLMJKFHDECDABUVSTPRMNKLHJEF SIDE 11111111111111121122222222222222 DIRECTION IOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIO changed: step 17 01010000010000000001000001000001 fail ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER VURSNPLMJKFHDECDABUVSTPRMNKLHJEF SIDE 11111111111111121122222222222222 DIRECTION IOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIO changed: 1 step 18 01010000011000000001000001000001 fail ^ ^ ^ ^ ^ ^ ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER VURSNPLMJKFHDECDABUVSTPRMNKLHJEF SIDE 11111111111111121122222222222222 DIRECTION IOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIO changed: 0 step 19 01010000010000000001000001000001 fail ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER VURSNPLMJKFHDECDABUVSTPRMNKLHJEF SIDE 11111111111111121122222222222222 DIRECTION IOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIO changed: step 20 01010000010000000001000001000001 fail ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER VURSNPLMJKFHDECDABUVSTPRMNKLHJEF SIDE 11111111111111121122222222222222 DIRECTION IOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIO changed: 1 step 21 01010000010010000001000001000001 fail ^ ^ ^ ^ ^ ^ ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER VURSNPLMJKFHDECDABUVSTPRMNKLHJEF SIDE 11111111111111121122222222222222 DIRECTION IOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIO changed: 0 step 22 01010000010000000001000001000001 fail ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER VURSNPLMJKFHDECDABUVSTPRMNKLHJEF SIDE 11111111111111121122222222222222 DIRECTION IOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIO changed: step 23 01010000010000000001000001000001 fail ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER VURSNPLMJKFHDECDABUVSTPRMNKLHJEF SIDE 11111111111111121122222222222222 DIRECTION IOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIO changed: 1 step 24 01010000010000100001000001000001 fail ^ ^ ^ ^ ^ ^ ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER VURSNPLMJKFHDECDABUVSTPRMNKLHJEF SIDE 11111111111111121122222222222222 DIRECTION IOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIO changed: 0 step 25 01010000010000000001000001000001 fail ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER VURSNPLMJKFHDECDABUVSTPRMNKLHJEF SIDE 11111111111111121122222222222222 DIRECTION IOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIO changed: step 26 01010000010000000001000001000001 fail ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER VURSNPLMJKFHDECDABUVSTPRMNKLHJEF SIDE 11111111111111121122222222222222 DIRECTION IOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIO changed: 1 step 27 01010000010000001001000001000001 fail ^ ^ ^ ^ ^ ^ ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER VURSNPLMJKFHDECDABUVSTPRMNKLHJEF SIDE 11111111111111121122222222222222 DIRECTION IOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIO changed: 0 step 28 01010000010000000001000001000001 fail ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER VURSNPLMJKFHDECDABUVSTPRMNKLHJEF SIDE 11111111111111121122222222222222 DIRECTION IOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIO changed: step 29 01010000010000000001000001000001 fail ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER VURSNPLMJKFHDECDABUVSTPRMNKLHJEF SIDE 11111111111111121122222222222222 DIRECTION IOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIO changed: 10 1 step 30 01010000010000000010010001000001 fail ^ ^ ^ ^ ^ ^ ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER VURSNPLMJKFHDECDABUVSTPRMNKLHJEF SIDE 11111111111111121122222222222222 DIRECTION IOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIO changed: 01 0 step 31 01010000010000000001000001000001 fail ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER VURSNPLMJKFHDECDABUVSTPRMNKLHJEF SIDE 11111111111111121122222222222222 DIRECTION IOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIO changed: step 32 01010000010000000001000001000001 fail ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER VURSNPLMJKFHDECDABUVSTPRMNKLHJEF SIDE 11111111111111121122222222222222 DIRECTION IOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIO changed: 1 step 33 01010000010000000001100001000001 fail ^ ^ ^ ^ ^ ^ ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER VURSNPLMJKFHDECDABUVSTPRMNKLHJEF SIDE 11111111111111121122222222222222 DIRECTION IOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIO changed: 0 step 34 01010000010000000001000001000001 fail ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER VURSNPLMJKFHDECDABUVSTPRMNKLHJEF SIDE 11111111111111121122222222222222 DIRECTION IOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIO changed: step 35 01010000010000000001000001000001 fail ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER VURSNPLMJKFHDECDABUVSTPRMNKLHJEF SIDE 11111111111111121122222222222222 DIRECTION IOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIO changed: 11 step 36 01010000010000000001001101000001 fail ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER VURSNPLMJKFHDECDABUVSTPRMNKLHJEF SIDE 11111111111111121122222222222222 DIRECTION IOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIO changed: 00 step 37 01010000010000000001000001000001 fail ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER VURSNPLMJKFHDECDABUVSTPRMNKLHJEF SIDE 11111111111111121122222222222222 DIRECTION IOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIO changed: step 38 01010000010000000001000001000001 fail ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER VURSNPLMJKFHDECDABUVSTPRMNKLHJEF SIDE 11111111111111121122222222222222 DIRECTION IOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIO changed: 10 step 39 01010000010000000001000010000001 fail ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER VURSNPLMJKFHDECDABUVSTPRMNKLHJEF SIDE 11111111111111121122222222222222 DIRECTION IOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIO changed: 01 step 40 01010000010000000001000001000001 fail ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER VURSNPLMJKFHDECDABUVSTPRMNKLHJEF SIDE 11111111111111121122222222222222 DIRECTION IOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIO changed: step 41 01010000010000000001000001000001 fail ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER VURSNPLMJKFHDECDABUVSTPRMNKLHJEF SIDE 11111111111111121122222222222222 DIRECTION IOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIO changed: 1 step 42 01010000010000000001000001100001 fail ^ ^ ^ ^ ^ ^ ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER VURSNPLMJKFHDECDABUVSTPRMNKLHJEF SIDE 11111111111111121122222222222222 DIRECTION IOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIO changed: 0 step 43 01010000010000000001000001000001 fail ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER VURSNPLMJKFHDECDABUVSTPRMNKLHJEF SIDE 11111111111111121122222222222222 DIRECTION IOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIO changed: step 44 01010000010000000001000001000001 fail ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER VURSNPLMJKFHDECDABUVSTPRMNKLHJEF SIDE 11111111111111121122222222222222 DIRECTION IOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIO changed: 1 step 45 01010000010000000001000001001001 fail ^ ^ ^ ^ ^ ^ ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER VURSNPLMJKFHDECDABUVSTPRMNKLHJEF SIDE 11111111111111121122222222222222 DIRECTION IOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIO changed: 0 step 46 01010000010000000001000001000001 fail ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER VURSNPLMJKFHDECDABUVSTPRMNKLHJEF SIDE 11111111111111121122222222222222 DIRECTION IOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIO changed: step 47 01010000010000000001000001000001 fail ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER VURSNPLMJKFHDECDABUVSTPRMNKLHJEF SIDE 11111111111111121122222222222222 DIRECTION IOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIO changed: 10 step 48 01010000010000000001000001000010 fail ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER VURSNPLMJKFHDECDABUVSTPRMNKLHJEF SIDE 11111111111111121122222222222222 DIRECTION IOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIO changed: 01 step 49 01010000010000000001000001000001 fail ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER VURSNPLMJKFHDECDABUVSTPRMNKLHJEF SIDE 11111111111111121122222222222222 DIRECTION IOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIO changed: step 50 01010000010000000001000001000001 fail ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER VURSNPLMJKFHDECDABUVSTPRMNKLHJEF SIDE 11111111111111121122222222222222 DIRECTION IOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIO changed: 1 10 11110 111 11110 11110 11110 step 51 11100111100111011110011110011110 fail ^ ^^ ^ ^^ ^^^ ^ ^^ ^ ^^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER VURSNPLMJKFHDECDABUVSTPRMNKLHJEF SIDE 11111111111111121122222222222222 DIRECTION IOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIO changed: 0 step 52 01100111100111011110011110011110 fail ^^ ^ ^^ ^^^ ^ ^^ ^ ^^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER VURSNPLMJKFHDECDABUVSTPRMNKLHJEF SIDE 11111111111111121122222222222222 DIRECTION IOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIO changed: 1 step 53 11100111100111011110011110011110 fail ^ ^^ ^ ^^ ^^^ ^ ^^ ^ ^^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER VURSNPLMJKFHDECDABUVSTPRMNKLHJEF SIDE 11111111111111121122222222222222 DIRECTION IOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIO changed: 0 0 step 54 11000011100111011110011110011110 fail ^ ^^ ^ ^^ ^^^ ^ ^^ ^ ^^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER VURSNPLMJKFHDECDABUVSTPRMNKLHJEF SIDE 11111111111111121122222222222222 DIRECTION IOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIO changed: 1 1 step 55 11100111100111011110011110011110 fail ^ ^^ ^ ^^ ^^^ ^ ^^ ^ ^^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER VURSNPLMJKFHDECDABUVSTPRMNKLHJEF SIDE 11111111111111121122222222222222 DIRECTION IOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIO changed: step 56 11100111100111011110011110011110 fail ^ ^ ^^ ^^^ ^ ^^ ^ ^^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER VURSNPLMJKFHDECDABUVSTPRMNKLHJEF SIDE 11111111111111121122222222222222 DIRECTION IOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIO changed: step 57 11100111100111011110011110011110 fail ^ ^^ ^ ^^ ^^^ ^ ^^ ^ ^^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER VURSNPLMJKFHDECDABUVSTPRMNKLHJEF SIDE 11111111111111121122222222222222 DIRECTION IOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIO changed: 1 00 step 58 11101100100111011110011110011110 fail ^ ^ ^ ^^ ^^^ ^ ^^ ^ ^^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER VURSNPLMJKFHDECDABUVSTPRMNKLHJEF SIDE 11111111111111121122222222222222 DIRECTION IOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIO changed: 0 11 step 59 11100111100111011110011110011110 fail ^ ^^ ^ ^^ ^^^ ^ ^^ ^ ^^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER VURSNPLMJKFHDECDABUVSTPRMNKLHJEF SIDE 11111111111111121122222222222222 DIRECTION IOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIO changed: 01 0 step 60 11100111010011011110011110011110 fail ^ ^^ ^ ^ ^^^ ^ ^^ ^ ^^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER VURSNPLMJKFHDECDABUVSTPRMNKLHJEF SIDE 11111111111111121122222222222222 DIRECTION IOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIO changed: 10 1 step 61 11100111100111011110011110011110 fail ^ ^^ ^ ^^ ^^^ ^ ^^ ^ ^^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER VURSNPLMJKFHDECDABUVSTPRMNKLHJEF SIDE 11111111111111121122222222222222 DIRECTION IOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIO changed: step 62 11100111100111011110011110011110 fail ^ ^^ ^ ^^^ ^ ^^ ^ ^^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER VURSNPLMJKFHDECDABUVSTPRMNKLHJEF SIDE 11111111111111121122222222222222 DIRECTION IOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIO changed: step 63 11100111100111011110011110011110 fail ^ ^^ ^ ^^ ^^^ ^ ^^ ^ ^^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER VURSNPLMJKFHDECDABUVSTPRMNKLHJEF SIDE 11111111111111121122222222222222 DIRECTION IOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIO changed: 1 00 step 64 11100111101100011110011110011110 fail ^ ^^ ^ ^ ^^^ ^ ^^ ^ ^^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER VURSNPLMJKFHDECDABUVSTPRMNKLHJEF SIDE 11111111111111121122222222222222 DIRECTION IOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIO changed: 0 11 step 65 11100111100111011110011110011110 fail ^ ^^ ^ ^^ ^^^ ^ ^^ ^ ^^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER VURSNPLMJKFHDECDABUVSTPRMNKLHJEF SIDE 11111111111111121122222222222222 DIRECTION IOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIO changed: step 66 11100111100111011110011110011110 fail ^ ^^ ^ ^^ ^ ^ ^^ ^ ^^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER VURSNPLMJKFHDECDABUVSTPRMNKLHJEF SIDE 11111111111111121122222222222222 DIRECTION IOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIO changed: step 67 11100111100111011110011110011110 fail ^ ^^ ^ ^^ ^^^ ^ ^^ ^ ^^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER VURSNPLMJKFHDECDABUVSTPRMNKLHJEF SIDE 11111111111111121122222222222222 DIRECTION IOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIO changed: 1 00 step 68 11100111100111110010011110011110 fail ^ ^^ ^ ^^ ^ ^ ^ ^^ ^ ^^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER VURSNPLMJKFHDECDABUVSTPRMNKLHJEF SIDE 11111111111111121122222222222222 DIRECTION IOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIO changed: 0 11 step 69 11100111100111011110011110011110 fail ^ ^^ ^ ^^ ^^^ ^ ^^ ^ ^^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER VURSNPLMJKFHDECDABUVSTPRMNKLHJEF SIDE 11111111111111121122222222222222 DIRECTION IOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIO changed: 01 0 step 70 11100111100111011101001110011110 fail ^ ^^ ^ ^^ ^^^ ^ ^ ^ ^^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER VURSNPLMJKFHDECDABUVSTPRMNKLHJEF SIDE 11111111111111121122222222222222 DIRECTION IOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIO changed: 10 1 step 71 11100111100111011110011110011110 fail ^ ^^ ^ ^^ ^^^ ^ ^^ ^ ^^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER VURSNPLMJKFHDECDABUVSTPRMNKLHJEF SIDE 11111111111111121122222222222222 DIRECTION IOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIO changed: step 72 11100111100111011110011110011110 fail ^ ^^ ^ ^^ ^^^ ^ ^ ^^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER VURSNPLMJKFHDECDABUVSTPRMNKLHJEF SIDE 11111111111111121122222222222222 DIRECTION IOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIO changed: step 73 11100111100111011110011110011110 fail ^ ^^ ^ ^^ ^^^ ^ ^^ ^ ^^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER VURSNPLMJKFHDECDABUVSTPRMNKLHJEF SIDE 11111111111111121122222222222222 DIRECTION IOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIO changed: 1 00 step 74 11100111100111011110110010011110 fail ^ ^^ ^ ^^ ^^^ ^ ^ ^ ^^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER VURSNPLMJKFHDECDABUVSTPRMNKLHJEF SIDE 11111111111111121122222222222222 DIRECTION IOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIO changed: 0 11 step 75 11100111100111011110011110011110 fail ^ ^^ ^ ^^ ^^^ ^ ^^ ^ ^^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER VURSNPLMJKFHDECDABUVSTPRMNKLHJEF SIDE 11111111111111121122222222222222 DIRECTION IOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIO changed: 01 0 step 76 11100111100111011110011101001110 fail ^ ^^ ^ ^^ ^^^ ^ ^^ ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER VURSNPLMJKFHDECDABUVSTPRMNKLHJEF SIDE 11111111111111121122222222222222 DIRECTION IOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIO changed: 10 1 step 77 11100111100111011110011110011110 fail ^ ^^ ^ ^^ ^^^ ^ ^^ ^ ^^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER VURSNPLMJKFHDECDABUVSTPRMNKLHJEF SIDE 11111111111111121122222222222222 DIRECTION IOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIO changed: step 78 11100111100111011110011110011110 fail ^ ^^ ^ ^^ ^^^ ^ ^^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER VURSNPLMJKFHDECDABUVSTPRMNKLHJEF SIDE 11111111111111121122222222222222 DIRECTION IOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIO changed: step 79 11100111100111011110011110011110 fail ^ ^^ ^ ^^ ^^^ ^ ^^ ^ ^^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER VURSNPLMJKFHDECDABUVSTPRMNKLHJEF SIDE 11111111111111121122222222222222 DIRECTION IOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIO changed: 1 00 step 80 11100111100111011110011110110010 fail ^ ^^ ^ ^^ ^^^ ^ ^^ ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER VURSNPLMJKFHDECDABUVSTPRMNKLHJEF SIDE 11111111111111121122222222222222 DIRECTION IOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIO changed: 0 11 step 81 11100111100111011110011110011110 fail ^ ^^ ^ ^^ ^^^ ^ ^^ ^ ^^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER VURSNPLMJKFHDECDABUVSTPRMNKLHJEF SIDE 11111111111111121122222222222222 DIRECTION IOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIO changed: 0 01 step 82 11100111100111001110011110011101 fail ^ ^^ ^ ^^ ^^ ^ ^^ ^ ^^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER VURSNPLMJKFHDECDABUVSTPRMNKLHJEF SIDE 11111111111111121122222222222222 DIRECTION IOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIO changed: 1 10 step 83 11100111100111011110011110011110 fail ^ ^^ ^ ^^ ^^^ ^ ^^ ^ ^^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER VURSNPLMJKFHDECDABUVSTPRMNKLHJEF SIDE 11111111111111121122222222222222 DIRECTION IOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIO changed: step 84 11100111100111011110011110011110 fail ^ ^^ ^ ^^ ^^^ ^ ^^ ^ ^^ ^ test 49: *** FAIL *************************** 84 steps failed SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER VURSNPLMJKFHDECDABUVSTPRMNKLHJEF SIDE 11111111111111121122222222222222 DIRECTION IOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIO this fail O OIO O IO OIO O IO O IO O all fails O OIO O IO OIO O IO O IO O was hi 11111111111111111111111111111111 rising ^ ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ falling v vvvvvvvvvvvvvvvvvvvvvvvvvvvvvv was lo 0 000000000000000000000000000000 total fails 49, total passes 0 SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER VURSNPLMJKFHDECDABUVSTPRMNKLHJEF SIDE 11111111111111121122222222222222 DIRECTION IOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIO changed: 0 011000011000100001100001100001 step 1 01011000011000100001100001100001 fail ^^ ^ ^^ ^^^ ^ ^^ ^ ^^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER VURSNPLMJKFHDECDABUVSTPRMNKLHJEF SIDE 11111111111111121122222222222222 DIRECTION IOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIO changed: 0 0 0 step 2 01010000011000100001000001000001 fail ^ ^ ^^ ^^^ ^ ^ ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER VURSNPLMJKFHDECDABUVSTPRMNKLHJEF SIDE 11111111111111121122222222222222 DIRECTION IOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIO changed: 1 step 3 11010000011000100001000001000001 fail ^ ^ ^ ^^ ^^^ ^ ^ ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER VURSNPLMJKFHDECDABUVSTPRMNKLHJEF SIDE 11111111111111121122222222222222 DIRECTION IOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIO changed: 0 0 0 step 4 01010000010000000001000001000001 fail ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER VURSNPLMJKFHDECDABUVSTPRMNKLHJEF SIDE 11111111111111121122222222222222 DIRECTION IOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIO changed: step 5 01010000010000000001000001000001 fail ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER VURSNPLMJKFHDECDABUVSTPRMNKLHJEF SIDE 11111111111111121122222222222222 DIRECTION IOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIO changed: 10 1 step 6 01100100010000000001000001000001 fail ^ ^ ^ ^ ^ ^ ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER VURSNPLMJKFHDECDABUVSTPRMNKLHJEF SIDE 11111111111111121122222222222222 DIRECTION IOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIO changed: 01 0 step 7 01010000010000000001000001000001 fail ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER VURSNPLMJKFHDECDABUVSTPRMNKLHJEF SIDE 11111111111111121122222222222222 DIRECTION IOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIO changed: step 8 01010000010000000001000001000001 fail ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER VURSNPLMJKFHDECDABUVSTPRMNKLHJEF SIDE 11111111111111121122222222222222 DIRECTION IOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIO changed: 1 step 9 01011000010000000001000001000001 fail ^ ^ ^ ^ ^ ^ ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER VURSNPLMJKFHDECDABUVSTPRMNKLHJEF SIDE 11111111111111121122222222222222 DIRECTION IOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIO changed: 0 step 10 01010000010000000001000001000001 fail ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER VURSNPLMJKFHDECDABUVSTPRMNKLHJEF SIDE 11111111111111121122222222222222 DIRECTION IOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIO changed: step 11 01010000010000000001000001000001 fail ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER VURSNPLMJKFHDECDABUVSTPRMNKLHJEF SIDE 11111111111111121122222222222222 DIRECTION IOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIO changed: 11 step 12 01010011010000000001000001000001 fail ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER VURSNPLMJKFHDECDABUVSTPRMNKLHJEF SIDE 11111111111111121122222222222222 DIRECTION IOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIO changed: 00 step 13 01010000010000000001000001000001 fail ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER VURSNPLMJKFHDECDABUVSTPRMNKLHJEF SIDE 11111111111111121122222222222222 DIRECTION IOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIO changed: step 14 01010000010000000001000001000001 fail ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER VURSNPLMJKFHDECDABUVSTPRMNKLHJEF SIDE 11111111111111121122222222222222 DIRECTION IOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIO changed: 10 step 15 01010000100000000001000001000001 fail ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER VURSNPLMJKFHDECDABUVSTPRMNKLHJEF SIDE 11111111111111121122222222222222 DIRECTION IOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIO changed: 01 step 16 01010000010000000001000001000001 fail ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER VURSNPLMJKFHDECDABUVSTPRMNKLHJEF SIDE 11111111111111121122222222222222 DIRECTION IOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIO changed: step 17 01010000010000000001000001000001 fail ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER VURSNPLMJKFHDECDABUVSTPRMNKLHJEF SIDE 11111111111111121122222222222222 DIRECTION IOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIO changed: 1 step 18 01010000011000000001000001000001 fail ^ ^ ^ ^ ^ ^ ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER VURSNPLMJKFHDECDABUVSTPRMNKLHJEF SIDE 11111111111111121122222222222222 DIRECTION IOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIO changed: 0 step 19 01010000010000000001000001000001 fail ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER VURSNPLMJKFHDECDABUVSTPRMNKLHJEF SIDE 11111111111111121122222222222222 DIRECTION IOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIO changed: step 20 01010000010000000001000001000001 fail ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER VURSNPLMJKFHDECDABUVSTPRMNKLHJEF SIDE 11111111111111121122222222222222 DIRECTION IOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIO changed: 1 step 21 01010000010010000001000001000001 fail ^ ^ ^ ^ ^ ^ ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER VURSNPLMJKFHDECDABUVSTPRMNKLHJEF SIDE 11111111111111121122222222222222 DIRECTION IOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIO changed: 0 step 22 01010000010000000001000001000001 fail ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER VURSNPLMJKFHDECDABUVSTPRMNKLHJEF SIDE 11111111111111121122222222222222 DIRECTION IOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIO changed: step 23 01010000010000000001000001000001 fail ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER VURSNPLMJKFHDECDABUVSTPRMNKLHJEF SIDE 11111111111111121122222222222222 DIRECTION IOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIO changed: 1 step 24 01010000010000100001000001000001 fail ^ ^ ^ ^ ^ ^ ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER VURSNPLMJKFHDECDABUVSTPRMNKLHJEF SIDE 11111111111111121122222222222222 DIRECTION IOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIO changed: 0 step 25 01010000010000000001000001000001 fail ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER VURSNPLMJKFHDECDABUVSTPRMNKLHJEF SIDE 11111111111111121122222222222222 DIRECTION IOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIO changed: step 26 01010000010000000001000001000001 fail ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER VURSNPLMJKFHDECDABUVSTPRMNKLHJEF SIDE 11111111111111121122222222222222 DIRECTION IOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIO changed: 1 step 27 01010000010000001001000001000001 fail ^ ^ ^ ^ ^ ^ ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER VURSNPLMJKFHDECDABUVSTPRMNKLHJEF SIDE 11111111111111121122222222222222 DIRECTION IOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIO changed: 0 step 28 01010000010000000001000001000001 fail ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER VURSNPLMJKFHDECDABUVSTPRMNKLHJEF SIDE 11111111111111121122222222222222 DIRECTION IOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIO changed: step 29 01010000010000000001000001000001 fail ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER VURSNPLMJKFHDECDABUVSTPRMNKLHJEF SIDE 11111111111111121122222222222222 DIRECTION IOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIO changed: 10 1 step 30 01010000010000000010010001000001 fail ^ ^ ^ ^ ^ ^ ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER VURSNPLMJKFHDECDABUVSTPRMNKLHJEF SIDE 11111111111111121122222222222222 DIRECTION IOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIO changed: 01 0 step 31 01010000010000000001000001000001 fail ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER VURSNPLMJKFHDECDABUVSTPRMNKLHJEF SIDE 11111111111111121122222222222222 DIRECTION IOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIO changed: step 32 01010000010000000001000001000001 fail ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER VURSNPLMJKFHDECDABUVSTPRMNKLHJEF SIDE 11111111111111121122222222222222 DIRECTION IOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIO changed: 1 step 33 01010000010000000001100001000001 fail ^ ^ ^ ^ ^ ^ ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER VURSNPLMJKFHDECDABUVSTPRMNKLHJEF SIDE 11111111111111121122222222222222 DIRECTION IOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIO changed: 0 step 34 01010000010000000001000001000001 fail ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER VURSNPLMJKFHDECDABUVSTPRMNKLHJEF SIDE 11111111111111121122222222222222 DIRECTION IOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIO changed: step 35 01010000010000000001000001000001 fail ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER VURSNPLMJKFHDECDABUVSTPRMNKLHJEF SIDE 11111111111111121122222222222222 DIRECTION IOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIO changed: 11 step 36 01010000010000000001001101000001 fail ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER VURSNPLMJKFHDECDABUVSTPRMNKLHJEF SIDE 11111111111111121122222222222222 DIRECTION IOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIO changed: 00 step 37 01010000010000000001000001000001 fail ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER VURSNPLMJKFHDECDABUVSTPRMNKLHJEF SIDE 11111111111111121122222222222222 DIRECTION IOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIO changed: step 38 01010000010000000001000001000001 fail ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER VURSNPLMJKFHDECDABUVSTPRMNKLHJEF SIDE 11111111111111121122222222222222 DIRECTION IOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIO changed: 10 step 39 01010000010000000001000010000001 fail ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER VURSNPLMJKFHDECDABUVSTPRMNKLHJEF SIDE 11111111111111121122222222222222 DIRECTION IOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIO changed: 01 step 40 01010000010000000001000001000001 fail ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER VURSNPLMJKFHDECDABUVSTPRMNKLHJEF SIDE 11111111111111121122222222222222 DIRECTION IOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIO changed: step 41 01010000010000000001000001000001 fail ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER VURSNPLMJKFHDECDABUVSTPRMNKLHJEF SIDE 11111111111111121122222222222222 DIRECTION IOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIO changed: 1 step 42 01010000010000000001000001100001 fail ^ ^ ^ ^ ^ ^ ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER VURSNPLMJKFHDECDABUVSTPRMNKLHJEF SIDE 11111111111111121122222222222222 DIRECTION IOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIO changed: 0 step 43 01010000010000000001000001000001 fail ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER VURSNPLMJKFHDECDABUVSTPRMNKLHJEF SIDE 11111111111111121122222222222222 DIRECTION IOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIO changed: step 44 01010000010000000001000001000001 fail ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER VURSNPLMJKFHDECDABUVSTPRMNKLHJEF SIDE 11111111111111121122222222222222 DIRECTION IOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIO changed: 1 step 45 01010000010000000001000001001001 fail ^ ^ ^ ^ ^ ^ ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER VURSNPLMJKFHDECDABUVSTPRMNKLHJEF SIDE 11111111111111121122222222222222 DIRECTION IOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIO changed: 0 step 46 01010000010000000001000001000001 fail ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER VURSNPLMJKFHDECDABUVSTPRMNKLHJEF SIDE 11111111111111121122222222222222 DIRECTION IOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIO changed: step 47 01010000010000000001000001000001 fail ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER VURSNPLMJKFHDECDABUVSTPRMNKLHJEF SIDE 11111111111111121122222222222222 DIRECTION IOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIO changed: 10 step 48 01010000010000000001000001000010 fail ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER VURSNPLMJKFHDECDABUVSTPRMNKLHJEF SIDE 11111111111111121122222222222222 DIRECTION IOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIO changed: 01 step 49 01010000010000000001000001000001 fail ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER VURSNPLMJKFHDECDABUVSTPRMNKLHJEF SIDE 11111111111111121122222222222222 DIRECTION IOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIO changed: step 50 01010000010000000001000001000001 fail ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER VURSNPLMJKFHDECDABUVSTPRMNKLHJEF SIDE 11111111111111121122222222222222 DIRECTION IOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIO changed: 1 10 11110 111 11110 11110 11110 step 51 11100111100111011110011110011110 fail ^ ^^ ^ ^^ ^^^ ^ ^^ ^ ^^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER VURSNPLMJKFHDECDABUVSTPRMNKLHJEF SIDE 11111111111111121122222222222222 DIRECTION IOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIO changed: 0 step 52 01100111100111011110011110011110 fail ^^ ^ ^^ ^^^ ^ ^^ ^ ^^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER VURSNPLMJKFHDECDABUVSTPRMNKLHJEF SIDE 11111111111111121122222222222222 DIRECTION IOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIO changed: 1 step 53 11100111100111011110011110011110 fail ^ ^^ ^ ^^ ^^^ ^ ^^ ^ ^^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER VURSNPLMJKFHDECDABUVSTPRMNKLHJEF SIDE 11111111111111121122222222222222 DIRECTION IOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIO changed: 0 0 step 54 11000011100111011110011110011110 fail ^ ^^ ^ ^^ ^^^ ^ ^^ ^ ^^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER VURSNPLMJKFHDECDABUVSTPRMNKLHJEF SIDE 11111111111111121122222222222222 DIRECTION IOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIO changed: 1 1 step 55 11100111100111011110011110011110 fail ^ ^^ ^ ^^ ^^^ ^ ^^ ^ ^^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER VURSNPLMJKFHDECDABUVSTPRMNKLHJEF SIDE 11111111111111121122222222222222 DIRECTION IOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIO changed: step 56 11100111100111011110011110011110 fail ^ ^ ^^ ^^^ ^ ^^ ^ ^^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER VURSNPLMJKFHDECDABUVSTPRMNKLHJEF SIDE 11111111111111121122222222222222 DIRECTION IOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIO changed: step 57 11100111100111011110011110011110 fail ^ ^^ ^ ^^ ^^^ ^ ^^ ^ ^^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER VURSNPLMJKFHDECDABUVSTPRMNKLHJEF SIDE 11111111111111121122222222222222 DIRECTION IOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIO changed: 1 00 step 58 11101100100111011110011110011110 fail ^ ^ ^ ^^ ^^^ ^ ^^ ^ ^^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER VURSNPLMJKFHDECDABUVSTPRMNKLHJEF SIDE 11111111111111121122222222222222 DIRECTION IOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIO changed: 0 11 step 59 11100111100111011110011110011110 fail ^ ^^ ^ ^^ ^^^ ^ ^^ ^ ^^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER VURSNPLMJKFHDECDABUVSTPRMNKLHJEF SIDE 11111111111111121122222222222222 DIRECTION IOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIO changed: 01 0 step 60 11100111010011011110011110011110 fail ^ ^^ ^ ^ ^^^ ^ ^^ ^ ^^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER VURSNPLMJKFHDECDABUVSTPRMNKLHJEF SIDE 11111111111111121122222222222222 DIRECTION IOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIO changed: 10 1 step 61 11100111100111011110011110011110 fail ^ ^^ ^ ^^ ^^^ ^ ^^ ^ ^^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER VURSNPLMJKFHDECDABUVSTPRMNKLHJEF SIDE 11111111111111121122222222222222 DIRECTION IOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIO changed: step 62 11100111100111011110011110011110 fail ^ ^^ ^ ^^^ ^ ^^ ^ ^^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER VURSNPLMJKFHDECDABUVSTPRMNKLHJEF SIDE 11111111111111121122222222222222 DIRECTION IOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIO changed: step 63 11100111100111011110011110011110 fail ^ ^^ ^ ^^ ^^^ ^ ^^ ^ ^^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER VURSNPLMJKFHDECDABUVSTPRMNKLHJEF SIDE 11111111111111121122222222222222 DIRECTION IOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIO changed: 1 00 step 64 11100111101100011110011110011110 fail ^ ^^ ^ ^ ^^^ ^ ^^ ^ ^^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER VURSNPLMJKFHDECDABUVSTPRMNKLHJEF SIDE 11111111111111121122222222222222 DIRECTION IOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIO changed: 0 11 step 65 11100111100111011110011110011110 fail ^ ^^ ^ ^^ ^^^ ^ ^^ ^ ^^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER VURSNPLMJKFHDECDABUVSTPRMNKLHJEF SIDE 11111111111111121122222222222222 DIRECTION IOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIO changed: step 66 11100111100111011110011110011110 fail ^ ^^ ^ ^^ ^ ^ ^^ ^ ^^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER VURSNPLMJKFHDECDABUVSTPRMNKLHJEF SIDE 11111111111111121122222222222222 DIRECTION IOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIO changed: step 67 11100111100111011110011110011110 fail ^ ^^ ^ ^^ ^^^ ^ ^^ ^ ^^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER VURSNPLMJKFHDECDABUVSTPRMNKLHJEF SIDE 11111111111111121122222222222222 DIRECTION IOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIO changed: 1 00 step 68 11100111100111110010011110011110 fail ^ ^^ ^ ^^ ^ ^ ^ ^^ ^ ^^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER VURSNPLMJKFHDECDABUVSTPRMNKLHJEF SIDE 11111111111111121122222222222222 DIRECTION IOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIO changed: 0 11 step 69 11100111100111011110011110011110 fail ^ ^^ ^ ^^ ^^^ ^ ^^ ^ ^^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER VURSNPLMJKFHDECDABUVSTPRMNKLHJEF SIDE 11111111111111121122222222222222 DIRECTION IOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIO changed: 01 0 step 70 11100111100111011101001110011110 fail ^ ^^ ^ ^^ ^^^ ^ ^ ^ ^^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER VURSNPLMJKFHDECDABUVSTPRMNKLHJEF SIDE 11111111111111121122222222222222 DIRECTION IOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIO changed: 10 1 step 71 11100111100111011110011110011110 fail ^ ^^ ^ ^^ ^^^ ^ ^^ ^ ^^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER VURSNPLMJKFHDECDABUVSTPRMNKLHJEF SIDE 11111111111111121122222222222222 DIRECTION IOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIO changed: step 72 11100111100111011110011110011110 fail ^ ^^ ^ ^^ ^^^ ^ ^ ^^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER VURSNPLMJKFHDECDABUVSTPRMNKLHJEF SIDE 11111111111111121122222222222222 DIRECTION IOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIO changed: step 73 11100111100111011110011110011110 fail ^ ^^ ^ ^^ ^^^ ^ ^^ ^ ^^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER VURSNPLMJKFHDECDABUVSTPRMNKLHJEF SIDE 11111111111111121122222222222222 DIRECTION IOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIO changed: 1 00 step 74 11100111100111011110110010011110 fail ^ ^^ ^ ^^ ^^^ ^ ^ ^ ^^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER VURSNPLMJKFHDECDABUVSTPRMNKLHJEF SIDE 11111111111111121122222222222222 DIRECTION IOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIO changed: 0 11 step 75 11100111100111011110011110011110 fail ^ ^^ ^ ^^ ^^^ ^ ^^ ^ ^^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER VURSNPLMJKFHDECDABUVSTPRMNKLHJEF SIDE 11111111111111121122222222222222 DIRECTION IOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIO changed: 01 0 step 76 11100111100111011110011101001110 fail ^ ^^ ^ ^^ ^^^ ^ ^^ ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER VURSNPLMJKFHDECDABUVSTPRMNKLHJEF SIDE 11111111111111121122222222222222 DIRECTION IOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIO changed: 10 1 step 77 11100111100111011110011110011110 fail ^ ^^ ^ ^^ ^^^ ^ ^^ ^ ^^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER VURSNPLMJKFHDECDABUVSTPRMNKLHJEF SIDE 11111111111111121122222222222222 DIRECTION IOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIO changed: step 78 11100111100111011110011110011110 fail ^ ^^ ^ ^^ ^^^ ^ ^^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER VURSNPLMJKFHDECDABUVSTPRMNKLHJEF SIDE 11111111111111121122222222222222 DIRECTION IOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIO changed: step 79 11100111100111011110011110011110 fail ^ ^^ ^ ^^ ^^^ ^ ^^ ^ ^^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER VURSNPLMJKFHDECDABUVSTPRMNKLHJEF SIDE 11111111111111121122222222222222 DIRECTION IOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIO changed: 1 00 step 80 11100111100111011110011110110010 fail ^ ^^ ^ ^^ ^^^ ^ ^^ ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER VURSNPLMJKFHDECDABUVSTPRMNKLHJEF SIDE 11111111111111121122222222222222 DIRECTION IOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIO changed: 0 11 step 81 11100111100111011110011110011110 fail ^ ^^ ^ ^^ ^^^ ^ ^^ ^ ^^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER VURSNPLMJKFHDECDABUVSTPRMNKLHJEF SIDE 11111111111111121122222222222222 DIRECTION IOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIO changed: 0 01 step 82 11100111100111001110011110011101 fail ^ ^^ ^ ^^ ^^ ^ ^^ ^ ^^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER VURSNPLMJKFHDECDABUVSTPRMNKLHJEF SIDE 11111111111111121122222222222222 DIRECTION IOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIO changed: 1 10 step 83 11100111100111011110011110011110 fail ^ ^^ ^ ^^ ^^^ ^ ^^ ^ ^^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER VURSNPLMJKFHDECDABUVSTPRMNKLHJEF SIDE 11111111111111121122222222222222 DIRECTION IOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIO changed: step 84 11100111100111011110011110011110 fail ^ ^^ ^ ^^ ^^^ ^ ^^ ^ ^^ ^ test 50: *** FAIL *************************** 84 steps failed SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER VURSNPLMJKFHDECDABUVSTPRMNKLHJEF SIDE 11111111111111121122222222222222 DIRECTION IOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIO this fail O OIO O IO OIO O IO O IO O all fails O OIO O IO OIO O IO O IO O was hi 11111111111111111111111111111111 rising ^ ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ falling v vvvvvvvvvvvvvvvvvvvvvvvvvvvvvv was lo 0 000000000000000000000000000000 total fails 50, total passes 0 SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER VURSNPLMJKFHDECDABUVSTPRMNKLHJEF SIDE 11111111111111121122222222222222 DIRECTION IOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIO changed: 0 011000011000100001100001100001 step 1 01011000011000100001100001100001 fail ^^ ^ ^^ ^^^ ^ ^^ ^ ^^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER VURSNPLMJKFHDECDABUVSTPRMNKLHJEF SIDE 11111111111111121122222222222222 DIRECTION IOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIO changed: 0 0 0 step 2 01010000011000100001000001000001 fail ^ ^ ^^ ^^^ ^ ^ ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER VURSNPLMJKFHDECDABUVSTPRMNKLHJEF SIDE 11111111111111121122222222222222 DIRECTION IOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIO changed: 1 step 3 11010000011000100001000001000001 fail ^ ^ ^ ^^ ^^^ ^ ^ ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER VURSNPLMJKFHDECDABUVSTPRMNKLHJEF SIDE 11111111111111121122222222222222 DIRECTION IOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIO changed: 0 0 0 step 4 01010000010000000001000001000001 fail ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER VURSNPLMJKFHDECDABUVSTPRMNKLHJEF SIDE 11111111111111121122222222222222 DIRECTION IOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIO changed: step 5 01010000010000000001000001000001 fail ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER VURSNPLMJKFHDECDABUVSTPRMNKLHJEF SIDE 11111111111111121122222222222222 DIRECTION IOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIO changed: 10 1 step 6 01100100010000000001000001000001 fail ^ ^ ^ ^ ^ ^ ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER VURSNPLMJKFHDECDABUVSTPRMNKLHJEF SIDE 11111111111111121122222222222222 DIRECTION IOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIO changed: 01 0 step 7 01010000010000000001000001000001 fail ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER VURSNPLMJKFHDECDABUVSTPRMNKLHJEF SIDE 11111111111111121122222222222222 DIRECTION IOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIO changed: step 8 01010000010000000001000001000001 fail ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER VURSNPLMJKFHDECDABUVSTPRMNKLHJEF SIDE 11111111111111121122222222222222 DIRECTION IOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIO changed: 1 step 9 01011000010000000001000001000001 fail ^ ^ ^ ^ ^ ^ ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER VURSNPLMJKFHDECDABUVSTPRMNKLHJEF SIDE 11111111111111121122222222222222 DIRECTION IOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIO changed: 0 step 10 01010000010000000001000001000001 fail ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER VURSNPLMJKFHDECDABUVSTPRMNKLHJEF SIDE 11111111111111121122222222222222 DIRECTION IOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIO changed: step 11 01010000010000000001000001000001 fail ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER VURSNPLMJKFHDECDABUVSTPRMNKLHJEF SIDE 11111111111111121122222222222222 DIRECTION IOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIO changed: 11 step 12 01010011010000000001000001000001 fail ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER VURSNPLMJKFHDECDABUVSTPRMNKLHJEF SIDE 11111111111111121122222222222222 DIRECTION IOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIO changed: 00 step 13 01010000010000000001000001000001 fail ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER VURSNPLMJKFHDECDABUVSTPRMNKLHJEF SIDE 11111111111111121122222222222222 DIRECTION IOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIO changed: step 14 01010000010000000001000001000001 fail ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER VURSNPLMJKFHDECDABUVSTPRMNKLHJEF SIDE 11111111111111121122222222222222 DIRECTION IOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIO changed: 10 step 15 01010000100000000001000001000001 fail ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER VURSNPLMJKFHDECDABUVSTPRMNKLHJEF SIDE 11111111111111121122222222222222 DIRECTION IOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIO changed: 01 step 16 01010000010000000001000001000001 fail ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER VURSNPLMJKFHDECDABUVSTPRMNKLHJEF SIDE 11111111111111121122222222222222 DIRECTION IOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIO changed: step 17 01010000010000000001000001000001 fail ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER VURSNPLMJKFHDECDABUVSTPRMNKLHJEF SIDE 11111111111111121122222222222222 DIRECTION IOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIO changed: 1 step 18 01010000011000000001000001000001 fail ^ ^ ^ ^ ^ ^ ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER VURSNPLMJKFHDECDABUVSTPRMNKLHJEF SIDE 11111111111111121122222222222222 DIRECTION IOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIO changed: 0 step 19 01010000010000000001000001000001 fail ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER VURSNPLMJKFHDECDABUVSTPRMNKLHJEF SIDE 11111111111111121122222222222222 DIRECTION IOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIO changed: step 20 01010000010000000001000001000001 fail ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER VURSNPLMJKFHDECDABUVSTPRMNKLHJEF SIDE 11111111111111121122222222222222 DIRECTION IOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIO changed: 1 step 21 01010000010010000001000001000001 fail ^ ^ ^ ^ ^ ^ ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER VURSNPLMJKFHDECDABUVSTPRMNKLHJEF SIDE 11111111111111121122222222222222 DIRECTION IOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIO changed: 0 step 22 01010000010000000001000001000001 fail ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER VURSNPLMJKFHDECDABUVSTPRMNKLHJEF SIDE 11111111111111121122222222222222 DIRECTION IOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIO changed: step 23 01010000010000000001000001000001 fail ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER VURSNPLMJKFHDECDABUVSTPRMNKLHJEF SIDE 11111111111111121122222222222222 DIRECTION IOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIO changed: 1 step 24 01010000010000100001000001000001 fail ^ ^ ^ ^ ^ ^ ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER VURSNPLMJKFHDECDABUVSTPRMNKLHJEF SIDE 11111111111111121122222222222222 DIRECTION IOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIO changed: 0 step 25 01010000010000000001000001000001 fail ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER VURSNPLMJKFHDECDABUVSTPRMNKLHJEF SIDE 11111111111111121122222222222222 DIRECTION IOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIO changed: step 26 01010000010000000001000001000001 fail ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER VURSNPLMJKFHDECDABUVSTPRMNKLHJEF SIDE 11111111111111121122222222222222 DIRECTION IOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIO changed: 1 step 27 01010000010000001001000001000001 fail ^ ^ ^ ^ ^ ^ ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER VURSNPLMJKFHDECDABUVSTPRMNKLHJEF SIDE 11111111111111121122222222222222 DIRECTION IOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIO changed: 0 step 28 01010000010000000001000001000001 fail ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER VURSNPLMJKFHDECDABUVSTPRMNKLHJEF SIDE 11111111111111121122222222222222 DIRECTION IOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIO changed: step 29 01010000010000000001000001000001 fail ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER VURSNPLMJKFHDECDABUVSTPRMNKLHJEF SIDE 11111111111111121122222222222222 DIRECTION IOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIO changed: 10 1 step 30 01010000010000000010010001000001 fail ^ ^ ^ ^ ^ ^ ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER VURSNPLMJKFHDECDABUVSTPRMNKLHJEF SIDE 11111111111111121122222222222222 DIRECTION IOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIO changed: 01 0 step 31 01010000010000000001000001000001 fail ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER VURSNPLMJKFHDECDABUVSTPRMNKLHJEF SIDE 11111111111111121122222222222222 DIRECTION IOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIO changed: step 32 01010000010000000001000001000001 fail ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER VURSNPLMJKFHDECDABUVSTPRMNKLHJEF SIDE 11111111111111121122222222222222 DIRECTION IOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIO changed: 1 step 33 01010000010000000001100001000001 fail ^ ^ ^ ^ ^ ^ ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER VURSNPLMJKFHDECDABUVSTPRMNKLHJEF SIDE 11111111111111121122222222222222 DIRECTION IOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIO changed: 0 step 34 01010000010000000001000001000001 fail ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER VURSNPLMJKFHDECDABUVSTPRMNKLHJEF SIDE 11111111111111121122222222222222 DIRECTION IOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIO changed: step 35 01010000010000000001000001000001 fail ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER VURSNPLMJKFHDECDABUVSTPRMNKLHJEF SIDE 11111111111111121122222222222222 DIRECTION IOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIO changed: 11 step 36 01010000010000000001001101000001 fail ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER VURSNPLMJKFHDECDABUVSTPRMNKLHJEF SIDE 11111111111111121122222222222222 DIRECTION IOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIO changed: 00 step 37 01010000010000000001000001000001 fail ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER VURSNPLMJKFHDECDABUVSTPRMNKLHJEF SIDE 11111111111111121122222222222222 DIRECTION IOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIO changed: step 38 01010000010000000001000001000001 fail ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER VURSNPLMJKFHDECDABUVSTPRMNKLHJEF SIDE 11111111111111121122222222222222 DIRECTION IOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIO changed: 10 step 39 01010000010000000001000010000001 fail ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER VURSNPLMJKFHDECDABUVSTPRMNKLHJEF SIDE 11111111111111121122222222222222 DIRECTION IOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIO changed: 01 step 40 01010000010000000001000001000001 fail ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER VURSNPLMJKFHDECDABUVSTPRMNKLHJEF SIDE 11111111111111121122222222222222 DIRECTION IOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIO changed: step 41 01010000010000000001000001000001 fail ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER VURSNPLMJKFHDECDABUVSTPRMNKLHJEF SIDE 11111111111111121122222222222222 DIRECTION IOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIO changed: 1 step 42 01010000010000000001000001100001 fail ^ ^ ^ ^ ^ ^ ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER VURSNPLMJKFHDECDABUVSTPRMNKLHJEF SIDE 11111111111111121122222222222222 DIRECTION IOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIO changed: 0 step 43 01010000010000000001000001000001 fail ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER VURSNPLMJKFHDECDABUVSTPRMNKLHJEF SIDE 11111111111111121122222222222222 DIRECTION IOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIO changed: step 44 01010000010000000001000001000001 fail ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER VURSNPLMJKFHDECDABUVSTPRMNKLHJEF SIDE 11111111111111121122222222222222 DIRECTION IOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIO changed: 1 step 45 01010000010000000001000001001001 fail ^ ^ ^ ^ ^ ^ ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER VURSNPLMJKFHDECDABUVSTPRMNKLHJEF SIDE 11111111111111121122222222222222 DIRECTION IOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIO changed: 0 step 46 01010000010000000001000001000001 fail ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER VURSNPLMJKFHDECDABUVSTPRMNKLHJEF SIDE 11111111111111121122222222222222 DIRECTION IOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIO changed: step 47 01010000010000000001000001000001 fail ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER VURSNPLMJKFHDECDABUVSTPRMNKLHJEF SIDE 11111111111111121122222222222222 DIRECTION IOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIO changed: 10 step 48 01010000010000000001000001000010 fail ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER VURSNPLMJKFHDECDABUVSTPRMNKLHJEF SIDE 11111111111111121122222222222222 DIRECTION IOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIO changed: 01 step 49 01010000010000000001000001000001 fail ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER VURSNPLMJKFHDECDABUVSTPRMNKLHJEF SIDE 11111111111111121122222222222222 DIRECTION IOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIO changed: step 50 01010000010000000001000001000001 fail ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER VURSNPLMJKFHDECDABUVSTPRMNKLHJEF SIDE 11111111111111121122222222222222 DIRECTION IOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIO changed: 1 10 11110 111 11110 11110 11110 step 51 11100111100111011110011110011110 fail ^ ^^ ^ ^^ ^^^ ^ ^^ ^ ^^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER VURSNPLMJKFHDECDABUVSTPRMNKLHJEF SIDE 11111111111111121122222222222222 DIRECTION IOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIO changed: 0 step 52 01100111100111011110011110011110 fail ^^ ^ ^^ ^^^ ^ ^^ ^ ^^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER VURSNPLMJKFHDECDABUVSTPRMNKLHJEF SIDE 11111111111111121122222222222222 DIRECTION IOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIO changed: 1 step 53 11100111100111011110011110011110 fail ^ ^^ ^ ^^ ^^^ ^ ^^ ^ ^^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER VURSNPLMJKFHDECDABUVSTPRMNKLHJEF SIDE 11111111111111121122222222222222 DIRECTION IOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIO changed: 0 0 step 54 11000011100111011110011110011110 fail ^ ^^ ^ ^^ ^^^ ^ ^^ ^ ^^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER VURSNPLMJKFHDECDABUVSTPRMNKLHJEF SIDE 11111111111111121122222222222222 DIRECTION IOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIO changed: 1 1 step 55 11100111100111011110011110011110 fail ^ ^^ ^ ^^ ^^^ ^ ^^ ^ ^^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER VURSNPLMJKFHDECDABUVSTPRMNKLHJEF SIDE 11111111111111121122222222222222 DIRECTION IOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIO changed: step 56 11100111100111011110011110011110 fail ^ ^ ^^ ^^^ ^ ^^ ^ ^^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER VURSNPLMJKFHDECDABUVSTPRMNKLHJEF SIDE 11111111111111121122222222222222 DIRECTION IOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIO changed: step 57 11100111100111011110011110011110 fail ^ ^^ ^ ^^ ^^^ ^ ^^ ^ ^^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER VURSNPLMJKFHDECDABUVSTPRMNKLHJEF SIDE 11111111111111121122222222222222 DIRECTION IOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIO changed: 1 00 step 58 11101100100111011110011110011110 fail ^ ^ ^ ^^ ^^^ ^ ^^ ^ ^^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER VURSNPLMJKFHDECDABUVSTPRMNKLHJEF SIDE 11111111111111121122222222222222 DIRECTION IOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIO changed: 0 11 step 59 11100111100111011110011110011110 fail ^ ^^ ^ ^^ ^^^ ^ ^^ ^ ^^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER VURSNPLMJKFHDECDABUVSTPRMNKLHJEF SIDE 11111111111111121122222222222222 DIRECTION IOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIO changed: 01 0 step 60 11100111010011011110011110011110 fail ^ ^^ ^ ^ ^^^ ^ ^^ ^ ^^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER VURSNPLMJKFHDECDABUVSTPRMNKLHJEF SIDE 11111111111111121122222222222222 DIRECTION IOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIO changed: 10 1 step 61 11100111100111011110011110011110 fail ^ ^^ ^ ^^ ^^^ ^ ^^ ^ ^^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER VURSNPLMJKFHDECDABUVSTPRMNKLHJEF SIDE 11111111111111121122222222222222 DIRECTION IOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIO changed: step 62 11100111100111011110011110011110 fail ^ ^^ ^ ^^^ ^ ^^ ^ ^^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER VURSNPLMJKFHDECDABUVSTPRMNKLHJEF SIDE 11111111111111121122222222222222 DIRECTION IOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIO changed: step 63 11100111100111011110011110011110 fail ^ ^^ ^ ^^ ^^^ ^ ^^ ^ ^^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER VURSNPLMJKFHDECDABUVSTPRMNKLHJEF SIDE 11111111111111121122222222222222 DIRECTION IOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIO changed: 1 00 step 64 11100111101100011110011110011110 fail ^ ^^ ^ ^ ^^^ ^ ^^ ^ ^^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER VURSNPLMJKFHDECDABUVSTPRMNKLHJEF SIDE 11111111111111121122222222222222 DIRECTION IOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIO changed: 0 11 step 65 11100111100111011110011110011110 fail ^ ^^ ^ ^^ ^^^ ^ ^^ ^ ^^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER VURSNPLMJKFHDECDABUVSTPRMNKLHJEF SIDE 11111111111111121122222222222222 DIRECTION IOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIO changed: step 66 11100111100111011110011110011110 fail ^ ^^ ^ ^^ ^ ^ ^^ ^ ^^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER VURSNPLMJKFHDECDABUVSTPRMNKLHJEF SIDE 11111111111111121122222222222222 DIRECTION IOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIO changed: step 67 11100111100111011110011110011110 fail ^ ^^ ^ ^^ ^^^ ^ ^^ ^ ^^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER VURSNPLMJKFHDECDABUVSTPRMNKLHJEF SIDE 11111111111111121122222222222222 DIRECTION IOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIO changed: 1 00 step 68 11100111100111110010011110011110 fail ^ ^^ ^ ^^ ^ ^ ^ ^^ ^ ^^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER VURSNPLMJKFHDECDABUVSTPRMNKLHJEF SIDE 11111111111111121122222222222222 DIRECTION IOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIO changed: 0 11 step 69 11100111100111011110011110011110 fail ^ ^^ ^ ^^ ^^^ ^ ^^ ^ ^^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER VURSNPLMJKFHDECDABUVSTPRMNKLHJEF SIDE 11111111111111121122222222222222 DIRECTION IOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIO changed: 01 0 step 70 11100111100111011101001110011110 fail ^ ^^ ^ ^^ ^^^ ^ ^ ^ ^^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER VURSNPLMJKFHDECDABUVSTPRMNKLHJEF SIDE 11111111111111121122222222222222 DIRECTION IOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIO changed: 10 1 step 71 11100111100111011110011110011110 fail ^ ^^ ^ ^^ ^^^ ^ ^^ ^ ^^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER VURSNPLMJKFHDECDABUVSTPRMNKLHJEF SIDE 11111111111111121122222222222222 DIRECTION IOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIO changed: step 72 11100111100111011110011110011110 fail ^ ^^ ^ ^^ ^^^ ^ ^ ^^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER VURSNPLMJKFHDECDABUVSTPRMNKLHJEF SIDE 11111111111111121122222222222222 DIRECTION IOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIO changed: step 73 11100111100111011110011110011110 fail ^ ^^ ^ ^^ ^^^ ^ ^^ ^ ^^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER VURSNPLMJKFHDECDABUVSTPRMNKLHJEF SIDE 11111111111111121122222222222222 DIRECTION IOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIO changed: 1 00 step 74 11100111100111011110110010011110 fail ^ ^^ ^ ^^ ^^^ ^ ^ ^ ^^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER VURSNPLMJKFHDECDABUVSTPRMNKLHJEF SIDE 11111111111111121122222222222222 DIRECTION IOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIO changed: 0 11 step 75 11100111100111011110011110011110 fail ^ ^^ ^ ^^ ^^^ ^ ^^ ^ ^^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER VURSNPLMJKFHDECDABUVSTPRMNKLHJEF SIDE 11111111111111121122222222222222 DIRECTION IOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIO changed: 01 0 step 76 11100111100111011110011101001110 fail ^ ^^ ^ ^^ ^^^ ^ ^^ ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER VURSNPLMJKFHDECDABUVSTPRMNKLHJEF SIDE 11111111111111121122222222222222 DIRECTION IOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIO changed: 10 1 step 77 11100111100111011110011110011110 fail ^ ^^ ^ ^^ ^^^ ^ ^^ ^ ^^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER VURSNPLMJKFHDECDABUVSTPRMNKLHJEF SIDE 11111111111111121122222222222222 DIRECTION IOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIO changed: step 78 11100111100111011110011110011110 fail ^ ^^ ^ ^^ ^^^ ^ ^^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER VURSNPLMJKFHDECDABUVSTPRMNKLHJEF SIDE 11111111111111121122222222222222 DIRECTION IOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIO changed: step 79 11100111100111011110011110011110 fail ^ ^^ ^ ^^ ^^^ ^ ^^ ^ ^^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER VURSNPLMJKFHDECDABUVSTPRMNKLHJEF SIDE 11111111111111121122222222222222 DIRECTION IOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIO changed: 1 00 step 80 11100111100111011110011110110010 fail ^ ^^ ^ ^^ ^^^ ^ ^^ ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER VURSNPLMJKFHDECDABUVSTPRMNKLHJEF SIDE 11111111111111121122222222222222 DIRECTION IOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIO changed: 0 11 step 81 11100111100111011110011110011110 fail ^ ^^ ^ ^^ ^^^ ^ ^^ ^ ^^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER VURSNPLMJKFHDECDABUVSTPRMNKLHJEF SIDE 11111111111111121122222222222222 DIRECTION IOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIO changed: 0 01 step 82 11100111100111001110011110011101 fail ^ ^^ ^ ^^ ^^ ^ ^^ ^ ^^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER VURSNPLMJKFHDECDABUVSTPRMNKLHJEF SIDE 11111111111111121122222222222222 DIRECTION IOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIO changed: 1 10 step 83 11100111100111011110011110011110 fail ^ ^^ ^ ^^ ^^^ ^ ^^ ^ ^^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER VURSNPLMJKFHDECDABUVSTPRMNKLHJEF SIDE 11111111111111121122222222222222 DIRECTION IOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIO changed: step 84 11100111100111011110011110011110 fail ^ ^^ ^ ^^ ^^^ ^ ^^ ^ ^^ ^ test 51: *** FAIL *************************** 84 steps failed SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER VURSNPLMJKFHDECDABUVSTPRMNKLHJEF SIDE 11111111111111121122222222222222 DIRECTION IOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIO this fail O OIO O IO OIO O IO O IO O all fails O OIO O IO OIO O IO O IO O was hi 11111111111111111111111111111111 rising ^ ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ falling v vvvvvvvvvvvvvvvvvvvvvvvvvvvvvv was lo 0 000000000000000000000000000000 total fails 51, total passes 0 SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER VURSNPLMJKFHDECDABUVSTPRMNKLHJEF SIDE 11111111111111121122222222222222 DIRECTION IOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIO changed: 0 011000011000100001100001100001 step 1 01011000011000100001100001100001 fail ^^ ^ ^^ ^^^ ^ ^^ ^ ^^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER VURSNPLMJKFHDECDABUVSTPRMNKLHJEF SIDE 11111111111111121122222222222222 DIRECTION IOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIO changed: 0 0 0 step 2 01010000011000100001000001000001 fail ^ ^ ^^ ^^^ ^ ^ ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER VURSNPLMJKFHDECDABUVSTPRMNKLHJEF SIDE 11111111111111121122222222222222 DIRECTION IOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIO changed: 1 step 3 11010000011000100001000001000001 fail ^ ^ ^ ^^ ^^^ ^ ^ ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER VURSNPLMJKFHDECDABUVSTPRMNKLHJEF SIDE 11111111111111121122222222222222 DIRECTION IOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIO changed: 0 0 0 step 4 01010000010000000001000001000001 fail ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER VURSNPLMJKFHDECDABUVSTPRMNKLHJEF SIDE 11111111111111121122222222222222 DIRECTION IOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIO changed: step 5 01010000010000000001000001000001 fail ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER VURSNPLMJKFHDECDABUVSTPRMNKLHJEF SIDE 11111111111111121122222222222222 DIRECTION IOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIO changed: 10 1 step 6 01100100010000000001000001000001 fail ^ ^ ^ ^ ^ ^ ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER VURSNPLMJKFHDECDABUVSTPRMNKLHJEF SIDE 11111111111111121122222222222222 DIRECTION IOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIO changed: 01 0 step 7 01010000010000000001000001000001 fail ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER VURSNPLMJKFHDECDABUVSTPRMNKLHJEF SIDE 11111111111111121122222222222222 DIRECTION IOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIO changed: step 8 01010000010000000001000001000001 fail ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER VURSNPLMJKFHDECDABUVSTPRMNKLHJEF SIDE 11111111111111121122222222222222 DIRECTION IOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIO changed: 1 step 9 01011000010000000001000001000001 fail ^ ^ ^ ^ ^ ^ ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER VURSNPLMJKFHDECDABUVSTPRMNKLHJEF SIDE 11111111111111121122222222222222 DIRECTION IOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIO changed: 0 step 10 01010000010000000001000001000001 fail ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER VURSNPLMJKFHDECDABUVSTPRMNKLHJEF SIDE 11111111111111121122222222222222 DIRECTION IOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIO changed: step 11 01010000010000000001000001000001 fail ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER VURSNPLMJKFHDECDABUVSTPRMNKLHJEF SIDE 11111111111111121122222222222222 DIRECTION IOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIO changed: 11 step 12 01010011010000000001000001000001 fail ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER VURSNPLMJKFHDECDABUVSTPRMNKLHJEF SIDE 11111111111111121122222222222222 DIRECTION IOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIO changed: 00 step 13 01010000010000000001000001000001 fail ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER VURSNPLMJKFHDECDABUVSTPRMNKLHJEF SIDE 11111111111111121122222222222222 DIRECTION IOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIO changed: step 14 01010000010000000001000001000001 fail ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER VURSNPLMJKFHDECDABUVSTPRMNKLHJEF SIDE 11111111111111121122222222222222 DIRECTION IOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIO changed: 10 step 15 01010000100000000001000001000001 fail ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER VURSNPLMJKFHDECDABUVSTPRMNKLHJEF SIDE 11111111111111121122222222222222 DIRECTION IOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIO changed: 01 step 16 01010000010000000001000001000001 fail ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER VURSNPLMJKFHDECDABUVSTPRMNKLHJEF SIDE 11111111111111121122222222222222 DIRECTION IOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIO changed: step 17 01010000010000000001000001000001 fail ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER VURSNPLMJKFHDECDABUVSTPRMNKLHJEF SIDE 11111111111111121122222222222222 DIRECTION IOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIO changed: 1 step 18 01010000011000000001000001000001 fail ^ ^ ^ ^ ^ ^ ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER VURSNPLMJKFHDECDABUVSTPRMNKLHJEF SIDE 11111111111111121122222222222222 DIRECTION IOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIO changed: 0 step 19 01010000010000000001000001000001 fail ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER VURSNPLMJKFHDECDABUVSTPRMNKLHJEF SIDE 11111111111111121122222222222222 DIRECTION IOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIO changed: step 20 01010000010000000001000001000001 fail ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER VURSNPLMJKFHDECDABUVSTPRMNKLHJEF SIDE 11111111111111121122222222222222 DIRECTION IOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIO changed: 1 step 21 01010000010010000001000001000001 fail ^ ^ ^ ^ ^ ^ ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER VURSNPLMJKFHDECDABUVSTPRMNKLHJEF SIDE 11111111111111121122222222222222 DIRECTION IOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIO changed: 0 step 22 01010000010000000001000001000001 fail ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER VURSNPLMJKFHDECDABUVSTPRMNKLHJEF SIDE 11111111111111121122222222222222 DIRECTION IOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIO changed: step 23 01010000010000000001000001000001 fail ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER VURSNPLMJKFHDECDABUVSTPRMNKLHJEF SIDE 11111111111111121122222222222222 DIRECTION IOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIO changed: 1 step 24 01010000010000100001000001000001 fail ^ ^ ^ ^ ^ ^ ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER VURSNPLMJKFHDECDABUVSTPRMNKLHJEF SIDE 11111111111111121122222222222222 DIRECTION IOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIO changed: 0 step 25 01010000010000000001000001000001 fail ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER VURSNPLMJKFHDECDABUVSTPRMNKLHJEF SIDE 11111111111111121122222222222222 DIRECTION IOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIO changed: step 26 01010000010000000001000001000001 fail ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER VURSNPLMJKFHDECDABUVSTPRMNKLHJEF SIDE 11111111111111121122222222222222 DIRECTION IOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIO changed: 1 step 27 01010000010000001001000001000001 fail ^ ^ ^ ^ ^ ^ ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER VURSNPLMJKFHDECDABUVSTPRMNKLHJEF SIDE 11111111111111121122222222222222 DIRECTION IOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIO changed: 0 step 28 01010000010000000001000001000001 fail ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER VURSNPLMJKFHDECDABUVSTPRMNKLHJEF SIDE 11111111111111121122222222222222 DIRECTION IOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIO changed: step 29 01010000010000000001000001000001 fail ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER VURSNPLMJKFHDECDABUVSTPRMNKLHJEF SIDE 11111111111111121122222222222222 DIRECTION IOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIO changed: 10 1 step 30 01010000010000000010010001000001 fail ^ ^ ^ ^ ^ ^ ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER VURSNPLMJKFHDECDABUVSTPRMNKLHJEF SIDE 11111111111111121122222222222222 DIRECTION IOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIO changed: 01 0 step 31 01010000010000000001000001000001 fail ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER VURSNPLMJKFHDECDABUVSTPRMNKLHJEF SIDE 11111111111111121122222222222222 DIRECTION IOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIO changed: step 32 01010000010000000001000001000001 fail ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER VURSNPLMJKFHDECDABUVSTPRMNKLHJEF SIDE 11111111111111121122222222222222 DIRECTION IOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIO changed: 1 step 33 01010000010000000001100001000001 fail ^ ^ ^ ^ ^ ^ ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER VURSNPLMJKFHDECDABUVSTPRMNKLHJEF SIDE 11111111111111121122222222222222 DIRECTION IOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIO changed: 0 step 34 01010000010000000001000001000001 fail ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER VURSNPLMJKFHDECDABUVSTPRMNKLHJEF SIDE 11111111111111121122222222222222 DIRECTION IOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIO changed: step 35 01010000010000000001000001000001 fail ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER VURSNPLMJKFHDECDABUVSTPRMNKLHJEF SIDE 11111111111111121122222222222222 DIRECTION IOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIO changed: 11 step 36 01010000010000000001001101000001 fail ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER VURSNPLMJKFHDECDABUVSTPRMNKLHJEF SIDE 11111111111111121122222222222222 DIRECTION IOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIO changed: 00 step 37 01010000010000000001000001000001 fail ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER VURSNPLMJKFHDECDABUVSTPRMNKLHJEF SIDE 11111111111111121122222222222222 DIRECTION IOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIO changed: step 38 01010000010000000001000001000001 fail ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER VURSNPLMJKFHDECDABUVSTPRMNKLHJEF SIDE 11111111111111121122222222222222 DIRECTION IOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIO changed: 10 step 39 01010000010000000001000010000001 fail ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER VURSNPLMJKFHDECDABUVSTPRMNKLHJEF SIDE 11111111111111121122222222222222 DIRECTION IOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIO changed: 01 step 40 01010000010000000001000001000001 fail ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER VURSNPLMJKFHDECDABUVSTPRMNKLHJEF SIDE 11111111111111121122222222222222 DIRECTION IOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIO changed: step 41 01010000010000000001000001000001 fail ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER VURSNPLMJKFHDECDABUVSTPRMNKLHJEF SIDE 11111111111111121122222222222222 DIRECTION IOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIO changed: 1 step 42 01010000010000000001000001100001 fail ^ ^ ^ ^ ^ ^ ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER VURSNPLMJKFHDECDABUVSTPRMNKLHJEF SIDE 11111111111111121122222222222222 DIRECTION IOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIO changed: 0 step 43 01010000010000000001000001000001 fail ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER VURSNPLMJKFHDECDABUVSTPRMNKLHJEF SIDE 11111111111111121122222222222222 DIRECTION IOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIO changed: step 44 01010000010000000001000001000001 fail ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER VURSNPLMJKFHDECDABUVSTPRMNKLHJEF SIDE 11111111111111121122222222222222 DIRECTION IOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIO changed: 1 step 45 01010000010000000001000001001001 fail ^ ^ ^ ^ ^ ^ ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER VURSNPLMJKFHDECDABUVSTPRMNKLHJEF SIDE 11111111111111121122222222222222 DIRECTION IOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIO changed: 0 step 46 01010000010000000001000001000001 fail ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER VURSNPLMJKFHDECDABUVSTPRMNKLHJEF SIDE 11111111111111121122222222222222 DIRECTION IOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIO changed: step 47 01010000010000000001000001000001 fail ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER VURSNPLMJKFHDECDABUVSTPRMNKLHJEF SIDE 11111111111111121122222222222222 DIRECTION IOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIO changed: 10 step 48 01010000010000000001000001000010 fail ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER VURSNPLMJKFHDECDABUVSTPRMNKLHJEF SIDE 11111111111111121122222222222222 DIRECTION IOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIO changed: 01 step 49 01010000010000000001000001000001 fail ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER VURSNPLMJKFHDECDABUVSTPRMNKLHJEF SIDE 11111111111111121122222222222222 DIRECTION IOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIO changed: step 50 01010000010000000001000001000001 fail ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER VURSNPLMJKFHDECDABUVSTPRMNKLHJEF SIDE 11111111111111121122222222222222 DIRECTION IOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIO changed: 1 10 11110 111 11110 11110 11110 step 51 11100111100111011110011110011110 fail ^ ^^ ^ ^^ ^^^ ^ ^^ ^ ^^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER VURSNPLMJKFHDECDABUVSTPRMNKLHJEF SIDE 11111111111111121122222222222222 DIRECTION IOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIO changed: 0 step 52 01100111100111011110011110011110 fail ^^ ^ ^^ ^^^ ^ ^^ ^ ^^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER VURSNPLMJKFHDECDABUVSTPRMNKLHJEF SIDE 11111111111111121122222222222222 DIRECTION IOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIO changed: 1 step 53 11100111100111011110011110011110 fail ^ ^^ ^ ^^ ^^^ ^ ^^ ^ ^^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER VURSNPLMJKFHDECDABUVSTPRMNKLHJEF SIDE 11111111111111121122222222222222 DIRECTION IOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIO changed: 0 0 step 54 11000011100111011110011110011110 fail ^ ^^ ^ ^^ ^^^ ^ ^^ ^ ^^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER VURSNPLMJKFHDECDABUVSTPRMNKLHJEF SIDE 11111111111111121122222222222222 DIRECTION IOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIO changed: 1 1 step 55 11100111100111011110011110011110 fail ^ ^^ ^ ^^ ^^^ ^ ^^ ^ ^^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER VURSNPLMJKFHDECDABUVSTPRMNKLHJEF SIDE 11111111111111121122222222222222 DIRECTION IOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIO changed: step 56 11100111100111011110011110011110 fail ^ ^ ^^ ^^^ ^ ^^ ^ ^^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER VURSNPLMJKFHDECDABUVSTPRMNKLHJEF SIDE 11111111111111121122222222222222 DIRECTION IOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIO changed: step 57 11100111100111011110011110011110 fail ^ ^^ ^ ^^ ^^^ ^ ^^ ^ ^^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER VURSNPLMJKFHDECDABUVSTPRMNKLHJEF SIDE 11111111111111121122222222222222 DIRECTION IOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIO changed: 1 00 step 58 11101100100111011110011110011110 fail ^ ^ ^ ^^ ^^^ ^ ^^ ^ ^^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER VURSNPLMJKFHDECDABUVSTPRMNKLHJEF SIDE 11111111111111121122222222222222 DIRECTION IOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIO changed: 0 11 step 59 11100111100111011110011110011110 fail ^ ^^ ^ ^^ ^^^ ^ ^^ ^ ^^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER VURSNPLMJKFHDECDABUVSTPRMNKLHJEF SIDE 11111111111111121122222222222222 DIRECTION IOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIO changed: 01 0 step 60 11100111010011011110011110011110 fail ^ ^^ ^ ^ ^^^ ^ ^^ ^ ^^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER VURSNPLMJKFHDECDABUVSTPRMNKLHJEF SIDE 11111111111111121122222222222222 DIRECTION IOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIO changed: 10 1 step 61 11100111100111011110011110011110 fail ^ ^^ ^ ^^ ^^^ ^ ^^ ^ ^^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER VURSNPLMJKFHDECDABUVSTPRMNKLHJEF SIDE 11111111111111121122222222222222 DIRECTION IOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIO changed: step 62 11100111100111011110011110011110 fail ^ ^^ ^ ^^^ ^ ^^ ^ ^^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER VURSNPLMJKFHDECDABUVSTPRMNKLHJEF SIDE 11111111111111121122222222222222 DIRECTION IOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIO changed: step 63 11100111100111011110011110011110 fail ^ ^^ ^ ^^ ^^^ ^ ^^ ^ ^^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER VURSNPLMJKFHDECDABUVSTPRMNKLHJEF SIDE 11111111111111121122222222222222 DIRECTION IOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIO changed: 1 00 step 64 11100111101100011110011110011110 fail ^ ^^ ^ ^ ^^^ ^ ^^ ^ ^^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER VURSNPLMJKFHDECDABUVSTPRMNKLHJEF SIDE 11111111111111121122222222222222 DIRECTION IOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIO changed: 0 11 step 65 11100111100111011110011110011110 fail ^ ^^ ^ ^^ ^^^ ^ ^^ ^ ^^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER VURSNPLMJKFHDECDABUVSTPRMNKLHJEF SIDE 11111111111111121122222222222222 DIRECTION IOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIO changed: step 66 11100111100111011110011110011110 fail ^ ^^ ^ ^^ ^ ^ ^^ ^ ^^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER VURSNPLMJKFHDECDABUVSTPRMNKLHJEF SIDE 11111111111111121122222222222222 DIRECTION IOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIO changed: step 67 11100111100111011110011110011110 fail ^ ^^ ^ ^^ ^^^ ^ ^^ ^ ^^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER VURSNPLMJKFHDECDABUVSTPRMNKLHJEF SIDE 11111111111111121122222222222222 DIRECTION IOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIO changed: 1 00 step 68 11100111100111110010011110011110 fail ^ ^^ ^ ^^ ^ ^ ^ ^^ ^ ^^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER VURSNPLMJKFHDECDABUVSTPRMNKLHJEF SIDE 11111111111111121122222222222222 DIRECTION IOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIO changed: 0 11 step 69 11100111100111011110011110011110 fail ^ ^^ ^ ^^ ^^^ ^ ^^ ^ ^^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER VURSNPLMJKFHDECDABUVSTPRMNKLHJEF SIDE 11111111111111121122222222222222 DIRECTION IOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIO changed: 01 0 step 70 11100111100111011101001110011110 fail ^ ^^ ^ ^^ ^^^ ^ ^ ^ ^^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER VURSNPLMJKFHDECDABUVSTPRMNKLHJEF SIDE 11111111111111121122222222222222 DIRECTION IOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIO changed: 10 1 step 71 11100111100111011110011110011110 fail ^ ^^ ^ ^^ ^^^ ^ ^^ ^ ^^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER VURSNPLMJKFHDECDABUVSTPRMNKLHJEF SIDE 11111111111111121122222222222222 DIRECTION IOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIO changed: step 72 11100111100111011110011110011110 fail ^ ^^ ^ ^^ ^^^ ^ ^ ^^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER VURSNPLMJKFHDECDABUVSTPRMNKLHJEF SIDE 11111111111111121122222222222222 DIRECTION IOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIO changed: step 73 11100111100111011110011110011110 fail ^ ^^ ^ ^^ ^^^ ^ ^^ ^ ^^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER VURSNPLMJKFHDECDABUVSTPRMNKLHJEF SIDE 11111111111111121122222222222222 DIRECTION IOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIO changed: 1 00 step 74 11100111100111011110110010011110 fail ^ ^^ ^ ^^ ^^^ ^ ^ ^ ^^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER VURSNPLMJKFHDECDABUVSTPRMNKLHJEF SIDE 11111111111111121122222222222222 DIRECTION IOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIO changed: 0 11 step 75 11100111100111011110011110011110 fail ^ ^^ ^ ^^ ^^^ ^ ^^ ^ ^^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER VURSNPLMJKFHDECDABUVSTPRMNKLHJEF SIDE 11111111111111121122222222222222 DIRECTION IOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIO changed: 01 0 step 76 11100111100111011110011101001110 fail ^ ^^ ^ ^^ ^^^ ^ ^^ ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER VURSNPLMJKFHDECDABUVSTPRMNKLHJEF SIDE 11111111111111121122222222222222 DIRECTION IOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIO changed: 10 1 step 77 11100111100111011110011110011110 fail ^ ^^ ^ ^^ ^^^ ^ ^^ ^ ^^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER VURSNPLMJKFHDECDABUVSTPRMNKLHJEF SIDE 11111111111111121122222222222222 DIRECTION IOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIO changed: step 78 11100111100111011110011110011110 fail ^ ^^ ^ ^^ ^^^ ^ ^^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER VURSNPLMJKFHDECDABUVSTPRMNKLHJEF SIDE 11111111111111121122222222222222 DIRECTION IOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIO changed: step 79 11100111100111011110011110011110 fail ^ ^^ ^ ^^ ^^^ ^ ^^ ^ ^^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER VURSNPLMJKFHDECDABUVSTPRMNKLHJEF SIDE 11111111111111121122222222222222 DIRECTION IOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIO changed: 1 00 step 80 11100111100111011110011110110010 fail ^ ^^ ^ ^^ ^^^ ^ ^^ ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER VURSNPLMJKFHDECDABUVSTPRMNKLHJEF SIDE 11111111111111121122222222222222 DIRECTION IOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIO changed: 0 11 step 81 11100111100111011110011110011110 fail ^ ^^ ^ ^^ ^^^ ^ ^^ ^ ^^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER VURSNPLMJKFHDECDABUVSTPRMNKLHJEF SIDE 11111111111111121122222222222222 DIRECTION IOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIO changed: 0 01 step 82 11100111100111001110011110011101 fail ^ ^^ ^ ^^ ^^ ^ ^^ ^ ^^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER VURSNPLMJKFHDECDABUVSTPRMNKLHJEF SIDE 11111111111111121122222222222222 DIRECTION IOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIO changed: 1 10 step 83 11100111100111011110011110011110 fail ^ ^^ ^ ^^ ^^^ ^ ^^ ^ ^^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER VURSNPLMJKFHDECDABUVSTPRMNKLHJEF SIDE 11111111111111121122222222222222 DIRECTION IOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIO changed: step 84 11100111100111011110011110011110 fail ^ ^^ ^ ^^ ^^^ ^ ^^ ^ ^^ ^ test 52: *** FAIL *************************** 84 steps failed SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER VURSNPLMJKFHDECDABUVSTPRMNKLHJEF SIDE 11111111111111121122222222222222 DIRECTION IOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIO this fail O OIO O IO OIO O IO O IO O all fails O OIO O IO OIO O IO O IO O was hi 11111111111111111111111111111111 rising ^ ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ falling v vvvvvvvvvvvvvvvvvvvvvvvvvvvvvv was lo 0 000000000000000000000000000000 total fails 52, total passes 0 SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER VURSNPLMJKFHDECDABUVSTPRMNKLHJEF SIDE 11111111111111121122222222222222 DIRECTION IOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIO changed: 0 011000011000100001100001100001 step 1 01011000011000100001100001100001 fail ^^ ^ ^^ ^^^ ^ ^^ ^ ^^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER VURSNPLMJKFHDECDABUVSTPRMNKLHJEF SIDE 11111111111111121122222222222222 DIRECTION IOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIO changed: 0 0 0 step 2 01010000011000100001000001000001 fail ^ ^ ^^ ^^^ ^ ^ ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER VURSNPLMJKFHDECDABUVSTPRMNKLHJEF SIDE 11111111111111121122222222222222 DIRECTION IOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIO changed: 1 step 3 11010000011000100001000001000001 fail ^ ^ ^ ^^ ^^^ ^ ^ ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER VURSNPLMJKFHDECDABUVSTPRMNKLHJEF SIDE 11111111111111121122222222222222 DIRECTION IOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIO changed: 0 0 0 step 4 01010000010000000001000001000001 fail ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER VURSNPLMJKFHDECDABUVSTPRMNKLHJEF SIDE 11111111111111121122222222222222 DIRECTION IOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIO changed: step 5 01010000010000000001000001000001 fail ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER VURSNPLMJKFHDECDABUVSTPRMNKLHJEF SIDE 11111111111111121122222222222222 DIRECTION IOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIO changed: 10 1 step 6 01100100010000000001000001000001 fail ^ ^ ^ ^ ^ ^ ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER VURSNPLMJKFHDECDABUVSTPRMNKLHJEF SIDE 11111111111111121122222222222222 DIRECTION IOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIO changed: 01 0 step 7 01010000010000000001000001000001 fail ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER VURSNPLMJKFHDECDABUVSTPRMNKLHJEF SIDE 11111111111111121122222222222222 DIRECTION IOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIO changed: step 8 01010000010000000001000001000001 fail ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER VURSNPLMJKFHDECDABUVSTPRMNKLHJEF SIDE 11111111111111121122222222222222 DIRECTION IOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIO changed: 1 step 9 01011000010000000001000001000001 fail ^ ^ ^ ^ ^ ^ ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER VURSNPLMJKFHDECDABUVSTPRMNKLHJEF SIDE 11111111111111121122222222222222 DIRECTION IOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIO changed: 0 step 10 01010000010000000001000001000001 fail ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER VURSNPLMJKFHDECDABUVSTPRMNKLHJEF SIDE 11111111111111121122222222222222 DIRECTION IOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIO changed: step 11 01010000010000000001000001000001 fail ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER VURSNPLMJKFHDECDABUVSTPRMNKLHJEF SIDE 11111111111111121122222222222222 DIRECTION IOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIO changed: 11 step 12 01010011010000000001000001000001 fail ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER VURSNPLMJKFHDECDABUVSTPRMNKLHJEF SIDE 11111111111111121122222222222222 DIRECTION IOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIO changed: 00 step 13 01010000010000000001000001000001 fail ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER VURSNPLMJKFHDECDABUVSTPRMNKLHJEF SIDE 11111111111111121122222222222222 DIRECTION IOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIO changed: step 14 01010000010000000001000001000001 fail ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER VURSNPLMJKFHDECDABUVSTPRMNKLHJEF SIDE 11111111111111121122222222222222 DIRECTION IOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIO changed: 10 step 15 01010000100000000001000001000001 fail ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER VURSNPLMJKFHDECDABUVSTPRMNKLHJEF SIDE 11111111111111121122222222222222 DIRECTION IOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIO changed: 01 step 16 01010000010000000001000001000001 fail ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER VURSNPLMJKFHDECDABUVSTPRMNKLHJEF SIDE 11111111111111121122222222222222 DIRECTION IOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIO changed: step 17 01010000010000000001000001000001 fail ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER VURSNPLMJKFHDECDABUVSTPRMNKLHJEF SIDE 11111111111111121122222222222222 DIRECTION IOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIO changed: 1 step 18 01010000011000000001000001000001 fail ^ ^ ^ ^ ^ ^ ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER VURSNPLMJKFHDECDABUVSTPRMNKLHJEF SIDE 11111111111111121122222222222222 DIRECTION IOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIO changed: 0 step 19 01010000010000000001000001000001 fail ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER VURSNPLMJKFHDECDABUVSTPRMNKLHJEF SIDE 11111111111111121122222222222222 DIRECTION IOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIO changed: step 20 01010000010000000001000001000001 fail ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER VURSNPLMJKFHDECDABUVSTPRMNKLHJEF SIDE 11111111111111121122222222222222 DIRECTION IOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIO changed: 1 step 21 01010000010010000001000001000001 fail ^ ^ ^ ^ ^ ^ ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER VURSNPLMJKFHDECDABUVSTPRMNKLHJEF SIDE 11111111111111121122222222222222 DIRECTION IOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIO changed: 0 step 22 01010000010000000001000001000001 fail ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER VURSNPLMJKFHDECDABUVSTPRMNKLHJEF SIDE 11111111111111121122222222222222 DIRECTION IOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIO changed: step 23 01010000010000000001000001000001 fail ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER VURSNPLMJKFHDECDABUVSTPRMNKLHJEF SIDE 11111111111111121122222222222222 DIRECTION IOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIO changed: 1 step 24 01010000010000100001000001000001 fail ^ ^ ^ ^ ^ ^ ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER VURSNPLMJKFHDECDABUVSTPRMNKLHJEF SIDE 11111111111111121122222222222222 DIRECTION IOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIO changed: 0 step 25 01010000010000000001000001000001 fail ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER VURSNPLMJKFHDECDABUVSTPRMNKLHJEF SIDE 11111111111111121122222222222222 DIRECTION IOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIO changed: step 26 01010000010000000001000001000001 fail ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER VURSNPLMJKFHDECDABUVSTPRMNKLHJEF SIDE 11111111111111121122222222222222 DIRECTION IOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIO changed: 1 step 27 01010000010000001001000001000001 fail ^ ^ ^ ^ ^ ^ ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER VURSNPLMJKFHDECDABUVSTPRMNKLHJEF SIDE 11111111111111121122222222222222 DIRECTION IOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIO changed: 0 step 28 01010000010000000001000001000001 fail ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER VURSNPLMJKFHDECDABUVSTPRMNKLHJEF SIDE 11111111111111121122222222222222 DIRECTION IOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIO changed: step 29 01010000010000000001000001000001 fail ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER VURSNPLMJKFHDECDABUVSTPRMNKLHJEF SIDE 11111111111111121122222222222222 DIRECTION IOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIO changed: 10 1 step 30 01010000010000000010010001000001 fail ^ ^ ^ ^ ^ ^ ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER VURSNPLMJKFHDECDABUVSTPRMNKLHJEF SIDE 11111111111111121122222222222222 DIRECTION IOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIO changed: 01 0 step 31 01010000010000000001000001000001 fail ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER VURSNPLMJKFHDECDABUVSTPRMNKLHJEF SIDE 11111111111111121122222222222222 DIRECTION IOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIO changed: step 32 01010000010000000001000001000001 fail ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER VURSNPLMJKFHDECDABUVSTPRMNKLHJEF SIDE 11111111111111121122222222222222 DIRECTION IOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIO changed: 1 step 33 01010000010000000001100001000001 fail ^ ^ ^ ^ ^ ^ ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER VURSNPLMJKFHDECDABUVSTPRMNKLHJEF SIDE 11111111111111121122222222222222 DIRECTION IOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIO changed: 0 step 34 01010000010000000001000001000001 fail ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER VURSNPLMJKFHDECDABUVSTPRMNKLHJEF SIDE 11111111111111121122222222222222 DIRECTION IOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIO changed: step 35 01010000010000000001000001000001 fail ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER VURSNPLMJKFHDECDABUVSTPRMNKLHJEF SIDE 11111111111111121122222222222222 DIRECTION IOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIO changed: 11 step 36 01010000010000000001001101000001 fail ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER VURSNPLMJKFHDECDABUVSTPRMNKLHJEF SIDE 11111111111111121122222222222222 DIRECTION IOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIO changed: 00 step 37 01010000010000000001000001000001 fail ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER VURSNPLMJKFHDECDABUVSTPRMNKLHJEF SIDE 11111111111111121122222222222222 DIRECTION IOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIO changed: step 38 01010000010000000001000001000001 fail ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER VURSNPLMJKFHDECDABUVSTPRMNKLHJEF SIDE 11111111111111121122222222222222 DIRECTION IOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIO changed: 10 step 39 01010000010000000001000010000001 fail ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER VURSNPLMJKFHDECDABUVSTPRMNKLHJEF SIDE 11111111111111121122222222222222 DIRECTION IOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIO changed: 01 step 40 01010000010000000001000001000001 fail ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER VURSNPLMJKFHDECDABUVSTPRMNKLHJEF SIDE 11111111111111121122222222222222 DIRECTION IOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIO changed: step 41 01010000010000000001000001000001 fail ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER VURSNPLMJKFHDECDABUVSTPRMNKLHJEF SIDE 11111111111111121122222222222222 DIRECTION IOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIO changed: 1 step 42 01010000010000000001000001100001 fail ^ ^ ^ ^ ^ ^ ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER VURSNPLMJKFHDECDABUVSTPRMNKLHJEF SIDE 11111111111111121122222222222222 DIRECTION IOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIO changed: 0 step 43 01010000010000000001000001000001 fail ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER VURSNPLMJKFHDECDABUVSTPRMNKLHJEF SIDE 11111111111111121122222222222222 DIRECTION IOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIO changed: step 44 01010000010000000001000001000001 fail ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER VURSNPLMJKFHDECDABUVSTPRMNKLHJEF SIDE 11111111111111121122222222222222 DIRECTION IOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIO changed: 1 step 45 01010000010000000001000001001001 fail ^ ^ ^ ^ ^ ^ ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER VURSNPLMJKFHDECDABUVSTPRMNKLHJEF SIDE 11111111111111121122222222222222 DIRECTION IOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIO changed: 0 step 46 01010000010000000001000001000001 fail ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER VURSNPLMJKFHDECDABUVSTPRMNKLHJEF SIDE 11111111111111121122222222222222 DIRECTION IOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIO changed: step 47 01010000010000000001000001000001 fail ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER VURSNPLMJKFHDECDABUVSTPRMNKLHJEF SIDE 11111111111111121122222222222222 DIRECTION IOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIO changed: 10 step 48 01010000010000000001000001000010 fail ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER VURSNPLMJKFHDECDABUVSTPRMNKLHJEF SIDE 11111111111111121122222222222222 DIRECTION IOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIO changed: 01 step 49 01010000010000000001000001000001 fail ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER VURSNPLMJKFHDECDABUVSTPRMNKLHJEF SIDE 11111111111111121122222222222222 DIRECTION IOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIO changed: step 50 01010000010000000001000001000001 fail ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER VURSNPLMJKFHDECDABUVSTPRMNKLHJEF SIDE 11111111111111121122222222222222 DIRECTION IOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIO changed: 1 10 11110 111 11110 11110 11110 step 51 11100111100111011110011110011110 fail ^ ^^ ^ ^^ ^^^ ^ ^^ ^ ^^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER VURSNPLMJKFHDECDABUVSTPRMNKLHJEF SIDE 11111111111111121122222222222222 DIRECTION IOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIO changed: 0 step 52 01100111100111011110011110011110 fail ^^ ^ ^^ ^^^ ^ ^^ ^ ^^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER VURSNPLMJKFHDECDABUVSTPRMNKLHJEF SIDE 11111111111111121122222222222222 DIRECTION IOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIO changed: 1 step 53 11100111100111011110011110011110 fail ^ ^^ ^ ^^ ^^^ ^ ^^ ^ ^^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER VURSNPLMJKFHDECDABUVSTPRMNKLHJEF SIDE 11111111111111121122222222222222 DIRECTION IOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIO changed: 0 0 step 54 11000011100111011110011110011110 fail ^ ^^ ^ ^^ ^^^ ^ ^^ ^ ^^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER VURSNPLMJKFHDECDABUVSTPRMNKLHJEF SIDE 11111111111111121122222222222222 DIRECTION IOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIO changed: 1 1 step 55 11100111100111011110011110011110 fail ^ ^^ ^ ^^ ^^^ ^ ^^ ^ ^^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER VURSNPLMJKFHDECDABUVSTPRMNKLHJEF SIDE 11111111111111121122222222222222 DIRECTION IOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIO changed: step 56 11100111100111011110011110011110 fail ^ ^ ^^ ^^^ ^ ^^ ^ ^^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER VURSNPLMJKFHDECDABUVSTPRMNKLHJEF SIDE 11111111111111121122222222222222 DIRECTION IOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIO changed: step 57 11100111100111011110011110011110 fail ^ ^^ ^ ^^ ^^^ ^ ^^ ^ ^^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER VURSNPLMJKFHDECDABUVSTPRMNKLHJEF SIDE 11111111111111121122222222222222 DIRECTION IOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIO changed: 1 00 step 58 11101100100111011110011110011110 fail ^ ^ ^ ^^ ^^^ ^ ^^ ^ ^^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER VURSNPLMJKFHDECDABUVSTPRMNKLHJEF SIDE 11111111111111121122222222222222 DIRECTION IOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIO changed: 0 11 step 59 11100111100111011110011110011110 fail ^ ^^ ^ ^^ ^^^ ^ ^^ ^ ^^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER VURSNPLMJKFHDECDABUVSTPRMNKLHJEF SIDE 11111111111111121122222222222222 DIRECTION IOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIO changed: 01 0 step 60 11100111010011011110011110011110 fail ^ ^^ ^ ^ ^^^ ^ ^^ ^ ^^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER VURSNPLMJKFHDECDABUVSTPRMNKLHJEF SIDE 11111111111111121122222222222222 DIRECTION IOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIO changed: 10 1 step 61 11100111100111011110011110011110 fail ^ ^^ ^ ^^ ^^^ ^ ^^ ^ ^^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER VURSNPLMJKFHDECDABUVSTPRMNKLHJEF SIDE 11111111111111121122222222222222 DIRECTION IOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIO changed: step 62 11100111100111011110011110011110 fail ^ ^^ ^ ^^^ ^ ^^ ^ ^^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER VURSNPLMJKFHDECDABUVSTPRMNKLHJEF SIDE 11111111111111121122222222222222 DIRECTION IOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIO changed: step 63 11100111100111011110011110011110 fail ^ ^^ ^ ^^ ^^^ ^ ^^ ^ ^^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER VURSNPLMJKFHDECDABUVSTPRMNKLHJEF SIDE 11111111111111121122222222222222 DIRECTION IOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIO changed: 1 00 step 64 11100111101100011110011110011110 fail ^ ^^ ^ ^ ^^^ ^ ^^ ^ ^^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER VURSNPLMJKFHDECDABUVSTPRMNKLHJEF SIDE 11111111111111121122222222222222 DIRECTION IOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIO changed: 0 11 step 65 11100111100111011110011110011110 fail ^ ^^ ^ ^^ ^^^ ^ ^^ ^ ^^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER VURSNPLMJKFHDECDABUVSTPRMNKLHJEF SIDE 11111111111111121122222222222222 DIRECTION IOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIO changed: step 66 11100111100111011110011110011110 fail ^ ^^ ^ ^^ ^ ^ ^^ ^ ^^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER VURSNPLMJKFHDECDABUVSTPRMNKLHJEF SIDE 11111111111111121122222222222222 DIRECTION IOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIO changed: step 67 11100111100111011110011110011110 fail ^ ^^ ^ ^^ ^^^ ^ ^^ ^ ^^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER VURSNPLMJKFHDECDABUVSTPRMNKLHJEF SIDE 11111111111111121122222222222222 DIRECTION IOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIO changed: 1 00 step 68 11100111100111110010011110011110 fail ^ ^^ ^ ^^ ^ ^ ^ ^^ ^ ^^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER VURSNPLMJKFHDECDABUVSTPRMNKLHJEF SIDE 11111111111111121122222222222222 DIRECTION IOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIO changed: 0 11 step 69 11100111100111011110011110011110 fail ^ ^^ ^ ^^ ^^^ ^ ^^ ^ ^^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER VURSNPLMJKFHDECDABUVSTPRMNKLHJEF SIDE 11111111111111121122222222222222 DIRECTION IOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIO changed: 01 0 step 70 11100111100111011101001110011110 fail ^ ^^ ^ ^^ ^^^ ^ ^ ^ ^^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER VURSNPLMJKFHDECDABUVSTPRMNKLHJEF SIDE 11111111111111121122222222222222 DIRECTION IOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIO changed: 10 1 step 71 11100111100111011110011110011110 fail ^ ^^ ^ ^^ ^^^ ^ ^^ ^ ^^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER VURSNPLMJKFHDECDABUVSTPRMNKLHJEF SIDE 11111111111111121122222222222222 DIRECTION IOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIO changed: step 72 11100111100111011110011110011110 fail ^ ^^ ^ ^^ ^^^ ^ ^ ^^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER VURSNPLMJKFHDECDABUVSTPRMNKLHJEF SIDE 11111111111111121122222222222222 DIRECTION IOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIO changed: step 73 11100111100111011110011110011110 fail ^ ^^ ^ ^^ ^^^ ^ ^^ ^ ^^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER VURSNPLMJKFHDECDABUVSTPRMNKLHJEF SIDE 11111111111111121122222222222222 DIRECTION IOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIO changed: 1 00 step 74 11100111100111011110110010011110 fail ^ ^^ ^ ^^ ^^^ ^ ^ ^ ^^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER VURSNPLMJKFHDECDABUVSTPRMNKLHJEF SIDE 11111111111111121122222222222222 DIRECTION IOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIO changed: 0 11 step 75 11100111100111011110011110011110 fail ^ ^^ ^ ^^ ^^^ ^ ^^ ^ ^^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER VURSNPLMJKFHDECDABUVSTPRMNKLHJEF SIDE 11111111111111121122222222222222 DIRECTION IOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIO changed: 01 0 step 76 11100111100111011110011101001110 fail ^ ^^ ^ ^^ ^^^ ^ ^^ ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER VURSNPLMJKFHDECDABUVSTPRMNKLHJEF SIDE 11111111111111121122222222222222 DIRECTION IOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIO changed: 10 1 step 77 11100111100111011110011110011110 fail ^ ^^ ^ ^^ ^^^ ^ ^^ ^ ^^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER VURSNPLMJKFHDECDABUVSTPRMNKLHJEF SIDE 11111111111111121122222222222222 DIRECTION IOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIO changed: step 78 11100111100111011110011110011110 fail ^ ^^ ^ ^^ ^^^ ^ ^^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER VURSNPLMJKFHDECDABUVSTPRMNKLHJEF SIDE 11111111111111121122222222222222 DIRECTION IOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIO changed: step 79 11100111100111011110011110011110 fail ^ ^^ ^ ^^ ^^^ ^ ^^ ^ ^^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER VURSNPLMJKFHDECDABUVSTPRMNKLHJEF SIDE 11111111111111121122222222222222 DIRECTION IOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIO changed: 1 00 step 80 11100111100111011110011110110010 fail ^ ^^ ^ ^^ ^^^ ^ ^^ ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER VURSNPLMJKFHDECDABUVSTPRMNKLHJEF SIDE 11111111111111121122222222222222 DIRECTION IOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIO changed: 0 11 step 81 11100111100111011110011110011110 fail ^ ^^ ^ ^^ ^^^ ^ ^^ ^ ^^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER VURSNPLMJKFHDECDABUVSTPRMNKLHJEF SIDE 11111111111111121122222222222222 DIRECTION IOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIO changed: 0 01 step 82 11100111100111001110011110011101 fail ^ ^^ ^ ^^ ^^ ^ ^^ ^ ^^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER VURSNPLMJKFHDECDABUVSTPRMNKLHJEF SIDE 11111111111111121122222222222222 DIRECTION IOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIO changed: 1 10 step 83 11100111100111011110011110011110 fail ^ ^^ ^ ^^ ^^^ ^ ^^ ^ ^^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER VURSNPLMJKFHDECDABUVSTPRMNKLHJEF SIDE 11111111111111121122222222222222 DIRECTION IOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIO changed: step 84 11100111100111011110011110011110 fail ^ ^^ ^ ^^ ^^^ ^ ^^ ^ ^^ ^ test 53: *** FAIL *************************** 84 steps failed SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER VURSNPLMJKFHDECDABUVSTPRMNKLHJEF SIDE 11111111111111121122222222222222 DIRECTION IOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIO this fail O OIO O IO OIO O IO O IO O all fails O OIO O IO OIO O IO O IO O was hi 11111111111111111111111111111111 rising ^ ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ falling v vvvvvvvvvvvvvvvvvvvvvvvvvvvvvv was lo 0 000000000000000000000000000000 total fails 53, total passes 0 SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER VURSNPLMJKFHDECDABUVSTPRMNKLHJEF SIDE 11111111111111121122222222222222 DIRECTION IOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIO changed: 0 011000011000100001100001100001 step 1 01011000011000100001100001100001 fail ^^ ^ ^^ ^^^ ^ ^^ ^ ^^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER VURSNPLMJKFHDECDABUVSTPRMNKLHJEF SIDE 11111111111111121122222222222222 DIRECTION IOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIO changed: 0 0 0 step 2 01010000011000100001000001000001 fail ^ ^ ^^ ^^^ ^ ^ ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER VURSNPLMJKFHDECDABUVSTPRMNKLHJEF SIDE 11111111111111121122222222222222 DIRECTION IOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIO changed: 1 step 3 11010000011000100001000001000001 fail ^ ^ ^ ^^ ^^^ ^ ^ ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER VURSNPLMJKFHDECDABUVSTPRMNKLHJEF SIDE 11111111111111121122222222222222 DIRECTION IOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIO changed: 0 0 0 step 4 01010000010000000001000001000001 fail ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER VURSNPLMJKFHDECDABUVSTPRMNKLHJEF SIDE 11111111111111121122222222222222 DIRECTION IOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIO changed: step 5 01010000010000000001000001000001 fail ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER VURSNPLMJKFHDECDABUVSTPRMNKLHJEF SIDE 11111111111111121122222222222222 DIRECTION IOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIO changed: 10 1 step 6 01100100010000000001000001000001 fail ^ ^ ^ ^ ^ ^ ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER VURSNPLMJKFHDECDABUVSTPRMNKLHJEF SIDE 11111111111111121122222222222222 DIRECTION IOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIO changed: 01 0 step 7 01010000010000000001000001000001 fail ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER VURSNPLMJKFHDECDABUVSTPRMNKLHJEF SIDE 11111111111111121122222222222222 DIRECTION IOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIO changed: step 8 01010000010000000001000001000001 fail ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER VURSNPLMJKFHDECDABUVSTPRMNKLHJEF SIDE 11111111111111121122222222222222 DIRECTION IOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIO changed: 1 step 9 01011000010000000001000001000001 fail ^ ^ ^ ^ ^ ^ ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER VURSNPLMJKFHDECDABUVSTPRMNKLHJEF SIDE 11111111111111121122222222222222 DIRECTION IOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIO changed: 0 step 10 01010000010000000001000001000001 fail ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER VURSNPLMJKFHDECDABUVSTPRMNKLHJEF SIDE 11111111111111121122222222222222 DIRECTION IOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIO changed: step 11 01010000010000000001000001000001 fail ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER VURSNPLMJKFHDECDABUVSTPRMNKLHJEF SIDE 11111111111111121122222222222222 DIRECTION IOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIO changed: 11 step 12 01010011010000000001000001000001 fail ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER VURSNPLMJKFHDECDABUVSTPRMNKLHJEF SIDE 11111111111111121122222222222222 DIRECTION IOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIO changed: 00 step 13 01010000010000000001000001000001 fail ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER VURSNPLMJKFHDECDABUVSTPRMNKLHJEF SIDE 11111111111111121122222222222222 DIRECTION IOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIO changed: step 14 01010000010000000001000001000001 fail ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER VURSNPLMJKFHDECDABUVSTPRMNKLHJEF SIDE 11111111111111121122222222222222 DIRECTION IOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIO changed: 10 step 15 01010000100000000001000001000001 fail ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER VURSNPLMJKFHDECDABUVSTPRMNKLHJEF SIDE 11111111111111121122222222222222 DIRECTION IOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIO changed: 01 step 16 01010000010000000001000001000001 fail ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER VURSNPLMJKFHDECDABUVSTPRMNKLHJEF SIDE 11111111111111121122222222222222 DIRECTION IOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIO changed: step 17 01010000010000000001000001000001 fail ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER VURSNPLMJKFHDECDABUVSTPRMNKLHJEF SIDE 11111111111111121122222222222222 DIRECTION IOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIO changed: 1 step 18 01010000011000000001000001000001 fail ^ ^ ^ ^ ^ ^ ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER VURSNPLMJKFHDECDABUVSTPRMNKLHJEF SIDE 11111111111111121122222222222222 DIRECTION IOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIO changed: 0 step 19 01010000010000000001000001000001 fail ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER VURSNPLMJKFHDECDABUVSTPRMNKLHJEF SIDE 11111111111111121122222222222222 DIRECTION IOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIO changed: step 20 01010000010000000001000001000001 fail ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER VURSNPLMJKFHDECDABUVSTPRMNKLHJEF SIDE 11111111111111121122222222222222 DIRECTION IOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIO changed: 1 step 21 01010000010010000001000001000001 fail ^ ^ ^ ^ ^ ^ ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER VURSNPLMJKFHDECDABUVSTPRMNKLHJEF SIDE 11111111111111121122222222222222 DIRECTION IOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIO changed: 0 step 22 01010000010000000001000001000001 fail ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER VURSNPLMJKFHDECDABUVSTPRMNKLHJEF SIDE 11111111111111121122222222222222 DIRECTION IOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIO changed: step 23 01010000010000000001000001000001 fail ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER VURSNPLMJKFHDECDABUVSTPRMNKLHJEF SIDE 11111111111111121122222222222222 DIRECTION IOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIO changed: 1 step 24 01010000010000100001000001000001 fail ^ ^ ^ ^ ^ ^ ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER VURSNPLMJKFHDECDABUVSTPRMNKLHJEF SIDE 11111111111111121122222222222222 DIRECTION IOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIO changed: 0 step 25 01010000010000000001000001000001 fail ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER VURSNPLMJKFHDECDABUVSTPRMNKLHJEF SIDE 11111111111111121122222222222222 DIRECTION IOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIO changed: step 26 01010000010000000001000001000001 fail ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER VURSNPLMJKFHDECDABUVSTPRMNKLHJEF SIDE 11111111111111121122222222222222 DIRECTION IOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIO changed: 1 step 27 01010000010000001001000001000001 fail ^ ^ ^ ^ ^ ^ ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER VURSNPLMJKFHDECDABUVSTPRMNKLHJEF SIDE 11111111111111121122222222222222 DIRECTION IOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIO changed: 0 step 28 01010000010000000001000001000001 fail ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER VURSNPLMJKFHDECDABUVSTPRMNKLHJEF SIDE 11111111111111121122222222222222 DIRECTION IOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIO changed: step 29 01010000010000000001000001000001 fail ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER VURSNPLMJKFHDECDABUVSTPRMNKLHJEF SIDE 11111111111111121122222222222222 DIRECTION IOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIO changed: 10 1 step 30 01010000010000000010010001000001 fail ^ ^ ^ ^ ^ ^ ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER VURSNPLMJKFHDECDABUVSTPRMNKLHJEF SIDE 11111111111111121122222222222222 DIRECTION IOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIO changed: 01 0 step 31 01010000010000000001000001000001 fail ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER VURSNPLMJKFHDECDABUVSTPRMNKLHJEF SIDE 11111111111111121122222222222222 DIRECTION IOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIO changed: step 32 01010000010000000001000001000001 fail ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER VURSNPLMJKFHDECDABUVSTPRMNKLHJEF SIDE 11111111111111121122222222222222 DIRECTION IOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIO changed: 1 step 33 01010000010000000001100001000001 fail ^ ^ ^ ^ ^ ^ ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER VURSNPLMJKFHDECDABUVSTPRMNKLHJEF SIDE 11111111111111121122222222222222 DIRECTION IOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIO changed: 0 step 34 01010000010000000001000001000001 fail ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER VURSNPLMJKFHDECDABUVSTPRMNKLHJEF SIDE 11111111111111121122222222222222 DIRECTION IOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIO changed: step 35 01010000010000000001000001000001 fail ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER VURSNPLMJKFHDECDABUVSTPRMNKLHJEF SIDE 11111111111111121122222222222222 DIRECTION IOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIO changed: 11 step 36 01010000010000000001001101000001 fail ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER VURSNPLMJKFHDECDABUVSTPRMNKLHJEF SIDE 11111111111111121122222222222222 DIRECTION IOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIO changed: 00 step 37 01010000010000000001000001000001 fail ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER VURSNPLMJKFHDECDABUVSTPRMNKLHJEF SIDE 11111111111111121122222222222222 DIRECTION IOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIO changed: step 38 01010000010000000001000001000001 fail ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER VURSNPLMJKFHDECDABUVSTPRMNKLHJEF SIDE 11111111111111121122222222222222 DIRECTION IOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIO changed: 10 step 39 01010000010000000001000010000001 fail ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER VURSNPLMJKFHDECDABUVSTPRMNKLHJEF SIDE 11111111111111121122222222222222 DIRECTION IOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIO changed: 01 step 40 01010000010000000001000001000001 fail ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER VURSNPLMJKFHDECDABUVSTPRMNKLHJEF SIDE 11111111111111121122222222222222 DIRECTION IOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIO changed: step 41 01010000010000000001000001000001 fail ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER VURSNPLMJKFHDECDABUVSTPRMNKLHJEF SIDE 11111111111111121122222222222222 DIRECTION IOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIO changed: 1 step 42 01010000010000000001000001100001 fail ^ ^ ^ ^ ^ ^ ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER VURSNPLMJKFHDECDABUVSTPRMNKLHJEF SIDE 11111111111111121122222222222222 DIRECTION IOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIO changed: 0 step 43 01010000010000000001000001000001 fail ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER VURSNPLMJKFHDECDABUVSTPRMNKLHJEF SIDE 11111111111111121122222222222222 DIRECTION IOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIO changed: step 44 01010000010000000001000001000001 fail ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER VURSNPLMJKFHDECDABUVSTPRMNKLHJEF SIDE 11111111111111121122222222222222 DIRECTION IOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIO changed: 1 step 45 01010000010000000001000001001001 fail ^ ^ ^ ^ ^ ^ ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER VURSNPLMJKFHDECDABUVSTPRMNKLHJEF SIDE 11111111111111121122222222222222 DIRECTION IOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIO changed: 0 step 46 01010000010000000001000001000001 fail ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER VURSNPLMJKFHDECDABUVSTPRMNKLHJEF SIDE 11111111111111121122222222222222 DIRECTION IOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIO changed: step 47 01010000010000000001000001000001 fail ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER VURSNPLMJKFHDECDABUVSTPRMNKLHJEF SIDE 11111111111111121122222222222222 DIRECTION IOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIO changed: 10 step 48 01010000010000000001000001000010 fail ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER VURSNPLMJKFHDECDABUVSTPRMNKLHJEF SIDE 11111111111111121122222222222222 DIRECTION IOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIO changed: 01 step 49 01010000010000000001000001000001 fail ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER VURSNPLMJKFHDECDABUVSTPRMNKLHJEF SIDE 11111111111111121122222222222222 DIRECTION IOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIO changed: step 50 01010000010000000001000001000001 fail ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER VURSNPLMJKFHDECDABUVSTPRMNKLHJEF SIDE 11111111111111121122222222222222 DIRECTION IOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIO changed: 1 10 11110 111 11110 11110 11110 step 51 11100111100111011110011110011110 fail ^ ^^ ^ ^^ ^^^ ^ ^^ ^ ^^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER VURSNPLMJKFHDECDABUVSTPRMNKLHJEF SIDE 11111111111111121122222222222222 DIRECTION IOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIO changed: 0 step 52 01100111100111011110011110011110 fail ^^ ^ ^^ ^^^ ^ ^^ ^ ^^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER VURSNPLMJKFHDECDABUVSTPRMNKLHJEF SIDE 11111111111111121122222222222222 DIRECTION IOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIO changed: 1 step 53 11100111100111011110011110011110 fail ^ ^^ ^ ^^ ^^^ ^ ^^ ^ ^^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER VURSNPLMJKFHDECDABUVSTPRMNKLHJEF SIDE 11111111111111121122222222222222 DIRECTION IOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIO changed: 0 0 step 54 11000011100111011110011110011110 fail ^ ^^ ^ ^^ ^^^ ^ ^^ ^ ^^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER VURSNPLMJKFHDECDABUVSTPRMNKLHJEF SIDE 11111111111111121122222222222222 DIRECTION IOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIO changed: 1 1 step 55 11100111100111011110011110011110 fail ^ ^^ ^ ^^ ^^^ ^ ^^ ^ ^^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER VURSNPLMJKFHDECDABUVSTPRMNKLHJEF SIDE 11111111111111121122222222222222 DIRECTION IOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIO changed: step 56 11100111100111011110011110011110 fail ^ ^ ^^ ^^^ ^ ^^ ^ ^^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER VURSNPLMJKFHDECDABUVSTPRMNKLHJEF SIDE 11111111111111121122222222222222 DIRECTION IOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIO changed: step 57 11100111100111011110011110011110 fail ^ ^^ ^ ^^ ^^^ ^ ^^ ^ ^^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER VURSNPLMJKFHDECDABUVSTPRMNKLHJEF SIDE 11111111111111121122222222222222 DIRECTION IOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIO changed: 1 00 step 58 11101100100111011110011110011110 fail ^ ^ ^ ^^ ^^^ ^ ^^ ^ ^^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER VURSNPLMJKFHDECDABUVSTPRMNKLHJEF SIDE 11111111111111121122222222222222 DIRECTION IOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIO changed: 0 11 step 59 11100111100111011110011110011110 fail ^ ^^ ^ ^^ ^^^ ^ ^^ ^ ^^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER VURSNPLMJKFHDECDABUVSTPRMNKLHJEF SIDE 11111111111111121122222222222222 DIRECTION IOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIO changed: 01 0 step 60 11100111010011011110011110011110 fail ^ ^^ ^ ^ ^^^ ^ ^^ ^ ^^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER VURSNPLMJKFHDECDABUVSTPRMNKLHJEF SIDE 11111111111111121122222222222222 DIRECTION IOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIO changed: 10 1 step 61 11100111100111011110011110011110 fail ^ ^^ ^ ^^ ^^^ ^ ^^ ^ ^^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER VURSNPLMJKFHDECDABUVSTPRMNKLHJEF SIDE 11111111111111121122222222222222 DIRECTION IOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIO changed: step 62 11100111100111011110011110011110 fail ^ ^^ ^ ^^^ ^ ^^ ^ ^^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER VURSNPLMJKFHDECDABUVSTPRMNKLHJEF SIDE 11111111111111121122222222222222 DIRECTION IOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIO changed: step 63 11100111100111011110011110011110 fail ^ ^^ ^ ^^ ^^^ ^ ^^ ^ ^^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER VURSNPLMJKFHDECDABUVSTPRMNKLHJEF SIDE 11111111111111121122222222222222 DIRECTION IOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIO changed: 1 00 step 64 11100111101100011110011110011110 fail ^ ^^ ^ ^ ^^^ ^ ^^ ^ ^^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER VURSNPLMJKFHDECDABUVSTPRMNKLHJEF SIDE 11111111111111121122222222222222 DIRECTION IOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIO changed: 0 11 step 65 11100111100111011110011110011110 fail ^ ^^ ^ ^^ ^^^ ^ ^^ ^ ^^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER VURSNPLMJKFHDECDABUVSTPRMNKLHJEF SIDE 11111111111111121122222222222222 DIRECTION IOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIO changed: step 66 11100111100111011110011110011110 fail ^ ^^ ^ ^^ ^ ^ ^^ ^ ^^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER VURSNPLMJKFHDECDABUVSTPRMNKLHJEF SIDE 11111111111111121122222222222222 DIRECTION IOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIO changed: step 67 11100111100111011110011110011110 fail ^ ^^ ^ ^^ ^^^ ^ ^^ ^ ^^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER VURSNPLMJKFHDECDABUVSTPRMNKLHJEF SIDE 11111111111111121122222222222222 DIRECTION IOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIO changed: 1 00 step 68 11100111100111110010011110011110 fail ^ ^^ ^ ^^ ^ ^ ^ ^^ ^ ^^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER VURSNPLMJKFHDECDABUVSTPRMNKLHJEF SIDE 11111111111111121122222222222222 DIRECTION IOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIO changed: 0 11 step 69 11100111100111011110011110011110 fail ^ ^^ ^ ^^ ^^^ ^ ^^ ^ ^^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER VURSNPLMJKFHDECDABUVSTPRMNKLHJEF SIDE 11111111111111121122222222222222 DIRECTION IOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIO changed: 01 0 step 70 11100111100111011101001110011110 fail ^ ^^ ^ ^^ ^^^ ^ ^ ^ ^^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER VURSNPLMJKFHDECDABUVSTPRMNKLHJEF SIDE 11111111111111121122222222222222 DIRECTION IOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIO changed: 10 1 step 71 11100111100111011110011110011110 fail ^ ^^ ^ ^^ ^^^ ^ ^^ ^ ^^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER VURSNPLMJKFHDECDABUVSTPRMNKLHJEF SIDE 11111111111111121122222222222222 DIRECTION IOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIO changed: step 72 11100111100111011110011110011110 fail ^ ^^ ^ ^^ ^^^ ^ ^ ^^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER VURSNPLMJKFHDECDABUVSTPRMNKLHJEF SIDE 11111111111111121122222222222222 DIRECTION IOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIO changed: step 73 11100111100111011110011110011110 fail ^ ^^ ^ ^^ ^^^ ^ ^^ ^ ^^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER VURSNPLMJKFHDECDABUVSTPRMNKLHJEF SIDE 11111111111111121122222222222222 DIRECTION IOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIO changed: 1 00 step 74 11100111100111011110110010011110 fail ^ ^^ ^ ^^ ^^^ ^ ^ ^ ^^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER VURSNPLMJKFHDECDABUVSTPRMNKLHJEF SIDE 11111111111111121122222222222222 DIRECTION IOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIO changed: 0 11 step 75 11100111100111011110011110011110 fail ^ ^^ ^ ^^ ^^^ ^ ^^ ^ ^^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER VURSNPLMJKFHDECDABUVSTPRMNKLHJEF SIDE 11111111111111121122222222222222 DIRECTION IOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIO changed: 01 0 step 76 11100111100111011110011101001110 fail ^ ^^ ^ ^^ ^^^ ^ ^^ ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER VURSNPLMJKFHDECDABUVSTPRMNKLHJEF SIDE 11111111111111121122222222222222 DIRECTION IOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIO changed: 10 1 step 77 11100111100111011110011110011110 fail ^ ^^ ^ ^^ ^^^ ^ ^^ ^ ^^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER VURSNPLMJKFHDECDABUVSTPRMNKLHJEF SIDE 11111111111111121122222222222222 DIRECTION IOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIO changed: step 78 11100111100111011110011110011110 fail ^ ^^ ^ ^^ ^^^ ^ ^^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER VURSNPLMJKFHDECDABUVSTPRMNKLHJEF SIDE 11111111111111121122222222222222 DIRECTION IOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIO changed: step 79 11100111100111011110011110011110 fail ^ ^^ ^ ^^ ^^^ ^ ^^ ^ ^^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER VURSNPLMJKFHDECDABUVSTPRMNKLHJEF SIDE 11111111111111121122222222222222 DIRECTION IOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIO changed: 1 00 step 80 11100111100111011110011110110010 fail ^ ^^ ^ ^^ ^^^ ^ ^^ ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER VURSNPLMJKFHDECDABUVSTPRMNKLHJEF SIDE 11111111111111121122222222222222 DIRECTION IOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIO changed: 0 11 step 81 11100111100111011110011110011110 fail ^ ^^ ^ ^^ ^^^ ^ ^^ ^ ^^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER VURSNPLMJKFHDECDABUVSTPRMNKLHJEF SIDE 11111111111111121122222222222222 DIRECTION IOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIO changed: 0 01 step 82 11100111100111001110011110011101 fail ^ ^^ ^ ^^ ^^ ^ ^^ ^ ^^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER VURSNPLMJKFHDECDABUVSTPRMNKLHJEF SIDE 11111111111111121122222222222222 DIRECTION IOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIO changed: 1 10 step 83 11100111100111011110011110011110 fail ^ ^^ ^ ^^ ^^^ ^ ^^ ^ ^^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER VURSNPLMJKFHDECDABUVSTPRMNKLHJEF SIDE 11111111111111121122222222222222 DIRECTION IOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIO changed: step 84 11100111100111011110011110011110 fail ^ ^^ ^ ^^ ^^^ ^ ^^ ^ ^^ ^ test 54: *** FAIL *************************** 84 steps failed SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER VURSNPLMJKFHDECDABUVSTPRMNKLHJEF SIDE 11111111111111121122222222222222 DIRECTION IOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIO this fail O OIO O IO OIO O IO O IO O all fails O OIO O IO OIO O IO O IO O was hi 11111111111111111111111111111111 rising ^ ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ falling v vvvvvvvvvvvvvvvvvvvvvvvvvvvvvv was lo 0 000000000000000000000000000000 total fails 54, total passes 0 SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER VURSNPLMJKFHDECDABUVSTPRMNKLHJEF SIDE 11111111111111121122222222222222 DIRECTION IOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIO changed: 0 011000011000100001100001100001 step 1 01011000011000100001100001100001 fail ^^ ^ ^^ ^^^ ^ ^^ ^ ^^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER VURSNPLMJKFHDECDABUVSTPRMNKLHJEF SIDE 11111111111111121122222222222222 DIRECTION IOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIO changed: 0 0 0 step 2 01010000011000100001000001000001 fail ^ ^ ^^ ^^^ ^ ^ ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER VURSNPLMJKFHDECDABUVSTPRMNKLHJEF SIDE 11111111111111121122222222222222 DIRECTION IOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIO changed: 1 step 3 11010000011000100001000001000001 fail ^ ^ ^ ^^ ^^^ ^ ^ ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER VURSNPLMJKFHDECDABUVSTPRMNKLHJEF SIDE 11111111111111121122222222222222 DIRECTION IOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIO changed: 0 0 0 step 4 01010000010000000001000001000001 fail ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER VURSNPLMJKFHDECDABUVSTPRMNKLHJEF SIDE 11111111111111121122222222222222 DIRECTION IOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIO changed: step 5 01010000010000000001000001000001 fail ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER VURSNPLMJKFHDECDABUVSTPRMNKLHJEF SIDE 11111111111111121122222222222222 DIRECTION IOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIO changed: 10 1 step 6 01100100010000000001000001000001 fail ^ ^ ^ ^ ^ ^ ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER VURSNPLMJKFHDECDABUVSTPRMNKLHJEF SIDE 11111111111111121122222222222222 DIRECTION IOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIO changed: 01 0 step 7 01010000010000000001000001000001 fail ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER VURSNPLMJKFHDECDABUVSTPRMNKLHJEF SIDE 11111111111111121122222222222222 DIRECTION IOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIO changed: step 8 01010000010000000001000001000001 fail ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER VURSNPLMJKFHDECDABUVSTPRMNKLHJEF SIDE 11111111111111121122222222222222 DIRECTION IOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIO changed: 1 step 9 01011000010000000001000001000001 fail ^ ^ ^ ^ ^ ^ ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER VURSNPLMJKFHDECDABUVSTPRMNKLHJEF SIDE 11111111111111121122222222222222 DIRECTION IOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIO changed: 0 step 10 01010000010000000001000001000001 fail ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER VURSNPLMJKFHDECDABUVSTPRMNKLHJEF SIDE 11111111111111121122222222222222 DIRECTION IOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIO changed: step 11 01010000010000000001000001000001 fail ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER VURSNPLMJKFHDECDABUVSTPRMNKLHJEF SIDE 11111111111111121122222222222222 DIRECTION IOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIO changed: 11 step 12 01010011010000000001000001000001 fail ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER VURSNPLMJKFHDECDABUVSTPRMNKLHJEF SIDE 11111111111111121122222222222222 DIRECTION IOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIO changed: 00 step 13 01010000010000000001000001000001 fail ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER VURSNPLMJKFHDECDABUVSTPRMNKLHJEF SIDE 11111111111111121122222222222222 DIRECTION IOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIO changed: step 14 01010000010000000001000001000001 fail ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER VURSNPLMJKFHDECDABUVSTPRMNKLHJEF SIDE 11111111111111121122222222222222 DIRECTION IOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIO changed: 10 step 15 01010000100000000001000001000001 fail ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER VURSNPLMJKFHDECDABUVSTPRMNKLHJEF SIDE 11111111111111121122222222222222 DIRECTION IOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIO changed: 01 step 16 01010000010000000001000001000001 fail ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER VURSNPLMJKFHDECDABUVSTPRMNKLHJEF SIDE 11111111111111121122222222222222 DIRECTION IOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIO changed: step 17 01010000010000000001000001000001 fail ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER VURSNPLMJKFHDECDABUVSTPRMNKLHJEF SIDE 11111111111111121122222222222222 DIRECTION IOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIO changed: 1 step 18 01010000011000000001000001000001 fail ^ ^ ^ ^ ^ ^ ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER VURSNPLMJKFHDECDABUVSTPRMNKLHJEF SIDE 11111111111111121122222222222222 DIRECTION IOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIO changed: 0 step 19 01010000010000000001000001000001 fail ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER VURSNPLMJKFHDECDABUVSTPRMNKLHJEF SIDE 11111111111111121122222222222222 DIRECTION IOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIO changed: step 20 01010000010000000001000001000001 fail ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER VURSNPLMJKFHDECDABUVSTPRMNKLHJEF SIDE 11111111111111121122222222222222 DIRECTION IOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIO changed: 1 step 21 01010000010010000001000001000001 fail ^ ^ ^ ^ ^ ^ ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER VURSNPLMJKFHDECDABUVSTPRMNKLHJEF SIDE 11111111111111121122222222222222 DIRECTION IOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIO changed: 0 step 22 01010000010000000001000001000001 fail ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER VURSNPLMJKFHDECDABUVSTPRMNKLHJEF SIDE 11111111111111121122222222222222 DIRECTION IOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIO changed: step 23 01010000010000000001000001000001 fail ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER VURSNPLMJKFHDECDABUVSTPRMNKLHJEF SIDE 11111111111111121122222222222222 DIRECTION IOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIO changed: 1 step 24 01010000010000100001000001000001 fail ^ ^ ^ ^ ^ ^ ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER VURSNPLMJKFHDECDABUVSTPRMNKLHJEF SIDE 11111111111111121122222222222222 DIRECTION IOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIO changed: 0 step 25 01010000010000000001000001000001 fail ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER VURSNPLMJKFHDECDABUVSTPRMNKLHJEF SIDE 11111111111111121122222222222222 DIRECTION IOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIO changed: step 26 01010000010000000001000001000001 fail ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER VURSNPLMJKFHDECDABUVSTPRMNKLHJEF SIDE 11111111111111121122222222222222 DIRECTION IOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIO changed: 1 step 27 01010000010000001001000001000001 fail ^ ^ ^ ^ ^ ^ ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER VURSNPLMJKFHDECDABUVSTPRMNKLHJEF SIDE 11111111111111121122222222222222 DIRECTION IOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIO changed: 0 step 28 01010000010000000001000001000001 fail ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER VURSNPLMJKFHDECDABUVSTPRMNKLHJEF SIDE 11111111111111121122222222222222 DIRECTION IOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIO changed: step 29 01010000010000000001000001000001 fail ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER VURSNPLMJKFHDECDABUVSTPRMNKLHJEF SIDE 11111111111111121122222222222222 DIRECTION IOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIO changed: 10 1 step 30 01010000010000000010010001000001 fail ^ ^ ^ ^ ^ ^ ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER VURSNPLMJKFHDECDABUVSTPRMNKLHJEF SIDE 11111111111111121122222222222222 DIRECTION IOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIO changed: 01 0 step 31 01010000010000000001000001000001 fail ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER VURSNPLMJKFHDECDABUVSTPRMNKLHJEF SIDE 11111111111111121122222222222222 DIRECTION IOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIO changed: step 32 01010000010000000001000001000001 fail ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER VURSNPLMJKFHDECDABUVSTPRMNKLHJEF SIDE 11111111111111121122222222222222 DIRECTION IOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIO changed: 1 step 33 01010000010000000001100001000001 fail ^ ^ ^ ^ ^ ^ ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER VURSNPLMJKFHDECDABUVSTPRMNKLHJEF SIDE 11111111111111121122222222222222 DIRECTION IOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIO changed: 0 step 34 01010000010000000001000001000001 fail ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER VURSNPLMJKFHDECDABUVSTPRMNKLHJEF SIDE 11111111111111121122222222222222 DIRECTION IOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIO changed: step 35 01010000010000000001000001000001 fail ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER VURSNPLMJKFHDECDABUVSTPRMNKLHJEF SIDE 11111111111111121122222222222222 DIRECTION IOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIO changed: 11 step 36 01010000010000000001001101000001 fail ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER VURSNPLMJKFHDECDABUVSTPRMNKLHJEF SIDE 11111111111111121122222222222222 DIRECTION IOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIO changed: 00 step 37 01010000010000000001000001000001 fail ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER VURSNPLMJKFHDECDABUVSTPRMNKLHJEF SIDE 11111111111111121122222222222222 DIRECTION IOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIO changed: step 38 01010000010000000001000001000001 fail ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER VURSNPLMJKFHDECDABUVSTPRMNKLHJEF SIDE 11111111111111121122222222222222 DIRECTION IOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIO changed: 10 step 39 01010000010000000001000010000001 fail ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER VURSNPLMJKFHDECDABUVSTPRMNKLHJEF SIDE 11111111111111121122222222222222 DIRECTION IOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIO changed: 01 step 40 01010000010000000001000001000001 fail ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER VURSNPLMJKFHDECDABUVSTPRMNKLHJEF SIDE 11111111111111121122222222222222 DIRECTION IOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIO changed: step 41 01010000010000000001000001000001 fail ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER VURSNPLMJKFHDECDABUVSTPRMNKLHJEF SIDE 11111111111111121122222222222222 DIRECTION IOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIO changed: 1 step 42 01010000010000000001000001100001 fail ^ ^ ^ ^ ^ ^ ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER VURSNPLMJKFHDECDABUVSTPRMNKLHJEF SIDE 11111111111111121122222222222222 DIRECTION IOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIO changed: 0 step 43 01010000010000000001000001000001 fail ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER VURSNPLMJKFHDECDABUVSTPRMNKLHJEF SIDE 11111111111111121122222222222222 DIRECTION IOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIO changed: step 44 01010000010000000001000001000001 fail ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER VURSNPLMJKFHDECDABUVSTPRMNKLHJEF SIDE 11111111111111121122222222222222 DIRECTION IOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIO changed: 1 step 45 01010000010000000001000001001001 fail ^ ^ ^ ^ ^ ^ ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER VURSNPLMJKFHDECDABUVSTPRMNKLHJEF SIDE 11111111111111121122222222222222 DIRECTION IOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIO changed: 0 step 46 01010000010000000001000001000001 fail ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER VURSNPLMJKFHDECDABUVSTPRMNKLHJEF SIDE 11111111111111121122222222222222 DIRECTION IOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIO changed: step 47 01010000010000000001000001000001 fail ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER VURSNPLMJKFHDECDABUVSTPRMNKLHJEF SIDE 11111111111111121122222222222222 DIRECTION IOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIO changed: 10 step 48 01010000010000000001000001000010 fail ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER VURSNPLMJKFHDECDABUVSTPRMNKLHJEF SIDE 11111111111111121122222222222222 DIRECTION IOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIO changed: 01 step 49 01010000010000000001000001000001 fail ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER VURSNPLMJKFHDECDABUVSTPRMNKLHJEF SIDE 11111111111111121122222222222222 DIRECTION IOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIO changed: step 50 01010000010000000001000001000001 fail ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER VURSNPLMJKFHDECDABUVSTPRMNKLHJEF SIDE 11111111111111121122222222222222 DIRECTION IOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIO changed: 1 10 11110 111 11110 11110 11110 step 51 11100111100111011110011110011110 fail ^ ^^ ^ ^^ ^^^ ^ ^^ ^ ^^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER VURSNPLMJKFHDECDABUVSTPRMNKLHJEF SIDE 11111111111111121122222222222222 DIRECTION IOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIO changed: 0 step 52 01100111100111011110011110011110 fail ^^ ^ ^^ ^^^ ^ ^^ ^ ^^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER VURSNPLMJKFHDECDABUVSTPRMNKLHJEF SIDE 11111111111111121122222222222222 DIRECTION IOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIO changed: 1 step 53 11100111100111011110011110011110 fail ^ ^^ ^ ^^ ^^^ ^ ^^ ^ ^^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER VURSNPLMJKFHDECDABUVSTPRMNKLHJEF SIDE 11111111111111121122222222222222 DIRECTION IOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIO changed: 0 0 step 54 11000011100111011110011110011110 fail ^ ^^ ^ ^^ ^^^ ^ ^^ ^ ^^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER VURSNPLMJKFHDECDABUVSTPRMNKLHJEF SIDE 11111111111111121122222222222222 DIRECTION IOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIO changed: 1 1 step 55 11100111100111011110011110011110 fail ^ ^^ ^ ^^ ^^^ ^ ^^ ^ ^^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER VURSNPLMJKFHDECDABUVSTPRMNKLHJEF SIDE 11111111111111121122222222222222 DIRECTION IOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIO changed: step 56 11100111100111011110011110011110 fail ^ ^ ^^ ^^^ ^ ^^ ^ ^^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER VURSNPLMJKFHDECDABUVSTPRMNKLHJEF SIDE 11111111111111121122222222222222 DIRECTION IOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIO changed: step 57 11100111100111011110011110011110 fail ^ ^^ ^ ^^ ^^^ ^ ^^ ^ ^^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER VURSNPLMJKFHDECDABUVSTPRMNKLHJEF SIDE 11111111111111121122222222222222 DIRECTION IOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIO changed: 1 00 step 58 11101100100111011110011110011110 fail ^ ^ ^ ^^ ^^^ ^ ^^ ^ ^^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER VURSNPLMJKFHDECDABUVSTPRMNKLHJEF SIDE 11111111111111121122222222222222 DIRECTION IOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIO changed: 0 11 step 59 11100111100111011110011110011110 fail ^ ^^ ^ ^^ ^^^ ^ ^^ ^ ^^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER VURSNPLMJKFHDECDABUVSTPRMNKLHJEF SIDE 11111111111111121122222222222222 DIRECTION IOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIO changed: 01 0 step 60 11100111010011011110011110011110 fail ^ ^^ ^ ^ ^^^ ^ ^^ ^ ^^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER VURSNPLMJKFHDECDABUVSTPRMNKLHJEF SIDE 11111111111111121122222222222222 DIRECTION IOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIO changed: 10 1 step 61 11100111100111011110011110011110 fail ^ ^^ ^ ^^ ^^^ ^ ^^ ^ ^^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER VURSNPLMJKFHDECDABUVSTPRMNKLHJEF SIDE 11111111111111121122222222222222 DIRECTION IOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIO changed: step 62 11100111100111011110011110011110 fail ^ ^^ ^ ^^^ ^ ^^ ^ ^^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER VURSNPLMJKFHDECDABUVSTPRMNKLHJEF SIDE 11111111111111121122222222222222 DIRECTION IOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIO changed: step 63 11100111100111011110011110011110 fail ^ ^^ ^ ^^ ^^^ ^ ^^ ^ ^^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER VURSNPLMJKFHDECDABUVSTPRMNKLHJEF SIDE 11111111111111121122222222222222 DIRECTION IOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIO changed: 1 00 step 64 11100111101100011110011110011110 fail ^ ^^ ^ ^ ^^^ ^ ^^ ^ ^^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER VURSNPLMJKFHDECDABUVSTPRMNKLHJEF SIDE 11111111111111121122222222222222 DIRECTION IOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIO changed: 0 11 step 65 11100111100111011110011110011110 fail ^ ^^ ^ ^^ ^^^ ^ ^^ ^ ^^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER VURSNPLMJKFHDECDABUVSTPRMNKLHJEF SIDE 11111111111111121122222222222222 DIRECTION IOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIO changed: step 66 11100111100111011110011110011110 fail ^ ^^ ^ ^^ ^ ^ ^^ ^ ^^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER VURSNPLMJKFHDECDABUVSTPRMNKLHJEF SIDE 11111111111111121122222222222222 DIRECTION IOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIO changed: step 67 11100111100111011110011110011110 fail ^ ^^ ^ ^^ ^^^ ^ ^^ ^ ^^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER VURSNPLMJKFHDECDABUVSTPRMNKLHJEF SIDE 11111111111111121122222222222222 DIRECTION IOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIO changed: 1 00 step 68 11100111100111110010011110011110 fail ^ ^^ ^ ^^ ^ ^ ^ ^^ ^ ^^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER VURSNPLMJKFHDECDABUVSTPRMNKLHJEF SIDE 11111111111111121122222222222222 DIRECTION IOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIO changed: 0 11 step 69 11100111100111011110011110011110 fail ^ ^^ ^ ^^ ^^^ ^ ^^ ^ ^^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER VURSNPLMJKFHDECDABUVSTPRMNKLHJEF SIDE 11111111111111121122222222222222 DIRECTION IOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIO changed: 01 0 step 70 11100111100111011101001110011110 fail ^ ^^ ^ ^^ ^^^ ^ ^ ^ ^^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER VURSNPLMJKFHDECDABUVSTPRMNKLHJEF SIDE 11111111111111121122222222222222 DIRECTION IOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIO changed: 10 1 step 71 11100111100111011110011110011110 fail ^ ^^ ^ ^^ ^^^ ^ ^^ ^ ^^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER VURSNPLMJKFHDECDABUVSTPRMNKLHJEF SIDE 11111111111111121122222222222222 DIRECTION IOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIO changed: step 72 11100111100111011110011110011110 fail ^ ^^ ^ ^^ ^^^ ^ ^ ^^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER VURSNPLMJKFHDECDABUVSTPRMNKLHJEF SIDE 11111111111111121122222222222222 DIRECTION IOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIO changed: step 73 11100111100111011110011110011110 fail ^ ^^ ^ ^^ ^^^ ^ ^^ ^ ^^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER VURSNPLMJKFHDECDABUVSTPRMNKLHJEF SIDE 11111111111111121122222222222222 DIRECTION IOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIO changed: 1 00 step 74 11100111100111011110110010011110 fail ^ ^^ ^ ^^ ^^^ ^ ^ ^ ^^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER VURSNPLMJKFHDECDABUVSTPRMNKLHJEF SIDE 11111111111111121122222222222222 DIRECTION IOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIO changed: 0 11 step 75 11100111100111011110011110011110 fail ^ ^^ ^ ^^ ^^^ ^ ^^ ^ ^^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER VURSNPLMJKFHDECDABUVSTPRMNKLHJEF SIDE 11111111111111121122222222222222 DIRECTION IOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIO changed: 01 0 step 76 11100111100111011110011101001110 fail ^ ^^ ^ ^^ ^^^ ^ ^^ ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER VURSNPLMJKFHDECDABUVSTPRMNKLHJEF SIDE 11111111111111121122222222222222 DIRECTION IOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIO changed: 10 1 step 77 11100111100111011110011110011110 fail ^ ^^ ^ ^^ ^^^ ^ ^^ ^ ^^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER VURSNPLMJKFHDECDABUVSTPRMNKLHJEF SIDE 11111111111111121122222222222222 DIRECTION IOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIO changed: step 78 11100111100111011110011110011110 fail ^ ^^ ^ ^^ ^^^ ^ ^^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER VURSNPLMJKFHDECDABUVSTPRMNKLHJEF SIDE 11111111111111121122222222222222 DIRECTION IOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIO changed: step 79 11100111100111011110011110011110 fail ^ ^^ ^ ^^ ^^^ ^ ^^ ^ ^^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER VURSNPLMJKFHDECDABUVSTPRMNKLHJEF SIDE 11111111111111121122222222222222 DIRECTION IOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIO changed: 1 00 step 80 11100111100111011110011110110010 fail ^ ^^ ^ ^^ ^^^ ^ ^^ ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER VURSNPLMJKFHDECDABUVSTPRMNKLHJEF SIDE 11111111111111121122222222222222 DIRECTION IOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIO changed: 0 11 step 81 11100111100111011110011110011110 fail ^ ^^ ^ ^^ ^^^ ^ ^^ ^ ^^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER VURSNPLMJKFHDECDABUVSTPRMNKLHJEF SIDE 11111111111111121122222222222222 DIRECTION IOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIO changed: 0 01 step 82 11100111100111001110011110011101 fail ^ ^^ ^ ^^ ^^ ^ ^^ ^ ^^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER VURSNPLMJKFHDECDABUVSTPRMNKLHJEF SIDE 11111111111111121122222222222222 DIRECTION IOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIO changed: 1 10 step 83 11100111100111011110011110011110 fail ^ ^^ ^ ^^ ^^^ ^ ^^ ^ ^^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER VURSNPLMJKFHDECDABUVSTPRMNKLHJEF SIDE 11111111111111121122222222222222 DIRECTION IOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIO changed: step 84 11100111100111011110011110011110 fail ^ ^^ ^ ^^ ^^^ ^ ^^ ^ ^^ ^ test 55: *** FAIL *************************** 84 steps failed SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER VURSNPLMJKFHDECDABUVSTPRMNKLHJEF SIDE 11111111111111121122222222222222 DIRECTION IOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIO this fail O OIO O IO OIO O IO O IO O all fails O OIO O IO OIO O IO O IO O was hi 11111111111111111111111111111111 rising ^ ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ falling v vvvvvvvvvvvvvvvvvvvvvvvvvvvvvv was lo 0 000000000000000000000000000000 total fails 55, total passes 0 SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER VURSNPLMJKFHDECDABUVSTPRMNKLHJEF SIDE 11111111111111121122222222222222 DIRECTION IOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIO changed: 0 011000011000100001100001100001 step 1 01011000011000100001100001100001 fail ^^ ^ ^^ ^^^ ^ ^^ ^ ^^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER VURSNPLMJKFHDECDABUVSTPRMNKLHJEF SIDE 11111111111111121122222222222222 DIRECTION IOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIO changed: 0 0 0 step 2 01010000011000100001000001000001 fail ^ ^ ^^ ^^^ ^ ^ ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER VURSNPLMJKFHDECDABUVSTPRMNKLHJEF SIDE 11111111111111121122222222222222 DIRECTION IOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIO changed: 1 step 3 11010000011000100001000001000001 fail ^ ^ ^ ^^ ^^^ ^ ^ ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER VURSNPLMJKFHDECDABUVSTPRMNKLHJEF SIDE 11111111111111121122222222222222 DIRECTION IOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIO changed: 0 0 0 step 4 01010000010000000001000001000001 fail ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER VURSNPLMJKFHDECDABUVSTPRMNKLHJEF SIDE 11111111111111121122222222222222 DIRECTION IOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIO changed: step 5 01010000010000000001000001000001 fail ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER VURSNPLMJKFHDECDABUVSTPRMNKLHJEF SIDE 11111111111111121122222222222222 DIRECTION IOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIO changed: 10 1 step 6 01100100010000000001000001000001 fail ^ ^ ^ ^ ^ ^ ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER VURSNPLMJKFHDECDABUVSTPRMNKLHJEF SIDE 11111111111111121122222222222222 DIRECTION IOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIO changed: 01 0 step 7 01010000010000000001000001000001 fail ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER VURSNPLMJKFHDECDABUVSTPRMNKLHJEF SIDE 11111111111111121122222222222222 DIRECTION IOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIO changed: step 8 01010000010000000001000001000001 fail ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER VURSNPLMJKFHDECDABUVSTPRMNKLHJEF SIDE 11111111111111121122222222222222 DIRECTION IOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIO changed: 1 step 9 01011000010000000001000001000001 fail ^ ^ ^ ^ ^ ^ ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER VURSNPLMJKFHDECDABUVSTPRMNKLHJEF SIDE 11111111111111121122222222222222 DIRECTION IOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIO changed: 0 step 10 01010000010000000001000001000001 fail ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER VURSNPLMJKFHDECDABUVSTPRMNKLHJEF SIDE 11111111111111121122222222222222 DIRECTION IOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIO changed: step 11 01010000010000000001000001000001 fail ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER VURSNPLMJKFHDECDABUVSTPRMNKLHJEF SIDE 11111111111111121122222222222222 DIRECTION IOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIO changed: 11 step 12 01010011010000000001000001000001 fail ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER VURSNPLMJKFHDECDABUVSTPRMNKLHJEF SIDE 11111111111111121122222222222222 DIRECTION IOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIO changed: 00 step 13 01010000010000000001000001000001 fail ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER VURSNPLMJKFHDECDABUVSTPRMNKLHJEF SIDE 11111111111111121122222222222222 DIRECTION IOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIO changed: step 14 01010000010000000001000001000001 fail ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER VURSNPLMJKFHDECDABUVSTPRMNKLHJEF SIDE 11111111111111121122222222222222 DIRECTION IOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIO changed: 10 step 15 01010000100000000001000001000001 fail ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER VURSNPLMJKFHDECDABUVSTPRMNKLHJEF SIDE 11111111111111121122222222222222 DIRECTION IOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIO changed: 01 step 16 01010000010000000001000001000001 fail ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER VURSNPLMJKFHDECDABUVSTPRMNKLHJEF SIDE 11111111111111121122222222222222 DIRECTION IOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIO changed: step 17 01010000010000000001000001000001 fail ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER VURSNPLMJKFHDECDABUVSTPRMNKLHJEF SIDE 11111111111111121122222222222222 DIRECTION IOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIO changed: 1 step 18 01010000011000000001000001000001 fail ^ ^ ^ ^ ^ ^ ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER VURSNPLMJKFHDECDABUVSTPRMNKLHJEF SIDE 11111111111111121122222222222222 DIRECTION IOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIO changed: 0 step 19 01010000010000000001000001000001 fail ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER VURSNPLMJKFHDECDABUVSTPRMNKLHJEF SIDE 11111111111111121122222222222222 DIRECTION IOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIO changed: step 20 01010000010000000001000001000001 fail ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER VURSNPLMJKFHDECDABUVSTPRMNKLHJEF SIDE 11111111111111121122222222222222 DIRECTION IOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIO changed: 1 step 21 01010000010010000001000001000001 fail ^ ^ ^ ^ ^ ^ ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER VURSNPLMJKFHDECDABUVSTPRMNKLHJEF SIDE 11111111111111121122222222222222 DIRECTION IOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIO changed: 0 step 22 01010000010000000001000001000001 fail ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER VURSNPLMJKFHDECDABUVSTPRMNKLHJEF SIDE 11111111111111121122222222222222 DIRECTION IOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIO changed: step 23 01010000010000000001000001000001 fail ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER VURSNPLMJKFHDECDABUVSTPRMNKLHJEF SIDE 11111111111111121122222222222222 DIRECTION IOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIO changed: 1 step 24 01010000010000100001000001000001 fail ^ ^ ^ ^ ^ ^ ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER VURSNPLMJKFHDECDABUVSTPRMNKLHJEF SIDE 11111111111111121122222222222222 DIRECTION IOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIO changed: 0 step 25 01010000010000000001000001000001 fail ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER VURSNPLMJKFHDECDABUVSTPRMNKLHJEF SIDE 11111111111111121122222222222222 DIRECTION IOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIO changed: step 26 01010000010000000001000001000001 fail ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER VURSNPLMJKFHDECDABUVSTPRMNKLHJEF SIDE 11111111111111121122222222222222 DIRECTION IOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIO changed: 1 step 27 01010000010000001001000001000001 fail ^ ^ ^ ^ ^ ^ ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER VURSNPLMJKFHDECDABUVSTPRMNKLHJEF SIDE 11111111111111121122222222222222 DIRECTION IOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIO changed: 0 step 28 01010000010000000001000001000001 fail ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER VURSNPLMJKFHDECDABUVSTPRMNKLHJEF SIDE 11111111111111121122222222222222 DIRECTION IOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIO changed: step 29 01010000010000000001000001000001 fail ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER VURSNPLMJKFHDECDABUVSTPRMNKLHJEF SIDE 11111111111111121122222222222222 DIRECTION IOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIO changed: 10 1 step 30 01010000010000000010010001000001 fail ^ ^ ^ ^ ^ ^ ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER VURSNPLMJKFHDECDABUVSTPRMNKLHJEF SIDE 11111111111111121122222222222222 DIRECTION IOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIO changed: 01 0 step 31 01010000010000000001000001000001 fail ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER VURSNPLMJKFHDECDABUVSTPRMNKLHJEF SIDE 11111111111111121122222222222222 DIRECTION IOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIO changed: step 32 01010000010000000001000001000001 fail ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER VURSNPLMJKFHDECDABUVSTPRMNKLHJEF SIDE 11111111111111121122222222222222 DIRECTION IOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIO changed: 1 step 33 01010000010000000001100001000001 fail ^ ^ ^ ^ ^ ^ ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER VURSNPLMJKFHDECDABUVSTPRMNKLHJEF SIDE 11111111111111121122222222222222 DIRECTION IOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIO changed: 0 step 34 01010000010000000001000001000001 fail ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER VURSNPLMJKFHDECDABUVSTPRMNKLHJEF SIDE 11111111111111121122222222222222 DIRECTION IOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIO changed: step 35 01010000010000000001000001000001 fail ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER VURSNPLMJKFHDECDABUVSTPRMNKLHJEF SIDE 11111111111111121122222222222222 DIRECTION IOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIO changed: 11 step 36 01010000010000000001001101000001 fail ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER VURSNPLMJKFHDECDABUVSTPRMNKLHJEF SIDE 11111111111111121122222222222222 DIRECTION IOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIO changed: 00 step 37 01010000010000000001000001000001 fail ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER VURSNPLMJKFHDECDABUVSTPRMNKLHJEF SIDE 11111111111111121122222222222222 DIRECTION IOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIO changed: step 38 01010000010000000001000001000001 fail ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER VURSNPLMJKFHDECDABUVSTPRMNKLHJEF SIDE 11111111111111121122222222222222 DIRECTION IOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIO changed: 10 step 39 01010000010000000001000010000001 fail ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER VURSNPLMJKFHDECDABUVSTPRMNKLHJEF SIDE 11111111111111121122222222222222 DIRECTION IOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIO changed: 01 step 40 01010000010000000001000001000001 fail ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER VURSNPLMJKFHDECDABUVSTPRMNKLHJEF SIDE 11111111111111121122222222222222 DIRECTION IOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIO changed: step 41 01010000010000000001000001000001 fail ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER VURSNPLMJKFHDECDABUVSTPRMNKLHJEF SIDE 11111111111111121122222222222222 DIRECTION IOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIO changed: 1 step 42 01010000010000000001000001100001 fail ^ ^ ^ ^ ^ ^ ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER VURSNPLMJKFHDECDABUVSTPRMNKLHJEF SIDE 11111111111111121122222222222222 DIRECTION IOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIO changed: 0 step 43 01010000010000000001000001000001 fail ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER VURSNPLMJKFHDECDABUVSTPRMNKLHJEF SIDE 11111111111111121122222222222222 DIRECTION IOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIO changed: step 44 01010000010000000001000001000001 fail ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER VURSNPLMJKFHDECDABUVSTPRMNKLHJEF SIDE 11111111111111121122222222222222 DIRECTION IOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIO changed: 1 step 45 01010000010000000001000001001001 fail ^ ^ ^ ^ ^ ^ ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER VURSNPLMJKFHDECDABUVSTPRMNKLHJEF SIDE 11111111111111121122222222222222 DIRECTION IOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIO changed: 0 step 46 01010000010000000001000001000001 fail ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER VURSNPLMJKFHDECDABUVSTPRMNKLHJEF SIDE 11111111111111121122222222222222 DIRECTION IOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIO changed: step 47 01010000010000000001000001000001 fail ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER VURSNPLMJKFHDECDABUVSTPRMNKLHJEF SIDE 11111111111111121122222222222222 DIRECTION IOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIO changed: 10 step 48 01010000010000000001000001000010 fail ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER VURSNPLMJKFHDECDABUVSTPRMNKLHJEF SIDE 11111111111111121122222222222222 DIRECTION IOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIO changed: 01 step 49 01010000010000000001000001000001 fail ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER VURSNPLMJKFHDECDABUVSTPRMNKLHJEF SIDE 11111111111111121122222222222222 DIRECTION IOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIO changed: step 50 01010000010000000001000001000001 fail ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER VURSNPLMJKFHDECDABUVSTPRMNKLHJEF SIDE 11111111111111121122222222222222 DIRECTION IOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIO changed: 1 10 11110 111 11110 11110 11110 step 51 11100111100111011110011110011110 fail ^ ^^ ^ ^^ ^^^ ^ ^^ ^ ^^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER VURSNPLMJKFHDECDABUVSTPRMNKLHJEF SIDE 11111111111111121122222222222222 DIRECTION IOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIO changed: 0 step 52 01100111100111011110011110011110 fail ^^ ^ ^^ ^^^ ^ ^^ ^ ^^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER VURSNPLMJKFHDECDABUVSTPRMNKLHJEF SIDE 11111111111111121122222222222222 DIRECTION IOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIO changed: 1 step 53 11100111100111011110011110011110 fail ^ ^^ ^ ^^ ^^^ ^ ^^ ^ ^^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER VURSNPLMJKFHDECDABUVSTPRMNKLHJEF SIDE 11111111111111121122222222222222 DIRECTION IOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIO changed: 0 0 step 54 11000011100111011110011110011110 fail ^ ^^ ^ ^^ ^^^ ^ ^^ ^ ^^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER VURSNPLMJKFHDECDABUVSTPRMNKLHJEF SIDE 11111111111111121122222222222222 DIRECTION IOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIO changed: 1 1 step 55 11100111100111011110011110011110 fail ^ ^^ ^ ^^ ^^^ ^ ^^ ^ ^^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER VURSNPLMJKFHDECDABUVSTPRMNKLHJEF SIDE 11111111111111121122222222222222 DIRECTION IOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIO changed: step 56 11100111100111011110011110011110 fail ^ ^ ^^ ^^^ ^ ^^ ^ ^^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER VURSNPLMJKFHDECDABUVSTPRMNKLHJEF SIDE 11111111111111121122222222222222 DIRECTION IOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIO changed: step 57 11100111100111011110011110011110 fail ^ ^^ ^ ^^ ^^^ ^ ^^ ^ ^^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER VURSNPLMJKFHDECDABUVSTPRMNKLHJEF SIDE 11111111111111121122222222222222 DIRECTION IOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIO changed: 1 00 step 58 11101100100111011110011110011110 fail ^ ^ ^ ^^ ^^^ ^ ^^ ^ ^^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER VURSNPLMJKFHDECDABUVSTPRMNKLHJEF SIDE 11111111111111121122222222222222 DIRECTION IOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIO changed: 0 11 step 59 11100111100111011110011110011110 fail ^ ^^ ^ ^^ ^^^ ^ ^^ ^ ^^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER VURSNPLMJKFHDECDABUVSTPRMNKLHJEF SIDE 11111111111111121122222222222222 DIRECTION IOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIO changed: 01 0 step 60 11100111010011011110011110011110 fail ^ ^^ ^ ^ ^^^ ^ ^^ ^ ^^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER VURSNPLMJKFHDECDABUVSTPRMNKLHJEF SIDE 11111111111111121122222222222222 DIRECTION IOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIO changed: 10 1 step 61 11100111100111011110011110011110 fail ^ ^^ ^ ^^ ^^^ ^ ^^ ^ ^^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER VURSNPLMJKFHDECDABUVSTPRMNKLHJEF SIDE 11111111111111121122222222222222 DIRECTION IOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIO changed: step 62 11100111100111011110011110011110 fail ^ ^^ ^ ^^^ ^ ^^ ^ ^^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER VURSNPLMJKFHDECDABUVSTPRMNKLHJEF SIDE 11111111111111121122222222222222 DIRECTION IOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIO changed: step 63 11100111100111011110011110011110 fail ^ ^^ ^ ^^ ^^^ ^ ^^ ^ ^^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER VURSNPLMJKFHDECDABUVSTPRMNKLHJEF SIDE 11111111111111121122222222222222 DIRECTION IOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIO changed: 1 00 step 64 11100111101100011110011110011110 fail ^ ^^ ^ ^ ^^^ ^ ^^ ^ ^^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER VURSNPLMJKFHDECDABUVSTPRMNKLHJEF SIDE 11111111111111121122222222222222 DIRECTION IOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIO changed: 0 11 step 65 11100111100111011110011110011110 fail ^ ^^ ^ ^^ ^^^ ^ ^^ ^ ^^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER VURSNPLMJKFHDECDABUVSTPRMNKLHJEF SIDE 11111111111111121122222222222222 DIRECTION IOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIO changed: step 66 11100111100111011110011110011110 fail ^ ^^ ^ ^^ ^ ^ ^^ ^ ^^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER VURSNPLMJKFHDECDABUVSTPRMNKLHJEF SIDE 11111111111111121122222222222222 DIRECTION IOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIO changed: step 67 11100111100111011110011110011110 fail ^ ^^ ^ ^^ ^^^ ^ ^^ ^ ^^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER VURSNPLMJKFHDECDABUVSTPRMNKLHJEF SIDE 11111111111111121122222222222222 DIRECTION IOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIO changed: 1 00 step 68 11100111100111110010011110011110 fail ^ ^^ ^ ^^ ^ ^ ^ ^^ ^ ^^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER VURSNPLMJKFHDECDABUVSTPRMNKLHJEF SIDE 11111111111111121122222222222222 DIRECTION IOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIO changed: 0 11 step 69 11100111100111011110011110011110 fail ^ ^^ ^ ^^ ^^^ ^ ^^ ^ ^^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER VURSNPLMJKFHDECDABUVSTPRMNKLHJEF SIDE 11111111111111121122222222222222 DIRECTION IOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIO changed: 01 0 step 70 11100111100111011101001110011110 fail ^ ^^ ^ ^^ ^^^ ^ ^ ^ ^^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER VURSNPLMJKFHDECDABUVSTPRMNKLHJEF SIDE 11111111111111121122222222222222 DIRECTION IOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIO changed: 10 1 step 71 11100111100111011110011110011110 fail ^ ^^ ^ ^^ ^^^ ^ ^^ ^ ^^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER VURSNPLMJKFHDECDABUVSTPRMNKLHJEF SIDE 11111111111111121122222222222222 DIRECTION IOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIO changed: step 72 11100111100111011110011110011110 fail ^ ^^ ^ ^^ ^^^ ^ ^ ^^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER VURSNPLMJKFHDECDABUVSTPRMNKLHJEF SIDE 11111111111111121122222222222222 DIRECTION IOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIO changed: step 73 11100111100111011110011110011110 fail ^ ^^ ^ ^^ ^^^ ^ ^^ ^ ^^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER VURSNPLMJKFHDECDABUVSTPRMNKLHJEF SIDE 11111111111111121122222222222222 DIRECTION IOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIO changed: 1 00 step 74 11100111100111011110110010011110 fail ^ ^^ ^ ^^ ^^^ ^ ^ ^ ^^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER VURSNPLMJKFHDECDABUVSTPRMNKLHJEF SIDE 11111111111111121122222222222222 DIRECTION IOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIO changed: 0 11 step 75 11100111100111011110011110011110 fail ^ ^^ ^ ^^ ^^^ ^ ^^ ^ ^^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER VURSNPLMJKFHDECDABUVSTPRMNKLHJEF SIDE 11111111111111121122222222222222 DIRECTION IOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIO changed: 01 0 step 76 11100111100111011110011101001110 fail ^ ^^ ^ ^^ ^^^ ^ ^^ ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER VURSNPLMJKFHDECDABUVSTPRMNKLHJEF SIDE 11111111111111121122222222222222 DIRECTION IOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIO changed: 10 1 step 77 11100111100111011110011110011110 fail ^ ^^ ^ ^^ ^^^ ^ ^^ ^ ^^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER VURSNPLMJKFHDECDABUVSTPRMNKLHJEF SIDE 11111111111111121122222222222222 DIRECTION IOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIO changed: step 78 11100111100111011110011110011110 fail ^ ^^ ^ ^^ ^^^ ^ ^^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER VURSNPLMJKFHDECDABUVSTPRMNKLHJEF SIDE 11111111111111121122222222222222 DIRECTION IOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIO changed: step 79 11100111100111011110011110011110 fail ^ ^^ ^ ^^ ^^^ ^ ^^ ^ ^^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER VURSNPLMJKFHDECDABUVSTPRMNKLHJEF SIDE 11111111111111121122222222222222 DIRECTION IOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIO changed: 1 00 step 80 11100111100111011110011110110010 fail ^ ^^ ^ ^^ ^^^ ^ ^^ ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER VURSNPLMJKFHDECDABUVSTPRMNKLHJEF SIDE 11111111111111121122222222222222 DIRECTION IOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIO changed: 0 11 step 81 11100111100111011110011110011110 fail ^ ^^ ^ ^^ ^^^ ^ ^^ ^ ^^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER VURSNPLMJKFHDECDABUVSTPRMNKLHJEF SIDE 11111111111111121122222222222222 DIRECTION IOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIO changed: 0 01 step 82 11100111100111001110011110011101 fail ^ ^^ ^ ^^ ^^ ^ ^^ ^ ^^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER VURSNPLMJKFHDECDABUVSTPRMNKLHJEF SIDE 11111111111111121122222222222222 DIRECTION IOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIO changed: 1 10 step 83 11100111100111011110011110011110 fail ^ ^^ ^ ^^ ^^^ ^ ^^ ^ ^^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER VURSNPLMJKFHDECDABUVSTPRMNKLHJEF SIDE 11111111111111121122222222222222 DIRECTION IOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIO changed: step 84 11100111100111011110011110011110 fail ^ ^^ ^ ^^ ^^^ ^ ^^ ^ ^^ ^ test 56: *** FAIL *************************** 84 steps failed SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER VURSNPLMJKFHDECDABUVSTPRMNKLHJEF SIDE 11111111111111121122222222222222 DIRECTION IOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIO this fail O OIO O IO OIO O IO O IO O all fails O OIO O IO OIO O IO O IO O was hi 11111111111111111111111111111111 rising ^ ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ falling v vvvvvvvvvvvvvvvvvvvvvvvvvvvvvv was lo 0 000000000000000000000000000000 total fails 56, total passes 0 SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER VURSNPLMJKFHDECDABUVSTPRMNKLHJEF SIDE 11111111111111121122222222222222 DIRECTION IOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIO changed: 0 011000011000100001100001100001 step 1 01011000011000100001100001100001 fail ^^ ^ ^^ ^^^ ^ ^^ ^ ^^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER VURSNPLMJKFHDECDABUVSTPRMNKLHJEF SIDE 11111111111111121122222222222222 DIRECTION IOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIO changed: 0 0 0 step 2 01010000011000100001000001000001 fail ^ ^ ^^ ^^^ ^ ^ ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER VURSNPLMJKFHDECDABUVSTPRMNKLHJEF SIDE 11111111111111121122222222222222 DIRECTION IOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIO changed: 1 step 3 11010000011000100001000001000001 fail ^ ^ ^ ^^ ^^^ ^ ^ ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER VURSNPLMJKFHDECDABUVSTPRMNKLHJEF SIDE 11111111111111121122222222222222 DIRECTION IOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIO changed: 0 0 0 step 4 01010000010000000001000001000001 fail ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER VURSNPLMJKFHDECDABUVSTPRMNKLHJEF SIDE 11111111111111121122222222222222 DIRECTION IOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIO changed: step 5 01010000010000000001000001000001 fail ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER VURSNPLMJKFHDECDABUVSTPRMNKLHJEF SIDE 11111111111111121122222222222222 DIRECTION IOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIO changed: 10 1 step 6 01100100010000000001000001000001 fail ^ ^ ^ ^ ^ ^ ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER VURSNPLMJKFHDECDABUVSTPRMNKLHJEF SIDE 11111111111111121122222222222222 DIRECTION IOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIO changed: 01 0 step 7 01010000010000000001000001000001 fail ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER VURSNPLMJKFHDECDABUVSTPRMNKLHJEF SIDE 11111111111111121122222222222222 DIRECTION IOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIO changed: step 8 01010000010000000001000001000001 fail ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER VURSNPLMJKFHDECDABUVSTPRMNKLHJEF SIDE 11111111111111121122222222222222 DIRECTION IOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIO changed: 1 step 9 01011000010000000001000001000001 fail ^ ^ ^ ^ ^ ^ ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER VURSNPLMJKFHDECDABUVSTPRMNKLHJEF SIDE 11111111111111121122222222222222 DIRECTION IOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIO changed: 0 step 10 01010000010000000001000001000001 fail ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER VURSNPLMJKFHDECDABUVSTPRMNKLHJEF SIDE 11111111111111121122222222222222 DIRECTION IOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIO changed: step 11 01010000010000000001000001000001 fail ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER VURSNPLMJKFHDECDABUVSTPRMNKLHJEF SIDE 11111111111111121122222222222222 DIRECTION IOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIO changed: 11 step 12 01010011010000000001000001000001 fail ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER VURSNPLMJKFHDECDABUVSTPRMNKLHJEF SIDE 11111111111111121122222222222222 DIRECTION IOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIO changed: 00 step 13 01010000010000000001000001000001 fail ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER VURSNPLMJKFHDECDABUVSTPRMNKLHJEF SIDE 11111111111111121122222222222222 DIRECTION IOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIO changed: step 14 01010000010000000001000001000001 fail ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER VURSNPLMJKFHDECDABUVSTPRMNKLHJEF SIDE 11111111111111121122222222222222 DIRECTION IOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIO changed: 10 step 15 01010000100000000001000001000001 fail ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER VURSNPLMJKFHDECDABUVSTPRMNKLHJEF SIDE 11111111111111121122222222222222 DIRECTION IOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIO changed: 01 step 16 01010000010000000001000001000001 fail ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER VURSNPLMJKFHDECDABUVSTPRMNKLHJEF SIDE 11111111111111121122222222222222 DIRECTION IOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIO changed: step 17 01010000010000000001000001000001 fail ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER VURSNPLMJKFHDECDABUVSTPRMNKLHJEF SIDE 11111111111111121122222222222222 DIRECTION IOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIO changed: 1 step 18 01010000011000000001000001000001 fail ^ ^ ^ ^ ^ ^ ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER VURSNPLMJKFHDECDABUVSTPRMNKLHJEF SIDE 11111111111111121122222222222222 DIRECTION IOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIO changed: 0 step 19 01010000010000000001000001000001 fail ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER VURSNPLMJKFHDECDABUVSTPRMNKLHJEF SIDE 11111111111111121122222222222222 DIRECTION IOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIO changed: step 20 01010000010000000001000001000001 fail ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER VURSNPLMJKFHDECDABUVSTPRMNKLHJEF SIDE 11111111111111121122222222222222 DIRECTION IOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIO changed: 1 step 21 01010000010010000001000001000001 fail ^ ^ ^ ^ ^ ^ ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER VURSNPLMJKFHDECDABUVSTPRMNKLHJEF SIDE 11111111111111121122222222222222 DIRECTION IOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIO changed: 0 step 22 01010000010000000001000001000001 fail ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER VURSNPLMJKFHDECDABUVSTPRMNKLHJEF SIDE 11111111111111121122222222222222 DIRECTION IOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIO changed: step 23 01010000010000000001000001000001 fail ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER VURSNPLMJKFHDECDABUVSTPRMNKLHJEF SIDE 11111111111111121122222222222222 DIRECTION IOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIO changed: 1 step 24 01010000010000100001000001000001 fail ^ ^ ^ ^ ^ ^ ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER VURSNPLMJKFHDECDABUVSTPRMNKLHJEF SIDE 11111111111111121122222222222222 DIRECTION IOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIO changed: 0 step 25 01010000010000000001000001000001 fail ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER VURSNPLMJKFHDECDABUVSTPRMNKLHJEF SIDE 11111111111111121122222222222222 DIRECTION IOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIO changed: step 26 01010000010000000001000001000001 fail ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER VURSNPLMJKFHDECDABUVSTPRMNKLHJEF SIDE 11111111111111121122222222222222 DIRECTION IOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIO changed: 1 step 27 01010000010000001001000001000001 fail ^ ^ ^ ^ ^ ^ ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER VURSNPLMJKFHDECDABUVSTPRMNKLHJEF SIDE 11111111111111121122222222222222 DIRECTION IOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIO changed: 0 step 28 01010000010000000001000001000001 fail ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER VURSNPLMJKFHDECDABUVSTPRMNKLHJEF SIDE 11111111111111121122222222222222 DIRECTION IOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIO changed: step 29 01010000010000000001000001000001 fail ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER VURSNPLMJKFHDECDABUVSTPRMNKLHJEF SIDE 11111111111111121122222222222222 DIRECTION IOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIO changed: 10 1 step 30 01010000010000000010010001000001 fail ^ ^ ^ ^ ^ ^ ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER VURSNPLMJKFHDECDABUVSTPRMNKLHJEF SIDE 11111111111111121122222222222222 DIRECTION IOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIO changed: 01 0 step 31 01010000010000000001000001000001 fail ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER VURSNPLMJKFHDECDABUVSTPRMNKLHJEF SIDE 11111111111111121122222222222222 DIRECTION IOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIO changed: step 32 01010000010000000001000001000001 fail ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER VURSNPLMJKFHDECDABUVSTPRMNKLHJEF SIDE 11111111111111121122222222222222 DIRECTION IOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIO changed: 1 step 33 01010000010000000001100001000001 fail ^ ^ ^ ^ ^ ^ ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER VURSNPLMJKFHDECDABUVSTPRMNKLHJEF SIDE 11111111111111121122222222222222 DIRECTION IOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIO changed: 0 step 34 01010000010000000001000001000001 fail ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER VURSNPLMJKFHDECDABUVSTPRMNKLHJEF SIDE 11111111111111121122222222222222 DIRECTION IOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIO changed: step 35 01010000010000000001000001000001 fail ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER VURSNPLMJKFHDECDABUVSTPRMNKLHJEF SIDE 11111111111111121122222222222222 DIRECTION IOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIO changed: 11 step 36 01010000010000000001001101000001 fail ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER VURSNPLMJKFHDECDABUVSTPRMNKLHJEF SIDE 11111111111111121122222222222222 DIRECTION IOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIO changed: 00 step 37 01010000010000000001000001000001 fail ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER VURSNPLMJKFHDECDABUVSTPRMNKLHJEF SIDE 11111111111111121122222222222222 DIRECTION IOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIO changed: step 38 01010000010000000001000001000001 fail ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER VURSNPLMJKFHDECDABUVSTPRMNKLHJEF SIDE 11111111111111121122222222222222 DIRECTION IOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIO changed: 10 step 39 01010000010000000001000010000001 fail ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER VURSNPLMJKFHDECDABUVSTPRMNKLHJEF SIDE 11111111111111121122222222222222 DIRECTION IOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIO changed: 01 step 40 01010000010000000001000001000001 fail ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER VURSNPLMJKFHDECDABUVSTPRMNKLHJEF SIDE 11111111111111121122222222222222 DIRECTION IOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIO changed: step 41 01010000010000000001000001000001 fail ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER VURSNPLMJKFHDECDABUVSTPRMNKLHJEF SIDE 11111111111111121122222222222222 DIRECTION IOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIO changed: 1 step 42 01010000010000000001000001100001 fail ^ ^ ^ ^ ^ ^ ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER VURSNPLMJKFHDECDABUVSTPRMNKLHJEF SIDE 11111111111111121122222222222222 DIRECTION IOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIO changed: 0 step 43 01010000010000000001000001000001 fail ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER VURSNPLMJKFHDECDABUVSTPRMNKLHJEF SIDE 11111111111111121122222222222222 DIRECTION IOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIO changed: step 44 01010000010000000001000001000001 fail ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER VURSNPLMJKFHDECDABUVSTPRMNKLHJEF SIDE 11111111111111121122222222222222 DIRECTION IOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIO changed: 1 step 45 01010000010000000001000001001001 fail ^ ^ ^ ^ ^ ^ ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER VURSNPLMJKFHDECDABUVSTPRMNKLHJEF SIDE 11111111111111121122222222222222 DIRECTION IOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIO changed: 0 step 46 01010000010000000001000001000001 fail ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER VURSNPLMJKFHDECDABUVSTPRMNKLHJEF SIDE 11111111111111121122222222222222 DIRECTION IOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIO changed: step 47 01010000010000000001000001000001 fail ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER VURSNPLMJKFHDECDABUVSTPRMNKLHJEF SIDE 11111111111111121122222222222222 DIRECTION IOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIO changed: 10 step 48 01010000010000000001000001000010 fail ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER VURSNPLMJKFHDECDABUVSTPRMNKLHJEF SIDE 11111111111111121122222222222222 DIRECTION IOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIO changed: 01 step 49 01010000010000000001000001000001 fail ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER VURSNPLMJKFHDECDABUVSTPRMNKLHJEF SIDE 11111111111111121122222222222222 DIRECTION IOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIO changed: step 50 01010000010000000001000001000001 fail ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER VURSNPLMJKFHDECDABUVSTPRMNKLHJEF SIDE 11111111111111121122222222222222 DIRECTION IOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIO changed: 1 10 11110 111 11110 11110 11110 step 51 11100111100111011110011110011110 fail ^ ^^ ^ ^^ ^^^ ^ ^^ ^ ^^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER VURSNPLMJKFHDECDABUVSTPRMNKLHJEF SIDE 11111111111111121122222222222222 DIRECTION IOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIO changed: 0 step 52 01100111100111011110011110011110 fail ^^ ^ ^^ ^^^ ^ ^^ ^ ^^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER VURSNPLMJKFHDECDABUVSTPRMNKLHJEF SIDE 11111111111111121122222222222222 DIRECTION IOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIO changed: 1 step 53 11100111100111011110011110011110 fail ^ ^^ ^ ^^ ^^^ ^ ^^ ^ ^^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER VURSNPLMJKFHDECDABUVSTPRMNKLHJEF SIDE 11111111111111121122222222222222 DIRECTION IOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIO changed: 0 0 step 54 11000011100111011110011110011110 fail ^ ^^ ^ ^^ ^^^ ^ ^^ ^ ^^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER VURSNPLMJKFHDECDABUVSTPRMNKLHJEF SIDE 11111111111111121122222222222222 DIRECTION IOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIO changed: 1 1 step 55 11100111100111011110011110011110 fail ^ ^^ ^ ^^ ^^^ ^ ^^ ^ ^^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER VURSNPLMJKFHDECDABUVSTPRMNKLHJEF SIDE 11111111111111121122222222222222 DIRECTION IOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIO changed: step 56 11100111100111011110011110011110 fail ^ ^ ^^ ^^^ ^ ^^ ^ ^^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER VURSNPLMJKFHDECDABUVSTPRMNKLHJEF SIDE 11111111111111121122222222222222 DIRECTION IOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIO changed: step 57 11100111100111011110011110011110 fail ^ ^^ ^ ^^ ^^^ ^ ^^ ^ ^^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER VURSNPLMJKFHDECDABUVSTPRMNKLHJEF SIDE 11111111111111121122222222222222 DIRECTION IOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIO changed: 1 00 step 58 11101100100111011110011110011110 fail ^ ^ ^ ^^ ^^^ ^ ^^ ^ ^^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER VURSNPLMJKFHDECDABUVSTPRMNKLHJEF SIDE 11111111111111121122222222222222 DIRECTION IOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIO changed: 0 11 step 59 11100111100111011110011110011110 fail ^ ^^ ^ ^^ ^^^ ^ ^^ ^ ^^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER VURSNPLMJKFHDECDABUVSTPRMNKLHJEF SIDE 11111111111111121122222222222222 DIRECTION IOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIO changed: 01 0 step 60 11100111010011011110011110011110 fail ^ ^^ ^ ^ ^^^ ^ ^^ ^ ^^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER VURSNPLMJKFHDECDABUVSTPRMNKLHJEF SIDE 11111111111111121122222222222222 DIRECTION IOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIO changed: 10 1 step 61 11100111100111011110011110011110 fail ^ ^^ ^ ^^ ^^^ ^ ^^ ^ ^^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER VURSNPLMJKFHDECDABUVSTPRMNKLHJEF SIDE 11111111111111121122222222222222 DIRECTION IOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIO changed: step 62 11100111100111011110011110011110 fail ^ ^^ ^ ^^^ ^ ^^ ^ ^^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER VURSNPLMJKFHDECDABUVSTPRMNKLHJEF SIDE 11111111111111121122222222222222 DIRECTION IOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIO changed: step 63 11100111100111011110011110011110 fail ^ ^^ ^ ^^ ^^^ ^ ^^ ^ ^^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER VURSNPLMJKFHDECDABUVSTPRMNKLHJEF SIDE 11111111111111121122222222222222 DIRECTION IOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIO changed: 1 00 step 64 11100111101100011110011110011110 fail ^ ^^ ^ ^ ^^^ ^ ^^ ^ ^^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER VURSNPLMJKFHDECDABUVSTPRMNKLHJEF SIDE 11111111111111121122222222222222 DIRECTION IOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIO changed: 0 11 step 65 11100111100111011110011110011110 fail ^ ^^ ^ ^^ ^^^ ^ ^^ ^ ^^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER VURSNPLMJKFHDECDABUVSTPRMNKLHJEF SIDE 11111111111111121122222222222222 DIRECTION IOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIO changed: step 66 11100111100111011110011110011110 fail ^ ^^ ^ ^^ ^ ^ ^^ ^ ^^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER VURSNPLMJKFHDECDABUVSTPRMNKLHJEF SIDE 11111111111111121122222222222222 DIRECTION IOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIO changed: step 67 11100111100111011110011110011110 fail ^ ^^ ^ ^^ ^^^ ^ ^^ ^ ^^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER VURSNPLMJKFHDECDABUVSTPRMNKLHJEF SIDE 11111111111111121122222222222222 DIRECTION IOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIO changed: 1 00 step 68 11100111100111110010011110011110 fail ^ ^^ ^ ^^ ^ ^ ^ ^^ ^ ^^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER VURSNPLMJKFHDECDABUVSTPRMNKLHJEF SIDE 11111111111111121122222222222222 DIRECTION IOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIO changed: 0 11 step 69 11100111100111011110011110011110 fail ^ ^^ ^ ^^ ^^^ ^ ^^ ^ ^^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER VURSNPLMJKFHDECDABUVSTPRMNKLHJEF SIDE 11111111111111121122222222222222 DIRECTION IOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIO changed: 01 0 step 70 11100111100111011101001110011110 fail ^ ^^ ^ ^^ ^^^ ^ ^ ^ ^^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER VURSNPLMJKFHDECDABUVSTPRMNKLHJEF SIDE 11111111111111121122222222222222 DIRECTION IOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIO changed: 10 1 step 71 11100111100111011110011110011110 fail ^ ^^ ^ ^^ ^^^ ^ ^^ ^ ^^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER VURSNPLMJKFHDECDABUVSTPRMNKLHJEF SIDE 11111111111111121122222222222222 DIRECTION IOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIO changed: step 72 11100111100111011110011110011110 fail ^ ^^ ^ ^^ ^^^ ^ ^ ^^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER VURSNPLMJKFHDECDABUVSTPRMNKLHJEF SIDE 11111111111111121122222222222222 DIRECTION IOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIO changed: step 73 11100111100111011110011110011110 fail ^ ^^ ^ ^^ ^^^ ^ ^^ ^ ^^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER VURSNPLMJKFHDECDABUVSTPRMNKLHJEF SIDE 11111111111111121122222222222222 DIRECTION IOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIO changed: 1 00 step 74 11100111100111011110110010011110 fail ^ ^^ ^ ^^ ^^^ ^ ^ ^ ^^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER VURSNPLMJKFHDECDABUVSTPRMNKLHJEF SIDE 11111111111111121122222222222222 DIRECTION IOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIO changed: 0 11 step 75 11100111100111011110011110011110 fail ^ ^^ ^ ^^ ^^^ ^ ^^ ^ ^^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER VURSNPLMJKFHDECDABUVSTPRMNKLHJEF SIDE 11111111111111121122222222222222 DIRECTION IOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIO changed: 01 0 step 76 11100111100111011110011101001110 fail ^ ^^ ^ ^^ ^^^ ^ ^^ ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER VURSNPLMJKFHDECDABUVSTPRMNKLHJEF SIDE 11111111111111121122222222222222 DIRECTION IOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIO changed: 10 1 step 77 11100111100111011110011110011110 fail ^ ^^ ^ ^^ ^^^ ^ ^^ ^ ^^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER VURSNPLMJKFHDECDABUVSTPRMNKLHJEF SIDE 11111111111111121122222222222222 DIRECTION IOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIO changed: step 78 11100111100111011110011110011110 fail ^ ^^ ^ ^^ ^^^ ^ ^^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER VURSNPLMJKFHDECDABUVSTPRMNKLHJEF SIDE 11111111111111121122222222222222 DIRECTION IOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIO changed: step 79 11100111100111011110011110011110 fail ^ ^^ ^ ^^ ^^^ ^ ^^ ^ ^^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER VURSNPLMJKFHDECDABUVSTPRMNKLHJEF SIDE 11111111111111121122222222222222 DIRECTION IOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIO changed: 1 00 step 80 11100111100111011110011110110010 fail ^ ^^ ^ ^^ ^^^ ^ ^^ ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER VURSNPLMJKFHDECDABUVSTPRMNKLHJEF SIDE 11111111111111121122222222222222 DIRECTION IOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIO changed: 0 11 step 81 11100111100111011110011110011110 fail ^ ^^ ^ ^^ ^^^ ^ ^^ ^ ^^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER VURSNPLMJKFHDECDABUVSTPRMNKLHJEF SIDE 11111111111111121122222222222222 DIRECTION IOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIO changed: 0 01 step 82 11100111100111001110011110011101 fail ^ ^^ ^ ^^ ^^ ^ ^^ ^ ^^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER VURSNPLMJKFHDECDABUVSTPRMNKLHJEF SIDE 11111111111111121122222222222222 DIRECTION IOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIO changed: 1 10 step 83 11100111100111011110011110011110 fail ^ ^^ ^ ^^ ^^^ ^ ^^ ^ ^^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER VURSNPLMJKFHDECDABUVSTPRMNKLHJEF SIDE 11111111111111121122222222222222 DIRECTION IOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIO changed: step 84 11100111100111011110011110011110 fail ^ ^^ ^ ^^ ^^^ ^ ^^ ^ ^^ ^ test 57: *** FAIL *************************** 84 steps failed SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER VURSNPLMJKFHDECDABUVSTPRMNKLHJEF SIDE 11111111111111121122222222222222 DIRECTION IOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIO this fail O OIO O IO OIO O IO O IO O all fails O OIO O IO OIO O IO O IO O was hi 11111111111111111111111111111111 rising ^ ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ falling v vvvvvvvvvvvvvvvvvvvvvvvvvvvvvv was lo 0 000000000000000000000000000000 total fails 57, total passes 0 SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER VURSNPLMJKFHDECDABUVSTPRMNKLHJEF SIDE 11111111111111121122222222222222 DIRECTION IOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIO changed: 0 011000011000100001100001100001 step 1 01011000011000100001100001100001 fail ^^ ^ ^^ ^^^ ^ ^^ ^ ^^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER VURSNPLMJKFHDECDABUVSTPRMNKLHJEF SIDE 11111111111111121122222222222222 DIRECTION IOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIO changed: 0 0 0 step 2 01010000011000100001000001000001 fail ^ ^ ^^ ^^^ ^ ^ ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER VURSNPLMJKFHDECDABUVSTPRMNKLHJEF SIDE 11111111111111121122222222222222 DIRECTION IOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIO changed: 1 step 3 11010000011000100001000001000001 fail ^ ^ ^ ^^ ^^^ ^ ^ ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER VURSNPLMJKFHDECDABUVSTPRMNKLHJEF SIDE 11111111111111121122222222222222 DIRECTION IOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIO changed: 0 0 0 step 4 01010000010000000001000001000001 fail ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER VURSNPLMJKFHDECDABUVSTPRMNKLHJEF SIDE 11111111111111121122222222222222 DIRECTION IOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIO changed: step 5 01010000010000000001000001000001 fail ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER VURSNPLMJKFHDECDABUVSTPRMNKLHJEF SIDE 11111111111111121122222222222222 DIRECTION IOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIO changed: 10 1 step 6 01100100010000000001000001000001 fail ^ ^ ^ ^ ^ ^ ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER VURSNPLMJKFHDECDABUVSTPRMNKLHJEF SIDE 11111111111111121122222222222222 DIRECTION IOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIO changed: 01 0 step 7 01010000010000000001000001000001 fail ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER VURSNPLMJKFHDECDABUVSTPRMNKLHJEF SIDE 11111111111111121122222222222222 DIRECTION IOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIO changed: step 8 01010000010000000001000001000001 fail ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER VURSNPLMJKFHDECDABUVSTPRMNKLHJEF SIDE 11111111111111121122222222222222 DIRECTION IOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIO changed: 1 step 9 01011000010000000001000001000001 fail ^ ^ ^ ^ ^ ^ ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER VURSNPLMJKFHDECDABUVSTPRMNKLHJEF SIDE 11111111111111121122222222222222 DIRECTION IOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIO changed: 0 step 10 01010000010000000001000001000001 fail ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER VURSNPLMJKFHDECDABUVSTPRMNKLHJEF SIDE 11111111111111121122222222222222 DIRECTION IOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIO changed: step 11 01010000010000000001000001000001 fail ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER VURSNPLMJKFHDECDABUVSTPRMNKLHJEF SIDE 11111111111111121122222222222222 DIRECTION IOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIO changed: 11 step 12 01010011010000000001000001000001 fail ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER VURSNPLMJKFHDECDABUVSTPRMNKLHJEF SIDE 11111111111111121122222222222222 DIRECTION IOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIO changed: 00 step 13 01010000010000000001000001000001 fail ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER VURSNPLMJKFHDECDABUVSTPRMNKLHJEF SIDE 11111111111111121122222222222222 DIRECTION IOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIO changed: step 14 01010000010000000001000001000001 fail ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER VURSNPLMJKFHDECDABUVSTPRMNKLHJEF SIDE 11111111111111121122222222222222 DIRECTION IOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIO changed: 10 step 15 01010000100000000001000001000001 fail ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER VURSNPLMJKFHDECDABUVSTPRMNKLHJEF SIDE 11111111111111121122222222222222 DIRECTION IOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIO changed: 01 step 16 01010000010000000001000001000001 fail ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER VURSNPLMJKFHDECDABUVSTPRMNKLHJEF SIDE 11111111111111121122222222222222 DIRECTION IOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIO changed: step 17 01010000010000000001000001000001 fail ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER VURSNPLMJKFHDECDABUVSTPRMNKLHJEF SIDE 11111111111111121122222222222222 DIRECTION IOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIO changed: 1 step 18 01010000011000000001000001000001 fail ^ ^ ^ ^ ^ ^ ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER VURSNPLMJKFHDECDABUVSTPRMNKLHJEF SIDE 11111111111111121122222222222222 DIRECTION IOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIO changed: 0 step 19 01010000010000000001000001000001 fail ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER VURSNPLMJKFHDECDABUVSTPRMNKLHJEF SIDE 11111111111111121122222222222222 DIRECTION IOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIO changed: step 20 01010000010000000001000001000001 fail ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER VURSNPLMJKFHDECDABUVSTPRMNKLHJEF SIDE 11111111111111121122222222222222 DIRECTION IOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIO changed: 1 step 21 01010000010010000001000001000001 fail ^ ^ ^ ^ ^ ^ ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER VURSNPLMJKFHDECDABUVSTPRMNKLHJEF SIDE 11111111111111121122222222222222 DIRECTION IOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIO changed: 0 step 22 01010000010000000001000001000001 fail ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER VURSNPLMJKFHDECDABUVSTPRMNKLHJEF SIDE 11111111111111121122222222222222 DIRECTION IOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIO changed: step 23 01010000010000000001000001000001 fail ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER VURSNPLMJKFHDECDABUVSTPRMNKLHJEF SIDE 11111111111111121122222222222222 DIRECTION IOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIO changed: 1 step 24 01010000010000100001000001000001 fail ^ ^ ^ ^ ^ ^ ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER VURSNPLMJKFHDECDABUVSTPRMNKLHJEF SIDE 11111111111111121122222222222222 DIRECTION IOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIO changed: 0 step 25 01010000010000000001000001000001 fail ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER VURSNPLMJKFHDECDABUVSTPRMNKLHJEF SIDE 11111111111111121122222222222222 DIRECTION IOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIO changed: step 26 01010000010000000001000001000001 fail ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER VURSNPLMJKFHDECDABUVSTPRMNKLHJEF SIDE 11111111111111121122222222222222 DIRECTION IOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIO changed: 1 step 27 01010000010000001001000001000001 fail ^ ^ ^ ^ ^ ^ ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER VURSNPLMJKFHDECDABUVSTPRMNKLHJEF SIDE 11111111111111121122222222222222 DIRECTION IOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIO changed: 0 step 28 01010000010000000001000001000001 fail ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER VURSNPLMJKFHDECDABUVSTPRMNKLHJEF SIDE 11111111111111121122222222222222 DIRECTION IOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIO changed: step 29 01010000010000000001000001000001 fail ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER VURSNPLMJKFHDECDABUVSTPRMNKLHJEF SIDE 11111111111111121122222222222222 DIRECTION IOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIO changed: 10 1 step 30 01010000010000000010010001000001 fail ^ ^ ^ ^ ^ ^ ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER VURSNPLMJKFHDECDABUVSTPRMNKLHJEF SIDE 11111111111111121122222222222222 DIRECTION IOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIO changed: 01 0 step 31 01010000010000000001000001000001 fail ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER VURSNPLMJKFHDECDABUVSTPRMNKLHJEF SIDE 11111111111111121122222222222222 DIRECTION IOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIO changed: step 32 01010000010000000001000001000001 fail ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER VURSNPLMJKFHDECDABUVSTPRMNKLHJEF SIDE 11111111111111121122222222222222 DIRECTION IOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIO changed: 1 step 33 01010000010000000001100001000001 fail ^ ^ ^ ^ ^ ^ ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER VURSNPLMJKFHDECDABUVSTPRMNKLHJEF SIDE 11111111111111121122222222222222 DIRECTION IOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIO changed: 0 step 34 01010000010000000001000001000001 fail ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER VURSNPLMJKFHDECDABUVSTPRMNKLHJEF SIDE 11111111111111121122222222222222 DIRECTION IOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIO changed: step 35 01010000010000000001000001000001 fail ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER VURSNPLMJKFHDECDABUVSTPRMNKLHJEF SIDE 11111111111111121122222222222222 DIRECTION IOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIO changed: 11 step 36 01010000010000000001001101000001 fail ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER VURSNPLMJKFHDECDABUVSTPRMNKLHJEF SIDE 11111111111111121122222222222222 DIRECTION IOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIO changed: 00 step 37 01010000010000000001000001000001 fail ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER VURSNPLMJKFHDECDABUVSTPRMNKLHJEF SIDE 11111111111111121122222222222222 DIRECTION IOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIO changed: step 38 01010000010000000001000001000001 fail ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER VURSNPLMJKFHDECDABUVSTPRMNKLHJEF SIDE 11111111111111121122222222222222 DIRECTION IOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIO changed: 10 step 39 01010000010000000001000010000001 fail ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER VURSNPLMJKFHDECDABUVSTPRMNKLHJEF SIDE 11111111111111121122222222222222 DIRECTION IOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIO changed: 01 step 40 01010000010000000001000001000001 fail ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER VURSNPLMJKFHDECDABUVSTPRMNKLHJEF SIDE 11111111111111121122222222222222 DIRECTION IOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIO changed: step 41 01010000010000000001000001000001 fail ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER VURSNPLMJKFHDECDABUVSTPRMNKLHJEF SIDE 11111111111111121122222222222222 DIRECTION IOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIO changed: 1 step 42 01010000010000000001000001100001 fail ^ ^ ^ ^ ^ ^ ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER VURSNPLMJKFHDECDABUVSTPRMNKLHJEF SIDE 11111111111111121122222222222222 DIRECTION IOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIO changed: 0 step 43 01010000010000000001000001000001 fail ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER VURSNPLMJKFHDECDABUVSTPRMNKLHJEF SIDE 11111111111111121122222222222222 DIRECTION IOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIO changed: step 44 01010000010000000001000001000001 fail ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER VURSNPLMJKFHDECDABUVSTPRMNKLHJEF SIDE 11111111111111121122222222222222 DIRECTION IOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIO changed: 1 step 45 01010000010000000001000001001001 fail ^ ^ ^ ^ ^ ^ ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER VURSNPLMJKFHDECDABUVSTPRMNKLHJEF SIDE 11111111111111121122222222222222 DIRECTION IOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIO changed: 0 step 46 01010000010000000001000001000001 fail ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER VURSNPLMJKFHDECDABUVSTPRMNKLHJEF SIDE 11111111111111121122222222222222 DIRECTION IOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIO changed: step 47 01010000010000000001000001000001 fail ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER VURSNPLMJKFHDECDABUVSTPRMNKLHJEF SIDE 11111111111111121122222222222222 DIRECTION IOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIO changed: 10 step 48 01010000010000000001000001000010 fail ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER VURSNPLMJKFHDECDABUVSTPRMNKLHJEF SIDE 11111111111111121122222222222222 DIRECTION IOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIO changed: 01 step 49 01010000010000000001000001000001 fail ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER VURSNPLMJKFHDECDABUVSTPRMNKLHJEF SIDE 11111111111111121122222222222222 DIRECTION IOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIO changed: step 50 01010000010000000001000001000001 fail ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER VURSNPLMJKFHDECDABUVSTPRMNKLHJEF SIDE 11111111111111121122222222222222 DIRECTION IOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIO changed: 1 10 11110 111 11110 11110 11110 step 51 11100111100111011110011110011110 fail ^ ^^ ^ ^^ ^^^ ^ ^^ ^ ^^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER VURSNPLMJKFHDECDABUVSTPRMNKLHJEF SIDE 11111111111111121122222222222222 DIRECTION IOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIO changed: 0 step 52 01100111100111011110011110011110 fail ^^ ^ ^^ ^^^ ^ ^^ ^ ^^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER VURSNPLMJKFHDECDABUVSTPRMNKLHJEF SIDE 11111111111111121122222222222222 DIRECTION IOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIO changed: 1 step 53 11100111100111011110011110011110 fail ^ ^^ ^ ^^ ^^^ ^ ^^ ^ ^^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER VURSNPLMJKFHDECDABUVSTPRMNKLHJEF SIDE 11111111111111121122222222222222 DIRECTION IOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIO changed: 0 0 step 54 11000011100111011110011110011110 fail ^ ^^ ^ ^^ ^^^ ^ ^^ ^ ^^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER VURSNPLMJKFHDECDABUVSTPRMNKLHJEF SIDE 11111111111111121122222222222222 DIRECTION IOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIO changed: 1 1 step 55 11100111100111011110011110011110 fail ^ ^^ ^ ^^ ^^^ ^ ^^ ^ ^^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER VURSNPLMJKFHDECDABUVSTPRMNKLHJEF SIDE 11111111111111121122222222222222 DIRECTION IOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIO changed: step 56 11100111100111011110011110011110 fail ^ ^ ^^ ^^^ ^ ^^ ^ ^^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER VURSNPLMJKFHDECDABUVSTPRMNKLHJEF SIDE 11111111111111121122222222222222 DIRECTION IOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIO changed: step 57 11100111100111011110011110011110 fail ^ ^^ ^ ^^ ^^^ ^ ^^ ^ ^^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER VURSNPLMJKFHDECDABUVSTPRMNKLHJEF SIDE 11111111111111121122222222222222 DIRECTION IOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIO changed: 1 00 step 58 11101100100111011110011110011110 fail ^ ^ ^ ^^ ^^^ ^ ^^ ^ ^^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER VURSNPLMJKFHDECDABUVSTPRMNKLHJEF SIDE 11111111111111121122222222222222 DIRECTION IOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIO changed: 0 11 step 59 11100111100111011110011110011110 fail ^ ^^ ^ ^^ ^^^ ^ ^^ ^ ^^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER VURSNPLMJKFHDECDABUVSTPRMNKLHJEF SIDE 11111111111111121122222222222222 DIRECTION IOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIO changed: 01 0 step 60 11100111010011011110011110011110 fail ^ ^^ ^ ^ ^^^ ^ ^^ ^ ^^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER VURSNPLMJKFHDECDABUVSTPRMNKLHJEF SIDE 11111111111111121122222222222222 DIRECTION IOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIO changed: 10 1 step 61 11100111100111011110011110011110 fail ^ ^^ ^ ^^ ^^^ ^ ^^ ^ ^^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER VURSNPLMJKFHDECDABUVSTPRMNKLHJEF SIDE 11111111111111121122222222222222 DIRECTION IOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIO changed: step 62 11100111100111011110011110011110 fail ^ ^^ ^ ^^^ ^ ^^ ^ ^^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER VURSNPLMJKFHDECDABUVSTPRMNKLHJEF SIDE 11111111111111121122222222222222 DIRECTION IOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIO changed: step 63 11100111100111011110011110011110 fail ^ ^^ ^ ^^ ^^^ ^ ^^ ^ ^^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER VURSNPLMJKFHDECDABUVSTPRMNKLHJEF SIDE 11111111111111121122222222222222 DIRECTION IOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIO changed: 1 00 step 64 11100111101100011110011110011110 fail ^ ^^ ^ ^ ^^^ ^ ^^ ^ ^^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER VURSNPLMJKFHDECDABUVSTPRMNKLHJEF SIDE 11111111111111121122222222222222 DIRECTION IOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIO changed: 0 11 step 65 11100111100111011110011110011110 fail ^ ^^ ^ ^^ ^^^ ^ ^^ ^ ^^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER VURSNPLMJKFHDECDABUVSTPRMNKLHJEF SIDE 11111111111111121122222222222222 DIRECTION IOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIO changed: step 66 11100111100111011110011110011110 fail ^ ^^ ^ ^^ ^ ^ ^^ ^ ^^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER VURSNPLMJKFHDECDABUVSTPRMNKLHJEF SIDE 11111111111111121122222222222222 DIRECTION IOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIO changed: step 67 11100111100111011110011110011110 fail ^ ^^ ^ ^^ ^^^ ^ ^^ ^ ^^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER VURSNPLMJKFHDECDABUVSTPRMNKLHJEF SIDE 11111111111111121122222222222222 DIRECTION IOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIO changed: 1 00 step 68 11100111100111110010011110011110 fail ^ ^^ ^ ^^ ^ ^ ^ ^^ ^ ^^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER VURSNPLMJKFHDECDABUVSTPRMNKLHJEF SIDE 11111111111111121122222222222222 DIRECTION IOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIO changed: 0 11 step 69 11100111100111011110011110011110 fail ^ ^^ ^ ^^ ^^^ ^ ^^ ^ ^^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER VURSNPLMJKFHDECDABUVSTPRMNKLHJEF SIDE 11111111111111121122222222222222 DIRECTION IOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIO changed: 01 0 step 70 11100111100111011101001110011110 fail ^ ^^ ^ ^^ ^^^ ^ ^ ^ ^^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER VURSNPLMJKFHDECDABUVSTPRMNKLHJEF SIDE 11111111111111121122222222222222 DIRECTION IOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIO changed: 10 1 step 71 11100111100111011110011110011110 fail ^ ^^ ^ ^^ ^^^ ^ ^^ ^ ^^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER VURSNPLMJKFHDECDABUVSTPRMNKLHJEF SIDE 11111111111111121122222222222222 DIRECTION IOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIO changed: step 72 11100111100111011110011110011110 fail ^ ^^ ^ ^^ ^^^ ^ ^ ^^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER VURSNPLMJKFHDECDABUVSTPRMNKLHJEF SIDE 11111111111111121122222222222222 DIRECTION IOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIO changed: step 73 11100111100111011110011110011110 fail ^ ^^ ^ ^^ ^^^ ^ ^^ ^ ^^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER VURSNPLMJKFHDECDABUVSTPRMNKLHJEF SIDE 11111111111111121122222222222222 DIRECTION IOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIO changed: 1 00 step 74 11100111100111011110110010011110 fail ^ ^^ ^ ^^ ^^^ ^ ^ ^ ^^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER VURSNPLMJKFHDECDABUVSTPRMNKLHJEF SIDE 11111111111111121122222222222222 DIRECTION IOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIO changed: 0 11 step 75 11100111100111011110011110011110 fail ^ ^^ ^ ^^ ^^^ ^ ^^ ^ ^^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER VURSNPLMJKFHDECDABUVSTPRMNKLHJEF SIDE 11111111111111121122222222222222 DIRECTION IOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIO changed: 01 0 step 76 11100111100111011110011101001110 fail ^ ^^ ^ ^^ ^^^ ^ ^^ ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER VURSNPLMJKFHDECDABUVSTPRMNKLHJEF SIDE 11111111111111121122222222222222 DIRECTION IOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIO changed: 10 1 step 77 11100111100111011110011110011110 fail ^ ^^ ^ ^^ ^^^ ^ ^^ ^ ^^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER VURSNPLMJKFHDECDABUVSTPRMNKLHJEF SIDE 11111111111111121122222222222222 DIRECTION IOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIO changed: step 78 11100111100111011110011110011110 fail ^ ^^ ^ ^^ ^^^ ^ ^^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER VURSNPLMJKFHDECDABUVSTPRMNKLHJEF SIDE 11111111111111121122222222222222 DIRECTION IOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIO changed: step 79 11100111100111011110011110011110 fail ^ ^^ ^ ^^ ^^^ ^ ^^ ^ ^^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER VURSNPLMJKFHDECDABUVSTPRMNKLHJEF SIDE 11111111111111121122222222222222 DIRECTION IOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIO changed: 1 00 step 80 11100111100111011110011110110010 fail ^ ^^ ^ ^^ ^^^ ^ ^^ ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER VURSNPLMJKFHDECDABUVSTPRMNKLHJEF SIDE 11111111111111121122222222222222 DIRECTION IOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIO changed: 0 11 step 81 11100111100111011110011110011110 fail ^ ^^ ^ ^^ ^^^ ^ ^^ ^ ^^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER VURSNPLMJKFHDECDABUVSTPRMNKLHJEF SIDE 11111111111111121122222222222222 DIRECTION IOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIO changed: 0 01 step 82 11100111100111001110011110011101 fail ^ ^^ ^ ^^ ^^ ^ ^^ ^ ^^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER VURSNPLMJKFHDECDABUVSTPRMNKLHJEF SIDE 11111111111111121122222222222222 DIRECTION IOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIO changed: 1 10 step 83 11100111100111011110011110011110 fail ^ ^^ ^ ^^ ^^^ ^ ^^ ^ ^^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER VURSNPLMJKFHDECDABUVSTPRMNKLHJEF SIDE 11111111111111121122222222222222 DIRECTION IOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIO changed: step 84 11100111100111011110011110011110 fail ^ ^^ ^ ^^ ^^^ ^ ^^ ^ ^^ ^ test 58: *** FAIL *************************** 84 steps failed SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER VURSNPLMJKFHDECDABUVSTPRMNKLHJEF SIDE 11111111111111121122222222222222 DIRECTION IOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIO this fail O OIO O IO OIO O IO O IO O all fails O OIO O IO OIO O IO O IO O was hi 11111111111111111111111111111111 rising ^ ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ falling v vvvvvvvvvvvvvvvvvvvvvvvvvvvvvv was lo 0 000000000000000000000000000000 total fails 58, total passes 0 SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER VURSNPLMJKFHDECDABUVSTPRMNKLHJEF SIDE 11111111111111121122222222222222 DIRECTION IOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIO changed: 0 011000011000100001100001100001 step 1 01011000011000100001100001100001 fail ^^ ^ ^^ ^^^ ^ ^^ ^ ^^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER VURSNPLMJKFHDECDABUVSTPRMNKLHJEF SIDE 11111111111111121122222222222222 DIRECTION IOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIO changed: 0 0 0 step 2 01010000011000100001000001000001 fail ^ ^ ^^ ^^^ ^ ^ ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER VURSNPLMJKFHDECDABUVSTPRMNKLHJEF SIDE 11111111111111121122222222222222 DIRECTION IOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIO changed: 1 0 0 step 3 11010000010000000001000001000001 fail ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER VURSNPLMJKFHDECDABUVSTPRMNKLHJEF SIDE 11111111111111121122222222222222 DIRECTION IOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIO changed: 0 step 4 01010000010000000001000001000001 fail ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER VURSNPLMJKFHDECDABUVSTPRMNKLHJEF SIDE 11111111111111121122222222222222 DIRECTION IOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIO changed: step 5 01010000010000000001000001000001 fail ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER VURSNPLMJKFHDECDABUVSTPRMNKLHJEF SIDE 11111111111111121122222222222222 DIRECTION IOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIO changed: 10 1 step 6 01100100010000000001000001000001 fail ^ ^ ^ ^ ^ ^ ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER VURSNPLMJKFHDECDABUVSTPRMNKLHJEF SIDE 11111111111111121122222222222222 DIRECTION IOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIO changed: 01 0 step 7 01010000010000000001000001000001 fail ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER VURSNPLMJKFHDECDABUVSTPRMNKLHJEF SIDE 11111111111111121122222222222222 DIRECTION IOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIO changed: step 8 01010000010000000001000001000001 fail ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER VURSNPLMJKFHDECDABUVSTPRMNKLHJEF SIDE 11111111111111121122222222222222 DIRECTION IOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIO changed: 1 step 9 01011000010000000001000001000001 fail ^ ^ ^ ^ ^ ^ ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER VURSNPLMJKFHDECDABUVSTPRMNKLHJEF SIDE 11111111111111121122222222222222 DIRECTION IOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIO changed: 0 step 10 01010000010000000001000001000001 fail ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER VURSNPLMJKFHDECDABUVSTPRMNKLHJEF SIDE 11111111111111121122222222222222 DIRECTION IOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIO changed: step 11 01010000010000000001000001000001 fail ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER VURSNPLMJKFHDECDABUVSTPRMNKLHJEF SIDE 11111111111111121122222222222222 DIRECTION IOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIO changed: 11 step 12 01010011010000000001000001000001 fail ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER VURSNPLMJKFHDECDABUVSTPRMNKLHJEF SIDE 11111111111111121122222222222222 DIRECTION IOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIO changed: 00 step 13 01010000010000000001000001000001 fail ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER VURSNPLMJKFHDECDABUVSTPRMNKLHJEF SIDE 11111111111111121122222222222222 DIRECTION IOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIO changed: step 14 01010000010000000001000001000001 fail ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER VURSNPLMJKFHDECDABUVSTPRMNKLHJEF SIDE 11111111111111121122222222222222 DIRECTION IOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIO changed: 10 step 15 01010000100000000001000001000001 fail ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER VURSNPLMJKFHDECDABUVSTPRMNKLHJEF SIDE 11111111111111121122222222222222 DIRECTION IOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIO changed: 01 step 16 01010000010000000001000001000001 fail ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER VURSNPLMJKFHDECDABUVSTPRMNKLHJEF SIDE 11111111111111121122222222222222 DIRECTION IOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIO changed: step 17 01010000010000000001000001000001 fail ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER VURSNPLMJKFHDECDABUVSTPRMNKLHJEF SIDE 11111111111111121122222222222222 DIRECTION IOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIO changed: 1 step 18 01010000011000000001000001000001 fail ^ ^ ^ ^ ^ ^ ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER VURSNPLMJKFHDECDABUVSTPRMNKLHJEF SIDE 11111111111111121122222222222222 DIRECTION IOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIO changed: 0 step 19 01010000010000000001000001000001 fail ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER VURSNPLMJKFHDECDABUVSTPRMNKLHJEF SIDE 11111111111111121122222222222222 DIRECTION IOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIO changed: step 20 01010000010000000001000001000001 fail ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER VURSNPLMJKFHDECDABUVSTPRMNKLHJEF SIDE 11111111111111121122222222222222 DIRECTION IOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIO changed: 1 step 21 01010000010010000001000001000001 fail ^ ^ ^ ^ ^ ^ ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER VURSNPLMJKFHDECDABUVSTPRMNKLHJEF SIDE 11111111111111121122222222222222 DIRECTION IOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIO changed: 0 step 22 01010000010000000001000001000001 fail ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER VURSNPLMJKFHDECDABUVSTPRMNKLHJEF SIDE 11111111111111121122222222222222 DIRECTION IOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIO changed: step 23 01010000010000000001000001000001 fail ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER VURSNPLMJKFHDECDABUVSTPRMNKLHJEF SIDE 11111111111111121122222222222222 DIRECTION IOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIO changed: 1 step 24 01010000010000100001000001000001 fail ^ ^ ^ ^ ^ ^ ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER VURSNPLMJKFHDECDABUVSTPRMNKLHJEF SIDE 11111111111111121122222222222222 DIRECTION IOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIO changed: 0 step 25 01010000010000000001000001000001 fail ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER VURSNPLMJKFHDECDABUVSTPRMNKLHJEF SIDE 11111111111111121122222222222222 DIRECTION IOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIO changed: step 26 01010000010000000001000001000001 fail ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER VURSNPLMJKFHDECDABUVSTPRMNKLHJEF SIDE 11111111111111121122222222222222 DIRECTION IOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIO changed: 1 step 27 01010000010000001001000001000001 fail ^ ^ ^ ^ ^ ^ ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER VURSNPLMJKFHDECDABUVSTPRMNKLHJEF SIDE 11111111111111121122222222222222 DIRECTION IOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIO changed: 0 step 28 01010000010000000001000001000001 fail ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER VURSNPLMJKFHDECDABUVSTPRMNKLHJEF SIDE 11111111111111121122222222222222 DIRECTION IOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIO changed: step 29 01010000010000000001000001000001 fail ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER VURSNPLMJKFHDECDABUVSTPRMNKLHJEF SIDE 11111111111111121122222222222222 DIRECTION IOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIO changed: 10 1 step 30 01010000010000000010010001000001 fail ^ ^ ^ ^ ^ ^ ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER VURSNPLMJKFHDECDABUVSTPRMNKLHJEF SIDE 11111111111111121122222222222222 DIRECTION IOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIO changed: 01 0 step 31 01010000010000000001000001000001 fail ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER VURSNPLMJKFHDECDABUVSTPRMNKLHJEF SIDE 11111111111111121122222222222222 DIRECTION IOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIO changed: step 32 01010000010000000001000001000001 fail ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER VURSNPLMJKFHDECDABUVSTPRMNKLHJEF SIDE 11111111111111121122222222222222 DIRECTION IOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIO changed: 1 step 33 01010000010000000001100001000001 fail ^ ^ ^ ^ ^ ^ ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER VURSNPLMJKFHDECDABUVSTPRMNKLHJEF SIDE 11111111111111121122222222222222 DIRECTION IOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIO changed: 0 step 34 01010000010000000001000001000001 fail ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER VURSNPLMJKFHDECDABUVSTPRMNKLHJEF SIDE 11111111111111121122222222222222 DIRECTION IOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIO changed: step 35 01010000010000000001000001000001 fail ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER VURSNPLMJKFHDECDABUVSTPRMNKLHJEF SIDE 11111111111111121122222222222222 DIRECTION IOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIO changed: 11 step 36 01010000010000000001001101000001 fail ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER VURSNPLMJKFHDECDABUVSTPRMNKLHJEF SIDE 11111111111111121122222222222222 DIRECTION IOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIO changed: 00 step 37 01010000010000000001000001000001 fail ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER VURSNPLMJKFHDECDABUVSTPRMNKLHJEF SIDE 11111111111111121122222222222222 DIRECTION IOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIO changed: step 38 01010000010000000001000001000001 fail ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER VURSNPLMJKFHDECDABUVSTPRMNKLHJEF SIDE 11111111111111121122222222222222 DIRECTION IOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIO changed: 10 step 39 01010000010000000001000010000001 fail ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER VURSNPLMJKFHDECDABUVSTPRMNKLHJEF SIDE 11111111111111121122222222222222 DIRECTION IOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIO changed: 01 step 40 01010000010000000001000001000001 fail ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER VURSNPLMJKFHDECDABUVSTPRMNKLHJEF SIDE 11111111111111121122222222222222 DIRECTION IOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIO changed: step 41 01010000010000000001000001000001 fail ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER VURSNPLMJKFHDECDABUVSTPRMNKLHJEF SIDE 11111111111111121122222222222222 DIRECTION IOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIO changed: 1 step 42 01010000010000000001000001100001 fail ^ ^ ^ ^ ^ ^ ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER VURSNPLMJKFHDECDABUVSTPRMNKLHJEF SIDE 11111111111111121122222222222222 DIRECTION IOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIO changed: 0 step 43 01010000010000000001000001000001 fail ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER VURSNPLMJKFHDECDABUVSTPRMNKLHJEF SIDE 11111111111111121122222222222222 DIRECTION IOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIO changed: step 44 01010000010000000001000001000001 fail ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER VURSNPLMJKFHDECDABUVSTPRMNKLHJEF SIDE 11111111111111121122222222222222 DIRECTION IOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIO changed: 1 step 45 01010000010000000001000001001001 fail ^ ^ ^ ^ ^ ^ ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER VURSNPLMJKFHDECDABUVSTPRMNKLHJEF SIDE 11111111111111121122222222222222 DIRECTION IOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIO changed: 0 step 46 01010000010000000001000001000001 fail ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER VURSNPLMJKFHDECDABUVSTPRMNKLHJEF SIDE 11111111111111121122222222222222 DIRECTION IOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIO changed: step 47 01010000010000000001000001000001 fail ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER VURSNPLMJKFHDECDABUVSTPRMNKLHJEF SIDE 11111111111111121122222222222222 DIRECTION IOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIO changed: 10 step 48 01010000010000000001000001000010 fail ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER VURSNPLMJKFHDECDABUVSTPRMNKLHJEF SIDE 11111111111111121122222222222222 DIRECTION IOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIO changed: 01 step 49 01010000010000000001000001000001 fail ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER VURSNPLMJKFHDECDABUVSTPRMNKLHJEF SIDE 11111111111111121122222222222222 DIRECTION IOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIO changed: step 50 01010000010000000001000001000001 fail ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER VURSNPLMJKFHDECDABUVSTPRMNKLHJEF SIDE 11111111111111121122222222222222 DIRECTION IOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIO changed: 1 10 11110 111 11110 11110 11110 step 51 11100111100111011110011110011110 fail ^ ^^ ^ ^^ ^^^ ^ ^^ ^ ^^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER VURSNPLMJKFHDECDABUVSTPRMNKLHJEF SIDE 11111111111111121122222222222222 DIRECTION IOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIO changed: 0 step 52 01100111100111011110011110011110 fail ^^ ^ ^^ ^^^ ^ ^^ ^ ^^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER VURSNPLMJKFHDECDABUVSTPRMNKLHJEF SIDE 11111111111111121122222222222222 DIRECTION IOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIO changed: 1 step 53 11100111100111011110011110011110 fail ^ ^^ ^ ^^ ^^^ ^ ^^ ^ ^^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER VURSNPLMJKFHDECDABUVSTPRMNKLHJEF SIDE 11111111111111121122222222222222 DIRECTION IOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIO changed: 0 0 step 54 11000011100111011110011110011110 fail ^ ^^ ^ ^^ ^^^ ^ ^^ ^ ^^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER VURSNPLMJKFHDECDABUVSTPRMNKLHJEF SIDE 11111111111111121122222222222222 DIRECTION IOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIO changed: 1 1 step 55 11100111100111011110011110011110 fail ^ ^^ ^ ^^ ^^^ ^ ^^ ^ ^^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER VURSNPLMJKFHDECDABUVSTPRMNKLHJEF SIDE 11111111111111121122222222222222 DIRECTION IOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIO changed: step 56 11100111100111011110011110011110 fail ^ ^ ^^ ^^^ ^ ^^ ^ ^^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER VURSNPLMJKFHDECDABUVSTPRMNKLHJEF SIDE 11111111111111121122222222222222 DIRECTION IOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIO changed: step 57 11100111100111011110011110011110 fail ^ ^^ ^ ^^ ^^^ ^ ^^ ^ ^^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER VURSNPLMJKFHDECDABUVSTPRMNKLHJEF SIDE 11111111111111121122222222222222 DIRECTION IOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIO changed: 1 00 step 58 11101100100111011110011110011110 fail ^ ^ ^ ^^ ^^^ ^ ^^ ^ ^^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER VURSNPLMJKFHDECDABUVSTPRMNKLHJEF SIDE 11111111111111121122222222222222 DIRECTION IOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIO changed: 0 11 step 59 11100111100111011110011110011110 fail ^ ^^ ^ ^^ ^^^ ^ ^^ ^ ^^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER VURSNPLMJKFHDECDABUVSTPRMNKLHJEF SIDE 11111111111111121122222222222222 DIRECTION IOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIO changed: 01 0 step 60 11100111010011011110011110011110 fail ^ ^^ ^ ^ ^^^ ^ ^^ ^ ^^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER VURSNPLMJKFHDECDABUVSTPRMNKLHJEF SIDE 11111111111111121122222222222222 DIRECTION IOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIO changed: 10 1 step 61 11100111100111011110011110011110 fail ^ ^^ ^ ^^ ^^^ ^ ^^ ^ ^^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER VURSNPLMJKFHDECDABUVSTPRMNKLHJEF SIDE 11111111111111121122222222222222 DIRECTION IOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIO changed: step 62 11100111100111011110011110011110 fail ^ ^^ ^ ^^^ ^ ^^ ^ ^^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER VURSNPLMJKFHDECDABUVSTPRMNKLHJEF SIDE 11111111111111121122222222222222 DIRECTION IOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIO changed: step 63 11100111100111011110011110011110 fail ^ ^^ ^ ^^ ^^^ ^ ^^ ^ ^^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER VURSNPLMJKFHDECDABUVSTPRMNKLHJEF SIDE 11111111111111121122222222222222 DIRECTION IOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIO changed: 1 00 step 64 11100111101100011110011110011110 fail ^ ^^ ^ ^ ^^^ ^ ^^ ^ ^^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER VURSNPLMJKFHDECDABUVSTPRMNKLHJEF SIDE 11111111111111121122222222222222 DIRECTION IOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIO changed: 0 11 step 65 11100111100111011110011110011110 fail ^ ^^ ^ ^^ ^^^ ^ ^^ ^ ^^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER VURSNPLMJKFHDECDABUVSTPRMNKLHJEF SIDE 11111111111111121122222222222222 DIRECTION IOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIO changed: step 66 11100111100111011110011110011110 fail ^ ^^ ^ ^^ ^ ^ ^^ ^ ^^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER VURSNPLMJKFHDECDABUVSTPRMNKLHJEF SIDE 11111111111111121122222222222222 DIRECTION IOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIO changed: step 67 11100111100111011110011110011110 fail ^ ^^ ^ ^^ ^^^ ^ ^^ ^ ^^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER VURSNPLMJKFHDECDABUVSTPRMNKLHJEF SIDE 11111111111111121122222222222222 DIRECTION IOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIO changed: 1 00 step 68 11100111100111110010011110011110 fail ^ ^^ ^ ^^ ^ ^ ^ ^^ ^ ^^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER VURSNPLMJKFHDECDABUVSTPRMNKLHJEF SIDE 11111111111111121122222222222222 DIRECTION IOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIO changed: 0 11 step 69 11100111100111011110011110011110 fail ^ ^^ ^ ^^ ^^^ ^ ^^ ^ ^^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER VURSNPLMJKFHDECDABUVSTPRMNKLHJEF SIDE 11111111111111121122222222222222 DIRECTION IOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIO changed: 01 0 step 70 11100111100111011101001110011110 fail ^ ^^ ^ ^^ ^^^ ^ ^ ^ ^^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER VURSNPLMJKFHDECDABUVSTPRMNKLHJEF SIDE 11111111111111121122222222222222 DIRECTION IOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIO changed: 10 1 step 71 11100111100111011110011110011110 fail ^ ^^ ^ ^^ ^^^ ^ ^^ ^ ^^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER VURSNPLMJKFHDECDABUVSTPRMNKLHJEF SIDE 11111111111111121122222222222222 DIRECTION IOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIO changed: step 72 11100111100111011110011110011110 fail ^ ^^ ^ ^^ ^^^ ^ ^ ^^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER VURSNPLMJKFHDECDABUVSTPRMNKLHJEF SIDE 11111111111111121122222222222222 DIRECTION IOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIO changed: step 73 11100111100111011110011110011110 fail ^ ^^ ^ ^^ ^^^ ^ ^^ ^ ^^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER VURSNPLMJKFHDECDABUVSTPRMNKLHJEF SIDE 11111111111111121122222222222222 DIRECTION IOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIO changed: 1 00 step 74 11100111100111011110110010011110 fail ^ ^^ ^ ^^ ^^^ ^ ^ ^ ^^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER VURSNPLMJKFHDECDABUVSTPRMNKLHJEF SIDE 11111111111111121122222222222222 DIRECTION IOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIO changed: 0 11 step 75 11100111100111011110011110011110 fail ^ ^^ ^ ^^ ^^^ ^ ^^ ^ ^^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER VURSNPLMJKFHDECDABUVSTPRMNKLHJEF SIDE 11111111111111121122222222222222 DIRECTION IOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIO changed: 01 0 step 76 11100111100111011110011101001110 fail ^ ^^ ^ ^^ ^^^ ^ ^^ ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER VURSNPLMJKFHDECDABUVSTPRMNKLHJEF SIDE 11111111111111121122222222222222 DIRECTION IOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIO changed: 10 1 step 77 11100111100111011110011110011110 fail ^ ^^ ^ ^^ ^^^ ^ ^^ ^ ^^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER VURSNPLMJKFHDECDABUVSTPRMNKLHJEF SIDE 11111111111111121122222222222222 DIRECTION IOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIO changed: step 78 11100111100111011110011110011110 fail ^ ^^ ^ ^^ ^^^ ^ ^^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER VURSNPLMJKFHDECDABUVSTPRMNKLHJEF SIDE 11111111111111121122222222222222 DIRECTION IOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIO changed: step 79 11100111100111011110011110011110 fail ^ ^^ ^ ^^ ^^^ ^ ^^ ^ ^^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER VURSNPLMJKFHDECDABUVSTPRMNKLHJEF SIDE 11111111111111121122222222222222 DIRECTION IOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIO changed: 1 00 step 80 11100111100111011110011110110010 fail ^ ^^ ^ ^^ ^^^ ^ ^^ ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER VURSNPLMJKFHDECDABUVSTPRMNKLHJEF SIDE 11111111111111121122222222222222 DIRECTION IOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIO changed: 0 11 step 81 11100111100111011110011110011110 fail ^ ^^ ^ ^^ ^^^ ^ ^^ ^ ^^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER VURSNPLMJKFHDECDABUVSTPRMNKLHJEF SIDE 11111111111111121122222222222222 DIRECTION IOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIO changed: 0 01 step 82 11100111100111001110011110011101 fail ^ ^^ ^ ^^ ^^ ^ ^^ ^ ^^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER VURSNPLMJKFHDECDABUVSTPRMNKLHJEF SIDE 11111111111111121122222222222222 DIRECTION IOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIO changed: 1 10 step 83 11100111100111011110011110011110 fail ^ ^^ ^ ^^ ^^^ ^ ^^ ^ ^^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER VURSNPLMJKFHDECDABUVSTPRMNKLHJEF SIDE 11111111111111121122222222222222 DIRECTION IOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIO changed: step 84 11100111100111011110011110011110 fail ^ ^^ ^ ^^ ^^^ ^ ^^ ^ ^^ ^ test 59: *** FAIL *************************** 84 steps failed SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER VURSNPLMJKFHDECDABUVSTPRMNKLHJEF SIDE 11111111111111121122222222222222 DIRECTION IOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIO this fail O OIO O IO OIO O IO O IO O all fails O OIO O IO OIO O IO O IO O was hi 11111111111111111111111111111111 rising ^ ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ falling v vvvvvvvvvvvvvvvvvvvvvvvvvvvvvv was lo 0 000000000000000000000000000000 total fails 59, total passes 0 SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER VURSNPLMJKFHDECDABUVSTPRMNKLHJEF SIDE 11111111111111121122222222222222 DIRECTION IOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIO changed: 0 011000011000100001100001100001 step 1 01011000011000100001100001100001 fail ^^ ^ ^^ ^^^ ^ ^^ ^ ^^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER VURSNPLMJKFHDECDABUVSTPRMNKLHJEF SIDE 11111111111111121122222222222222 DIRECTION IOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIO changed: 0 0 0 step 2 01010000011000100001000001000001 fail ^ ^ ^^ ^^^ ^ ^ ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER VURSNPLMJKFHDECDABUVSTPRMNKLHJEF SIDE 11111111111111121122222222222222 DIRECTION IOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIO changed: 1 step 3 11010000011000100001000001000001 fail ^ ^ ^ ^^ ^^^ ^ ^ ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER VURSNPLMJKFHDECDABUVSTPRMNKLHJEF SIDE 11111111111111121122222222222222 DIRECTION IOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIO changed: 0 0 0 step 4 01010000010000000001000001000001 fail ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER VURSNPLMJKFHDECDABUVSTPRMNKLHJEF SIDE 11111111111111121122222222222222 DIRECTION IOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIO changed: step 5 01010000010000000001000001000001 fail ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER VURSNPLMJKFHDECDABUVSTPRMNKLHJEF SIDE 11111111111111121122222222222222 DIRECTION IOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIO changed: 10 1 step 6 01100100010000000001000001000001 fail ^ ^ ^ ^ ^ ^ ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER VURSNPLMJKFHDECDABUVSTPRMNKLHJEF SIDE 11111111111111121122222222222222 DIRECTION IOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIO changed: 01 0 step 7 01010000010000000001000001000001 fail ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER VURSNPLMJKFHDECDABUVSTPRMNKLHJEF SIDE 11111111111111121122222222222222 DIRECTION IOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIO changed: step 8 01010000010000000001000001000001 fail ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER VURSNPLMJKFHDECDABUVSTPRMNKLHJEF SIDE 11111111111111121122222222222222 DIRECTION IOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIO changed: 1 step 9 01011000010000000001000001000001 fail ^ ^ ^ ^ ^ ^ ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER VURSNPLMJKFHDECDABUVSTPRMNKLHJEF SIDE 11111111111111121122222222222222 DIRECTION IOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIO changed: 0 step 10 01010000010000000001000001000001 fail ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER VURSNPLMJKFHDECDABUVSTPRMNKLHJEF SIDE 11111111111111121122222222222222 DIRECTION IOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIO changed: step 11 01010000010000000001000001000001 fail ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER VURSNPLMJKFHDECDABUVSTPRMNKLHJEF SIDE 11111111111111121122222222222222 DIRECTION IOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIO changed: 11 step 12 01010011010000000001000001000001 fail ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER VURSNPLMJKFHDECDABUVSTPRMNKLHJEF SIDE 11111111111111121122222222222222 DIRECTION IOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIO changed: 00 step 13 01010000010000000001000001000001 fail ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER VURSNPLMJKFHDECDABUVSTPRMNKLHJEF SIDE 11111111111111121122222222222222 DIRECTION IOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIO changed: step 14 01010000010000000001000001000001 fail ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER VURSNPLMJKFHDECDABUVSTPRMNKLHJEF SIDE 11111111111111121122222222222222 DIRECTION IOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIO changed: 10 step 15 01010000100000000001000001000001 fail ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER VURSNPLMJKFHDECDABUVSTPRMNKLHJEF SIDE 11111111111111121122222222222222 DIRECTION IOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIO changed: 01 step 16 01010000010000000001000001000001 fail ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER VURSNPLMJKFHDECDABUVSTPRMNKLHJEF SIDE 11111111111111121122222222222222 DIRECTION IOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIO changed: step 17 01010000010000000001000001000001 fail ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER VURSNPLMJKFHDECDABUVSTPRMNKLHJEF SIDE 11111111111111121122222222222222 DIRECTION IOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIO changed: 1 step 18 01010000011000000001000001000001 fail ^ ^ ^ ^ ^ ^ ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER VURSNPLMJKFHDECDABUVSTPRMNKLHJEF SIDE 11111111111111121122222222222222 DIRECTION IOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIO changed: 0 step 19 01010000010000000001000001000001 fail ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER VURSNPLMJKFHDECDABUVSTPRMNKLHJEF SIDE 11111111111111121122222222222222 DIRECTION IOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIO changed: step 20 01010000010000000001000001000001 fail ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER VURSNPLMJKFHDECDABUVSTPRMNKLHJEF SIDE 11111111111111121122222222222222 DIRECTION IOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIO changed: 1 step 21 01010000010010000001000001000001 fail ^ ^ ^ ^ ^ ^ ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER VURSNPLMJKFHDECDABUVSTPRMNKLHJEF SIDE 11111111111111121122222222222222 DIRECTION IOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIO changed: 0 step 22 01010000010000000001000001000001 fail ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER VURSNPLMJKFHDECDABUVSTPRMNKLHJEF SIDE 11111111111111121122222222222222 DIRECTION IOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIO changed: step 23 01010000010000000001000001000001 fail ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER VURSNPLMJKFHDECDABUVSTPRMNKLHJEF SIDE 11111111111111121122222222222222 DIRECTION IOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIO changed: 1 step 24 01010000010000100001000001000001 fail ^ ^ ^ ^ ^ ^ ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER VURSNPLMJKFHDECDABUVSTPRMNKLHJEF SIDE 11111111111111121122222222222222 DIRECTION IOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIO changed: 0 step 25 01010000010000000001000001000001 fail ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER VURSNPLMJKFHDECDABUVSTPRMNKLHJEF SIDE 11111111111111121122222222222222 DIRECTION IOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIO changed: step 26 01010000010000000001000001000001 fail ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER VURSNPLMJKFHDECDABUVSTPRMNKLHJEF SIDE 11111111111111121122222222222222 DIRECTION IOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIO changed: 1 step 27 01010000010000001001000001000001 fail ^ ^ ^ ^ ^ ^ ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER VURSNPLMJKFHDECDABUVSTPRMNKLHJEF SIDE 11111111111111121122222222222222 DIRECTION IOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIO changed: 0 step 28 01010000010000000001000001000001 fail ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER VURSNPLMJKFHDECDABUVSTPRMNKLHJEF SIDE 11111111111111121122222222222222 DIRECTION IOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIO changed: step 29 01010000010000000001000001000001 fail ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER VURSNPLMJKFHDECDABUVSTPRMNKLHJEF SIDE 11111111111111121122222222222222 DIRECTION IOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIO changed: 10 1 step 30 01010000010000000010010001000001 fail ^ ^ ^ ^ ^ ^ ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER VURSNPLMJKFHDECDABUVSTPRMNKLHJEF SIDE 11111111111111121122222222222222 DIRECTION IOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIO changed: 01 0 step 31 01010000010000000001000001000001 fail ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER VURSNPLMJKFHDECDABUVSTPRMNKLHJEF SIDE 11111111111111121122222222222222 DIRECTION IOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIO changed: step 32 01010000010000000001000001000001 fail ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER VURSNPLMJKFHDECDABUVSTPRMNKLHJEF SIDE 11111111111111121122222222222222 DIRECTION IOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIO changed: 1 step 33 01010000010000000001100001000001 fail ^ ^ ^ ^ ^ ^ ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER VURSNPLMJKFHDECDABUVSTPRMNKLHJEF SIDE 11111111111111121122222222222222 DIRECTION IOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIO changed: 0 step 34 01010000010000000001000001000001 fail ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER VURSNPLMJKFHDECDABUVSTPRMNKLHJEF SIDE 11111111111111121122222222222222 DIRECTION IOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIO changed: step 35 01010000010000000001000001000001 fail ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER VURSNPLMJKFHDECDABUVSTPRMNKLHJEF SIDE 11111111111111121122222222222222 DIRECTION IOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIO changed: 11 step 36 01010000010000000001001101000001 fail ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER VURSNPLMJKFHDECDABUVSTPRMNKLHJEF SIDE 11111111111111121122222222222222 DIRECTION IOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIO changed: 00 step 37 01010000010000000001000001000001 fail ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER VURSNPLMJKFHDECDABUVSTPRMNKLHJEF SIDE 11111111111111121122222222222222 DIRECTION IOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIO changed: step 38 01010000010000000001000001000001 fail ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER VURSNPLMJKFHDECDABUVSTPRMNKLHJEF SIDE 11111111111111121122222222222222 DIRECTION IOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIO changed: 10 step 39 01010000010000000001000010000001 fail ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER VURSNPLMJKFHDECDABUVSTPRMNKLHJEF SIDE 11111111111111121122222222222222 DIRECTION IOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIO changed: 01 step 40 01010000010000000001000001000001 fail ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER VURSNPLMJKFHDECDABUVSTPRMNKLHJEF SIDE 11111111111111121122222222222222 DIRECTION IOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIO changed: step 41 01010000010000000001000001000001 fail ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER VURSNPLMJKFHDECDABUVSTPRMNKLHJEF SIDE 11111111111111121122222222222222 DIRECTION IOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIO changed: 1 step 42 01010000010000000001000001100001 fail ^ ^ ^ ^ ^ ^ ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER VURSNPLMJKFHDECDABUVSTPRMNKLHJEF SIDE 11111111111111121122222222222222 DIRECTION IOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIO changed: 0 step 43 01010000010000000001000001000001 fail ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER VURSNPLMJKFHDECDABUVSTPRMNKLHJEF SIDE 11111111111111121122222222222222 DIRECTION IOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIO changed: step 44 01010000010000000001000001000001 fail ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER VURSNPLMJKFHDECDABUVSTPRMNKLHJEF SIDE 11111111111111121122222222222222 DIRECTION IOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIO changed: 1 step 45 01010000010000000001000001001001 fail ^ ^ ^ ^ ^ ^ ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER VURSNPLMJKFHDECDABUVSTPRMNKLHJEF SIDE 11111111111111121122222222222222 DIRECTION IOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIO changed: 0 step 46 01010000010000000001000001000001 fail ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER VURSNPLMJKFHDECDABUVSTPRMNKLHJEF SIDE 11111111111111121122222222222222 DIRECTION IOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIO changed: step 47 01010000010000000001000001000001 fail ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER VURSNPLMJKFHDECDABUVSTPRMNKLHJEF SIDE 11111111111111121122222222222222 DIRECTION IOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIO changed: 10 step 48 01010000010000000001000001000010 fail ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER VURSNPLMJKFHDECDABUVSTPRMNKLHJEF SIDE 11111111111111121122222222222222 DIRECTION IOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIO changed: 01 step 49 01010000010000000001000001000001 fail ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER VURSNPLMJKFHDECDABUVSTPRMNKLHJEF SIDE 11111111111111121122222222222222 DIRECTION IOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIO changed: step 50 01010000010000000001000001000001 fail ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER VURSNPLMJKFHDECDABUVSTPRMNKLHJEF SIDE 11111111111111121122222222222222 DIRECTION IOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIO changed: 1 10 11110 111 11110 11110 11110 step 51 11100111100111011110011110011110 fail ^ ^^ ^ ^^ ^^^ ^ ^^ ^ ^^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER VURSNPLMJKFHDECDABUVSTPRMNKLHJEF SIDE 11111111111111121122222222222222 DIRECTION IOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIO changed: 0 step 52 01100111100111011110011110011110 fail ^^ ^ ^^ ^^^ ^ ^^ ^ ^^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER VURSNPLMJKFHDECDABUVSTPRMNKLHJEF SIDE 11111111111111121122222222222222 DIRECTION IOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIO changed: 1 step 53 11100111100111011110011110011110 fail ^ ^^ ^ ^^ ^^^ ^ ^^ ^ ^^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER VURSNPLMJKFHDECDABUVSTPRMNKLHJEF SIDE 11111111111111121122222222222222 DIRECTION IOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIO changed: 0 0 step 54 11000011100111011110011110011110 fail ^ ^^ ^ ^^ ^^^ ^ ^^ ^ ^^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER VURSNPLMJKFHDECDABUVSTPRMNKLHJEF SIDE 11111111111111121122222222222222 DIRECTION IOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIO changed: 1 1 step 55 11100111100111011110011110011110 fail ^ ^^ ^ ^^ ^^^ ^ ^^ ^ ^^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER VURSNPLMJKFHDECDABUVSTPRMNKLHJEF SIDE 11111111111111121122222222222222 DIRECTION IOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIO changed: step 56 11100111100111011110011110011110 fail ^ ^ ^^ ^^^ ^ ^^ ^ ^^ ^ space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C toggle comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER VURSNPLMJKFHDECDABUVSTPRMNKLHJEF SIDE 11111111111111121122222222222222 DIRECTION IOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIO all fails O OIO O IO OIO O IO O IO O was lo 0 000000000000000000000000000000 falling v vvvvvvvvvvvvvvvvvvvvvvvvvvvvvv rising ^ ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ was hi 11111111111111111111111111111111 total fails 59, total passes 0 Main menu Mon Jul 27 14:46:59 2015 test file is: tests\m111.tst delay is: 0 trigger is: 1 1 read test file 2 set test delay 3 set test trigger 4 run test 5 output loading test 8 diags 9 exit UUT power is okay Mon Jul 27 14:47:01 2015 space single step O run once (one test, all steps) F run, stop on fail G go (run tests N run, stop on fail, no print S scope (run, no print) C toggle comment printout + increase speed (less delay) - decrease speed (more delay)(slower) Q quit test SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER VURSNPLMJKFHDECDABUVSTPRMNKLHJEF SIDE 11111111111111121122222222222222 DIRECTION IOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIO changed: step 1 01010000010000000001000001000001 fail ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C toggle comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER VURSNPLMJKFHDECDABUVSTPRMNKLHJEF SIDE 11111111111111121122222222222222 DIRECTION IOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIO all fails O O O O O O O O O O was lo 0 0 00000 000000000 00000 00000 falling rising was hi 1 1 1 1 1 1 total fails 0, total passes 0 Main menu Mon Jul 27 14:47:36 2015 test file is: tests\m111.tst delay is: 0 trigger is: 1 1 read test file 2 set test delay 3 set test trigger 4 run test 5 output loading test 8 diags 9 exit Enter test file name? trying to open test file: tests\m113.tst reading test file: tests\m113.tst comment: M113 10 2-input NAND comment: pins: PINS pins: 1 I AA1 E1-1 pins: 2 I AB1 E1-2 pins: 3 O AC1 E1-3 pins: 4 I AD1 E1-4 pins: 5 I AE1 E1-5 pins: 6 O AF1 E1-6 pins: 7 I AD2 E1-13 pins: 8 I AE2 E1-12 pins: 9 O AF2 E1-11 pins: 10 I AH1 E3-4 pins: 11 I AJ1 E3-5 pins: 12 O AK1 E3-6 pins: 13 I AH2 E3-10 pins: 14 I AJ2 E3-9 pins: 15 O AK2 E3-8 pins: 16 I AL1 E2-1 pins: 17 I AM1 E2-2 pins: 18 O AN1 E2-3 pins: 19 I AL2 E3-10 pins: 20 I AM2 E3-9 pins: 21 O AN2 E3-8 pins: 22 I AP1 E2-4 pins: 23 I AR1 E2-5 pins: 24 O AS1 E2-6 pins: 25 I AP2 E2-13 pins: 26 I AR2 E2-12 pins: 27 O AS2 E2-11 pins: 28 I AT2 E2-10 pins: 29 I AU2 E2-9 pins: 30 O AV2 E2-8 pins: direction: IIOIIOIIOIIOIIOIIOIIOIIOIIOIIO test 1: 001001001001001001001001001001 test 2: 110110110110110110110110110110 test 3: 011 test 4: 001 test 5: 101 test 6: 110 test 7: 011 test 8: 001 test 9: 101 test 10: 110 test 11: 011 test 12: 001 test 13: 101 test 14: 110 test 15: 011 test 16: 001 test 17: 101 test 18: 110 test 19: 011 test 20: 001 test 21: 101 test 22: 110 test 23: 011 test 24: 001 test 25: 101 test 26: 110 test 27: 011 test 28: 001 test 29: 101 test 30: 110 test 31: 011 test 32: 001 test 33: 101 test 34: 110 test 35: 011 test 36: 001 test 37: 101 test 38: 110 test 39: 011 test 40: 001 test 41: 101 test 42: 110 test 43: 001001001001001001001001001001 test 44: 011 test 45: 110 test 46: 101 test 47: 001 test 48: 011 test 49: 110 test 50: 101 test 51: 001 test 52: 011 test 53: 110 test 54: 101 test 55: 001 test 56: 011 test 57: 110 test 58: 101 test 59: 001 test 60: 011 test 61: 110 test 62: 101 test 63: 001 test 64: 011 test 65: 110 test 66: 101 test 67: 001 test 68: 011 test 69: 110 test 70: 101 test 71: 001 test 72: 011 test 73: 110 test 74: 101 test 75: 001 test 76: 011 test 77: 110 test 78: 101 test 79: 001 test 80: 011 test 81: 110 test 82: 101 test 83: 001 end: END summary column 1: offset 0, mask 0x8000 column 2: offset 0, mask 0x4000 column 3: offset 0, mask 0x2000 column 4: offset 0, mask 0x1000 column 5: offset 0, mask 0x0800 column 6: offset 0, mask 0x0400 column 7: offset 0, mask 0x0010 column 8: offset 0, mask 0x0008 column 9: offset 0, mask 0x0004 column 10: offset 0, mask 0x0200 column 11: offset 0, mask 0x0100 column 12: offset 1, mask 0x8000 column 13: offset 0, mask 0x0002 column 14: offset 0, mask 0x0001 column 15: offset 1, mask 0x0001 column 16: offset 1, mask 0x4000 column 17: offset 1, mask 0x2000 column 18: offset 1, mask 0x1000 column 19: offset 1, mask 0x0002 column 20: offset 1, mask 0x0004 column 21: offset 1, mask 0x0008 column 22: offset 1, mask 0x0800 column 23: offset 1, mask 0x0400 column 24: offset 1, mask 0x0200 column 25: offset 1, mask 0x0010 column 26: offset 1, mask 0x0020 column 27: offset 1, mask 0x0040 column 28: offset 1, mask 0x0080 column 29: offset 2, mask 0x0001 column 30: offset 2, mask 0x0002 direction bits (1=input) 0x24E4 0x9349 0xFFFA 0xFFFF 0xF0FF pullup bits (1=pullup) 0x0000 0x0000 0x0000 0x0000 0x0000 test step out_data dont care 1: 0x2404 0x9249 0x0002 0x0000 0x0000 2: 0xDB1B 0x6CB6 0x0001 0x0000 0x0000 3: 0x7B1B 0x6CB6 0x0001 0x0000 0x0000 4: 0x3B1B 0x6CB6 0x0001 0x0000 0x0000 5: 0xBB1B 0x6CB6 0x0001 0x0000 0x0000 6: 0xDB1B 0x6CB6 0x0001 0x0000 0x0000 7: 0xCF1B 0x6CB6 0x0001 0x0000 0x0000 8: 0xC71B 0x6CB6 0x0001 0x0000 0x0000 9: 0xD71B 0x6CB6 0x0001 0x0000 0x0000 10: 0xDB1B 0x6CB6 0x0001 0x0000 0x0000 11: 0xDB0F 0x6CB6 0x0001 0x0000 0x0000 12: 0xDB07 0x6CB6 0x0001 0x0000 0x0000 13: 0xDB17 0x6CB6 0x0001 0x0000 0x0000 14: 0xDB1B 0x6CB6 0x0001 0x0000 0x0000 15: 0xD91B 0xECB6 0x0001 0x0000 0x0000 16: 0xD81B 0xECB6 0x0001 0x0000 0x0000 17: 0xDA1B 0xECB6 0x0001 0x0000 0x0000 18: 0xDB1B 0x6CB6 0x0001 0x0000 0x0000 19: 0xDB19 0x6CB7 0x0001 0x0000 0x0000 20: 0xDB18 0x6CB7 0x0001 0x0000 0x0000 21: 0xDB1A 0x6CB7 0x0001 0x0000 0x0000 22: 0xDB1B 0x6CB6 0x0001 0x0000 0x0000 23: 0xDB1B 0x3CB6 0x0001 0x0000 0x0000 24: 0xDB1B 0x1CB6 0x0001 0x0000 0x0000 25: 0xDB1B 0x5CB6 0x0001 0x0000 0x0000 26: 0xDB1B 0x6CB6 0x0001 0x0000 0x0000 27: 0xDB1B 0x6CBC 0x0001 0x0000 0x0000 28: 0xDB1B 0x6CB8 0x0001 0x0000 0x0000 29: 0xDB1B 0x6CBA 0x0001 0x0000 0x0000 30: 0xDB1B 0x6CB6 0x0001 0x0000 0x0000 31: 0xDB1B 0x66B6 0x0001 0x0000 0x0000 32: 0xDB1B 0x62B6 0x0001 0x0000 0x0000 33: 0xDB1B 0x6AB6 0x0001 0x0000 0x0000 34: 0xDB1B 0x6CB6 0x0001 0x0000 0x0000 35: 0xDB1B 0x6CE6 0x0001 0x0000 0x0000 36: 0xDB1B 0x6CC6 0x0001 0x0000 0x0000 37: 0xDB1B 0x6CD6 0x0001 0x0000 0x0000 38: 0xDB1B 0x6CB6 0x0001 0x0000 0x0000 39: 0xDB1B 0x6C36 0x0003 0x0000 0x0000 40: 0xDB1B 0x6C36 0x0002 0x0000 0x0000 41: 0xDB1B 0x6CB6 0x0002 0x0000 0x0000 42: 0xDB1B 0x6CB6 0x0001 0x0000 0x0000 43: 0x2404 0x9249 0x0002 0x0000 0x0000 44: 0x6404 0x9249 0x0002 0x0000 0x0000 45: 0xC404 0x9249 0x0002 0x0000 0x0000 46: 0xA404 0x9249 0x0002 0x0000 0x0000 47: 0x2404 0x9249 0x0002 0x0000 0x0000 48: 0x2C04 0x9249 0x0002 0x0000 0x0000 49: 0x3804 0x9249 0x0002 0x0000 0x0000 50: 0x3404 0x9249 0x0002 0x0000 0x0000 51: 0x2404 0x9249 0x0002 0x0000 0x0000 52: 0x240C 0x9249 0x0002 0x0000 0x0000 53: 0x2418 0x9249 0x0002 0x0000 0x0000 54: 0x2414 0x9249 0x0002 0x0000 0x0000 55: 0x2404 0x9249 0x0002 0x0000 0x0000 56: 0x2504 0x9249 0x0002 0x0000 0x0000 57: 0x2704 0x1249 0x0002 0x0000 0x0000 58: 0x2604 0x9249 0x0002 0x0000 0x0000 59: 0x2404 0x9249 0x0002 0x0000 0x0000 60: 0x2405 0x9249 0x0002 0x0000 0x0000 61: 0x2407 0x9248 0x0002 0x0000 0x0000 62: 0x2406 0x9249 0x0002 0x0000 0x0000 63: 0x2404 0x9249 0x0002 0x0000 0x0000 64: 0x2404 0xB249 0x0002 0x0000 0x0000 65: 0x2404 0xE249 0x0002 0x0000 0x0000 66: 0x2404 0xD249 0x0002 0x0000 0x0000 67: 0x2404 0x9249 0x0002 0x0000 0x0000 68: 0x2404 0x924D 0x0002 0x0000 0x0000 69: 0x2404 0x9247 0x0002 0x0000 0x0000 70: 0x2404 0x924B 0x0002 0x0000 0x0000 71: 0x2404 0x9249 0x0002 0x0000 0x0000 72: 0x2404 0x9649 0x0002 0x0000 0x0000 73: 0x2404 0x9C49 0x0002 0x0000 0x0000 74: 0x2404 0x9A49 0x0002 0x0000 0x0000 75: 0x2404 0x9249 0x0002 0x0000 0x0000 76: 0x2404 0x9269 0x0002 0x0000 0x0000 77: 0x2404 0x9239 0x0002 0x0000 0x0000 78: 0x2404 0x9259 0x0002 0x0000 0x0000 79: 0x2404 0x9249 0x0002 0x0000 0x0000 80: 0x2404 0x9249 0x0003 0x0000 0x0000 81: 0x2404 0x92C9 0x0001 0x0000 0x0000 82: 0x2404 0x92C9 0x0002 0x0000 0x0000 83: 0x2404 0x9249 0x0002 0x0000 0x0000 PINs used (in edge connector order) (G=ground,P=power) SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBB LETTER ABCDEFHJKLMNPRSTUVABCDEFHJKLMNPRSTUVABCDEFHJKLMNPRSTUVABCDEFHJKLMNPRSTUV SIDE 111111111111111111222222222222222222111111111111111111222222222222222222 USAGE IIOIIOIIOIIOIIOG P GIIOIIOIIOIIOIIO G P G UUT has 20 inputs UUT has 10 outputs contains 30 pins/columns 36 pins are not used contains 83 'test steps' M113 10 2-input NAND PINS Main menu Mon Jul 27 14:47:52 2015 test file is: tests\m113.tst delay is: 0 trigger is: 1 1 read test file 2 set test delay 3 set test trigger 4 run test 5 output loading test 8 diags 9 exit UUT power is okay Mon Jul 27 14:47:57 2015 space single step O run once (one test, all steps) F run, stop on fail G go (run tests N run, stop on fail, no print S scope (run, no print) C toggle comment printout + increase speed (less delay) - decrease speed (more delay)(slower) Q quit test step 1 001001001001001001001001001001 step 2 110110110110110110110110110110 step 3 011110110110110110110110110110 step 4 001110110110110110110110110110 step 5 101110110110110110110110110110 step 6 110110110110110110110110110110 step 7 110011110110110110110110110110 step 8 110001110110110110110110110110 step 9 110101110110110110110110110110 step 10 110110110110110110110110110110 step 11 110110011110110110110110110110 step 12 110110001110110110110110110110 step 13 110110101110110110110110110110 step 14 110110110110110110110110110110 step 15 110110110011110110110110110110 step 16 110110110001110110110110110110 step 17 110110110101110110110110110110 step 18 110110110110110110110110110110 step 19 110110110110011110110110110110 step 20 110110110110001110110110110110 step 21 110110110110101110110110110110 step 22 110110110110110110110110110110 step 23 110110110110110011110110110110 step 24 110110110110110001110110110110 step 25 110110110110110101110110110110 step 26 110110110110110110110110110110 step 27 110110110110110110011110110110 step 28 110110110110110110001110110110 step 29 110110110110110110101110110110 step 30 110110110110110110110110110110 step 31 110110110110110110110011110110 step 32 110110110110110110110001110110 step 33 110110110110110110110101110110 step 34 110110110110110110110110110110 step 35 110110110110110110110110011110 step 36 110110110110110110110110001110 step 37 110110110110110110110110101110 step 38 110110110110110110110110110110 step 39 110110110110110110110110110011 step 40 110110110110110110110110110001 step 41 110110110110110110110110110101 step 42 110110110110110110110110110110 step 43 001001001001001001001001001001 step 44 011001001001001001001001001001 step 45 110001001001001001001001001001 step 46 101001001001001001001001001001 step 47 001001001001001001001001001001 step 48 001011001001001001001001001001 step 49 001110001001001001001001001001 step 50 001101001001001001001001001001 step 51 001001001001001001001001001001 step 52 001001011001001001001001001001 step 53 001001110001001001001001001001 step 54 001001101001001001001001001001 step 55 001001001001001001001001001001 step 56 001001001011001001001001001001 step 57 001001001110001001001001001001 step 58 001001001101001001001001001001 step 59 001001001001001001001001001001 step 60 001001001001011001001001001001 step 61 001001001001110001001001001001 step 62 001001001001101001001001001001 step 63 001001001001001001001001001001 step 64 001001001001001011001001001001 step 65 001001001001001110001001001001 step 66 001001001001001101001001001001 step 67 001001001001001001001001001001 step 68 001001001001001001011001001001 step 69 001001001001001001110001001001 step 70 001001001001001001101001001001 step 71 001001001001001001001001001001 step 72 001001001001001001001011001001 step 73 001001001001001001001110001001 step 74 001001001001001001001101001001 step 75 001001001001001001001001001001 step 76 001001001001001001001001011001 step 77 001001001001001001001001110001 step 78 001001001001001001001001101001 step 79 001001001001001001001001001001 step 80 001001001001001001001001001011 step 81 001001001001001001001001001110 step 82 001001001001001001001001001101 step 83 001001001001001001001001001001 test 1: pass SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFDEFHJKHJKLMNLMNPRSPRSTUV SIDE 111111222111222111222111222222 DIRECTION IIOIIOIIOIIOIIOIIOIIOIIOIIOIIO this fail all fails was hi 111111111111111111111111111111 rising ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ falling vvvvvvvvvvvvvvvvvvvvvvvvvvvvvv was lo 000000000000000000000000000000 total fails 0, total passes 1 step 1 001001001001001001001001001001 step 2 110110110110110110110110110110 step 3 011110110110110110110110110110 step 4 001110110110110110110110110110 step 5 101110110110110110110110110110 step 6 110110110110110110110110110110 step 7 110011110110110110110110110110 step 8 110001110110110110110110110110 step 9 110101110110110110110110110110 step 10 110110110110110110110110110110 step 11 110110011110110110110110110110 step 12 110110001110110110110110110110 step 13 110110101110110110110110110110 step 14 110110110110110110110110110110 step 15 110110110011110110110110110110 step 16 110110110001110110110110110110 step 17 110110110101110110110110110110 step 18 110110110110110110110110110110 step 19 110110110110011110110110110110 step 20 110110110110001110110110110110 step 21 110110110110101110110110110110 step 22 110110110110110110110110110110 step 23 110110110110110011110110110110 step 24 110110110110110001110110110110 step 25 110110110110110101110110110110 step 26 110110110110110110110110110110 step 27 110110110110110110011110110110 step 28 110110110110110110001110110110 step 29 110110110110110110101110110110 step 30 110110110110110110110110110110 step 31 110110110110110110110011110110 step 32 110110110110110110110001110110 step 33 110110110110110110110101110110 step 34 110110110110110110110110110110 step 35 110110110110110110110110011110 step 36 110110110110110110110110001110 step 37 110110110110110110110110101110 step 38 110110110110110110110110110110 step 39 110110110110110110110110110011 step 40 110110110110110110110110110001 step 41 110110110110110110110110110101 step 42 110110110110110110110110110110 step 43 001001001001001001001001001001 step 44 011001001001001001001001001001 step 45 110001001001001001001001001001 step 46 101001001001001001001001001001 step 47 001001001001001001001001001001 step 48 001011001001001001001001001001 step 49 001110001001001001001001001001 step 50 001101001001001001001001001001 step 51 001001001001001001001001001001 step 52 001001011001001001001001001001 step 53 001001110001001001001001001001 step 54 001001101001001001001001001001 step 55 001001001001001001001001001001 step 56 001001001011001001001001001001 step 57 001001001110001001001001001001 step 58 001001001101001001001001001001 step 59 001001001001001001001001001001 step 60 001001001001011001001001001001 step 61 001001001001110001001001001001 step 62 001001001001101001001001001001 step 63 001001001001001001001001001001 step 64 001001001001001011001001001001 step 65 001001001001001110001001001001 step 66 001001001001001101001001001001 step 67 001001001001001001001001001001 step 68 001001001001001001011001001001 step 69 001001001001001001110001001001 step 70 001001001001001001101001001001 step 71 001001001001001001001001001001 step 72 001001001001001001001011001001 step 73 001001001001001001001110001001 step 74 001001001001001001001101001001 step 75 001001001001001001001001001001 step 76 001001001001001001001001011001 step 77 001001001001001001001001110001 step 78 001001001001001001001001101001 step 79 001001001001001001001001001001 step 80 001001001001001001001001001011 step 81 001001001001001001001001001110 step 82 001001001001001001001001001101 step 83 001001001001001001001001001001 test 2: pass SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFDEFHJKHJKLMNLMNPRSPRSTUV SIDE 111111222111222111222111222222 DIRECTION IIOIIOIIOIIOIIOIIOIIOIIOIIOIIO this fail all fails was hi 111111111111111111111111111111 rising ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ falling vvvvvvvvvvvvvvvvvvvvvvvvvvvvvv was lo 000000000000000000000000000000 total fails 0, total passes 2 step 1 001001001001001001001001001001 step 2 110110110110110110110110110110 step 3 011110110110110110110110110110 step 4 001110110110110110110110110110 step 5 101110110110110110110110110110 step 6 110110110110110110110110110110 step 7 110011110110110110110110110110 step 8 110001110110110110110110110110 step 9 110101110110110110110110110110 step 10 110110110110110110110110110110 step 11 110110011110110110110110110110 step 12 110110001110110110110110110110 step 13 110110101110110110110110110110 step 14 110110110110110110110110110110 step 15 110110110011110110110110110110 step 16 110110110001110110110110110110 step 17 110110110101110110110110110110 step 18 110110110110110110110110110110 step 19 110110110110011110110110110110 step 20 110110110110001110110110110110 step 21 110110110110101110110110110110 step 22 110110110110110110110110110110 step 23 110110110110110011110110110110 step 24 110110110110110001110110110110 step 25 110110110110110101110110110110 step 26 110110110110110110110110110110 step 27 110110110110110110011110110110 step 28 110110110110110110001110110110 step 29 110110110110110110101110110110 step 30 110110110110110110110110110110 step 31 110110110110110110110011110110 step 32 110110110110110110110001110110 step 33 110110110110110110110101110110 step 34 110110110110110110110110110110 step 35 110110110110110110110110011110 step 36 110110110110110110110110001110 step 37 110110110110110110110110101110 step 38 110110110110110110110110110110 step 39 110110110110110110110110110011 step 40 110110110110110110110110110001 step 41 110110110110110110110110110101 step 42 110110110110110110110110110110 step 43 001001001001001001001001001001 step 44 011001001001001001001001001001 step 45 110001001001001001001001001001 step 46 101001001001001001001001001001 step 47 001001001001001001001001001001 step 48 001011001001001001001001001001 step 49 001110001001001001001001001001 step 50 001101001001001001001001001001 step 51 001001001001001001001001001001 step 52 001001011001001001001001001001 step 53 001001110001001001001001001001 step 54 001001101001001001001001001001 step 55 001001001001001001001001001001 step 56 001001001011001001001001001001 step 57 001001001110001001001001001001 step 58 001001001101001001001001001001 step 59 001001001001001001001001001001 step 60 001001001001011001001001001001 step 61 001001001001110001001001001001 step 62 001001001001101001001001001001 step 63 001001001001001001001001001001 step 64 001001001001001011001001001001 step 65 001001001001001110001001001001 step 66 001001001001001101001001001001 step 67 001001001001001001001001001001 step 68 001001001001001001011001001001 step 69 001001001001001001110001001001 step 70 001001001001001001101001001001 step 71 001001001001001001001001001001 step 72 001001001001001001001011001001 step 73 001001001001001001001110001001 step 74 001001001001001001001101001001 step 75 001001001001001001001001001001 step 76 001001001001001001001001011001 step 77 001001001001001001001001110001 step 78 001001001001001001001001101001 step 79 001001001001001001001001001001 step 80 001001001001001001001001001011 step 81 001001001001001001001001001110 step 82 001001001001001001001001001101 step 83 001001001001001001001001001001 test 3: pass SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFDEFHJKHJKLMNLMNPRSPRSTUV SIDE 111111222111222111222111222222 DIRECTION IIOIIOIIOIIOIIOIIOIIOIIOIIOIIO this fail all fails was hi 111111111111111111111111111111 rising ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ falling vvvvvvvvvvvvvvvvvvvvvvvvvvvvvv was lo 000000000000000000000000000000 total fails 0, total passes 3 step 1 001001001001001001001001001001 step 2 110110110110110110110110110110 step 3 011110110110110110110110110110 step 4 001110110110110110110110110110 step 5 101110110110110110110110110110 step 6 110110110110110110110110110110 step 7 110011110110110110110110110110 step 8 110001110110110110110110110110 step 9 110101110110110110110110110110 step 10 110110110110110110110110110110 step 11 110110011110110110110110110110 step 12 110110001110110110110110110110 step 13 110110101110110110110110110110 step 14 110110110110110110110110110110 step 15 110110110011110110110110110110 step 16 110110110001110110110110110110 step 17 110110110101110110110110110110 step 18 110110110110110110110110110110 step 19 110110110110011110110110110110 step 20 110110110110001110110110110110 step 21 110110110110101110110110110110 step 22 110110110110110110110110110110 step 23 110110110110110011110110110110 step 24 110110110110110001110110110110 step 25 110110110110110101110110110110 step 26 110110110110110110110110110110 step 27 110110110110110110011110110110 step 28 110110110110110110001110110110 step 29 110110110110110110101110110110 step 30 110110110110110110110110110110 step 31 110110110110110110110011110110 step 32 110110110110110110110001110110 step 33 110110110110110110110101110110 step 34 110110110110110110110110110110 step 35 110110110110110110110110011110 step 36 110110110110110110110110001110 step 37 110110110110110110110110101110 step 38 110110110110110110110110110110 step 39 110110110110110110110110110011 step 40 110110110110110110110110110001 step 41 110110110110110110110110110101 step 42 110110110110110110110110110110 step 43 001001001001001001001001001001 step 44 011001001001001001001001001001 step 45 110001001001001001001001001001 step 46 101001001001001001001001001001 step 47 001001001001001001001001001001 step 48 001011001001001001001001001001 step 49 001110001001001001001001001001 step 50 001101001001001001001001001001 step 51 001001001001001001001001001001 step 52 001001011001001001001001001001 step 53 001001110001001001001001001001 step 54 001001101001001001001001001001 step 55 001001001001001001001001001001 step 56 001001001011001001001001001001 step 57 001001001110001001001001001001 step 58 001001001101001001001001001001 step 59 001001001001001001001001001001 step 60 001001001001011001001001001001 step 61 001001001001110001001001001001 step 62 001001001001101001001001001001 step 63 001001001001001001001001001001 step 64 001001001001001011001001001001 step 65 001001001001001110001001001001 step 66 001001001001001101001001001001 step 67 001001001001001001001001001001 step 68 001001001001001001011001001001 step 69 001001001001001001110001001001 step 70 001001001001001001101001001001 step 71 001001001001001001001001001001 step 72 001001001001001001001011001001 step 73 001001001001001001001110001001 step 74 001001001001001001001101001001 step 75 001001001001001001001001001001 step 76 001001001001001001001001011001 step 77 001001001001001001001001110001 step 78 001001001001001001001001101001 step 79 001001001001001001001001001001 step 80 001001001001001001001001001011 step 81 001001001001001001001001001110 step 82 001001001001001001001001001101 step 83 001001001001001001001001001001 test 4: pass SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFDEFHJKHJKLMNLMNPRSPRSTUV SIDE 111111222111222111222111222222 DIRECTION IIOIIOIIOIIOIIOIIOIIOIIOIIOIIO this fail all fails was hi 111111111111111111111111111111 rising ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ falling vvvvvvvvvvvvvvvvvvvvvvvvvvvvvv was lo 000000000000000000000000000000 total fails 0, total passes 4 step 1 001001001001001001001001001001 step 2 110110110110110110110110110110 step 3 011110110110110110110110110110 step 4 001110110110110110110110110110 step 5 101110110110110110110110110110 step 6 110110110110110110110110110110 step 7 110011110110110110110110110110 step 8 110001110110110110110110110110 step 9 110101110110110110110110110110 step 10 110110110110110110110110110110 step 11 110110011110110110110110110110 step 12 110110001110110110110110110110 step 13 110110101110110110110110110110 step 14 110110110110110110110110110110 step 15 110110110011110110110110110110 step 16 110110110001110110110110110110 step 17 110110110101110110110110110110 step 18 110110110110110110110110110110 step 19 110110110110011110110110110110 step 20 110110110110001110110110110110 step 21 110110110110101110110110110110 step 22 110110110110110110110110110110 step 23 110110110110110011110110110110 step 24 110110110110110001110110110110 step 25 110110110110110101110110110110 step 26 110110110110110110110110110110 step 27 110110110110110110011110110110 step 28 110110110110110110001110110110 step 29 110110110110110110101110110110 step 30 110110110110110110110110110110 step 31 110110110110110110110011110110 step 32 110110110110110110110001110110 step 33 110110110110110110110101110110 step 34 110110110110110110110110110110 step 35 110110110110110110110110011110 step 36 110110110110110110110110001110 step 37 110110110110110110110110101110 step 38 110110110110110110110110110110 step 39 110110110110110110110110110011 step 40 110110110110110110110110110001 step 41 110110110110110110110110110101 step 42 110110110110110110110110110110 step 43 001001001001001001001001001001 step 44 011001001001001001001001001001 step 45 110001001001001001001001001001 step 46 101001001001001001001001001001 step 47 001001001001001001001001001001 step 48 001011001001001001001001001001 step 49 001110001001001001001001001001 step 50 001101001001001001001001001001 step 51 001001001001001001001001001001 step 52 001001011001001001001001001001 step 53 001001110001001001001001001001 step 54 001001101001001001001001001001 step 55 001001001001001001001001001001 step 56 001001001011001001001001001001 step 57 001001001110001001001001001001 step 58 001001001101001001001001001001 step 59 001001001001001001001001001001 step 60 001001001001011001001001001001 step 61 001001001001110001001001001001 step 62 001001001001101001001001001001 step 63 001001001001001001001001001001 step 64 001001001001001011001001001001 step 65 001001001001001110001001001001 step 66 001001001001001101001001001001 step 67 001001001001001001001001001001 step 68 001001001001001001011001001001 step 69 001001001001001001110001001001 step 70 001001001001001001101001001001 step 71 001001001001001001001001001001 step 72 001001001001001001001011001001 step 73 001001001001001001001110001001 step 74 001001001001001001001101001001 step 75 001001001001001001001001001001 step 76 001001001001001001001001011001 step 77 001001001001001001001001110001 step 78 001001001001001001001001101001 step 79 001001001001001001001001001001 step 80 001001001001001001001001001011 step 81 001001001001001001001001001110 step 82 001001001001001001001001001101 step 83 001001001001001001001001001001 test 5: pass SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFDEFHJKHJKLMNLMNPRSPRSTUV SIDE 111111222111222111222111222222 DIRECTION IIOIIOIIOIIOIIOIIOIIOIIOIIOIIO this fail all fails was hi 111111111111111111111111111111 rising ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ falling vvvvvvvvvvvvvvvvvvvvvvvvvvvvvv was lo 000000000000000000000000000000 total fails 0, total passes 5 step 1 001001001001001001001001001001 step 2 110110110110110110110110110110 step 3 011110110110110110110110110110 step 4 001110110110110110110110110110 step 5 101110110110110110110110110110 step 6 110110110110110110110110110110 step 7 110011110110110110110110110110 step 8 110001110110110110110110110110 step 9 110101110110110110110110110110 step 10 110110110110110110110110110110 step 11 110110011110110110110110110110 step 12 110110001110110110110110110110 step 13 110110101110110110110110110110 step 14 110110110110110110110110110110 step 15 110110110011110110110110110110 step 16 110110110001110110110110110110 step 17 110110110101110110110110110110 step 18 110110110110110110110110110110 step 19 110110110110011110110110110110 step 20 110110110110001110110110110110 step 21 110110110110101110110110110110 step 22 110110110110110110110110110110 step 23 110110110110110011110110110110 step 24 110110110110110001110110110110 step 25 110110110110110101110110110110 step 26 110110110110110110110110110110 step 27 110110110110110110011110110110 step 28 110110110110110110001110110110 step 29 110110110110110110101110110110 step 30 110110110110110110110110110110 step 31 110110110110110110110011110110 step 32 110110110110110110110001110110 step 33 110110110110110110110101110110 step 34 110110110110110110110110110110 step 35 110110110110110110110110011110 step 36 110110110110110110110110001110 step 37 110110110110110110110110101110 step 38 110110110110110110110110110110 step 39 110110110110110110110110110011 step 40 110110110110110110110110110001 step 41 110110110110110110110110110101 step 42 110110110110110110110110110110 step 43 001001001001001001001001001001 step 44 011001001001001001001001001001 step 45 110001001001001001001001001001 step 46 101001001001001001001001001001 step 47 001001001001001001001001001001 step 48 001011001001001001001001001001 step 49 001110001001001001001001001001 step 50 001101001001001001001001001001 step 51 001001001001001001001001001001 step 52 001001011001001001001001001001 step 53 001001110001001001001001001001 step 54 001001101001001001001001001001 step 55 001001001001001001001001001001 step 56 001001001011001001001001001001 step 57 001001001110001001001001001001 step 58 001001001101001001001001001001 step 59 001001001001001001001001001001 step 60 001001001001011001001001001001 step 61 001001001001110001001001001001 step 62 001001001001101001001001001001 step 63 001001001001001001001001001001 step 64 001001001001001011001001001001 step 65 001001001001001110001001001001 step 66 001001001001001101001001001001 step 67 001001001001001001001001001001 step 68 001001001001001001011001001001 step 69 001001001001001001110001001001 step 70 001001001001001001101001001001 step 71 001001001001001001001001001001 step 72 001001001001001001001011001001 step 73 001001001001001001001110001001 step 74 001001001001001001001101001001 step 75 001001001001001001001001001001 step 76 001001001001001001001001011001 step 77 001001001001001001001001110001 step 78 001001001001001001001001101001 step 79 001001001001001001001001001001 step 80 001001001001001001001001001011 step 81 001001001001001001001001001110 step 82 001001001001001001001001001101 step 83 001001001001001001001001001001 test 6: pass SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFDEFHJKHJKLMNLMNPRSPRSTUV SIDE 111111222111222111222111222222 DIRECTION IIOIIOIIOIIOIIOIIOIIOIIOIIOIIO this fail all fails was hi 111111111111111111111111111111 rising ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ falling vvvvvvvvvvvvvvvvvvvvvvvvvvvvvv was lo 000000000000000000000000000000 total fails 0, total passes 6 step 1 001001001001001001001001001001 step 2 110110110110110110110110110110 step 3 011110110110110110110110110110 step 4 001110110110110110110110110110 step 5 101110110110110110110110110110 step 6 110110110110110110110110110110 step 7 110011110110110110110110110110 step 8 110001110110110110110110110110 step 9 110101110110110110110110110110 step 10 110110110110110110110110110110 step 11 110110011110110110110110110110 step 12 110110001110110110110110110110 step 13 110110101110110110110110110110 step 14 110110110110110110110110110110 step 15 110110110011110110110110110110 step 16 110110110001110110110110110110 step 17 110110110101110110110110110110 step 18 110110110110110110110110110110 step 19 110110110110011110110110110110 step 20 110110110110001110110110110110 step 21 110110110110101110110110110110 step 22 110110110110110110110110110110 step 23 110110110110110011110110110110 step 24 110110110110110001110110110110 step 25 110110110110110101110110110110 step 26 110110110110110110110110110110 step 27 110110110110110110011110110110 step 28 110110110110110110001110110110 step 29 110110110110110110101110110110 step 30 110110110110110110110110110110 step 31 110110110110110110110011110110 step 32 110110110110110110110001110110 step 33 110110110110110110110101110110 step 34 110110110110110110110110110110 step 35 110110110110110110110110011110 step 36 110110110110110110110110001110 step 37 110110110110110110110110101110 step 38 110110110110110110110110110110 step 39 110110110110110110110110110011 step 40 110110110110110110110110110001 step 41 110110110110110110110110110101 step 42 110110110110110110110110110110 step 43 001001001001001001001001001001 step 44 011001001001001001001001001001 step 45 110001001001001001001001001001 step 46 101001001001001001001001001001 step 47 001001001001001001001001001001 step 48 001011001001001001001001001001 step 49 001110001001001001001001001001 step 50 001101001001001001001001001001 step 51 001001001001001001001001001001 step 52 001001011001001001001001001001 step 53 001001110001001001001001001001 step 54 001001101001001001001001001001 step 55 001001001001001001001001001001 step 56 001001001011001001001001001001 step 57 001001001110001001001001001001 step 58 001001001101001001001001001001 step 59 001001001001001001001001001001 step 60 001001001001011001001001001001 step 61 001001001001110001001001001001 step 62 001001001001101001001001001001 step 63 001001001001001001001001001001 step 64 001001001001001011001001001001 step 65 001001001001001110001001001001 step 66 001001001001001101001001001001 step 67 001001001001001001001001001001 step 68 001001001001001001011001001001 step 69 001001001001001001110001001001 step 70 001001001001001001101001001001 step 71 001001001001001001001001001001 step 72 001001001001001001001011001001 step 73 001001001001001001001110001001 step 74 001001001001001001001101001001 step 75 001001001001001001001001001001 step 76 001001001001001001001001011001 step 77 001001001001001001001001110001 step 78 001001001001001001001001101001 step 79 001001001001001001001001001001 step 80 001001001001001001001001001011 step 81 001001001001001001001001001110 step 82 001001001001001001001001001101 step 83 001001001001001001001001001001 test 7: pass SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFDEFHJKHJKLMNLMNPRSPRSTUV SIDE 111111222111222111222111222222 DIRECTION IIOIIOIIOIIOIIOIIOIIOIIOIIOIIO this fail all fails was hi 111111111111111111111111111111 rising ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ falling vvvvvvvvvvvvvvvvvvvvvvvvvvvvvv was lo 000000000000000000000000000000 total fails 0, total passes 7 step 1 001001001001001001001001001001 step 2 110110110110110110110110110110 step 3 011110110110110110110110110110 step 4 001110110110110110110110110110 step 5 101110110110110110110110110110 step 6 110110110110110110110110110110 step 7 110011110110110110110110110110 step 8 110001110110110110110110110110 step 9 110101110110110110110110110110 step 10 110110110110110110110110110110 step 11 110110011110110110110110110110 step 12 110110001110110110110110110110 step 13 110110101110110110110110110110 step 14 110110110110110110110110110110 step 15 110110110011110110110110110110 step 16 110110110001110110110110110110 step 17 110110110101110110110110110110 step 18 110110110110110110110110110110 step 19 110110110110011110110110110110 step 20 110110110110001110110110110110 step 21 110110110110101110110110110110 step 22 110110110110110110110110110110 step 23 110110110110110011110110110110 step 24 110110110110110001110110110110 step 25 110110110110110101110110110110 step 26 110110110110110110110110110110 step 27 110110110110110110011110110110 step 28 110110110110110110001110110110 step 29 110110110110110110101110110110 step 30 110110110110110110110110110110 step 31 110110110110110110110011110110 step 32 110110110110110110110001110110 step 33 110110110110110110110101110110 step 34 110110110110110110110110110110 step 35 110110110110110110110110011110 step 36 110110110110110110110110001110 step 37 110110110110110110110110101110 step 38 110110110110110110110110110110 step 39 110110110110110110110110110011 step 40 110110110110110110110110110001 step 41 110110110110110110110110110101 step 42 110110110110110110110110110110 step 43 001001001001001001001001001001 step 44 011001001001001001001001001001 step 45 110001001001001001001001001001 step 46 101001001001001001001001001001 step 47 001001001001001001001001001001 step 48 001011001001001001001001001001 step 49 001110001001001001001001001001 step 50 001101001001001001001001001001 step 51 001001001001001001001001001001 step 52 001001011001001001001001001001 step 53 001001110001001001001001001001 step 54 001001101001001001001001001001 step 55 001001001001001001001001001001 step 56 001001001011001001001001001001 step 57 001001001110001001001001001001 step 58 001001001101001001001001001001 step 59 001001001001001001001001001001 step 60 001001001001011001001001001001 step 61 001001001001110001001001001001 step 62 001001001001101001001001001001 step 63 001001001001001001001001001001 step 64 001001001001001011001001001001 step 65 001001001001001110001001001001 step 66 001001001001001101001001001001 step 67 001001001001001001001001001001 step 68 001001001001001001011001001001 step 69 001001001001001001110001001001 step 70 001001001001001001101001001001 step 71 001001001001001001001001001001 step 72 001001001001001001001011001001 step 73 001001001001001001001110001001 step 74 001001001001001001001101001001 step 75 001001001001001001001001001001 step 76 001001001001001001001001011001 step 77 001001001001001001001001110001 step 78 001001001001001001001001101001 step 79 001001001001001001001001001001 step 80 001001001001001001001001001011 step 81 001001001001001001001001001110 step 82 001001001001001001001001001101 step 83 001001001001001001001001001001 test 8: pass SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFDEFHJKHJKLMNLMNPRSPRSTUV SIDE 111111222111222111222111222222 DIRECTION IIOIIOIIOIIOIIOIIOIIOIIOIIOIIO this fail all fails was hi 111111111111111111111111111111 rising ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ falling vvvvvvvvvvvvvvvvvvvvvvvvvvvvvv was lo 000000000000000000000000000000 total fails 0, total passes 8 step 1 001001001001001001001001001001 step 2 110110110110110110110110110110 step 3 011110110110110110110110110110 step 4 001110110110110110110110110110 step 5 101110110110110110110110110110 step 6 110110110110110110110110110110 step 7 110011110110110110110110110110 step 8 110001110110110110110110110110 step 9 110101110110110110110110110110 step 10 110110110110110110110110110110 step 11 110110011110110110110110110110 step 12 110110001110110110110110110110 step 13 110110101110110110110110110110 step 14 110110110110110110110110110110 step 15 110110110011110110110110110110 step 16 110110110001110110110110110110 step 17 110110110101110110110110110110 step 18 110110110110110110110110110110 step 19 110110110110011110110110110110 step 20 110110110110001110110110110110 step 21 110110110110101110110110110110 step 22 110110110110110110110110110110 step 23 110110110110110011110110110110 step 24 110110110110110001110110110110 step 25 110110110110110101110110110110 step 26 110110110110110110110110110110 step 27 110110110110110110011110110110 step 28 110110110110110110001110110110 step 29 110110110110110110101110110110 step 30 110110110110110110110110110110 step 31 110110110110110110110011110110 step 32 110110110110110110110001110110 step 33 110110110110110110110101110110 step 34 110110110110110110110110110110 step 35 110110110110110110110110011110 step 36 110110110110110110110110001110 step 37 110110110110110110110110101110 step 38 110110110110110110110110110110 step 39 110110110110110110110110110011 step 40 110110110110110110110110110001 step 41 110110110110110110110110110101 step 42 110110110110110110110110110110 step 43 001001001001001001001001001001 step 44 011001001001001001001001001001 step 45 110001001001001001001001001001 step 46 101001001001001001001001001001 step 47 001001001001001001001001001001 step 48 001011001001001001001001001001 step 49 001110001001001001001001001001 step 50 001101001001001001001001001001 step 51 001001001001001001001001001001 step 52 001001011001001001001001001001 step 53 001001110001001001001001001001 step 54 001001101001001001001001001001 step 55 001001001001001001001001001001 step 56 001001001011001001001001001001 step 57 001001001110001001001001001001 step 58 001001001101001001001001001001 step 59 001001001001001001001001001001 step 60 001001001001011001001001001001 step 61 001001001001110001001001001001 step 62 001001001001101001001001001001 step 63 001001001001001001001001001001 step 64 001001001001001011001001001001 step 65 001001001001001110001001001001 step 66 001001001001001101001001001001 step 67 001001001001001001001001001001 step 68 001001001001001001011001001001 step 69 001001001001001001110001001001 step 70 001001001001001001101001001001 step 71 001001001001001001001001001001 step 72 001001001001001001001011001001 step 73 001001001001001001001110001001 step 74 001001001001001001001101001001 step 75 001001001001001001001001001001 step 76 001001001001001001001001011001 step 77 001001001001001001001001110001 step 78 001001001001001001001001101001 step 79 001001001001001001001001001001 step 80 001001001001001001001001001011 step 81 001001001001001001001001001110 step 82 001001001001001001001001001101 step 83 001001001001001001001001001001 test 9: pass SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFDEFHJKHJKLMNLMNPRSPRSTUV SIDE 111111222111222111222111222222 DIRECTION IIOIIOIIOIIOIIOIIOIIOIIOIIOIIO this fail all fails was hi 111111111111111111111111111111 rising ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ falling vvvvvvvvvvvvvvvvvvvvvvvvvvvvvv was lo 000000000000000000000000000000 total fails 0, total passes 9 step 1 001001001001001001001001001001 step 2 110110110110110110110110110110 step 3 011110110110110110110110110110 step 4 001110110110110110110110110110 step 5 101110110110110110110110110110 step 6 110110110110110110110110110110 step 7 110011110110110110110110110110 step 8 110001110110110110110110110110 step 9 110101110110110110110110110110 step 10 110110110110110110110110110110 step 11 110110011110110110110110110110 step 12 110110001110110110110110110110 step 13 110110101110110110110110110110 step 14 110110110110110110110110110110 step 15 110110110011110110110110110110 step 16 110110110001110110110110110110 step 17 110110110101110110110110110110 step 18 110110110110110110110110110110 step 19 110110110110011110110110110110 step 20 110110110110001110110110110110 step 21 110110110110101110110110110110 step 22 110110110110110110110110110110 step 23 110110110110110011110110110110 step 24 110110110110110001110110110110 step 25 110110110110110101110110110110 step 26 110110110110110110110110110110 step 27 110110110110110110011110110110 step 28 110110110110110110001110110110 step 29 110110110110110110101110110110 step 30 110110110110110110110110110110 step 31 110110110110110110110011110110 step 32 110110110110110110110001110110 step 33 110110110110110110110101110110 step 34 110110110110110110110110110110 step 35 110110110110110110110110011110 step 36 110110110110110110110110001110 step 37 110110110110110110110110101110 step 38 110110110110110110110110110110 step 39 110110110110110110110110110011 step 40 110110110110110110110110110001 step 41 110110110110110110110110110101 step 42 110110110110110110110110110110 step 43 001001001001001001001001001001 step 44 011001001001001001001001001001 step 45 110001001001001001001001001001 step 46 101001001001001001001001001001 step 47 001001001001001001001001001001 step 48 001011001001001001001001001001 step 49 001110001001001001001001001001 step 50 001101001001001001001001001001 step 51 001001001001001001001001001001 step 52 001001011001001001001001001001 step 53 001001110001001001001001001001 step 54 001001101001001001001001001001 step 55 001001001001001001001001001001 step 56 001001001011001001001001001001 step 57 001001001110001001001001001001 step 58 001001001101001001001001001001 step 59 001001001001001001001001001001 step 60 001001001001011001001001001001 step 61 001001001001110001001001001001 step 62 001001001001101001001001001001 step 63 001001001001001001001001001001 step 64 001001001001001011001001001001 step 65 001001001001001110001001001001 step 66 001001001001001101001001001001 step 67 001001001001001001001001001001 step 68 001001001001001001011001001001 step 69 001001001001001001110001001001 step 70 001001001001001001101001001001 step 71 001001001001001001001001001001 step 72 001001001001001001001011001001 step 73 001001001001001001001110001001 step 74 001001001001001001001101001001 step 75 001001001001001001001001001001 step 76 001001001001001001001001011001 step 77 001001001001001001001001110001 step 78 001001001001001001001001101001 step 79 001001001001001001001001001001 step 80 001001001001001001001001001011 step 81 001001001001001001001001001110 step 82 001001001001001001001001001101 step 83 001001001001001001001001001001 test 10: pass SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFDEFHJKHJKLMNLMNPRSPRSTUV SIDE 111111222111222111222111222222 DIRECTION IIOIIOIIOIIOIIOIIOIIOIIOIIOIIO this fail all fails was hi 111111111111111111111111111111 rising ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ falling vvvvvvvvvvvvvvvvvvvvvvvvvvvvvv was lo 000000000000000000000000000000 total fails 0, total passes 10 step 1 001001001001001001001001001001 step 2 110110110110110110110110110110 step 3 011110110110110110110110110110 step 4 001110110110110110110110110110 step 5 101110110110110110110110110110 step 6 110110110110110110110110110110 step 7 110011110110110110110110110110 step 8 110001110110110110110110110110 step 9 110101110110110110110110110110 step 10 110110110110110110110110110110 step 11 110110011110110110110110110110 step 12 110110001110110110110110110110 step 13 110110101110110110110110110110 step 14 110110110110110110110110110110 step 15 110110110011110110110110110110 step 16 110110110001110110110110110110 step 17 110110110101110110110110110110 step 18 110110110110110110110110110110 step 19 110110110110011110110110110110 step 20 110110110110001110110110110110 step 21 110110110110101110110110110110 step 22 110110110110110110110110110110 step 23 110110110110110011110110110110 step 24 110110110110110001110110110110 step 25 110110110110110101110110110110 step 26 110110110110110110110110110110 step 27 110110110110110110011110110110 step 28 110110110110110110001110110110 step 29 110110110110110110101110110110 step 30 110110110110110110110110110110 step 31 110110110110110110110011110110 step 32 110110110110110110110001110110 step 33 110110110110110110110101110110 step 34 110110110110110110110110110110 step 35 110110110110110110110110011110 step 36 110110110110110110110110001110 step 37 110110110110110110110110101110 step 38 110110110110110110110110110110 step 39 110110110110110110110110110011 step 40 110110110110110110110110110001 step 41 110110110110110110110110110101 step 42 110110110110110110110110110110 step 43 001001001001001001001001001001 step 44 011001001001001001001001001001 step 45 110001001001001001001001001001 step 46 101001001001001001001001001001 step 47 001001001001001001001001001001 step 48 001011001001001001001001001001 step 49 001110001001001001001001001001 step 50 001101001001001001001001001001 step 51 001001001001001001001001001001 step 52 001001011001001001001001001001 step 53 001001110001001001001001001001 step 54 001001101001001001001001001001 step 55 001001001001001001001001001001 step 56 001001001011001001001001001001 step 57 001001001110001001001001001001 step 58 001001001101001001001001001001 step 59 001001001001001001001001001001 step 60 001001001001011001001001001001 step 61 001001001001110001001001001001 step 62 001001001001101001001001001001 step 63 001001001001001001001001001001 step 64 001001001001001011001001001001 step 65 001001001001001110001001001001 step 66 001001001001001101001001001001 step 67 001001001001001001001001001001 step 68 001001001001001001011001001001 step 69 001001001001001001110001001001 step 70 001001001001001001101001001001 step 71 001001001001001001001001001001 step 72 001001001001001001001011001001 step 73 001001001001001001001110001001 step 74 001001001001001001001101001001 step 75 001001001001001001001001001001 step 76 001001001001001001001001011001 step 77 001001001001001001001001110001 step 78 001001001001001001001001101001 step 79 001001001001001001001001001001 step 80 001001001001001001001001001011 step 81 001001001001001001001001001110 step 82 001001001001001001001001001101 step 83 001001001001001001001001001001 test 11: pass SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFDEFHJKHJKLMNLMNPRSPRSTUV SIDE 111111222111222111222111222222 DIRECTION IIOIIOIIOIIOIIOIIOIIOIIOIIOIIO this fail all fails was hi 111111111111111111111111111111 rising ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ falling vvvvvvvvvvvvvvvvvvvvvvvvvvvvvv was lo 000000000000000000000000000000 total fails 0, total passes 11 step 1 001001001001001001001001001001 step 2 110110110110110110110110110110 step 3 011110110110110110110110110110 step 4 001110110110110110110110110110 step 5 101110110110110110110110110110 step 6 110110110110110110110110110110 step 7 110011110110110110110110110110 step 8 110001110110110110110110110110 step 9 110101110110110110110110110110 step 10 110110110110110110110110110110 step 11 110110011110110110110110110110 step 12 110110001110110110110110110110 step 13 110110101110110110110110110110 step 14 110110110110110110110110110110 step 15 110110110011110110110110110110 step 16 110110110001110110110110110110 step 17 110110110101110110110110110110 step 18 110110110110110110110110110110 step 19 110110110110011110110110110110 step 20 110110110110001110110110110110 step 21 110110110110101110110110110110 step 22 110110110110110110110110110110 step 23 110110110110110011110110110110 step 24 110110110110110001110110110110 step 25 110110110110110101110110110110 step 26 110110110110110110110110110110 step 27 110110110110110110011110110110 step 28 110110110110110110001110110110 step 29 110110110110110110101110110110 step 30 110110110110110110110110110110 step 31 110110110110110110110011110110 step 32 110110110110110110110001110110 step 33 110110110110110110110101110110 step 34 110110110110110110110110110110 step 35 110110110110110110110110011110 step 36 110110110110110110110110001110 step 37 110110110110110110110110101110 step 38 110110110110110110110110110110 step 39 110110110110110110110110110011 step 40 110110110110110110110110110001 step 41 110110110110110110110110110101 step 42 110110110110110110110110110110 step 43 001001001001001001001001001001 step 44 011001001001001001001001001001 step 45 110001001001001001001001001001 step 46 101001001001001001001001001001 step 47 001001001001001001001001001001 step 48 001011001001001001001001001001 step 49 001110001001001001001001001001 step 50 001101001001001001001001001001 step 51 001001001001001001001001001001 step 52 001001011001001001001001001001 step 53 001001110001001001001001001001 step 54 001001101001001001001001001001 step 55 001001001001001001001001001001 step 56 001001001011001001001001001001 step 57 001001001110001001001001001001 step 58 001001001101001001001001001001 step 59 001001001001001001001001001001 step 60 001001001001011001001001001001 step 61 001001001001110001001001001001 step 62 001001001001101001001001001001 step 63 001001001001001001001001001001 step 64 001001001001001011001001001001 step 65 001001001001001110001001001001 step 66 001001001001001101001001001001 step 67 001001001001001001001001001001 step 68 001001001001001001011001001001 step 69 001001001001001001110001001001 step 70 001001001001001001101001001001 step 71 001001001001001001001001001001 step 72 001001001001001001001011001001 step 73 001001001001001001001110001001 step 74 001001001001001001001101001001 step 75 001001001001001001001001001001 step 76 001001001001001001001001011001 step 77 001001001001001001001001110001 step 78 001001001001001001001001101001 step 79 001001001001001001001001001001 step 80 001001001001001001001001001011 step 81 001001001001001001001001001110 step 82 001001001001001001001001001101 step 83 001001001001001001001001001001 test 12: pass SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFDEFHJKHJKLMNLMNPRSPRSTUV SIDE 111111222111222111222111222222 DIRECTION IIOIIOIIOIIOIIOIIOIIOIIOIIOIIO this fail all fails was hi 111111111111111111111111111111 rising ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ falling vvvvvvvvvvvvvvvvvvvvvvvvvvvvvv was lo 000000000000000000000000000000 total fails 0, total passes 12 step 1 001001001001001001001001001001 step 2 110110110110110110110110110110 step 3 011110110110110110110110110110 step 4 001110110110110110110110110110 step 5 101110110110110110110110110110 step 6 110110110110110110110110110110 step 7 110011110110110110110110110110 step 8 110001110110110110110110110110 step 9 110101110110110110110110110110 step 10 110110110110110110110110110110 step 11 110110011110110110110110110110 step 12 110110001110110110110110110110 step 13 110110101110110110110110110110 step 14 110110110110110110110110110110 step 15 110110110011110110110110110110 step 16 110110110001110110110110110110 step 17 110110110101110110110110110110 step 18 110110110110110110110110110110 step 19 110110110110011110110110110110 step 20 110110110110001110110110110110 step 21 110110110110101110110110110110 step 22 110110110110110110110110110110 step 23 110110110110110011110110110110 step 24 110110110110110001110110110110 step 25 110110110110110101110110110110 step 26 110110110110110110110110110110 step 27 110110110110110110011110110110 step 28 110110110110110110001110110110 step 29 110110110110110110101110110110 step 30 110110110110110110110110110110 step 31 110110110110110110110011110110 step 32 110110110110110110110001110110 step 33 110110110110110110110101110110 step 34 110110110110110110110110110110 step 35 110110110110110110110110011110 step 36 110110110110110110110110001110 step 37 110110110110110110110110101110 step 38 110110110110110110110110110110 step 39 110110110110110110110110110011 step 40 110110110110110110110110110001 step 41 110110110110110110110110110101 step 42 110110110110110110110110110110 step 43 001001001001001001001001001001 step 44 011001001001001001001001001001 step 45 110001001001001001001001001001 step 46 101001001001001001001001001001 step 47 001001001001001001001001001001 step 48 001011001001001001001001001001 step 49 001110001001001001001001001001 step 50 001101001001001001001001001001 step 51 001001001001001001001001001001 step 52 001001011001001001001001001001 step 53 001001110001001001001001001001 step 54 001001101001001001001001001001 step 55 001001001001001001001001001001 step 56 001001001011001001001001001001 step 57 001001001110001001001001001001 step 58 001001001101001001001001001001 step 59 001001001001001001001001001001 step 60 001001001001011001001001001001 step 61 001001001001110001001001001001 step 62 001001001001101001001001001001 step 63 001001001001001001001001001001 step 64 001001001001001011001001001001 step 65 001001001001001110001001001001 step 66 001001001001001101001001001001 step 67 001001001001001001001001001001 step 68 001001001001001001011001001001 step 69 001001001001001001110001001001 step 70 001001001001001001101001001001 step 71 001001001001001001001001001001 step 72 001001001001001001001011001001 step 73 001001001001001001001110001001 step 74 001001001001001001001101001001 step 75 001001001001001001001001001001 step 76 001001001001001001001001011001 step 77 001001001001001001001001110001 step 78 001001001001001001001001101001 step 79 001001001001001001001001001001 step 80 001001001001001001001001001011 step 81 001001001001001001001001001110 step 82 001001001001001001001001001101 step 83 001001001001001001001001001001 test 13: pass SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFDEFHJKHJKLMNLMNPRSPRSTUV SIDE 111111222111222111222111222222 DIRECTION IIOIIOIIOIIOIIOIIOIIOIIOIIOIIO this fail all fails was hi 111111111111111111111111111111 rising ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ falling vvvvvvvvvvvvvvvvvvvvvvvvvvvvvv was lo 000000000000000000000000000000 total fails 0, total passes 13 step 1 001001001001001001001001001001 step 2 110110110110110110110110110110 step 3 011110110110110110110110110110 step 4 001110110110110110110110110110 step 5 101110110110110110110110110110 step 6 110110110110110110110110110110 step 7 110011110110110110110110110110 step 8 110001110110110110110110110110 step 9 110101110110110110110110110110 step 10 110110110110110110110110110110 step 11 110110011110110110110110110110 step 12 110110001110110110110110110110 step 13 110110101110110110110110110110 step 14 110110110110110110110110110110 step 15 110110110011110110110110110110 step 16 110110110001110110110110110110 step 17 110110110101110110110110110110 step 18 110110110110110110110110110110 step 19 110110110110011110110110110110 step 20 110110110110001110110110110110 step 21 110110110110101110110110110110 step 22 110110110110110110110110110110 step 23 110110110110110011110110110110 step 24 110110110110110001110110110110 step 25 110110110110110101110110110110 step 26 110110110110110110110110110110 step 27 110110110110110110011110110110 step 28 110110110110110110001110110110 step 29 110110110110110110101110110110 step 30 110110110110110110110110110110 step 31 110110110110110110110011110110 step 32 110110110110110110110001110110 step 33 110110110110110110110101110110 step 34 110110110110110110110110110110 step 35 110110110110110110110110011110 step 36 110110110110110110110110001110 step 37 110110110110110110110110101110 step 38 110110110110110110110110110110 step 39 110110110110110110110110110011 step 40 110110110110110110110110110001 step 41 110110110110110110110110110101 step 42 110110110110110110110110110110 step 43 001001001001001001001001001001 step 44 011001001001001001001001001001 step 45 110001001001001001001001001001 step 46 101001001001001001001001001001 step 47 001001001001001001001001001001 step 48 001011001001001001001001001001 step 49 001110001001001001001001001001 step 50 001101001001001001001001001001 step 51 001001001001001001001001001001 step 52 001001011001001001001001001001 step 53 001001110001001001001001001001 step 54 001001101001001001001001001001 step 55 001001001001001001001001001001 step 56 001001001011001001001001001001 step 57 001001001110001001001001001001 step 58 001001001101001001001001001001 step 59 001001001001001001001001001001 step 60 001001001001011001001001001001 step 61 001001001001110001001001001001 step 62 001001001001101001001001001001 step 63 001001001001001001001001001001 step 64 001001001001001011001001001001 step 65 001001001001001110001001001001 step 66 001001001001001101001001001001 step 67 001001001001001001001001001001 step 68 001001001001001001011001001001 step 69 001001001001001001110001001001 step 70 001001001001001001101001001001 step 71 001001001001001001001001001001 step 72 001001001001001001001011001001 step 73 001001001001001001001110001001 step 74 001001001001001001001101001001 step 75 001001001001001001001001001001 step 76 001001001001001001001001011001 step 77 001001001001001001001001110001 step 78 001001001001001001001001101001 step 79 001001001001001001001001001001 step 80 001001001001001001001001001011 step 81 001001001001001001001001001110 step 82 001001001001001001001001001101 step 83 001001001001001001001001001001 test 14: pass SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFDEFHJKHJKLMNLMNPRSPRSTUV SIDE 111111222111222111222111222222 DIRECTION IIOIIOIIOIIOIIOIIOIIOIIOIIOIIO this fail all fails was hi 111111111111111111111111111111 rising ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ falling vvvvvvvvvvvvvvvvvvvvvvvvvvvvvv was lo 000000000000000000000000000000 total fails 0, total passes 14 step 1 001001001001001001001001001001 step 2 110110110110110110110110110110 step 3 011110110110110110110110110110 step 4 001110110110110110110110110110 step 5 101110110110110110110110110110 step 6 110110110110110110110110110110 step 7 110011110110110110110110110110 step 8 110001110110110110110110110110 step 9 110101110110110110110110110110 step 10 110110110110110110110110110110 step 11 110110011110110110110110110110 step 12 110110001110110110110110110110 step 13 110110101110110110110110110110 step 14 110110110110110110110110110110 step 15 110110110011110110110110110110 step 16 110110110001110110110110110110 step 17 110110110101110110110110110110 step 18 110110110110110110110110110110 step 19 110110110110011110110110110110 step 20 110110110110001110110110110110 step 21 110110110110101110110110110110 step 22 110110110110110110110110110110 step 23 110110110110110011110110110110 step 24 110110110110110001110110110110 step 25 110110110110110101110110110110 step 26 110110110110110110110110110110 step 27 110110110110110110011110110110 step 28 110110110110110110001110110110 step 29 110110110110110110101110110110 step 30 110110110110110110110110110110 step 31 110110110110110110110011110110 step 32 110110110110110110110001110110 step 33 110110110110110110110101110110 step 34 110110110110110110110110110110 step 35 110110110110110110110110011110 step 36 110110110110110110110110001110 step 37 110110110110110110110110101110 step 38 110110110110110110110110110110 step 39 110110110110110110110110110011 step 40 110110110110110110110110110001 step 41 110110110110110110110110110101 step 42 110110110110110110110110110110 step 43 001001001001001001001001001001 step 44 011001001001001001001001001001 step 45 110001001001001001001001001001 step 46 101001001001001001001001001001 step 47 001001001001001001001001001001 step 48 001011001001001001001001001001 step 49 001110001001001001001001001001 step 50 001101001001001001001001001001 step 51 001001001001001001001001001001 step 52 001001011001001001001001001001 step 53 001001110001001001001001001001 step 54 001001101001001001001001001001 step 55 001001001001001001001001001001 step 56 001001001011001001001001001001 step 57 001001001110001001001001001001 step 58 001001001101001001001001001001 step 59 001001001001001001001001001001 step 60 001001001001011001001001001001 step 61 001001001001110001001001001001 step 62 001001001001101001001001001001 step 63 001001001001001001001001001001 step 64 001001001001001011001001001001 step 65 001001001001001110001001001001 step 66 001001001001001101001001001001 step 67 001001001001001001001001001001 step 68 001001001001001001011001001001 step 69 001001001001001001110001001001 step 70 001001001001001001101001001001 step 71 001001001001001001001001001001 step 72 001001001001001001001011001001 step 73 001001001001001001001110001001 step 74 001001001001001001001101001001 step 75 001001001001001001001001001001 step 76 001001001001001001001001011001 step 77 001001001001001001001001110001 step 78 001001001001001001001001101001 step 79 001001001001001001001001001001 step 80 001001001001001001001001001011 step 81 001001001001001001001001001110 step 82 001001001001001001001001001101 step 83 001001001001001001001001001001 test 15: pass SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFDEFHJKHJKLMNLMNPRSPRSTUV SIDE 111111222111222111222111222222 DIRECTION IIOIIOIIOIIOIIOIIOIIOIIOIIOIIO this fail all fails was hi 111111111111111111111111111111 rising ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ falling vvvvvvvvvvvvvvvvvvvvvvvvvvvvvv was lo 000000000000000000000000000000 total fails 0, total passes 15 step 1 001001001001001001001001001001 step 2 110110110110110110110110110110 step 3 011110110110110110110110110110 step 4 001110110110110110110110110110 step 5 101110110110110110110110110110 step 6 110110110110110110110110110110 step 7 110011110110110110110110110110 step 8 110001110110110110110110110110 step 9 110101110110110110110110110110 step 10 110110110110110110110110110110 step 11 110110011110110110110110110110 step 12 110110001110110110110110110110 step 13 110110101110110110110110110110 step 14 110110110110110110110110110110 step 15 110110110011110110110110110110 step 16 110110110001110110110110110110 step 17 110110110101110110110110110110 step 18 110110110110110110110110110110 step 19 110110110110011110110110110110 step 20 110110110110001110110110110110 step 21 110110110110101110110110110110 step 22 110110110110110110110110110110 step 23 110110110110110011110110110110 step 24 110110110110110001110110110110 step 25 110110110110110101110110110110 step 26 110110110110110110110110110110 step 27 110110110110110110011110110110 step 28 110110110110110110001110110110 step 29 110110110110110110101110110110 step 30 110110110110110110110110110110 step 31 110110110110110110110011110110 step 32 110110110110110110110001110110 step 33 110110110110110110110101110110 step 34 110110110110110110110110110110 step 35 110110110110110110110110011110 step 36 110110110110110110110110001110 step 37 110110110110110110110110101110 step 38 110110110110110110110110110110 step 39 110110110110110110110110110011 step 40 110110110110110110110110110001 step 41 110110110110110110110110110101 step 42 110110110110110110110110110110 step 43 001001001001001001001001001001 step 44 011001001001001001001001001001 step 45 110001001001001001001001001001 step 46 101001001001001001001001001001 step 47 001001001001001001001001001001 step 48 001011001001001001001001001001 step 49 001110001001001001001001001001 step 50 001101001001001001001001001001 step 51 001001001001001001001001001001 step 52 001001011001001001001001001001 step 53 001001110001001001001001001001 step 54 001001101001001001001001001001 step 55 001001001001001001001001001001 step 56 001001001011001001001001001001 step 57 001001001110001001001001001001 step 58 001001001101001001001001001001 step 59 001001001001001001001001001001 step 60 001001001001011001001001001001 step 61 001001001001110001001001001001 step 62 001001001001101001001001001001 step 63 001001001001001001001001001001 step 64 001001001001001011001001001001 step 65 001001001001001110001001001001 step 66 001001001001001101001001001001 step 67 001001001001001001001001001001 step 68 001001001001001001011001001001 step 69 001001001001001001110001001001 step 70 001001001001001001101001001001 step 71 001001001001001001001001001001 step 72 001001001001001001001011001001 step 73 001001001001001001001110001001 step 74 001001001001001001001101001001 step 75 001001001001001001001001001001 step 76 001001001001001001001001011001 step 77 001001001001001001001001110001 step 78 001001001001001001001001101001 step 79 001001001001001001001001001001 step 80 001001001001001001001001001011 step 81 001001001001001001001001001110 step 82 001001001001001001001001001101 step 83 001001001001001001001001001001 test 16: pass SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFDEFHJKHJKLMNLMNPRSPRSTUV SIDE 111111222111222111222111222222 DIRECTION IIOIIOIIOIIOIIOIIOIIOIIOIIOIIO this fail all fails was hi 111111111111111111111111111111 rising ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ falling vvvvvvvvvvvvvvvvvvvvvvvvvvvvvv was lo 000000000000000000000000000000 total fails 0, total passes 16 step 1 001001001001001001001001001001 step 2 110110110110110110110110110110 step 3 011110110110110110110110110110 step 4 001110110110110110110110110110 step 5 101110110110110110110110110110 step 6 110110110110110110110110110110 step 7 110011110110110110110110110110 step 8 110001110110110110110110110110 step 9 110101110110110110110110110110 step 10 110110110110110110110110110110 step 11 110110011110110110110110110110 step 12 110110001110110110110110110110 step 13 110110101110110110110110110110 step 14 110110110110110110110110110110 step 15 110110110011110110110110110110 step 16 110110110001110110110110110110 step 17 110110110101110110110110110110 step 18 110110110110110110110110110110 step 19 110110110110011110110110110110 step 20 110110110110001110110110110110 step 21 110110110110101110110110110110 step 22 110110110110110110110110110110 step 23 110110110110110011110110110110 step 24 110110110110110001110110110110 step 25 110110110110110101110110110110 step 26 110110110110110110110110110110 step 27 110110110110110110011110110110 step 28 110110110110110110001110110110 step 29 110110110110110110101110110110 step 30 110110110110110110110110110110 step 31 110110110110110110110011110110 step 32 110110110110110110110001110110 step 33 110110110110110110110101110110 step 34 110110110110110110110110110110 step 35 110110110110110110110110011110 step 36 110110110110110110110110001110 step 37 110110110110110110110110101110 step 38 110110110110110110110110110110 step 39 110110110110110110110110110011 step 40 110110110110110110110110110001 step 41 110110110110110110110110110101 step 42 110110110110110110110110110110 step 43 001001001001001001001001001001 step 44 011001001001001001001001001001 step 45 110001001001001001001001001001 step 46 101001001001001001001001001001 step 47 001001001001001001001001001001 step 48 001011001001001001001001001001 step 49 001110001001001001001001001001 step 50 001101001001001001001001001001 step 51 001001001001001001001001001001 step 52 001001011001001001001001001001 step 53 001001110001001001001001001001 step 54 001001101001001001001001001001 step 55 001001001001001001001001001001 step 56 001001001011001001001001001001 step 57 001001001110001001001001001001 step 58 001001001101001001001001001001 step 59 001001001001001001001001001001 step 60 001001001001011001001001001001 step 61 001001001001110001001001001001 step 62 001001001001101001001001001001 step 63 001001001001001001001001001001 step 64 001001001001001011001001001001 step 65 001001001001001110001001001001 step 66 001001001001001101001001001001 step 67 001001001001001001001001001001 step 68 001001001001001001011001001001 step 69 001001001001001001110001001001 step 70 001001001001001001101001001001 step 71 001001001001001001001001001001 step 72 001001001001001001001011001001 step 73 001001001001001001001110001001 step 74 001001001001001001001101001001 step 75 001001001001001001001001001001 step 76 001001001001001001001001011001 step 77 001001001001001001001001110001 step 78 001001001001001001001001101001 step 79 001001001001001001001001001001 step 80 001001001001001001001001001011 step 81 001001001001001001001001001110 step 82 001001001001001001001001001101 step 83 001001001001001001001001001001 test 17: pass SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFDEFHJKHJKLMNLMNPRSPRSTUV SIDE 111111222111222111222111222222 DIRECTION IIOIIOIIOIIOIIOIIOIIOIIOIIOIIO this fail all fails was hi 111111111111111111111111111111 rising ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ falling vvvvvvvvvvvvvvvvvvvvvvvvvvvvvv was lo 000000000000000000000000000000 total fails 0, total passes 17 step 1 001001001001001001001001001001 step 2 110110110110110110110110110110 step 3 011110110110110110110110110110 step 4 001110110110110110110110110110 step 5 101110110110110110110110110110 step 6 110110110110110110110110110110 step 7 110011110110110110110110110110 step 8 110001110110110110110110110110 step 9 110101110110110110110110110110 step 10 110110110110110110110110110110 step 11 110110011110110110110110110110 step 12 110110001110110110110110110110 step 13 110110101110110110110110110110 step 14 110110110110110110110110110110 step 15 110110110011110110110110110110 step 16 110110110001110110110110110110 step 17 110110110101110110110110110110 step 18 110110110110110110110110110110 step 19 110110110110011110110110110110 step 20 110110110110001110110110110110 step 21 110110110110101110110110110110 step 22 110110110110110110110110110110 step 23 110110110110110011110110110110 step 24 110110110110110001110110110110 step 25 110110110110110101110110110110 step 26 110110110110110110110110110110 step 27 110110110110110110011110110110 step 28 110110110110110110001110110110 step 29 110110110110110110101110110110 step 30 110110110110110110110110110110 step 31 110110110110110110110011110110 step 32 110110110110110110110001110110 step 33 110110110110110110110101110110 step 34 110110110110110110110110110110 step 35 110110110110110110110110011110 step 36 110110110110110110110110001110 step 37 110110110110110110110110101110 step 38 110110110110110110110110110110 step 39 110110110110110110110110110011 step 40 110110110110110110110110110001 step 41 110110110110110110110110110101 step 42 110110110110110110110110110110 step 43 001001001001001001001001001001 step 44 011001001001001001001001001001 step 45 110001001001001001001001001001 step 46 101001001001001001001001001001 step 47 001001001001001001001001001001 step 48 001011001001001001001001001001 step 49 001110001001001001001001001001 step 50 001101001001001001001001001001 step 51 001001001001001001001001001001 step 52 001001011001001001001001001001 step 53 001001110001001001001001001001 step 54 001001101001001001001001001001 step 55 001001001001001001001001001001 step 56 001001001011001001001001001001 step 57 001001001110001001001001001001 step 58 001001001101001001001001001001 step 59 001001001001001001001001001001 step 60 001001001001011001001001001001 step 61 001001001001110001001001001001 step 62 001001001001101001001001001001 step 63 001001001001001001001001001001 step 64 001001001001001011001001001001 step 65 001001001001001110001001001001 step 66 001001001001001101001001001001 step 67 001001001001001001001001001001 step 68 001001001001001001011001001001 step 69 001001001001001001110001001001 step 70 001001001001001001101001001001 step 71 001001001001001001001001001001 step 72 001001001001001001001011001001 step 73 001001001001001001001110001001 step 74 001001001001001001001101001001 step 75 001001001001001001001001001001 step 76 001001001001001001001001011001 step 77 001001001001001001001001110001 step 78 001001001001001001001001101001 step 79 001001001001001001001001001001 step 80 001001001001001001001001001011 step 81 001001001001001001001001001110 step 82 001001001001001001001001001101 step 83 001001001001001001001001001001 test 18: pass SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFDEFHJKHJKLMNLMNPRSPRSTUV SIDE 111111222111222111222111222222 DIRECTION IIOIIOIIOIIOIIOIIOIIOIIOIIOIIO this fail all fails was hi 111111111111111111111111111111 rising ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ falling vvvvvvvvvvvvvvvvvvvvvvvvvvvvvv was lo 000000000000000000000000000000 total fails 0, total passes 18 step 1 001001001001001001001001001001 step 2 110110110110110110110110110110 step 3 011110110110110110110110110110 step 4 001110110110110110110110110110 step 5 101110110110110110110110110110 step 6 110110110110110110110110110110 step 7 110011110110110110110110110110 step 8 110001110110110110110110110110 step 9 110101110110110110110110110110 step 10 110110110110110110110110110110 step 11 110110011110110110110110110110 step 12 110110001110110110110110110110 step 13 110110101110110110110110110110 step 14 110110110110110110110110110110 step 15 110110110011110110110110110110 step 16 110110110001110110110110110110 step 17 110110110101110110110110110110 step 18 110110110110110110110110110110 step 19 110110110110011110110110110110 step 20 110110110110001110110110110110 step 21 110110110110101110110110110110 step 22 110110110110110110110110110110 step 23 110110110110110011110110110110 step 24 110110110110110001110110110110 step 25 110110110110110101110110110110 step 26 110110110110110110110110110110 step 27 110110110110110110011110110110 step 28 110110110110110110001110110110 step 29 110110110110110110101110110110 step 30 110110110110110110110110110110 step 31 110110110110110110110011110110 step 32 110110110110110110110001110110 step 33 110110110110110110110101110110 step 34 110110110110110110110110110110 step 35 110110110110110110110110011110 step 36 110110110110110110110110001110 step 37 110110110110110110110110101110 step 38 110110110110110110110110110110 step 39 110110110110110110110110110011 step 40 110110110110110110110110110001 step 41 110110110110110110110110110101 step 42 110110110110110110110110110110 step 43 001001001001001001001001001001 step 44 011001001001001001001001001001 step 45 110001001001001001001001001001 step 46 101001001001001001001001001001 step 47 001001001001001001001001001001 step 48 001011001001001001001001001001 step 49 001110001001001001001001001001 step 50 001101001001001001001001001001 step 51 001001001001001001001001001001 step 52 001001011001001001001001001001 step 53 001001110001001001001001001001 step 54 001001101001001001001001001001 step 55 001001001001001001001001001001 step 56 001001001011001001001001001001 step 57 001001001110001001001001001001 step 58 001001001101001001001001001001 step 59 001001001001001001001001001001 step 60 001001001001011001001001001001 step 61 001001001001110001001001001001 step 62 001001001001101001001001001001 step 63 001001001001001001001001001001 step 64 001001001001001011001001001001 step 65 001001001001001110001001001001 step 66 001001001001001101001001001001 step 67 001001001001001001001001001001 step 68 001001001001001001011001001001 step 69 001001001001001001110001001001 step 70 001001001001001001101001001001 step 71 001001001001001001001001001001 step 72 001001001001001001001011001001 step 73 001001001001001001001110001001 step 74 001001001001001001001101001001 step 75 001001001001001001001001001001 step 76 001001001001001001001001011001 step 77 001001001001001001001001110001 step 78 001001001001001001001001101001 step 79 001001001001001001001001001001 step 80 001001001001001001001001001011 step 81 001001001001001001001001001110 step 82 001001001001001001001001001101 step 83 001001001001001001001001001001 test 19: pass SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFDEFHJKHJKLMNLMNPRSPRSTUV SIDE 111111222111222111222111222222 DIRECTION IIOIIOIIOIIOIIOIIOIIOIIOIIOIIO this fail all fails was hi 111111111111111111111111111111 rising ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ falling vvvvvvvvvvvvvvvvvvvvvvvvvvvvvv was lo 000000000000000000000000000000 total fails 0, total passes 19 step 1 001001001001001001001001001001 step 2 110110110110110110110110110110 step 3 011110110110110110110110110110 step 4 001110110110110110110110110110 step 5 101110110110110110110110110110 step 6 110110110110110110110110110110 step 7 110011110110110110110110110110 step 8 110001110110110110110110110110 step 9 110101110110110110110110110110 step 10 110110110110110110110110110110 step 11 110110011110110110110110110110 step 12 110110001110110110110110110110 step 13 110110101110110110110110110110 step 14 110110110110110110110110110110 step 15 110110110011110110110110110110 step 16 110110110001110110110110110110 step 17 110110110101110110110110110110 step 18 110110110110110110110110110110 step 19 110110110110011110110110110110 step 20 110110110110001110110110110110 step 21 110110110110101110110110110110 step 22 110110110110110110110110110110 step 23 110110110110110011110110110110 step 24 110110110110110001110110110110 step 25 110110110110110101110110110110 step 26 110110110110110110110110110110 step 27 110110110110110110011110110110 step 28 110110110110110110001110110110 step 29 110110110110110110101110110110 step 30 110110110110110110110110110110 step 31 110110110110110110110011110110 step 32 110110110110110110110001110110 step 33 110110110110110110110101110110 step 34 110110110110110110110110110110 step 35 110110110110110110110110011110 step 36 110110110110110110110110001110 step 37 110110110110110110110110101110 step 38 110110110110110110110110110110 step 39 110110110110110110110110110011 step 40 110110110110110110110110110001 step 41 110110110110110110110110110101 step 42 110110110110110110110110110110 step 43 001001001001001001001001001001 step 44 011001001001001001001001001001 step 45 110001001001001001001001001001 step 46 101001001001001001001001001001 step 47 001001001001001001001001001001 step 48 001011001001001001001001001001 step 49 001110001001001001001001001001 step 50 001101001001001001001001001001 step 51 001001001001001001001001001001 step 52 001001011001001001001001001001 step 53 001001110001001001001001001001 step 54 001001101001001001001001001001 step 55 001001001001001001001001001001 step 56 001001001011001001001001001001 step 57 001001001110001001001001001001 step 58 001001001101001001001001001001 step 59 001001001001001001001001001001 step 60 001001001001011001001001001001 step 61 001001001001110001001001001001 step 62 001001001001101001001001001001 step 63 001001001001001001001001001001 step 64 001001001001001011001001001001 step 65 001001001001001110001001001001 step 66 001001001001001101001001001001 step 67 001001001001001001001001001001 step 68 001001001001001001011001001001 step 69 001001001001001001110001001001 step 70 001001001001001001101001001001 step 71 001001001001001001001001001001 step 72 001001001001001001001011001001 step 73 001001001001001001001110001001 step 74 001001001001001001001101001001 step 75 001001001001001001001001001001 step 76 001001001001001001001001011001 step 77 001001001001001001001001110001 step 78 001001001001001001001001101001 step 79 001001001001001001001001001001 step 80 001001001001001001001001001011 step 81 001001001001001001001001001110 step 82 001001001001001001001001001101 step 83 001001001001001001001001001001 test 20: pass SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFDEFHJKHJKLMNLMNPRSPRSTUV SIDE 111111222111222111222111222222 DIRECTION IIOIIOIIOIIOIIOIIOIIOIIOIIOIIO this fail all fails was hi 111111111111111111111111111111 rising ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ falling vvvvvvvvvvvvvvvvvvvvvvvvvvvvvv was lo 000000000000000000000000000000 total fails 0, total passes 20 step 1 001001001001001001001001001001 step 2 110110110110110110110110110110 step 3 011110110110110110110110110110 step 4 001110110110110110110110110110 step 5 101110110110110110110110110110 step 6 110110110110110110110110110110 step 7 110011110110110110110110110110 step 8 110001110110110110110110110110 step 9 110101110110110110110110110110 step 10 110110110110110110110110110110 step 11 110110011110110110110110110110 step 12 110110001110110110110110110110 step 13 110110101110110110110110110110 step 14 110110110110110110110110110110 step 15 110110110011110110110110110110 step 16 110110110001110110110110110110 step 17 110110110101110110110110110110 step 18 110110110110110110110110110110 step 19 110110110110011110110110110110 step 20 110110110110001110110110110110 step 21 110110110110101110110110110110 step 22 110110110110110110110110110110 step 23 110110110110110011110110110110 step 24 110110110110110001110110110110 step 25 110110110110110101110110110110 step 26 110110110110110110110110110110 step 27 110110110110110110011110110110 step 28 110110110110110110001110110110 step 29 110110110110110110101110110110 step 30 110110110110110110110110110110 step 31 110110110110110110110011110110 step 32 110110110110110110110001110110 step 33 110110110110110110110101110110 step 34 110110110110110110110110110110 step 35 110110110110110110110110011110 step 36 110110110110110110110110001110 step 37 110110110110110110110110101110 step 38 110110110110110110110110110110 step 39 110110110110110110110110110011 step 40 110110110110110110110110110001 step 41 110110110110110110110110110101 step 42 110110110110110110110110110110 step 43 001001001001001001001001001001 step 44 011001001001001001001001001001 step 45 110001001001001001001001001001 step 46 101001001001001001001001001001 step 47 001001001001001001001001001001 step 48 001011001001001001001001001001 step 49 001110001001001001001001001001 step 50 001101001001001001001001001001 step 51 001001001001001001001001001001 step 52 001001011001001001001001001001 step 53 001001110001001001001001001001 step 54 001001101001001001001001001001 step 55 001001001001001001001001001001 step 56 001001001011001001001001001001 step 57 001001001110001001001001001001 step 58 001001001101001001001001001001 step 59 001001001001001001001001001001 step 60 001001001001011001001001001001 step 61 001001001001110001001001001001 step 62 001001001001101001001001001001 step 63 001001001001001001001001001001 step 64 001001001001001011001001001001 step 65 001001001001001110001001001001 step 66 001001001001001101001001001001 step 67 001001001001001001001001001001 step 68 001001001001001001011001001001 step 69 001001001001001001110001001001 step 70 001001001001001001101001001001 step 71 001001001001001001001001001001 step 72 001001001001001001001011001001 step 73 001001001001001001001110001001 step 74 001001001001001001001101001001 step 75 001001001001001001001001001001 step 76 001001001001001001001001011001 step 77 001001001001001001001001110001 step 78 001001001001001001001001101001 step 79 001001001001001001001001001001 step 80 001001001001001001001001001011 step 81 001001001001001001001001001110 step 82 001001001001001001001001001101 step 83 001001001001001001001001001001 test 21: pass SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFDEFHJKHJKLMNLMNPRSPRSTUV SIDE 111111222111222111222111222222 DIRECTION IIOIIOIIOIIOIIOIIOIIOIIOIIOIIO this fail all fails was hi 111111111111111111111111111111 rising ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ falling vvvvvvvvvvvvvvvvvvvvvvvvvvvvvv was lo 000000000000000000000000000000 total fails 0, total passes 21 step 1 001001001001001001001001001001 step 2 110110110110110110110110110110 step 3 011110110110110110110110110110 step 4 001110110110110110110110110110 step 5 101110110110110110110110110110 step 6 110110110110110110110110110110 step 7 110011110110110110110110110110 step 8 110001110110110110110110110110 step 9 110101110110110110110110110110 step 10 110110110110110110110110110110 step 11 110110011110110110110110110110 step 12 110110001110110110110110110110 step 13 110110101110110110110110110110 step 14 110110110110110110110110110110 step 15 110110110011110110110110110110 step 16 110110110001110110110110110110 step 17 110110110101110110110110110110 step 18 110110110110110110110110110110 step 19 110110110110011110110110110110 step 20 110110110110001110110110110110 step 21 110110110110101110110110110110 step 22 110110110110110110110110110110 step 23 110110110110110011110110110110 step 24 110110110110110001110110110110 step 25 110110110110110101110110110110 step 26 110110110110110110110110110110 step 27 110110110110110110011110110110 step 28 110110110110110110001110110110 step 29 110110110110110110101110110110 step 30 110110110110110110110110110110 step 31 110110110110110110110011110110 step 32 110110110110110110110001110110 step 33 110110110110110110110101110110 step 34 110110110110110110110110110110 step 35 110110110110110110110110011110 step 36 110110110110110110110110001110 step 37 110110110110110110110110101110 step 38 110110110110110110110110110110 step 39 110110110110110110110110110011 step 40 110110110110110110110110110001 step 41 110110110110110110110110110101 step 42 110110110110110110110110110110 step 43 001001001001001001001001001001 step 44 011001001001001001001001001001 step 45 110001001001001001001001001001 step 46 101001001001001001001001001001 step 47 001001001001001001001001001001 step 48 001011001001001001001001001001 step 49 001110001001001001001001001001 step 50 001101001001001001001001001001 step 51 001001001001001001001001001001 step 52 001001011001001001001001001001 step 53 001001110001001001001001001001 step 54 001001101001001001001001001001 step 55 001001001001001001001001001001 step 56 001001001011001001001001001001 step 57 001001001110001001001001001001 step 58 001001001101001001001001001001 step 59 001001001001001001001001001001 step 60 001001001001011001001001001001 step 61 001001001001110001001001001001 step 62 001001001001101001001001001001 step 63 001001001001001001001001001001 step 64 001001001001001011001001001001 step 65 001001001001001110001001001001 step 66 001001001001001101001001001001 step 67 001001001001001001001001001001 step 68 001001001001001001011001001001 step 69 001001001001001001110001001001 step 70 001001001001001001101001001001 step 71 001001001001001001001001001001 step 72 001001001001001001001011001001 step 73 001001001001001001001110001001 step 74 001001001001001001001101001001 step 75 001001001001001001001001001001 step 76 001001001001001001001001011001 step 77 001001001001001001001001110001 step 78 001001001001001001001001101001 step 79 001001001001001001001001001001 step 80 001001001001001001001001001011 step 81 001001001001001001001001001110 step 82 001001001001001001001001001101 step 83 001001001001001001001001001001 test 22: pass SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFDEFHJKHJKLMNLMNPRSPRSTUV SIDE 111111222111222111222111222222 DIRECTION IIOIIOIIOIIOIIOIIOIIOIIOIIOIIO this fail all fails was hi 111111111111111111111111111111 rising ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ falling vvvvvvvvvvvvvvvvvvvvvvvvvvvvvv was lo 000000000000000000000000000000 total fails 0, total passes 22 step 1 001001001001001001001001001001 step 2 110110110110110110110110110110 step 3 011110110110110110110110110110 step 4 001110110110110110110110110110 step 5 101110110110110110110110110110 step 6 110110110110110110110110110110 step 7 110011110110110110110110110110 step 8 110001110110110110110110110110 step 9 110101110110110110110110110110 step 10 110110110110110110110110110110 step 11 110110011110110110110110110110 step 12 110110001110110110110110110110 step 13 110110101110110110110110110110 step 14 110110110110110110110110110110 step 15 110110110011110110110110110110 step 16 110110110001110110110110110110 step 17 110110110101110110110110110110 step 18 110110110110110110110110110110 step 19 110110110110011110110110110110 step 20 110110110110001110110110110110 step 21 110110110110101110110110110110 step 22 110110110110110110110110110110 step 23 110110110110110011110110110110 step 24 110110110110110001110110110110 step 25 110110110110110101110110110110 step 26 110110110110110110110110110110 step 27 110110110110110110011110110110 step 28 110110110110110110001110110110 step 29 110110110110110110101110110110 step 30 110110110110110110110110110110 step 31 110110110110110110110011110110 step 32 110110110110110110110001110110 step 33 110110110110110110110101110110 step 34 110110110110110110110110110110 step 35 110110110110110110110110011110 step 36 110110110110110110110110001110 step 37 110110110110110110110110101110 step 38 110110110110110110110110110110 step 39 110110110110110110110110110011 step 40 110110110110110110110110110001 step 41 110110110110110110110110110101 step 42 110110110110110110110110110110 step 43 001001001001001001001001001001 step 44 011001001001001001001001001001 step 45 110001001001001001001001001001 step 46 101001001001001001001001001001 step 47 001001001001001001001001001001 step 48 001011001001001001001001001001 step 49 001110001001001001001001001001 step 50 001101001001001001001001001001 step 51 001001001001001001001001001001 step 52 001001011001001001001001001001 step 53 001001110001001001001001001001 step 54 001001101001001001001001001001 step 55 001001001001001001001001001001 step 56 001001001011001001001001001001 step 57 001001001110001001001001001001 step 58 001001001101001001001001001001 step 59 001001001001001001001001001001 step 60 001001001001011001001001001001 step 61 001001001001110001001001001001 step 62 001001001001101001001001001001 step 63 001001001001001001001001001001 step 64 001001001001001011001001001001 step 65 001001001001001110001001001001 step 66 001001001001001101001001001001 step 67 001001001001001001001001001001 step 68 001001001001001001011001001001 step 69 001001001001001001110001001001 step 70 001001001001001001101001001001 step 71 001001001001001001001001001001 step 72 001001001001001001001011001001 step 73 001001001001001001001110001001 step 74 001001001001001001001101001001 step 75 001001001001001001001001001001 step 76 001001001001001001001001011001 step 77 001001001001001001001001110001 step 78 001001001001001001001001101001 step 79 001001001001001001001001001001 step 80 001001001001001001001001001011 step 81 001001001001001001001001001110 step 82 001001001001001001001001001101 step 83 001001001001001001001001001001 test 23: pass SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFDEFHJKHJKLMNLMNPRSPRSTUV SIDE 111111222111222111222111222222 DIRECTION IIOIIOIIOIIOIIOIIOIIOIIOIIOIIO this fail all fails was hi 111111111111111111111111111111 rising ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ falling vvvvvvvvvvvvvvvvvvvvvvvvvvvvvv was lo 000000000000000000000000000000 total fails 0, total passes 23 step 1 001001001001001001001001001001 step 2 110110110110110110110110110110 step 3 011110110110110110110110110110 step 4 001110110110110110110110110110 step 5 101110110110110110110110110110 step 6 110110110110110110110110110110 step 7 110011110110110110110110110110 step 8 110001110110110110110110110110 step 9 110101110110110110110110110110 step 10 110110110110110110110110110110 step 11 110110011110110110110110110110 step 12 110110001110110110110110110110 step 13 110110101110110110110110110110 step 14 110110110110110110110110110110 step 15 110110110011110110110110110110 step 16 110110110001110110110110110110 step 17 110110110101110110110110110110 step 18 110110110110110110110110110110 step 19 110110110110011110110110110110 step 20 110110110110001110110110110110 step 21 110110110110101110110110110110 step 22 110110110110110110110110110110 step 23 110110110110110011110110110110 step 24 110110110110110001110110110110 step 25 110110110110110101110110110110 step 26 110110110110110110110110110110 step 27 110110110110110110011110110110 step 28 110110110110110110001110110110 step 29 110110110110110110101110110110 step 30 110110110110110110110110110110 step 31 110110110110110110110011110110 step 32 110110110110110110110001110110 step 33 110110110110110110110101110110 step 34 110110110110110110110110110110 step 35 110110110110110110110110011110 step 36 110110110110110110110110001110 step 37 110110110110110110110110101110 step 38 110110110110110110110110110110 step 39 110110110110110110110110110011 step 40 110110110110110110110110110001 step 41 110110110110110110110110110101 step 42 110110110110110110110110110110 step 43 001001001001001001001001001001 step 44 011001001001001001001001001001 step 45 110001001001001001001001001001 step 46 101001001001001001001001001001 step 47 001001001001001001001001001001 step 48 001011001001001001001001001001 step 49 001110001001001001001001001001 step 50 001101001001001001001001001001 step 51 001001001001001001001001001001 step 52 001001011001001001001001001001 step 53 001001110001001001001001001001 step 54 001001101001001001001001001001 step 55 001001001001001001001001001001 step 56 001001001011001001001001001001 step 57 001001001110001001001001001001 step 58 001001001101001001001001001001 step 59 001001001001001001001001001001 step 60 001001001001011001001001001001 step 61 001001001001110001001001001001 step 62 001001001001101001001001001001 step 63 001001001001001001001001001001 step 64 001001001001001011001001001001 step 65 001001001001001110001001001001 step 66 001001001001001101001001001001 step 67 001001001001001001001001001001 step 68 001001001001001001011001001001 step 69 001001001001001001110001001001 step 70 001001001001001001101001001001 step 71 001001001001001001001001001001 step 72 001001001001001001001011001001 step 73 001001001001001001001110001001 step 74 001001001001001001001101001001 step 75 001001001001001001001001001001 step 76 001001001001001001001001011001 step 77 001001001001001001001001110001 step 78 001001001001001001001001101001 step 79 001001001001001001001001001001 step 80 001001001001001001001001001011 step 81 001001001001001001001001001110 step 82 001001001001001001001001001101 step 83 001001001001001001001001001001 test 24: pass SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFDEFHJKHJKLMNLMNPRSPRSTUV SIDE 111111222111222111222111222222 DIRECTION IIOIIOIIOIIOIIOIIOIIOIIOIIOIIO this fail all fails was hi 111111111111111111111111111111 rising ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ falling vvvvvvvvvvvvvvvvvvvvvvvvvvvvvv was lo 000000000000000000000000000000 total fails 0, total passes 24 step 1 001001001001001001001001001001 step 2 110110110110110110110110110110 step 3 011110110110110110110110110110 step 4 001110110110110110110110110110 step 5 101110110110110110110110110110 step 6 110110110110110110110110110110 step 7 110011110110110110110110110110 step 8 110001110110110110110110110110 step 9 110101110110110110110110110110 step 10 110110110110110110110110110110 step 11 110110011110110110110110110110 step 12 110110001110110110110110110110 step 13 110110101110110110110110110110 step 14 110110110110110110110110110110 step 15 110110110011110110110110110110 step 16 110110110001110110110110110110 step 17 110110110101110110110110110110 step 18 110110110110110110110110110110 step 19 110110110110011110110110110110 step 20 110110110110001110110110110110 step 21 110110110110101110110110110110 step 22 110110110110110110110110110110 step 23 110110110110110011110110110110 step 24 110110110110110001110110110110 step 25 110110110110110101110110110110 step 26 110110110110110110110110110110 step 27 110110110110110110011110110110 step 28 110110110110110110001110110110 step 29 110110110110110110101110110110 step 30 110110110110110110110110110110 step 31 110110110110110110110011110110 step 32 110110110110110110110001110110 step 33 110110110110110110110101110110 step 34 110110110110110110110110110110 step 35 110110110110110110110110011110 step 36 110110110110110110110110001110 step 37 110110110110110110110110101110 step 38 110110110110110110110110110110 step 39 110110110110110110110110110011 step 40 110110110110110110110110110001 step 41 110110110110110110110110110101 step 42 110110110110110110110110110110 step 43 001001001001001001001001001001 step 44 011001001001001001001001001001 step 45 110001001001001001001001001001 step 46 101001001001001001001001001001 step 47 001001001001001001001001001001 step 48 001011001001001001001001001001 step 49 001110001001001001001001001001 step 50 001101001001001001001001001001 step 51 001001001001001001001001001001 step 52 001001011001001001001001001001 step 53 001001110001001001001001001001 step 54 001001101001001001001001001001 step 55 001001001001001001001001001001 step 56 001001001011001001001001001001 step 57 001001001110001001001001001001 step 58 001001001101001001001001001001 step 59 001001001001001001001001001001 step 60 001001001001011001001001001001 step 61 001001001001110001001001001001 step 62 001001001001101001001001001001 step 63 001001001001001001001001001001 step 64 001001001001001011001001001001 step 65 001001001001001110001001001001 step 66 001001001001001101001001001001 step 67 001001001001001001001001001001 step 68 001001001001001001011001001001 step 69 001001001001001001110001001001 step 70 001001001001001001101001001001 step 71 001001001001001001001001001001 step 72 001001001001001001001011001001 step 73 001001001001001001001110001001 step 74 001001001001001001001101001001 step 75 001001001001001001001001001001 step 76 001001001001001001001001011001 step 77 001001001001001001001001110001 step 78 001001001001001001001001101001 step 79 001001001001001001001001001001 step 80 001001001001001001001001001011 step 81 001001001001001001001001001110 step 82 001001001001001001001001001101 step 83 001001001001001001001001001001 test 25: pass SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFDEFHJKHJKLMNLMNPRSPRSTUV SIDE 111111222111222111222111222222 DIRECTION IIOIIOIIOIIOIIOIIOIIOIIOIIOIIO this fail all fails was hi 111111111111111111111111111111 rising ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ falling vvvvvvvvvvvvvvvvvvvvvvvvvvvvvv was lo 000000000000000000000000000000 total fails 0, total passes 25 step 1 001001001001001001001001001001 step 2 110110110110110110110110110110 step 3 011110110110110110110110110110 step 4 001110110110110110110110110110 step 5 101110110110110110110110110110 step 6 110110110110110110110110110110 step 7 110011110110110110110110110110 step 8 110001110110110110110110110110 step 9 110101110110110110110110110110 step 10 110110110110110110110110110110 step 11 110110011110110110110110110110 step 12 110110001110110110110110110110 step 13 110110101110110110110110110110 step 14 110110110110110110110110110110 step 15 110110110011110110110110110110 step 16 110110110001110110110110110110 step 17 110110110101110110110110110110 step 18 110110110110110110110110110110 step 19 110110110110011110110110110110 step 20 110110110110001110110110110110 step 21 110110110110101110110110110110 step 22 110110110110110110110110110110 step 23 110110110110110011110110110110 step 24 110110110110110001110110110110 step 25 110110110110110101110110110110 step 26 110110110110110110110110110110 step 27 110110110110110110011110110110 step 28 110110110110110110001110110110 step 29 110110110110110110101110110110 step 30 110110110110110110110110110110 step 31 110110110110110110110011110110 step 32 110110110110110110110001110110 step 33 110110110110110110110101110110 step 34 110110110110110110110110110110 step 35 110110110110110110110110011110 step 36 110110110110110110110110001110 step 37 110110110110110110110110101110 step 38 110110110110110110110110110110 step 39 110110110110110110110110110011 step 40 110110110110110110110110110001 step 41 110110110110110110110110110101 step 42 110110110110110110110110110110 step 43 001001001001001001001001001001 step 44 011001001001001001001001001001 step 45 110001001001001001001001001001 step 46 101001001001001001001001001001 step 47 001001001001001001001001001001 step 48 001011001001001001001001001001 step 49 001110001001001001001001001001 step 50 001101001001001001001001001001 step 51 001001001001001001001001001001 step 52 001001011001001001001001001001 step 53 001001110001001001001001001001 step 54 001001101001001001001001001001 step 55 001001001001001001001001001001 step 56 001001001011001001001001001001 step 57 001001001110001001001001001001 step 58 001001001101001001001001001001 step 59 001001001001001001001001001001 step 60 001001001001011001001001001001 step 61 001001001001110001001001001001 step 62 001001001001101001001001001001 step 63 001001001001001001001001001001 step 64 001001001001001011001001001001 step 65 001001001001001110001001001001 step 66 001001001001001101001001001001 step 67 001001001001001001001001001001 step 68 001001001001001001011001001001 step 69 001001001001001001110001001001 step 70 001001001001001001101001001001 step 71 001001001001001001001001001001 step 72 001001001001001001001011001001 step 73 001001001001001001001110001001 step 74 001001001001001001001101001001 step 75 001001001001001001001001001001 step 76 001001001001001001001001011001 step 77 001001001001001001001001110001 step 78 001001001001001001001001101001 step 79 001001001001001001001001001001 step 80 001001001001001001001001001011 step 81 001001001001001001001001001110 step 82 001001001001001001001001001101 step 83 001001001001001001001001001001 test 26: pass SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFDEFHJKHJKLMNLMNPRSPRSTUV SIDE 111111222111222111222111222222 DIRECTION IIOIIOIIOIIOIIOIIOIIOIIOIIOIIO this fail all fails was hi 111111111111111111111111111111 rising ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ falling vvvvvvvvvvvvvvvvvvvvvvvvvvvvvv was lo 000000000000000000000000000000 total fails 0, total passes 26 step 1 001001001001001001001001001001 step 2 110110110110110110110110110110 step 3 011110110110110110110110110110 step 4 001110110110110110110110110110 step 5 101110110110110110110110110110 step 6 110110110110110110110110110110 step 7 110011110110110110110110110110 step 8 110001110110110110110110110110 step 9 110101110110110110110110110110 step 10 110110110110110110110110110110 step 11 110110011110110110110110110110 step 12 110110001110110110110110110110 step 13 110110101110110110110110110110 step 14 110110110110110110110110110110 step 15 110110110011110110110110110110 step 16 110110110001110110110110110110 step 17 110110110101110110110110110110 step 18 110110110110110110110110110110 step 19 110110110110011110110110110110 step 20 110110110110001110110110110110 step 21 110110110110101110110110110110 step 22 110110110110110110110110110110 step 23 110110110110110011110110110110 step 24 110110110110110001110110110110 step 25 110110110110110101110110110110 step 26 110110110110110110110110110110 step 27 110110110110110110011110110110 step 28 110110110110110110001110110110 step 29 110110110110110110101110110110 step 30 110110110110110110110110110110 step 31 110110110110110110110011110110 step 32 110110110110110110110001110110 step 33 110110110110110110110101110110 step 34 110110110110110110110110110110 step 35 110110110110110110110110011110 step 36 110110110110110110110110001110 step 37 110110110110110110110110101110 step 38 110110110110110110110110110110 step 39 110110110110110110110110110011 step 40 110110110110110110110110110001 step 41 110110110110110110110110110101 step 42 110110110110110110110110110110 step 43 001001001001001001001001001001 step 44 011001001001001001001001001001 step 45 110001001001001001001001001001 step 46 101001001001001001001001001001 step 47 001001001001001001001001001001 step 48 001011001001001001001001001001 step 49 001110001001001001001001001001 step 50 001101001001001001001001001001 step 51 001001001001001001001001001001 step 52 001001011001001001001001001001 step 53 001001110001001001001001001001 step 54 001001101001001001001001001001 step 55 001001001001001001001001001001 step 56 001001001011001001001001001001 step 57 001001001110001001001001001001 step 58 001001001101001001001001001001 step 59 001001001001001001001001001001 step 60 001001001001011001001001001001 step 61 001001001001110001001001001001 step 62 001001001001101001001001001001 step 63 001001001001001001001001001001 step 64 001001001001001011001001001001 step 65 001001001001001110001001001001 step 66 001001001001001101001001001001 step 67 001001001001001001001001001001 step 68 001001001001001001011001001001 step 69 001001001001001001110001001001 step 70 001001001001001001101001001001 step 71 001001001001001001001001001001 step 72 001001001001001001001011001001 step 73 001001001001001001001110001001 step 74 001001001001001001001101001001 step 75 001001001001001001001001001001 step 76 001001001001001001001001011001 step 77 001001001001001001001001110001 step 78 001001001001001001001001101001 step 79 001001001001001001001001001001 step 80 001001001001001001001001001011 step 81 001001001001001001001001001110 step 82 001001001001001001001001001101 step 83 001001001001001001001001001001 test 27: pass SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFDEFHJKHJKLMNLMNPRSPRSTUV SIDE 111111222111222111222111222222 DIRECTION IIOIIOIIOIIOIIOIIOIIOIIOIIOIIO this fail all fails was hi 111111111111111111111111111111 rising ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ falling vvvvvvvvvvvvvvvvvvvvvvvvvvvvvv was lo 000000000000000000000000000000 total fails 0, total passes 27 step 1 001001001001001001001001001001 step 2 110110110110110110110110110110 step 3 011110110110110110110110110110 step 4 001110110110110110110110110110 step 5 101110110110110110110110110110 step 6 110110110110110110110110110110 step 7 110011110110110110110110110110 step 8 110001110110110110110110110110 step 9 110101110110110110110110110110 step 10 110110110110110110110110110110 step 11 110110011110110110110110110110 step 12 110110001110110110110110110110 step 13 110110101110110110110110110110 step 14 110110110110110110110110110110 step 15 110110110011110110110110110110 step 16 110110110001110110110110110110 step 17 110110110101110110110110110110 step 18 110110110110110110110110110110 step 19 110110110110011110110110110110 step 20 110110110110001110110110110110 step 21 110110110110101110110110110110 step 22 110110110110110110110110110110 step 23 110110110110110011110110110110 step 24 110110110110110001110110110110 step 25 110110110110110101110110110110 step 26 110110110110110110110110110110 step 27 110110110110110110011110110110 step 28 110110110110110110001110110110 step 29 110110110110110110101110110110 step 30 110110110110110110110110110110 step 31 110110110110110110110011110110 step 32 110110110110110110110001110110 step 33 110110110110110110110101110110 step 34 110110110110110110110110110110 step 35 110110110110110110110110011110 step 36 110110110110110110110110001110 step 37 110110110110110110110110101110 step 38 110110110110110110110110110110 step 39 110110110110110110110110110011 step 40 110110110110110110110110110001 step 41 110110110110110110110110110101 step 42 110110110110110110110110110110 step 43 001001001001001001001001001001 step 44 011001001001001001001001001001 step 45 110001001001001001001001001001 step 46 101001001001001001001001001001 step 47 001001001001001001001001001001 step 48 001011001001001001001001001001 step 49 001110001001001001001001001001 step 50 001101001001001001001001001001 step 51 001001001001001001001001001001 step 52 001001011001001001001001001001 step 53 001001110001001001001001001001 step 54 001001101001001001001001001001 step 55 001001001001001001001001001001 step 56 001001001011001001001001001001 step 57 001001001110001001001001001001 step 58 001001001101001001001001001001 step 59 001001001001001001001001001001 step 60 001001001001011001001001001001 step 61 001001001001110001001001001001 step 62 001001001001101001001001001001 step 63 001001001001001001001001001001 step 64 001001001001001011001001001001 step 65 001001001001001110001001001001 step 66 001001001001001101001001001001 step 67 001001001001001001001001001001 step 68 001001001001001001011001001001 step 69 001001001001001001110001001001 step 70 001001001001001001101001001001 step 71 001001001001001001001001001001 step 72 001001001001001001001011001001 step 73 001001001001001001001110001001 step 74 001001001001001001001101001001 step 75 001001001001001001001001001001 step 76 001001001001001001001001011001 step 77 001001001001001001001001110001 step 78 001001001001001001001001101001 step 79 001001001001001001001001001001 step 80 001001001001001001001001001011 step 81 001001001001001001001001001110 step 82 001001001001001001001001001101 step 83 001001001001001001001001001001 test 28: pass SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFDEFHJKHJKLMNLMNPRSPRSTUV SIDE 111111222111222111222111222222 DIRECTION IIOIIOIIOIIOIIOIIOIIOIIOIIOIIO this fail all fails was hi 111111111111111111111111111111 rising ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ falling vvvvvvvvvvvvvvvvvvvvvvvvvvvvvv was lo 000000000000000000000000000000 total fails 0, total passes 28 step 1 001001001001001001001001001001 step 2 110110110110110110110110110110 step 3 011110110110110110110110110110 step 4 001110110110110110110110110110 step 5 101110110110110110110110110110 step 6 110110110110110110110110110110 step 7 110011110110110110110110110110 step 8 110001110110110110110110110110 step 9 110101110110110110110110110110 step 10 110110110110110110110110110110 step 11 110110011110110110110110110110 step 12 110110001110110110110110110110 step 13 110110101110110110110110110110 step 14 110110110110110110110110110110 step 15 110110110011110110110110110110 step 16 110110110001110110110110110110 step 17 110110110101110110110110110110 step 18 110110110110110110110110110110 step 19 110110110110011110110110110110 step 20 110110110110001110110110110110 step 21 110110110110101110110110110110 step 22 110110110110110110110110110110 step 23 110110110110110011110110110110 step 24 110110110110110001110110110110 step 25 110110110110110101110110110110 step 26 110110110110110110110110110110 step 27 110110110110110110011110110110 step 28 110110110110110110001110110110 step 29 110110110110110110101110110110 step 30 110110110110110110110110110110 step 31 110110110110110110110011110110 step 32 110110110110110110110001110110 step 33 110110110110110110110101110110 step 34 110110110110110110110110110110 step 35 110110110110110110110110011110 step 36 110110110110110110110110001110 step 37 110110110110110110110110101110 step 38 110110110110110110110110110110 step 39 110110110110110110110110110011 step 40 110110110110110110110110110001 step 41 110110110110110110110110110101 step 42 110110110110110110110110110110 step 43 001001001001001001001001001001 step 44 011001001001001001001001001001 step 45 110001001001001001001001001001 step 46 101001001001001001001001001001 step 47 001001001001001001001001001001 step 48 001011001001001001001001001001 step 49 001110001001001001001001001001 step 50 001101001001001001001001001001 step 51 001001001001001001001001001001 step 52 001001011001001001001001001001 step 53 001001110001001001001001001001 step 54 001001101001001001001001001001 step 55 001001001001001001001001001001 step 56 001001001011001001001001001001 step 57 001001001110001001001001001001 step 58 001001001101001001001001001001 step 59 001001001001001001001001001001 step 60 001001001001011001001001001001 step 61 001001001001110001001001001001 step 62 001001001001101001001001001001 step 63 001001001001001001001001001001 step 64 001001001001001011001001001001 step 65 001001001001001110001001001001 step 66 001001001001001101001001001001 step 67 001001001001001001001001001001 step 68 001001001001001001011001001001 step 69 001001001001001001110001001001 step 70 001001001001001001101001001001 step 71 001001001001001001001001001001 step 72 001001001001001001001011001001 step 73 001001001001001001001110001001 step 74 001001001001001001001101001001 step 75 001001001001001001001001001001 step 76 001001001001001001001001011001 step 77 001001001001001001001001110001 step 78 001001001001001001001001101001 step 79 001001001001001001001001001001 step 80 001001001001001001001001001011 step 81 001001001001001001001001001110 step 82 001001001001001001001001001101 step 83 001001001001001001001001001001 test 29: pass SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFDEFHJKHJKLMNLMNPRSPRSTUV SIDE 111111222111222111222111222222 DIRECTION IIOIIOIIOIIOIIOIIOIIOIIOIIOIIO this fail all fails was hi 111111111111111111111111111111 rising ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ falling vvvvvvvvvvvvvvvvvvvvvvvvvvvvvv was lo 000000000000000000000000000000 total fails 0, total passes 29 step 1 001001001001001001001001001001 step 2 110110110110110110110110110110 step 3 011110110110110110110110110110 step 4 001110110110110110110110110110 step 5 101110110110110110110110110110 step 6 110110110110110110110110110110 step 7 110011110110110110110110110110 step 8 110001110110110110110110110110 step 9 110101110110110110110110110110 step 10 110110110110110110110110110110 step 11 110110011110110110110110110110 step 12 110110001110110110110110110110 step 13 110110101110110110110110110110 step 14 110110110110110110110110110110 step 15 110110110011110110110110110110 step 16 110110110001110110110110110110 step 17 110110110101110110110110110110 step 18 110110110110110110110110110110 step 19 110110110110011110110110110110 step 20 110110110110001110110110110110 step 21 110110110110101110110110110110 step 22 110110110110110110110110110110 step 23 110110110110110011110110110110 step 24 110110110110110001110110110110 step 25 110110110110110101110110110110 step 26 110110110110110110110110110110 step 27 110110110110110110011110110110 step 28 110110110110110110001110110110 step 29 110110110110110110101110110110 step 30 110110110110110110110110110110 step 31 110110110110110110110011110110 step 32 110110110110110110110001110110 step 33 110110110110110110110101110110 step 34 110110110110110110110110110110 step 35 110110110110110110110110011110 step 36 110110110110110110110110001110 step 37 110110110110110110110110101110 step 38 110110110110110110110110110110 step 39 110110110110110110110110110011 step 40 110110110110110110110110110001 step 41 110110110110110110110110110101 step 42 110110110110110110110110110110 step 43 001001001001001001001001001001 step 44 011001001001001001001001001001 step 45 110001001001001001001001001001 step 46 101001001001001001001001001001 step 47 001001001001001001001001001001 step 48 001011001001001001001001001001 step 49 001110001001001001001001001001 step 50 001101001001001001001001001001 step 51 001001001001001001001001001001 step 52 001001011001001001001001001001 step 53 001001110001001001001001001001 step 54 001001101001001001001001001001 step 55 001001001001001001001001001001 step 56 001001001011001001001001001001 step 57 001001001110001001001001001001 step 58 001001001101001001001001001001 step 59 001001001001001001001001001001 step 60 001001001001011001001001001001 step 61 001001001001110001001001001001 step 62 001001001001101001001001001001 step 63 001001001001001001001001001001 step 64 001001001001001011001001001001 step 65 001001001001001110001001001001 step 66 001001001001001101001001001001 step 67 001001001001001001001001001001 step 68 001001001001001001011001001001 step 69 001001001001001001110001001001 step 70 001001001001001001101001001001 step 71 001001001001001001001001001001 step 72 001001001001001001001011001001 step 73 001001001001001001001110001001 step 74 001001001001001001001101001001 step 75 001001001001001001001001001001 step 76 001001001001001001001001011001 step 77 001001001001001001001001110001 step 78 001001001001001001001001101001 step 79 001001001001001001001001001001 step 80 001001001001001001001001001011 step 81 001001001001001001001001001110 step 82 001001001001001001001001001101 step 83 001001001001001001001001001001 test 30: pass SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFDEFHJKHJKLMNLMNPRSPRSTUV SIDE 111111222111222111222111222222 DIRECTION IIOIIOIIOIIOIIOIIOIIOIIOIIOIIO this fail all fails was hi 111111111111111111111111111111 rising ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ falling vvvvvvvvvvvvvvvvvvvvvvvvvvvvvv was lo 000000000000000000000000000000 total fails 0, total passes 30 step 1 001001001001001001001001001001 step 2 110110110110110110110110110110 step 3 011110110110110110110110110110 step 4 001110110110110110110110110110 step 5 101110110110110110110110110110 step 6 110110110110110110110110110110 step 7 110011110110110110110110110110 step 8 110001110110110110110110110110 step 9 110101110110110110110110110110 step 10 110110110110110110110110110110 step 11 110110011110110110110110110110 step 12 110110001110110110110110110110 step 13 110110101110110110110110110110 step 14 110110110110110110110110110110 step 15 110110110011110110110110110110 step 16 110110110001110110110110110110 step 17 110110110101110110110110110110 step 18 110110110110110110110110110110 step 19 110110110110011110110110110110 step 20 110110110110001110110110110110 step 21 110110110110101110110110110110 step 22 110110110110110110110110110110 step 23 110110110110110011110110110110 step 24 110110110110110001110110110110 step 25 110110110110110101110110110110 step 26 110110110110110110110110110110 step 27 110110110110110110011110110110 step 28 110110110110110110001110110110 step 29 110110110110110110101110110110 step 30 110110110110110110110110110110 step 31 110110110110110110110011110110 step 32 110110110110110110110001110110 step 33 110110110110110110110101110110 step 34 110110110110110110110110110110 step 35 110110110110110110110110011110 step 36 110110110110110110110110001110 step 37 110110110110110110110110101110 step 38 110110110110110110110110110110 step 39 110110110110110110110110110011 step 40 110110110110110110110110110001 step 41 110110110110110110110110110101 step 42 110110110110110110110110110110 step 43 001001001001001001001001001001 step 44 011001001001001001001001001001 step 45 110001001001001001001001001001 step 46 101001001001001001001001001001 step 47 001001001001001001001001001001 step 48 001011001001001001001001001001 step 49 001110001001001001001001001001 step 50 001101001001001001001001001001 step 51 001001001001001001001001001001 step 52 001001011001001001001001001001 step 53 001001110001001001001001001001 step 54 001001101001001001001001001001 step 55 001001001001001001001001001001 step 56 001001001011001001001001001001 step 57 001001001110001001001001001001 step 58 001001001101001001001001001001 step 59 001001001001001001001001001001 step 60 001001001001011001001001001001 step 61 001001001001110001001001001001 step 62 001001001001101001001001001001 step 63 001001001001001001001001001001 step 64 001001001001001011001001001001 step 65 001001001001001110001001001001 step 66 001001001001001101001001001001 step 67 001001001001001001001001001001 step 68 001001001001001001011001001001 step 69 001001001001001001110001001001 step 70 001001001001001001101001001001 step 71 001001001001001001001001001001 step 72 001001001001001001001011001001 step 73 001001001001001001001110001001 step 74 001001001001001001001101001001 step 75 001001001001001001001001001001 step 76 001001001001001001001001011001 step 77 001001001001001001001001110001 step 78 001001001001001001001001101001 step 79 001001001001001001001001001001 step 80 001001001001001001001001001011 step 81 001001001001001001001001001110 step 82 001001001001001001001001001101 step 83 001001001001001001001001001001 test 31: pass SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFDEFHJKHJKLMNLMNPRSPRSTUV SIDE 111111222111222111222111222222 DIRECTION IIOIIOIIOIIOIIOIIOIIOIIOIIOIIO this fail all fails was hi 111111111111111111111111111111 rising ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ falling vvvvvvvvvvvvvvvvvvvvvvvvvvvvvv was lo 000000000000000000000000000000 total fails 0, total passes 31 step 1 001001001001001001001001001001 step 2 110110110110110110110110110110 step 3 011110110110110110110110110110 step 4 001110110110110110110110110110 step 5 101110110110110110110110110110 step 6 110110110110110110110110110110 step 7 110011110110110110110110110110 step 8 110001110110110110110110110110 step 9 110101110110110110110110110110 step 10 110110110110110110110110110110 step 11 110110011110110110110110110110 step 12 110110001110110110110110110110 step 13 110110101110110110110110110110 step 14 110110110110110110110110110110 step 15 110110110011110110110110110110 step 16 110110110001110110110110110110 step 17 110110110101110110110110110110 step 18 110110110110110110110110110110 step 19 110110110110011110110110110110 step 20 110110110110001110110110110110 step 21 110110110110101110110110110110 step 22 110110110110110110110110110110 step 23 110110110110110011110110110110 step 24 110110110110110001110110110110 step 25 110110110110110101110110110110 step 26 110110110110110110110110110110 step 27 110110110110110110011110110110 step 28 110110110110110110001110110110 step 29 110110110110110110101110110110 step 30 110110110110110110110110110110 step 31 110110110110110110110011110110 step 32 110110110110110110110001110110 step 33 110110110110110110110101110110 step 34 110110110110110110110110110110 step 35 110110110110110110110110011110 step 36 110110110110110110110110001110 step 37 110110110110110110110110101110 step 38 110110110110110110110110110110 step 39 110110110110110110110110110011 step 40 110110110110110110110110110001 step 41 110110110110110110110110110101 step 42 110110110110110110110110110110 step 43 001001001001001001001001001001 step 44 011001001001001001001001001001 step 45 110001001001001001001001001001 step 46 101001001001001001001001001001 step 47 001001001001001001001001001001 step 48 001011001001001001001001001001 step 49 001110001001001001001001001001 step 50 001101001001001001001001001001 step 51 001001001001001001001001001001 step 52 001001011001001001001001001001 step 53 001001110001001001001001001001 step 54 001001101001001001001001001001 step 55 001001001001001001001001001001 step 56 001001001011001001001001001001 step 57 001001001110001001001001001001 step 58 001001001101001001001001001001 step 59 001001001001001001001001001001 step 60 001001001001011001001001001001 step 61 001001001001110001001001001001 step 62 001001001001101001001001001001 step 63 001001001001001001001001001001 step 64 001001001001001011001001001001 step 65 001001001001001110001001001001 step 66 001001001001001101001001001001 step 67 001001001001001001001001001001 step 68 001001001001001001011001001001 step 69 001001001001001001110001001001 step 70 001001001001001001101001001001 step 71 001001001001001001001001001001 step 72 001001001001001001001011001001 step 73 001001001001001001001110001001 step 74 001001001001001001001101001001 step 75 001001001001001001001001001001 step 76 001001001001001001001001011001 step 77 001001001001001001001001110001 step 78 001001001001001001001001101001 step 79 001001001001001001001001001001 step 80 001001001001001001001001001011 step 81 001001001001001001001001001110 step 82 001001001001001001001001001101 step 83 001001001001001001001001001001 test 32: pass SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFDEFHJKHJKLMNLMNPRSPRSTUV SIDE 111111222111222111222111222222 DIRECTION IIOIIOIIOIIOIIOIIOIIOIIOIIOIIO this fail all fails was hi 111111111111111111111111111111 rising ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ falling vvvvvvvvvvvvvvvvvvvvvvvvvvvvvv was lo 000000000000000000000000000000 total fails 0, total passes 32 step 1 001001001001001001001001001001 step 2 110110110110110110110110110110 step 3 011110110110110110110110110110 step 4 001110110110110110110110110110 step 5 101110110110110110110110110110 step 6 110110110110110110110110110110 step 7 110011110110110110110110110110 step 8 110001110110110110110110110110 step 9 110101110110110110110110110110 step 10 110110110110110110110110110110 step 11 110110011110110110110110110110 step 12 110110001110110110110110110110 step 13 110110101110110110110110110110 step 14 110110110110110110110110110110 step 15 110110110011110110110110110110 step 16 110110110001110110110110110110 step 17 110110110101110110110110110110 step 18 110110110110110110110110110110 step 19 110110110110011110110110110110 step 20 110110110110001110110110110110 step 21 110110110110101110110110110110 step 22 110110110110110110110110110110 step 23 110110110110110011110110110110 step 24 110110110110110001110110110110 step 25 110110110110110101110110110110 step 26 110110110110110110110110110110 step 27 110110110110110110011110110110 step 28 110110110110110110001110110110 step 29 110110110110110110101110110110 step 30 110110110110110110110110110110 step 31 110110110110110110110011110110 step 32 110110110110110110110001110110 step 33 110110110110110110110101110110 step 34 110110110110110110110110110110 step 35 110110110110110110110110011110 step 36 110110110110110110110110001110 step 37 110110110110110110110110101110 step 38 110110110110110110110110110110 step 39 110110110110110110110110110011 step 40 110110110110110110110110110001 step 41 110110110110110110110110110101 step 42 110110110110110110110110110110 step 43 001001001001001001001001001001 step 44 011001001001001001001001001001 step 45 110001001001001001001001001001 step 46 101001001001001001001001001001 step 47 001001001001001001001001001001 step 48 001011001001001001001001001001 step 49 001110001001001001001001001001 step 50 001101001001001001001001001001 step 51 001001001001001001001001001001 step 52 001001011001001001001001001001 step 53 001001110001001001001001001001 step 54 001001101001001001001001001001 step 55 001001001001001001001001001001 step 56 001001001011001001001001001001 step 57 001001001110001001001001001001 step 58 001001001101001001001001001001 step 59 001001001001001001001001001001 step 60 001001001001011001001001001001 step 61 001001001001110001001001001001 step 62 001001001001101001001001001001 step 63 001001001001001001001001001001 step 64 001001001001001011001001001001 step 65 001001001001001110001001001001 step 66 001001001001001101001001001001 step 67 001001001001001001001001001001 step 68 001001001001001001011001001001 step 69 001001001001001001110001001001 step 70 001001001001001001101001001001 step 71 001001001001001001001001001001 step 72 001001001001001001001011001001 step 73 001001001001001001001110001001 step 74 001001001001001001001101001001 step 75 001001001001001001001001001001 step 76 001001001001001001001001011001 step 77 001001001001001001001001110001 step 78 001001001001001001001001101001 step 79 001001001001001001001001001001 step 80 001001001001001001001001001011 step 81 001001001001001001001001001110 step 82 001001001001001001001001001101 step 83 001001001001001001001001001001 test 33: pass SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFDEFHJKHJKLMNLMNPRSPRSTUV SIDE 111111222111222111222111222222 DIRECTION IIOIIOIIOIIOIIOIIOIIOIIOIIOIIO this fail all fails was hi 111111111111111111111111111111 rising ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ falling vvvvvvvvvvvvvvvvvvvvvvvvvvvvvv was lo 000000000000000000000000000000 total fails 0, total passes 33 step 1 001001001001001001001001001001 step 2 110110110110110110110110110110 step 3 011110110110110110110110110110 step 4 001110110110110110110110110110 step 5 101110110110110110110110110110 step 6 110110110110110110110110110110 step 7 110011110110110110110110110110 step 8 110001110110110110110110110110 step 9 110101110110110110110110110110 step 10 110110110110110110110110110110 step 11 110110011110110110110110110110 step 12 110110001110110110110110110110 step 13 110110101110110110110110110110 step 14 110110110110110110110110110110 step 15 110110110011110110110110110110 step 16 110110110001110110110110110110 step 17 110110110101110110110110110110 step 18 110110110110110110110110110110 step 19 110110110110011110110110110110 step 20 110110110110001110110110110110 step 21 110110110110101110110110110110 step 22 110110110110110110110110110110 step 23 110110110110110011110110110110 step 24 110110110110110001110110110110 step 25 110110110110110101110110110110 step 26 110110110110110110110110110110 step 27 110110110110110110011110110110 step 28 110110110110110110001110110110 step 29 110110110110110110101110110110 step 30 110110110110110110110110110110 step 31 110110110110110110110011110110 step 32 110110110110110110110001110110 step 33 110110110110110110110101110110 step 34 110110110110110110110110110110 step 35 110110110110110110110110011110 step 36 110110110110110110110110001110 step 37 110110110110110110110110101110 step 38 110110110110110110110110110110 step 39 110110110110110110110110110011 step 40 110110110110110110110110110001 step 41 110110110110110110110110110101 step 42 110110110110110110110110110110 step 43 001001001001001001001001001001 step 44 011001001001001001001001001001 step 45 110001001001001001001001001001 step 46 101001001001001001001001001001 step 47 001001001001001001001001001001 step 48 001011001001001001001001001001 step 49 001110001001001001001001001001 step 50 001101001001001001001001001001 step 51 001001001001001001001001001001 step 52 001001011001001001001001001001 step 53 001001110001001001001001001001 step 54 001001101001001001001001001001 step 55 001001001001001001001001001001 step 56 001001001011001001001001001001 step 57 001001001110001001001001001001 step 58 001001001101001001001001001001 step 59 001001001001001001001001001001 step 60 001001001001011001001001001001 step 61 001001001001110001001001001001 step 62 001001001001101001001001001001 step 63 001001001001001001001001001001 step 64 001001001001001011001001001001 step 65 001001001001001110001001001001 step 66 001001001001001101001001001001 step 67 001001001001001001001001001001 step 68 001001001001001001011001001001 step 69 001001001001001001110001001001 step 70 001001001001001001101001001001 step 71 001001001001001001001001001001 step 72 001001001001001001001011001001 step 73 001001001001001001001110001001 step 74 001001001001001001001101001001 step 75 001001001001001001001001001001 step 76 001001001001001001001001011001 step 77 001001001001001001001001110001 step 78 001001001001001001001001101001 step 79 001001001001001001001001001001 step 80 001001001001001001001001001011 step 81 001001001001001001001001001110 step 82 001001001001001001001001001101 step 83 001001001001001001001001001001 test 34: pass SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFDEFHJKHJKLMNLMNPRSPRSTUV SIDE 111111222111222111222111222222 DIRECTION IIOIIOIIOIIOIIOIIOIIOIIOIIOIIO this fail all fails was hi 111111111111111111111111111111 rising ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ falling vvvvvvvvvvvvvvvvvvvvvvvvvvvvvv was lo 000000000000000000000000000000 total fails 0, total passes 34 step 1 001001001001001001001001001001 step 2 110110110110110110110110110110 step 3 011110110110110110110110110110 step 4 001110110110110110110110110110 step 5 101110110110110110110110110110 step 6 110110110110110110110110110110 step 7 110011110110110110110110110110 step 8 110001110110110110110110110110 step 9 110101110110110110110110110110 step 10 110110110110110110110110110110 step 11 110110011110110110110110110110 step 12 110110001110110110110110110110 step 13 110110101110110110110110110110 step 14 110110110110110110110110110110 step 15 110110110011110110110110110110 step 16 110110110001110110110110110110 step 17 110110110101110110110110110110 step 18 110110110110110110110110110110 step 19 110110110110011110110110110110 step 20 110110110110001110110110110110 step 21 110110110110101110110110110110 step 22 110110110110110110110110110110 space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C toggle comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit scope (run, no print) ppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppp ppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppp ppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppp ppppppppppppp space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C toggle comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFDEFHJKHJKLMNLMNPRSPRSTUV SIDE 111111222111222111222111222222 DIRECTION IIOIIOIIOIIOIIOIIOIIOIIOIIOIIO all fails was lo 000000000000000000000000000000 falling vvvvvvvvvvvvvvvvvvvvvvvvvvvvvv rising ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ was hi 111111111111111111111111111111 total fails 0, total passes 284 Main menu Mon Jul 27 14:48:22 2015 test file is: tests\m113.tst delay is: 0 trigger is: 1 1 read test file 2 set test delay 3 set test trigger 4 run test 5 output loading test 8 diags 9 exit Enter test file name? trying to open test file: tests\m115.tst reading test file: tests\m115.tst comment: M115 REV C 8 3-input NAND comment: pins: PINS pins: 1 I AA1 E1-11 pins: 2 I AB1 E1-10 pins: 3 I AC1 E1-9 pins: 4 O AD1 E1-8 pins: 5 I AD2 E1-2 pins: 6 I AE2 E1-1 pins: 7 I AF2 E1-13 pins: 8 O AH2 E1-12 pins: 9 I AE1 E1-3 pins: 10 I AF1 E1-4 pins: 11 I AH1 E1-5 pins: 12 O AJ1 E1-6 pins: 13 I AJ2 E3-11 pins: 14 I AK2 E3-10 pins: 15 I AL2 E3-9 pins: 16 O AM2 E3-8 pins: 17 I AK1 E2-1 pins: 18 I AL1 E2-2 pins: 19 I AM1 E2-13 pins: 20 O AN1 E2-12 pins: 21 I AN2 E2-11 pins: 22 I AP2 E2-10 pins: 23 I AR2 E2-9 pins: 24 O AS2 E2-8 pins: 25 I AP1 E2-3 pins: 26 I AR1 E2-4 pins: 27 I AS1 E2-5 pins: 28 O AU1 E2-6 pins: 29 I AT2 E3-5 pins: 30 I AU2 E3-4 pins: 31 I AV2 E3-3 pins: 32 O AV1 E3-6 pins: direction: IIIOIIIOIIIOIIIOIIIOIIIOIIIOIIIO test 1: 00010001000100010001000100010001 test 2: 0001 test 3: 0011 test 4: 0101 test 5: 0111 test 6: 1001 test 7: 1011 test 8: 1101 test 9: 1110 test 10: 0001 test 11: 0001 test 12: 0011 test 13: 0101 test 14: 0111 test 15: 1001 test 16: 1011 test 17: 1101 test 18: 1110 test 19: 0001 test 20: 0001 test 21: 0011 test 22: 0101 test 23: 0111 test 24: 1001 test 25: 1011 test 26: 1101 test 27: 1110 test 28: 0001 test 29: 0001 test 30: 0011 test 31: 0101 test 32: 0111 test 33: 1001 test 34: 1011 test 35: 1101 test 36: 1110 test 37: 0001 test 38: 0001 test 39: 0011 test 40: 0101 test 41: 0111 test 42: 1001 test 43: 1011 test 44: 1101 test 45: 1110 test 46: 0001 test 47: 0001 test 48: 0011 test 49: 0101 test 50: 0111 test 51: 1001 test 52: 1011 test 53: 1101 test 54: 1110 test 55: 0001 test 56: 0001 test 57: 0011 test 58: 0101 test 59: 0111 test 60: 1001 test 61: 1011 test 62: 1101 test 63: 1110 test 64: 0001 test 65: 0001 test 66: 0011 test 67: 0101 test 68: 0111 test 69: 1001 test 70: 1011 test 71: 1101 test 72: 1110 test 73: 0001 test 74: 00010001000100010001000100010001 test 75: 11101110111011101110111011101110 test 76: 0001 test 77: 0011 test 78: 0101 test 79: 0111 test 80: 1001 test 81: 1011 test 82: 1101 test 83: 1110 test 84: 0001 test 85: 0011 test 86: 0101 test 87: 0111 test 88: 1001 test 89: 1011 test 90: 1101 test 91: 1110 test 92: 0001 test 93: 0011 test 94: 0101 test 95: 0111 test 96: 1001 test 97: 1011 test 98: 1101 test 99: 1110 test 100: 0001 test 101: 0011 test 102: 0101 test 103: 0111 test 104: 1001 test 105: 1011 test 106: 1101 test 107: 1110 test 108: 0001 test 109: 0011 test 110: 0101 test 111: 0111 test 112: 1001 test 113: 1011 test 114: 1101 test 115: 1110 test 116: 0001 test 117: 0011 test 118: 0101 test 119: 0111 test 120: 1001 test 121: 1011 test 122: 1101 test 123: 1110 test 124: 0001 test 125: 0011 test 126: 0101 test 127: 0111 test 128: 1001 test 129: 1011 test 130: 1101 test 131: 1110 test 132: 0001 test 133: 0011 test 134: 0101 test 135: 0111 test 136: 1001 test 137: 1011 test 138: 1101 test 139: 1110 test 140: 11101110111011101110111011101110 end: END summary column 1: offset 0, mask 0x8000 column 2: offset 0, mask 0x4000 column 3: offset 0, mask 0x2000 column 4: offset 0, mask 0x1000 column 5: offset 0, mask 0x0010 column 6: offset 0, mask 0x0008 column 7: offset 0, mask 0x0004 column 8: offset 0, mask 0x0002 column 9: offset 0, mask 0x0800 column 10: offset 0, mask 0x0400 column 11: offset 0, mask 0x0200 column 12: offset 0, mask 0x0100 column 13: offset 0, mask 0x0001 column 14: offset 1, mask 0x0001 column 15: offset 1, mask 0x0002 column 16: offset 1, mask 0x0004 column 17: offset 1, mask 0x8000 column 18: offset 1, mask 0x4000 column 19: offset 1, mask 0x2000 column 20: offset 1, mask 0x1000 column 21: offset 1, mask 0x0008 column 22: offset 1, mask 0x0010 column 23: offset 1, mask 0x0020 column 24: offset 1, mask 0x0040 column 25: offset 1, mask 0x0800 column 26: offset 1, mask 0x0400 column 27: offset 1, mask 0x0200 column 28: offset 2, mask 0x8000 column 29: offset 1, mask 0x0080 column 30: offset 2, mask 0x0001 column 31: offset 2, mask 0x0002 column 32: offset 2, mask 0x4000 direction bits (1=input) 0x11E2 0x1144 0xFFF8 0xFFFF 0xF0FF pullup bits (1=pullup) 0x0000 0x0000 0x0000 0x0000 0x0000 test step out_data dont care 1: 0x1102 0x1044 0xC000 0x0000 0x0000 2: 0x1102 0x1044 0xC000 0x0000 0x0000 3: 0x3102 0x1044 0xC000 0x0000 0x0000 4: 0x5102 0x1044 0xC000 0x0000 0x0000 5: 0x7102 0x1044 0xC000 0x0000 0x0000 6: 0x9102 0x1044 0xC000 0x0000 0x0000 7: 0xB102 0x1044 0xC000 0x0000 0x0000 8: 0xD102 0x1044 0xC000 0x0000 0x0000 9: 0xE102 0x1044 0xC000 0x0000 0x0000 10: 0x1102 0x1044 0xC000 0x0000 0x0000 11: 0x1102 0x1044 0xC000 0x0000 0x0000 12: 0x1106 0x1044 0xC000 0x0000 0x0000 13: 0x110A 0x1044 0xC000 0x0000 0x0000 14: 0x110E 0x1044 0xC000 0x0000 0x0000 15: 0x1112 0x1044 0xC000 0x0000 0x0000 16: 0x1116 0x1044 0xC000 0x0000 0x0000 17: 0x111A 0x1044 0xC000 0x0000 0x0000 18: 0x111C 0x1044 0xC000 0x0000 0x0000 19: 0x1102 0x1044 0xC000 0x0000 0x0000 20: 0x1102 0x1044 0xC000 0x0000 0x0000 21: 0x1302 0x1044 0xC000 0x0000 0x0000 22: 0x1502 0x1044 0xC000 0x0000 0x0000 23: 0x1702 0x1044 0xC000 0x0000 0x0000 24: 0x1902 0x1044 0xC000 0x0000 0x0000 25: 0x1B02 0x1044 0xC000 0x0000 0x0000 26: 0x1D02 0x1044 0xC000 0x0000 0x0000 27: 0x1E02 0x1044 0xC000 0x0000 0x0000 28: 0x1102 0x1044 0xC000 0x0000 0x0000 29: 0x1102 0x1044 0xC000 0x0000 0x0000 30: 0x1102 0x1046 0xC000 0x0000 0x0000 31: 0x1102 0x1045 0xC000 0x0000 0x0000 32: 0x1102 0x1047 0xC000 0x0000 0x0000 33: 0x1103 0x1044 0xC000 0x0000 0x0000 34: 0x1103 0x1046 0xC000 0x0000 0x0000 35: 0x1103 0x1045 0xC000 0x0000 0x0000 36: 0x1103 0x1043 0xC000 0x0000 0x0000 37: 0x1102 0x1044 0xC000 0x0000 0x0000 38: 0x1102 0x1044 0xC000 0x0000 0x0000 39: 0x1102 0x3044 0xC000 0x0000 0x0000 40: 0x1102 0x5044 0xC000 0x0000 0x0000 41: 0x1102 0x7044 0xC000 0x0000 0x0000 42: 0x1102 0x9044 0xC000 0x0000 0x0000 43: 0x1102 0xB044 0xC000 0x0000 0x0000 44: 0x1102 0xD044 0xC000 0x0000 0x0000 45: 0x1102 0xE044 0xC000 0x0000 0x0000 46: 0x1102 0x1044 0xC000 0x0000 0x0000 47: 0x1102 0x1044 0xC000 0x0000 0x0000 48: 0x1102 0x1064 0xC000 0x0000 0x0000 49: 0x1102 0x1054 0xC000 0x0000 0x0000 50: 0x1102 0x1074 0xC000 0x0000 0x0000 51: 0x1102 0x104C 0xC000 0x0000 0x0000 52: 0x1102 0x106C 0xC000 0x0000 0x0000 53: 0x1102 0x105C 0xC000 0x0000 0x0000 54: 0x1102 0x103C 0xC000 0x0000 0x0000 55: 0x1102 0x1044 0xC000 0x0000 0x0000 56: 0x1102 0x1044 0xC000 0x0000 0x0000 57: 0x1102 0x1244 0xC000 0x0000 0x0000 58: 0x1102 0x1444 0xC000 0x0000 0x0000 59: 0x1102 0x1644 0xC000 0x0000 0x0000 60: 0x1102 0x1844 0xC000 0x0000 0x0000 61: 0x1102 0x1A44 0xC000 0x0000 0x0000 62: 0x1102 0x1C44 0xC000 0x0000 0x0000 63: 0x1102 0x1E44 0x4000 0x0000 0x0000 64: 0x1102 0x1044 0xC000 0x0000 0x0000 65: 0x1102 0x1044 0xC000 0x0000 0x0000 66: 0x1102 0x1044 0xC002 0x0000 0x0000 67: 0x1102 0x1044 0xC001 0x0000 0x0000 68: 0x1102 0x1044 0xC003 0x0000 0x0000 69: 0x1102 0x10C4 0xC000 0x0000 0x0000 70: 0x1102 0x10C4 0xC002 0x0000 0x0000 71: 0x1102 0x10C4 0xC001 0x0000 0x0000 72: 0x1102 0x10C4 0x8003 0x0000 0x0000 73: 0x1102 0x1044 0xC000 0x0000 0x0000 74: 0x1102 0x1044 0xC000 0x0000 0x0000 75: 0xEE1D 0xEEBB 0x0003 0x0000 0x0000 76: 0x1E1D 0xEEBB 0x0003 0x0000 0x0000 77: 0x3E1D 0xEEBB 0x0003 0x0000 0x0000 78: 0x5E1D 0xEEBB 0x0003 0x0000 0x0000 79: 0x7E1D 0xEEBB 0x0003 0x0000 0x0000 80: 0x9E1D 0xEEBB 0x0003 0x0000 0x0000 81: 0xBE1D 0xEEBB 0x0003 0x0000 0x0000 82: 0xDE1D 0xEEBB 0x0003 0x0000 0x0000 83: 0xEE1D 0xEEBB 0x0003 0x0000 0x0000 84: 0xEE03 0xEEBB 0x0003 0x0000 0x0000 85: 0xEE07 0xEEBB 0x0003 0x0000 0x0000 86: 0xEE0B 0xEEBB 0x0003 0x0000 0x0000 87: 0xEE0F 0xEEBB 0x0003 0x0000 0x0000 88: 0xEE13 0xEEBB 0x0003 0x0000 0x0000 89: 0xEE17 0xEEBB 0x0003 0x0000 0x0000 90: 0xEE1B 0xEEBB 0x0003 0x0000 0x0000 91: 0xEE1D 0xEEBB 0x0003 0x0000 0x0000 92: 0xE11D 0xEEBB 0x0003 0x0000 0x0000 93: 0xE31D 0xEEBB 0x0003 0x0000 0x0000 94: 0xE51D 0xEEBB 0x0003 0x0000 0x0000 95: 0xE71D 0xEEBB 0x0003 0x0000 0x0000 96: 0xE91D 0xEEBB 0x0003 0x0000 0x0000 97: 0xEB1D 0xEEBB 0x0003 0x0000 0x0000 98: 0xED1D 0xEEBB 0x0003 0x0000 0x0000 99: 0xEE1D 0xEEBB 0x0003 0x0000 0x0000 100: 0xEE1C 0xEEBC 0x0003 0x0000 0x0000 101: 0xEE1C 0xEEBE 0x0003 0x0000 0x0000 102: 0xEE1C 0xEEBD 0x0003 0x0000 0x0000 103: 0xEE1C 0xEEBF 0x0003 0x0000 0x0000 104: 0xEE1D 0xEEBC 0x0003 0x0000 0x0000 105: 0xEE1D 0xEEBE 0x0003 0x0000 0x0000 106: 0xEE1D 0xEEBD 0x0003 0x0000 0x0000 107: 0xEE1D 0xEEBB 0x0003 0x0000 0x0000 108: 0xEE1D 0x1EBB 0x0003 0x0000 0x0000 109: 0xEE1D 0x3EBB 0x0003 0x0000 0x0000 110: 0xEE1D 0x5EBB 0x0003 0x0000 0x0000 111: 0xEE1D 0x7EBB 0x0003 0x0000 0x0000 112: 0xEE1D 0x9EBB 0x0003 0x0000 0x0000 113: 0xEE1D 0xBEBB 0x0003 0x0000 0x0000 114: 0xEE1D 0xDEBB 0x0003 0x0000 0x0000 115: 0xEE1D 0xEEBB 0x0003 0x0000 0x0000 116: 0xEE1D 0xEEC3 0x0003 0x0000 0x0000 117: 0xEE1D 0xEEE3 0x0003 0x0000 0x0000 118: 0xEE1D 0xEED3 0x0003 0x0000 0x0000 119: 0xEE1D 0xEEF3 0x0003 0x0000 0x0000 120: 0xEE1D 0xEECB 0x0003 0x0000 0x0000 121: 0xEE1D 0xEEEB 0x0003 0x0000 0x0000 122: 0xEE1D 0xEEDB 0x0003 0x0000 0x0000 123: 0xEE1D 0xEEBB 0x0003 0x0000 0x0000 124: 0xEE1D 0xE0BB 0x8003 0x0000 0x0000 125: 0xEE1D 0xE2BB 0x8003 0x0000 0x0000 126: 0xEE1D 0xE4BB 0x8003 0x0000 0x0000 127: 0xEE1D 0xE6BB 0x8003 0x0000 0x0000 128: 0xEE1D 0xE8BB 0x8003 0x0000 0x0000 129: 0xEE1D 0xEABB 0x8003 0x0000 0x0000 130: 0xEE1D 0xECBB 0x8003 0x0000 0x0000 131: 0xEE1D 0xEEBB 0x0003 0x0000 0x0000 132: 0xEE1D 0xEE3B 0x4000 0x0000 0x0000 133: 0xEE1D 0xEE3B 0x4002 0x0000 0x0000 134: 0xEE1D 0xEE3B 0x4001 0x0000 0x0000 135: 0xEE1D 0xEE3B 0x4003 0x0000 0x0000 136: 0xEE1D 0xEEBB 0x4000 0x0000 0x0000 137: 0xEE1D 0xEEBB 0x4002 0x0000 0x0000 138: 0xEE1D 0xEEBB 0x4001 0x0000 0x0000 139: 0xEE1D 0xEEBB 0x0003 0x0000 0x0000 140: 0xEE1D 0xEEBB 0x0003 0x0000 0x0000 PINs used (in edge connector order) (G=ground,P=power) SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBB LETTER ABCDEFHJKLMNPRSTUVABCDEFHJKLMNPRSTUVABCDEFHJKLMNPRSTUVABCDEFHJKLMNPRSTUV SIDE 111111111111111111222222222222222222111111111111111111222222222222222222 USAGE IIIOIIIOIIIOIIIGOOP GIIIOIIIOIIIOIII G P G UUT has 24 inputs UUT has 8 outputs contains 32 pins/columns 34 pins are not used contains 140 'test steps' M115 REV C 8 3-input NAND PINS Main menu Mon Jul 27 14:49:41 2015 test file is: tests\m115.tst delay is: 0 trigger is: 1 1 read test file 2 set test delay 3 set test trigger 4 run test 5 output loading test 8 diags 9 exit UUT power is okay Mon Jul 27 14:50:07 2015 space single step O run once (one test, all steps) F run, stop on fail G go (run tests N run, stop on fail, no print S scope (run, no print) C toggle comment printout + increase speed (less delay) - decrease speed (more delay)(slower) Q quit test scope (run, no print) ppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppp p space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C toggle comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDDEFHEFHJJKLMKLMNNPRSPRSUTUVV SIDE 11112222111122221111222211112221 DIRECTION IIIOIIIOIIIOIIIOIIIOIIIOIIIOIIIO all fails was lo 00000000000000000000000000000000 falling vvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvv rising ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ was hi 11111111111111111111111111111111 total fails 0, total passes 80 Main menu Mon Jul 27 14:50:14 2015 test file is: tests\m115.tst delay is: 0 trigger is: 1 1 read test file 2 set test delay 3 set test trigger 4 run test 5 output loading test 8 diags 9 exit UUT power is okay Mon Jul 27 14:51:31 2015 space single step O run once (one test, all steps) F run, stop on fail G go (run tests N run, stop on fail, no print S scope (run, no print) C toggle comment printout + increase speed (less delay) - decrease speed (more delay)(slower) Q quit test scope (run, no print) ppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppp space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C toggle comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDDEFHEFHJJKLMKLMNNPRSPRSUTUVV SIDE 11112222111122221111222211112221 DIRECTION IIIOIIIOIIIOIIIOIIIOIIIOIIIOIIIO all fails was lo 00000000000000000000000000000000 falling vvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvv rising ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ was hi 11111111111111111111111111111111 total fails 0, total passes 69 Main menu Mon Jul 27 14:51:37 2015 test file is: tests\m115.tst delay is: 0 trigger is: 1 1 read test file 2 set test delay 3 set test trigger 4 run test 5 output loading test 8 diags 9 exit UUT power is okay Mon Jul 27 14:52:39 2015 space single step O run once (one test, all steps) F run, stop on fail G go (run tests N run, stop on fail, no print S scope (run, no print) C toggle comment printout + increase speed (less delay) - decrease speed (more delay)(slower) Q quit test scope (run, no print) pppppppppppppppppppppppppppppppppppppppppppppppppppppppppp space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C toggle comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDDEFHEFHJJKLMKLMNNPRSPRSUTUVV SIDE 11112222111122221111222211112221 DIRECTION IIIOIIIOIIIOIIIOIIIOIIIOIIIOIIIO all fails was lo 00000000000000000000000000000000 falling vvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvv rising ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ was hi 11111111111111111111111111111111 total fails 0, total passes 58 Main menu Mon Jul 27 14:52:45 2015 test file is: tests\m115.tst delay is: 0 trigger is: 1 1 read test file 2 set test delay 3 set test trigger 4 run test 5 output loading test 8 diags 9 exit UUT power is okay Mon Jul 27 14:53:47 2015 space single step O run once (one test, all steps) F run, stop on fail G go (run tests N run, stop on fail, no print S scope (run, no print) C toggle comment printout + increase speed (less delay) - decrease speed (more delay)(slower) Q quit test scope (run, no print) ppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppp pppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppp space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C toggle comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDDEFHEFHJJKLMKLMNNPRSPRSUTUVV SIDE 11112222111122221111222211112221 DIRECTION IIIOIIIOIIIOIIIOIIIOIIIOIIIOIIIO all fails was lo 00000000000000000000000000000000 falling vvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvv rising ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ was hi 11111111111111111111111111111111 total fails 0, total passes 149 Main menu Mon Jul 27 14:54:15 2015 test file is: tests\m115.tst delay is: 0 trigger is: 1 1 read test file 2 set test delay 3 set test trigger 4 run test 5 output loading test 8 diags 9 exit UUT power is okay Mon Jul 27 14:55:10 2015 space single step O run once (one test, all steps) F run, stop on fail G go (run tests N run, stop on fail, no print S scope (run, no print) C toggle comment printout + increase speed (less delay) - decrease speed (more delay)(slower) Q quit test scope (run, no print) ppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppp space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C toggle comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDDEFHEFHJJKLMKLMNNPRSPRSUTUVV SIDE 11112222111122221111222211112221 DIRECTION IIIOIIIOIIIOIIIOIIIOIIIOIIIOIIIO all fails was lo 00000000000000000000000000000000 falling vvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvv rising ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ was hi 11111111111111111111111111111111 total fails 0, total passes 69 Main menu Mon Jul 27 14:55:16 2015 test file is: tests\m115.tst delay is: 0 trigger is: 1 1 read test file 2 set test delay 3 set test trigger 4 run test 5 output loading test 8 diags 9 exit UUT power is okay Mon Jul 27 14:56:32 2015 space single step O run once (one test, all steps) F run, stop on fail G go (run tests N run, stop on fail, no print S scope (run, no print) C toggle comment printout + increase speed (less delay) - decrease speed (more delay)(slower) Q quit test scope (run, no print) ppppppppppppppppppppppppppppppppppppppppppppppppppppppppppp space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C toggle comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDDEFHEFHJJKLMKLMNNPRSPRSUTUVV SIDE 11112222111122221111222211112221 DIRECTION IIIOIIIOIIIOIIIOIIIOIIIOIIIOIIIO all fails was lo 00000000000000000000000000000000 falling vvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvv rising ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ was hi 11111111111111111111111111111111 total fails 0, total passes 59 Main menu Mon Jul 27 14:56:38 2015 test file is: tests\m115.tst delay is: 0 trigger is: 1 1 read test file 2 set test delay 3 set test trigger 4 run test 5 output loading test 8 diags 9 exit UUT power is okay Mon Jul 27 14:57:47 2015 space single step O run once (one test, all steps) F run, stop on fail G go (run tests N run, stop on fail, no print S scope (run, no print) C toggle comment printout + increase speed (less delay) - decrease speed (more delay)(slower) Q quit test scope (run, no print) ppppppppppppppppppppppppppppppppppppppppppppppppppppppppppp space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C toggle comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDDEFHEFHJJKLMKLMNNPRSPRSUTUVV SIDE 11112222111122221111222211112221 DIRECTION IIIOIIIOIIIOIIIOIIIOIIIOIIIOIIIO all fails was lo 00000000000000000000000000000000 falling vvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvv rising ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ was hi 11111111111111111111111111111111 total fails 0, total passes 59 Main menu Mon Jul 27 14:57:53 2015 test file is: tests\m115.tst delay is: 0 trigger is: 1 1 read test file 2 set test delay 3 set test trigger 4 run test 5 output loading test 8 diags 9 exit UUT power is okay Mon Jul 27 14:59:24 2015 space single step O run once (one test, all steps) F run, stop on fail G go (run tests N run, stop on fail, no print S scope (run, no print) C toggle comment printout + increase speed (less delay) - decrease speed (more delay)(slower) Q quit test scope (run, no print) ppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppp ppppppppppppppppppppppppppppppp space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C toggle comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDDEFHEFHJJKLMKLMNNPRSPRSUTUVV SIDE 11112222111122221111222211112221 DIRECTION IIIOIIIOIIIOIIIOIIIOIIIOIIIOIIIO all fails was lo 00000000000000000000000000000000 falling vvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvv rising ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ was hi 11111111111111111111111111111111 total fails 0, total passes 110 Main menu Mon Jul 27 14:59:33 2015 test file is: tests\m115.tst delay is: 0 trigger is: 1 1 read test file 2 set test delay 3 set test trigger 4 run test 5 output loading test 8 diags 9 exit Enter test file name? trying to open test file: tests\m117.tst reading test file: tests\m117.tst comment: M117 REV 3 6 4-input NAND comment: pins: PINS pins: 1 I AA1 E1-13 pins: 2 I AB1 E1-12 pins: 3 I AC1 E1-10 pins: 4 I AD1 E1-9 pins: 5 O AE1 E1-8 pins: 6 I AF1 E2-13 pins: 7 I AH1 E2-12 pins: 8 I AJ1 E2-10 pins: 9 I AK1 E2-9 pins: 10 O AL1 E2-8 pins: 11 I AM1 E3-13 pins: 12 I AN1 E3-12 pins: 13 I AP1 E3-10 pins: 14 I AR1 E3-9 pins: 15 O AS1 E3-8 pins: 16 I AD2 E1-5 pins: 17 I AE2 E1-4 pins: 18 I AF2 E1-2 pins: 19 I AH2 E1-1 pins: 20 O AJ2 E1-6 pins: 21 I AK2 E2-5 pins: 22 I AL2 E2-4 pins: 23 I AM2 E2-2 pins: 24 I AN2 E2-1 pins: 25 O AP2 E2-6 pins: 26 I AR2 E3-1 pins: 27 I AS2 E3-2 pins: 28 I AT2 E3-4 pins: 29 I AU2 E3-5 pins: 30 O AV2 E3-6 pins: direction: IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO test 1: 000010000100001000010000100001 test 2: 00001 test 3: 00011 test 4: 00101 test 5: 00111 test 6: 01001 test 7: 01011 test 8: 01101 test 9: 01111 test 10: 10001 test 11: 10011 test 12: 10101 test 13: 10111 test 14: 11001 test 15: 11011 test 16: 11101 test 17: 11110 test 18: 00001 test 19: 00001 test 20: 00011 test 21: 00101 test 22: 00111 test 23: 01001 test 24: 01011 test 25: 01101 test 26: 01111 test 27: 10001 test 28: 10011 test 29: 10101 test 30: 10111 test 31: 11001 test 32: 11011 test 33: 11101 test 34: 11110 test 35: 00001 test 36: 00001 test 37: 00011 test 38: 00101 test 39: 00111 test 40: 01001 test 41: 01011 test 42: 01101 test 43: 01111 test 44: 10001 test 45: 10011 test 46: 10101 test 47: 10111 test 48: 11001 test 49: 11011 test 50: 11101 test 51: 11110 test 52: 00001 test 53: 00001 test 54: 00011 test 55: 00101 test 56: 00111 test 57: 01001 test 58: 01011 test 59: 01101 test 60: 01111 test 61: 10001 test 62: 10011 test 63: 10101 test 64: 10111 test 65: 11001 test 66: 11011 test 67: 11101 test 68: 11110 test 69: 00001 test 70: 00001 test 71: 00011 test 72: 00101 test 73: 00111 test 74: 01001 test 75: 01011 test 76: 01101 test 77: 01111 test 78: 10001 test 79: 10011 test 80: 10101 test 81: 10111 test 82: 11001 test 83: 11011 test 84: 11101 test 85: 11110 test 86: 00001 test 87: 00001 test 88: 00011 test 89: 00101 test 90: 00111 test 91: 01001 test 92: 01011 test 93: 01101 test 94: 01111 test 95: 10001 test 96: 10011 test 97: 10101 test 98: 10111 test 99: 11001 test 100: 11011 test 101: 11101 test 102: 11110 test 103: 00001 test 104: 000010000100001000010000100001 test 105: 111101111011110111101111011110 test 106: 00001 test 107: 00011 test 108: 00101 test 109: 00111 test 110: 01001 test 111: 01011 test 112: 01101 test 113: 01111 test 114: 10001 test 115: 10011 test 116: 10101 test 117: 10111 test 118: 11001 test 119: 11011 test 120: 11101 test 121: 11110 test 122: 00001 test 123: 00011 test 124: 00101 test 125: 00111 test 126: 01001 test 127: 01011 test 128: 01101 test 129: 01111 test 130: 10001 test 131: 10011 test 132: 10101 test 133: 10111 test 134: 11001 test 135: 11011 test 136: 11101 test 137: 11110 test 138: 00001 test 139: 00011 test 140: 00101 test 141: 00111 test 142: 01001 test 143: 01011 test 144: 01101 test 145: 01111 test 146: 10001 test 147: 10011 test 148: 10101 test 149: 10111 test 150: 11001 test 151: 11011 test 152: 11101 test 153: 11110 test 154: 00001 test 155: 00011 test 156: 00101 test 157: 00111 test 158: 01001 test 159: 01011 test 160: 01101 test 161: 01111 test 162: 10001 test 163: 10011 test 164: 10101 test 165: 10111 test 166: 11001 test 167: 11011 test 168: 11101 test 169: 11110 test 170: 00001 test 171: 00011 test 172: 00101 test 173: 00111 test 174: 01001 test 175: 01011 test 176: 01101 test 177: 01111 test 178: 10001 test 179: 10011 test 180: 10101 test 181: 10111 test 182: 11001 test 183: 11011 test 184: 11101 test 185: 11110 test 186: 00001 test 187: 00011 test 188: 00101 test 189: 00111 test 190: 01001 test 191: 01011 test 192: 01101 test 193: 01111 test 194: 10001 test 195: 10011 test 196: 10101 test 197: 10111 test 198: 11001 test 199: 11011 test 200: 11101 test 201: 11110 test 202: 111101111011110111101111011110 end: END summary column 1: offset 0, mask 0x8000 column 2: offset 0, mask 0x4000 column 3: offset 0, mask 0x2000 column 4: offset 0, mask 0x1000 column 5: offset 0, mask 0x0800 column 6: offset 0, mask 0x0400 column 7: offset 0, mask 0x0200 column 8: offset 0, mask 0x0100 column 9: offset 1, mask 0x8000 column 10: offset 1, mask 0x4000 column 11: offset 1, mask 0x2000 column 12: offset 1, mask 0x1000 column 13: offset 1, mask 0x0800 column 14: offset 1, mask 0x0400 column 15: offset 1, mask 0x0200 column 16: offset 0, mask 0x0010 column 17: offset 0, mask 0x0008 column 18: offset 0, mask 0x0004 column 19: offset 0, mask 0x0002 column 20: offset 0, mask 0x0001 column 21: offset 1, mask 0x0001 column 22: offset 1, mask 0x0002 column 23: offset 1, mask 0x0004 column 24: offset 1, mask 0x0008 column 25: offset 1, mask 0x0010 column 26: offset 1, mask 0x0020 column 27: offset 1, mask 0x0040 column 28: offset 1, mask 0x0080 column 29: offset 2, mask 0x0001 column 30: offset 2, mask 0x0002 direction bits (1=input) 0x08E1 0x4310 0xFFFA 0xFFFF 0xF0FF pullup bits (1=pullup) 0x0000 0x0000 0x0000 0x0000 0x0000 test step out_data dont care 1: 0x0801 0x4210 0x0002 0x0000 0x0000 2: 0x0801 0x4210 0x0002 0x0000 0x0000 3: 0x1801 0x4210 0x0002 0x0000 0x0000 4: 0x2801 0x4210 0x0002 0x0000 0x0000 5: 0x3801 0x4210 0x0002 0x0000 0x0000 6: 0x4801 0x4210 0x0002 0x0000 0x0000 7: 0x5801 0x4210 0x0002 0x0000 0x0000 8: 0x6801 0x4210 0x0002 0x0000 0x0000 9: 0x7801 0x4210 0x0002 0x0000 0x0000 10: 0x8801 0x4210 0x0002 0x0000 0x0000 11: 0x9801 0x4210 0x0002 0x0000 0x0000 12: 0xA801 0x4210 0x0002 0x0000 0x0000 13: 0xB801 0x4210 0x0002 0x0000 0x0000 14: 0xC801 0x4210 0x0002 0x0000 0x0000 15: 0xD801 0x4210 0x0002 0x0000 0x0000 16: 0xE801 0x4210 0x0002 0x0000 0x0000 17: 0xF001 0x4210 0x0002 0x0000 0x0000 18: 0x0801 0x4210 0x0002 0x0000 0x0000 19: 0x0801 0x4210 0x0002 0x0000 0x0000 20: 0x0801 0xC210 0x0002 0x0000 0x0000 21: 0x0901 0x4210 0x0002 0x0000 0x0000 22: 0x0901 0xC210 0x0002 0x0000 0x0000 23: 0x0A01 0x4210 0x0002 0x0000 0x0000 24: 0x0A01 0xC210 0x0002 0x0000 0x0000 25: 0x0B01 0x4210 0x0002 0x0000 0x0000 26: 0x0B01 0xC210 0x0002 0x0000 0x0000 27: 0x0C01 0x4210 0x0002 0x0000 0x0000 28: 0x0C01 0xC210 0x0002 0x0000 0x0000 29: 0x0D01 0x4210 0x0002 0x0000 0x0000 30: 0x0D01 0xC210 0x0002 0x0000 0x0000 31: 0x0E01 0x4210 0x0002 0x0000 0x0000 32: 0x0E01 0xC210 0x0002 0x0000 0x0000 33: 0x0F01 0x4210 0x0002 0x0000 0x0000 34: 0x0F01 0x8210 0x0002 0x0000 0x0000 35: 0x0801 0x4210 0x0002 0x0000 0x0000 36: 0x0801 0x4210 0x0002 0x0000 0x0000 37: 0x0801 0x4610 0x0002 0x0000 0x0000 38: 0x0801 0x4A10 0x0002 0x0000 0x0000 39: 0x0801 0x4E10 0x0002 0x0000 0x0000 40: 0x0801 0x5210 0x0002 0x0000 0x0000 41: 0x0801 0x5610 0x0002 0x0000 0x0000 42: 0x0801 0x5A10 0x0002 0x0000 0x0000 43: 0x0801 0x5E10 0x0002 0x0000 0x0000 44: 0x0801 0x6210 0x0002 0x0000 0x0000 45: 0x0801 0x6610 0x0002 0x0000 0x0000 46: 0x0801 0x6A10 0x0002 0x0000 0x0000 47: 0x0801 0x6E10 0x0002 0x0000 0x0000 48: 0x0801 0x7210 0x0002 0x0000 0x0000 49: 0x0801 0x7610 0x0002 0x0000 0x0000 50: 0x0801 0x7A10 0x0002 0x0000 0x0000 51: 0x0801 0x7C10 0x0002 0x0000 0x0000 52: 0x0801 0x4210 0x0002 0x0000 0x0000 53: 0x0801 0x4210 0x0002 0x0000 0x0000 54: 0x0803 0x4210 0x0002 0x0000 0x0000 55: 0x0805 0x4210 0x0002 0x0000 0x0000 56: 0x0807 0x4210 0x0002 0x0000 0x0000 57: 0x0809 0x4210 0x0002 0x0000 0x0000 58: 0x080B 0x4210 0x0002 0x0000 0x0000 59: 0x080D 0x4210 0x0002 0x0000 0x0000 60: 0x080F 0x4210 0x0002 0x0000 0x0000 61: 0x0811 0x4210 0x0002 0x0000 0x0000 62: 0x0813 0x4210 0x0002 0x0000 0x0000 63: 0x0815 0x4210 0x0002 0x0000 0x0000 64: 0x0817 0x4210 0x0002 0x0000 0x0000 65: 0x0819 0x4210 0x0002 0x0000 0x0000 66: 0x081B 0x4210 0x0002 0x0000 0x0000 67: 0x081D 0x4210 0x0002 0x0000 0x0000 68: 0x081E 0x4210 0x0002 0x0000 0x0000 69: 0x0801 0x4210 0x0002 0x0000 0x0000 70: 0x0801 0x4210 0x0002 0x0000 0x0000 71: 0x0801 0x4218 0x0002 0x0000 0x0000 72: 0x0801 0x4214 0x0002 0x0000 0x0000 73: 0x0801 0x421C 0x0002 0x0000 0x0000 74: 0x0801 0x4212 0x0002 0x0000 0x0000 75: 0x0801 0x421A 0x0002 0x0000 0x0000 76: 0x0801 0x4216 0x0002 0x0000 0x0000 77: 0x0801 0x421E 0x0002 0x0000 0x0000 78: 0x0801 0x4211 0x0002 0x0000 0x0000 79: 0x0801 0x4219 0x0002 0x0000 0x0000 80: 0x0801 0x4215 0x0002 0x0000 0x0000 81: 0x0801 0x421D 0x0002 0x0000 0x0000 82: 0x0801 0x4213 0x0002 0x0000 0x0000 83: 0x0801 0x421B 0x0002 0x0000 0x0000 84: 0x0801 0x4217 0x0002 0x0000 0x0000 85: 0x0801 0x420F 0x0002 0x0000 0x0000 86: 0x0801 0x4210 0x0002 0x0000 0x0000 87: 0x0801 0x4210 0x0002 0x0000 0x0000 88: 0x0801 0x4210 0x0003 0x0000 0x0000 89: 0x0801 0x4290 0x0002 0x0000 0x0000 90: 0x0801 0x4290 0x0003 0x0000 0x0000 91: 0x0801 0x4250 0x0002 0x0000 0x0000 92: 0x0801 0x4250 0x0003 0x0000 0x0000 93: 0x0801 0x42D0 0x0002 0x0000 0x0000 94: 0x0801 0x42D0 0x0003 0x0000 0x0000 95: 0x0801 0x4230 0x0002 0x0000 0x0000 96: 0x0801 0x4230 0x0003 0x0000 0x0000 97: 0x0801 0x42B0 0x0002 0x0000 0x0000 98: 0x0801 0x42B0 0x0003 0x0000 0x0000 99: 0x0801 0x4270 0x0002 0x0000 0x0000 100: 0x0801 0x4270 0x0003 0x0000 0x0000 101: 0x0801 0x42F0 0x0002 0x0000 0x0000 102: 0x0801 0x42F0 0x0001 0x0000 0x0000 103: 0x0801 0x4210 0x0002 0x0000 0x0000 104: 0x0801 0x4210 0x0002 0x0000 0x0000 105: 0xF71E 0xBCEF 0x0001 0x0000 0x0000 106: 0x0F1E 0xBCEF 0x0001 0x0000 0x0000 107: 0x1F1E 0xBCEF 0x0001 0x0000 0x0000 108: 0x2F1E 0xBCEF 0x0001 0x0000 0x0000 109: 0x3F1E 0xBCEF 0x0001 0x0000 0x0000 110: 0x4F1E 0xBCEF 0x0001 0x0000 0x0000 111: 0x5F1E 0xBCEF 0x0001 0x0000 0x0000 112: 0x6F1E 0xBCEF 0x0001 0x0000 0x0000 113: 0x7F1E 0xBCEF 0x0001 0x0000 0x0000 114: 0x8F1E 0xBCEF 0x0001 0x0000 0x0000 115: 0x9F1E 0xBCEF 0x0001 0x0000 0x0000 116: 0xAF1E 0xBCEF 0x0001 0x0000 0x0000 117: 0xBF1E 0xBCEF 0x0001 0x0000 0x0000 118: 0xCF1E 0xBCEF 0x0001 0x0000 0x0000 119: 0xDF1E 0xBCEF 0x0001 0x0000 0x0000 120: 0xEF1E 0xBCEF 0x0001 0x0000 0x0000 121: 0xF71E 0xBCEF 0x0001 0x0000 0x0000 122: 0xF01E 0x7CEF 0x0001 0x0000 0x0000 123: 0xF01E 0xFCEF 0x0001 0x0000 0x0000 124: 0xF11E 0x7CEF 0x0001 0x0000 0x0000 125: 0xF11E 0xFCEF 0x0001 0x0000 0x0000 126: 0xF21E 0x7CEF 0x0001 0x0000 0x0000 127: 0xF21E 0xFCEF 0x0001 0x0000 0x0000 128: 0xF31E 0x7CEF 0x0001 0x0000 0x0000 129: 0xF31E 0xFCEF 0x0001 0x0000 0x0000 130: 0xF41E 0x7CEF 0x0001 0x0000 0x0000 131: 0xF41E 0xFCEF 0x0001 0x0000 0x0000 132: 0xF51E 0x7CEF 0x0001 0x0000 0x0000 133: 0xF51E 0xFCEF 0x0001 0x0000 0x0000 134: 0xF61E 0x7CEF 0x0001 0x0000 0x0000 135: 0xF61E 0xFCEF 0x0001 0x0000 0x0000 136: 0xF71E 0x7CEF 0x0001 0x0000 0x0000 137: 0xF71E 0xBCEF 0x0001 0x0000 0x0000 138: 0xF71E 0x82EF 0x0001 0x0000 0x0000 139: 0xF71E 0x86EF 0x0001 0x0000 0x0000 140: 0xF71E 0x8AEF 0x0001 0x0000 0x0000 141: 0xF71E 0x8EEF 0x0001 0x0000 0x0000 142: 0xF71E 0x92EF 0x0001 0x0000 0x0000 143: 0xF71E 0x96EF 0x0001 0x0000 0x0000 144: 0xF71E 0x9AEF 0x0001 0x0000 0x0000 145: 0xF71E 0x9EEF 0x0001 0x0000 0x0000 146: 0xF71E 0xA2EF 0x0001 0x0000 0x0000 147: 0xF71E 0xA6EF 0x0001 0x0000 0x0000 148: 0xF71E 0xAAEF 0x0001 0x0000 0x0000 149: 0xF71E 0xAEEF 0x0001 0x0000 0x0000 150: 0xF71E 0xB2EF 0x0001 0x0000 0x0000 151: 0xF71E 0xB6EF 0x0001 0x0000 0x0000 152: 0xF71E 0xBAEF 0x0001 0x0000 0x0000 153: 0xF71E 0xBCEF 0x0001 0x0000 0x0000 154: 0xF701 0xBCEF 0x0001 0x0000 0x0000 155: 0xF703 0xBCEF 0x0001 0x0000 0x0000 156: 0xF705 0xBCEF 0x0001 0x0000 0x0000 157: 0xF707 0xBCEF 0x0001 0x0000 0x0000 158: 0xF709 0xBCEF 0x0001 0x0000 0x0000 159: 0xF70B 0xBCEF 0x0001 0x0000 0x0000 160: 0xF70D 0xBCEF 0x0001 0x0000 0x0000 161: 0xF70F 0xBCEF 0x0001 0x0000 0x0000 162: 0xF711 0xBCEF 0x0001 0x0000 0x0000 163: 0xF713 0xBCEF 0x0001 0x0000 0x0000 164: 0xF715 0xBCEF 0x0001 0x0000 0x0000 165: 0xF717 0xBCEF 0x0001 0x0000 0x0000 166: 0xF719 0xBCEF 0x0001 0x0000 0x0000 167: 0xF71B 0xBCEF 0x0001 0x0000 0x0000 168: 0xF71D 0xBCEF 0x0001 0x0000 0x0000 169: 0xF71E 0xBCEF 0x0001 0x0000 0x0000 170: 0xF71E 0xBCF0 0x0001 0x0000 0x0000 171: 0xF71E 0xBCF8 0x0001 0x0000 0x0000 172: 0xF71E 0xBCF4 0x0001 0x0000 0x0000 173: 0xF71E 0xBCFC 0x0001 0x0000 0x0000 174: 0xF71E 0xBCF2 0x0001 0x0000 0x0000 175: 0xF71E 0xBCFA 0x0001 0x0000 0x0000 176: 0xF71E 0xBCF6 0x0001 0x0000 0x0000 177: 0xF71E 0xBCFE 0x0001 0x0000 0x0000 178: 0xF71E 0xBCF1 0x0001 0x0000 0x0000 179: 0xF71E 0xBCF9 0x0001 0x0000 0x0000 180: 0xF71E 0xBCF5 0x0001 0x0000 0x0000 181: 0xF71E 0xBCFD 0x0001 0x0000 0x0000 182: 0xF71E 0xBCF3 0x0001 0x0000 0x0000 183: 0xF71E 0xBCFB 0x0001 0x0000 0x0000 184: 0xF71E 0xBCF7 0x0001 0x0000 0x0000 185: 0xF71E 0xBCEF 0x0001 0x0000 0x0000 186: 0xF71E 0xBC0F 0x0002 0x0000 0x0000 187: 0xF71E 0xBC0F 0x0003 0x0000 0x0000 188: 0xF71E 0xBC8F 0x0002 0x0000 0x0000 189: 0xF71E 0xBC8F 0x0003 0x0000 0x0000 190: 0xF71E 0xBC4F 0x0002 0x0000 0x0000 191: 0xF71E 0xBC4F 0x0003 0x0000 0x0000 192: 0xF71E 0xBCCF 0x0002 0x0000 0x0000 193: 0xF71E 0xBCCF 0x0003 0x0000 0x0000 194: 0xF71E 0xBC2F 0x0002 0x0000 0x0000 195: 0xF71E 0xBC2F 0x0003 0x0000 0x0000 196: 0xF71E 0xBCAF 0x0002 0x0000 0x0000 197: 0xF71E 0xBCAF 0x0003 0x0000 0x0000 198: 0xF71E 0xBC6F 0x0002 0x0000 0x0000 199: 0xF71E 0xBC6F 0x0003 0x0000 0x0000 200: 0xF71E 0xBCEF 0x0002 0x0000 0x0000 201: 0xF71E 0xBCEF 0x0001 0x0000 0x0000 202: 0xF71E 0xBCEF 0x0001 0x0000 0x0000 PINs used (in edge connector order) (G=ground,P=power) SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBB LETTER ABCDEFHJKLMNPRSTUVABCDEFHJKLMNPRSTUVABCDEFHJKLMNPRSTUVABCDEFHJKLMNPRSTUV SIDE 111111111111111111222222222222222222111111111111111111222222222222222222 USAGE IIIIOIIIIOIIIIOG P GIIIIOIIIIOIIIIO G P G UUT has 24 inputs UUT has 6 outputs contains 30 pins/columns 36 pins are not used contains 202 'test steps' M117 REV 3 6 4-input NAND PINS Main menu Mon Jul 27 15:01:06 2015 test file is: tests\m117.tst delay is: 0 trigger is: 1 1 read test file 2 set test delay 3 set test trigger 4 run test 5 output loading test 8 diags 9 exit UUT power is okay Mon Jul 27 15:01:32 2015 space single step O run once (one test, all steps) F run, stop on fail G go (run tests N run, stop on fail, no print S scope (run, no print) C toggle comment printout + increase speed (less delay) - decrease speed (more delay)(slower) Q quit test scope (run, no print) pppppppppppppppppppppppppppppppppppppppppppppppppp space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C toggle comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFHJKLMNPRSDEFHJKLMNPRSTUV SIDE 111111111111111222222222222222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO all fails was lo 000000000000000000000000000000 falling vvvvvvvvvvvvvvvvvvvvvvvvvvvvvv rising ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ was hi 111111111111111111111111111111 total fails 0, total passes 50 Main menu Mon Jul 27 15:01:40 2015 test file is: tests\m117.tst delay is: 0 trigger is: 1 1 read test file 2 set test delay 3 set test trigger 4 run test 5 output loading test 8 diags 9 exit UUT power is okay Mon Jul 27 15:02:44 2015 space single step O run once (one test, all steps) F run, stop on fail G go (run tests N run, stop on fail, no print S scope (run, no print) C toggle comment printout + increase speed (less delay) - decrease speed (more delay)(slower) Q quit test scope (run, no print) ppppppppppppppppppppppppppppppppppppppppppppp space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C toggle comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFHJKLMNPRSDEFHJKLMNPRSTUV SIDE 111111111111111222222222222222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO all fails was lo 000000000000000000000000000000 falling vvvvvvvvvvvvvvvvvvvvvvvvvvvvvv rising ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ was hi 111111111111111111111111111111 total fails 0, total passes 45 Main menu Mon Jul 27 15:02:52 2015 test file is: tests\m117.tst delay is: 0 trigger is: 1 1 read test file 2 set test delay 3 set test trigger 4 run test 5 output loading test 8 diags 9 exit UUT power is okay Mon Jul 27 15:04:01 2015 space single step O run once (one test, all steps) F run, stop on fail G go (run tests N run, stop on fail, no print S scope (run, no print) C toggle comment printout + increase speed (less delay) - decrease speed (more delay)(slower) Q quit test scope (run, no print) ppppppppppppppppppppppppppppppppppppppppppp space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C toggle comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFHJKLMNPRSDEFHJKLMNPRSTUV SIDE 111111111111111222222222222222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO all fails was lo 000000000000000000000000000000 falling vvvvvvvvvvvvvvvvvvvvvvvvvvvvvv rising ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ was hi 111111111111111111111111111111 total fails 0, total passes 43 Main menu Mon Jul 27 15:04:07 2015 test file is: tests\m117.tst delay is: 0 trigger is: 1 1 read test file 2 set test delay 3 set test trigger 4 run test 5 output loading test 8 diags 9 exit UUT power is okay Mon Jul 27 15:05:08 2015 space single step O run once (one test, all steps) F run, stop on fail G go (run tests N run, stop on fail, no print S scope (run, no print) C toggle comment printout + increase speed (less delay) - decrease speed (more delay)(slower) Q quit test scope (run, no print) ppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppp ppppppppppppppppppppppppppppp space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C toggle comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFHJKLMNPRSDEFHJKLMNPRSTUV SIDE 111111111111111222222222222222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO all fails was lo 000000000000000000000000000000 falling vvvvvvvvvvvvvvvvvvvvvvvvvvvvvv rising ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ was hi 111111111111111111111111111111 total fails 0, total passes 108 Main menu Mon Jul 27 15:05:21 2015 test file is: tests\m117.tst delay is: 0 trigger is: 1 1 read test file 2 set test delay 3 set test trigger 4 run test 5 output loading test 8 diags 9 exit UUT power is okay Mon Jul 27 15:06:18 2015 space single step O run once (one test, all steps) F run, stop on fail G go (run tests N run, stop on fail, no print S scope (run, no print) C toggle comment printout + increase speed (less delay) - decrease speed (more delay)(slower) Q quit test scope (run, no print) ppppppppppppppppppppppppppppppppppppppppppppppppppp space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C toggle comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFHJKLMNPRSDEFHJKLMNPRSTUV SIDE 111111111111111222222222222222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO all fails was lo 000000000000000000000000000000 falling vvvvvvvvvvvvvvvvvvvvvvvvvvvvvv rising ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ was hi 111111111111111111111111111111 total fails 0, total passes 51 Main menu Mon Jul 27 15:06:24 2015 test file is: tests\m117.tst delay is: 0 trigger is: 1 1 read test file 2 set test delay 3 set test trigger 4 run test 5 output loading test 8 diags 9 exit UUT power is okay Mon Jul 27 15:07:12 2015 space single step O run once (one test, all steps) F run, stop on fail G go (run tests N run, stop on fail, no print S scope (run, no print) C toggle comment printout + increase speed (less delay) - decrease speed (more delay)(slower) Q quit test scope (run, no print) pppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppp space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C toggle comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFHJKLMNPRSDEFHJKLMNPRSTUV SIDE 111111111111111222222222222222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO all fails was lo 000000000000000000000000000000 falling vvvvvvvvvvvvvvvvvvvvvvvvvvvvvv rising ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ was hi 111111111111111111111111111111 total fails 0, total passes 64 Main menu Mon Jul 27 15:07:21 2015 test file is: tests\m117.tst delay is: 0 trigger is: 1 1 read test file 2 set test delay 3 set test trigger 4 run test 5 output loading test 8 diags 9 exit UUT power is okay Mon Jul 27 15:08:18 2015 space single step O run once (one test, all steps) F run, stop on fail G go (run tests N run, stop on fail, no print S scope (run, no print) C toggle comment printout + increase speed (less delay) - decrease speed (more delay)(slower) Q quit test scope (run, no print) pppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppp space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C toggle comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFHJKLMNPRSDEFHJKLMNPRSTUV SIDE 111111111111111222222222222222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO all fails was lo 000000000000000000000000000000 falling vvvvvvvvvvvvvvvvvvvvvvvvvvvvvv rising ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ was hi 111111111111111111111111111111 total fails 0, total passes 78 Main menu Mon Jul 27 15:08:27 2015 test file is: tests\m117.tst delay is: 0 trigger is: 1 1 read test file 2 set test delay 3 set test trigger 4 run test 5 output loading test 8 diags 9 exit UUT power is okay Mon Jul 27 15:10:01 2015 space single step O run once (one test, all steps) F run, stop on fail G go (run tests N run, stop on fail, no print S scope (run, no print) C toggle comment printout + increase speed (less delay) - decrease speed (more delay)(slower) Q quit test scope (run, no print) ppppppppppppppppppppppppppppppppppppppp space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C toggle comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFHJKLMNPRSDEFHJKLMNPRSTUV SIDE 111111111111111222222222222222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO all fails was lo 000000000000000000000000000000 falling vvvvvvvvvvvvvvvvvvvvvvvvvvvvvv rising ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ was hi 111111111111111111111111111111 total fails 0, total passes 39 Main menu Mon Jul 27 15:10:07 2015 test file is: tests\m117.tst delay is: 0 trigger is: 1 1 read test file 2 set test delay 3 set test trigger 4 run test 5 output loading test 8 diags 9 exit UUT power is okay Mon Jul 27 15:10:59 2015 space single step O run once (one test, all steps) F run, stop on fail G go (run tests N run, stop on fail, no print S scope (run, no print) C toggle comment printout + increase speed (less delay) - decrease speed (more delay)(slower) Q quit test scope (run, no print) pppppppppppppppppppppppppppppppppppppppp space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C toggle comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFHJKLMNPRSDEFHJKLMNPRSTUV SIDE 111111111111111222222222222222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO all fails was lo 000000000000000000000000000000 falling vvvvvvvvvvvvvvvvvvvvvvvvvvvvvv rising ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ was hi 111111111111111111111111111111 total fails 0, total passes 40 Main menu Mon Jul 27 15:11:04 2015 test file is: tests\m117.tst delay is: 0 trigger is: 1 1 read test file 2 set test delay 3 set test trigger 4 run test 5 output loading test 8 diags 9 exit Enter test file name? trying to open test file: tests\x could not open test file. valid test files are: reverting back to test file: tests\m117.tst Main menu Mon Jul 27 15:12:31 2015 test file is: tests\m117.tst delay is: 0 trigger is: 1 1 read test file 2 set test delay 3 set test trigger 4 run test 5 output loading test 8 diags 9 exit Enter test file name? trying to open test file: tests\m119.tst reading test file: tests\m119.tst comment: M119 REV B 3 8-input NAND comment: pins: PINS pins: 1 I AA1 E1-12 pins: 2 I AB1 E1-11 pins: 3 I AC1 E1-5 pins: 4 I AD1 E1-6 pins: 5 I AD2 E1-4 pins: 6 I AE2 E1-3 pins: 7 I AF2 E1-2 pins: 8 I AH2 E1-1 pins: 9 O AJ2 E1-8 pins: 10 I AF1 E2-12 pins: 11 I AH1 E2-11 pins: 12 I AJ1 E2-5 pins: 13 I AK1 E2-6 pins: 14 I AK2 E2-4 pins: 15 I AL2 E2-3 pins: 16 I AM2 E2-2 pins: 17 I AN2 E2-1 pins: 18 O AP2 E2-8 pins: 19 I AM1 E3-12 pins: 20 I AN1 E3-11 pins: 21 I AP1 E3-5 pins: 22 I AR1 E3-6 pins: 23 I AR2 E3-4 pins: 24 I AS2 E3-3 pins: 25 I AT2 E3-2 pins: 26 I AU2 E3-1 pins: 27 O AV2 E3-8 pins: direction: IIIIIIIIOIIIIIIIIOIIIIIIIIO test 1: 000000001000000001000000001 test 2: 000000001 test 3: 000000011 test 4: 000000101 test 5: 000000111 test 6: 000001001 test 7: 000001011 test 8: 000001101 test 9: 000001111 test 10: 000010001 test 11: 000010011 test 12: 000010101 test 13: 000010111 test 14: 000011001 test 15: 000011011 test 16: 000011101 test 17: 000011111 test 18: 000100001 test 19: 000100011 test 20: 000100101 test 21: 000100111 test 22: 000101001 test 23: 000101011 test 24: 000101101 test 25: 000101111 test 26: 000110001 test 27: 000110011 test 28: 000110101 test 29: 000110111 test 30: 000111001 test 31: 000111011 test 32: 000111101 test 33: 000111111 test 34: 001000001 test 35: 001000011 test 36: 001000101 test 37: 001000111 test 38: 001001001 test 39: 001001011 test 40: 001001101 test 41: 001001111 test 42: 001010001 test 43: 001010011 test 44: 001010101 test 45: 001010111 test 46: 001011001 test 47: 001011011 test 48: 001011101 test 49: 001011111 test 50: 001100001 test 51: 001100011 test 52: 001100101 test 53: 001100111 test 54: 001101001 test 55: 001101011 test 56: 001101101 test 57: 001101111 test 58: 001110001 test 59: 001110011 test 60: 001110101 test 61: 001110111 test 62: 001111001 test 63: 001111011 test 64: 001111101 test 65: 001111111 test 66: 010000001 test 67: 010000011 test 68: 010000101 test 69: 010000111 test 70: 010001001 test 71: 010001011 test 72: 010001101 test 73: 010001111 test 74: 010010001 test 75: 010010011 test 76: 010010101 test 77: 010010111 test 78: 010011001 test 79: 010011011 test 80: 010011101 test 81: 010011111 test 82: 010100001 test 83: 010100011 test 84: 010100101 test 85: 010100111 test 86: 010101001 test 87: 010101011 test 88: 010101101 test 89: 010101111 test 90: 010110001 test 91: 010110011 test 92: 010110101 test 93: 010110111 test 94: 010111001 test 95: 010111011 test 96: 010111101 test 97: 010111111 test 98: 011000001 test 99: 011000011 test 100: 011000101 test 101: 011000111 test 102: 011001001 test 103: 011001011 test 104: 011001101 test 105: 011001111 test 106: 011010001 test 107: 011010011 test 108: 011010101 test 109: 011010111 test 110: 011011001 test 111: 011011011 test 112: 011011101 test 113: 011011111 test 114: 011100001 test 115: 011100011 test 116: 011100101 test 117: 011100111 test 118: 011101001 test 119: 011101011 test 120: 011101101 test 121: 011101111 test 122: 011110001 test 123: 011110011 test 124: 011110101 test 125: 011110111 test 126: 011111001 test 127: 011111011 test 128: 011111101 test 129: 011111111 test 130: 100000001 test 131: 100000011 test 132: 100000101 test 133: 100000111 test 134: 100001001 test 135: 100001011 test 136: 100001101 test 137: 100001111 test 138: 100010001 test 139: 100010011 test 140: 100010101 test 141: 100010111 test 142: 100011001 test 143: 100011011 test 144: 100011101 test 145: 100011111 test 146: 100100001 test 147: 100100011 test 148: 100100101 test 149: 100100111 test 150: 100101001 test 151: 100101011 test 152: 100101101 test 153: 100101111 test 154: 100110001 test 155: 100110011 test 156: 100110101 test 157: 100110111 test 158: 100111001 test 159: 100111011 test 160: 100111101 test 161: 100111111 test 162: 101000001 test 163: 101000011 test 164: 101000101 test 165: 101000111 test 166: 101001001 test 167: 101001011 test 168: 101001101 test 169: 101001111 test 170: 101010001 test 171: 101010011 test 172: 101010101 test 173: 101010111 test 174: 101011001 test 175: 101011011 test 176: 101011101 test 177: 101011111 test 178: 101100001 test 179: 101100011 test 180: 101100101 test 181: 101100111 test 182: 101101001 test 183: 101101011 test 184: 101101101 test 185: 101101111 test 186: 101110001 test 187: 101110011 test 188: 101110101 test 189: 101110111 test 190: 101111001 test 191: 101111011 test 192: 101111101 test 193: 101111111 test 194: 110000001 test 195: 110000011 test 196: 110000101 test 197: 110000111 test 198: 110001001 test 199: 110001011 test 200: 110001101 test 201: 110001111 test 202: 110010001 test 203: 110010011 test 204: 110010101 test 205: 110010111 test 206: 110011001 test 207: 110011011 test 208: 110011101 test 209: 110011111 test 210: 110100001 test 211: 110100011 test 212: 110100101 test 213: 110100111 test 214: 110101001 test 215: 110101011 test 216: 110101101 test 217: 110101111 test 218: 110110001 test 219: 110110011 test 220: 110110101 test 221: 110110111 test 222: 110111001 test 223: 110111011 test 224: 110111101 test 225: 110111111 test 226: 111000001 test 227: 111000011 test 228: 111000101 test 229: 111000111 test 230: 111001001 test 231: 111001011 test 232: 111001101 test 233: 111001111 test 234: 111010001 test 235: 111010011 test 236: 111010101 test 237: 111010111 test 238: 111011001 test 239: 111011011 test 240: 111011101 test 241: 111011111 test 242: 111100001 test 243: 111100011 test 244: 111100101 test 245: 111100111 test 246: 111101001 test 247: 111101011 test 248: 111101101 test 249: 111101111 test 250: 111110001 test 251: 111110011 test 252: 111110101 test 253: 111110111 test 254: 111111001 test 255: 111111011 test 256: 111111101 test 257: 111111110 test 258: 000000001 test 259: 000000001 test 260: 000000011 test 261: 000000101 test 262: 000000111 test 263: 000001001 test 264: 000001011 test 265: 000001101 test 266: 000001111 test 267: 000010001 test 268: 000010011 test 269: 000010101 test 270: 000010111 test 271: 000011001 test 272: 000011011 test 273: 000011101 test 274: 000011111 test 275: 000100001 test 276: 000100011 test 277: 000100101 test 278: 000100111 test 279: 000101001 test 280: 000101011 test 281: 000101101 test 282: 000101111 test 283: 000110001 test 284: 000110011 test 285: 000110101 test 286: 000110111 test 287: 000111001 test 288: 000111011 test 289: 000111101 test 290: 000111111 test 291: 001000001 test 292: 001000011 test 293: 001000101 test 294: 001000111 test 295: 001001001 test 296: 001001011 test 297: 001001101 test 298: 001001111 test 299: 001010001 test 300: 001010011 test 301: 001010101 test 302: 001010111 test 303: 001011001 test 304: 001011011 test 305: 001011101 test 306: 001011111 test 307: 001100001 test 308: 001100011 test 309: 001100101 test 310: 001100111 test 311: 001101001 test 312: 001101011 test 313: 001101101 test 314: 001101111 test 315: 001110001 test 316: 001110011 test 317: 001110101 test 318: 001110111 test 319: 001111001 test 320: 001111011 test 321: 001111101 test 322: 001111111 test 323: 010000001 test 324: 010000011 test 325: 010000101 test 326: 010000111 test 327: 010001001 test 328: 010001011 test 329: 010001101 test 330: 010001111 test 331: 010010001 test 332: 010010011 test 333: 010010101 test 334: 010010111 test 335: 010011001 test 336: 010011011 test 337: 010011101 test 338: 010011111 test 339: 010100001 test 340: 010100011 test 341: 010100101 test 342: 010100111 test 343: 010101001 test 344: 010101011 test 345: 010101101 test 346: 010101111 test 347: 010110001 test 348: 010110011 test 349: 010110101 test 350: 010110111 test 351: 010111001 test 352: 010111011 test 353: 010111101 test 354: 010111111 test 355: 011000001 test 356: 011000011 test 357: 011000101 test 358: 011000111 test 359: 011001001 test 360: 011001011 test 361: 011001101 test 362: 011001111 test 363: 011010001 test 364: 011010011 test 365: 011010101 test 366: 011010111 test 367: 011011001 test 368: 011011011 test 369: 011011101 test 370: 011011111 test 371: 011100001 test 372: 011100011 test 373: 011100101 test 374: 011100111 test 375: 011101001 test 376: 011101011 test 377: 011101101 test 378: 011101111 test 379: 011110001 test 380: 011110011 test 381: 011110101 test 382: 011110111 test 383: 011111001 test 384: 011111011 test 385: 011111101 test 386: 011111111 test 387: 100000001 test 388: 100000011 test 389: 100000101 test 390: 100000111 test 391: 100001001 test 392: 100001011 test 393: 100001101 test 394: 100001111 test 395: 100010001 test 396: 100010011 test 397: 100010101 test 398: 100010111 test 399: 100011001 test 400: 100011011 test 401: 100011101 test 402: 100011111 test 403: 100100001 test 404: 100100011 test 405: 100100101 test 406: 100100111 test 407: 100101001 test 408: 100101011 test 409: 100101101 test 410: 100101111 test 411: 100110001 test 412: 100110011 test 413: 100110101 test 414: 100110111 test 415: 100111001 test 416: 100111011 test 417: 100111101 test 418: 100111111 test 419: 101000001 test 420: 101000011 test 421: 101000101 test 422: 101000111 test 423: 101001001 test 424: 101001011 test 425: 101001101 test 426: 101001111 test 427: 101010001 test 428: 101010011 test 429: 101010101 test 430: 101010111 test 431: 101011001 test 432: 101011011 test 433: 101011101 test 434: 101011111 test 435: 101100001 test 436: 101100011 test 437: 101100101 test 438: 101100111 test 439: 101101001 test 440: 101101011 test 441: 101101101 test 442: 101101111 test 443: 101110001 test 444: 101110011 test 445: 101110101 test 446: 101110111 test 447: 101111001 test 448: 101111011 test 449: 101111101 test 450: 101111111 test 451: 110000001 test 452: 110000011 test 453: 110000101 test 454: 110000111 test 455: 110001001 test 456: 110001011 test 457: 110001101 test 458: 110001111 test 459: 110010001 test 460: 110010011 test 461: 110010101 test 462: 110010111 test 463: 110011001 test 464: 110011011 test 465: 110011101 test 466: 110011111 test 467: 110100001 test 468: 110100011 test 469: 110100101 test 470: 110100111 test 471: 110101001 test 472: 110101011 test 473: 110101101 test 474: 110101111 test 475: 110110001 test 476: 110110011 test 477: 110110101 test 478: 110110111 test 479: 110111001 test 480: 110111011 test 481: 110111101 test 482: 110111111 test 483: 111000001 test 484: 111000011 test 485: 111000101 test 486: 111000111 test 487: 111001001 test 488: 111001011 test 489: 111001101 test 490: 111001111 test 491: 111010001 test 492: 111010011 test 493: 111010101 test 494: 111010111 test 495: 111011001 test 496: 111011011 test 497: 111011101 test 498: 111011111 test 499: 111100001 test 500: 111100011 test 501: 111100101 test 502: 111100111 test 503: 111101001 test 504: 111101011 test 505: 111101101 test 506: 111101111 test 507: 111110001 test 508: 111110011 test 509: 111110101 test 510: 111110111 test 511: 111111001 test 512: 111111011 test 513: 111111101 test 514: 111111110 test 515: 000000001 test 516: 000000001 test 517: 000000011 test 518: 000000101 test 519: 000000111 test 520: 000001001 test 521: 000001011 test 522: 000001101 test 523: 000001111 test 524: 000010001 test 525: 000010011 test 526: 000010101 test 527: 000010111 test 528: 000011001 test 529: 000011011 test 530: 000011101 test 531: 000011111 test 532: 000100001 test 533: 000100011 test 534: 000100101 test 535: 000100111 test 536: 000101001 test 537: 000101011 test 538: 000101101 test 539: 000101111 test 540: 000110001 test 541: 000110011 test 542: 000110101 test 543: 000110111 test 544: 000111001 test 545: 000111011 test 546: 000111101 test 547: 000111111 test 548: 001000001 test 549: 001000011 test 550: 001000101 test 551: 001000111 test 552: 001001001 test 553: 001001011 test 554: 001001101 test 555: 001001111 test 556: 001010001 test 557: 001010011 test 558: 001010101 test 559: 001010111 test 560: 001011001 test 561: 001011011 test 562: 001011101 test 563: 001011111 test 564: 001100001 test 565: 001100011 test 566: 001100101 test 567: 001100111 test 568: 001101001 test 569: 001101011 test 570: 001101101 test 571: 001101111 test 572: 001110001 test 573: 001110011 test 574: 001110101 test 575: 001110111 test 576: 001111001 test 577: 001111011 test 578: 001111101 test 579: 001111111 test 580: 010000001 test 581: 010000011 test 582: 010000101 test 583: 010000111 test 584: 010001001 test 585: 010001011 test 586: 010001101 test 587: 010001111 test 588: 010010001 test 589: 010010011 test 590: 010010101 test 591: 010010111 test 592: 010011001 test 593: 010011011 test 594: 010011101 test 595: 010011111 test 596: 010100001 test 597: 010100011 test 598: 010100101 test 599: 010100111 test 600: 010101001 test 601: 010101011 test 602: 010101101 test 603: 010101111 test 604: 010110001 test 605: 010110011 test 606: 010110101 test 607: 010110111 test 608: 010111001 test 609: 010111011 test 610: 010111101 test 611: 010111111 test 612: 011000001 test 613: 011000011 test 614: 011000101 test 615: 011000111 test 616: 011001001 test 617: 011001011 test 618: 011001101 test 619: 011001111 test 620: 011010001 test 621: 011010011 test 622: 011010101 test 623: 011010111 test 624: 011011001 test 625: 011011011 test 626: 011011101 test 627: 011011111 test 628: 011100001 test 629: 011100011 test 630: 011100101 test 631: 011100111 test 632: 011101001 test 633: 011101011 test 634: 011101101 test 635: 011101111 test 636: 011110001 test 637: 011110011 test 638: 011110101 test 639: 011110111 test 640: 011111001 test 641: 011111011 test 642: 011111101 test 643: 011111111 test 644: 100000001 test 645: 100000011 test 646: 100000101 test 647: 100000111 test 648: 100001001 test 649: 100001011 test 650: 100001101 test 651: 100001111 test 652: 100010001 test 653: 100010011 test 654: 100010101 test 655: 100010111 test 656: 100011001 test 657: 100011011 test 658: 100011101 test 659: 100011111 test 660: 100100001 test 661: 100100011 test 662: 100100101 test 663: 100100111 test 664: 100101001 test 665: 100101011 test 666: 100101101 test 667: 100101111 test 668: 100110001 test 669: 100110011 test 670: 100110101 test 671: 100110111 test 672: 100111001 test 673: 100111011 test 674: 100111101 test 675: 100111111 test 676: 101000001 test 677: 101000011 test 678: 101000101 test 679: 101000111 test 680: 101001001 test 681: 101001011 test 682: 101001101 test 683: 101001111 test 684: 101010001 test 685: 101010011 test 686: 101010101 test 687: 101010111 test 688: 101011001 test 689: 101011011 test 690: 101011101 test 691: 101011111 test 692: 101100001 test 693: 101100011 test 694: 101100101 test 695: 101100111 test 696: 101101001 test 697: 101101011 test 698: 101101101 test 699: 101101111 test 700: 101110001 test 701: 101110011 test 702: 101110101 test 703: 101110111 test 704: 101111001 test 705: 101111011 test 706: 101111101 test 707: 101111111 test 708: 110000001 test 709: 110000011 test 710: 110000101 test 711: 110000111 test 712: 110001001 test 713: 110001011 test 714: 110001101 test 715: 110001111 test 716: 110010001 test 717: 110010011 test 718: 110010101 test 719: 110010111 test 720: 110011001 test 721: 110011011 test 722: 110011101 test 723: 110011111 test 724: 110100001 test 725: 110100011 test 726: 110100101 test 727: 110100111 test 728: 110101001 test 729: 110101011 test 730: 110101101 test 731: 110101111 test 732: 110110001 test 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test 1410: 011110111 test 1411: 011111001 test 1412: 011111011 test 1413: 011111101 test 1414: 011111111 test 1415: 100000001 test 1416: 100000011 test 1417: 100000101 test 1418: 100000111 test 1419: 100001001 test 1420: 100001011 test 1421: 100001101 test 1422: 100001111 test 1423: 100010001 test 1424: 100010011 test 1425: 100010101 test 1426: 100010111 test 1427: 100011001 test 1428: 100011011 test 1429: 100011101 test 1430: 100011111 test 1431: 100100001 test 1432: 100100011 test 1433: 100100101 test 1434: 100100111 test 1435: 100101001 test 1436: 100101011 test 1437: 100101101 test 1438: 100101111 test 1439: 100110001 test 1440: 100110011 test 1441: 100110101 test 1442: 100110111 test 1443: 100111001 test 1444: 100111011 test 1445: 100111101 test 1446: 100111111 test 1447: 101000001 test 1448: 101000011 test 1449: 101000101 test 1450: 101000111 test 1451: 101001001 test 1452: 101001011 test 1453: 101001101 test 1454: 101001111 test 1455: 101010001 test 1456: 101010011 test 1457: 101010101 test 1458: 101010111 test 1459: 101011001 test 1460: 101011011 test 1461: 101011101 test 1462: 101011111 test 1463: 101100001 test 1464: 101100011 test 1465: 101100101 test 1466: 101100111 test 1467: 101101001 test 1468: 101101011 test 1469: 101101101 test 1470: 101101111 test 1471: 101110001 test 1472: 101110011 test 1473: 101110101 test 1474: 101110111 test 1475: 101111001 test 1476: 101111011 test 1477: 101111101 test 1478: 101111111 test 1479: 110000001 test 1480: 110000011 test 1481: 110000101 test 1482: 110000111 test 1483: 110001001 test 1484: 110001011 test 1485: 110001101 test 1486: 110001111 test 1487: 110010001 test 1488: 110010011 test 1489: 110010101 test 1490: 110010111 test 1491: 110011001 test 1492: 110011011 test 1493: 110011101 test 1494: 110011111 test 1495: 110100001 test 1496: 110100011 test 1497: 110100101 test 1498: 110100111 test 1499: 110101001 test 1500: 110101011 test 1501: 110101101 test 1502: 110101111 test 1503: 110110001 test 1504: 110110011 test 1505: 110110101 test 1506: 110110111 test 1507: 110111001 test 1508: 110111011 test 1509: 110111101 test 1510: 110111111 test 1511: 111000001 test 1512: 111000011 test 1513: 111000101 test 1514: 111000111 test 1515: 111001001 test 1516: 111001011 test 1517: 111001101 test 1518: 111001111 test 1519: 111010001 test 1520: 111010011 test 1521: 111010101 test 1522: 111010111 test 1523: 111011001 test 1524: 111011011 test 1525: 111011101 test 1526: 111011111 test 1527: 111100001 test 1528: 111100011 test 1529: 111100101 test 1530: 111100111 test 1531: 111101001 test 1532: 111101011 test 1533: 111101101 test 1534: 111101111 test 1535: 111110001 test 1536: 111110011 test 1537: 111110101 test 1538: 111110111 test 1539: 111111001 test 1540: 111111011 test 1541: 111111101 test 1542: 111111110 test 1543: 111111110111111110111111110 end: END summary column 1: offset 0, mask 0x8000 column 2: offset 0, mask 0x4000 column 3: offset 0, mask 0x2000 column 4: offset 0, mask 0x1000 column 5: offset 0, mask 0x0010 column 6: offset 0, mask 0x0008 column 7: offset 0, mask 0x0004 column 8: offset 0, mask 0x0002 column 9: offset 0, mask 0x0001 column 10: offset 0, mask 0x0400 column 11: offset 0, mask 0x0200 column 12: offset 0, mask 0x0100 column 13: offset 1, mask 0x8000 column 14: offset 1, mask 0x0001 column 15: offset 1, mask 0x0002 column 16: offset 1, mask 0x0004 column 17: offset 1, mask 0x0008 column 18: offset 1, mask 0x0010 column 19: offset 1, mask 0x2000 column 20: offset 1, mask 0x1000 column 21: offset 1, mask 0x0800 column 22: offset 1, mask 0x0400 column 23: offset 1, mask 0x0020 column 24: offset 1, mask 0x0040 column 25: offset 1, mask 0x0080 column 26: offset 2, mask 0x0001 column 27: offset 2, mask 0x0002 direction bits (1=input) 0x08E1 0x4310 0xFFFA 0xFFFF 0xF0FF pullup bits (1=pullup) 0x0000 0x0000 0x0000 0x0000 0x0000 test step out_data dont care 1: 0x0001 0x0010 0x0002 0x0000 0x0000 2: 0x0001 0x0010 0x0002 0x0000 0x0000 3: 0x0003 0x0010 0x0002 0x0000 0x0000 4: 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0xB8CF 0x0002 0x0000 0x0000 1518: 0xF71E 0xB8CF 0x0003 0x0000 0x0000 1519: 0xF71E 0xB82F 0x0002 0x0000 0x0000 1520: 0xF71E 0xB82F 0x0003 0x0000 0x0000 1521: 0xF71E 0xB8AF 0x0002 0x0000 0x0000 1522: 0xF71E 0xB8AF 0x0003 0x0000 0x0000 1523: 0xF71E 0xB86F 0x0002 0x0000 0x0000 1524: 0xF71E 0xB86F 0x0003 0x0000 0x0000 1525: 0xF71E 0xB8EF 0x0002 0x0000 0x0000 1526: 0xF71E 0xB8EF 0x0003 0x0000 0x0000 1527: 0xF71E 0xBC0F 0x0002 0x0000 0x0000 1528: 0xF71E 0xBC0F 0x0003 0x0000 0x0000 1529: 0xF71E 0xBC8F 0x0002 0x0000 0x0000 1530: 0xF71E 0xBC8F 0x0003 0x0000 0x0000 1531: 0xF71E 0xBC4F 0x0002 0x0000 0x0000 1532: 0xF71E 0xBC4F 0x0003 0x0000 0x0000 1533: 0xF71E 0xBCCF 0x0002 0x0000 0x0000 1534: 0xF71E 0xBCCF 0x0003 0x0000 0x0000 1535: 0xF71E 0xBC2F 0x0002 0x0000 0x0000 1536: 0xF71E 0xBC2F 0x0003 0x0000 0x0000 1537: 0xF71E 0xBCAF 0x0002 0x0000 0x0000 1538: 0xF71E 0xBCAF 0x0003 0x0000 0x0000 1539: 0xF71E 0xBC6F 0x0002 0x0000 0x0000 1540: 0xF71E 0xBC6F 0x0003 0x0000 0x0000 1541: 0xF71E 0xBCEF 0x0002 0x0000 0x0000 1542: 0xF71E 0xBCEF 0x0001 0x0000 0x0000 1543: 0xF71E 0xBCEF 0x0001 0x0000 0x0000 PINs used (in edge connector order) (G=ground,P=power) SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBB LETTER ABCDEFHJKLMNPRSTUVABCDEFHJKLMNPRSTUVABCDEFHJKLMNPRSTUVABCDEFHJKLMNPRSTUV SIDE 111111111111111111222222222222222222111111111111111111222222222222222222 USAGE IIII IIII IIII G P GIIIIOIIIIOIIIIO G P G UUT has 24 inputs UUT has 3 outputs contains 27 pins/columns 39 pins are not used contains 1543 'test steps' M119 REV B 3 8-input NAND PINS Main menu Mon Jul 27 15:12:58 2015 test file is: tests\m119.tst delay is: 0 trigger is: 1 1 read test file 2 set test delay 3 set test trigger 4 run test 5 output loading test 8 diags 9 exit UUT power is okay Mon Jul 27 15:13:12 2015 space single step O run once (one test, all steps) F run, stop on fail G go (run tests N run, stop on fail, no print S scope (run, no print) C toggle comment printout + increase speed (less delay) - decrease speed (more delay)(slower) Q quit test scope (run, no print) ppppppppppppppppp space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C toggle comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDDEFHJFHJKKLMNPMNPRRSTUV SIDE 111122222111122222111122222 DIRECTION IIIIIIIIOIIIIIIIIOIIIIIIIIO all fails was lo 000000000000000000000000000 falling vvvvvvvvvvvvvvvvvvvvvvvvvvv rising ^^^^^^^^^^^^^^^^^^^^^^^^^^^ was hi 111111111111111111111111111 total fails 0, total passes 17 Main menu Mon Jul 27 15:13:27 2015 test file is: tests\m119.tst delay is: 0 trigger is: 1 1 read test file 2 set test delay 3 set test trigger 4 run test 5 output loading test 8 diags 9 exit Enter test file name? trying to open test file: tests\m119.tst reading test file: tests\m119.tst comment: M119 REV B 3 8-input NAND comment: pins: PINS pins: 1 I AA1 E1-12 pins: 2 I AB1 E1-11 pins: 3 I AC1 E1-5 pins: 4 I AD1 E1-6 pins: 5 I AD2 E1-4 pins: 6 I AE2 E1-3 pins: 7 I AF2 E1-2 pins: 8 I AH2 E1-1 pins: 9 O AJ2 E1-8 pins: 10 I AF1 E2-12 pins: 11 I AH1 E2-11 pins: 12 I AJ1 E2-5 pins: 13 I AK1 E2-6 pins: 14 I AK2 E2-4 pins: 15 I AL2 E2-3 pins: 16 I AM2 E2-2 pins: 17 I AN2 E2-1 pins: 18 O AP2 E2-8 pins: 19 I AM1 E3-12 pins: 20 I AN1 E3-11 pins: 21 I AP1 E3-5 pins: 22 I AR1 E3-6 pins: 23 I AR2 E3-4 pins: 24 I AS2 E3-3 pins: 25 I AT2 E3-2 pins: 26 I AU2 E3-1 pins: 27 O AV2 E3-8 pins: direction: IIIIIIIIOIIIIIIIIOIIIIIIIIO test 1: 000000001000000001000000001 test 2: 000000001 test 3: 000000011 test 4: 000000101 test 5: 000000111 test 6: 000001001 test 7: 000001011 test 8: 000001101 test 9: 000001111 test 10: 000010001 test 11: 000010011 test 12: 000010101 test 13: 000010111 test 14: 000011001 test 15: 000011011 test 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test 120: 011101101 test 121: 011101111 test 122: 011110001 test 123: 011110011 test 124: 011110101 test 125: 011110111 test 126: 011111001 test 127: 011111011 test 128: 011111101 test 129: 011111111 test 130: 100000001 test 131: 100000011 test 132: 100000101 test 133: 100000111 test 134: 100001001 test 135: 100001011 test 136: 100001101 test 137: 100001111 test 138: 100010001 test 139: 100010011 test 140: 100010101 test 141: 100010111 test 142: 100011001 test 143: 100011011 test 144: 100011101 test 145: 100011111 test 146: 100100001 test 147: 100100011 test 148: 100100101 test 149: 100100111 test 150: 100101001 test 151: 100101011 test 152: 100101101 test 153: 100101111 test 154: 100110001 test 155: 100110011 test 156: 100110101 test 157: 100110111 test 158: 100111001 test 159: 100111011 test 160: 100111101 test 161: 100111111 test 162: 101000001 test 163: 101000011 test 164: 101000101 test 165: 101000111 test 166: 101001001 test 167: 101001011 test 168: 101001101 test 169: 101001111 test 170: 101010001 test 171: 101010011 test 172: 101010101 test 173: 101010111 test 174: 101011001 test 175: 101011011 test 176: 101011101 test 177: 101011111 test 178: 101100001 test 179: 101100011 test 180: 101100101 test 181: 101100111 test 182: 101101001 test 183: 101101011 test 184: 101101101 test 185: 101101111 test 186: 101110001 test 187: 101110011 test 188: 101110101 test 189: 101110111 test 190: 101111001 test 191: 101111011 test 192: 101111101 test 193: 101111111 test 194: 110000001 test 195: 110000011 test 196: 110000101 test 197: 110000111 test 198: 110001001 test 199: 110001011 test 200: 110001101 test 201: 110001111 test 202: 110010001 test 203: 110010011 test 204: 110010101 test 205: 110010111 test 206: 110011001 test 207: 110011011 test 208: 110011101 test 209: 110011111 test 210: 110100001 test 211: 110100011 test 212: 110100101 test 213: 110100111 test 214: 110101001 test 215: 110101011 test 216: 110101101 test 217: 110101111 test 218: 110110001 test 219: 110110011 test 220: 110110101 test 221: 110110111 test 222: 110111001 test 223: 110111011 test 224: 110111101 test 225: 110111111 test 226: 111000001 test 227: 111000011 test 228: 111000101 test 229: 111000111 test 230: 111001001 test 231: 111001011 test 232: 111001101 test 233: 111001111 test 234: 111010001 test 235: 111010011 test 236: 111010101 test 237: 111010111 test 238: 111011001 test 239: 111011011 test 240: 111011101 test 241: 111011111 test 242: 111100001 test 243: 111100011 test 244: 111100101 test 245: 111100111 test 246: 111101001 test 247: 111101011 test 248: 111101101 test 249: 111101111 test 250: 111110001 test 251: 111110011 test 252: 111110101 test 253: 111110111 test 254: 111111001 test 255: 111111011 test 256: 111111101 test 257: 111111110 test 258: 000000001 test 259: 000000001 test 260: 000000011 test 261: 000000101 test 262: 000000111 test 263: 000001001 test 264: 000001011 test 265: 000001101 test 266: 000001111 test 267: 000010001 test 268: 000010011 test 269: 000010101 test 270: 000010111 test 271: 000011001 test 272: 000011011 test 273: 000011101 test 274: 000011111 test 275: 000100001 test 276: 000100011 test 277: 000100101 test 278: 000100111 test 279: 000101001 test 280: 000101011 test 281: 000101101 test 282: 000101111 test 283: 000110001 test 284: 000110011 test 285: 000110101 test 286: 000110111 test 287: 000111001 test 288: 000111011 test 289: 000111101 test 290: 000111111 test 291: 001000001 test 292: 001000011 test 293: 001000101 test 294: 001000111 test 295: 001001001 test 296: 001001011 test 297: 001001101 test 298: 001001111 test 299: 001010001 test 300: 001010011 test 301: 001010101 test 302: 001010111 test 303: 001011001 test 304: 001011011 test 305: 001011101 test 306: 001011111 test 307: 001100001 test 308: 001100011 test 309: 001100101 test 310: 001100111 test 311: 001101001 test 312: 001101011 test 313: 001101101 test 314: 001101111 test 315: 001110001 test 316: 001110011 test 317: 001110101 test 318: 001110111 test 319: 001111001 test 320: 001111011 test 321: 001111101 test 322: 001111111 test 323: 010000001 test 324: 010000011 test 325: 010000101 test 326: 010000111 test 327: 010001001 test 328: 010001011 test 329: 010001101 test 330: 010001111 test 331: 010010001 test 332: 010010011 test 333: 010010101 test 334: 010010111 test 335: 010011001 test 336: 010011011 test 337: 010011101 test 338: 010011111 test 339: 010100001 test 340: 010100011 test 341: 010100101 test 342: 010100111 test 343: 010101001 test 344: 010101011 test 345: 010101101 test 346: 010101111 test 347: 010110001 test 348: 010110011 test 349: 010110101 test 350: 010110111 test 351: 010111001 test 352: 010111011 test 353: 010111101 test 354: 010111111 test 355: 011000001 test 356: 011000011 test 357: 011000101 test 358: 011000111 test 359: 011001001 test 360: 011001011 test 361: 011001101 test 362: 011001111 test 363: 011010001 test 364: 011010011 test 365: 011010101 test 366: 011010111 test 367: 011011001 test 368: 011011011 test 369: 011011101 test 370: 011011111 test 371: 011100001 test 372: 011100011 test 373: 011100101 test 374: 011100111 test 375: 011101001 test 376: 011101011 test 377: 011101101 test 378: 011101111 test 379: 011110001 test 380: 011110011 test 381: 011110101 test 382: 011110111 test 383: 011111001 test 384: 011111011 test 385: 011111101 test 386: 011111111 test 387: 100000001 test 388: 100000011 test 389: 100000101 test 390: 100000111 test 391: 100001001 test 392: 100001011 test 393: 100001101 test 394: 100001111 test 395: 100010001 test 396: 100010011 test 397: 100010101 test 398: 100010111 test 399: 100011001 test 400: 100011011 test 401: 100011101 test 402: 100011111 test 403: 100100001 test 404: 100100011 test 405: 100100101 test 406: 100100111 test 407: 100101001 test 408: 100101011 test 409: 100101101 test 410: 100101111 test 411: 100110001 test 412: 100110011 test 413: 100110101 test 414: 100110111 test 415: 100111001 test 416: 100111011 test 417: 100111101 test 418: 100111111 test 419: 101000001 test 420: 101000011 test 421: 101000101 test 422: 101000111 test 423: 101001001 test 424: 101001011 test 425: 101001101 test 426: 101001111 test 427: 101010001 test 428: 101010011 test 429: 101010101 test 430: 101010111 test 431: 101011001 test 432: 101011011 test 433: 101011101 test 434: 101011111 test 435: 101100001 test 436: 101100011 test 437: 101100101 test 438: 101100111 test 439: 101101001 test 440: 101101011 test 441: 101101101 test 442: 101101111 test 443: 101110001 test 444: 101110011 test 445: 101110101 test 446: 101110111 test 447: 101111001 test 448: 101111011 test 449: 101111101 test 450: 101111111 test 451: 110000001 test 452: 110000011 test 453: 110000101 test 454: 110000111 test 455: 110001001 test 456: 110001011 test 457: 110001101 test 458: 110001111 test 459: 110010001 test 460: 110010011 test 461: 110010101 test 462: 110010111 test 463: 110011001 test 464: 110011011 test 465: 110011101 test 466: 110011111 test 467: 110100001 test 468: 110100011 test 469: 110100101 test 470: 110100111 test 471: 110101001 test 472: 110101011 test 473: 110101101 test 474: 110101111 test 475: 110110001 test 476: 110110011 test 477: 110110101 test 478: 110110111 test 479: 110111001 test 480: 110111011 test 481: 110111101 test 482: 110111111 test 483: 111000001 test 484: 111000011 test 485: 111000101 test 486: 111000111 test 487: 111001001 test 488: 111001011 test 489: 111001101 test 490: 111001111 test 491: 111010001 test 492: 111010011 test 493: 111010101 test 494: 111010111 test 495: 111011001 test 496: 111011011 test 497: 111011101 test 498: 111011111 test 499: 111100001 test 500: 111100011 test 501: 111100101 test 502: 111100111 test 503: 111101001 test 504: 111101011 test 505: 111101101 test 506: 111101111 test 507: 111110001 test 508: 111110011 test 509: 111110101 test 510: 111110111 test 511: 111111001 test 512: 111111011 test 513: 111111101 test 514: 111111110 test 515: 000000001 test 516: 000000001 test 517: 000000011 test 518: 000000101 test 519: 000000111 test 520: 000001001 test 521: 000001011 test 522: 000001101 test 523: 000001111 test 524: 000010001 test 525: 000010011 test 526: 000010101 test 527: 000010111 test 528: 000011001 test 529: 000011011 test 530: 000011101 test 531: 000011111 test 532: 000100001 test 533: 000100011 test 534: 000100101 test 535: 000100111 test 536: 000101001 test 537: 000101011 test 538: 000101101 test 539: 000101111 test 540: 000110001 test 541: 000110011 test 542: 000110101 test 543: 000110111 test 544: 000111001 test 545: 000111011 test 546: 000111101 test 547: 000111111 test 548: 001000001 test 549: 001000011 test 550: 001000101 test 551: 001000111 test 552: 001001001 test 553: 001001011 test 554: 001001101 test 555: 001001111 test 556: 001010001 test 557: 001010011 test 558: 001010101 test 559: 001010111 test 560: 001011001 test 561: 001011011 test 562: 001011101 test 563: 001011111 test 564: 001100001 test 565: 001100011 test 566: 001100101 test 567: 001100111 test 568: 001101001 test 569: 001101011 test 570: 001101101 test 571: 001101111 test 572: 001110001 test 573: 001110011 test 574: 001110101 test 575: 001110111 test 576: 001111001 test 577: 001111011 test 578: 001111101 test 579: 001111111 test 580: 010000001 test 581: 010000011 test 582: 010000101 test 583: 010000111 test 584: 010001001 test 585: 010001011 test 586: 010001101 test 587: 010001111 test 588: 010010001 test 589: 010010011 test 590: 010010101 test 591: 010010111 test 592: 010011001 test 593: 010011011 test 594: 010011101 test 595: 010011111 test 596: 010100001 test 597: 010100011 test 598: 010100101 test 599: 010100111 test 600: 010101001 test 601: 010101011 test 602: 010101101 test 603: 010101111 test 604: 010110001 test 605: 010110011 test 606: 010110101 test 607: 010110111 test 608: 010111001 test 609: 010111011 test 610: 010111101 test 611: 010111111 test 612: 011000001 test 613: 011000011 test 614: 011000101 test 615: 011000111 test 616: 011001001 test 617: 011001011 test 618: 011001101 test 619: 011001111 test 620: 011010001 test 621: 011010011 test 622: 011010101 test 623: 011010111 test 624: 011011001 test 625: 011011011 test 626: 011011101 test 627: 011011111 test 628: 011100001 test 629: 011100011 test 630: 011100101 test 631: 011100111 test 632: 011101001 test 633: 011101011 test 634: 011101101 test 635: 011101111 test 636: 011110001 test 637: 011110011 test 638: 011110101 test 639: 011110111 test 640: 011111001 test 641: 011111011 test 642: 011111101 test 643: 011111111 test 644: 100000001 test 645: 100000011 test 646: 100000101 test 647: 100000111 test 648: 100001001 test 649: 100001011 test 650: 100001101 test 651: 100001111 test 652: 100010001 test 653: 100010011 test 654: 100010101 test 655: 100010111 test 656: 100011001 test 657: 100011011 test 658: 100011101 test 659: 100011111 test 660: 100100001 test 661: 100100011 test 662: 100100101 test 663: 100100111 test 664: 100101001 test 665: 100101011 test 666: 100101101 test 667: 100101111 test 668: 100110001 test 669: 100110011 test 670: 100110101 test 671: 100110111 test 672: 100111001 test 673: 100111011 test 674: 100111101 test 675: 100111111 test 676: 101000001 test 677: 101000011 test 678: 101000101 test 679: 101000111 test 680: 101001001 test 681: 101001011 test 682: 101001101 test 683: 101001111 test 684: 101010001 test 685: 101010011 test 686: 101010101 test 687: 101010111 test 688: 101011001 test 689: 101011011 test 690: 101011101 test 691: 101011111 test 692: 101100001 test 693: 101100011 test 694: 101100101 test 695: 101100111 test 696: 101101001 test 697: 101101011 test 698: 101101101 test 699: 101101111 test 700: 101110001 test 701: 101110011 test 702: 101110101 test 703: 101110111 test 704: 101111001 test 705: 101111011 test 706: 101111101 test 707: 101111111 test 708: 110000001 test 709: 110000011 test 710: 110000101 test 711: 110000111 test 712: 110001001 test 713: 110001011 test 714: 110001101 test 715: 110001111 test 716: 110010001 test 717: 110010011 test 718: 110010101 test 719: 110010111 test 720: 110011001 test 721: 110011011 test 722: 110011101 test 723: 110011111 test 724: 110100001 test 725: 110100011 test 726: 110100101 test 727: 110100111 test 728: 110101001 test 729: 110101011 test 730: 110101101 test 731: 110101111 test 732: 110110001 test 733: 110110011 test 734: 110110101 test 735: 110110111 test 736: 110111001 test 737: 110111011 test 738: 110111101 test 739: 110111111 test 740: 111000001 test 741: 111000011 test 742: 111000101 test 743: 111000111 test 744: 111001001 test 745: 111001011 test 746: 111001101 test 747: 111001111 test 748: 111010001 test 749: 111010011 test 750: 111010101 test 751: 111010111 test 752: 111011001 test 753: 111011011 test 754: 111011101 test 755: 111011111 test 756: 111100001 test 757: 111100011 test 758: 111100101 test 759: 111100111 test 760: 111101001 test 761: 111101011 test 762: 111101101 test 763: 111101111 test 764: 111110001 test 765: 111110011 test 766: 111110101 test 767: 111110111 test 768: 111111001 test 769: 111111011 test 770: 111111101 test 771: 111111110 test 772: 000000001 test 773: 000000001000000001000000001 test 774: 111111110111111110111111110 test 775: 000000001 test 776: 000000011 test 777: 000000101 test 778: 000000111 test 779: 000001001 test 780: 000001011 test 781: 000001101 test 782: 000001111 test 783: 000010001 test 784: 000010011 test 785: 000010101 test 786: 000010111 test 787: 000011001 test 788: 000011011 test 789: 000011101 test 790: 000011111 test 791: 000100001 test 792: 000100011 test 793: 000100101 test 794: 000100111 test 795: 000101001 test 796: 000101011 test 797: 000101101 test 798: 000101111 test 799: 000110001 test 800: 000110011 test 801: 000110101 test 802: 000110111 test 803: 000111001 test 804: 000111011 test 805: 000111101 test 806: 000111111 test 807: 001000001 test 808: 001000011 test 809: 001000101 test 810: 001000111 test 811: 001001001 test 812: 001001011 test 813: 001001101 test 814: 001001111 test 815: 001010001 test 816: 001010011 test 817: 001010101 test 818: 001010111 test 819: 001011001 test 820: 001011011 test 821: 001011101 test 822: 001011111 test 823: 001100001 test 824: 001100011 test 825: 001100101 test 826: 001100111 test 827: 001101001 test 828: 001101011 test 829: 001101101 test 830: 001101111 test 831: 001110001 test 832: 001110011 test 833: 001110101 test 834: 001110111 test 835: 001111001 test 836: 001111011 test 837: 001111101 test 838: 001111111 test 839: 010000001 test 840: 010000011 test 841: 010000101 test 842: 010000111 test 843: 010001001 test 844: 010001011 test 845: 010001101 test 846: 010001111 test 847: 010010001 test 848: 010010011 test 849: 010010101 test 850: 010010111 test 851: 010011001 test 852: 010011011 test 853: 010011101 test 854: 010011111 test 855: 010100001 test 856: 010100011 test 857: 010100101 test 858: 010100111 test 859: 010101001 test 860: 010101011 test 861: 010101101 test 862: 010101111 test 863: 010110001 test 864: 010110011 test 865: 010110101 test 866: 010110111 test 867: 010111001 test 868: 010111011 test 869: 010111101 test 870: 010111111 test 871: 011000001 test 872: 011000011 test 873: 011000101 test 874: 011000111 test 875: 011001001 test 876: 011001011 test 877: 011001101 test 878: 011001111 test 879: 011010001 test 880: 011010011 test 881: 011010101 test 882: 011010111 test 883: 011011001 test 884: 011011011 test 885: 011011101 test 886: 011011111 test 887: 011100001 test 888: 011100011 test 889: 011100101 test 890: 011100111 test 891: 011101001 test 892: 011101011 test 893: 011101101 test 894: 011101111 test 895: 011110001 test 896: 011110011 test 897: 011110101 test 898: 011110111 test 899: 011111001 test 900: 011111011 test 901: 011111101 test 902: 011111111 test 903: 100000001 test 904: 100000011 test 905: 100000101 test 906: 100000111 test 907: 100001001 test 908: 100001011 test 909: 100001101 test 910: 100001111 test 911: 100010001 test 912: 100010011 test 913: 100010101 test 914: 100010111 test 915: 100011001 test 916: 100011011 test 917: 100011101 test 918: 100011111 test 919: 100100001 test 920: 100100011 test 921: 100100101 test 922: 100100111 test 923: 100101001 test 924: 100101011 test 925: 100101101 test 926: 100101111 test 927: 100110001 test 928: 100110011 test 929: 100110101 test 930: 100110111 test 931: 100111001 test 932: 100111011 test 933: 100111101 test 934: 100111111 test 935: 101000001 test 936: 101000011 test 937: 101000101 test 938: 101000111 test 939: 101001001 test 940: 101001011 test 941: 101001101 test 942: 101001111 test 943: 101010001 test 944: 101010011 test 945: 101010101 test 946: 101010111 test 947: 101011001 test 948: 101011011 test 949: 101011101 test 950: 101011111 test 951: 101100001 test 952: 101100011 test 953: 101100101 test 954: 101100111 test 955: 101101001 test 956: 101101011 test 957: 101101101 test 958: 101101111 test 959: 101110001 test 960: 101110011 test 961: 101110101 test 962: 101110111 test 963: 101111001 test 964: 101111011 test 965: 101111101 test 966: 101111111 test 967: 110000001 test 968: 110000011 test 969: 110000101 test 970: 110000111 test 971: 110001001 test 972: 110001011 test 973: 110001101 test 974: 110001111 test 975: 110010001 test 976: 110010011 test 977: 110010101 test 978: 110010111 test 979: 110011001 test 980: 110011011 test 981: 110011101 test 982: 110011111 test 983: 110100001 test 984: 110100011 test 985: 110100101 test 986: 110100111 test 987: 110101001 test 988: 110101011 test 989: 110101101 test 990: 110101111 test 991: 110110001 test 992: 110110011 test 993: 110110101 test 994: 110110111 test 995: 110111001 test 996: 110111011 test 997: 110111101 test 998: 110111111 test 999: 111000001 test 1000: 111000011 test 1001: 111000101 test 1002: 111000111 test 1003: 111001001 test 1004: 111001011 test 1005: 111001101 test 1006: 111001111 test 1007: 111010001 test 1008: 111010011 test 1009: 111010101 test 1010: 111010111 test 1011: 111011001 test 1012: 111011011 test 1013: 111011101 test 1014: 111011111 test 1015: 111100001 test 1016: 111100011 test 1017: 111100101 test 1018: 111100111 test 1019: 111101001 test 1020: 111101011 test 1021: 111101101 test 1022: 111101111 test 1023: 111110001 test 1024: 111110011 test 1025: 111110101 test 1026: 111110111 test 1027: 111111001 test 1028: 111111011 test 1029: 111111101 test 1030: 111111110 test 1031: 000000001 test 1032: 000000011 test 1033: 000000101 test 1034: 000000111 test 1035: 000001001 test 1036: 000001011 test 1037: 000001101 test 1038: 000001111 test 1039: 000010001 test 1040: 000010011 test 1041: 000010101 test 1042: 000010111 test 1043: 000011001 test 1044: 000011011 test 1045: 000011101 test 1046: 000011111 test 1047: 000100001 test 1048: 000100011 test 1049: 000100101 test 1050: 000100111 test 1051: 000101001 test 1052: 000101011 test 1053: 000101101 test 1054: 000101111 test 1055: 000110001 test 1056: 000110011 test 1057: 000110101 test 1058: 000110111 test 1059: 000111001 test 1060: 000111011 test 1061: 000111101 test 1062: 000111111 test 1063: 001000001 test 1064: 001000011 test 1065: 001000101 test 1066: 001000111 test 1067: 001001001 test 1068: 001001011 test 1069: 001001101 test 1070: 001001111 test 1071: 001010001 test 1072: 001010011 test 1073: 001010101 test 1074: 001010111 test 1075: 001011001 test 1076: 001011011 test 1077: 001011101 test 1078: 001011111 test 1079: 001100001 test 1080: 001100011 test 1081: 001100101 test 1082: 001100111 test 1083: 001101001 test 1084: 001101011 test 1085: 001101101 test 1086: 001101111 test 1087: 001110001 test 1088: 001110011 test 1089: 001110101 test 1090: 001110111 test 1091: 001111001 test 1092: 001111011 test 1093: 001111101 test 1094: 001111111 test 1095: 010000001 test 1096: 010000011 test 1097: 010000101 test 1098: 010000111 test 1099: 010001001 test 1100: 010001011 test 1101: 010001101 test 1102: 010001111 test 1103: 010010001 test 1104: 010010011 test 1105: 010010101 test 1106: 010010111 test 1107: 010011001 test 1108: 010011011 test 1109: 010011101 test 1110: 010011111 test 1111: 010100001 test 1112: 010100011 test 1113: 010100101 test 1114: 010100111 test 1115: 010101001 test 1116: 010101011 test 1117: 010101101 test 1118: 010101111 test 1119: 010110001 test 1120: 010110011 test 1121: 010110101 test 1122: 010110111 test 1123: 010111001 test 1124: 010111011 test 1125: 010111101 test 1126: 010111111 test 1127: 011000001 test 1128: 011000011 test 1129: 011000101 test 1130: 011000111 test 1131: 011001001 test 1132: 011001011 test 1133: 011001101 test 1134: 011001111 test 1135: 011010001 test 1136: 011010011 test 1137: 011010101 test 1138: 011010111 test 1139: 011011001 test 1140: 011011011 test 1141: 011011101 test 1142: 011011111 test 1143: 011100001 test 1144: 011100011 test 1145: 011100101 test 1146: 011100111 test 1147: 011101001 test 1148: 011101011 test 1149: 011101101 test 1150: 011101111 test 1151: 011110001 test 1152: 011110011 test 1153: 011110101 test 1154: 011110111 test 1155: 011111001 test 1156: 011111011 test 1157: 011111101 test 1158: 011111111 test 1159: 100000001 test 1160: 100000011 test 1161: 100000101 test 1162: 100000111 test 1163: 100001001 test 1164: 100001011 test 1165: 100001101 test 1166: 100001111 test 1167: 100010001 test 1168: 100010011 test 1169: 100010101 test 1170: 100010111 test 1171: 100011001 test 1172: 100011011 test 1173: 100011101 test 1174: 100011111 test 1175: 100100001 test 1176: 100100011 test 1177: 100100101 test 1178: 100100111 test 1179: 100101001 test 1180: 100101011 test 1181: 100101101 test 1182: 100101111 test 1183: 100110001 test 1184: 100110011 test 1185: 100110101 test 1186: 100110111 test 1187: 100111001 test 1188: 100111011 test 1189: 100111101 test 1190: 100111111 test 1191: 101000001 test 1192: 101000011 test 1193: 101000101 test 1194: 101000111 test 1195: 101001001 test 1196: 101001011 test 1197: 101001101 test 1198: 101001111 test 1199: 101010001 test 1200: 101010011 test 1201: 101010101 test 1202: 101010111 test 1203: 101011001 test 1204: 101011011 test 1205: 101011101 test 1206: 101011111 test 1207: 101100001 test 1208: 101100011 test 1209: 101100101 test 1210: 101100111 test 1211: 101101001 test 1212: 101101011 test 1213: 101101101 test 1214: 101101111 test 1215: 101110001 test 1216: 101110011 test 1217: 101110101 test 1218: 101110111 test 1219: 101111001 test 1220: 101111011 test 1221: 101111101 test 1222: 101111111 test 1223: 110000001 test 1224: 110000011 test 1225: 110000101 test 1226: 110000111 test 1227: 110001001 test 1228: 110001011 test 1229: 110001101 test 1230: 110001111 test 1231: 110010001 test 1232: 110010011 test 1233: 110010101 test 1234: 110010111 test 1235: 110011001 test 1236: 110011011 test 1237: 110011101 test 1238: 110011111 test 1239: 110100001 test 1240: 110100011 test 1241: 110100101 test 1242: 110100111 test 1243: 110101001 test 1244: 110101011 test 1245: 110101101 test 1246: 110101111 test 1247: 110110001 test 1248: 110110011 test 1249: 110110101 test 1250: 110110111 test 1251: 110111001 test 1252: 110111011 test 1253: 110111101 test 1254: 110111111 test 1255: 111000001 test 1256: 111000011 test 1257: 111000101 test 1258: 111000111 test 1259: 111001001 test 1260: 111001011 test 1261: 111001101 test 1262: 111001111 test 1263: 111010001 test 1264: 111010011 test 1265: 111010101 test 1266: 111010111 test 1267: 111011001 test 1268: 111011011 test 1269: 111011101 test 1270: 111011111 test 1271: 111100001 test 1272: 111100011 test 1273: 111100101 test 1274: 111100111 test 1275: 111101001 test 1276: 111101011 test 1277: 111101101 test 1278: 111101111 test 1279: 111110001 test 1280: 111110011 test 1281: 111110101 test 1282: 111110111 test 1283: 111111001 test 1284: 111111011 test 1285: 111111101 test 1286: 111111110 test 1287: 000000001 test 1288: 000000011 test 1289: 000000101 test 1290: 000000111 test 1291: 000001001 test 1292: 000001011 test 1293: 000001101 test 1294: 000001111 test 1295: 000010001 test 1296: 000010011 test 1297: 000010101 test 1298: 000010111 test 1299: 000011001 test 1300: 000011011 test 1301: 000011101 test 1302: 000011111 test 1303: 000100001 test 1304: 000100011 test 1305: 000100101 test 1306: 000100111 test 1307: 000101001 test 1308: 000101011 test 1309: 000101101 test 1310: 000101111 test 1311: 000110001 test 1312: 000110011 test 1313: 000110101 test 1314: 000110111 test 1315: 000111001 test 1316: 000111011 test 1317: 000111101 test 1318: 000111111 test 1319: 001000001 test 1320: 001000011 test 1321: 001000101 test 1322: 001000111 test 1323: 001001001 test 1324: 001001011 test 1325: 001001101 test 1326: 001001111 test 1327: 001010001 test 1328: 001010011 test 1329: 001010101 test 1330: 001010111 test 1331: 001011001 test 1332: 001011011 test 1333: 001011101 test 1334: 001011111 test 1335: 001100001 test 1336: 001100011 test 1337: 001100101 test 1338: 001100111 test 1339: 001101001 test 1340: 001101011 test 1341: 001101101 test 1342: 001101111 test 1343: 001110001 test 1344: 001110011 test 1345: 001110101 test 1346: 001110111 test 1347: 001111001 test 1348: 001111011 test 1349: 001111101 test 1350: 001111111 test 1351: 010000001 test 1352: 010000011 test 1353: 010000101 test 1354: 010000111 test 1355: 010001001 test 1356: 010001011 test 1357: 010001101 test 1358: 010001111 test 1359: 010010001 test 1360: 010010011 test 1361: 010010101 test 1362: 010010111 test 1363: 010011001 test 1364: 010011011 test 1365: 010011101 test 1366: 010011111 test 1367: 010100001 test 1368: 010100011 test 1369: 010100101 test 1370: 010100111 test 1371: 010101001 test 1372: 010101011 test 1373: 010101101 test 1374: 010101111 test 1375: 010110001 test 1376: 010110011 test 1377: 010110101 test 1378: 010110111 test 1379: 010111001 test 1380: 010111011 test 1381: 010111101 test 1382: 010111111 test 1383: 011000001 test 1384: 011000011 test 1385: 011000101 test 1386: 011000111 test 1387: 011001001 test 1388: 011001011 test 1389: 011001101 test 1390: 011001111 test 1391: 011010001 test 1392: 011010011 test 1393: 011010101 test 1394: 011010111 test 1395: 011011001 test 1396: 011011011 test 1397: 011011101 test 1398: 011011111 test 1399: 011100001 test 1400: 011100011 test 1401: 011100101 test 1402: 011100111 test 1403: 011101001 test 1404: 011101011 test 1405: 011101101 test 1406: 011101111 test 1407: 011110001 test 1408: 011110011 test 1409: 011110101 test 1410: 011110111 test 1411: 011111001 test 1412: 011111011 test 1413: 011111101 test 1414: 011111111 test 1415: 100000001 test 1416: 100000011 test 1417: 100000101 test 1418: 100000111 test 1419: 100001001 test 1420: 100001011 test 1421: 100001101 test 1422: 100001111 test 1423: 100010001 test 1424: 100010011 test 1425: 100010101 test 1426: 100010111 test 1427: 100011001 test 1428: 100011011 test 1429: 100011101 test 1430: 100011111 test 1431: 100100001 test 1432: 100100011 test 1433: 100100101 test 1434: 100100111 test 1435: 100101001 test 1436: 100101011 test 1437: 100101101 test 1438: 100101111 test 1439: 100110001 test 1440: 100110011 test 1441: 100110101 test 1442: 100110111 test 1443: 100111001 test 1444: 100111011 test 1445: 100111101 test 1446: 100111111 test 1447: 101000001 test 1448: 101000011 test 1449: 101000101 test 1450: 101000111 test 1451: 101001001 test 1452: 101001011 test 1453: 101001101 test 1454: 101001111 test 1455: 101010001 test 1456: 101010011 test 1457: 101010101 test 1458: 101010111 test 1459: 101011001 test 1460: 101011011 test 1461: 101011101 test 1462: 101011111 test 1463: 101100001 test 1464: 101100011 test 1465: 101100101 test 1466: 101100111 test 1467: 101101001 test 1468: 101101011 test 1469: 101101101 test 1470: 101101111 test 1471: 101110001 test 1472: 101110011 test 1473: 101110101 test 1474: 101110111 test 1475: 101111001 test 1476: 101111011 test 1477: 101111101 test 1478: 101111111 test 1479: 110000001 test 1480: 110000011 test 1481: 110000101 test 1482: 110000111 test 1483: 110001001 test 1484: 110001011 test 1485: 110001101 test 1486: 110001111 test 1487: 110010001 test 1488: 110010011 test 1489: 110010101 test 1490: 110010111 test 1491: 110011001 test 1492: 110011011 test 1493: 110011101 test 1494: 110011111 test 1495: 110100001 test 1496: 110100011 test 1497: 110100101 test 1498: 110100111 test 1499: 110101001 test 1500: 110101011 test 1501: 110101101 test 1502: 110101111 test 1503: 110110001 test 1504: 110110011 test 1505: 110110101 test 1506: 110110111 test 1507: 110111001 test 1508: 110111011 test 1509: 110111101 test 1510: 110111111 test 1511: 111000001 test 1512: 111000011 test 1513: 111000101 test 1514: 111000111 test 1515: 111001001 test 1516: 111001011 test 1517: 111001101 test 1518: 111001111 test 1519: 111010001 test 1520: 111010011 test 1521: 111010101 test 1522: 111010111 test 1523: 111011001 test 1524: 111011011 test 1525: 111011101 test 1526: 111011111 test 1527: 111100001 test 1528: 111100011 test 1529: 111100101 test 1530: 111100111 test 1531: 111101001 test 1532: 111101011 test 1533: 111101101 test 1534: 111101111 test 1535: 111110001 test 1536: 111110011 test 1537: 111110101 test 1538: 111110111 test 1539: 111111001 test 1540: 111111011 test 1541: 111111101 test 1542: 111111110 test 1543: 111111110111111110111111110 end: END summary column 1: offset 0, mask 0x8000 column 2: offset 0, mask 0x4000 column 3: offset 0, mask 0x2000 column 4: offset 0, mask 0x1000 column 5: offset 0, mask 0x0010 column 6: offset 0, mask 0x0008 column 7: offset 0, mask 0x0004 column 8: offset 0, mask 0x0002 column 9: offset 0, mask 0x0001 column 10: offset 0, mask 0x0400 column 11: offset 0, mask 0x0200 column 12: offset 0, mask 0x0100 column 13: offset 1, mask 0x8000 column 14: offset 1, mask 0x0001 column 15: offset 1, mask 0x0002 column 16: offset 1, mask 0x0004 column 17: offset 1, mask 0x0008 column 18: offset 1, mask 0x0010 column 19: offset 1, mask 0x2000 column 20: offset 1, mask 0x1000 column 21: offset 1, mask 0x0800 column 22: offset 1, mask 0x0400 column 23: offset 1, mask 0x0020 column 24: offset 1, mask 0x0040 column 25: offset 1, mask 0x0080 column 26: offset 2, mask 0x0001 column 27: offset 2, mask 0x0002 direction bits (1=input) 0x08E1 0x4310 0xFFFA 0xFFFF 0xF0FF pullup bits (1=pullup) 0x0000 0x0000 0x0000 0x0000 0x0000 test step out_data dont care 1: 0x0001 0x0010 0x0002 0x0000 0x0000 2: 0x0001 0x0010 0x0002 0x0000 0x0000 3: 0x0003 0x0010 0x0002 0x0000 0x0000 4: 0x0005 0x0010 0x0002 0x0000 0x0000 5: 0x0007 0x0010 0x0002 0x0000 0x0000 6: 0x0009 0x0010 0x0002 0x0000 0x0000 7: 0x000B 0x0010 0x0002 0x0000 0x0000 8: 0x000D 0x0010 0x0002 0x0000 0x0000 9: 0x000F 0x0010 0x0002 0x0000 0x0000 10: 0x0011 0x0010 0x0002 0x0000 0x0000 11: 0x0013 0x0010 0x0002 0x0000 0x0000 12: 0x0015 0x0010 0x0002 0x0000 0x0000 13: 0x0017 0x0010 0x0002 0x0000 0x0000 14: 0x0019 0x0010 0x0002 0x0000 0x0000 15: 0x001B 0x0010 0x0002 0x0000 0x0000 16: 0x001D 0x0010 0x0002 0x0000 0x0000 17: 0x001F 0x0010 0x0002 0x0000 0x0000 18: 0x1001 0x0010 0x0002 0x0000 0x0000 19: 0x1003 0x0010 0x0002 0x0000 0x0000 20: 0x1005 0x0010 0x0002 0x0000 0x0000 21: 0x1007 0x0010 0x0002 0x0000 0x0000 22: 0x1009 0x0010 0x0002 0x0000 0x0000 23: 0x100B 0x0010 0x0002 0x0000 0x0000 24: 0x100D 0x0010 0x0002 0x0000 0x0000 25: 0x100F 0x0010 0x0002 0x0000 0x0000 26: 0x1011 0x0010 0x0002 0x0000 0x0000 27: 0x1013 0x0010 0x0002 0x0000 0x0000 28: 0x1015 0x0010 0x0002 0x0000 0x0000 29: 0x1017 0x0010 0x0002 0x0000 0x0000 30: 0x1019 0x0010 0x0002 0x0000 0x0000 31: 0x101B 0x0010 0x0002 0x0000 0x0000 32: 0x101D 0x0010 0x0002 0x0000 0x0000 33: 0x101F 0x0010 0x0002 0x0000 0x0000 34: 0x2001 0x0010 0x0002 0x0000 0x0000 35: 0x2003 0x0010 0x0002 0x0000 0x0000 36: 0x2005 0x0010 0x0002 0x0000 0x0000 37: 0x2007 0x0010 0x0002 0x0000 0x0000 38: 0x2009 0x0010 0x0002 0x0000 0x0000 39: 0x200B 0x0010 0x0002 0x0000 0x0000 40: 0x200D 0x0010 0x0002 0x0000 0x0000 41: 0x200F 0x0010 0x0002 0x0000 0x0000 42: 0x2011 0x0010 0x0002 0x0000 0x0000 43: 0x2013 0x0010 0x0002 0x0000 0x0000 44: 0x2015 0x0010 0x0002 0x0000 0x0000 45: 0x2017 0x0010 0x0002 0x0000 0x0000 46: 0x2019 0x0010 0x0002 0x0000 0x0000 47: 0x201B 0x0010 0x0002 0x0000 0x0000 48: 0x201D 0x0010 0x0002 0x0000 0x0000 49: 0x201F 0x0010 0x0002 0x0000 0x0000 50: 0x3001 0x0010 0x0002 0x0000 0x0000 51: 0x3003 0x0010 0x0002 0x0000 0x0000 52: 0x3005 0x0010 0x0002 0x0000 0x0000 53: 0x3007 0x0010 0x0002 0x0000 0x0000 54: 0x3009 0x0010 0x0002 0x0000 0x0000 55: 0x300B 0x0010 0x0002 0x0000 0x0000 56: 0x300D 0x0010 0x0002 0x0000 0x0000 57: 0x300F 0x0010 0x0002 0x0000 0x0000 58: 0x3011 0x0010 0x0002 0x0000 0x0000 59: 0x3013 0x0010 0x0002 0x0000 0x0000 60: 0x3015 0x0010 0x0002 0x0000 0x0000 61: 0x3017 0x0010 0x0002 0x0000 0x0000 62: 0x3019 0x0010 0x0002 0x0000 0x0000 63: 0x301B 0x0010 0x0002 0x0000 0x0000 64: 0x301D 0x0010 0x0002 0x0000 0x0000 65: 0x301F 0x0010 0x0002 0x0000 0x0000 66: 0x4001 0x0010 0x0002 0x0000 0x0000 67: 0x4003 0x0010 0x0002 0x0000 0x0000 68: 0x4005 0x0010 0x0002 0x0000 0x0000 69: 0x4007 0x0010 0x0002 0x0000 0x0000 70: 0x4009 0x0010 0x0002 0x0000 0x0000 71: 0x400B 0x0010 0x0002 0x0000 0x0000 72: 0x400D 0x0010 0x0002 0x0000 0x0000 73: 0x400F 0x0010 0x0002 0x0000 0x0000 74: 0x4011 0x0010 0x0002 0x0000 0x0000 75: 0x4013 0x0010 0x0002 0x0000 0x0000 76: 0x4015 0x0010 0x0002 0x0000 0x0000 77: 0x4017 0x0010 0x0002 0x0000 0x0000 78: 0x4019 0x0010 0x0002 0x0000 0x0000 79: 0x401B 0x0010 0x0002 0x0000 0x0000 80: 0x401D 0x0010 0x0002 0x0000 0x0000 81: 0x401F 0x0010 0x0002 0x0000 0x0000 82: 0x5001 0x0010 0x0002 0x0000 0x0000 83: 0x5003 0x0010 0x0002 0x0000 0x0000 84: 0x5005 0x0010 0x0002 0x0000 0x0000 85: 0x5007 0x0010 0x0002 0x0000 0x0000 86: 0x5009 0x0010 0x0002 0x0000 0x0000 87: 0x500B 0x0010 0x0002 0x0000 0x0000 88: 0x500D 0x0010 0x0002 0x0000 0x0000 89: 0x500F 0x0010 0x0002 0x0000 0x0000 90: 0x5011 0x0010 0x0002 0x0000 0x0000 91: 0x5013 0x0010 0x0002 0x0000 0x0000 92: 0x5015 0x0010 0x0002 0x0000 0x0000 93: 0x5017 0x0010 0x0002 0x0000 0x0000 94: 0x5019 0x0010 0x0002 0x0000 0x0000 95: 0x501B 0x0010 0x0002 0x0000 0x0000 96: 0x501D 0x0010 0x0002 0x0000 0x0000 97: 0x501F 0x0010 0x0002 0x0000 0x0000 98: 0x6001 0x0010 0x0002 0x0000 0x0000 99: 0x6003 0x0010 0x0002 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0xB0CF 0x0003 0x0000 0x0000 1487: 0xF71E 0xB02F 0x0002 0x0000 0x0000 1488: 0xF71E 0xB02F 0x0003 0x0000 0x0000 1489: 0xF71E 0xB0AF 0x0002 0x0000 0x0000 1490: 0xF71E 0xB0AF 0x0003 0x0000 0x0000 1491: 0xF71E 0xB06F 0x0002 0x0000 0x0000 1492: 0xF71E 0xB06F 0x0003 0x0000 0x0000 1493: 0xF71E 0xB0EF 0x0002 0x0000 0x0000 1494: 0xF71E 0xB0EF 0x0003 0x0000 0x0000 1495: 0xF71E 0xB40F 0x0002 0x0000 0x0000 1496: 0xF71E 0xB40F 0x0003 0x0000 0x0000 1497: 0xF71E 0xB48F 0x0002 0x0000 0x0000 1498: 0xF71E 0xB48F 0x0003 0x0000 0x0000 1499: 0xF71E 0xB44F 0x0002 0x0000 0x0000 1500: 0xF71E 0xB44F 0x0003 0x0000 0x0000 1501: 0xF71E 0xB4CF 0x0002 0x0000 0x0000 1502: 0xF71E 0xB4CF 0x0003 0x0000 0x0000 1503: 0xF71E 0xB42F 0x0002 0x0000 0x0000 1504: 0xF71E 0xB42F 0x0003 0x0000 0x0000 1505: 0xF71E 0xB4AF 0x0002 0x0000 0x0000 1506: 0xF71E 0xB4AF 0x0003 0x0000 0x0000 1507: 0xF71E 0xB46F 0x0002 0x0000 0x0000 1508: 0xF71E 0xB46F 0x0003 0x0000 0x0000 1509: 0xF71E 0xB4EF 0x0002 0x0000 0x0000 1510: 0xF71E 0xB4EF 0x0003 0x0000 0x0000 1511: 0xF71E 0xB80F 0x0002 0x0000 0x0000 1512: 0xF71E 0xB80F 0x0003 0x0000 0x0000 1513: 0xF71E 0xB88F 0x0002 0x0000 0x0000 1514: 0xF71E 0xB88F 0x0003 0x0000 0x0000 1515: 0xF71E 0xB84F 0x0002 0x0000 0x0000 1516: 0xF71E 0xB84F 0x0003 0x0000 0x0000 1517: 0xF71E 0xB8CF 0x0002 0x0000 0x0000 1518: 0xF71E 0xB8CF 0x0003 0x0000 0x0000 1519: 0xF71E 0xB82F 0x0002 0x0000 0x0000 1520: 0xF71E 0xB82F 0x0003 0x0000 0x0000 1521: 0xF71E 0xB8AF 0x0002 0x0000 0x0000 1522: 0xF71E 0xB8AF 0x0003 0x0000 0x0000 1523: 0xF71E 0xB86F 0x0002 0x0000 0x0000 1524: 0xF71E 0xB86F 0x0003 0x0000 0x0000 1525: 0xF71E 0xB8EF 0x0002 0x0000 0x0000 1526: 0xF71E 0xB8EF 0x0003 0x0000 0x0000 1527: 0xF71E 0xBC0F 0x0002 0x0000 0x0000 1528: 0xF71E 0xBC0F 0x0003 0x0000 0x0000 1529: 0xF71E 0xBC8F 0x0002 0x0000 0x0000 1530: 0xF71E 0xBC8F 0x0003 0x0000 0x0000 1531: 0xF71E 0xBC4F 0x0002 0x0000 0x0000 1532: 0xF71E 0xBC4F 0x0003 0x0000 0x0000 1533: 0xF71E 0xBCCF 0x0002 0x0000 0x0000 1534: 0xF71E 0xBCCF 0x0003 0x0000 0x0000 1535: 0xF71E 0xBC2F 0x0002 0x0000 0x0000 1536: 0xF71E 0xBC2F 0x0003 0x0000 0x0000 1537: 0xF71E 0xBCAF 0x0002 0x0000 0x0000 1538: 0xF71E 0xBCAF 0x0003 0x0000 0x0000 1539: 0xF71E 0xBC6F 0x0002 0x0000 0x0000 1540: 0xF71E 0xBC6F 0x0003 0x0000 0x0000 1541: 0xF71E 0xBCEF 0x0002 0x0000 0x0000 1542: 0xF71E 0xBCEF 0x0001 0x0000 0x0000 1543: 0xF71E 0xBCEF 0x0001 0x0000 0x0000 PINs used (in edge connector order) (G=ground,P=power) SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBB LETTER ABCDEFHJKLMNPRSTUVABCDEFHJKLMNPRSTUVABCDEFHJKLMNPRSTUVABCDEFHJKLMNPRSTUV SIDE 111111111111111111222222222222222222111111111111111111222222222222222222 USAGE IIII IIII IIII G P GIIIIOIIIIOIIIIO G P G UUT has 24 inputs UUT has 3 outputs contains 27 pins/columns 39 pins are not used contains 1543 'test steps' M119 REV B 3 8-input NAND PINS Main menu Mon Jul 27 15:13:57 2015 test file is: tests\m119.tst delay is: 0 trigger is: 1 1 read test file 2 set test delay 3 set test trigger 4 run test 5 output loading test 8 diags 9 exit Enter test file name? trying to open test file: tests\1 could not open test file. valid test files are: reverting back to test file: tests\m119.tst Main menu Mon Jul 27 15:14:39 2015 test file is: tests\m119.tst delay is: 0 trigger is: 1 1 read test file 2 set test delay 3 set test trigger 4 run test 5 output loading test 8 diags 9 exit Enter test file name? trying to open test file: tests\m310.tst reading test file: tests\m310.tst comment: M310 REV D DELAY LINE comment: comment: USE SINGLE STEP AND DMM. comment: USE OSCILLOSCOPE TO SEE PULSES. comment: comment: AE1 IS THE INPUT FOR THE AF1 OUTPUT. comment: AH1 IS THE INPUT FOR THE AJ1 OUTPUT. comment: CONNECT AE1 TO EACH TAP: comment: pins: PINS pins: 1 I AH2 PULSE INPUT (EDGE?) pins: 2 O AJ2 0 NS DELAY TAP pins: 3 O AK2 50 NS DELAY TAP pins: 4 O AL2 100 NS DELAY TAP pins: 5 O AM2 150 NS DELAY TAP pins: 6 O AN2 200 NS DELAY TAP pins: 7 O AP2 250 NS DELAY TAP pins: 8 O AR2 300 NS DELAY TAP pins: 9 O AS2 350 NS DELAY TAP pins: 10 O AT2 400 NS DELAY TAP pins: 11 O AU2 450 NS DELAY TAP pins: 12 O AV2 500 NS DELAY TAP pins: 13 I AE1 INPUT 1 (NORMALLY CONNECTED TO A DELAY TAP) pins: 14 O AF1 OUTPUT 1 7440 BUFFER 48MA DRIVE PULSES HI (100 NS) pins: 15 I AH1 INPUT 2 (NORMALLY CONNECTED TO A DELAY TAP) pins: 16 O AJ1 OUTPUT 2 7440 BUFFER 48MA DRIVE PULSES HI (100 NS) pins: direction: IOOOOOOOOOOOIOIO test 1: 0111111111110000 test 2: 100000000000 test 3: 011111111111001X test 4: 100000000000 test 5: 0111111111111X00 test 6: 100000000000 test 7: 0111111111110X0X test 8: 100000000000 end: END summary column 1: offset 0, mask 0x0002 column 2: offset 0, mask 0x0001 column 3: offset 1, mask 0x0001 column 4: offset 1, mask 0x0002 column 5: offset 1, mask 0x0004 column 6: offset 1, mask 0x0008 column 7: offset 1, mask 0x0010 column 8: offset 1, mask 0x0020 column 9: offset 1, mask 0x0040 column 10: offset 1, mask 0x0080 column 11: offset 2, mask 0x0001 column 12: offset 2, mask 0x0002 column 13: offset 0, mask 0x0800 column 14: offset 0, mask 0x0400 column 15: offset 0, mask 0x0200 column 16: offset 0, mask 0x0100 direction bits (1=input) 0xF5FD 0xFFFF 0xFFFB 0xFFFF 0xF0FF pullup bits (1=pullup) 0x0000 0x0000 0x0000 0x0000 0x0000 test step out_data dont care 1: 0x0001 0x00FF 0x0003 0x0000 0x0000 2: 0x0002 0x0000 0x0000 0x0000 0x0000 3: 0x0201 0x00FF 0x0003 0x0000 0x0000 0x0100 0x0000 0x0000 0x0000 0x0000 4: 0x0202 0x0000 0x0000 0x0000 0x0000 0x0100 0x0000 0x0000 0x0000 0x0000 5: 0x0801 0x00FF 0x0003 0x0000 0x0000 0x0400 0x0000 0x0000 0x0000 0x0000 6: 0x0802 0x0000 0x0000 0x0000 0x0000 0x0400 0x0000 0x0000 0x0000 0x0000 7: 0x0001 0x00FF 0x0003 0x0000 0x0000 0x0500 0x0000 0x0000 0x0000 0x0000 8: 0x0002 0x0000 0x0000 0x0000 0x0000 0x0500 0x0000 0x0000 0x0000 0x0000 PINs used (in edge connector order) (G=ground,P=power) SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBB LETTER ABCDEFHJKLMNPRSTUVABCDEFHJKLMNPRSTUVABCDEFHJKLMNPRSTUVABCDEFHJKLMNPRSTUV SIDE 111111111111111111222222222222222222111111111111111111222222222222222222 USAGE IOIO G P G IOOOOOOOOOOO G P G UUT has 3 inputs UUT has 13 outputs contains 16 pins/columns 50 pins are not used contains 8 'test steps' M310 REV D DELAY LINE USE SINGLE STEP AND DMM. USE OSCILLOSCOPE TO SEE PULSES. AE1 IS THE INPUT FOR THE AF1 OUTPUT. AH1 IS THE INPUT FOR THE AJ1 OUTPUT. CONNECT AE1 TO EACH TAP: PINS Main menu Mon Jul 27 15:16:26 2015 test file is: tests\m310.tst delay is: 0 trigger is: 1 1 read test file 2 set test delay 3 set test trigger 4 run test 5 output loading test 8 diags 9 exit UUT power is okay Mon Jul 27 15:16:34 2015 space single step O run once (one test, all steps) F run, stop on fail G go (run tests N run, stop on fail, no print S scope (run, no print) C toggle comment printout + increase speed (less delay) - decrease speed (more delay)(slower) Q quit test scope (run, no print) ppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppp ppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppp ppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppp ppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppp ppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppp ppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppp ppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppp ppppppppppppppppppppppppppppppppppppppppppppppppppp space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C toggle comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAAAAAAAAAAAAAAA LETTER HJKLMNPRSTUVEFHJ SIDE 2222222222221111 DIRECTION IOOOOOOOOOOOIOIO all fails was lo 0000000000000000 falling vvvvvvvvvvvvv vv rising ^^^^^^^^^^^^^ ^^ was hi 1111111111111 11 total fails 0, total passes 604 Main menu Mon Jul 27 15:16:39 2015 test file is: tests\m310.tst delay is: 0 trigger is: 1 1 read test file 2 set test delay 3 set test trigger 4 run test 5 output loading test 8 diags 9 exit UUT power is okay Mon Jul 27 15:17:31 2015 space single step O run once (one test, all steps) F run, stop on fail G go (run tests N run, stop on fail, no print S scope (run, no print) C toggle comment printout + increase speed (less delay) - decrease speed (more delay)(slower) Q quit test scope (run, no print) ppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppp ppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppp ppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppp ppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppp ppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppp ppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppp space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C toggle comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAAAAAAAAAAAAAAA LETTER HJKLMNPRSTUVEFHJ SIDE 2222222222221111 DIRECTION IOOOOOOOOOOOIOIO all fails was lo 0000000000000000 falling vvvvvvvvvvvvvvvv rising ^^^^^^^^^^^^^^^^ was hi 1111111111111111 total fails 0, total passes 462 Main menu Mon Jul 27 15:17:34 2015 test file is: tests\m310.tst delay is: 0 trigger is: 1 1 read test file 2 set test delay 3 set test trigger 4 run test 5 output loading test 8 diags 9 exit UUT power is okay Mon Jul 27 15:18:28 2015 space single step O run once (one test, all steps) F run, stop on fail G go (run tests N run, stop on fail, no print S scope (run, no print) C toggle comment printout + increase speed (less delay) - decrease speed (more delay)(slower) Q quit test scope (run, no print) ppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppp ppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppp ppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppp ppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppp ppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppp pppppppppppppppppppppppppppppppppppppppppppppp space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C toggle comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAAAAAAAAAAAAAAA LETTER HJKLMNPRSTUVEFHJ SIDE 2222222222221111 DIRECTION IOOOOOOOOOOOIOIO all fails was lo 0000000000000000 falling vvvvvvvvvvvvvvvv rising ^^^^^^^^^^^^^^^^ was hi 1111111111111111 total fails 0, total passes 441 Main menu Mon Jul 27 15:18:32 2015 test file is: tests\m310.tst delay is: 0 trigger is: 1 1 read test file 2 set test delay 3 set test trigger 4 run test 5 output loading test 8 diags 9 exit UUT power is okay Mon Jul 27 15:19:54 2015 space single step O run once (one test, all steps) F run, stop on fail G go (run tests N run, stop on fail, no print S scope (run, no print) C toggle comment printout + increase speed (less delay) - decrease speed (more delay)(slower) Q quit test scope (run, no print) ppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppp ppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppp ppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppp ppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppp ppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppp ppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppp ppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppp ppppppp space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C toggle comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAAAAAAAAAAAAAAA LETTER HJKLMNPRSTUVEFHJ SIDE 2222222222221111 DIRECTION IOOOOOOOOOOOIOIO all fails was lo 0000000000000000 falling vvvvvvvvvvvvvvvv rising ^^^^^^^^^^^^^^^^ was hi 1111111111111111 total fails 0, total passes 560 Main menu Mon Jul 27 15:19:58 2015 test file is: tests\m310.tst delay is: 0 trigger is: 1 1 read test file 2 set test delay 3 set test trigger 4 run test 5 output loading test 8 diags 9 exit Enter test file name? trying to open test file: tests\m160.tst reading test file: tests\m160.tst comment: M160 3 AND-OR TREES (4-2-2-2-3;4-2-2-4;2-2) comment: pins: PINS pins: 1 I AA1 E2-1 4-X-X-X-X pins: 2 I AB1 E2-2 4-X-X-X-X pins: 3 I AC1 E2-3 4-X-X-X-X pins: 4 I AD1 E2-13 4-X-X-X-X pins: 5 I AE1 E1-13 X-2-X-X-X pins: 6 I AF1 E1-1 X-2-X-X-X pins: 7 I AH1 E1-2 X-X-2-X-X pins: 8 I AJ1 E1-3 X-X-2-X-X pins: 9 I AK1 E1-5 X-X-X-2-X pins: 10 I AL1 E1-4 X-X-X-2-X pins: 11 I AM1 E2-6 X-X-X-X-3 pins: 12 I AN1 E2-5 X-X-X-X-3 pins: 13 I AP1 E2-4 X-X-X-X-3 pins: 14 O AR1 E1-8 OUPUT pins: 15 I AD2 E4-3 4-X-X-X pins: 16 I AE2 E4-2 4-X-X-X pins: 17 I AF2 E4-1 4-X-X-X pins: 18 I AH2 E4-13 4-X-X-X pins: 19 I AJ2 E3-1 X-2-X-X pins: 20 I AK2 E3-13 X-2-X-X pins: 21 I AL2 E3-10 X-X-2-X pins: 22 I AM2 E3-9 X-X-2-X pins: 23 I AN2 E4-8 X-X-X-4 pins: 24 I AP2 E4-5 X-X-X-4 pins: 25 I AR2 E4-6 X-X-X-4 pins: 26 I AS2 E4-4 X-X-X-4 pins: 27 O AT2 E3-8 OUTPUT pins: 28 I AS1 E3-5 2-X pins: 29 I AU1 E3-4 2-X pins: 30 I AV1 E3-2 X-2 pins: 31 I AU2 E3-3 X-2 pins: 32 O AV2 E3-6 OUTPUT pins: direction: IIIIIIIIIIIIIOIIIIIIIIIIIIOIIIIO test 1: 00000000000001000000000000100001 test 2: 0001 1 test 3: 0011 1 test 4: 0010 1 test 5: 0110 1 test 6: 0111 1 test 7: 0101 1 test 8: 0100 1 test 9: 1100 1 test 10: 1101 1 test 11: 1111 0 test 12: 1110 1 test 13: 1010 1 test 14: 1011 1 test 15: 1001 1 test 16: 1000 1 test 17: 00000000000001000000000000100001 test 18: 01 1 test 19: 10 1 test 20: 11 0 test 21: 01 1 test 22: 00000000000001000000000000100001 test 23: 01 1 test 24: 10 1 test 25: 11 0 test 26: 01 1 test 27: 00000000000001000000000000100001 test 28: 01 1 test 29: 10 1 test 30: 11 0 test 31: 01 1 test 32: 00000000000001000000000000100001 test 33: 0011 test 34: 0111 test 35: 0101 test 36: 0101 test 37: 1110 test 38: 1011 test 39: 1001 test 40: 00000000000001000000000000100001 test 41: 0001 1 test 42: 0011 1 test 43: 0010 1 test 44: 0110 1 test 45: 0111 1 test 46: 0101 1 test 47: 0100 1 test 48: 1100 1 test 49: 1101 1 test 50: 1111 0 test 51: 1110 1 test 52: 1010 1 test 53: 1011 1 test 54: 1001 1 test 55: 1000 1 test 56: 00000000000001000000000000100001 test 57: 01 1 test 58: 10 1 test 59: 11 0 test 60: 01 1 test 61: 00000000000001000000000000100001 test 62: 01 1 test 63: 10 1 test 64: 11 0 test 65: 01 1 test 66: 00000000000001000000000000100001 test 67: 00011 test 68: 00111 test 69: 00101 test 70: 01101 test 71: 01111 test 72: 01011 test 73: 01001 test 74: 11001 test 75: 11011 test 76: 11110 test 77: 11101 test 78: 10101 test 79: 10111 test 80: 10011 test 81: 10001 test 82: 00000000000001000000000000100001 test 83: 01 1 test 84: 10 1 test 85: 11 0 test 86: 01 1 test 87: 00000000000001000000000000100001 test 88: 011 test 89: 101 test 90: 110 test 91: 011 test 92: 00000000000001000000000000100001 end: END summary column 1: offset 0, mask 0x8000 column 2: offset 0, mask 0x4000 column 3: offset 0, mask 0x2000 column 4: offset 0, mask 0x1000 column 5: offset 0, mask 0x0800 column 6: offset 0, mask 0x0400 column 7: offset 0, mask 0x0200 column 8: offset 0, mask 0x0100 column 9: offset 1, mask 0x8000 column 10: offset 1, mask 0x4000 column 11: offset 1, mask 0x2000 column 12: offset 1, mask 0x1000 column 13: offset 1, mask 0x0800 column 14: offset 1, mask 0x0400 column 15: offset 0, mask 0x0010 column 16: offset 0, mask 0x0008 column 17: offset 0, mask 0x0004 column 18: offset 0, mask 0x0002 column 19: offset 0, mask 0x0001 column 20: offset 1, mask 0x0001 column 21: offset 1, mask 0x0002 column 22: offset 1, mask 0x0004 column 23: offset 1, mask 0x0008 column 24: offset 1, mask 0x0010 column 25: offset 1, mask 0x0020 column 26: offset 1, mask 0x0040 column 27: offset 1, mask 0x0080 column 28: offset 1, mask 0x0200 column 29: offset 2, mask 0x8000 column 30: offset 2, mask 0x4000 column 31: offset 2, mask 0x0001 column 32: offset 2, mask 0x0002 direction bits (1=input) 0x00E0 0x0580 0x3FFA 0xFFFF 0xF0FF pullup bits (1=pullup) 0x0000 0x0000 0x0000 0x0000 0x0000 test step out_data dont care 1: 0x0000 0x0480 0x0002 0x0000 0x0000 2: 0x1000 0x0480 0x0002 0x0000 0x0000 3: 0x3000 0x0480 0x0002 0x0000 0x0000 4: 0x2000 0x0480 0x0002 0x0000 0x0000 5: 0x6000 0x0480 0x0002 0x0000 0x0000 6: 0x7000 0x0480 0x0002 0x0000 0x0000 7: 0x5000 0x0480 0x0002 0x0000 0x0000 8: 0x4000 0x0480 0x0002 0x0000 0x0000 9: 0xC000 0x0480 0x0002 0x0000 0x0000 10: 0xD000 0x0480 0x0002 0x0000 0x0000 11: 0xF000 0x0080 0x0002 0x0000 0x0000 12: 0xE000 0x0480 0x0002 0x0000 0x0000 13: 0xA000 0x0480 0x0002 0x0000 0x0000 14: 0xB000 0x0480 0x0002 0x0000 0x0000 15: 0x9000 0x0480 0x0002 0x0000 0x0000 16: 0x8000 0x0480 0x0002 0x0000 0x0000 17: 0x0000 0x0480 0x0002 0x0000 0x0000 18: 0x0400 0x0480 0x0002 0x0000 0x0000 19: 0x0800 0x0480 0x0002 0x0000 0x0000 20: 0x0C00 0x0080 0x0002 0x0000 0x0000 21: 0x0400 0x0480 0x0002 0x0000 0x0000 22: 0x0000 0x0480 0x0002 0x0000 0x0000 23: 0x0100 0x0480 0x0002 0x0000 0x0000 24: 0x0200 0x0480 0x0002 0x0000 0x0000 25: 0x0300 0x0080 0x0002 0x0000 0x0000 26: 0x0100 0x0480 0x0002 0x0000 0x0000 27: 0x0000 0x0480 0x0002 0x0000 0x0000 28: 0x0000 0x4480 0x0002 0x0000 0x0000 29: 0x0000 0x8480 0x0002 0x0000 0x0000 30: 0x0000 0xC080 0x0002 0x0000 0x0000 31: 0x0000 0x4480 0x0002 0x0000 0x0000 32: 0x0000 0x0480 0x0002 0x0000 0x0000 33: 0x0000 0x0C80 0x0002 0x0000 0x0000 34: 0x0000 0x1C80 0x0002 0x0000 0x0000 35: 0x0000 0x1480 0x0002 0x0000 0x0000 36: 0x0000 0x1480 0x0002 0x0000 0x0000 37: 0x0000 0x3880 0x0002 0x0000 0x0000 38: 0x0000 0x2C80 0x0002 0x0000 0x0000 39: 0x0000 0x2480 0x0002 0x0000 0x0000 40: 0x0000 0x0480 0x0002 0x0000 0x0000 41: 0x0002 0x0480 0x0002 0x0000 0x0000 42: 0x0006 0x0480 0x0002 0x0000 0x0000 43: 0x0004 0x0480 0x0002 0x0000 0x0000 44: 0x000C 0x0480 0x0002 0x0000 0x0000 45: 0x000E 0x0480 0x0002 0x0000 0x0000 46: 0x000A 0x0480 0x0002 0x0000 0x0000 47: 0x0008 0x0480 0x0002 0x0000 0x0000 48: 0x0018 0x0480 0x0002 0x0000 0x0000 49: 0x001A 0x0480 0x0002 0x0000 0x0000 50: 0x001E 0x0400 0x0002 0x0000 0x0000 51: 0x001C 0x0480 0x0002 0x0000 0x0000 52: 0x0014 0x0480 0x0002 0x0000 0x0000 53: 0x0016 0x0480 0x0002 0x0000 0x0000 54: 0x0012 0x0480 0x0002 0x0000 0x0000 55: 0x0010 0x0480 0x0002 0x0000 0x0000 56: 0x0000 0x0480 0x0002 0x0000 0x0000 57: 0x0000 0x0481 0x0002 0x0000 0x0000 58: 0x0001 0x0480 0x0002 0x0000 0x0000 59: 0x0001 0x0401 0x0002 0x0000 0x0000 60: 0x0000 0x0481 0x0002 0x0000 0x0000 61: 0x0000 0x0480 0x0002 0x0000 0x0000 62: 0x0000 0x0484 0x0002 0x0000 0x0000 63: 0x0000 0x0482 0x0002 0x0000 0x0000 64: 0x0000 0x0406 0x0002 0x0000 0x0000 65: 0x0000 0x0484 0x0002 0x0000 0x0000 66: 0x0000 0x0480 0x0002 0x0000 0x0000 67: 0x0000 0x04C0 0x0002 0x0000 0x0000 68: 0x0000 0x04E0 0x0002 0x0000 0x0000 69: 0x0000 0x04A0 0x0002 0x0000 0x0000 70: 0x0000 0x04B0 0x0002 0x0000 0x0000 71: 0x0000 0x04F0 0x0002 0x0000 0x0000 72: 0x0000 0x04D0 0x0002 0x0000 0x0000 73: 0x0000 0x0490 0x0002 0x0000 0x0000 74: 0x0000 0x0498 0x0002 0x0000 0x0000 75: 0x0000 0x04D8 0x0002 0x0000 0x0000 76: 0x0000 0x0478 0x0002 0x0000 0x0000 77: 0x0000 0x04B8 0x0002 0x0000 0x0000 78: 0x0000 0x04A8 0x0002 0x0000 0x0000 79: 0x0000 0x04E8 0x0002 0x0000 0x0000 80: 0x0000 0x04C8 0x0002 0x0000 0x0000 81: 0x0000 0x0488 0x0002 0x0000 0x0000 82: 0x0000 0x0480 0x0002 0x0000 0x0000 83: 0x0000 0x0480 0x8002 0x0000 0x0000 84: 0x0000 0x0680 0x0002 0x0000 0x0000 85: 0x0000 0x0680 0x8000 0x0000 0x0000 86: 0x0000 0x0480 0x8002 0x0000 0x0000 87: 0x0000 0x0480 0x0002 0x0000 0x0000 88: 0x0000 0x0480 0x0003 0x0000 0x0000 89: 0x0000 0x0480 0x4002 0x0000 0x0000 90: 0x0000 0x0480 0x4001 0x0000 0x0000 91: 0x0000 0x0480 0x0003 0x0000 0x0000 92: 0x0000 0x0480 0x0002 0x0000 0x0000 PINs used (in edge connector order) (G=ground,P=power) SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBB LETTER ABCDEFHJKLMNPRSTUVABCDEFHJKLMNPRSTUVABCDEFHJKLMNPRSTUVABCDEFHJKLMNPRSTUV SIDE 111111111111111111222222222222222222111111111111111111222222222222222222 USAGE IIIIIIIIIIIIIOIGIIP GIIIIIIIIIIIIOIO G P G UUT has 29 inputs UUT has 3 outputs contains 32 pins/columns 34 pins are not used contains 92 'test steps' M160 3 AND-OR TREES (4-2-2-2-3;4-2-2-4;2-2) PINS Main menu Mon Jul 27 15:20:50 2015 test file is: tests\m160.tst delay is: 0 trigger is: 1 1 read test file 2 set test delay 3 set test trigger 4 run test 5 output loading test 8 diags 9 exit UUT power is okay Mon Jul 27 15:21:04 2015 space single step O run once (one test, all steps) F run, stop on fail G go (run tests N run, stop on fail, no print S scope (run, no print) C toggle comment printout + increase speed (less delay) - decrease speed (more delay)(slower) Q quit test scope (run, no print) ppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppp pp space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C toggle comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFHJKLMNPRDEFHJKLMNPRSTSUVUV SIDE 11111111111111222222222222211122 DIRECTION IIIIIIIIIIIIIOIIIIIIIIIIIIOIIIIO all fails was lo 00000000000000000000000000000000 falling vvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvv rising ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ was hi 11111111111111111111111111111111 total fails 0, total passes 81 Main menu Mon Jul 27 15:21:10 2015 test file is: tests\m160.tst delay is: 0 trigger is: 1 1 read test file 2 set test delay 3 set test trigger 4 run test 5 output loading test 8 diags 9 exit Enter test file name? trying to open test file: tests\m617.tst reading test file: tests\m617.tst comment: M617 REV E 6 4-INPUT NAND BUFFERS (48ma) (7440) comment: pins: PINS pins: 1 I AA1 E1-13 pins: 2 I AB1 E1-12 pins: 3 I AC1 E1-10 pins: 4 I AD1 E1-9 pins: 5 O AE1 E1-8 pins: 6 I AF1 E2-13 pins: 7 I AH1 E2-12 pins: 8 I AJ1 E2-10 pins: 9 I AK1 E2-9 pins: 10 O AL1 E2-8 pins: 11 I AM1 E3-13 pins: 12 I AN1 E3-12 pins: 13 I AP1 E3-10 pins: 14 I AR1 E3-9 pins: 15 O AS1 E3-8 pins: 16 I AD2 E1-5 pins: 17 I AE2 E1-4 pins: 18 I AF2 E1-2 pins: 19 I AH2 E1-1 pins: 20 O AJ2 E1-6 pins: 21 I AK2 E2-5 pins: 22 I AL2 E2-4 pins: 23 I AM2 E2-2 pins: 24 I AN2 E2-1 pins: 25 O AP2 E2-6 pins: 26 I AR2 E3-1 pins: 27 I AS2 E3-2 pins: 28 I AT2 E3-4 pins: 29 I AU2 E3-5 pins: 30 O AV2 E3-6 pins: direction: IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO test 1: 000010000100001000010000100001 test 2: 00001 test 3: 00011 test 4: 00101 test 5: 00111 test 6: 01001 test 7: 01011 test 8: 01101 test 9: 01111 test 10: 10001 test 11: 10011 test 12: 10101 test 13: 10111 test 14: 11001 test 15: 11011 test 16: 11101 test 17: 11110 test 18: 00001 test 19: 00001 test 20: 00011 test 21: 00101 test 22: 00111 test 23: 01001 test 24: 01011 test 25: 01101 test 26: 01111 test 27: 10001 test 28: 10011 test 29: 10101 test 30: 10111 test 31: 11001 test 32: 11011 test 33: 11101 test 34: 11110 test 35: 00001 test 36: 00001 test 37: 00011 test 38: 00101 test 39: 00111 test 40: 01001 test 41: 01011 test 42: 01101 test 43: 01111 test 44: 10001 test 45: 10011 test 46: 10101 test 47: 10111 test 48: 11001 test 49: 11011 test 50: 11101 test 51: 11110 test 52: 00001 test 53: 00001 test 54: 00011 test 55: 00101 test 56: 00111 test 57: 01001 test 58: 01011 test 59: 01101 test 60: 01111 test 61: 10001 test 62: 10011 test 63: 10101 test 64: 10111 test 65: 11001 test 66: 11011 test 67: 11101 test 68: 11110 test 69: 00001 test 70: 00001 test 71: 00011 test 72: 00101 test 73: 00111 test 74: 01001 test 75: 01011 test 76: 01101 test 77: 01111 test 78: 10001 test 79: 10011 test 80: 10101 test 81: 10111 test 82: 11001 test 83: 11011 test 84: 11101 test 85: 11110 test 86: 00001 test 87: 00001 test 88: 00011 test 89: 00101 test 90: 00111 test 91: 01001 test 92: 01011 test 93: 01101 test 94: 01111 test 95: 10001 test 96: 10011 test 97: 10101 test 98: 10111 test 99: 11001 test 100: 11011 test 101: 11101 test 102: 11110 test 103: 00001 test 104: 000010000100001000010000100001 test 105: 111101111011110111101111011110 test 106: 00001 test 107: 00011 test 108: 00101 test 109: 00111 test 110: 01001 test 111: 01011 test 112: 01101 test 113: 01111 test 114: 10001 test 115: 10011 test 116: 10101 test 117: 10111 test 118: 11001 test 119: 11011 test 120: 11101 test 121: 11110 test 122: 00001 test 123: 00011 test 124: 00101 test 125: 00111 test 126: 01001 test 127: 01011 test 128: 01101 test 129: 01111 test 130: 10001 test 131: 10011 test 132: 10101 test 133: 10111 test 134: 11001 test 135: 11011 test 136: 11101 test 137: 11110 test 138: 00001 test 139: 00011 test 140: 00101 test 141: 00111 test 142: 01001 test 143: 01011 test 144: 01101 test 145: 01111 test 146: 10001 test 147: 10011 test 148: 10101 test 149: 10111 test 150: 11001 test 151: 11011 test 152: 11101 test 153: 11110 test 154: 00001 test 155: 00011 test 156: 00101 test 157: 00111 test 158: 01001 test 159: 01011 test 160: 01101 test 161: 01111 test 162: 10001 test 163: 10011 test 164: 10101 test 165: 10111 test 166: 11001 test 167: 11011 test 168: 11101 test 169: 11110 test 170: 00001 test 171: 00011 test 172: 00101 test 173: 00111 test 174: 01001 test 175: 01011 test 176: 01101 test 177: 01111 test 178: 10001 test 179: 10011 test 180: 10101 test 181: 10111 test 182: 11001 test 183: 11011 test 184: 11101 test 185: 11110 test 186: 00001 test 187: 00011 test 188: 00101 test 189: 00111 test 190: 01001 test 191: 01011 test 192: 01101 test 193: 01111 test 194: 10001 test 195: 10011 test 196: 10101 test 197: 10111 test 198: 11001 test 199: 11011 test 200: 11101 test 201: 11110 test 202: 111101111011110111101111011110 end: END summary column 1: offset 0, mask 0x8000 column 2: offset 0, mask 0x4000 column 3: offset 0, mask 0x2000 column 4: offset 0, mask 0x1000 column 5: offset 0, mask 0x0800 column 6: offset 0, mask 0x0400 column 7: offset 0, mask 0x0200 column 8: offset 0, mask 0x0100 column 9: offset 1, mask 0x8000 column 10: offset 1, mask 0x4000 column 11: offset 1, mask 0x2000 column 12: offset 1, mask 0x1000 column 13: offset 1, mask 0x0800 column 14: offset 1, mask 0x0400 column 15: offset 1, mask 0x0200 column 16: offset 0, mask 0x0010 column 17: offset 0, mask 0x0008 column 18: offset 0, mask 0x0004 column 19: offset 0, mask 0x0002 column 20: offset 0, mask 0x0001 column 21: offset 1, mask 0x0001 column 22: offset 1, mask 0x0002 column 23: offset 1, mask 0x0004 column 24: offset 1, mask 0x0008 column 25: offset 1, mask 0x0010 column 26: offset 1, mask 0x0020 column 27: offset 1, mask 0x0040 column 28: offset 1, mask 0x0080 column 29: offset 2, mask 0x0001 column 30: offset 2, mask 0x0002 direction bits (1=input) 0x08E1 0x4310 0xFFFA 0xFFFF 0xF0FF pullup bits (1=pullup) 0x0000 0x0000 0x0000 0x0000 0x0000 test step out_data dont care 1: 0x0801 0x4210 0x0002 0x0000 0x0000 2: 0x0801 0x4210 0x0002 0x0000 0x0000 3: 0x1801 0x4210 0x0002 0x0000 0x0000 4: 0x2801 0x4210 0x0002 0x0000 0x0000 5: 0x3801 0x4210 0x0002 0x0000 0x0000 6: 0x4801 0x4210 0x0002 0x0000 0x0000 7: 0x5801 0x4210 0x0002 0x0000 0x0000 8: 0x6801 0x4210 0x0002 0x0000 0x0000 9: 0x7801 0x4210 0x0002 0x0000 0x0000 10: 0x8801 0x4210 0x0002 0x0000 0x0000 11: 0x9801 0x4210 0x0002 0x0000 0x0000 12: 0xA801 0x4210 0x0002 0x0000 0x0000 13: 0xB801 0x4210 0x0002 0x0000 0x0000 14: 0xC801 0x4210 0x0002 0x0000 0x0000 15: 0xD801 0x4210 0x0002 0x0000 0x0000 16: 0xE801 0x4210 0x0002 0x0000 0x0000 17: 0xF001 0x4210 0x0002 0x0000 0x0000 18: 0x0801 0x4210 0x0002 0x0000 0x0000 19: 0x0801 0x4210 0x0002 0x0000 0x0000 20: 0x0801 0xC210 0x0002 0x0000 0x0000 21: 0x0901 0x4210 0x0002 0x0000 0x0000 22: 0x0901 0xC210 0x0002 0x0000 0x0000 23: 0x0A01 0x4210 0x0002 0x0000 0x0000 24: 0x0A01 0xC210 0x0002 0x0000 0x0000 25: 0x0B01 0x4210 0x0002 0x0000 0x0000 26: 0x0B01 0xC210 0x0002 0x0000 0x0000 27: 0x0C01 0x4210 0x0002 0x0000 0x0000 28: 0x0C01 0xC210 0x0002 0x0000 0x0000 29: 0x0D01 0x4210 0x0002 0x0000 0x0000 30: 0x0D01 0xC210 0x0002 0x0000 0x0000 31: 0x0E01 0x4210 0x0002 0x0000 0x0000 32: 0x0E01 0xC210 0x0002 0x0000 0x0000 33: 0x0F01 0x4210 0x0002 0x0000 0x0000 34: 0x0F01 0x8210 0x0002 0x0000 0x0000 35: 0x0801 0x4210 0x0002 0x0000 0x0000 36: 0x0801 0x4210 0x0002 0x0000 0x0000 37: 0x0801 0x4610 0x0002 0x0000 0x0000 38: 0x0801 0x4A10 0x0002 0x0000 0x0000 39: 0x0801 0x4E10 0x0002 0x0000 0x0000 40: 0x0801 0x5210 0x0002 0x0000 0x0000 41: 0x0801 0x5610 0x0002 0x0000 0x0000 42: 0x0801 0x5A10 0x0002 0x0000 0x0000 43: 0x0801 0x5E10 0x0002 0x0000 0x0000 44: 0x0801 0x6210 0x0002 0x0000 0x0000 45: 0x0801 0x6610 0x0002 0x0000 0x0000 46: 0x0801 0x6A10 0x0002 0x0000 0x0000 47: 0x0801 0x6E10 0x0002 0x0000 0x0000 48: 0x0801 0x7210 0x0002 0x0000 0x0000 49: 0x0801 0x7610 0x0002 0x0000 0x0000 50: 0x0801 0x7A10 0x0002 0x0000 0x0000 51: 0x0801 0x7C10 0x0002 0x0000 0x0000 52: 0x0801 0x4210 0x0002 0x0000 0x0000 53: 0x0801 0x4210 0x0002 0x0000 0x0000 54: 0x0803 0x4210 0x0002 0x0000 0x0000 55: 0x0805 0x4210 0x0002 0x0000 0x0000 56: 0x0807 0x4210 0x0002 0x0000 0x0000 57: 0x0809 0x4210 0x0002 0x0000 0x0000 58: 0x080B 0x4210 0x0002 0x0000 0x0000 59: 0x080D 0x4210 0x0002 0x0000 0x0000 60: 0x080F 0x4210 0x0002 0x0000 0x0000 61: 0x0811 0x4210 0x0002 0x0000 0x0000 62: 0x0813 0x4210 0x0002 0x0000 0x0000 63: 0x0815 0x4210 0x0002 0x0000 0x0000 64: 0x0817 0x4210 0x0002 0x0000 0x0000 65: 0x0819 0x4210 0x0002 0x0000 0x0000 66: 0x081B 0x4210 0x0002 0x0000 0x0000 67: 0x081D 0x4210 0x0002 0x0000 0x0000 68: 0x081E 0x4210 0x0002 0x0000 0x0000 69: 0x0801 0x4210 0x0002 0x0000 0x0000 70: 0x0801 0x4210 0x0002 0x0000 0x0000 71: 0x0801 0x4218 0x0002 0x0000 0x0000 72: 0x0801 0x4214 0x0002 0x0000 0x0000 73: 0x0801 0x421C 0x0002 0x0000 0x0000 74: 0x0801 0x4212 0x0002 0x0000 0x0000 75: 0x0801 0x421A 0x0002 0x0000 0x0000 76: 0x0801 0x4216 0x0002 0x0000 0x0000 77: 0x0801 0x421E 0x0002 0x0000 0x0000 78: 0x0801 0x4211 0x0002 0x0000 0x0000 79: 0x0801 0x4219 0x0002 0x0000 0x0000 80: 0x0801 0x4215 0x0002 0x0000 0x0000 81: 0x0801 0x421D 0x0002 0x0000 0x0000 82: 0x0801 0x4213 0x0002 0x0000 0x0000 83: 0x0801 0x421B 0x0002 0x0000 0x0000 84: 0x0801 0x4217 0x0002 0x0000 0x0000 85: 0x0801 0x420F 0x0002 0x0000 0x0000 86: 0x0801 0x4210 0x0002 0x0000 0x0000 87: 0x0801 0x4210 0x0002 0x0000 0x0000 88: 0x0801 0x4210 0x0003 0x0000 0x0000 89: 0x0801 0x4290 0x0002 0x0000 0x0000 90: 0x0801 0x4290 0x0003 0x0000 0x0000 91: 0x0801 0x4250 0x0002 0x0000 0x0000 92: 0x0801 0x4250 0x0003 0x0000 0x0000 93: 0x0801 0x42D0 0x0002 0x0000 0x0000 94: 0x0801 0x42D0 0x0003 0x0000 0x0000 95: 0x0801 0x4230 0x0002 0x0000 0x0000 96: 0x0801 0x4230 0x0003 0x0000 0x0000 97: 0x0801 0x42B0 0x0002 0x0000 0x0000 98: 0x0801 0x42B0 0x0003 0x0000 0x0000 99: 0x0801 0x4270 0x0002 0x0000 0x0000 100: 0x0801 0x4270 0x0003 0x0000 0x0000 101: 0x0801 0x42F0 0x0002 0x0000 0x0000 102: 0x0801 0x42F0 0x0001 0x0000 0x0000 103: 0x0801 0x4210 0x0002 0x0000 0x0000 104: 0x0801 0x4210 0x0002 0x0000 0x0000 105: 0xF71E 0xBCEF 0x0001 0x0000 0x0000 106: 0x0F1E 0xBCEF 0x0001 0x0000 0x0000 107: 0x1F1E 0xBCEF 0x0001 0x0000 0x0000 108: 0x2F1E 0xBCEF 0x0001 0x0000 0x0000 109: 0x3F1E 0xBCEF 0x0001 0x0000 0x0000 110: 0x4F1E 0xBCEF 0x0001 0x0000 0x0000 111: 0x5F1E 0xBCEF 0x0001 0x0000 0x0000 112: 0x6F1E 0xBCEF 0x0001 0x0000 0x0000 113: 0x7F1E 0xBCEF 0x0001 0x0000 0x0000 114: 0x8F1E 0xBCEF 0x0001 0x0000 0x0000 115: 0x9F1E 0xBCEF 0x0001 0x0000 0x0000 116: 0xAF1E 0xBCEF 0x0001 0x0000 0x0000 117: 0xBF1E 0xBCEF 0x0001 0x0000 0x0000 118: 0xCF1E 0xBCEF 0x0001 0x0000 0x0000 119: 0xDF1E 0xBCEF 0x0001 0x0000 0x0000 120: 0xEF1E 0xBCEF 0x0001 0x0000 0x0000 121: 0xF71E 0xBCEF 0x0001 0x0000 0x0000 122: 0xF01E 0x7CEF 0x0001 0x0000 0x0000 123: 0xF01E 0xFCEF 0x0001 0x0000 0x0000 124: 0xF11E 0x7CEF 0x0001 0x0000 0x0000 125: 0xF11E 0xFCEF 0x0001 0x0000 0x0000 126: 0xF21E 0x7CEF 0x0001 0x0000 0x0000 127: 0xF21E 0xFCEF 0x0001 0x0000 0x0000 128: 0xF31E 0x7CEF 0x0001 0x0000 0x0000 129: 0xF31E 0xFCEF 0x0001 0x0000 0x0000 130: 0xF41E 0x7CEF 0x0001 0x0000 0x0000 131: 0xF41E 0xFCEF 0x0001 0x0000 0x0000 132: 0xF51E 0x7CEF 0x0001 0x0000 0x0000 133: 0xF51E 0xFCEF 0x0001 0x0000 0x0000 134: 0xF61E 0x7CEF 0x0001 0x0000 0x0000 135: 0xF61E 0xFCEF 0x0001 0x0000 0x0000 136: 0xF71E 0x7CEF 0x0001 0x0000 0x0000 137: 0xF71E 0xBCEF 0x0001 0x0000 0x0000 138: 0xF71E 0x82EF 0x0001 0x0000 0x0000 139: 0xF71E 0x86EF 0x0001 0x0000 0x0000 140: 0xF71E 0x8AEF 0x0001 0x0000 0x0000 141: 0xF71E 0x8EEF 0x0001 0x0000 0x0000 142: 0xF71E 0x92EF 0x0001 0x0000 0x0000 143: 0xF71E 0x96EF 0x0001 0x0000 0x0000 144: 0xF71E 0x9AEF 0x0001 0x0000 0x0000 145: 0xF71E 0x9EEF 0x0001 0x0000 0x0000 146: 0xF71E 0xA2EF 0x0001 0x0000 0x0000 147: 0xF71E 0xA6EF 0x0001 0x0000 0x0000 148: 0xF71E 0xAAEF 0x0001 0x0000 0x0000 149: 0xF71E 0xAEEF 0x0001 0x0000 0x0000 150: 0xF71E 0xB2EF 0x0001 0x0000 0x0000 151: 0xF71E 0xB6EF 0x0001 0x0000 0x0000 152: 0xF71E 0xBAEF 0x0001 0x0000 0x0000 153: 0xF71E 0xBCEF 0x0001 0x0000 0x0000 154: 0xF701 0xBCEF 0x0001 0x0000 0x0000 155: 0xF703 0xBCEF 0x0001 0x0000 0x0000 156: 0xF705 0xBCEF 0x0001 0x0000 0x0000 157: 0xF707 0xBCEF 0x0001 0x0000 0x0000 158: 0xF709 0xBCEF 0x0001 0x0000 0x0000 159: 0xF70B 0xBCEF 0x0001 0x0000 0x0000 160: 0xF70D 0xBCEF 0x0001 0x0000 0x0000 161: 0xF70F 0xBCEF 0x0001 0x0000 0x0000 162: 0xF711 0xBCEF 0x0001 0x0000 0x0000 163: 0xF713 0xBCEF 0x0001 0x0000 0x0000 164: 0xF715 0xBCEF 0x0001 0x0000 0x0000 165: 0xF717 0xBCEF 0x0001 0x0000 0x0000 166: 0xF719 0xBCEF 0x0001 0x0000 0x0000 167: 0xF71B 0xBCEF 0x0001 0x0000 0x0000 168: 0xF71D 0xBCEF 0x0001 0x0000 0x0000 169: 0xF71E 0xBCEF 0x0001 0x0000 0x0000 170: 0xF71E 0xBCF0 0x0001 0x0000 0x0000 171: 0xF71E 0xBCF8 0x0001 0x0000 0x0000 172: 0xF71E 0xBCF4 0x0001 0x0000 0x0000 173: 0xF71E 0xBCFC 0x0001 0x0000 0x0000 174: 0xF71E 0xBCF2 0x0001 0x0000 0x0000 175: 0xF71E 0xBCFA 0x0001 0x0000 0x0000 176: 0xF71E 0xBCF6 0x0001 0x0000 0x0000 177: 0xF71E 0xBCFE 0x0001 0x0000 0x0000 178: 0xF71E 0xBCF1 0x0001 0x0000 0x0000 179: 0xF71E 0xBCF9 0x0001 0x0000 0x0000 180: 0xF71E 0xBCF5 0x0001 0x0000 0x0000 181: 0xF71E 0xBCFD 0x0001 0x0000 0x0000 182: 0xF71E 0xBCF3 0x0001 0x0000 0x0000 183: 0xF71E 0xBCFB 0x0001 0x0000 0x0000 184: 0xF71E 0xBCF7 0x0001 0x0000 0x0000 185: 0xF71E 0xBCEF 0x0001 0x0000 0x0000 186: 0xF71E 0xBC0F 0x0002 0x0000 0x0000 187: 0xF71E 0xBC0F 0x0003 0x0000 0x0000 188: 0xF71E 0xBC8F 0x0002 0x0000 0x0000 189: 0xF71E 0xBC8F 0x0003 0x0000 0x0000 190: 0xF71E 0xBC4F 0x0002 0x0000 0x0000 191: 0xF71E 0xBC4F 0x0003 0x0000 0x0000 192: 0xF71E 0xBCCF 0x0002 0x0000 0x0000 193: 0xF71E 0xBCCF 0x0003 0x0000 0x0000 194: 0xF71E 0xBC2F 0x0002 0x0000 0x0000 195: 0xF71E 0xBC2F 0x0003 0x0000 0x0000 196: 0xF71E 0xBCAF 0x0002 0x0000 0x0000 197: 0xF71E 0xBCAF 0x0003 0x0000 0x0000 198: 0xF71E 0xBC6F 0x0002 0x0000 0x0000 199: 0xF71E 0xBC6F 0x0003 0x0000 0x0000 200: 0xF71E 0xBCEF 0x0002 0x0000 0x0000 201: 0xF71E 0xBCEF 0x0001 0x0000 0x0000 202: 0xF71E 0xBCEF 0x0001 0x0000 0x0000 PINs used (in edge connector order) (G=ground,P=power) SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBB LETTER ABCDEFHJKLMNPRSTUVABCDEFHJKLMNPRSTUVABCDEFHJKLMNPRSTUVABCDEFHJKLMNPRSTUV SIDE 111111111111111111222222222222222222111111111111111111222222222222222222 USAGE IIIIOIIIIOIIIIOG P GIIIIOIIIIOIIIIO G P G UUT has 24 inputs UUT has 6 outputs contains 30 pins/columns 36 pins are not used contains 202 'test steps' M617 REV E 6 4-INPUT NAND BUFFERS (48ma) (7440) PINS Main menu Mon Jul 27 15:22:17 2015 test file is: tests\m617.tst delay is: 0 trigger is: 1 1 read test file 2 set test delay 3 set test trigger 4 run test 5 output loading test 8 diags 9 exit UUT power is okay Mon Jul 27 15:22:22 2015 space single step O run once (one test, all steps) F run, stop on fail G go (run tests N run, stop on fail, no print S scope (run, no print) C toggle comment printout + increase speed (less delay) - decrease speed (more delay)(slower) Q quit test scope (run, no print) FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C toggle comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFHJKLMNPRSDEFHJKLMNPRSTUV SIDE 111111111111111222222222222222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO all fails O was lo 000000000000000000000000000000 falling vvvvvvvvvvvvvvvvvvvvvvvvvvvvvv rising ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ was hi 111111111111111111111111111111 total fails 77, total passes 0 Main menu Mon Jul 27 15:22:33 2015 test file is: tests\m617.tst delay is: 0 trigger is: 1 1 read test file 2 set test delay 3 set test trigger 4 run test 5 output loading test 8 diags 9 exit Enter test file name? trying to open test file: tests\m617.tst reading test file: tests\m617.tst comment: M617 REV E 6 4-INPUT NAND BUFFERS (48ma) (7440) comment: pins: PINS pins: 1 I AA1 E1-13 pins: 2 I AB1 E1-12 pins: 3 I AC1 E1-10 pins: 4 I AD1 E1-9 pins: 5 O AE1 E1-8 pins: 6 I AF1 E2-13 pins: 7 I AH1 E2-12 pins: 8 I AJ1 E2-10 pins: 9 I AK1 E2-9 pins: 10 O AL1 E2-8 pins: 11 I AM1 E3-13 pins: 12 I AN1 E3-12 pins: 13 I AP1 E3-10 pins: 14 I AR1 E3-9 pins: 15 O AS1 E3-8 pins: 16 I AD2 E1-5 pins: 17 I AE2 E1-4 pins: 18 I AF2 E1-2 pins: 19 I AH2 E1-1 pins: 20 O AJ2 E1-6 pins: 21 I AK2 E2-5 pins: 22 I AL2 E2-4 pins: 23 I AM2 E2-2 pins: 24 I AN2 E2-1 pins: 25 O AP2 E2-6 pins: 26 I AR2 E3-1 pins: 27 I AS2 E3-2 pins: 28 I AT2 E3-4 pins: 29 I AU2 E3-5 pins: 30 O AV2 E3-6 pins: direction: IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO test 1: 000010000100001000010000100001 test 2: 00001 test 3: 00011 test 4: 00101 test 5: 00111 test 6: 01001 test 7: 01011 test 8: 01101 test 9: 01111 test 10: 10001 test 11: 10011 test 12: 10101 test 13: 10111 test 14: 11001 test 15: 11011 test 16: 11101 test 17: 11110 test 18: 00001 test 19: 00001 test 20: 00011 test 21: 00101 test 22: 00111 test 23: 01001 test 24: 01011 test 25: 01101 test 26: 01111 test 27: 10001 test 28: 10011 test 29: 10101 test 30: 10111 test 31: 11001 test 32: 11011 test 33: 11101 test 34: 11110 test 35: 00001 test 36: 00001 test 37: 00011 test 38: 00101 test 39: 00111 test 40: 01001 test 41: 01011 test 42: 01101 test 43: 01111 test 44: 10001 test 45: 10011 test 46: 10101 test 47: 10111 test 48: 11001 test 49: 11011 test 50: 11101 test 51: 11110 test 52: 00001 test 53: 00001 test 54: 00011 test 55: 00101 test 56: 00111 test 57: 01001 test 58: 01011 test 59: 01101 test 60: 01111 test 61: 10001 test 62: 10011 test 63: 10101 test 64: 10111 test 65: 11001 test 66: 11011 test 67: 11101 test 68: 11110 test 69: 00001 test 70: 00001 test 71: 00011 test 72: 00101 test 73: 00111 test 74: 01001 test 75: 01011 test 76: 01101 test 77: 01111 test 78: 10001 test 79: 10011 test 80: 10101 test 81: 10111 test 82: 11001 test 83: 11011 test 84: 11101 test 85: 11110 test 86: 00001 test 87: 00001 test 88: 00011 test 89: 00101 test 90: 00111 test 91: 01001 test 92: 01011 test 93: 01101 test 94: 01111 test 95: 10001 test 96: 10011 test 97: 10101 test 98: 10111 test 99: 11001 test 100: 11011 test 101: 11101 test 102: 11110 test 103: 00001 test 104: 000010000100001000010000100001 test 105: 111101111011110111101111011110 test 106: 00001 test 107: 00011 test 108: 00101 test 109: 00111 test 110: 01001 test 111: 01011 test 112: 01101 test 113: 01111 test 114: 10001 test 115: 10011 test 116: 10101 test 117: 10111 test 118: 11001 test 119: 11011 test 120: 11101 test 121: 11110 test 122: 00001 test 123: 00011 test 124: 00101 test 125: 00111 test 126: 01001 test 127: 01011 test 128: 01101 test 129: 01111 test 130: 10001 test 131: 10011 test 132: 10101 test 133: 10111 test 134: 11001 test 135: 11011 test 136: 11101 test 137: 11110 test 138: 00001 test 139: 00011 test 140: 00101 test 141: 00111 test 142: 01001 test 143: 01011 test 144: 01101 test 145: 01111 test 146: 10001 test 147: 10011 test 148: 10101 test 149: 10111 test 150: 11001 test 151: 11011 test 152: 11101 test 153: 11110 test 154: 00001 test 155: 00011 test 156: 00101 test 157: 00111 test 158: 01001 test 159: 01011 test 160: 01101 test 161: 01111 test 162: 10001 test 163: 10011 test 164: 10101 test 165: 10111 test 166: 11001 test 167: 11011 test 168: 11101 test 169: 11110 test 170: 00001 test 171: 00011 test 172: 00101 test 173: 00111 test 174: 01001 test 175: 01011 test 176: 01101 test 177: 01111 test 178: 10001 test 179: 10011 test 180: 10101 test 181: 10111 test 182: 11001 test 183: 11011 test 184: 11101 test 185: 11110 test 186: 00001 test 187: 00011 test 188: 00101 test 189: 00111 test 190: 01001 test 191: 01011 test 192: 01101 test 193: 01111 test 194: 10001 test 195: 10011 test 196: 10101 test 197: 10111 test 198: 11001 test 199: 11011 test 200: 11101 test 201: 11110 test 202: 111101111011110111101111011110 end: END summary column 1: offset 0, mask 0x8000 column 2: offset 0, mask 0x4000 column 3: offset 0, mask 0x2000 column 4: offset 0, mask 0x1000 column 5: offset 0, mask 0x0800 column 6: offset 0, mask 0x0400 column 7: offset 0, mask 0x0200 column 8: offset 0, mask 0x0100 column 9: offset 1, mask 0x8000 column 10: offset 1, mask 0x4000 column 11: offset 1, mask 0x2000 column 12: offset 1, mask 0x1000 column 13: offset 1, mask 0x0800 column 14: offset 1, mask 0x0400 column 15: offset 1, mask 0x0200 column 16: offset 0, mask 0x0010 column 17: offset 0, mask 0x0008 column 18: offset 0, mask 0x0004 column 19: offset 0, mask 0x0002 column 20: offset 0, mask 0x0001 column 21: offset 1, mask 0x0001 column 22: offset 1, mask 0x0002 column 23: offset 1, mask 0x0004 column 24: offset 1, mask 0x0008 column 25: offset 1, mask 0x0010 column 26: offset 1, mask 0x0020 column 27: offset 1, mask 0x0040 column 28: offset 1, mask 0x0080 column 29: offset 2, mask 0x0001 column 30: offset 2, mask 0x0002 direction bits (1=input) 0x08E1 0x4310 0xFFFA 0xFFFF 0xF0FF pullup bits (1=pullup) 0x0000 0x0000 0x0000 0x0000 0x0000 test step out_data dont care 1: 0x0801 0x4210 0x0002 0x0000 0x0000 2: 0x0801 0x4210 0x0002 0x0000 0x0000 3: 0x1801 0x4210 0x0002 0x0000 0x0000 4: 0x2801 0x4210 0x0002 0x0000 0x0000 5: 0x3801 0x4210 0x0002 0x0000 0x0000 6: 0x4801 0x4210 0x0002 0x0000 0x0000 7: 0x5801 0x4210 0x0002 0x0000 0x0000 8: 0x6801 0x4210 0x0002 0x0000 0x0000 9: 0x7801 0x4210 0x0002 0x0000 0x0000 10: 0x8801 0x4210 0x0002 0x0000 0x0000 11: 0x9801 0x4210 0x0002 0x0000 0x0000 12: 0xA801 0x4210 0x0002 0x0000 0x0000 13: 0xB801 0x4210 0x0002 0x0000 0x0000 14: 0xC801 0x4210 0x0002 0x0000 0x0000 15: 0xD801 0x4210 0x0002 0x0000 0x0000 16: 0xE801 0x4210 0x0002 0x0000 0x0000 17: 0xF001 0x4210 0x0002 0x0000 0x0000 18: 0x0801 0x4210 0x0002 0x0000 0x0000 19: 0x0801 0x4210 0x0002 0x0000 0x0000 20: 0x0801 0xC210 0x0002 0x0000 0x0000 21: 0x0901 0x4210 0x0002 0x0000 0x0000 22: 0x0901 0xC210 0x0002 0x0000 0x0000 23: 0x0A01 0x4210 0x0002 0x0000 0x0000 24: 0x0A01 0xC210 0x0002 0x0000 0x0000 25: 0x0B01 0x4210 0x0002 0x0000 0x0000 26: 0x0B01 0xC210 0x0002 0x0000 0x0000 27: 0x0C01 0x4210 0x0002 0x0000 0x0000 28: 0x0C01 0xC210 0x0002 0x0000 0x0000 29: 0x0D01 0x4210 0x0002 0x0000 0x0000 30: 0x0D01 0xC210 0x0002 0x0000 0x0000 31: 0x0E01 0x4210 0x0002 0x0000 0x0000 32: 0x0E01 0xC210 0x0002 0x0000 0x0000 33: 0x0F01 0x4210 0x0002 0x0000 0x0000 34: 0x0F01 0x8210 0x0002 0x0000 0x0000 35: 0x0801 0x4210 0x0002 0x0000 0x0000 36: 0x0801 0x4210 0x0002 0x0000 0x0000 37: 0x0801 0x4610 0x0002 0x0000 0x0000 38: 0x0801 0x4A10 0x0002 0x0000 0x0000 39: 0x0801 0x4E10 0x0002 0x0000 0x0000 40: 0x0801 0x5210 0x0002 0x0000 0x0000 41: 0x0801 0x5610 0x0002 0x0000 0x0000 42: 0x0801 0x5A10 0x0002 0x0000 0x0000 43: 0x0801 0x5E10 0x0002 0x0000 0x0000 44: 0x0801 0x6210 0x0002 0x0000 0x0000 45: 0x0801 0x6610 0x0002 0x0000 0x0000 46: 0x0801 0x6A10 0x0002 0x0000 0x0000 47: 0x0801 0x6E10 0x0002 0x0000 0x0000 48: 0x0801 0x7210 0x0002 0x0000 0x0000 49: 0x0801 0x7610 0x0002 0x0000 0x0000 50: 0x0801 0x7A10 0x0002 0x0000 0x0000 51: 0x0801 0x7C10 0x0002 0x0000 0x0000 52: 0x0801 0x4210 0x0002 0x0000 0x0000 53: 0x0801 0x4210 0x0002 0x0000 0x0000 54: 0x0803 0x4210 0x0002 0x0000 0x0000 55: 0x0805 0x4210 0x0002 0x0000 0x0000 56: 0x0807 0x4210 0x0002 0x0000 0x0000 57: 0x0809 0x4210 0x0002 0x0000 0x0000 58: 0x080B 0x4210 0x0002 0x0000 0x0000 59: 0x080D 0x4210 0x0002 0x0000 0x0000 60: 0x080F 0x4210 0x0002 0x0000 0x0000 61: 0x0811 0x4210 0x0002 0x0000 0x0000 62: 0x0813 0x4210 0x0002 0x0000 0x0000 63: 0x0815 0x4210 0x0002 0x0000 0x0000 64: 0x0817 0x4210 0x0002 0x0000 0x0000 65: 0x0819 0x4210 0x0002 0x0000 0x0000 66: 0x081B 0x4210 0x0002 0x0000 0x0000 67: 0x081D 0x4210 0x0002 0x0000 0x0000 68: 0x081E 0x4210 0x0002 0x0000 0x0000 69: 0x0801 0x4210 0x0002 0x0000 0x0000 70: 0x0801 0x4210 0x0002 0x0000 0x0000 71: 0x0801 0x4218 0x0002 0x0000 0x0000 72: 0x0801 0x4214 0x0002 0x0000 0x0000 73: 0x0801 0x421C 0x0002 0x0000 0x0000 74: 0x0801 0x4212 0x0002 0x0000 0x0000 75: 0x0801 0x421A 0x0002 0x0000 0x0000 76: 0x0801 0x4216 0x0002 0x0000 0x0000 77: 0x0801 0x421E 0x0002 0x0000 0x0000 78: 0x0801 0x4211 0x0002 0x0000 0x0000 79: 0x0801 0x4219 0x0002 0x0000 0x0000 80: 0x0801 0x4215 0x0002 0x0000 0x0000 81: 0x0801 0x421D 0x0002 0x0000 0x0000 82: 0x0801 0x4213 0x0002 0x0000 0x0000 83: 0x0801 0x421B 0x0002 0x0000 0x0000 84: 0x0801 0x4217 0x0002 0x0000 0x0000 85: 0x0801 0x420F 0x0002 0x0000 0x0000 86: 0x0801 0x4210 0x0002 0x0000 0x0000 87: 0x0801 0x4210 0x0002 0x0000 0x0000 88: 0x0801 0x4210 0x0003 0x0000 0x0000 89: 0x0801 0x4290 0x0002 0x0000 0x0000 90: 0x0801 0x4290 0x0003 0x0000 0x0000 91: 0x0801 0x4250 0x0002 0x0000 0x0000 92: 0x0801 0x4250 0x0003 0x0000 0x0000 93: 0x0801 0x42D0 0x0002 0x0000 0x0000 94: 0x0801 0x42D0 0x0003 0x0000 0x0000 95: 0x0801 0x4230 0x0002 0x0000 0x0000 96: 0x0801 0x4230 0x0003 0x0000 0x0000 97: 0x0801 0x42B0 0x0002 0x0000 0x0000 98: 0x0801 0x42B0 0x0003 0x0000 0x0000 99: 0x0801 0x4270 0x0002 0x0000 0x0000 100: 0x0801 0x4270 0x0003 0x0000 0x0000 101: 0x0801 0x42F0 0x0002 0x0000 0x0000 102: 0x0801 0x42F0 0x0001 0x0000 0x0000 103: 0x0801 0x4210 0x0002 0x0000 0x0000 104: 0x0801 0x4210 0x0002 0x0000 0x0000 105: 0xF71E 0xBCEF 0x0001 0x0000 0x0000 106: 0x0F1E 0xBCEF 0x0001 0x0000 0x0000 107: 0x1F1E 0xBCEF 0x0001 0x0000 0x0000 108: 0x2F1E 0xBCEF 0x0001 0x0000 0x0000 109: 0x3F1E 0xBCEF 0x0001 0x0000 0x0000 110: 0x4F1E 0xBCEF 0x0001 0x0000 0x0000 111: 0x5F1E 0xBCEF 0x0001 0x0000 0x0000 112: 0x6F1E 0xBCEF 0x0001 0x0000 0x0000 113: 0x7F1E 0xBCEF 0x0001 0x0000 0x0000 114: 0x8F1E 0xBCEF 0x0001 0x0000 0x0000 115: 0x9F1E 0xBCEF 0x0001 0x0000 0x0000 116: 0xAF1E 0xBCEF 0x0001 0x0000 0x0000 117: 0xBF1E 0xBCEF 0x0001 0x0000 0x0000 118: 0xCF1E 0xBCEF 0x0001 0x0000 0x0000 119: 0xDF1E 0xBCEF 0x0001 0x0000 0x0000 120: 0xEF1E 0xBCEF 0x0001 0x0000 0x0000 121: 0xF71E 0xBCEF 0x0001 0x0000 0x0000 122: 0xF01E 0x7CEF 0x0001 0x0000 0x0000 123: 0xF01E 0xFCEF 0x0001 0x0000 0x0000 124: 0xF11E 0x7CEF 0x0001 0x0000 0x0000 125: 0xF11E 0xFCEF 0x0001 0x0000 0x0000 126: 0xF21E 0x7CEF 0x0001 0x0000 0x0000 127: 0xF21E 0xFCEF 0x0001 0x0000 0x0000 128: 0xF31E 0x7CEF 0x0001 0x0000 0x0000 129: 0xF31E 0xFCEF 0x0001 0x0000 0x0000 130: 0xF41E 0x7CEF 0x0001 0x0000 0x0000 131: 0xF41E 0xFCEF 0x0001 0x0000 0x0000 132: 0xF51E 0x7CEF 0x0001 0x0000 0x0000 133: 0xF51E 0xFCEF 0x0001 0x0000 0x0000 134: 0xF61E 0x7CEF 0x0001 0x0000 0x0000 135: 0xF61E 0xFCEF 0x0001 0x0000 0x0000 136: 0xF71E 0x7CEF 0x0001 0x0000 0x0000 137: 0xF71E 0xBCEF 0x0001 0x0000 0x0000 138: 0xF71E 0x82EF 0x0001 0x0000 0x0000 139: 0xF71E 0x86EF 0x0001 0x0000 0x0000 140: 0xF71E 0x8AEF 0x0001 0x0000 0x0000 141: 0xF71E 0x8EEF 0x0001 0x0000 0x0000 142: 0xF71E 0x92EF 0x0001 0x0000 0x0000 143: 0xF71E 0x96EF 0x0001 0x0000 0x0000 144: 0xF71E 0x9AEF 0x0001 0x0000 0x0000 145: 0xF71E 0x9EEF 0x0001 0x0000 0x0000 146: 0xF71E 0xA2EF 0x0001 0x0000 0x0000 147: 0xF71E 0xA6EF 0x0001 0x0000 0x0000 148: 0xF71E 0xAAEF 0x0001 0x0000 0x0000 149: 0xF71E 0xAEEF 0x0001 0x0000 0x0000 150: 0xF71E 0xB2EF 0x0001 0x0000 0x0000 151: 0xF71E 0xB6EF 0x0001 0x0000 0x0000 152: 0xF71E 0xBAEF 0x0001 0x0000 0x0000 153: 0xF71E 0xBCEF 0x0001 0x0000 0x0000 154: 0xF701 0xBCEF 0x0001 0x0000 0x0000 155: 0xF703 0xBCEF 0x0001 0x0000 0x0000 156: 0xF705 0xBCEF 0x0001 0x0000 0x0000 157: 0xF707 0xBCEF 0x0001 0x0000 0x0000 158: 0xF709 0xBCEF 0x0001 0x0000 0x0000 159: 0xF70B 0xBCEF 0x0001 0x0000 0x0000 160: 0xF70D 0xBCEF 0x0001 0x0000 0x0000 161: 0xF70F 0xBCEF 0x0001 0x0000 0x0000 162: 0xF711 0xBCEF 0x0001 0x0000 0x0000 163: 0xF713 0xBCEF 0x0001 0x0000 0x0000 164: 0xF715 0xBCEF 0x0001 0x0000 0x0000 165: 0xF717 0xBCEF 0x0001 0x0000 0x0000 166: 0xF719 0xBCEF 0x0001 0x0000 0x0000 167: 0xF71B 0xBCEF 0x0001 0x0000 0x0000 168: 0xF71D 0xBCEF 0x0001 0x0000 0x0000 169: 0xF71E 0xBCEF 0x0001 0x0000 0x0000 170: 0xF71E 0xBCF0 0x0001 0x0000 0x0000 171: 0xF71E 0xBCF8 0x0001 0x0000 0x0000 172: 0xF71E 0xBCF4 0x0001 0x0000 0x0000 173: 0xF71E 0xBCFC 0x0001 0x0000 0x0000 174: 0xF71E 0xBCF2 0x0001 0x0000 0x0000 175: 0xF71E 0xBCFA 0x0001 0x0000 0x0000 176: 0xF71E 0xBCF6 0x0001 0x0000 0x0000 177: 0xF71E 0xBCFE 0x0001 0x0000 0x0000 178: 0xF71E 0xBCF1 0x0001 0x0000 0x0000 179: 0xF71E 0xBCF9 0x0001 0x0000 0x0000 180: 0xF71E 0xBCF5 0x0001 0x0000 0x0000 181: 0xF71E 0xBCFD 0x0001 0x0000 0x0000 182: 0xF71E 0xBCF3 0x0001 0x0000 0x0000 183: 0xF71E 0xBCFB 0x0001 0x0000 0x0000 184: 0xF71E 0xBCF7 0x0001 0x0000 0x0000 185: 0xF71E 0xBCEF 0x0001 0x0000 0x0000 186: 0xF71E 0xBC0F 0x0002 0x0000 0x0000 187: 0xF71E 0xBC0F 0x0003 0x0000 0x0000 188: 0xF71E 0xBC8F 0x0002 0x0000 0x0000 189: 0xF71E 0xBC8F 0x0003 0x0000 0x0000 190: 0xF71E 0xBC4F 0x0002 0x0000 0x0000 191: 0xF71E 0xBC4F 0x0003 0x0000 0x0000 192: 0xF71E 0xBCCF 0x0002 0x0000 0x0000 193: 0xF71E 0xBCCF 0x0003 0x0000 0x0000 194: 0xF71E 0xBC2F 0x0002 0x0000 0x0000 195: 0xF71E 0xBC2F 0x0003 0x0000 0x0000 196: 0xF71E 0xBCAF 0x0002 0x0000 0x0000 197: 0xF71E 0xBCAF 0x0003 0x0000 0x0000 198: 0xF71E 0xBC6F 0x0002 0x0000 0x0000 199: 0xF71E 0xBC6F 0x0003 0x0000 0x0000 200: 0xF71E 0xBCEF 0x0002 0x0000 0x0000 201: 0xF71E 0xBCEF 0x0001 0x0000 0x0000 202: 0xF71E 0xBCEF 0x0001 0x0000 0x0000 PINs used (in edge connector order) (G=ground,P=power) SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBB LETTER ABCDEFHJKLMNPRSTUVABCDEFHJKLMNPRSTUVABCDEFHJKLMNPRSTUVABCDEFHJKLMNPRSTUV SIDE 111111111111111111222222222222222222111111111111111111222222222222222222 USAGE IIIIOIIIIOIIIIOG P GIIIIOIIIIOIIIIO G P G UUT has 24 inputs UUT has 6 outputs contains 30 pins/columns 36 pins are not used contains 202 'test steps' M617 REV E 6 4-INPUT NAND BUFFERS (48ma) (7440) PINS Main menu Mon Jul 27 15:22:45 2015 test file is: tests\m617.tst delay is: 0 trigger is: 1 1 read test file 2 set test delay 3 set test trigger 4 run test 5 output loading test 8 diags 9 exit UUT power is okay Mon Jul 27 15:22:47 2015 space single step O run once (one test, all steps) F run, stop on fail G go (run tests N run, stop on fail, no print S scope (run, no print) C toggle comment printout + increase speed (less delay) - decrease speed (more delay)(slower) Q quit test scope (run, no print) FFFFFFFFFFFFFFFFFFFFFFFF space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C toggle comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit step 51 000010000111110000010000100001 step 52 000010000100001000010000100001 step 53 000010000100001000010000100001 step 54 000010000100001000110000100001 step 55 000010000100001001010000100001 step 56 000010000100001001110000100001 step 57 000010000100001010010000100001 step 58 000010000100001010110000100001 step 59 000010000100001011010000100001 step 60 000010000100001011110000100001 step 61 000010000100001100010000100001 step 62 000010000100001100110000100001 step 63 000010000100001101010000100001 step 64 000010000100001101110000100001 step 65 000010000100001110010000100001 step 66 000010000100001110110000100001 step 67 000010000100001111010000100001 step 68 000010000100001111100000100001 step 69 000010000100001000010000100001 step 70 000010000100001000010000100001 step 71 000010000100001000010001100001 step 72 000010000100001000010010100001 step 73 000010000100001000010011100001 step 74 000010000100001000010100100001 step 75 000010000100001000010101100001 step 76 000010000100001000010110100001 step 77 000010000100001000010111100001 step 78 000010000100001000011000100001 step 79 000010000100001000011001100001 step 80 000010000100001000011010100001 step 81 000010000100001000011011100001 step 82 000010000100001000011100100001 step 83 000010000100001000011101100001 step 84 000010000100001000011110100001 step 85 000010000100001000011111000001 step 86 000010000100001000010000100001 step 87 000010000100001000010000100001 step 88 000010000100001000010000100011 step 89 000010000100001000010000100101 step 90 000010000100001000010000100111 step 91 000010000100001000010000101001 step 92 000010000100001000010000101011 step 93 000010000100001000010000101101 step 94 000010000100001000010000101111 step 95 000010000100001000010000110001 step 96 000010000100001000010000110011 step 97 000010000100001000010000110101 step 98 000010000100001000010000110111 step 99 000010000100001000010000111001 step 100 000010000100001000010000111011 step 101 000010000100001000010000111101 step 102 000010000100001000010000111110 step 103 000010000100001000010000100001 step 104 000010000100001000010000100001 step 105 111101111011110111101111011110 step 106 000011111011110111101111011110 step 107 000111111011110111101111011110 step 108 001011111011110111101111011110 SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFHJKLMNPRSDEFHJKLMNPRSTUV SIDE 111111111111111222222222222222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 10 step 109 001101111011110111101111011110 fail ^ step 110 010011111011110111101111011110 step 111 010111111011110111101111011110 step 112 011011111011110111101111011110 SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFHJKLMNPRSDEFHJKLMNPRSTUV SIDE 111111111111111222222222222222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 10 step 113 011101111011110111101111011110 fail ^ step 114 100011111011110111101111011110 step 115 100111111011110111101111011110 step 116 101011111011110111101111011110 SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFHJKLMNPRSDEFHJKLMNPRSTUV SIDE 111111111111111222222222222222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 10 step 117 101101111011110111101111011110 fail ^ step 118 110011111011110111101111011110 step 119 110111111011110111101111011110 step 120 111011111011110111101111011110 step 121 111101111011110111101111011110 step 122 111100000111110111101111011110 step 123 111100001111110111101111011110 step 124 111100010111110111101111011110 step 125 111100011111110111101111011110 step 126 111100100111110111101111011110 step 127 111100101111110111101111011110 step 128 111100110111110111101111011110 step 129 111100111111110111101111011110 step 130 111101000111110111101111011110 step 131 111101001111110111101111011110 step 132 111101010111110111101111011110 step 133 111101011111110111101111011110 step 134 111101100111110111101111011110 step 135 111101101111110111101111011110 step 136 111101110111110111101111011110 step 137 111101111011110111101111011110 step 138 111101111000001111101111011110 step 139 111101111000011111101111011110 step 140 111101111000101111101111011110 step 141 111101111000111111101111011110 step 142 111101111001001111101111011110 step 143 111101111001011111101111011110 step 144 111101111001101111101111011110 step 145 111101111001111111101111011110 step 146 111101111010001111101111011110 step 147 111101111010011111101111011110 step 148 111101111010101111101111011110 step 149 111101111010111111101111011110 step 150 111101111011001111101111011110 step 151 111101111011011111101111011110 step 152 111101111011101111101111011110 step 153 111101111011110111101111011110 step 154 111101111011110000011111011110 step 155 111101111011110000111111011110 step 156 111101111011110001011111011110 step 157 111101111011110001111111011110 step 158 111101111011110010011111011110 step 159 111101111011110010111111011110 step 160 111101111011110011011111011110 step 161 111101111011110011111111011110 step 162 111101111011110100011111011110 step 163 111101111011110100111111011110 step 164 111101111011110101011111011110 step 165 111101111011110101111111011110 step 166 111101111011110110011111011110 step 167 111101111011110110111111011110 step 168 111101111011110111011111011110 step 169 111101111011110111101111011110 step 170 111101111011110111100000111110 step 171 111101111011110111100001111110 step 172 111101111011110111100010111110 step 173 111101111011110111100011111110 step 174 111101111011110111100100111110 step 175 111101111011110111100101111110 step 176 111101111011110111100110111110 step 177 111101111011110111100111111110 step 178 111101111011110111101000111110 step 179 111101111011110111101001111110 step 180 111101111011110111101010111110 step 181 111101111011110111101011111110 step 182 111101111011110111101100111110 step 183 111101111011110111101101111110 step 184 111101111011110111101110111110 step 185 111101111011110111101111011110 step 186 111101111011110111101111000001 step 187 111101111011110111101111000011 step 188 111101111011110111101111000101 step 189 111101111011110111101111000111 step 190 111101111011110111101111001001 step 191 111101111011110111101111001011 step 192 111101111011110111101111001101 step 193 111101111011110111101111001111 step 194 111101111011110111101111010001 step 195 111101111011110111101111010011 step 196 111101111011110111101111010101 step 197 111101111011110111101111010111 step 198 111101111011110111101111011001 step 199 111101111011110111101111011011 step 200 111101111011110111101111011101 step 201 111101111011110111101111011110 step 202 111101111011110111101111011110 test 25: *** FAIL *************************** 6 steps failed SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFHJKLMNPRSDEFHJKLMNPRSTUV SIDE 111111111111111222222222222222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO this fail O all fails O was hi 111111111111111111111111111111 rising ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ falling vvvvvvvvvvvvvvvvvvvvvvvvvvvvvv was lo 000000000000000000000000000000 total fails 25, total passes 0 step 1 000010000100001000010000100001 step 2 000010000100001000010000100001 step 3 000110000100001000010000100001 step 4 001010000100001000010000100001 SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFHJKLMNPRSDEFHJKLMNPRSTUV SIDE 111111111111111222222222222222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 10 step 5 001100000100001000010000100001 fail ^ step 6 010010000100001000010000100001 step 7 010110000100001000010000100001 step 8 011010000100001000010000100001 SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFHJKLMNPRSDEFHJKLMNPRSTUV SIDE 111111111111111222222222222222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 10 step 9 011100000100001000010000100001 fail ^ step 10 100010000100001000010000100001 step 11 100110000100001000010000100001 step 12 101010000100001000010000100001 SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFHJKLMNPRSDEFHJKLMNPRSTUV SIDE 111111111111111222222222222222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 10 step 13 101100000100001000010000100001 fail ^ step 14 110010000100001000010000100001 step 15 110110000100001000010000100001 step 16 111010000100001000010000100001 step 17 111100000100001000010000100001 step 18 000010000100001000010000100001 step 19 000010000100001000010000100001 step 20 000010001100001000010000100001 step 21 000010010100001000010000100001 step 22 000010011100001000010000100001 step 23 000010100100001000010000100001 step 24 000010101100001000010000100001 step 25 000010110100001000010000100001 step 26 000010111100001000010000100001 step 27 000011000100001000010000100001 step 28 000011001100001000010000100001 step 29 000011010100001000010000100001 step 30 000011011100001000010000100001 step 31 000011100100001000010000100001 step 32 000011101100001000010000100001 step 33 000011110100001000010000100001 step 34 000011111000001000010000100001 step 35 000010000100001000010000100001 step 36 000010000100001000010000100001 step 37 000010000100011000010000100001 step 38 000010000100101000010000100001 step 39 000010000100111000010000100001 step 40 000010000101001000010000100001 step 41 000010000101011000010000100001 step 42 000010000101101000010000100001 step 43 000010000101111000010000100001 step 44 000010000110001000010000100001 step 45 000010000110011000010000100001 step 46 000010000110101000010000100001 step 47 000010000110111000010000100001 step 48 000010000111001000010000100001 step 49 000010000111011000010000100001 step 50 000010000111101000010000100001 step 51 000010000111110000010000100001 step 52 000010000100001000010000100001 step 53 000010000100001000010000100001 step 54 000010000100001000110000100001 step 55 000010000100001001010000100001 step 56 000010000100001001110000100001 step 57 000010000100001010010000100001 step 58 000010000100001010110000100001 step 59 000010000100001011010000100001 step 60 000010000100001011110000100001 step 61 000010000100001100010000100001 step 62 000010000100001100110000100001 step 63 000010000100001101010000100001 step 64 000010000100001101110000100001 step 65 000010000100001110010000100001 step 66 000010000100001110110000100001 step 67 000010000100001111010000100001 step 68 000010000100001111100000100001 step 69 000010000100001000010000100001 step 70 000010000100001000010000100001 step 71 000010000100001000010001100001 step 72 000010000100001000010010100001 step 73 000010000100001000010011100001 step 74 000010000100001000010100100001 step 75 000010000100001000010101100001 step 76 000010000100001000010110100001 step 77 000010000100001000010111100001 step 78 000010000100001000011000100001 step 79 000010000100001000011001100001 step 80 000010000100001000011010100001 step 81 000010000100001000011011100001 step 82 000010000100001000011100100001 step 83 000010000100001000011101100001 step 84 000010000100001000011110100001 step 85 000010000100001000011111000001 step 86 000010000100001000010000100001 step 87 000010000100001000010000100001 step 88 000010000100001000010000100011 step 89 000010000100001000010000100101 step 90 000010000100001000010000100111 step 91 000010000100001000010000101001 step 92 000010000100001000010000101011 step 93 000010000100001000010000101101 step 94 000010000100001000010000101111 step 95 000010000100001000010000110001 step 96 000010000100001000010000110011 step 97 000010000100001000010000110101 step 98 000010000100001000010000110111 step 99 000010000100001000010000111001 step 100 000010000100001000010000111011 step 101 000010000100001000010000111101 step 102 000010000100001000010000111110 step 103 000010000100001000010000100001 step 104 000010000100001000010000100001 step 105 111101111011110111101111011110 step 106 000011111011110111101111011110 step 107 000111111011110111101111011110 step 108 001011111011110111101111011110 SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFHJKLMNPRSDEFHJKLMNPRSTUV SIDE 111111111111111222222222222222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 10 step 109 001101111011110111101111011110 fail ^ step 110 010011111011110111101111011110 step 111 010111111011110111101111011110 step 112 011011111011110111101111011110 SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFHJKLMNPRSDEFHJKLMNPRSTUV SIDE 111111111111111222222222222222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 10 step 113 011101111011110111101111011110 fail ^ step 114 100011111011110111101111011110 step 115 100111111011110111101111011110 step 116 101011111011110111101111011110 SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFHJKLMNPRSDEFHJKLMNPRSTUV SIDE 111111111111111222222222222222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 10 step 117 101101111011110111101111011110 fail ^ step 118 110011111011110111101111011110 step 119 110111111011110111101111011110 step 120 111011111011110111101111011110 step 121 111101111011110111101111011110 step 122 111100000111110111101111011110 step 123 111100001111110111101111011110 step 124 111100010111110111101111011110 step 125 111100011111110111101111011110 step 126 111100100111110111101111011110 step 127 111100101111110111101111011110 step 128 111100110111110111101111011110 step 129 111100111111110111101111011110 step 130 111101000111110111101111011110 step 131 111101001111110111101111011110 step 132 111101010111110111101111011110 step 133 111101011111110111101111011110 step 134 111101100111110111101111011110 step 135 111101101111110111101111011110 step 136 111101110111110111101111011110 step 137 111101111011110111101111011110 step 138 111101111000001111101111011110 step 139 111101111000011111101111011110 step 140 111101111000101111101111011110 step 141 111101111000111111101111011110 step 142 111101111001001111101111011110 step 143 111101111001011111101111011110 step 144 111101111001101111101111011110 step 145 111101111001111111101111011110 step 146 111101111010001111101111011110 step 147 111101111010011111101111011110 step 148 111101111010101111101111011110 step 149 111101111010111111101111011110 step 150 111101111011001111101111011110 step 151 111101111011011111101111011110 step 152 111101111011101111101111011110 step 153 111101111011110111101111011110 step 154 111101111011110000011111011110 step 155 111101111011110000111111011110 step 156 111101111011110001011111011110 step 157 111101111011110001111111011110 step 158 111101111011110010011111011110 step 159 111101111011110010111111011110 step 160 111101111011110011011111011110 step 161 111101111011110011111111011110 step 162 111101111011110100011111011110 step 163 111101111011110100111111011110 step 164 111101111011110101011111011110 step 165 111101111011110101111111011110 step 166 111101111011110110011111011110 step 167 111101111011110110111111011110 step 168 111101111011110111011111011110 step 169 111101111011110111101111011110 step 170 111101111011110111100000111110 step 171 111101111011110111100001111110 step 172 111101111011110111100010111110 step 173 111101111011110111100011111110 step 174 111101111011110111100100111110 step 175 111101111011110111100101111110 step 176 111101111011110111100110111110 step 177 111101111011110111100111111110 step 178 111101111011110111101000111110 step 179 111101111011110111101001111110 step 180 111101111011110111101010111110 step 181 111101111011110111101011111110 step 182 111101111011110111101100111110 step 183 111101111011110111101101111110 step 184 111101111011110111101110111110 step 185 111101111011110111101111011110 step 186 111101111011110111101111000001 step 187 111101111011110111101111000011 step 188 111101111011110111101111000101 step 189 111101111011110111101111000111 step 190 111101111011110111101111001001 step 191 111101111011110111101111001011 step 192 111101111011110111101111001101 step 193 111101111011110111101111001111 step 194 111101111011110111101111010001 step 195 111101111011110111101111010011 step 196 111101111011110111101111010101 step 197 111101111011110111101111010111 step 198 111101111011110111101111011001 step 199 111101111011110111101111011011 step 200 111101111011110111101111011101 step 201 111101111011110111101111011110 step 202 111101111011110111101111011110 test 26: *** FAIL *************************** 6 steps failed SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFHJKLMNPRSDEFHJKLMNPRSTUV SIDE 111111111111111222222222222222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO this fail O all fails O was hi 111111111111111111111111111111 rising ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ falling vvvvvvvvvvvvvvvvvvvvvvvvvvvvvv was lo 000000000000000000000000000000 total fails 26, total passes 0 step 1 000010000100001000010000100001 step 2 000010000100001000010000100001 step 3 000110000100001000010000100001 step 4 001010000100001000010000100001 SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFHJKLMNPRSDEFHJKLMNPRSTUV SIDE 111111111111111222222222222222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 10 step 5 001100000100001000010000100001 fail ^ step 6 010010000100001000010000100001 step 7 010110000100001000010000100001 step 8 011010000100001000010000100001 SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFHJKLMNPRSDEFHJKLMNPRSTUV SIDE 111111111111111222222222222222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 10 step 9 011100000100001000010000100001 fail ^ step 10 100010000100001000010000100001 step 11 100110000100001000010000100001 step 12 101010000100001000010000100001 SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFHJKLMNPRSDEFHJKLMNPRSTUV SIDE 111111111111111222222222222222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 10 step 13 101100000100001000010000100001 fail ^ step 14 110010000100001000010000100001 step 15 110110000100001000010000100001 step 16 111010000100001000010000100001 step 17 111100000100001000010000100001 step 18 000010000100001000010000100001 step 19 000010000100001000010000100001 step 20 000010001100001000010000100001 step 21 000010010100001000010000100001 step 22 000010011100001000010000100001 step 23 000010100100001000010000100001 step 24 000010101100001000010000100001 step 25 000010110100001000010000100001 step 26 000010111100001000010000100001 step 27 000011000100001000010000100001 step 28 000011001100001000010000100001 step 29 000011010100001000010000100001 step 30 000011011100001000010000100001 step 31 000011100100001000010000100001 step 32 000011101100001000010000100001 step 33 000011110100001000010000100001 step 34 000011111000001000010000100001 step 35 000010000100001000010000100001 step 36 000010000100001000010000100001 step 37 000010000100011000010000100001 step 38 000010000100101000010000100001 step 39 000010000100111000010000100001 step 40 000010000101001000010000100001 step 41 000010000101011000010000100001 step 42 000010000101101000010000100001 step 43 000010000101111000010000100001 step 44 000010000110001000010000100001 step 45 000010000110011000010000100001 step 46 000010000110101000010000100001 step 47 000010000110111000010000100001 step 48 000010000111001000010000100001 step 49 000010000111011000010000100001 step 50 000010000111101000010000100001 step 51 000010000111110000010000100001 step 52 000010000100001000010000100001 step 53 000010000100001000010000100001 step 54 000010000100001000110000100001 step 55 000010000100001001010000100001 step 56 000010000100001001110000100001 step 57 000010000100001010010000100001 step 58 000010000100001010110000100001 step 59 000010000100001011010000100001 step 60 000010000100001011110000100001 step 61 000010000100001100010000100001 step 62 000010000100001100110000100001 step 63 000010000100001101010000100001 step 64 000010000100001101110000100001 step 65 000010000100001110010000100001 step 66 000010000100001110110000100001 step 67 000010000100001111010000100001 step 68 000010000100001111100000100001 step 69 000010000100001000010000100001 step 70 000010000100001000010000100001 step 71 000010000100001000010001100001 step 72 000010000100001000010010100001 step 73 000010000100001000010011100001 step 74 000010000100001000010100100001 step 75 000010000100001000010101100001 step 76 000010000100001000010110100001 step 77 000010000100001000010111100001 step 78 000010000100001000011000100001 step 79 000010000100001000011001100001 step 80 000010000100001000011010100001 step 81 000010000100001000011011100001 step 82 000010000100001000011100100001 step 83 000010000100001000011101100001 step 84 000010000100001000011110100001 step 85 000010000100001000011111000001 step 86 000010000100001000010000100001 step 87 000010000100001000010000100001 step 88 000010000100001000010000100011 step 89 000010000100001000010000100101 step 90 000010000100001000010000100111 step 91 000010000100001000010000101001 step 92 000010000100001000010000101011 step 93 000010000100001000010000101101 step 94 000010000100001000010000101111 step 95 000010000100001000010000110001 step 96 000010000100001000010000110011 step 97 000010000100001000010000110101 step 98 000010000100001000010000110111 step 99 000010000100001000010000111001 step 100 000010000100001000010000111011 step 101 000010000100001000010000111101 step 102 000010000100001000010000111110 step 103 000010000100001000010000100001 step 104 000010000100001000010000100001 step 105 111101111011110111101111011110 step 106 000011111011110111101111011110 step 107 000111111011110111101111011110 step 108 001011111011110111101111011110 SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFHJKLMNPRSDEFHJKLMNPRSTUV SIDE 111111111111111222222222222222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 10 step 109 001101111011110111101111011110 fail ^ step 110 010011111011110111101111011110 step 111 010111111011110111101111011110 step 112 011011111011110111101111011110 SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFHJKLMNPRSDEFHJKLMNPRSTUV SIDE 111111111111111222222222222222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 10 step 113 011101111011110111101111011110 fail ^ step 114 100011111011110111101111011110 step 115 100111111011110111101111011110 step 116 101011111011110111101111011110 SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFHJKLMNPRSDEFHJKLMNPRSTUV SIDE 111111111111111222222222222222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 10 step 117 101101111011110111101111011110 fail ^ step 118 110011111011110111101111011110 step 119 110111111011110111101111011110 step 120 111011111011110111101111011110 step 121 111101111011110111101111011110 step 122 111100000111110111101111011110 step 123 111100001111110111101111011110 step 124 111100010111110111101111011110 step 125 111100011111110111101111011110 step 126 111100100111110111101111011110 step 127 111100101111110111101111011110 step 128 111100110111110111101111011110 step 129 111100111111110111101111011110 step 130 111101000111110111101111011110 step 131 111101001111110111101111011110 step 132 111101010111110111101111011110 step 133 111101011111110111101111011110 step 134 111101100111110111101111011110 step 135 111101101111110111101111011110 step 136 111101110111110111101111011110 step 137 111101111011110111101111011110 step 138 111101111000001111101111011110 step 139 111101111000011111101111011110 step 140 111101111000101111101111011110 step 141 111101111000111111101111011110 step 142 111101111001001111101111011110 step 143 111101111001011111101111011110 step 144 111101111001101111101111011110 step 145 111101111001111111101111011110 step 146 111101111010001111101111011110 step 147 111101111010011111101111011110 step 148 111101111010101111101111011110 step 149 111101111010111111101111011110 step 150 111101111011001111101111011110 step 151 111101111011011111101111011110 step 152 111101111011101111101111011110 step 153 111101111011110111101111011110 step 154 111101111011110000011111011110 step 155 111101111011110000111111011110 step 156 111101111011110001011111011110 step 157 111101111011110001111111011110 step 158 111101111011110010011111011110 step 159 111101111011110010111111011110 step 160 111101111011110011011111011110 step 161 111101111011110011111111011110 step 162 111101111011110100011111011110 step 163 111101111011110100111111011110 step 164 111101111011110101011111011110 step 165 111101111011110101111111011110 step 166 111101111011110110011111011110 step 167 111101111011110110111111011110 step 168 111101111011110111011111011110 step 169 111101111011110111101111011110 step 170 111101111011110111100000111110 step 171 111101111011110111100001111110 step 172 111101111011110111100010111110 step 173 111101111011110111100011111110 step 174 111101111011110111100100111110 step 175 111101111011110111100101111110 step 176 111101111011110111100110111110 step 177 111101111011110111100111111110 step 178 111101111011110111101000111110 step 179 111101111011110111101001111110 step 180 111101111011110111101010111110 step 181 111101111011110111101011111110 step 182 111101111011110111101100111110 step 183 111101111011110111101101111110 step 184 111101111011110111101110111110 step 185 111101111011110111101111011110 step 186 111101111011110111101111000001 step 187 111101111011110111101111000011 step 188 111101111011110111101111000101 step 189 111101111011110111101111000111 step 190 111101111011110111101111001001 step 191 111101111011110111101111001011 step 192 111101111011110111101111001101 step 193 111101111011110111101111001111 step 194 111101111011110111101111010001 step 195 111101111011110111101111010011 step 196 111101111011110111101111010101 step 197 111101111011110111101111010111 step 198 111101111011110111101111011001 step 199 111101111011110111101111011011 step 200 111101111011110111101111011101 step 201 111101111011110111101111011110 step 202 111101111011110111101111011110 test 27: *** FAIL *************************** 6 steps failed SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFHJKLMNPRSDEFHJKLMNPRSTUV SIDE 111111111111111222222222222222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO this fail O all fails O was hi 111111111111111111111111111111 rising ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ falling vvvvvvvvvvvvvvvvvvvvvvvvvvvvvv was lo 000000000000000000000000000000 total fails 27, total passes 0 step 1 000010000100001000010000100001 step 2 000010000100001000010000100001 step 3 000110000100001000010000100001 step 4 001010000100001000010000100001 SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFHJKLMNPRSDEFHJKLMNPRSTUV SIDE 111111111111111222222222222222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 10 step 5 001100000100001000010000100001 fail ^ step 6 010010000100001000010000100001 step 7 010110000100001000010000100001 step 8 011010000100001000010000100001 SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFHJKLMNPRSDEFHJKLMNPRSTUV SIDE 111111111111111222222222222222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 10 step 9 011100000100001000010000100001 fail ^ step 10 100010000100001000010000100001 step 11 100110000100001000010000100001 step 12 101010000100001000010000100001 SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFHJKLMNPRSDEFHJKLMNPRSTUV SIDE 111111111111111222222222222222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 10 step 13 101100000100001000010000100001 fail ^ step 14 110010000100001000010000100001 step 15 110110000100001000010000100001 step 16 111010000100001000010000100001 step 17 111100000100001000010000100001 step 18 000010000100001000010000100001 step 19 000010000100001000010000100001 step 20 000010001100001000010000100001 step 21 000010010100001000010000100001 step 22 000010011100001000010000100001 step 23 000010100100001000010000100001 step 24 000010101100001000010000100001 step 25 000010110100001000010000100001 step 26 000010111100001000010000100001 step 27 000011000100001000010000100001 step 28 000011001100001000010000100001 step 29 000011010100001000010000100001 step 30 000011011100001000010000100001 step 31 000011100100001000010000100001 step 32 000011101100001000010000100001 step 33 000011110100001000010000100001 step 34 000011111000001000010000100001 step 35 000010000100001000010000100001 step 36 000010000100001000010000100001 step 37 000010000100011000010000100001 step 38 000010000100101000010000100001 step 39 000010000100111000010000100001 step 40 000010000101001000010000100001 step 41 000010000101011000010000100001 step 42 000010000101101000010000100001 step 43 000010000101111000010000100001 step 44 000010000110001000010000100001 step 45 000010000110011000010000100001 step 46 000010000110101000010000100001 step 47 000010000110111000010000100001 step 48 000010000111001000010000100001 step 49 000010000111011000010000100001 step 50 000010000111101000010000100001 step 51 000010000111110000010000100001 step 52 000010000100001000010000100001 step 53 000010000100001000010000100001 step 54 000010000100001000110000100001 step 55 000010000100001001010000100001 step 56 000010000100001001110000100001 step 57 000010000100001010010000100001 step 58 000010000100001010110000100001 step 59 000010000100001011010000100001 step 60 000010000100001011110000100001 step 61 000010000100001100010000100001 step 62 000010000100001100110000100001 step 63 000010000100001101010000100001 step 64 000010000100001101110000100001 step 65 000010000100001110010000100001 step 66 000010000100001110110000100001 step 67 000010000100001111010000100001 step 68 000010000100001111100000100001 step 69 000010000100001000010000100001 step 70 000010000100001000010000100001 step 71 000010000100001000010001100001 step 72 000010000100001000010010100001 step 73 000010000100001000010011100001 step 74 000010000100001000010100100001 step 75 000010000100001000010101100001 step 76 000010000100001000010110100001 step 77 000010000100001000010111100001 step 78 000010000100001000011000100001 step 79 000010000100001000011001100001 step 80 000010000100001000011010100001 step 81 000010000100001000011011100001 step 82 000010000100001000011100100001 step 83 000010000100001000011101100001 step 84 000010000100001000011110100001 step 85 000010000100001000011111000001 step 86 000010000100001000010000100001 step 87 000010000100001000010000100001 step 88 000010000100001000010000100011 step 89 000010000100001000010000100101 step 90 000010000100001000010000100111 step 91 000010000100001000010000101001 step 92 000010000100001000010000101011 step 93 000010000100001000010000101101 step 94 000010000100001000010000101111 step 95 000010000100001000010000110001 step 96 000010000100001000010000110011 step 97 000010000100001000010000110101 step 98 000010000100001000010000110111 step 99 000010000100001000010000111001 step 100 000010000100001000010000111011 step 101 000010000100001000010000111101 step 102 000010000100001000010000111110 step 103 000010000100001000010000100001 step 104 000010000100001000010000100001 step 105 111101111011110111101111011110 step 106 000011111011110111101111011110 step 107 000111111011110111101111011110 step 108 001011111011110111101111011110 SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFHJKLMNPRSDEFHJKLMNPRSTUV SIDE 111111111111111222222222222222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 10 step 109 001101111011110111101111011110 fail ^ step 110 010011111011110111101111011110 step 111 010111111011110111101111011110 step 112 011011111011110111101111011110 SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFHJKLMNPRSDEFHJKLMNPRSTUV SIDE 111111111111111222222222222222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 10 step 113 011101111011110111101111011110 fail ^ step 114 100011111011110111101111011110 step 115 100111111011110111101111011110 step 116 101011111011110111101111011110 SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFHJKLMNPRSDEFHJKLMNPRSTUV SIDE 111111111111111222222222222222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 10 step 117 101101111011110111101111011110 fail ^ step 118 110011111011110111101111011110 step 119 110111111011110111101111011110 step 120 111011111011110111101111011110 step 121 111101111011110111101111011110 step 122 111100000111110111101111011110 step 123 111100001111110111101111011110 step 124 111100010111110111101111011110 step 125 111100011111110111101111011110 step 126 111100100111110111101111011110 step 127 111100101111110111101111011110 step 128 111100110111110111101111011110 step 129 111100111111110111101111011110 step 130 111101000111110111101111011110 step 131 111101001111110111101111011110 step 132 111101010111110111101111011110 step 133 111101011111110111101111011110 step 134 111101100111110111101111011110 step 135 111101101111110111101111011110 step 136 111101110111110111101111011110 step 137 111101111011110111101111011110 step 138 111101111000001111101111011110 step 139 111101111000011111101111011110 step 140 111101111000101111101111011110 step 141 111101111000111111101111011110 step 142 111101111001001111101111011110 step 143 111101111001011111101111011110 step 144 111101111001101111101111011110 step 145 111101111001111111101111011110 step 146 111101111010001111101111011110 step 147 111101111010011111101111011110 step 148 111101111010101111101111011110 step 149 111101111010111111101111011110 step 150 111101111011001111101111011110 step 151 111101111011011111101111011110 step 152 111101111011101111101111011110 step 153 111101111011110111101111011110 step 154 111101111011110000011111011110 step 155 111101111011110000111111011110 step 156 111101111011110001011111011110 step 157 111101111011110001111111011110 step 158 111101111011110010011111011110 step 159 111101111011110010111111011110 step 160 111101111011110011011111011110 step 161 111101111011110011111111011110 step 162 111101111011110100011111011110 step 163 111101111011110100111111011110 step 164 111101111011110101011111011110 step 165 111101111011110101111111011110 step 166 111101111011110110011111011110 step 167 111101111011110110111111011110 step 168 111101111011110111011111011110 step 169 111101111011110111101111011110 step 170 111101111011110111100000111110 step 171 111101111011110111100001111110 step 172 111101111011110111100010111110 step 173 111101111011110111100011111110 step 174 111101111011110111100100111110 step 175 111101111011110111100101111110 step 176 111101111011110111100110111110 step 177 111101111011110111100111111110 step 178 111101111011110111101000111110 step 179 111101111011110111101001111110 step 180 111101111011110111101010111110 step 181 111101111011110111101011111110 step 182 111101111011110111101100111110 step 183 111101111011110111101101111110 step 184 111101111011110111101110111110 step 185 111101111011110111101111011110 step 186 111101111011110111101111000001 step 187 111101111011110111101111000011 step 188 111101111011110111101111000101 step 189 111101111011110111101111000111 step 190 111101111011110111101111001001 step 191 111101111011110111101111001011 step 192 111101111011110111101111001101 step 193 111101111011110111101111001111 step 194 111101111011110111101111010001 step 195 111101111011110111101111010011 step 196 111101111011110111101111010101 step 197 111101111011110111101111010111 step 198 111101111011110111101111011001 step 199 111101111011110111101111011011 step 200 111101111011110111101111011101 step 201 111101111011110111101111011110 step 202 111101111011110111101111011110 test 28: *** FAIL *************************** 6 steps failed SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFHJKLMNPRSDEFHJKLMNPRSTUV SIDE 111111111111111222222222222222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO this fail O all fails O was hi 111111111111111111111111111111 rising ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ falling vvvvvvvvvvvvvvvvvvvvvvvvvvvvvv was lo 000000000000000000000000000000 total fails 28, total passes 0 step 1 000010000100001000010000100001 step 2 000010000100001000010000100001 step 3 000110000100001000010000100001 step 4 001010000100001000010000100001 SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFHJKLMNPRSDEFHJKLMNPRSTUV SIDE 111111111111111222222222222222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 10 step 5 001100000100001000010000100001 fail ^ step 6 010010000100001000010000100001 step 7 010110000100001000010000100001 step 8 011010000100001000010000100001 SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFHJKLMNPRSDEFHJKLMNPRSTUV SIDE 111111111111111222222222222222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 10 step 9 011100000100001000010000100001 fail ^ step 10 100010000100001000010000100001 step 11 100110000100001000010000100001 step 12 101010000100001000010000100001 SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFHJKLMNPRSDEFHJKLMNPRSTUV SIDE 111111111111111222222222222222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 10 step 13 101100000100001000010000100001 fail ^ step 14 110010000100001000010000100001 step 15 110110000100001000010000100001 step 16 111010000100001000010000100001 step 17 111100000100001000010000100001 step 18 000010000100001000010000100001 step 19 000010000100001000010000100001 step 20 000010001100001000010000100001 step 21 000010010100001000010000100001 step 22 000010011100001000010000100001 step 23 000010100100001000010000100001 step 24 000010101100001000010000100001 step 25 000010110100001000010000100001 step 26 000010111100001000010000100001 step 27 000011000100001000010000100001 step 28 000011001100001000010000100001 step 29 000011010100001000010000100001 step 30 000011011100001000010000100001 step 31 000011100100001000010000100001 step 32 000011101100001000010000100001 step 33 000011110100001000010000100001 step 34 000011111000001000010000100001 step 35 000010000100001000010000100001 step 36 000010000100001000010000100001 step 37 000010000100011000010000100001 step 38 000010000100101000010000100001 step 39 000010000100111000010000100001 step 40 000010000101001000010000100001 step 41 000010000101011000010000100001 step 42 000010000101101000010000100001 step 43 000010000101111000010000100001 step 44 000010000110001000010000100001 step 45 000010000110011000010000100001 step 46 000010000110101000010000100001 step 47 000010000110111000010000100001 step 48 000010000111001000010000100001 step 49 000010000111011000010000100001 step 50 000010000111101000010000100001 step 51 000010000111110000010000100001 step 52 000010000100001000010000100001 step 53 000010000100001000010000100001 step 54 000010000100001000110000100001 step 55 000010000100001001010000100001 step 56 000010000100001001110000100001 step 57 000010000100001010010000100001 step 58 000010000100001010110000100001 step 59 000010000100001011010000100001 step 60 000010000100001011110000100001 step 61 000010000100001100010000100001 step 62 000010000100001100110000100001 step 63 000010000100001101010000100001 step 64 000010000100001101110000100001 step 65 000010000100001110010000100001 step 66 000010000100001110110000100001 step 67 000010000100001111010000100001 step 68 000010000100001111100000100001 step 69 000010000100001000010000100001 step 70 000010000100001000010000100001 step 71 000010000100001000010001100001 step 72 000010000100001000010010100001 step 73 000010000100001000010011100001 step 74 000010000100001000010100100001 step 75 000010000100001000010101100001 step 76 000010000100001000010110100001 step 77 000010000100001000010111100001 step 78 000010000100001000011000100001 step 79 000010000100001000011001100001 step 80 000010000100001000011010100001 step 81 000010000100001000011011100001 step 82 000010000100001000011100100001 step 83 000010000100001000011101100001 step 84 000010000100001000011110100001 step 85 000010000100001000011111000001 step 86 000010000100001000010000100001 step 87 000010000100001000010000100001 step 88 000010000100001000010000100011 step 89 000010000100001000010000100101 step 90 000010000100001000010000100111 step 91 000010000100001000010000101001 step 92 000010000100001000010000101011 step 93 000010000100001000010000101101 step 94 000010000100001000010000101111 step 95 000010000100001000010000110001 step 96 000010000100001000010000110011 step 97 000010000100001000010000110101 step 98 000010000100001000010000110111 step 99 000010000100001000010000111001 step 100 000010000100001000010000111011 step 101 000010000100001000010000111101 step 102 000010000100001000010000111110 step 103 000010000100001000010000100001 step 104 000010000100001000010000100001 step 105 111101111011110111101111011110 step 106 000011111011110111101111011110 step 107 000111111011110111101111011110 step 108 001011111011110111101111011110 SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFHJKLMNPRSDEFHJKLMNPRSTUV SIDE 111111111111111222222222222222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 10 step 109 001101111011110111101111011110 fail ^ step 110 010011111011110111101111011110 step 111 010111111011110111101111011110 step 112 011011111011110111101111011110 SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFHJKLMNPRSDEFHJKLMNPRSTUV SIDE 111111111111111222222222222222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 10 step 113 011101111011110111101111011110 fail ^ step 114 100011111011110111101111011110 step 115 100111111011110111101111011110 step 116 101011111011110111101111011110 SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFHJKLMNPRSDEFHJKLMNPRSTUV SIDE 111111111111111222222222222222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 10 step 117 101101111011110111101111011110 fail ^ step 118 110011111011110111101111011110 step 119 110111111011110111101111011110 step 120 111011111011110111101111011110 step 121 111101111011110111101111011110 step 122 111100000111110111101111011110 step 123 111100001111110111101111011110 step 124 111100010111110111101111011110 step 125 111100011111110111101111011110 step 126 111100100111110111101111011110 step 127 111100101111110111101111011110 step 128 111100110111110111101111011110 step 129 111100111111110111101111011110 step 130 111101000111110111101111011110 step 131 111101001111110111101111011110 step 132 111101010111110111101111011110 step 133 111101011111110111101111011110 step 134 111101100111110111101111011110 step 135 111101101111110111101111011110 step 136 111101110111110111101111011110 step 137 111101111011110111101111011110 step 138 111101111000001111101111011110 step 139 111101111000011111101111011110 step 140 111101111000101111101111011110 step 141 111101111000111111101111011110 step 142 111101111001001111101111011110 step 143 111101111001011111101111011110 step 144 111101111001101111101111011110 step 145 111101111001111111101111011110 step 146 111101111010001111101111011110 step 147 111101111010011111101111011110 step 148 111101111010101111101111011110 step 149 111101111010111111101111011110 step 150 111101111011001111101111011110 step 151 111101111011011111101111011110 step 152 111101111011101111101111011110 step 153 111101111011110111101111011110 step 154 111101111011110000011111011110 step 155 111101111011110000111111011110 step 156 111101111011110001011111011110 step 157 111101111011110001111111011110 step 158 111101111011110010011111011110 step 159 111101111011110010111111011110 step 160 111101111011110011011111011110 step 161 111101111011110011111111011110 step 162 111101111011110100011111011110 step 163 111101111011110100111111011110 step 164 111101111011110101011111011110 step 165 111101111011110101111111011110 step 166 111101111011110110011111011110 step 167 111101111011110110111111011110 step 168 111101111011110111011111011110 step 169 111101111011110111101111011110 step 170 111101111011110111100000111110 step 171 111101111011110111100001111110 step 172 111101111011110111100010111110 step 173 111101111011110111100011111110 step 174 111101111011110111100100111110 step 175 111101111011110111100101111110 step 176 111101111011110111100110111110 step 177 111101111011110111100111111110 step 178 111101111011110111101000111110 step 179 111101111011110111101001111110 step 180 111101111011110111101010111110 step 181 111101111011110111101011111110 step 182 111101111011110111101100111110 step 183 111101111011110111101101111110 step 184 111101111011110111101110111110 step 185 111101111011110111101111011110 step 186 111101111011110111101111000001 step 187 111101111011110111101111000011 step 188 111101111011110111101111000101 step 189 111101111011110111101111000111 step 190 111101111011110111101111001001 step 191 111101111011110111101111001011 step 192 111101111011110111101111001101 step 193 111101111011110111101111001111 step 194 111101111011110111101111010001 step 195 111101111011110111101111010011 step 196 111101111011110111101111010101 step 197 111101111011110111101111010111 step 198 111101111011110111101111011001 step 199 111101111011110111101111011011 step 200 111101111011110111101111011101 step 201 111101111011110111101111011110 step 202 111101111011110111101111011110 test 29: *** FAIL *************************** 6 steps failed SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFHJKLMNPRSDEFHJKLMNPRSTUV SIDE 111111111111111222222222222222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO this fail O all fails O was hi 111111111111111111111111111111 rising ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ falling vvvvvvvvvvvvvvvvvvvvvvvvvvvvvv was lo 000000000000000000000000000000 total fails 29, total passes 0 step 1 000010000100001000010000100001 step 2 000010000100001000010000100001 step 3 000110000100001000010000100001 step 4 001010000100001000010000100001 SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFHJKLMNPRSDEFHJKLMNPRSTUV SIDE 111111111111111222222222222222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 10 step 5 001100000100001000010000100001 fail ^ step 6 010010000100001000010000100001 step 7 010110000100001000010000100001 step 8 011010000100001000010000100001 SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFHJKLMNPRSDEFHJKLMNPRSTUV SIDE 111111111111111222222222222222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 10 step 9 011100000100001000010000100001 fail ^ step 10 100010000100001000010000100001 step 11 100110000100001000010000100001 step 12 101010000100001000010000100001 SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFHJKLMNPRSDEFHJKLMNPRSTUV SIDE 111111111111111222222222222222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 10 step 13 101100000100001000010000100001 fail ^ step 14 110010000100001000010000100001 step 15 110110000100001000010000100001 step 16 111010000100001000010000100001 step 17 111100000100001000010000100001 step 18 000010000100001000010000100001 step 19 000010000100001000010000100001 step 20 000010001100001000010000100001 step 21 000010010100001000010000100001 step 22 000010011100001000010000100001 step 23 000010100100001000010000100001 step 24 000010101100001000010000100001 step 25 000010110100001000010000100001 step 26 000010111100001000010000100001 step 27 000011000100001000010000100001 step 28 000011001100001000010000100001 step 29 000011010100001000010000100001 step 30 000011011100001000010000100001 step 31 000011100100001000010000100001 step 32 000011101100001000010000100001 step 33 000011110100001000010000100001 step 34 000011111000001000010000100001 step 35 000010000100001000010000100001 step 36 000010000100001000010000100001 step 37 000010000100011000010000100001 step 38 000010000100101000010000100001 step 39 000010000100111000010000100001 step 40 000010000101001000010000100001 step 41 000010000101011000010000100001 step 42 000010000101101000010000100001 step 43 000010000101111000010000100001 step 44 000010000110001000010000100001 step 45 000010000110011000010000100001 step 46 000010000110101000010000100001 step 47 000010000110111000010000100001 step 48 000010000111001000010000100001 step 49 000010000111011000010000100001 step 50 000010000111101000010000100001 step 51 000010000111110000010000100001 step 52 000010000100001000010000100001 step 53 000010000100001000010000100001 step 54 000010000100001000110000100001 step 55 000010000100001001010000100001 step 56 000010000100001001110000100001 step 57 000010000100001010010000100001 step 58 000010000100001010110000100001 step 59 000010000100001011010000100001 step 60 000010000100001011110000100001 step 61 000010000100001100010000100001 step 62 000010000100001100110000100001 step 63 000010000100001101010000100001 step 64 000010000100001101110000100001 step 65 000010000100001110010000100001 step 66 000010000100001110110000100001 step 67 000010000100001111010000100001 step 68 000010000100001111100000100001 step 69 000010000100001000010000100001 step 70 000010000100001000010000100001 step 71 000010000100001000010001100001 step 72 000010000100001000010010100001 step 73 000010000100001000010011100001 step 74 000010000100001000010100100001 step 75 000010000100001000010101100001 step 76 000010000100001000010110100001 step 77 000010000100001000010111100001 step 78 000010000100001000011000100001 step 79 000010000100001000011001100001 step 80 000010000100001000011010100001 step 81 000010000100001000011011100001 step 82 000010000100001000011100100001 step 83 000010000100001000011101100001 step 84 000010000100001000011110100001 step 85 000010000100001000011111000001 step 86 000010000100001000010000100001 step 87 000010000100001000010000100001 step 88 000010000100001000010000100011 step 89 000010000100001000010000100101 step 90 000010000100001000010000100111 step 91 000010000100001000010000101001 step 92 000010000100001000010000101011 step 93 000010000100001000010000101101 step 94 000010000100001000010000101111 step 95 000010000100001000010000110001 step 96 000010000100001000010000110011 step 97 000010000100001000010000110101 step 98 000010000100001000010000110111 step 99 000010000100001000010000111001 step 100 000010000100001000010000111011 step 101 000010000100001000010000111101 step 102 000010000100001000010000111110 step 103 000010000100001000010000100001 step 104 000010000100001000010000100001 step 105 111101111011110111101111011110 step 106 000011111011110111101111011110 step 107 000111111011110111101111011110 step 108 001011111011110111101111011110 SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFHJKLMNPRSDEFHJKLMNPRSTUV SIDE 111111111111111222222222222222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 10 step 109 001101111011110111101111011110 fail ^ step 110 010011111011110111101111011110 step 111 010111111011110111101111011110 step 112 011011111011110111101111011110 SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFHJKLMNPRSDEFHJKLMNPRSTUV SIDE 111111111111111222222222222222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 10 step 113 011101111011110111101111011110 fail ^ step 114 100011111011110111101111011110 step 115 100111111011110111101111011110 step 116 101011111011110111101111011110 SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFHJKLMNPRSDEFHJKLMNPRSTUV SIDE 111111111111111222222222222222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 10 step 117 101101111011110111101111011110 fail ^ step 118 110011111011110111101111011110 step 119 110111111011110111101111011110 step 120 111011111011110111101111011110 step 121 111101111011110111101111011110 step 122 111100000111110111101111011110 step 123 111100001111110111101111011110 step 124 111100010111110111101111011110 step 125 111100011111110111101111011110 step 126 111100100111110111101111011110 step 127 111100101111110111101111011110 step 128 111100110111110111101111011110 step 129 111100111111110111101111011110 step 130 111101000111110111101111011110 step 131 111101001111110111101111011110 step 132 111101010111110111101111011110 step 133 111101011111110111101111011110 step 134 111101100111110111101111011110 step 135 111101101111110111101111011110 step 136 111101110111110111101111011110 step 137 111101111011110111101111011110 step 138 111101111000001111101111011110 step 139 111101111000011111101111011110 step 140 111101111000101111101111011110 step 141 111101111000111111101111011110 step 142 111101111001001111101111011110 step 143 111101111001011111101111011110 step 144 111101111001101111101111011110 step 145 111101111001111111101111011110 step 146 111101111010001111101111011110 step 147 111101111010011111101111011110 step 148 111101111010101111101111011110 step 149 111101111010111111101111011110 step 150 111101111011001111101111011110 step 151 111101111011011111101111011110 step 152 111101111011101111101111011110 step 153 111101111011110111101111011110 step 154 111101111011110000011111011110 step 155 111101111011110000111111011110 step 156 111101111011110001011111011110 step 157 111101111011110001111111011110 step 158 111101111011110010011111011110 step 159 111101111011110010111111011110 step 160 111101111011110011011111011110 step 161 111101111011110011111111011110 step 162 111101111011110100011111011110 step 163 111101111011110100111111011110 step 164 111101111011110101011111011110 step 165 111101111011110101111111011110 step 166 111101111011110110011111011110 step 167 111101111011110110111111011110 step 168 111101111011110111011111011110 step 169 111101111011110111101111011110 step 170 111101111011110111100000111110 step 171 111101111011110111100001111110 step 172 111101111011110111100010111110 step 173 111101111011110111100011111110 step 174 111101111011110111100100111110 step 175 111101111011110111100101111110 step 176 111101111011110111100110111110 step 177 111101111011110111100111111110 step 178 111101111011110111101000111110 step 179 111101111011110111101001111110 step 180 111101111011110111101010111110 step 181 111101111011110111101011111110 step 182 111101111011110111101100111110 step 183 111101111011110111101101111110 step 184 111101111011110111101110111110 step 185 111101111011110111101111011110 step 186 111101111011110111101111000001 step 187 111101111011110111101111000011 step 188 111101111011110111101111000101 step 189 111101111011110111101111000111 step 190 111101111011110111101111001001 step 191 111101111011110111101111001011 step 192 111101111011110111101111001101 step 193 111101111011110111101111001111 step 194 111101111011110111101111010001 step 195 111101111011110111101111010011 step 196 111101111011110111101111010101 step 197 111101111011110111101111010111 step 198 111101111011110111101111011001 step 199 111101111011110111101111011011 step 200 111101111011110111101111011101 step 201 111101111011110111101111011110 step 202 111101111011110111101111011110 test 30: *** FAIL *************************** 6 steps failed SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFHJKLMNPRSDEFHJKLMNPRSTUV SIDE 111111111111111222222222222222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO this fail O all fails O was hi 111111111111111111111111111111 rising ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ falling vvvvvvvvvvvvvvvvvvvvvvvvvvvvvv was lo 000000000000000000000000000000 total fails 30, total passes 0 step 1 000010000100001000010000100001 step 2 000010000100001000010000100001 step 3 000110000100001000010000100001 step 4 001010000100001000010000100001 SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFHJKLMNPRSDEFHJKLMNPRSTUV SIDE 111111111111111222222222222222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 10 step 5 001100000100001000010000100001 fail ^ step 6 010010000100001000010000100001 step 7 010110000100001000010000100001 step 8 011010000100001000010000100001 SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFHJKLMNPRSDEFHJKLMNPRSTUV SIDE 111111111111111222222222222222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 10 step 9 011100000100001000010000100001 fail ^ step 10 100010000100001000010000100001 step 11 100110000100001000010000100001 step 12 101010000100001000010000100001 SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFHJKLMNPRSDEFHJKLMNPRSTUV SIDE 111111111111111222222222222222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 10 step 13 101100000100001000010000100001 fail ^ step 14 110010000100001000010000100001 step 15 110110000100001000010000100001 step 16 111010000100001000010000100001 step 17 111100000100001000010000100001 step 18 000010000100001000010000100001 step 19 000010000100001000010000100001 step 20 000010001100001000010000100001 step 21 000010010100001000010000100001 step 22 000010011100001000010000100001 step 23 000010100100001000010000100001 step 24 000010101100001000010000100001 step 25 000010110100001000010000100001 step 26 000010111100001000010000100001 step 27 000011000100001000010000100001 step 28 000011001100001000010000100001 step 29 000011010100001000010000100001 step 30 000011011100001000010000100001 step 31 000011100100001000010000100001 step 32 000011101100001000010000100001 step 33 000011110100001000010000100001 step 34 000011111000001000010000100001 step 35 000010000100001000010000100001 step 36 000010000100001000010000100001 step 37 000010000100011000010000100001 step 38 000010000100101000010000100001 step 39 000010000100111000010000100001 step 40 000010000101001000010000100001 step 41 000010000101011000010000100001 step 42 000010000101101000010000100001 step 43 000010000101111000010000100001 step 44 000010000110001000010000100001 step 45 000010000110011000010000100001 step 46 000010000110101000010000100001 step 47 000010000110111000010000100001 step 48 000010000111001000010000100001 step 49 000010000111011000010000100001 step 50 000010000111101000010000100001 step 51 000010000111110000010000100001 step 52 000010000100001000010000100001 step 53 000010000100001000010000100001 step 54 000010000100001000110000100001 step 55 000010000100001001010000100001 step 56 000010000100001001110000100001 step 57 000010000100001010010000100001 step 58 000010000100001010110000100001 step 59 000010000100001011010000100001 step 60 000010000100001011110000100001 step 61 000010000100001100010000100001 step 62 000010000100001100110000100001 step 63 000010000100001101010000100001 step 64 000010000100001101110000100001 step 65 000010000100001110010000100001 step 66 000010000100001110110000100001 step 67 000010000100001111010000100001 step 68 000010000100001111100000100001 step 69 000010000100001000010000100001 step 70 000010000100001000010000100001 step 71 000010000100001000010001100001 step 72 000010000100001000010010100001 step 73 000010000100001000010011100001 step 74 000010000100001000010100100001 step 75 000010000100001000010101100001 step 76 000010000100001000010110100001 step 77 000010000100001000010111100001 step 78 000010000100001000011000100001 step 79 000010000100001000011001100001 step 80 000010000100001000011010100001 step 81 000010000100001000011011100001 step 82 000010000100001000011100100001 step 83 000010000100001000011101100001 step 84 000010000100001000011110100001 step 85 000010000100001000011111000001 step 86 000010000100001000010000100001 step 87 000010000100001000010000100001 step 88 000010000100001000010000100011 step 89 000010000100001000010000100101 step 90 000010000100001000010000100111 step 91 000010000100001000010000101001 step 92 000010000100001000010000101011 step 93 000010000100001000010000101101 step 94 000010000100001000010000101111 step 95 000010000100001000010000110001 step 96 000010000100001000010000110011 step 97 000010000100001000010000110101 step 98 000010000100001000010000110111 step 99 000010000100001000010000111001 step 100 000010000100001000010000111011 step 101 000010000100001000010000111101 step 102 000010000100001000010000111110 step 103 000010000100001000010000100001 step 104 000010000100001000010000100001 step 105 111101111011110111101111011110 step 106 000011111011110111101111011110 step 107 000111111011110111101111011110 step 108 001011111011110111101111011110 SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFHJKLMNPRSDEFHJKLMNPRSTUV SIDE 111111111111111222222222222222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 10 step 109 001101111011110111101111011110 fail ^ step 110 010011111011110111101111011110 step 111 010111111011110111101111011110 step 112 011011111011110111101111011110 SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFHJKLMNPRSDEFHJKLMNPRSTUV SIDE 111111111111111222222222222222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 10 step 113 011101111011110111101111011110 fail ^ step 114 100011111011110111101111011110 step 115 100111111011110111101111011110 step 116 101011111011110111101111011110 SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFHJKLMNPRSDEFHJKLMNPRSTUV SIDE 111111111111111222222222222222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 10 step 117 101101111011110111101111011110 fail ^ step 118 110011111011110111101111011110 step 119 110111111011110111101111011110 step 120 111011111011110111101111011110 step 121 111101111011110111101111011110 step 122 111100000111110111101111011110 step 123 111100001111110111101111011110 step 124 111100010111110111101111011110 step 125 111100011111110111101111011110 step 126 111100100111110111101111011110 step 127 111100101111110111101111011110 step 128 111100110111110111101111011110 step 129 111100111111110111101111011110 step 130 111101000111110111101111011110 step 131 111101001111110111101111011110 step 132 111101010111110111101111011110 step 133 111101011111110111101111011110 step 134 111101100111110111101111011110 step 135 111101101111110111101111011110 step 136 111101110111110111101111011110 step 137 111101111011110111101111011110 step 138 111101111000001111101111011110 step 139 111101111000011111101111011110 step 140 111101111000101111101111011110 step 141 111101111000111111101111011110 step 142 111101111001001111101111011110 step 143 111101111001011111101111011110 step 144 111101111001101111101111011110 step 145 111101111001111111101111011110 step 146 111101111010001111101111011110 step 147 111101111010011111101111011110 step 148 111101111010101111101111011110 step 149 111101111010111111101111011110 step 150 111101111011001111101111011110 step 151 111101111011011111101111011110 step 152 111101111011101111101111011110 step 153 111101111011110111101111011110 step 154 111101111011110000011111011110 step 155 111101111011110000111111011110 step 156 111101111011110001011111011110 step 157 111101111011110001111111011110 step 158 111101111011110010011111011110 step 159 111101111011110010111111011110 step 160 111101111011110011011111011110 step 161 111101111011110011111111011110 step 162 111101111011110100011111011110 step 163 111101111011110100111111011110 step 164 111101111011110101011111011110 step 165 111101111011110101111111011110 step 166 111101111011110110011111011110 step 167 111101111011110110111111011110 step 168 111101111011110111011111011110 step 169 111101111011110111101111011110 step 170 111101111011110111100000111110 step 171 111101111011110111100001111110 step 172 111101111011110111100010111110 step 173 111101111011110111100011111110 step 174 111101111011110111100100111110 step 175 111101111011110111100101111110 step 176 111101111011110111100110111110 step 177 111101111011110111100111111110 step 178 111101111011110111101000111110 step 179 111101111011110111101001111110 step 180 111101111011110111101010111110 step 181 111101111011110111101011111110 step 182 111101111011110111101100111110 step 183 111101111011110111101101111110 step 184 111101111011110111101110111110 step 185 111101111011110111101111011110 step 186 111101111011110111101111000001 step 187 111101111011110111101111000011 step 188 111101111011110111101111000101 step 189 111101111011110111101111000111 step 190 111101111011110111101111001001 step 191 111101111011110111101111001011 step 192 111101111011110111101111001101 step 193 111101111011110111101111001111 step 194 111101111011110111101111010001 step 195 111101111011110111101111010011 step 196 111101111011110111101111010101 step 197 111101111011110111101111010111 step 198 111101111011110111101111011001 step 199 111101111011110111101111011011 step 200 111101111011110111101111011101 step 201 111101111011110111101111011110 step 202 111101111011110111101111011110 test 31: *** FAIL *************************** 6 steps failed SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFHJKLMNPRSDEFHJKLMNPRSTUV SIDE 111111111111111222222222222222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO this fail O all fails O was hi 111111111111111111111111111111 rising ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ falling vvvvvvvvvvvvvvvvvvvvvvvvvvvvvv was lo 000000000000000000000000000000 total fails 31, total passes 0 step 1 000010000100001000010000100001 step 2 000010000100001000010000100001 step 3 000110000100001000010000100001 step 4 001010000100001000010000100001 SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFHJKLMNPRSDEFHJKLMNPRSTUV SIDE 111111111111111222222222222222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 10 step 5 001100000100001000010000100001 fail ^ step 6 010010000100001000010000100001 step 7 010110000100001000010000100001 step 8 011010000100001000010000100001 SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFHJKLMNPRSDEFHJKLMNPRSTUV SIDE 111111111111111222222222222222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 10 step 9 011100000100001000010000100001 fail ^ step 10 100010000100001000010000100001 step 11 100110000100001000010000100001 step 12 101010000100001000010000100001 SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFHJKLMNPRSDEFHJKLMNPRSTUV SIDE 111111111111111222222222222222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 10 step 13 101100000100001000010000100001 fail ^ step 14 110010000100001000010000100001 step 15 110110000100001000010000100001 step 16 111010000100001000010000100001 step 17 111100000100001000010000100001 step 18 000010000100001000010000100001 step 19 000010000100001000010000100001 step 20 000010001100001000010000100001 step 21 000010010100001000010000100001 step 22 000010011100001000010000100001 step 23 000010100100001000010000100001 step 24 000010101100001000010000100001 step 25 000010110100001000010000100001 step 26 000010111100001000010000100001 step 27 000011000100001000010000100001 step 28 000011001100001000010000100001 step 29 000011010100001000010000100001 step 30 000011011100001000010000100001 step 31 000011100100001000010000100001 step 32 000011101100001000010000100001 step 33 000011110100001000010000100001 step 34 000011111000001000010000100001 step 35 000010000100001000010000100001 step 36 000010000100001000010000100001 step 37 000010000100011000010000100001 step 38 000010000100101000010000100001 step 39 000010000100111000010000100001 step 40 000010000101001000010000100001 step 41 000010000101011000010000100001 step 42 000010000101101000010000100001 step 43 000010000101111000010000100001 step 44 000010000110001000010000100001 step 45 000010000110011000010000100001 step 46 000010000110101000010000100001 step 47 000010000110111000010000100001 step 48 000010000111001000010000100001 step 49 000010000111011000010000100001 step 50 000010000111101000010000100001 step 51 000010000111110000010000100001 step 52 000010000100001000010000100001 step 53 000010000100001000010000100001 step 54 000010000100001000110000100001 step 55 000010000100001001010000100001 step 56 000010000100001001110000100001 step 57 000010000100001010010000100001 step 58 000010000100001010110000100001 step 59 000010000100001011010000100001 step 60 000010000100001011110000100001 step 61 000010000100001100010000100001 step 62 000010000100001100110000100001 step 63 000010000100001101010000100001 step 64 000010000100001101110000100001 step 65 000010000100001110010000100001 step 66 000010000100001110110000100001 step 67 000010000100001111010000100001 step 68 000010000100001111100000100001 step 69 000010000100001000010000100001 step 70 000010000100001000010000100001 step 71 000010000100001000010001100001 step 72 000010000100001000010010100001 step 73 000010000100001000010011100001 step 74 000010000100001000010100100001 step 75 000010000100001000010101100001 step 76 000010000100001000010110100001 step 77 000010000100001000010111100001 step 78 000010000100001000011000100001 step 79 000010000100001000011001100001 step 80 000010000100001000011010100001 step 81 000010000100001000011011100001 step 82 000010000100001000011100100001 step 83 000010000100001000011101100001 step 84 000010000100001000011110100001 step 85 000010000100001000011111000001 step 86 000010000100001000010000100001 step 87 000010000100001000010000100001 step 88 000010000100001000010000100011 step 89 000010000100001000010000100101 step 90 000010000100001000010000100111 step 91 000010000100001000010000101001 step 92 000010000100001000010000101011 step 93 000010000100001000010000101101 step 94 000010000100001000010000101111 step 95 000010000100001000010000110001 step 96 000010000100001000010000110011 step 97 000010000100001000010000110101 step 98 000010000100001000010000110111 step 99 000010000100001000010000111001 step 100 000010000100001000010000111011 step 101 000010000100001000010000111101 step 102 000010000100001000010000111110 step 103 000010000100001000010000100001 step 104 000010000100001000010000100001 step 105 111101111011110111101111011110 step 106 000011111011110111101111011110 step 107 000111111011110111101111011110 step 108 001011111011110111101111011110 SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFHJKLMNPRSDEFHJKLMNPRSTUV SIDE 111111111111111222222222222222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 10 step 109 001101111011110111101111011110 fail ^ step 110 010011111011110111101111011110 step 111 010111111011110111101111011110 step 112 011011111011110111101111011110 SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFHJKLMNPRSDEFHJKLMNPRSTUV SIDE 111111111111111222222222222222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 10 step 113 011101111011110111101111011110 fail ^ step 114 100011111011110111101111011110 step 115 100111111011110111101111011110 step 116 101011111011110111101111011110 SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFHJKLMNPRSDEFHJKLMNPRSTUV SIDE 111111111111111222222222222222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 10 step 117 101101111011110111101111011110 fail ^ step 118 110011111011110111101111011110 step 119 110111111011110111101111011110 step 120 111011111011110111101111011110 step 121 111101111011110111101111011110 step 122 111100000111110111101111011110 step 123 111100001111110111101111011110 step 124 111100010111110111101111011110 step 125 111100011111110111101111011110 step 126 111100100111110111101111011110 step 127 111100101111110111101111011110 step 128 111100110111110111101111011110 step 129 111100111111110111101111011110 step 130 111101000111110111101111011110 step 131 111101001111110111101111011110 step 132 111101010111110111101111011110 step 133 111101011111110111101111011110 step 134 111101100111110111101111011110 step 135 111101101111110111101111011110 step 136 111101110111110111101111011110 step 137 111101111011110111101111011110 step 138 111101111000001111101111011110 step 139 111101111000011111101111011110 step 140 111101111000101111101111011110 step 141 111101111000111111101111011110 step 142 111101111001001111101111011110 step 143 111101111001011111101111011110 step 144 111101111001101111101111011110 step 145 111101111001111111101111011110 step 146 111101111010001111101111011110 step 147 111101111010011111101111011110 step 148 111101111010101111101111011110 step 149 111101111010111111101111011110 step 150 111101111011001111101111011110 step 151 111101111011011111101111011110 step 152 111101111011101111101111011110 step 153 111101111011110111101111011110 step 154 111101111011110000011111011110 step 155 111101111011110000111111011110 step 156 111101111011110001011111011110 step 157 111101111011110001111111011110 step 158 111101111011110010011111011110 step 159 111101111011110010111111011110 step 160 111101111011110011011111011110 step 161 111101111011110011111111011110 step 162 111101111011110100011111011110 step 163 111101111011110100111111011110 step 164 111101111011110101011111011110 step 165 111101111011110101111111011110 step 166 111101111011110110011111011110 step 167 111101111011110110111111011110 step 168 111101111011110111011111011110 step 169 111101111011110111101111011110 step 170 111101111011110111100000111110 step 171 111101111011110111100001111110 step 172 111101111011110111100010111110 step 173 111101111011110111100011111110 step 174 111101111011110111100100111110 step 175 111101111011110111100101111110 step 176 111101111011110111100110111110 step 177 111101111011110111100111111110 step 178 111101111011110111101000111110 step 179 111101111011110111101001111110 step 180 111101111011110111101010111110 step 181 111101111011110111101011111110 step 182 111101111011110111101100111110 step 183 111101111011110111101101111110 step 184 111101111011110111101110111110 step 185 111101111011110111101111011110 step 186 111101111011110111101111000001 step 187 111101111011110111101111000011 step 188 111101111011110111101111000101 step 189 111101111011110111101111000111 step 190 111101111011110111101111001001 step 191 111101111011110111101111001011 step 192 111101111011110111101111001101 step 193 111101111011110111101111001111 step 194 111101111011110111101111010001 step 195 111101111011110111101111010011 step 196 111101111011110111101111010101 step 197 111101111011110111101111010111 step 198 111101111011110111101111011001 step 199 111101111011110111101111011011 step 200 111101111011110111101111011101 step 201 111101111011110111101111011110 step 202 111101111011110111101111011110 test 32: *** FAIL *************************** 6 steps failed SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFHJKLMNPRSDEFHJKLMNPRSTUV SIDE 111111111111111222222222222222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO this fail O all fails O was hi 111111111111111111111111111111 rising ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ falling vvvvvvvvvvvvvvvvvvvvvvvvvvvvvv was lo 000000000000000000000000000000 total fails 32, total passes 0 step 1 000010000100001000010000100001 step 2 000010000100001000010000100001 step 3 000110000100001000010000100001 step 4 001010000100001000010000100001 SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFHJKLMNPRSDEFHJKLMNPRSTUV SIDE 111111111111111222222222222222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 10 step 5 001100000100001000010000100001 fail ^ step 6 010010000100001000010000100001 step 7 010110000100001000010000100001 step 8 011010000100001000010000100001 SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFHJKLMNPRSDEFHJKLMNPRSTUV SIDE 111111111111111222222222222222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 10 step 9 011100000100001000010000100001 fail ^ step 10 100010000100001000010000100001 step 11 100110000100001000010000100001 step 12 101010000100001000010000100001 SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFHJKLMNPRSDEFHJKLMNPRSTUV SIDE 111111111111111222222222222222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 10 step 13 101100000100001000010000100001 fail ^ step 14 110010000100001000010000100001 step 15 110110000100001000010000100001 step 16 111010000100001000010000100001 step 17 111100000100001000010000100001 step 18 000010000100001000010000100001 step 19 000010000100001000010000100001 step 20 000010001100001000010000100001 step 21 000010010100001000010000100001 step 22 000010011100001000010000100001 step 23 000010100100001000010000100001 step 24 000010101100001000010000100001 step 25 000010110100001000010000100001 step 26 000010111100001000010000100001 step 27 000011000100001000010000100001 step 28 000011001100001000010000100001 step 29 000011010100001000010000100001 step 30 000011011100001000010000100001 step 31 000011100100001000010000100001 step 32 000011101100001000010000100001 step 33 000011110100001000010000100001 step 34 000011111000001000010000100001 step 35 000010000100001000010000100001 step 36 000010000100001000010000100001 step 37 000010000100011000010000100001 step 38 000010000100101000010000100001 step 39 000010000100111000010000100001 step 40 000010000101001000010000100001 step 41 000010000101011000010000100001 step 42 000010000101101000010000100001 step 43 000010000101111000010000100001 step 44 000010000110001000010000100001 step 45 000010000110011000010000100001 step 46 000010000110101000010000100001 step 47 000010000110111000010000100001 step 48 000010000111001000010000100001 step 49 000010000111011000010000100001 step 50 000010000111101000010000100001 step 51 000010000111110000010000100001 step 52 000010000100001000010000100001 step 53 000010000100001000010000100001 step 54 000010000100001000110000100001 step 55 000010000100001001010000100001 step 56 000010000100001001110000100001 step 57 000010000100001010010000100001 step 58 000010000100001010110000100001 step 59 000010000100001011010000100001 step 60 000010000100001011110000100001 step 61 000010000100001100010000100001 step 62 000010000100001100110000100001 step 63 000010000100001101010000100001 step 64 000010000100001101110000100001 step 65 000010000100001110010000100001 step 66 000010000100001110110000100001 step 67 000010000100001111010000100001 step 68 000010000100001111100000100001 step 69 000010000100001000010000100001 step 70 000010000100001000010000100001 step 71 000010000100001000010001100001 step 72 000010000100001000010010100001 step 73 000010000100001000010011100001 step 74 000010000100001000010100100001 step 75 000010000100001000010101100001 step 76 000010000100001000010110100001 step 77 000010000100001000010111100001 step 78 000010000100001000011000100001 step 79 000010000100001000011001100001 step 80 000010000100001000011010100001 step 81 000010000100001000011011100001 step 82 000010000100001000011100100001 step 83 000010000100001000011101100001 step 84 000010000100001000011110100001 step 85 000010000100001000011111000001 step 86 000010000100001000010000100001 step 87 000010000100001000010000100001 step 88 000010000100001000010000100011 step 89 000010000100001000010000100101 step 90 000010000100001000010000100111 step 91 000010000100001000010000101001 step 92 000010000100001000010000101011 step 93 000010000100001000010000101101 step 94 000010000100001000010000101111 step 95 000010000100001000010000110001 step 96 000010000100001000010000110011 step 97 000010000100001000010000110101 step 98 000010000100001000010000110111 step 99 000010000100001000010000111001 step 100 000010000100001000010000111011 step 101 000010000100001000010000111101 step 102 000010000100001000010000111110 step 103 000010000100001000010000100001 step 104 000010000100001000010000100001 step 105 111101111011110111101111011110 step 106 000011111011110111101111011110 step 107 000111111011110111101111011110 step 108 001011111011110111101111011110 SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFHJKLMNPRSDEFHJKLMNPRSTUV SIDE 111111111111111222222222222222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 10 step 109 001101111011110111101111011110 fail ^ step 110 010011111011110111101111011110 step 111 010111111011110111101111011110 step 112 011011111011110111101111011110 SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFHJKLMNPRSDEFHJKLMNPRSTUV SIDE 111111111111111222222222222222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 10 step 113 011101111011110111101111011110 fail ^ step 114 100011111011110111101111011110 step 115 100111111011110111101111011110 step 116 101011111011110111101111011110 SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFHJKLMNPRSDEFHJKLMNPRSTUV SIDE 111111111111111222222222222222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 10 step 117 101101111011110111101111011110 fail ^ step 118 110011111011110111101111011110 step 119 110111111011110111101111011110 step 120 111011111011110111101111011110 step 121 111101111011110111101111011110 step 122 111100000111110111101111011110 step 123 111100001111110111101111011110 step 124 111100010111110111101111011110 step 125 111100011111110111101111011110 step 126 111100100111110111101111011110 step 127 111100101111110111101111011110 step 128 111100110111110111101111011110 step 129 111100111111110111101111011110 step 130 111101000111110111101111011110 step 131 111101001111110111101111011110 step 132 111101010111110111101111011110 step 133 111101011111110111101111011110 step 134 111101100111110111101111011110 step 135 111101101111110111101111011110 step 136 111101110111110111101111011110 step 137 111101111011110111101111011110 step 138 111101111000001111101111011110 step 139 111101111000011111101111011110 step 140 111101111000101111101111011110 step 141 111101111000111111101111011110 step 142 111101111001001111101111011110 step 143 111101111001011111101111011110 step 144 111101111001101111101111011110 step 145 111101111001111111101111011110 step 146 111101111010001111101111011110 step 147 111101111010011111101111011110 step 148 111101111010101111101111011110 step 149 111101111010111111101111011110 step 150 111101111011001111101111011110 step 151 111101111011011111101111011110 step 152 111101111011101111101111011110 step 153 111101111011110111101111011110 step 154 111101111011110000011111011110 step 155 111101111011110000111111011110 step 156 111101111011110001011111011110 step 157 111101111011110001111111011110 step 158 111101111011110010011111011110 step 159 111101111011110010111111011110 step 160 111101111011110011011111011110 step 161 111101111011110011111111011110 step 162 111101111011110100011111011110 step 163 111101111011110100111111011110 step 164 111101111011110101011111011110 step 165 111101111011110101111111011110 step 166 111101111011110110011111011110 step 167 111101111011110110111111011110 step 168 111101111011110111011111011110 step 169 111101111011110111101111011110 step 170 111101111011110111100000111110 step 171 111101111011110111100001111110 step 172 111101111011110111100010111110 step 173 111101111011110111100011111110 step 174 111101111011110111100100111110 step 175 111101111011110111100101111110 step 176 111101111011110111100110111110 step 177 111101111011110111100111111110 step 178 111101111011110111101000111110 step 179 111101111011110111101001111110 step 180 111101111011110111101010111110 step 181 111101111011110111101011111110 step 182 111101111011110111101100111110 step 183 111101111011110111101101111110 step 184 111101111011110111101110111110 step 185 111101111011110111101111011110 step 186 111101111011110111101111000001 step 187 111101111011110111101111000011 step 188 111101111011110111101111000101 step 189 111101111011110111101111000111 step 190 111101111011110111101111001001 step 191 111101111011110111101111001011 step 192 111101111011110111101111001101 step 193 111101111011110111101111001111 step 194 111101111011110111101111010001 step 195 111101111011110111101111010011 step 196 111101111011110111101111010101 step 197 111101111011110111101111010111 step 198 111101111011110111101111011001 step 199 111101111011110111101111011011 step 200 111101111011110111101111011101 step 201 111101111011110111101111011110 step 202 111101111011110111101111011110 test 33: *** FAIL *************************** 6 steps failed SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFHJKLMNPRSDEFHJKLMNPRSTUV SIDE 111111111111111222222222222222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO this fail O all fails O was hi 111111111111111111111111111111 rising ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ falling vvvvvvvvvvvvvvvvvvvvvvvvvvvvvv was lo 000000000000000000000000000000 total fails 33, total passes 0 step 1 000010000100001000010000100001 step 2 000010000100001000010000100001 step 3 000110000100001000010000100001 step 4 001010000100001000010000100001 SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFHJKLMNPRSDEFHJKLMNPRSTUV SIDE 111111111111111222222222222222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 10 step 5 001100000100001000010000100001 fail ^ step 6 010010000100001000010000100001 step 7 010110000100001000010000100001 step 8 011010000100001000010000100001 SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFHJKLMNPRSDEFHJKLMNPRSTUV SIDE 111111111111111222222222222222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 10 step 9 011100000100001000010000100001 fail ^ step 10 100010000100001000010000100001 step 11 100110000100001000010000100001 step 12 101010000100001000010000100001 SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFHJKLMNPRSDEFHJKLMNPRSTUV SIDE 111111111111111222222222222222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 10 step 13 101100000100001000010000100001 fail ^ step 14 110010000100001000010000100001 step 15 110110000100001000010000100001 step 16 111010000100001000010000100001 step 17 111100000100001000010000100001 step 18 000010000100001000010000100001 step 19 000010000100001000010000100001 step 20 000010001100001000010000100001 step 21 000010010100001000010000100001 step 22 000010011100001000010000100001 step 23 000010100100001000010000100001 step 24 000010101100001000010000100001 step 25 000010110100001000010000100001 step 26 000010111100001000010000100001 step 27 000011000100001000010000100001 step 28 000011001100001000010000100001 step 29 000011010100001000010000100001 step 30 000011011100001000010000100001 step 31 000011100100001000010000100001 step 32 000011101100001000010000100001 step 33 000011110100001000010000100001 step 34 000011111000001000010000100001 step 35 000010000100001000010000100001 step 36 000010000100001000010000100001 step 37 000010000100011000010000100001 step 38 000010000100101000010000100001 step 39 000010000100111000010000100001 step 40 000010000101001000010000100001 step 41 000010000101011000010000100001 step 42 000010000101101000010000100001 step 43 000010000101111000010000100001 step 44 000010000110001000010000100001 step 45 000010000110011000010000100001 step 46 000010000110101000010000100001 step 47 000010000110111000010000100001 step 48 000010000111001000010000100001 step 49 000010000111011000010000100001 step 50 000010000111101000010000100001 step 51 000010000111110000010000100001 step 52 000010000100001000010000100001 step 53 000010000100001000010000100001 step 54 000010000100001000110000100001 step 55 000010000100001001010000100001 step 56 000010000100001001110000100001 step 57 000010000100001010010000100001 step 58 000010000100001010110000100001 step 59 000010000100001011010000100001 step 60 000010000100001011110000100001 step 61 000010000100001100010000100001 step 62 000010000100001100110000100001 step 63 000010000100001101010000100001 step 64 000010000100001101110000100001 step 65 000010000100001110010000100001 step 66 000010000100001110110000100001 step 67 000010000100001111010000100001 space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C toggle comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit step 68 000010000100001111100000100001 step 69 000010000100001000010000100001 step 70 000010000100001000010000100001 step 71 000010000100001000010001100001 step 72 000010000100001000010010100001 step 73 000010000100001000010011100001 step 74 000010000100001000010100100001 step 75 000010000100001000010101100001 step 76 000010000100001000010110100001 step 77 000010000100001000010111100001 step 78 000010000100001000011000100001 step 79 000010000100001000011001100001 step 80 000010000100001000011010100001 step 81 000010000100001000011011100001 step 82 000010000100001000011100100001 step 83 000010000100001000011101100001 step 84 000010000100001000011110100001 step 85 000010000100001000011111000001 step 86 000010000100001000010000100001 step 87 000010000100001000010000100001 step 88 000010000100001000010000100011 step 89 000010000100001000010000100101 step 90 000010000100001000010000100111 step 91 000010000100001000010000101001 step 92 000010000100001000010000101011 step 93 000010000100001000010000101101 step 94 000010000100001000010000101111 step 95 000010000100001000010000110001 step 96 000010000100001000010000110011 step 97 000010000100001000010000110101 step 98 000010000100001000010000110111 step 99 000010000100001000010000111001 step 100 000010000100001000010000111011 step 101 000010000100001000010000111101 step 102 000010000100001000010000111110 step 103 000010000100001000010000100001 step 104 000010000100001000010000100001 step 105 111101111011110111101111011110 step 106 000011111011110111101111011110 step 107 000111111011110111101111011110 step 108 001011111011110111101111011110 SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFHJKLMNPRSDEFHJKLMNPRSTUV SIDE 111111111111111222222222222222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 10 step 109 001101111011110111101111011110 fail ^ space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C toggle comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit step 110 010011111011110111101111011110 step 111 010111111011110111101111011110 step 112 011011111011110111101111011110 SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFHJKLMNPRSDEFHJKLMNPRSTUV SIDE 111111111111111222222222222222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 10 step 113 011101111011110111101111011110 fail ^ space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C toggle comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit step 114 100011111011110111101111011110 step 115 100111111011110111101111011110 step 116 101011111011110111101111011110 SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFHJKLMNPRSDEFHJKLMNPRSTUV SIDE 111111111111111222222222222222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 10 step 117 101101111011110111101111011110 fail ^ space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C toggle comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit step 118 110011111011110111101111011110 step 119 110111111011110111101111011110 step 120 111011111011110111101111011110 step 121 111101111011110111101111011110 step 122 111100000111110111101111011110 step 123 111100001111110111101111011110 step 124 111100010111110111101111011110 step 125 111100011111110111101111011110 step 126 111100100111110111101111011110 step 127 111100101111110111101111011110 step 128 111100110111110111101111011110 step 129 111100111111110111101111011110 step 130 111101000111110111101111011110 step 131 111101001111110111101111011110 step 132 111101010111110111101111011110 step 133 111101011111110111101111011110 step 134 111101100111110111101111011110 step 135 111101101111110111101111011110 step 136 111101110111110111101111011110 step 137 111101111011110111101111011110 step 138 111101111000001111101111011110 step 139 111101111000011111101111011110 step 140 111101111000101111101111011110 step 141 111101111000111111101111011110 step 142 111101111001001111101111011110 step 143 111101111001011111101111011110 step 144 111101111001101111101111011110 step 145 111101111001111111101111011110 step 146 111101111010001111101111011110 step 147 111101111010011111101111011110 step 148 111101111010101111101111011110 step 149 111101111010111111101111011110 step 150 111101111011001111101111011110 step 151 111101111011011111101111011110 step 152 111101111011101111101111011110 step 153 111101111011110111101111011110 step 154 111101111011110000011111011110 step 155 111101111011110000111111011110 step 156 111101111011110001011111011110 step 157 111101111011110001111111011110 step 158 111101111011110010011111011110 step 159 111101111011110010111111011110 step 160 111101111011110011011111011110 step 161 111101111011110011111111011110 step 162 111101111011110100011111011110 step 163 111101111011110100111111011110 step 164 111101111011110101011111011110 step 165 111101111011110101111111011110 step 166 111101111011110110011111011110 step 167 111101111011110110111111011110 step 168 111101111011110111011111011110 step 169 111101111011110111101111011110 step 170 111101111011110111100000111110 step 171 111101111011110111100001111110 step 172 111101111011110111100010111110 step 173 111101111011110111100011111110 step 174 111101111011110111100100111110 step 175 111101111011110111100101111110 step 176 111101111011110111100110111110 step 177 111101111011110111100111111110 step 178 111101111011110111101000111110 step 179 111101111011110111101001111110 step 180 111101111011110111101010111110 step 181 111101111011110111101011111110 step 182 111101111011110111101100111110 step 183 111101111011110111101101111110 step 184 111101111011110111101110111110 step 185 111101111011110111101111011110 step 186 111101111011110111101111000001 step 187 111101111011110111101111000011 step 188 111101111011110111101111000101 step 189 111101111011110111101111000111 step 190 111101111011110111101111001001 step 191 111101111011110111101111001011 step 192 111101111011110111101111001101 step 193 111101111011110111101111001111 step 194 111101111011110111101111010001 step 195 111101111011110111101111010011 step 196 111101111011110111101111010101 step 197 111101111011110111101111010111 step 198 111101111011110111101111011001 step 199 111101111011110111101111011011 step 200 111101111011110111101111011101 step 201 111101111011110111101111011110 step 202 111101111011110111101111011110 test 34: *** FAIL *************************** 6 steps failed SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFHJKLMNPRSDEFHJKLMNPRSTUV SIDE 111111111111111222222222222222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO this fail O all fails O was hi 111111111111111111111111111111 rising ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ falling vvvvvvvvvvvvvvvvvvvvvvvvvvvvvv was lo 000000000000000000000000000000 total fails 34, total passes 0 step 1 000010000100001000010000100001 step 2 000010000100001000010000100001 step 3 000110000100001000010000100001 step 4 001010000100001000010000100001 SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFHJKLMNPRSDEFHJKLMNPRSTUV SIDE 111111111111111222222222222222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 10 step 5 001100000100001000010000100001 fail ^ space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C toggle comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit step 6 010010000100001000010000100001 step 7 010110000100001000010000100001 step 8 011010000100001000010000100001 SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFHJKLMNPRSDEFHJKLMNPRSTUV SIDE 111111111111111222222222222222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 10 step 9 011100000100001000010000100001 fail ^ step 10 100010000100001000010000100001 step 11 100110000100001000010000100001 step 12 101010000100001000010000100001 SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFHJKLMNPRSDEFHJKLMNPRSTUV SIDE 111111111111111222222222222222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 10 step 13 101100000100001000010000100001 fail ^ step 14 110010000100001000010000100001 step 15 110110000100001000010000100001 step 16 111010000100001000010000100001 step 17 111100000100001000010000100001 step 18 000010000100001000010000100001 step 19 000010000100001000010000100001 step 20 000010001100001000010000100001 step 21 000010010100001000010000100001 step 22 000010011100001000010000100001 step 23 000010100100001000010000100001 step 24 000010101100001000010000100001 step 25 000010110100001000010000100001 step 26 000010111100001000010000100001 step 27 000011000100001000010000100001 step 28 000011001100001000010000100001 step 29 000011010100001000010000100001 step 30 000011011100001000010000100001 step 31 000011100100001000010000100001 step 32 000011101100001000010000100001 step 33 000011110100001000010000100001 step 34 000011111000001000010000100001 step 35 000010000100001000010000100001 step 36 000010000100001000010000100001 step 37 000010000100011000010000100001 step 38 000010000100101000010000100001 step 39 000010000100111000010000100001 step 40 000010000101001000010000100001 step 41 000010000101011000010000100001 step 42 000010000101101000010000100001 step 43 000010000101111000010000100001 step 44 000010000110001000010000100001 step 45 000010000110011000010000100001 step 46 000010000110101000010000100001 step 47 000010000110111000010000100001 step 48 000010000111001000010000100001 step 49 000010000111011000010000100001 step 50 000010000111101000010000100001 step 51 000010000111110000010000100001 step 52 000010000100001000010000100001 step 53 000010000100001000010000100001 step 54 000010000100001000110000100001 step 55 000010000100001001010000100001 step 56 000010000100001001110000100001 step 57 000010000100001010010000100001 step 58 000010000100001010110000100001 step 59 000010000100001011010000100001 step 60 000010000100001011110000100001 step 61 000010000100001100010000100001 step 62 000010000100001100110000100001 step 63 000010000100001101010000100001 step 64 000010000100001101110000100001 step 65 000010000100001110010000100001 step 66 000010000100001110110000100001 step 67 000010000100001111010000100001 step 68 000010000100001111100000100001 step 69 000010000100001000010000100001 step 70 000010000100001000010000100001 step 71 000010000100001000010001100001 step 72 000010000100001000010010100001 step 73 000010000100001000010011100001 step 74 000010000100001000010100100001 step 75 000010000100001000010101100001 step 76 000010000100001000010110100001 step 77 000010000100001000010111100001 step 78 000010000100001000011000100001 step 79 000010000100001000011001100001 step 80 000010000100001000011010100001 step 81 000010000100001000011011100001 step 82 000010000100001000011100100001 step 83 000010000100001000011101100001 step 84 000010000100001000011110100001 step 85 000010000100001000011111000001 step 86 000010000100001000010000100001 step 87 000010000100001000010000100001 step 88 000010000100001000010000100011 step 89 000010000100001000010000100101 step 90 000010000100001000010000100111 step 91 000010000100001000010000101001 step 92 000010000100001000010000101011 step 93 000010000100001000010000101101 step 94 000010000100001000010000101111 step 95 000010000100001000010000110001 step 96 000010000100001000010000110011 step 97 000010000100001000010000110101 step 98 000010000100001000010000110111 step 99 000010000100001000010000111001 step 100 000010000100001000010000111011 step 101 000010000100001000010000111101 step 102 000010000100001000010000111110 step 103 000010000100001000010000100001 step 104 000010000100001000010000100001 step 105 111101111011110111101111011110 step 106 000011111011110111101111011110 step 107 000111111011110111101111011110 step 108 001011111011110111101111011110 SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFHJKLMNPRSDEFHJKLMNPRSTUV SIDE 111111111111111222222222222222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 10 step 109 001101111011110111101111011110 fail ^ step 110 010011111011110111101111011110 step 111 010111111011110111101111011110 step 112 011011111011110111101111011110 SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFHJKLMNPRSDEFHJKLMNPRSTUV SIDE 111111111111111222222222222222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 10 step 113 011101111011110111101111011110 fail ^ step 114 100011111011110111101111011110 step 115 100111111011110111101111011110 step 116 101011111011110111101111011110 SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFHJKLMNPRSDEFHJKLMNPRSTUV SIDE 111111111111111222222222222222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 10 step 117 101101111011110111101111011110 fail ^ step 118 110011111011110111101111011110 step 119 110111111011110111101111011110 step 120 111011111011110111101111011110 step 121 111101111011110111101111011110 step 122 111100000111110111101111011110 step 123 111100001111110111101111011110 step 124 111100010111110111101111011110 step 125 111100011111110111101111011110 step 126 111100100111110111101111011110 step 127 111100101111110111101111011110 step 128 111100110111110111101111011110 step 129 111100111111110111101111011110 step 130 111101000111110111101111011110 step 131 111101001111110111101111011110 step 132 111101010111110111101111011110 step 133 111101011111110111101111011110 step 134 111101100111110111101111011110 step 135 111101101111110111101111011110 step 136 111101110111110111101111011110 step 137 111101111011110111101111011110 step 138 111101111000001111101111011110 step 139 111101111000011111101111011110 step 140 111101111000101111101111011110 step 141 111101111000111111101111011110 step 142 111101111001001111101111011110 step 143 111101111001011111101111011110 step 144 111101111001101111101111011110 step 145 111101111001111111101111011110 step 146 111101111010001111101111011110 step 147 111101111010011111101111011110 step 148 111101111010101111101111011110 step 149 111101111010111111101111011110 step 150 111101111011001111101111011110 step 151 111101111011011111101111011110 step 152 111101111011101111101111011110 step 153 111101111011110111101111011110 step 154 111101111011110000011111011110 step 155 111101111011110000111111011110 step 156 111101111011110001011111011110 step 157 111101111011110001111111011110 step 158 111101111011110010011111011110 step 159 111101111011110010111111011110 step 160 111101111011110011011111011110 step 161 111101111011110011111111011110 step 162 111101111011110100011111011110 step 163 111101111011110100111111011110 step 164 111101111011110101011111011110 step 165 111101111011110101111111011110 step 166 111101111011110110011111011110 step 167 111101111011110110111111011110 step 168 111101111011110111011111011110 step 169 111101111011110111101111011110 step 170 111101111011110111100000111110 step 171 111101111011110111100001111110 step 172 111101111011110111100010111110 step 173 111101111011110111100011111110 step 174 111101111011110111100100111110 step 175 111101111011110111100101111110 step 176 111101111011110111100110111110 step 177 111101111011110111100111111110 step 178 111101111011110111101000111110 step 179 111101111011110111101001111110 step 180 111101111011110111101010111110 step 181 111101111011110111101011111110 step 182 111101111011110111101100111110 step 183 111101111011110111101101111110 step 184 111101111011110111101110111110 step 185 111101111011110111101111011110 step 186 111101111011110111101111000001 step 187 111101111011110111101111000011 step 188 111101111011110111101111000101 step 189 111101111011110111101111000111 step 190 111101111011110111101111001001 step 191 111101111011110111101111001011 step 192 111101111011110111101111001101 step 193 111101111011110111101111001111 step 194 111101111011110111101111010001 step 195 111101111011110111101111010011 step 196 111101111011110111101111010101 step 197 111101111011110111101111010111 step 198 111101111011110111101111011001 step 199 111101111011110111101111011011 step 200 111101111011110111101111011101 step 201 111101111011110111101111011110 step 202 111101111011110111101111011110 test 35: *** FAIL *************************** 6 steps failed SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFHJKLMNPRSDEFHJKLMNPRSTUV SIDE 111111111111111222222222222222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO this fail O all fails O was hi 111111111111111111111111111111 rising ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ falling vvvvvvvvvvvvvvvvvvvvvvvvvvvvvv was lo 000000000000000000000000000000 total fails 35, total passes 0 space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C toggle comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit step 1 000010000100001000010000100001 step 2 000010000100001000010000100001 step 3 000110000100001000010000100001 step 4 001010000100001000010000100001 SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFHJKLMNPRSDEFHJKLMNPRSTUV SIDE 111111111111111222222222222222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 10 step 5 001100000100001000010000100001 fail ^ step 6 010010000100001000010000100001 step 7 010110000100001000010000100001 step 8 011010000100001000010000100001 SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFHJKLMNPRSDEFHJKLMNPRSTUV SIDE 111111111111111222222222222222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 10 step 9 011100000100001000010000100001 fail ^ step 10 100010000100001000010000100001 step 11 100110000100001000010000100001 step 12 101010000100001000010000100001 SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFHJKLMNPRSDEFHJKLMNPRSTUV SIDE 111111111111111222222222222222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 10 step 13 101100000100001000010000100001 fail ^ step 14 110010000100001000010000100001 step 15 110110000100001000010000100001 step 16 111010000100001000010000100001 step 17 111100000100001000010000100001 step 18 000010000100001000010000100001 step 19 000010000100001000010000100001 step 20 000010001100001000010000100001 step 21 000010010100001000010000100001 step 22 000010011100001000010000100001 step 23 000010100100001000010000100001 step 24 000010101100001000010000100001 step 25 000010110100001000010000100001 step 26 000010111100001000010000100001 step 27 000011000100001000010000100001 step 28 000011001100001000010000100001 step 29 000011010100001000010000100001 step 30 000011011100001000010000100001 step 31 000011100100001000010000100001 step 32 000011101100001000010000100001 step 33 000011110100001000010000100001 step 34 000011111000001000010000100001 step 35 000010000100001000010000100001 step 36 000010000100001000010000100001 step 37 000010000100011000010000100001 step 38 000010000100101000010000100001 step 39 000010000100111000010000100001 step 40 000010000101001000010000100001 step 41 000010000101011000010000100001 step 42 000010000101101000010000100001 step 43 000010000101111000010000100001 step 44 000010000110001000010000100001 step 45 000010000110011000010000100001 step 46 000010000110101000010000100001 step 47 000010000110111000010000100001 step 48 000010000111001000010000100001 step 49 000010000111011000010000100001 step 50 000010000111101000010000100001 step 51 000010000111110000010000100001 step 52 000010000100001000010000100001 step 53 000010000100001000010000100001 step 54 000010000100001000110000100001 step 55 000010000100001001010000100001 step 56 000010000100001001110000100001 step 57 000010000100001010010000100001 step 58 000010000100001010110000100001 step 59 000010000100001011010000100001 step 60 000010000100001011110000100001 step 61 000010000100001100010000100001 step 62 000010000100001100110000100001 step 63 000010000100001101010000100001 step 64 000010000100001101110000100001 step 65 000010000100001110010000100001 step 66 000010000100001110110000100001 step 67 000010000100001111010000100001 step 68 000010000100001111100000100001 step 69 000010000100001000010000100001 step 70 000010000100001000010000100001 step 71 000010000100001000010001100001 step 72 000010000100001000010010100001 step 73 000010000100001000010011100001 step 74 000010000100001000010100100001 step 75 000010000100001000010101100001 step 76 000010000100001000010110100001 step 77 000010000100001000010111100001 step 78 000010000100001000011000100001 step 79 000010000100001000011001100001 step 80 000010000100001000011010100001 step 81 000010000100001000011011100001 step 82 000010000100001000011100100001 step 83 000010000100001000011101100001 step 84 000010000100001000011110100001 step 85 000010000100001000011111000001 step 86 000010000100001000010000100001 step 87 000010000100001000010000100001 step 88 000010000100001000010000100011 step 89 000010000100001000010000100101 step 90 000010000100001000010000100111 step 91 000010000100001000010000101001 step 92 000010000100001000010000101011 step 93 000010000100001000010000101101 step 94 000010000100001000010000101111 step 95 000010000100001000010000110001 step 96 000010000100001000010000110011 step 97 000010000100001000010000110101 step 98 000010000100001000010000110111 step 99 000010000100001000010000111001 step 100 000010000100001000010000111011 step 101 000010000100001000010000111101 step 102 000010000100001000010000111110 step 103 000010000100001000010000100001 step 104 000010000100001000010000100001 step 105 111101111011110111101111011110 step 106 000011111011110111101111011110 step 107 000111111011110111101111011110 step 108 001011111011110111101111011110 SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFHJKLMNPRSDEFHJKLMNPRSTUV SIDE 111111111111111222222222222222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 10 step 109 001101111011110111101111011110 fail ^ step 110 010011111011110111101111011110 step 111 010111111011110111101111011110 step 112 011011111011110111101111011110 SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFHJKLMNPRSDEFHJKLMNPRSTUV SIDE 111111111111111222222222222222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 10 step 113 011101111011110111101111011110 fail ^ step 114 100011111011110111101111011110 step 115 100111111011110111101111011110 step 116 101011111011110111101111011110 SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFHJKLMNPRSDEFHJKLMNPRSTUV SIDE 111111111111111222222222222222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 10 step 117 101101111011110111101111011110 fail ^ step 118 110011111011110111101111011110 step 119 110111111011110111101111011110 step 120 111011111011110111101111011110 step 121 111101111011110111101111011110 step 122 111100000111110111101111011110 step 123 111100001111110111101111011110 step 124 111100010111110111101111011110 step 125 111100011111110111101111011110 step 126 111100100111110111101111011110 step 127 111100101111110111101111011110 step 128 111100110111110111101111011110 step 129 111100111111110111101111011110 step 130 111101000111110111101111011110 step 131 111101001111110111101111011110 step 132 111101010111110111101111011110 step 133 111101011111110111101111011110 step 134 111101100111110111101111011110 step 135 111101101111110111101111011110 step 136 111101110111110111101111011110 step 137 111101111011110111101111011110 step 138 111101111000001111101111011110 step 139 111101111000011111101111011110 step 140 111101111000101111101111011110 step 141 111101111000111111101111011110 step 142 111101111001001111101111011110 step 143 111101111001011111101111011110 step 144 111101111001101111101111011110 step 145 111101111001111111101111011110 step 146 111101111010001111101111011110 step 147 111101111010011111101111011110 step 148 111101111010101111101111011110 step 149 111101111010111111101111011110 step 150 111101111011001111101111011110 step 151 111101111011011111101111011110 step 152 111101111011101111101111011110 step 153 111101111011110111101111011110 step 154 111101111011110000011111011110 step 155 111101111011110000111111011110 step 156 111101111011110001011111011110 step 157 111101111011110001111111011110 step 158 111101111011110010011111011110 step 159 111101111011110010111111011110 step 160 111101111011110011011111011110 step 161 111101111011110011111111011110 step 162 111101111011110100011111011110 step 163 111101111011110100111111011110 step 164 111101111011110101011111011110 step 165 111101111011110101111111011110 step 166 111101111011110110011111011110 step 167 111101111011110110111111011110 step 168 111101111011110111011111011110 step 169 111101111011110111101111011110 step 170 111101111011110111100000111110 step 171 111101111011110111100001111110 step 172 111101111011110111100010111110 step 173 111101111011110111100011111110 step 174 111101111011110111100100111110 step 175 111101111011110111100101111110 step 176 111101111011110111100110111110 step 177 111101111011110111100111111110 step 178 111101111011110111101000111110 step 179 111101111011110111101001111110 step 180 111101111011110111101010111110 step 181 111101111011110111101011111110 step 182 111101111011110111101100111110 step 183 111101111011110111101101111110 step 184 111101111011110111101110111110 step 185 111101111011110111101111011110 step 186 111101111011110111101111000001 step 187 111101111011110111101111000011 step 188 111101111011110111101111000101 step 189 111101111011110111101111000111 step 190 111101111011110111101111001001 step 191 111101111011110111101111001011 step 192 111101111011110111101111001101 step 193 111101111011110111101111001111 step 194 111101111011110111101111010001 step 195 111101111011110111101111010011 step 196 111101111011110111101111010101 step 197 111101111011110111101111010111 step 198 111101111011110111101111011001 step 199 111101111011110111101111011011 step 200 111101111011110111101111011101 step 201 111101111011110111101111011110 step 202 111101111011110111101111011110 test 36: *** FAIL *************************** 6 steps failed SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFHJKLMNPRSDEFHJKLMNPRSTUV SIDE 111111111111111222222222222222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO this fail O all fails O was hi 111111111111111111111111111111 rising ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ falling vvvvvvvvvvvvvvvvvvvvvvvvvvvvvv was lo 000000000000000000000000000000 total fails 36, total passes 0 space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C toggle comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit failure mode analysis: pin: 5 O AE1 E1-8 SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFHJKLMNPRSDEFHJKLMNPRSTUV SIDE 111111111111111222222222222222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO fails LO: 1111 1111111111111111111111111 fails LO: 00 0000000000000000000000000 fails HI: fails HI: space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C toggle comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFHJKLMNPRSDEFHJKLMNPRSTUV SIDE 111111111111111222222222222222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO all fails O was lo 000000000000000000000000000000 falling vvvvvvvvvvvvvvvvvvvvvvvvvvvvvv rising ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ was hi 111111111111111111111111111111 total fails 36, total passes 0 Main menu Mon Jul 27 15:24:02 2015 test file is: tests\m617.tst delay is: 0 trigger is: 1 1 read test file 2 set test delay 3 set test trigger 4 run test 5 output loading test 8 diags 9 exit UUT power is okay Mon Jul 27 15:24:04 2015 space single step O run once (one test, all steps) F run, stop on fail G go (run tests N run, stop on fail, no print S scope (run, no print) C toggle comment printout + increase speed (less delay) - decrease speed (more delay)(slower) Q quit test step 1 000010000100001000010000100001 step 2 000010000100001000010000100001 step 3 000110000100001000010000100001 step 4 001010000100001000010000100001 SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFHJKLMNPRSDEFHJKLMNPRSTUV SIDE 111111111111111222222222222222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 10 step 5 001100000100001000010000100001 fail ^ step 6 010010000100001000010000100001 step 7 010110000100001000010000100001 step 8 011010000100001000010000100001 SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFHJKLMNPRSDEFHJKLMNPRSTUV SIDE 111111111111111222222222222222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 10 step 9 011100000100001000010000100001 fail ^ step 10 100010000100001000010000100001 step 11 100110000100001000010000100001 step 12 101010000100001000010000100001 SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFHJKLMNPRSDEFHJKLMNPRSTUV SIDE 111111111111111222222222222222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 10 step 13 101100000100001000010000100001 fail ^ step 14 110010000100001000010000100001 step 15 110110000100001000010000100001 step 16 111010000100001000010000100001 step 17 111100000100001000010000100001 step 18 000010000100001000010000100001 step 19 000010000100001000010000100001 step 20 000010001100001000010000100001 step 21 000010010100001000010000100001 step 22 000010011100001000010000100001 step 23 000010100100001000010000100001 step 24 000010101100001000010000100001 step 25 000010110100001000010000100001 step 26 000010111100001000010000100001 step 27 000011000100001000010000100001 step 28 000011001100001000010000100001 step 29 000011010100001000010000100001 step 30 000011011100001000010000100001 step 31 000011100100001000010000100001 step 32 000011101100001000010000100001 step 33 000011110100001000010000100001 step 34 000011111000001000010000100001 step 35 000010000100001000010000100001 step 36 000010000100001000010000100001 step 37 000010000100011000010000100001 step 38 000010000100101000010000100001 step 39 000010000100111000010000100001 step 40 000010000101001000010000100001 step 41 000010000101011000010000100001 step 42 000010000101101000010000100001 step 43 000010000101111000010000100001 step 44 000010000110001000010000100001 step 45 000010000110011000010000100001 step 46 000010000110101000010000100001 step 47 000010000110111000010000100001 step 48 000010000111001000010000100001 step 49 000010000111011000010000100001 step 50 000010000111101000010000100001 step 51 000010000111110000010000100001 step 52 000010000100001000010000100001 step 53 000010000100001000010000100001 step 54 000010000100001000110000100001 step 55 000010000100001001010000100001 step 56 000010000100001001110000100001 step 57 000010000100001010010000100001 step 58 000010000100001010110000100001 step 59 000010000100001011010000100001 step 60 000010000100001011110000100001 step 61 000010000100001100010000100001 step 62 000010000100001100110000100001 step 63 000010000100001101010000100001 step 64 000010000100001101110000100001 step 65 000010000100001110010000100001 step 66 000010000100001110110000100001 step 67 000010000100001111010000100001 step 68 000010000100001111100000100001 step 69 000010000100001000010000100001 step 70 000010000100001000010000100001 step 71 000010000100001000010001100001 step 72 000010000100001000010010100001 step 73 000010000100001000010011100001 step 74 000010000100001000010100100001 step 75 000010000100001000010101100001 step 76 000010000100001000010110100001 step 77 000010000100001000010111100001 step 78 000010000100001000011000100001 step 79 000010000100001000011001100001 step 80 000010000100001000011010100001 step 81 000010000100001000011011100001 step 82 000010000100001000011100100001 step 83 000010000100001000011101100001 step 84 000010000100001000011110100001 step 85 000010000100001000011111000001 step 86 000010000100001000010000100001 step 87 000010000100001000010000100001 step 88 000010000100001000010000100011 step 89 000010000100001000010000100101 step 90 000010000100001000010000100111 step 91 000010000100001000010000101001 step 92 000010000100001000010000101011 step 93 000010000100001000010000101101 step 94 000010000100001000010000101111 step 95 000010000100001000010000110001 step 96 000010000100001000010000110011 step 97 000010000100001000010000110101 step 98 000010000100001000010000110111 step 99 000010000100001000010000111001 step 100 000010000100001000010000111011 step 101 000010000100001000010000111101 step 102 000010000100001000010000111110 step 103 000010000100001000010000100001 step 104 000010000100001000010000100001 step 105 111101111011110111101111011110 step 106 000011111011110111101111011110 step 107 000111111011110111101111011110 step 108 001011111011110111101111011110 SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFHJKLMNPRSDEFHJKLMNPRSTUV SIDE 111111111111111222222222222222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 10 step 109 001101111011110111101111011110 fail ^ step 110 010011111011110111101111011110 step 111 010111111011110111101111011110 step 112 011011111011110111101111011110 SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFHJKLMNPRSDEFHJKLMNPRSTUV SIDE 111111111111111222222222222222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 10 step 113 011101111011110111101111011110 fail ^ step 114 100011111011110111101111011110 step 115 100111111011110111101111011110 step 116 101011111011110111101111011110 SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFHJKLMNPRSDEFHJKLMNPRSTUV SIDE 111111111111111222222222222222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 10 step 117 101101111011110111101111011110 fail ^ step 118 110011111011110111101111011110 step 119 110111111011110111101111011110 step 120 111011111011110111101111011110 step 121 111101111011110111101111011110 step 122 111100000111110111101111011110 step 123 111100001111110111101111011110 step 124 111100010111110111101111011110 step 125 111100011111110111101111011110 step 126 111100100111110111101111011110 step 127 111100101111110111101111011110 step 128 111100110111110111101111011110 step 129 111100111111110111101111011110 step 130 111101000111110111101111011110 step 131 111101001111110111101111011110 step 132 111101010111110111101111011110 step 133 111101011111110111101111011110 step 134 111101100111110111101111011110 step 135 111101101111110111101111011110 step 136 111101110111110111101111011110 step 137 111101111011110111101111011110 step 138 111101111000001111101111011110 step 139 111101111000011111101111011110 step 140 111101111000101111101111011110 step 141 111101111000111111101111011110 step 142 111101111001001111101111011110 step 143 111101111001011111101111011110 step 144 111101111001101111101111011110 step 145 111101111001111111101111011110 step 146 111101111010001111101111011110 step 147 111101111010011111101111011110 step 148 111101111010101111101111011110 step 149 111101111010111111101111011110 step 150 111101111011001111101111011110 step 151 111101111011011111101111011110 step 152 111101111011101111101111011110 step 153 111101111011110111101111011110 step 154 111101111011110000011111011110 step 155 111101111011110000111111011110 step 156 111101111011110001011111011110 step 157 111101111011110001111111011110 step 158 111101111011110010011111011110 step 159 111101111011110010111111011110 step 160 111101111011110011011111011110 step 161 111101111011110011111111011110 step 162 111101111011110100011111011110 step 163 111101111011110100111111011110 step 164 111101111011110101011111011110 step 165 111101111011110101111111011110 step 166 111101111011110110011111011110 step 167 111101111011110110111111011110 step 168 111101111011110111011111011110 step 169 111101111011110111101111011110 step 170 111101111011110111100000111110 step 171 111101111011110111100001111110 step 172 111101111011110111100010111110 step 173 111101111011110111100011111110 step 174 111101111011110111100100111110 step 175 111101111011110111100101111110 step 176 111101111011110111100110111110 step 177 111101111011110111100111111110 step 178 111101111011110111101000111110 step 179 111101111011110111101001111110 step 180 111101111011110111101010111110 step 181 111101111011110111101011111110 step 182 111101111011110111101100111110 step 183 111101111011110111101101111110 step 184 111101111011110111101110111110 step 185 111101111011110111101111011110 step 186 111101111011110111101111000001 step 187 111101111011110111101111000011 step 188 111101111011110111101111000101 step 189 111101111011110111101111000111 step 190 111101111011110111101111001001 step 191 111101111011110111101111001011 step 192 111101111011110111101111001101 step 193 111101111011110111101111001111 step 194 111101111011110111101111010001 step 195 111101111011110111101111010011 step 196 111101111011110111101111010101 step 197 111101111011110111101111010111 step 198 111101111011110111101111011001 step 199 111101111011110111101111011011 step 200 111101111011110111101111011101 step 201 111101111011110111101111011110 step 202 111101111011110111101111011110 test 1: *** FAIL *************************** 6 steps failed SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFHJKLMNPRSDEFHJKLMNPRSTUV SIDE 111111111111111222222222222222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO this fail O all fails O was hi 111111111111111111111111111111 rising ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ falling vvvvvvvvvvvvvvvvvvvvvvvvvvvvvv was lo 000000000000000000000000000000 total fails 1, total passes 0 space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C toggle comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit up to this point: PINS that are always low PINS that are always high space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C toggle comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit step 1 000010000100001000010000100001 step 2 000010000100001000010000100001 step 3 000110000100001000010000100001 step 4 001010000100001000010000100001 SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFHJKLMNPRSDEFHJKLMNPRSTUV SIDE 111111111111111222222222222222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 10 step 5 001100000100001000010000100001 fail ^ step 6 010010000100001000010000100001 step 7 010110000100001000010000100001 step 8 011010000100001000010000100001 SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFHJKLMNPRSDEFHJKLMNPRSTUV SIDE 111111111111111222222222222222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 10 step 9 011100000100001000010000100001 fail ^ step 10 100010000100001000010000100001 step 11 100110000100001000010000100001 step 12 101010000100001000010000100001 SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFHJKLMNPRSDEFHJKLMNPRSTUV SIDE 111111111111111222222222222222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 10 step 13 101100000100001000010000100001 fail ^ step 14 110010000100001000010000100001 step 15 110110000100001000010000100001 step 16 111010000100001000010000100001 step 17 111100000100001000010000100001 step 18 000010000100001000010000100001 step 19 000010000100001000010000100001 step 20 000010001100001000010000100001 step 21 000010010100001000010000100001 step 22 000010011100001000010000100001 step 23 000010100100001000010000100001 step 24 000010101100001000010000100001 step 25 000010110100001000010000100001 step 26 000010111100001000010000100001 step 27 000011000100001000010000100001 step 28 000011001100001000010000100001 step 29 000011010100001000010000100001 step 30 000011011100001000010000100001 step 31 000011100100001000010000100001 step 32 000011101100001000010000100001 step 33 000011110100001000010000100001 step 34 000011111000001000010000100001 step 35 000010000100001000010000100001 step 36 000010000100001000010000100001 step 37 000010000100011000010000100001 step 38 000010000100101000010000100001 step 39 000010000100111000010000100001 step 40 000010000101001000010000100001 step 41 000010000101011000010000100001 step 42 000010000101101000010000100001 step 43 000010000101111000010000100001 step 44 000010000110001000010000100001 step 45 000010000110011000010000100001 step 46 000010000110101000010000100001 step 47 000010000110111000010000100001 step 48 000010000111001000010000100001 step 49 000010000111011000010000100001 step 50 000010000111101000010000100001 step 51 000010000111110000010000100001 step 52 000010000100001000010000100001 step 53 000010000100001000010000100001 step 54 000010000100001000110000100001 step 55 000010000100001001010000100001 step 56 000010000100001001110000100001 step 57 000010000100001010010000100001 step 58 000010000100001010110000100001 step 59 000010000100001011010000100001 step 60 000010000100001011110000100001 step 61 000010000100001100010000100001 step 62 000010000100001100110000100001 step 63 000010000100001101010000100001 step 64 000010000100001101110000100001 step 65 000010000100001110010000100001 step 66 000010000100001110110000100001 step 67 000010000100001111010000100001 step 68 000010000100001111100000100001 step 69 000010000100001000010000100001 step 70 000010000100001000010000100001 step 71 000010000100001000010001100001 step 72 000010000100001000010010100001 step 73 000010000100001000010011100001 step 74 000010000100001000010100100001 step 75 000010000100001000010101100001 step 76 000010000100001000010110100001 step 77 000010000100001000010111100001 step 78 000010000100001000011000100001 step 79 000010000100001000011001100001 step 80 000010000100001000011010100001 step 81 000010000100001000011011100001 step 82 000010000100001000011100100001 step 83 000010000100001000011101100001 step 84 000010000100001000011110100001 step 85 000010000100001000011111000001 step 86 000010000100001000010000100001 step 87 000010000100001000010000100001 step 88 000010000100001000010000100011 step 89 000010000100001000010000100101 step 90 000010000100001000010000100111 step 91 000010000100001000010000101001 step 92 000010000100001000010000101011 step 93 000010000100001000010000101101 step 94 000010000100001000010000101111 step 95 000010000100001000010000110001 step 96 000010000100001000010000110011 step 97 000010000100001000010000110101 step 98 000010000100001000010000110111 step 99 000010000100001000010000111001 step 100 000010000100001000010000111011 step 101 000010000100001000010000111101 step 102 000010000100001000010000111110 step 103 000010000100001000010000100001 step 104 000010000100001000010000100001 step 105 111101111011110111101111011110 step 106 000011111011110111101111011110 step 107 000111111011110111101111011110 step 108 001011111011110111101111011110 SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFHJKLMNPRSDEFHJKLMNPRSTUV SIDE 111111111111111222222222222222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 10 step 109 001101111011110111101111011110 fail ^ step 110 010011111011110111101111011110 step 111 010111111011110111101111011110 step 112 011011111011110111101111011110 SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFHJKLMNPRSDEFHJKLMNPRSTUV SIDE 111111111111111222222222222222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 10 step 113 011101111011110111101111011110 fail ^ step 114 100011111011110111101111011110 step 115 100111111011110111101111011110 step 116 101011111011110111101111011110 SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFHJKLMNPRSDEFHJKLMNPRSTUV SIDE 111111111111111222222222222222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 10 step 117 101101111011110111101111011110 fail ^ step 118 110011111011110111101111011110 step 119 110111111011110111101111011110 step 120 111011111011110111101111011110 step 121 111101111011110111101111011110 step 122 111100000111110111101111011110 step 123 111100001111110111101111011110 step 124 111100010111110111101111011110 step 125 111100011111110111101111011110 step 126 111100100111110111101111011110 step 127 111100101111110111101111011110 step 128 111100110111110111101111011110 step 129 111100111111110111101111011110 step 130 111101000111110111101111011110 step 131 111101001111110111101111011110 step 132 111101010111110111101111011110 step 133 111101011111110111101111011110 step 134 111101100111110111101111011110 step 135 111101101111110111101111011110 step 136 111101110111110111101111011110 step 137 111101111011110111101111011110 step 138 111101111000001111101111011110 step 139 111101111000011111101111011110 step 140 111101111000101111101111011110 step 141 111101111000111111101111011110 step 142 111101111001001111101111011110 step 143 111101111001011111101111011110 step 144 111101111001101111101111011110 step 145 111101111001111111101111011110 step 146 111101111010001111101111011110 step 147 111101111010011111101111011110 step 148 111101111010101111101111011110 step 149 111101111010111111101111011110 step 150 111101111011001111101111011110 step 151 111101111011011111101111011110 step 152 111101111011101111101111011110 step 153 111101111011110111101111011110 step 154 111101111011110000011111011110 step 155 111101111011110000111111011110 step 156 111101111011110001011111011110 step 157 111101111011110001111111011110 step 158 111101111011110010011111011110 step 159 111101111011110010111111011110 step 160 111101111011110011011111011110 step 161 111101111011110011111111011110 step 162 111101111011110100011111011110 step 163 111101111011110100111111011110 step 164 111101111011110101011111011110 step 165 111101111011110101111111011110 step 166 111101111011110110011111011110 step 167 111101111011110110111111011110 step 168 111101111011110111011111011110 step 169 111101111011110111101111011110 step 170 111101111011110111100000111110 step 171 111101111011110111100001111110 step 172 111101111011110111100010111110 step 173 111101111011110111100011111110 step 174 111101111011110111100100111110 step 175 111101111011110111100101111110 step 176 111101111011110111100110111110 step 177 111101111011110111100111111110 step 178 111101111011110111101000111110 step 179 111101111011110111101001111110 step 180 111101111011110111101010111110 step 181 111101111011110111101011111110 step 182 111101111011110111101100111110 step 183 111101111011110111101101111110 step 184 111101111011110111101110111110 step 185 111101111011110111101111011110 step 186 111101111011110111101111000001 step 187 111101111011110111101111000011 step 188 111101111011110111101111000101 step 189 111101111011110111101111000111 step 190 111101111011110111101111001001 step 191 111101111011110111101111001011 step 192 111101111011110111101111001101 step 193 111101111011110111101111001111 step 194 111101111011110111101111010001 step 195 111101111011110111101111010011 step 196 111101111011110111101111010101 step 197 111101111011110111101111010111 step 198 111101111011110111101111011001 step 199 111101111011110111101111011011 step 200 111101111011110111101111011101 step 201 111101111011110111101111011110 step 202 111101111011110111101111011110 test 2: *** FAIL *************************** 6 steps failed SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFHJKLMNPRSDEFHJKLMNPRSTUV SIDE 111111111111111222222222222222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO this fail O all fails O was hi 111111111111111111111111111111 rising ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ falling vvvvvvvvvvvvvvvvvvvvvvvvvvvvvv was lo 000000000000000000000000000000 total fails 2, total passes 0 space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C toggle comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit up to this point: PINS that are always low PINS that are always high space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C toggle comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit failure mode analysis: pin: 5 O AE1 E1-8 SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFHJKLMNPRSDEFHJKLMNPRSTUV SIDE 111111111111111222222222222222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO fails LO: 1111 1111111111111111111111111 fails LO: 00 0000000000000000000000000 fails HI: fails HI: space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C toggle comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit step 1 000010000100001000010000100001 step 2 000010000100001000010000100001 step 3 000110000100001000010000100001 step 4 001010000100001000010000100001 SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFHJKLMNPRSDEFHJKLMNPRSTUV SIDE 111111111111111222222222222222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 10 step 5 001100000100001000010000100001 fail ^ space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C toggle comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFHJKLMNPRSDEFHJKLMNPRSTUV SIDE 111111111111111222222222222222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 100 0 0 0 0 0 step 6 010000000000000000000000000000 fail ^ ^ ^ ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFHJKLMNPRSDEFHJKLMNPRSTUV SIDE 111111111111111222222222222222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 1 step 7 010100000000000000000000000000 fail ^ ^ ^ ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFHJKLMNPRSDEFHJKLMNPRSTUV SIDE 111111111111111222222222222222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 10 step 8 011000000000000000000000000000 fail ^ ^ ^ ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFHJKLMNPRSDEFHJKLMNPRSTUV SIDE 111111111111111222222222222222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 1 step 9 011100000000000000000000000000 fail ^ ^ ^ ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFHJKLMNPRSDEFHJKLMNPRSTUV SIDE 111111111111111222222222222222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 1000 step 10 100000000000000000000000000000 fail ^ ^ ^ ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFHJKLMNPRSDEFHJKLMNPRSTUV SIDE 111111111111111222222222222222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 1 step 11 100100000000000000000000000000 fail ^ ^ ^ ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFHJKLMNPRSDEFHJKLMNPRSTUV SIDE 111111111111111222222222222222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 10 step 12 101000000000000000000000000000 fail ^ ^ ^ ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFHJKLMNPRSDEFHJKLMNPRSTUV SIDE 111111111111111222222222222222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 1 step 13 101100000000000000000000000000 fail ^ ^ ^ ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFHJKLMNPRSDEFHJKLMNPRSTUV SIDE 111111111111111222222222222222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 100 step 14 110000000000000000000000000000 fail ^ ^ ^ ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFHJKLMNPRSDEFHJKLMNPRSTUV SIDE 111111111111111222222222222222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 1 step 15 110100000000000000000000000000 fail ^ ^ ^ ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFHJKLMNPRSDEFHJKLMNPRSTUV SIDE 111111111111111222222222222222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 10 step 16 111000000000000000000000000000 fail ^ ^ ^ ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFHJKLMNPRSDEFHJKLMNPRSTUV SIDE 111111111111111222222222222222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 1 step 17 111100000000000000000000000000 fail ^ ^ ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFHJKLMNPRSDEFHJKLMNPRSTUV SIDE 111111111111111222222222222222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 0000 step 18 000000000000000000000000000000 fail ^ ^ ^ ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFHJKLMNPRSDEFHJKLMNPRSTUV SIDE 111111111111111222222222222222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: step 19 000000000000000000000000000000 fail ^ ^ ^ ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFHJKLMNPRSDEFHJKLMNPRSTUV SIDE 111111111111111222222222222222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 1 step 20 000000001000000000000000000000 fail ^ ^ ^ ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFHJKLMNPRSDEFHJKLMNPRSTUV SIDE 111111111111111222222222222222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 10 step 21 000000010000000000000000000000 fail ^ ^ ^ ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFHJKLMNPRSDEFHJKLMNPRSTUV SIDE 111111111111111222222222222222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 1 step 22 000000011000000000000000000000 fail ^ ^ ^ ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFHJKLMNPRSDEFHJKLMNPRSTUV SIDE 111111111111111222222222222222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 100 step 23 000000100000000000000000000000 fail ^ ^ ^ ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFHJKLMNPRSDEFHJKLMNPRSTUV SIDE 111111111111111222222222222222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 1 step 24 000000101000000000000000000000 fail ^ ^ ^ ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFHJKLMNPRSDEFHJKLMNPRSTUV SIDE 111111111111111222222222222222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 10 step 25 000000110000000000000000000000 fail ^ ^ ^ ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFHJKLMNPRSDEFHJKLMNPRSTUV SIDE 111111111111111222222222222222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 1 step 26 000000111000000000000000000000 fail ^ ^ ^ ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFHJKLMNPRSDEFHJKLMNPRSTUV SIDE 111111111111111222222222222222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 1000 step 27 000001000000000000000000000000 fail ^ ^ ^ ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFHJKLMNPRSDEFHJKLMNPRSTUV SIDE 111111111111111222222222222222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 1 step 28 000001001000000000000000000000 fail ^ ^ ^ ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFHJKLMNPRSDEFHJKLMNPRSTUV SIDE 111111111111111222222222222222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 10 step 29 000001010000000000000000000000 fail ^ ^ ^ ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFHJKLMNPRSDEFHJKLMNPRSTUV SIDE 111111111111111222222222222222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 1 step 30 000001011000000000000000000000 fail ^ ^ ^ ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFHJKLMNPRSDEFHJKLMNPRSTUV SIDE 111111111111111222222222222222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 100 step 31 000001100000000000000000000000 fail ^ ^ ^ ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFHJKLMNPRSDEFHJKLMNPRSTUV SIDE 111111111111111222222222222222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 1 step 32 000001101000000000000000000000 fail ^ ^ ^ ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFHJKLMNPRSDEFHJKLMNPRSTUV SIDE 111111111111111222222222222222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 10 step 33 000001110000000000000000000000 fail ^ ^ ^ ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFHJKLMNPRSDEFHJKLMNPRSTUV SIDE 111111111111111222222222222222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 1 step 34 000001111000000000000000000000 fail ^ ^ ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFHJKLMNPRSDEFHJKLMNPRSTUV SIDE 111111111111111222222222222222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 0000 step 35 000000000000000000000000000000 fail ^ ^ ^ ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFHJKLMNPRSDEFHJKLMNPRSTUV SIDE 111111111111111222222222222222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: step 36 000000000000000000000000000000 fail ^ ^ ^ ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFHJKLMNPRSDEFHJKLMNPRSTUV SIDE 111111111111111222222222222222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 1 step 37 000000000000010000000000000000 fail ^ ^ ^ ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFHJKLMNPRSDEFHJKLMNPRSTUV SIDE 111111111111111222222222222222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 10 step 38 000000000000100000000000000000 fail ^ ^ ^ ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFHJKLMNPRSDEFHJKLMNPRSTUV SIDE 111111111111111222222222222222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 1 step 39 000000000000110000000000000000 fail ^ ^ ^ ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFHJKLMNPRSDEFHJKLMNPRSTUV SIDE 111111111111111222222222222222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 100 step 40 000000000001000000000000000000 fail ^ ^ ^ ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFHJKLMNPRSDEFHJKLMNPRSTUV SIDE 111111111111111222222222222222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 1 step 41 000000000001010000000000000000 fail ^ ^ ^ ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFHJKLMNPRSDEFHJKLMNPRSTUV SIDE 111111111111111222222222222222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 10 step 42 000000000001100000000000000000 fail ^ ^ ^ ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFHJKLMNPRSDEFHJKLMNPRSTUV SIDE 111111111111111222222222222222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 1 step 43 000000000001110000000000000000 fail ^ ^ ^ ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFHJKLMNPRSDEFHJKLMNPRSTUV SIDE 111111111111111222222222222222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 1000 step 44 000000000010000000000000000000 fail ^ ^ ^ ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFHJKLMNPRSDEFHJKLMNPRSTUV SIDE 111111111111111222222222222222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 1 step 45 000000000010010000000000000000 fail ^ ^ ^ ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFHJKLMNPRSDEFHJKLMNPRSTUV SIDE 111111111111111222222222222222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 10 step 46 000000000010100000000000000000 fail ^ ^ ^ ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFHJKLMNPRSDEFHJKLMNPRSTUV SIDE 111111111111111222222222222222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 1 step 47 000000000010110000000000000000 fail ^ ^ ^ ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFHJKLMNPRSDEFHJKLMNPRSTUV SIDE 111111111111111222222222222222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 100 step 48 000000000011000000000000000000 fail ^ ^ ^ ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFHJKLMNPRSDEFHJKLMNPRSTUV SIDE 111111111111111222222222222222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 1 step 49 000000000011010000000000000000 fail ^ ^ ^ ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFHJKLMNPRSDEFHJKLMNPRSTUV SIDE 111111111111111222222222222222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 10 step 50 000000000011100000000000000000 fail ^ ^ ^ ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFHJKLMNPRSDEFHJKLMNPRSTUV SIDE 111111111111111222222222222222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 1 step 51 000000000011110000000000000000 fail ^ ^ ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFHJKLMNPRSDEFHJKLMNPRSTUV SIDE 111111111111111222222222222222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 0000 step 52 000000000000000000000000000000 fail ^ ^ ^ ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFHJKLMNPRSDEFHJKLMNPRSTUV SIDE 111111111111111222222222222222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: step 53 000000000000000000000000000000 fail ^ ^ ^ ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFHJKLMNPRSDEFHJKLMNPRSTUV SIDE 111111111111111222222222222222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 1 step 54 000000000000000000100000000000 fail ^ ^ ^ ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFHJKLMNPRSDEFHJKLMNPRSTUV SIDE 111111111111111222222222222222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 10 step 55 000000000000000001000000000000 fail ^ ^ ^ ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFHJKLMNPRSDEFHJKLMNPRSTUV SIDE 111111111111111222222222222222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 1 step 56 000000000000000001100000000000 fail ^ ^ ^ ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFHJKLMNPRSDEFHJKLMNPRSTUV SIDE 111111111111111222222222222222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 100 step 57 000000000000000010000000000000 fail ^ ^ ^ ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFHJKLMNPRSDEFHJKLMNPRSTUV SIDE 111111111111111222222222222222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 1 step 58 000000000000000010100000000000 fail ^ ^ ^ ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFHJKLMNPRSDEFHJKLMNPRSTUV SIDE 111111111111111222222222222222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 10 step 59 000000000000000011000000000000 fail ^ ^ ^ ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFHJKLMNPRSDEFHJKLMNPRSTUV SIDE 111111111111111222222222222222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 1 step 60 000000000000000011100000000000 fail ^ ^ ^ ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFHJKLMNPRSDEFHJKLMNPRSTUV SIDE 111111111111111222222222222222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 1000 step 61 000000000000000100000000000000 fail ^ ^ ^ ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFHJKLMNPRSDEFHJKLMNPRSTUV SIDE 111111111111111222222222222222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 1 step 62 000000000000000100100000000000 fail ^ ^ ^ ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFHJKLMNPRSDEFHJKLMNPRSTUV SIDE 111111111111111222222222222222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 10 step 63 000000000000000101000000000000 fail ^ ^ ^ ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFHJKLMNPRSDEFHJKLMNPRSTUV SIDE 111111111111111222222222222222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 1 step 64 000000000000000101100000000000 fail ^ ^ ^ ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFHJKLMNPRSDEFHJKLMNPRSTUV SIDE 111111111111111222222222222222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 100 step 65 000000000000000110000000000000 fail ^ ^ ^ ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFHJKLMNPRSDEFHJKLMNPRSTUV SIDE 111111111111111222222222222222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 1 step 66 000000000000000110100000000000 fail ^ ^ ^ ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFHJKLMNPRSDEFHJKLMNPRSTUV SIDE 111111111111111222222222222222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 10 step 67 000000000000000111000000000000 fail ^ ^ ^ ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFHJKLMNPRSDEFHJKLMNPRSTUV SIDE 111111111111111222222222222222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 1 step 68 000000000000000111100000000000 fail ^ ^ ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFHJKLMNPRSDEFHJKLMNPRSTUV SIDE 111111111111111222222222222222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 0000 step 69 000000000000000000000000000000 fail ^ ^ ^ ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFHJKLMNPRSDEFHJKLMNPRSTUV SIDE 111111111111111222222222222222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: step 70 000000000000000000000000000000 fail ^ ^ ^ ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFHJKLMNPRSDEFHJKLMNPRSTUV SIDE 111111111111111222222222222222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 1 step 71 000000000000000000000001000000 fail ^ ^ ^ ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFHJKLMNPRSDEFHJKLMNPRSTUV SIDE 111111111111111222222222222222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 10 step 72 000000000000000000000010000000 fail ^ ^ ^ ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFHJKLMNPRSDEFHJKLMNPRSTUV SIDE 111111111111111222222222222222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 1 step 73 000000000000000000000011000000 fail ^ ^ ^ ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFHJKLMNPRSDEFHJKLMNPRSTUV SIDE 111111111111111222222222222222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 100 step 74 000000000000000000000100000000 fail ^ ^ ^ ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFHJKLMNPRSDEFHJKLMNPRSTUV SIDE 111111111111111222222222222222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 1 step 75 000000000000000000000101000000 fail ^ ^ ^ ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFHJKLMNPRSDEFHJKLMNPRSTUV SIDE 111111111111111222222222222222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 10 step 76 000000000000000000000110000000 fail ^ ^ ^ ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFHJKLMNPRSDEFHJKLMNPRSTUV SIDE 111111111111111222222222222222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 1 step 77 000000000000000000000111000000 fail ^ ^ ^ ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFHJKLMNPRSDEFHJKLMNPRSTUV SIDE 111111111111111222222222222222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 1000 step 78 000000000000000000001000000000 fail ^ ^ ^ ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFHJKLMNPRSDEFHJKLMNPRSTUV SIDE 111111111111111222222222222222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 1 step 79 000000000000000000001001000000 fail ^ ^ ^ ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFHJKLMNPRSDEFHJKLMNPRSTUV SIDE 111111111111111222222222222222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 10 step 80 000000000000000000001010000000 fail ^ ^ ^ ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFHJKLMNPRSDEFHJKLMNPRSTUV SIDE 111111111111111222222222222222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 1 step 81 000000000000000000001011000000 fail ^ ^ ^ ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFHJKLMNPRSDEFHJKLMNPRSTUV SIDE 111111111111111222222222222222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 100 step 82 000000000000000000001100000000 fail ^ ^ ^ ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFHJKLMNPRSDEFHJKLMNPRSTUV SIDE 111111111111111222222222222222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 1 step 83 000000000000000000001101000000 fail ^ ^ ^ ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFHJKLMNPRSDEFHJKLMNPRSTUV SIDE 111111111111111222222222222222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 10 step 84 000000000000000000001110000000 fail ^ ^ ^ ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFHJKLMNPRSDEFHJKLMNPRSTUV SIDE 111111111111111222222222222222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 1 step 85 000000000000000000001111000000 fail ^ ^ ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFHJKLMNPRSDEFHJKLMNPRSTUV SIDE 111111111111111222222222222222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 0000 step 86 000000000000000000000000000000 fail ^ ^ ^ ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFHJKLMNPRSDEFHJKLMNPRSTUV SIDE 111111111111111222222222222222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: step 87 000000000000000000000000000000 fail ^ ^ ^ ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFHJKLMNPRSDEFHJKLMNPRSTUV SIDE 111111111111111222222222222222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 1 step 88 000000000000000000000000000010 fail ^ ^ ^ ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFHJKLMNPRSDEFHJKLMNPRSTUV SIDE 111111111111111222222222222222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 10 step 89 000000000000000000000000000100 fail ^ ^ ^ ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFHJKLMNPRSDEFHJKLMNPRSTUV SIDE 111111111111111222222222222222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 1 step 90 000000000000000000000000000110 fail ^ ^ ^ ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFHJKLMNPRSDEFHJKLMNPRSTUV SIDE 111111111111111222222222222222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 100 step 91 000000000000000000000000001000 fail ^ ^ ^ ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFHJKLMNPRSDEFHJKLMNPRSTUV SIDE 111111111111111222222222222222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 1 step 92 000000000000000000000000001010 fail ^ ^ ^ ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFHJKLMNPRSDEFHJKLMNPRSTUV SIDE 111111111111111222222222222222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 10 step 93 000000000000000000000000001100 fail ^ ^ ^ ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFHJKLMNPRSDEFHJKLMNPRSTUV SIDE 111111111111111222222222222222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 1 step 94 000000000000000000000000001110 fail ^ ^ ^ ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFHJKLMNPRSDEFHJKLMNPRSTUV SIDE 111111111111111222222222222222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 1000 step 95 000000000000000000000000010000 fail ^ ^ ^ ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFHJKLMNPRSDEFHJKLMNPRSTUV SIDE 111111111111111222222222222222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 1 step 96 000000000000000000000000010010 fail ^ ^ ^ ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFHJKLMNPRSDEFHJKLMNPRSTUV SIDE 111111111111111222222222222222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 10 step 97 000000000000000000000000010100 fail ^ ^ ^ ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFHJKLMNPRSDEFHJKLMNPRSTUV SIDE 111111111111111222222222222222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 1 step 98 000000000000000000000000010110 fail ^ ^ ^ ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFHJKLMNPRSDEFHJKLMNPRSTUV SIDE 111111111111111222222222222222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 100 step 99 000000000000000000000000011000 fail ^ ^ ^ ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFHJKLMNPRSDEFHJKLMNPRSTUV SIDE 111111111111111222222222222222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 1 step 100 000000000000000000000000011010 fail ^ ^ ^ ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFHJKLMNPRSDEFHJKLMNPRSTUV SIDE 111111111111111222222222222222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 10 step 101 000000000000000000000000011100 fail ^ ^ ^ ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFHJKLMNPRSDEFHJKLMNPRSTUV SIDE 111111111111111222222222222222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 1 step 102 000000000000000000000000011110 fail ^ ^ ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFHJKLMNPRSDEFHJKLMNPRSTUV SIDE 111111111111111222222222222222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 0000 step 103 000000000000000000000000000000 fail ^ ^ ^ ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFHJKLMNPRSDEFHJKLMNPRSTUV SIDE 111111111111111222222222222222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: step 104 000000000000000000000000000000 fail ^ ^ ^ ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFHJKLMNPRSDEFHJKLMNPRSTUV SIDE 111111111111111222222222222222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 1111 1111 1111 1111 111111111 step 105 111101111011110111101111111110 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFHJKLMNPRSDEFHJKLMNPRSTUV SIDE 111111111111111222222222222222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 0000 0 step 106 000001111011110111101111011110 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFHJKLMNPRSDEFHJKLMNPRSTUV SIDE 111111111111111222222222222222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 1 step 107 000101111011110111101111011110 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFHJKLMNPRSDEFHJKLMNPRSTUV SIDE 111111111111111222222222222222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 10 step 108 001001111011110111101111011110 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFHJKLMNPRSDEFHJKLMNPRSTUV SIDE 111111111111111222222222222222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 1 step 109 001101111011110111101111011110 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFHJKLMNPRSDEFHJKLMNPRSTUV SIDE 111111111111111222222222222222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 100 step 110 010001111011110111101111011110 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFHJKLMNPRSDEFHJKLMNPRSTUV SIDE 111111111111111222222222222222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 1 step 111 010101111011110111101111011110 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFHJKLMNPRSDEFHJKLMNPRSTUV SIDE 111111111111111222222222222222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 10 step 112 011001111011110111101111011110 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFHJKLMNPRSDEFHJKLMNPRSTUV SIDE 111111111111111222222222222222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 1 step 113 011101111011110111101111011110 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFHJKLMNPRSDEFHJKLMNPRSTUV SIDE 111111111111111222222222222222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 1000 step 114 100001111011110111101111011110 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFHJKLMNPRSDEFHJKLMNPRSTUV SIDE 111111111111111222222222222222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 1 step 115 100101111011110111101111011110 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFHJKLMNPRSDEFHJKLMNPRSTUV SIDE 111111111111111222222222222222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 10 step 116 101001111011110111101111011110 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFHJKLMNPRSDEFHJKLMNPRSTUV SIDE 111111111111111222222222222222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 1 step 117 101101111011110111101111011110 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFHJKLMNPRSDEFHJKLMNPRSTUV SIDE 111111111111111222222222222222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 100 step 118 110001111011110111101111011110 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFHJKLMNPRSDEFHJKLMNPRSTUV SIDE 111111111111111222222222222222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 1 step 119 110101111011110111101111011110 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFHJKLMNPRSDEFHJKLMNPRSTUV SIDE 111111111111111222222222222222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 10 step 120 111001111011110111101111011110 fail ^ step 121 111101111011110111101111011110 SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFHJKLMNPRSDEFHJKLMNPRSTUV SIDE 111111111111111222222222222222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 0000 step 122 111100000011110111101111011110 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFHJKLMNPRSDEFHJKLMNPRSTUV SIDE 111111111111111222222222222222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 1 step 123 111100001011110111101111011110 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFHJKLMNPRSDEFHJKLMNPRSTUV SIDE 111111111111111222222222222222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 10 step 124 111100010011110111101111011110 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFHJKLMNPRSDEFHJKLMNPRSTUV SIDE 111111111111111222222222222222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 1 step 125 111100011011110111101111011110 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFHJKLMNPRSDEFHJKLMNPRSTUV SIDE 111111111111111222222222222222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 100 step 126 111100100011110111101111011110 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFHJKLMNPRSDEFHJKLMNPRSTUV SIDE 111111111111111222222222222222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 1 step 127 111100101011110111101111011110 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFHJKLMNPRSDEFHJKLMNPRSTUV SIDE 111111111111111222222222222222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 10 step 128 111100110011110111101111011110 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFHJKLMNPRSDEFHJKLMNPRSTUV SIDE 111111111111111222222222222222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 1 step 129 111100111011110111101111011110 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFHJKLMNPRSDEFHJKLMNPRSTUV SIDE 111111111111111222222222222222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 1000 step 130 111101000011110111101111011110 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFHJKLMNPRSDEFHJKLMNPRSTUV SIDE 111111111111111222222222222222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 1 step 131 111101001011110111101111011110 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFHJKLMNPRSDEFHJKLMNPRSTUV SIDE 111111111111111222222222222222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 10 step 132 111101010011110111101111011110 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFHJKLMNPRSDEFHJKLMNPRSTUV SIDE 111111111111111222222222222222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 1 step 133 111101011011110111101111011110 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFHJKLMNPRSDEFHJKLMNPRSTUV SIDE 111111111111111222222222222222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 100 step 134 111101100011110111101111011110 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFHJKLMNPRSDEFHJKLMNPRSTUV SIDE 111111111111111222222222222222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 1 step 135 111101101011110111101111011110 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFHJKLMNPRSDEFHJKLMNPRSTUV SIDE 111111111111111222222222222222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 10 step 136 111101110011110111101111011110 fail ^ step 137 111101111011110111101111011110 SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFHJKLMNPRSDEFHJKLMNPRSTUV SIDE 111111111111111222222222222222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 0000 step 138 111101111000000111101111011110 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFHJKLMNPRSDEFHJKLMNPRSTUV SIDE 111111111111111222222222222222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 1 step 139 111101111000010111101111011110 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFHJKLMNPRSDEFHJKLMNPRSTUV SIDE 111111111111111222222222222222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 10 step 140 111101111000100111101111011110 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFHJKLMNPRSDEFHJKLMNPRSTUV SIDE 111111111111111222222222222222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 1 step 141 111101111000110111101111011110 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFHJKLMNPRSDEFHJKLMNPRSTUV SIDE 111111111111111222222222222222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 100 step 142 111101111001000111101111011110 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFHJKLMNPRSDEFHJKLMNPRSTUV SIDE 111111111111111222222222222222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 1 step 143 111101111001010111101111011110 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFHJKLMNPRSDEFHJKLMNPRSTUV SIDE 111111111111111222222222222222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 10 step 144 111101111001100111101111011110 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFHJKLMNPRSDEFHJKLMNPRSTUV SIDE 111111111111111222222222222222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 1 step 145 111101111001110111101111011110 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFHJKLMNPRSDEFHJKLMNPRSTUV SIDE 111111111111111222222222222222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 1000 step 146 111101111010000111101111011110 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFHJKLMNPRSDEFHJKLMNPRSTUV SIDE 111111111111111222222222222222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 1 step 147 111101111010010111101111011110 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFHJKLMNPRSDEFHJKLMNPRSTUV SIDE 111111111111111222222222222222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 10 step 148 111101111010100111101111011110 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFHJKLMNPRSDEFHJKLMNPRSTUV SIDE 111111111111111222222222222222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 1 step 149 111101111010110111101111011110 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFHJKLMNPRSDEFHJKLMNPRSTUV SIDE 111111111111111222222222222222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 100 step 150 111101111011000111101111011110 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFHJKLMNPRSDEFHJKLMNPRSTUV SIDE 111111111111111222222222222222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 1 step 151 111101111011010111101111011110 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFHJKLMNPRSDEFHJKLMNPRSTUV SIDE 111111111111111222222222222222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 10 step 152 111101111011100111101111011110 fail ^ step 153 111101111011110111101111011110 SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFHJKLMNPRSDEFHJKLMNPRSTUV SIDE 111111111111111222222222222222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 0000 step 154 111101111011110000001111011110 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFHJKLMNPRSDEFHJKLMNPRSTUV SIDE 111111111111111222222222222222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 1 step 155 111101111011110000101111011110 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFHJKLMNPRSDEFHJKLMNPRSTUV SIDE 111111111111111222222222222222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 10 step 156 111101111011110001001111011110 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFHJKLMNPRSDEFHJKLMNPRSTUV SIDE 111111111111111222222222222222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 1 step 157 111101111011110001101111011110 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFHJKLMNPRSDEFHJKLMNPRSTUV SIDE 111111111111111222222222222222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 100 step 158 111101111011110010001111011110 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFHJKLMNPRSDEFHJKLMNPRSTUV SIDE 111111111111111222222222222222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 1 step 159 111101111011110010101111011110 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFHJKLMNPRSDEFHJKLMNPRSTUV SIDE 111111111111111222222222222222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 10 step 160 111101111011110011001111011110 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFHJKLMNPRSDEFHJKLMNPRSTUV SIDE 111111111111111222222222222222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 1 step 161 111101111011110011101111011110 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFHJKLMNPRSDEFHJKLMNPRSTUV SIDE 111111111111111222222222222222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 1000 step 162 111101111011110100001111011110 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFHJKLMNPRSDEFHJKLMNPRSTUV SIDE 111111111111111222222222222222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 1 step 163 111101111011110100101111011110 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFHJKLMNPRSDEFHJKLMNPRSTUV SIDE 111111111111111222222222222222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 10 step 164 111101111011110101001111011110 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFHJKLMNPRSDEFHJKLMNPRSTUV SIDE 111111111111111222222222222222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 1 step 165 111101111011110101101111011110 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFHJKLMNPRSDEFHJKLMNPRSTUV SIDE 111111111111111222222222222222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 100 step 166 111101111011110110001111011110 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFHJKLMNPRSDEFHJKLMNPRSTUV SIDE 111111111111111222222222222222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 1 step 167 111101111011110110101111011110 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFHJKLMNPRSDEFHJKLMNPRSTUV SIDE 111111111111111222222222222222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 10 step 168 111101111011110111001111011110 fail ^ step 169 111101111011110111101111011110 SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFHJKLMNPRSDEFHJKLMNPRSTUV SIDE 111111111111111222222222222222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 0000 step 170 111101111011110111100000011110 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFHJKLMNPRSDEFHJKLMNPRSTUV SIDE 111111111111111222222222222222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 1 step 171 111101111011110111100001011110 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFHJKLMNPRSDEFHJKLMNPRSTUV SIDE 111111111111111222222222222222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 10 step 172 111101111011110111100010011110 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFHJKLMNPRSDEFHJKLMNPRSTUV SIDE 111111111111111222222222222222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 1 step 173 111101111011110111100011011110 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFHJKLMNPRSDEFHJKLMNPRSTUV SIDE 111111111111111222222222222222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 100 step 174 111101111011110111100100011110 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFHJKLMNPRSDEFHJKLMNPRSTUV SIDE 111111111111111222222222222222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 1 step 175 111101111011110111100101011110 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFHJKLMNPRSDEFHJKLMNPRSTUV SIDE 111111111111111222222222222222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 10 step 176 111101111011110111100110011110 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFHJKLMNPRSDEFHJKLMNPRSTUV SIDE 111111111111111222222222222222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 1 step 177 111101111011110111100111011110 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFHJKLMNPRSDEFHJKLMNPRSTUV SIDE 111111111111111222222222222222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 1000 step 178 111101111011110111101000011110 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFHJKLMNPRSDEFHJKLMNPRSTUV SIDE 111111111111111222222222222222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 1 step 179 111101111011110111101001011110 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFHJKLMNPRSDEFHJKLMNPRSTUV SIDE 111111111111111222222222222222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 10 step 180 111101111011110111101010011110 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFHJKLMNPRSDEFHJKLMNPRSTUV SIDE 111111111111111222222222222222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 1 step 181 111101111011110111101011011110 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFHJKLMNPRSDEFHJKLMNPRSTUV SIDE 111111111111111222222222222222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 100 step 182 111101111011110111101100011110 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFHJKLMNPRSDEFHJKLMNPRSTUV SIDE 111111111111111222222222222222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 1 step 183 111101111011110111101101011110 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFHJKLMNPRSDEFHJKLMNPRSTUV SIDE 111111111111111222222222222222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 10 step 184 111101111011110111101110011110 fail ^ step 185 111101111011110111101111011110 SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFHJKLMNPRSDEFHJKLMNPRSTUV SIDE 111111111111111222222222222222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 0000 step 186 111101111011110111101111000000 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFHJKLMNPRSDEFHJKLMNPRSTUV SIDE 111111111111111222222222222222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 1 step 187 111101111011110111101111000010 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFHJKLMNPRSDEFHJKLMNPRSTUV SIDE 111111111111111222222222222222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 10 step 188 111101111011110111101111000100 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFHJKLMNPRSDEFHJKLMNPRSTUV SIDE 111111111111111222222222222222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 1 step 189 111101111011110111101111000110 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFHJKLMNPRSDEFHJKLMNPRSTUV SIDE 111111111111111222222222222222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 100 step 190 111101111011110111101111001000 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFHJKLMNPRSDEFHJKLMNPRSTUV SIDE 111111111111111222222222222222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 1 step 191 111101111011110111101111001010 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFHJKLMNPRSDEFHJKLMNPRSTUV SIDE 111111111111111222222222222222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 10 step 192 111101111011110111101111001100 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFHJKLMNPRSDEFHJKLMNPRSTUV SIDE 111111111111111222222222222222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 1 step 193 111101111011110111101111001110 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFHJKLMNPRSDEFHJKLMNPRSTUV SIDE 111111111111111222222222222222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 1000 step 194 111101111011110111101111010000 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFHJKLMNPRSDEFHJKLMNPRSTUV SIDE 111111111111111222222222222222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 1 step 195 111101111011110111101111010010 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFHJKLMNPRSDEFHJKLMNPRSTUV SIDE 111111111111111222222222222222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 10 step 196 111101111011110111101111010100 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFHJKLMNPRSDEFHJKLMNPRSTUV SIDE 111111111111111222222222222222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 1 step 197 111101111011110111101111010110 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFHJKLMNPRSDEFHJKLMNPRSTUV SIDE 111111111111111222222222222222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 100 step 198 111101111011110111101111011000 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFHJKLMNPRSDEFHJKLMNPRSTUV SIDE 111111111111111222222222222222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 1 step 199 111101111011110111101111011010 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFHJKLMNPRSDEFHJKLMNPRSTUV SIDE 111111111111111222222222222222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 10 step 200 111101111011110111101111011100 fail ^ step 201 111101111011110111101111011110 step 202 111101111011110111101111011110 test 3: *** FAIL *************************** 191 steps failed SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFHJKLMNPRSDEFHJKLMNPRSTUV SIDE 111111111111111222222222222222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO this fail O O O O O O all fails O O O O O O was hi 111111111111111111111111111111 rising ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ falling vvvvvvvvvvvvvvvvvvvvvvvvvvvvvv was lo 000000000000000000000000000000 total fails 3, total passes 0 space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C toggle comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFHJKLMNPRSDEFHJKLMNPRSTUV SIDE 111111111111111222222222222222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 0000 0000 0000 0000 0000 0000 step 1 000000000000000000000000000000 fail ^ ^ ^ ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFHJKLMNPRSDEFHJKLMNPRSTUV SIDE 111111111111111222222222222222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: step 2 000000000000000000000000000000 fail ^ ^ ^ ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFHJKLMNPRSDEFHJKLMNPRSTUV SIDE 111111111111111222222222222222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 1 step 3 000100000000000000000000000000 fail ^ ^ ^ ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFHJKLMNPRSDEFHJKLMNPRSTUV SIDE 111111111111111222222222222222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 10 step 4 001000000000000000000000000000 fail ^ ^ ^ ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFHJKLMNPRSDEFHJKLMNPRSTUV SIDE 111111111111111222222222222222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 1 step 5 001100000000000000000000000000 fail ^ ^ ^ ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFHJKLMNPRSDEFHJKLMNPRSTUV SIDE 111111111111111222222222222222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 100 step 6 010000000000000000000000000000 fail ^ ^ ^ ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFHJKLMNPRSDEFHJKLMNPRSTUV SIDE 111111111111111222222222222222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 1 step 7 010100000000000000000000000000 fail ^ ^ ^ ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFHJKLMNPRSDEFHJKLMNPRSTUV SIDE 111111111111111222222222222222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 10 step 8 011000000000000000000000000000 fail ^ ^ ^ ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFHJKLMNPRSDEFHJKLMNPRSTUV SIDE 111111111111111222222222222222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 1 step 9 011100000000000000000000000000 fail ^ ^ ^ ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFHJKLMNPRSDEFHJKLMNPRSTUV SIDE 111111111111111222222222222222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 1000 step 10 100000000000000000000000000000 fail ^ ^ ^ ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFHJKLMNPRSDEFHJKLMNPRSTUV SIDE 111111111111111222222222222222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 1 step 11 100100000000000000000000000000 fail ^ ^ ^ ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFHJKLMNPRSDEFHJKLMNPRSTUV SIDE 111111111111111222222222222222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 10 step 12 101000000000000000000000000000 fail ^ ^ ^ ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFHJKLMNPRSDEFHJKLMNPRSTUV SIDE 111111111111111222222222222222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 1 step 13 101100000000000000000000000000 fail ^ ^ ^ ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFHJKLMNPRSDEFHJKLMNPRSTUV SIDE 111111111111111222222222222222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 100 step 14 110000000000000000000000000000 fail ^ ^ ^ ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFHJKLMNPRSDEFHJKLMNPRSTUV SIDE 111111111111111222222222222222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 1 step 15 110100000000000000000000000000 fail ^ ^ ^ ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFHJKLMNPRSDEFHJKLMNPRSTUV SIDE 111111111111111222222222222222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 10 step 16 111000000000000000000000000000 fail ^ ^ ^ ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFHJKLMNPRSDEFHJKLMNPRSTUV SIDE 111111111111111222222222222222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 1 step 17 111100000000000000000000000000 fail ^ ^ ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFHJKLMNPRSDEFHJKLMNPRSTUV SIDE 111111111111111222222222222222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 0000 step 18 000000000000000000000000000000 fail ^ ^ ^ ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFHJKLMNPRSDEFHJKLMNPRSTUV SIDE 111111111111111222222222222222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: step 19 000000000000000000000000000000 fail ^ ^ ^ ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFHJKLMNPRSDEFHJKLMNPRSTUV SIDE 111111111111111222222222222222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 1 step 20 000000001000000000000000000000 fail ^ ^ ^ ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFHJKLMNPRSDEFHJKLMNPRSTUV SIDE 111111111111111222222222222222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 10 step 21 000000010000000000000000000000 fail ^ ^ ^ ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFHJKLMNPRSDEFHJKLMNPRSTUV SIDE 111111111111111222222222222222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 1 step 22 000000011000000000000000000000 fail ^ ^ ^ ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFHJKLMNPRSDEFHJKLMNPRSTUV SIDE 111111111111111222222222222222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 100 step 23 000000100000000000000000000000 fail ^ ^ ^ ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFHJKLMNPRSDEFHJKLMNPRSTUV SIDE 111111111111111222222222222222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 1 step 24 000000101000000000000000000000 fail ^ ^ ^ ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFHJKLMNPRSDEFHJKLMNPRSTUV SIDE 111111111111111222222222222222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 10 step 25 000000110000000000000000000000 fail ^ ^ ^ ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFHJKLMNPRSDEFHJKLMNPRSTUV SIDE 111111111111111222222222222222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 1 step 26 000000111000000000000000000000 fail ^ ^ ^ ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFHJKLMNPRSDEFHJKLMNPRSTUV SIDE 111111111111111222222222222222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 1000 step 27 000001000000000000000000000000 fail ^ ^ ^ ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFHJKLMNPRSDEFHJKLMNPRSTUV SIDE 111111111111111222222222222222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 1 step 28 000001001000000000000000000000 fail ^ ^ ^ ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFHJKLMNPRSDEFHJKLMNPRSTUV SIDE 111111111111111222222222222222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 10 step 29 000001010000000000000000000000 fail ^ ^ ^ ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFHJKLMNPRSDEFHJKLMNPRSTUV SIDE 111111111111111222222222222222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 1 step 30 000001011000000000000000000000 fail ^ ^ ^ ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFHJKLMNPRSDEFHJKLMNPRSTUV SIDE 111111111111111222222222222222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 100 step 31 000001100000000000000000000000 fail ^ ^ ^ ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFHJKLMNPRSDEFHJKLMNPRSTUV SIDE 111111111111111222222222222222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 1 step 32 000001101000000000000000000000 fail ^ ^ ^ ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFHJKLMNPRSDEFHJKLMNPRSTUV SIDE 111111111111111222222222222222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 10 step 33 000001110000000000000000000000 fail ^ ^ ^ ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFHJKLMNPRSDEFHJKLMNPRSTUV SIDE 111111111111111222222222222222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 1 step 34 000001111000000000000000000000 fail ^ ^ ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFHJKLMNPRSDEFHJKLMNPRSTUV SIDE 111111111111111222222222222222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 0000 step 35 000000000000000000000000000000 fail ^ ^ ^ ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFHJKLMNPRSDEFHJKLMNPRSTUV SIDE 111111111111111222222222222222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: step 36 000000000000000000000000000000 fail ^ ^ ^ ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFHJKLMNPRSDEFHJKLMNPRSTUV SIDE 111111111111111222222222222222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 1 step 37 000000000000010000000000000000 fail ^ ^ ^ ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFHJKLMNPRSDEFHJKLMNPRSTUV SIDE 111111111111111222222222222222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 10 step 38 000000000000100000000000000000 fail ^ ^ ^ ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFHJKLMNPRSDEFHJKLMNPRSTUV SIDE 111111111111111222222222222222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 1 step 39 000000000000110000000000000000 fail ^ ^ ^ ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFHJKLMNPRSDEFHJKLMNPRSTUV SIDE 111111111111111222222222222222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 100 step 40 000000000001000000000000000000 fail ^ ^ ^ ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFHJKLMNPRSDEFHJKLMNPRSTUV SIDE 111111111111111222222222222222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 1 step 41 000000000001010000000000000000 fail ^ ^ ^ ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFHJKLMNPRSDEFHJKLMNPRSTUV SIDE 111111111111111222222222222222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 10 step 42 000000000001100000000000000000 fail ^ ^ ^ ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFHJKLMNPRSDEFHJKLMNPRSTUV SIDE 111111111111111222222222222222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 1 step 43 000000000001110000000000000000 fail ^ ^ ^ ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFHJKLMNPRSDEFHJKLMNPRSTUV SIDE 111111111111111222222222222222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 1000 step 44 000000000010000000000000000000 fail ^ ^ ^ ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFHJKLMNPRSDEFHJKLMNPRSTUV SIDE 111111111111111222222222222222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 1 step 45 000000000010010000000000000000 fail ^ ^ ^ ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFHJKLMNPRSDEFHJKLMNPRSTUV SIDE 111111111111111222222222222222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 10 step 46 000000000010100000000000000000 fail ^ ^ ^ ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFHJKLMNPRSDEFHJKLMNPRSTUV SIDE 111111111111111222222222222222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 1 step 47 000000000010110000000000000000 fail ^ ^ ^ ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFHJKLMNPRSDEFHJKLMNPRSTUV SIDE 111111111111111222222222222222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 100 step 48 000000000011000000000000000000 fail ^ ^ ^ ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFHJKLMNPRSDEFHJKLMNPRSTUV SIDE 111111111111111222222222222222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 1 step 49 000000000011010000000000000000 fail ^ ^ ^ ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFHJKLMNPRSDEFHJKLMNPRSTUV SIDE 111111111111111222222222222222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 10 step 50 000000000011100000000000000000 fail ^ ^ ^ ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFHJKLMNPRSDEFHJKLMNPRSTUV SIDE 111111111111111222222222222222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 1 step 51 000000000011110000000000000000 fail ^ ^ ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFHJKLMNPRSDEFHJKLMNPRSTUV SIDE 111111111111111222222222222222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 0000 step 52 000000000000000000000000000000 fail ^ ^ ^ ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFHJKLMNPRSDEFHJKLMNPRSTUV SIDE 111111111111111222222222222222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: step 53 000000000000000000000000000000 fail ^ ^ ^ ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFHJKLMNPRSDEFHJKLMNPRSTUV SIDE 111111111111111222222222222222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 1 step 54 000000000000000000100000000000 fail ^ ^ ^ ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFHJKLMNPRSDEFHJKLMNPRSTUV SIDE 111111111111111222222222222222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 10 step 55 000000000000000001000000000000 fail ^ ^ ^ ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFHJKLMNPRSDEFHJKLMNPRSTUV SIDE 111111111111111222222222222222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 1 step 56 000000000000000001100000000000 fail ^ ^ ^ ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFHJKLMNPRSDEFHJKLMNPRSTUV SIDE 111111111111111222222222222222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 100 step 57 000000000000000010000000000000 fail ^ ^ ^ ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFHJKLMNPRSDEFHJKLMNPRSTUV SIDE 111111111111111222222222222222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 1 step 58 000000000000000010100000000000 fail ^ ^ ^ ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFHJKLMNPRSDEFHJKLMNPRSTUV SIDE 111111111111111222222222222222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 10 step 59 000000000000000011000000000000 fail ^ ^ ^ ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFHJKLMNPRSDEFHJKLMNPRSTUV SIDE 111111111111111222222222222222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 1 step 60 000000000000000011100000000000 fail ^ ^ ^ ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFHJKLMNPRSDEFHJKLMNPRSTUV SIDE 111111111111111222222222222222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 1000 step 61 000000000000000100000000000000 fail ^ ^ ^ ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFHJKLMNPRSDEFHJKLMNPRSTUV SIDE 111111111111111222222222222222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 1 step 62 000000000000000100100000000000 fail ^ ^ ^ ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFHJKLMNPRSDEFHJKLMNPRSTUV SIDE 111111111111111222222222222222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 10 step 63 000000000000000101000000000000 fail ^ ^ ^ ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFHJKLMNPRSDEFHJKLMNPRSTUV SIDE 111111111111111222222222222222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 1 step 64 000000000000000101100000000000 fail ^ ^ ^ ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFHJKLMNPRSDEFHJKLMNPRSTUV SIDE 111111111111111222222222222222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 100 step 65 000000000000000110000000000000 fail ^ ^ ^ ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFHJKLMNPRSDEFHJKLMNPRSTUV SIDE 111111111111111222222222222222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 1 step 66 000000000000000110100000000000 fail ^ ^ ^ ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFHJKLMNPRSDEFHJKLMNPRSTUV SIDE 111111111111111222222222222222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 10 step 67 000000000000000111000000000000 fail ^ ^ ^ ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFHJKLMNPRSDEFHJKLMNPRSTUV SIDE 111111111111111222222222222222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 1 step 68 000000000000000111100000000000 fail ^ ^ ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFHJKLMNPRSDEFHJKLMNPRSTUV SIDE 111111111111111222222222222222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 0000 step 69 000000000000000000000000000000 fail ^ ^ ^ ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFHJKLMNPRSDEFHJKLMNPRSTUV SIDE 111111111111111222222222222222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: step 70 000000000000000000000000000000 fail ^ ^ ^ ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFHJKLMNPRSDEFHJKLMNPRSTUV SIDE 111111111111111222222222222222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 1 step 71 000000000000000000000001000000 fail ^ ^ ^ ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFHJKLMNPRSDEFHJKLMNPRSTUV SIDE 111111111111111222222222222222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 10 step 72 000000000000000000000010000000 fail ^ ^ ^ ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFHJKLMNPRSDEFHJKLMNPRSTUV SIDE 111111111111111222222222222222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 1 step 73 000000000000000000000011000000 fail ^ ^ ^ ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFHJKLMNPRSDEFHJKLMNPRSTUV SIDE 111111111111111222222222222222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 100 step 74 000000000000000000000100000000 fail ^ ^ ^ ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFHJKLMNPRSDEFHJKLMNPRSTUV SIDE 111111111111111222222222222222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 1 step 75 000000000000000000000101000000 fail ^ ^ ^ ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFHJKLMNPRSDEFHJKLMNPRSTUV SIDE 111111111111111222222222222222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 10 step 76 000000000000000000000110000000 fail ^ ^ ^ ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFHJKLMNPRSDEFHJKLMNPRSTUV SIDE 111111111111111222222222222222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 1 step 77 000000000000000000000111000000 fail ^ ^ ^ ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFHJKLMNPRSDEFHJKLMNPRSTUV SIDE 111111111111111222222222222222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 1000 step 78 000000000000000000001000000000 fail ^ ^ ^ ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFHJKLMNPRSDEFHJKLMNPRSTUV SIDE 111111111111111222222222222222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 1 step 79 000000000000000000001001000000 fail ^ ^ ^ ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFHJKLMNPRSDEFHJKLMNPRSTUV SIDE 111111111111111222222222222222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 10 step 80 000000000000000000001010000000 fail ^ ^ ^ ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFHJKLMNPRSDEFHJKLMNPRSTUV SIDE 111111111111111222222222222222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 1 step 81 000000000000000000001011000000 fail ^ ^ ^ ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFHJKLMNPRSDEFHJKLMNPRSTUV SIDE 111111111111111222222222222222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 100 step 82 000000000000000000001100000000 fail ^ ^ ^ ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFHJKLMNPRSDEFHJKLMNPRSTUV SIDE 111111111111111222222222222222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 1 step 83 000000000000000000001101000000 fail ^ ^ ^ ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFHJKLMNPRSDEFHJKLMNPRSTUV SIDE 111111111111111222222222222222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 10 step 84 000000000000000000001110000000 fail ^ ^ ^ ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFHJKLMNPRSDEFHJKLMNPRSTUV SIDE 111111111111111222222222222222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 1 step 85 000000000000000000001111000000 fail ^ ^ ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFHJKLMNPRSDEFHJKLMNPRSTUV SIDE 111111111111111222222222222222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 0000 step 86 000000000000000000000000000000 fail ^ ^ ^ ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFHJKLMNPRSDEFHJKLMNPRSTUV SIDE 111111111111111222222222222222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: step 87 000000000000000000000000000000 fail ^ ^ ^ ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFHJKLMNPRSDEFHJKLMNPRSTUV SIDE 111111111111111222222222222222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 1 step 88 000000000000000000000000000010 fail ^ ^ ^ ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFHJKLMNPRSDEFHJKLMNPRSTUV SIDE 111111111111111222222222222222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 10 step 89 000000000000000000000000000100 fail ^ ^ ^ ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFHJKLMNPRSDEFHJKLMNPRSTUV SIDE 111111111111111222222222222222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 1 step 90 000000000000000000000000000110 fail ^ ^ ^ ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFHJKLMNPRSDEFHJKLMNPRSTUV SIDE 111111111111111222222222222222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 100 step 91 000000000000000000000000001000 fail ^ ^ ^ ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFHJKLMNPRSDEFHJKLMNPRSTUV SIDE 111111111111111222222222222222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 1 step 92 000000000000000000000000001010 fail ^ ^ ^ ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFHJKLMNPRSDEFHJKLMNPRSTUV SIDE 111111111111111222222222222222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 10 step 93 000000000000000000000000001100 fail ^ ^ ^ ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFHJKLMNPRSDEFHJKLMNPRSTUV SIDE 111111111111111222222222222222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 1 step 94 000000000000000000000000001110 fail ^ ^ ^ ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFHJKLMNPRSDEFHJKLMNPRSTUV SIDE 111111111111111222222222222222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 1000 step 95 000000000000000000000000010000 fail ^ ^ ^ ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFHJKLMNPRSDEFHJKLMNPRSTUV SIDE 111111111111111222222222222222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 1 step 96 000000000000000000000000010010 fail ^ ^ ^ ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFHJKLMNPRSDEFHJKLMNPRSTUV SIDE 111111111111111222222222222222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 10 step 97 000000000000000000000000010100 fail ^ ^ ^ ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFHJKLMNPRSDEFHJKLMNPRSTUV SIDE 111111111111111222222222222222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 1 step 98 000000000000000000000000010110 fail ^ ^ ^ ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFHJKLMNPRSDEFHJKLMNPRSTUV SIDE 111111111111111222222222222222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 100 step 99 000000000000000000000000011000 fail ^ ^ ^ ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFHJKLMNPRSDEFHJKLMNPRSTUV SIDE 111111111111111222222222222222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 1 step 100 000000000000000000000000011010 fail ^ ^ ^ ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFHJKLMNPRSDEFHJKLMNPRSTUV SIDE 111111111111111222222222222222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 10 step 101 000000000000000000000000011100 fail ^ ^ ^ ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFHJKLMNPRSDEFHJKLMNPRSTUV SIDE 111111111111111222222222222222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 1 step 102 000000000000000000000000011110 fail ^ ^ ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFHJKLMNPRSDEFHJKLMNPRSTUV SIDE 111111111111111222222222222222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 0000 step 103 000000000000000000000000000000 fail ^ ^ ^ ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFHJKLMNPRSDEFHJKLMNPRSTUV SIDE 111111111111111222222222222222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: step 104 000000000000000000000000000000 fail ^ ^ ^ ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFHJKLMNPRSDEFHJKLMNPRSTUV SIDE 111111111111111222222222222222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 1111 1111 1111 1111 111111111 step 105 111101111011110111101111111110 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFHJKLMNPRSDEFHJKLMNPRSTUV SIDE 111111111111111222222222222222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 0000 0 step 106 000001111011110111101111011110 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFHJKLMNPRSDEFHJKLMNPRSTUV SIDE 111111111111111222222222222222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 1 step 107 000101111011110111101111011110 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFHJKLMNPRSDEFHJKLMNPRSTUV SIDE 111111111111111222222222222222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 10 step 108 001001111011110111101111011110 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFHJKLMNPRSDEFHJKLMNPRSTUV SIDE 111111111111111222222222222222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 1 step 109 001101111011110111101111011110 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFHJKLMNPRSDEFHJKLMNPRSTUV SIDE 111111111111111222222222222222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 100 step 110 010001111011110111101111011110 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFHJKLMNPRSDEFHJKLMNPRSTUV SIDE 111111111111111222222222222222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 1 step 111 010101111011110111101111011110 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFHJKLMNPRSDEFHJKLMNPRSTUV SIDE 111111111111111222222222222222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 10 step 112 011001111011110111101111011110 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFHJKLMNPRSDEFHJKLMNPRSTUV SIDE 111111111111111222222222222222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 1 step 113 011101111011110111101111011110 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFHJKLMNPRSDEFHJKLMNPRSTUV SIDE 111111111111111222222222222222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 1000 step 114 100001111011110111101111011110 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFHJKLMNPRSDEFHJKLMNPRSTUV SIDE 111111111111111222222222222222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 1 step 115 100101111011110111101111011110 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFHJKLMNPRSDEFHJKLMNPRSTUV SIDE 111111111111111222222222222222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 10 step 116 101001111011110111101111011110 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFHJKLMNPRSDEFHJKLMNPRSTUV SIDE 111111111111111222222222222222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 1 step 117 101101111011110111101111011110 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFHJKLMNPRSDEFHJKLMNPRSTUV SIDE 111111111111111222222222222222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 100 step 118 110001111011110111101111011110 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFHJKLMNPRSDEFHJKLMNPRSTUV SIDE 111111111111111222222222222222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 1 step 119 110101111011110111101111011110 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFHJKLMNPRSDEFHJKLMNPRSTUV SIDE 111111111111111222222222222222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 10 step 120 111001111011110111101111011110 fail ^ step 121 111101111011110111101111011110 SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFHJKLMNPRSDEFHJKLMNPRSTUV SIDE 111111111111111222222222222222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 0000 step 122 111100000011110111101111011110 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFHJKLMNPRSDEFHJKLMNPRSTUV SIDE 111111111111111222222222222222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 1 step 123 111100001011110111101111011110 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFHJKLMNPRSDEFHJKLMNPRSTUV SIDE 111111111111111222222222222222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 10 step 124 111100010011110111101111011110 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFHJKLMNPRSDEFHJKLMNPRSTUV SIDE 111111111111111222222222222222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 1 step 125 111100011011110111101111011110 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFHJKLMNPRSDEFHJKLMNPRSTUV SIDE 111111111111111222222222222222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 100 step 126 111100100011110111101111011110 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFHJKLMNPRSDEFHJKLMNPRSTUV SIDE 111111111111111222222222222222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 1 step 127 111100101011110111101111011110 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFHJKLMNPRSDEFHJKLMNPRSTUV SIDE 111111111111111222222222222222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 10 step 128 111100110011110111101111011110 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFHJKLMNPRSDEFHJKLMNPRSTUV SIDE 111111111111111222222222222222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 1 step 129 111100111011110111101111011110 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFHJKLMNPRSDEFHJKLMNPRSTUV SIDE 111111111111111222222222222222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 1000 step 130 111101000011110111101111011110 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFHJKLMNPRSDEFHJKLMNPRSTUV SIDE 111111111111111222222222222222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 1 step 131 111101001011110111101111011110 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFHJKLMNPRSDEFHJKLMNPRSTUV SIDE 111111111111111222222222222222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 10 step 132 111101010011110111101111011110 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFHJKLMNPRSDEFHJKLMNPRSTUV SIDE 111111111111111222222222222222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 1 step 133 111101011011110111101111011110 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFHJKLMNPRSDEFHJKLMNPRSTUV SIDE 111111111111111222222222222222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 100 step 134 111101100011110111101111011110 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFHJKLMNPRSDEFHJKLMNPRSTUV SIDE 111111111111111222222222222222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 1 step 135 111101101011110111101111011110 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFHJKLMNPRSDEFHJKLMNPRSTUV SIDE 111111111111111222222222222222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 10 step 136 111101110011110111101111011110 fail ^ step 137 111101111011110111101111011110 SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFHJKLMNPRSDEFHJKLMNPRSTUV SIDE 111111111111111222222222222222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 0000 step 138 111101111000000111101111011110 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFHJKLMNPRSDEFHJKLMNPRSTUV SIDE 111111111111111222222222222222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 1 step 139 111101111000010111101111011110 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFHJKLMNPRSDEFHJKLMNPRSTUV SIDE 111111111111111222222222222222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 10 step 140 111101111000100111101111011110 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFHJKLMNPRSDEFHJKLMNPRSTUV SIDE 111111111111111222222222222222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 1 step 141 111101111000110111101111011110 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFHJKLMNPRSDEFHJKLMNPRSTUV SIDE 111111111111111222222222222222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 100 step 142 111101111001000111101111011110 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFHJKLMNPRSDEFHJKLMNPRSTUV SIDE 111111111111111222222222222222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 1 step 143 111101111001010111101111011110 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFHJKLMNPRSDEFHJKLMNPRSTUV SIDE 111111111111111222222222222222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 10 step 144 111101111001100111101111011110 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFHJKLMNPRSDEFHJKLMNPRSTUV SIDE 111111111111111222222222222222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 1 step 145 111101111001110111101111011110 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFHJKLMNPRSDEFHJKLMNPRSTUV SIDE 111111111111111222222222222222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 1000 step 146 111101111010000111101111011110 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFHJKLMNPRSDEFHJKLMNPRSTUV SIDE 111111111111111222222222222222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 1 step 147 111101111010010111101111011110 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFHJKLMNPRSDEFHJKLMNPRSTUV SIDE 111111111111111222222222222222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 10 step 148 111101111010100111101111011110 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFHJKLMNPRSDEFHJKLMNPRSTUV SIDE 111111111111111222222222222222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 1 step 149 111101111010110111101111011110 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFHJKLMNPRSDEFHJKLMNPRSTUV SIDE 111111111111111222222222222222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 100 step 150 111101111011000111101111011110 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFHJKLMNPRSDEFHJKLMNPRSTUV SIDE 111111111111111222222222222222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 1 step 151 111101111011010111101111011110 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFHJKLMNPRSDEFHJKLMNPRSTUV SIDE 111111111111111222222222222222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 10 step 152 111101111011100111101111011110 fail ^ step 153 111101111011110111101111011110 SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFHJKLMNPRSDEFHJKLMNPRSTUV SIDE 111111111111111222222222222222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 0000 step 154 111101111011110000001111011110 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFHJKLMNPRSDEFHJKLMNPRSTUV SIDE 111111111111111222222222222222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 1 step 155 111101111011110000101111011110 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFHJKLMNPRSDEFHJKLMNPRSTUV SIDE 111111111111111222222222222222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 10 step 156 111101111011110001001111011110 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFHJKLMNPRSDEFHJKLMNPRSTUV SIDE 111111111111111222222222222222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 1 step 157 111101111011110001101111011110 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFHJKLMNPRSDEFHJKLMNPRSTUV SIDE 111111111111111222222222222222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 100 step 158 111101111011110010001111011110 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFHJKLMNPRSDEFHJKLMNPRSTUV SIDE 111111111111111222222222222222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 1 step 159 111101111011110010101111011110 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFHJKLMNPRSDEFHJKLMNPRSTUV SIDE 111111111111111222222222222222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 10 step 160 111101111011110011001111011110 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFHJKLMNPRSDEFHJKLMNPRSTUV SIDE 111111111111111222222222222222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 1 step 161 111101111011110011101111011110 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFHJKLMNPRSDEFHJKLMNPRSTUV SIDE 111111111111111222222222222222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 1000 step 162 111101111011110100001111011110 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFHJKLMNPRSDEFHJKLMNPRSTUV SIDE 111111111111111222222222222222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 1 step 163 111101111011110100101111011110 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFHJKLMNPRSDEFHJKLMNPRSTUV SIDE 111111111111111222222222222222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 10 step 164 111101111011110101001111011110 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFHJKLMNPRSDEFHJKLMNPRSTUV SIDE 111111111111111222222222222222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 1 step 165 111101111011110101101111011110 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFHJKLMNPRSDEFHJKLMNPRSTUV SIDE 111111111111111222222222222222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 100 step 166 111101111011110110001111011110 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFHJKLMNPRSDEFHJKLMNPRSTUV SIDE 111111111111111222222222222222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 1 step 167 111101111011110110101111011110 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFHJKLMNPRSDEFHJKLMNPRSTUV SIDE 111111111111111222222222222222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 10 step 168 111101111011110111001111011110 fail ^ step 169 111101111011110111101111011110 SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFHJKLMNPRSDEFHJKLMNPRSTUV SIDE 111111111111111222222222222222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 0000 step 170 111101111011110111100000011110 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFHJKLMNPRSDEFHJKLMNPRSTUV SIDE 111111111111111222222222222222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 1 step 171 111101111011110111100001011110 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFHJKLMNPRSDEFHJKLMNPRSTUV SIDE 111111111111111222222222222222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 10 step 172 111101111011110111100010011110 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFHJKLMNPRSDEFHJKLMNPRSTUV SIDE 111111111111111222222222222222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 1 step 173 111101111011110111100011011110 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFHJKLMNPRSDEFHJKLMNPRSTUV SIDE 111111111111111222222222222222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 100 step 174 111101111011110111100100011110 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFHJKLMNPRSDEFHJKLMNPRSTUV SIDE 111111111111111222222222222222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 1 step 175 111101111011110111100101011110 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFHJKLMNPRSDEFHJKLMNPRSTUV SIDE 111111111111111222222222222222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 10 step 176 111101111011110111100110011110 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFHJKLMNPRSDEFHJKLMNPRSTUV SIDE 111111111111111222222222222222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 1 step 177 111101111011110111100111011110 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFHJKLMNPRSDEFHJKLMNPRSTUV SIDE 111111111111111222222222222222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 1000 step 178 111101111011110111101000011110 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFHJKLMNPRSDEFHJKLMNPRSTUV SIDE 111111111111111222222222222222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 1 step 179 111101111011110111101001011110 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFHJKLMNPRSDEFHJKLMNPRSTUV SIDE 111111111111111222222222222222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 10 step 180 111101111011110111101010011110 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFHJKLMNPRSDEFHJKLMNPRSTUV SIDE 111111111111111222222222222222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 1 step 181 111101111011110111101011011110 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFHJKLMNPRSDEFHJKLMNPRSTUV SIDE 111111111111111222222222222222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 100 step 182 111101111011110111101100011110 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFHJKLMNPRSDEFHJKLMNPRSTUV SIDE 111111111111111222222222222222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 1 step 183 111101111011110111101101011110 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFHJKLMNPRSDEFHJKLMNPRSTUV SIDE 111111111111111222222222222222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 10 step 184 111101111011110111101110011110 fail ^ step 185 111101111011110111101111011110 SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFHJKLMNPRSDEFHJKLMNPRSTUV SIDE 111111111111111222222222222222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 0000 step 186 111101111011110111101111000000 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFHJKLMNPRSDEFHJKLMNPRSTUV SIDE 111111111111111222222222222222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 1 step 187 111101111011110111101111000010 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFHJKLMNPRSDEFHJKLMNPRSTUV SIDE 111111111111111222222222222222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 10 step 188 111101111011110111101111000100 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFHJKLMNPRSDEFHJKLMNPRSTUV SIDE 111111111111111222222222222222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 1 step 189 111101111011110111101111000110 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFHJKLMNPRSDEFHJKLMNPRSTUV SIDE 111111111111111222222222222222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 100 step 190 111101111011110111101111001000 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFHJKLMNPRSDEFHJKLMNPRSTUV SIDE 111111111111111222222222222222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 1 step 191 111101111011110111101111001010 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFHJKLMNPRSDEFHJKLMNPRSTUV SIDE 111111111111111222222222222222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 10 step 192 111101111011110111101111001100 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFHJKLMNPRSDEFHJKLMNPRSTUV SIDE 111111111111111222222222222222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 1 step 193 111101111011110111101111001110 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFHJKLMNPRSDEFHJKLMNPRSTUV SIDE 111111111111111222222222222222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 1000 step 194 111101111011110111101111010000 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFHJKLMNPRSDEFHJKLMNPRSTUV SIDE 111111111111111222222222222222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 1 step 195 111101111011110111101111010010 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFHJKLMNPRSDEFHJKLMNPRSTUV SIDE 111111111111111222222222222222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 10 step 196 111101111011110111101111010100 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFHJKLMNPRSDEFHJKLMNPRSTUV SIDE 111111111111111222222222222222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 1 step 197 111101111011110111101111010110 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFHJKLMNPRSDEFHJKLMNPRSTUV SIDE 111111111111111222222222222222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 100 step 198 111101111011110111101111011000 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFHJKLMNPRSDEFHJKLMNPRSTUV SIDE 111111111111111222222222222222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 1 step 199 111101111011110111101111011010 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFHJKLMNPRSDEFHJKLMNPRSTUV SIDE 111111111111111222222222222222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 10 step 200 111101111011110111101111011100 fail ^ step 201 111101111011110111101111011110 step 202 111101111011110111101111011110 test 4: *** FAIL *************************** 195 steps failed SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFHJKLMNPRSDEFHJKLMNPRSTUV SIDE 111111111111111222222222222222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO this fail O O O O O O all fails O O O O O O was hi 111111111111111111111111111111 rising ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ falling vvvvvvvvvvvvvvvvvvvvvvvvvvvvvv was lo 000000000000000000000000000000 total fails 4, total passes 0 space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C toggle comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit up to this point: PINS that are always low PINS that are always high space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C toggle comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit failure mode analysis: pin: 5 O AE1 E1-8 SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFHJKLMNPRSDEFHJKLMNPRSTUV SIDE 111111111111111222222222222222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO fails LO: 1111 1111111111111111111111111 fails LO: 0000 0000000000000000000000000 fails HI: fails HI: pin: 10 O AL1 E2-8 SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFHJKLMNPRSDEFHJKLMNPRSTUV SIDE 111111111111111222222222222222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO fails LO: 1111 1111 1111 1111 1111 1111 fails LO: 000000000 00000000000000000000 fails HI: fails HI: pin: 15 O AS1 E3-8 SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFHJKLMNPRSDEFHJKLMNPRSTUV SIDE 111111111111111222222222222222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO fails LO: 1111 1111 1111 1111 1111 1111 fails LO: 00000000000000 000000000000000 fails HI: fails HI: pin: 20 O AJ2 E1-6 SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFHJKLMNPRSDEFHJKLMNPRSTUV SIDE 111111111111111222222222222222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO fails LO: 1111 1111 1111 1111 1111 1111 fails LO: 0000000000000000000 0000000000 fails HI: fails HI: pin: 25 O AP2 E2-6 SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFHJKLMNPRSDEFHJKLMNPRSTUV SIDE 111111111111111222222222222222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO fails LO: 1111 1111 1111 1111 1111 1111 fails LO: 000000000000000000000000 00000 fails HI: 1111 1111 1111 1111 1111 1111 fails HI: 0 0 0 0 0 pin: 30 O AV2 E3-6 SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFHJKLMNPRSDEFHJKLMNPRSTUV SIDE 111111111111111222222222222222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO fails LO: 1111 1111 1111 1111 1111 1111 fails LO: 00000000000000000000000000000 fails HI: fails HI: space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C toggle comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFHJKLMNPRSDEFHJKLMNPRSTUV SIDE 111111111111111222222222222222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 0000 0000 0000 0000 0000 0000 step 1 000000000000000000000000000000 fail ^ ^ ^ ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFHJKLMNPRSDEFHJKLMNPRSTUV SIDE 111111111111111222222222222222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: step 2 000000000000000000000000000000 fail ^ ^ ^ ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFHJKLMNPRSDEFHJKLMNPRSTUV SIDE 111111111111111222222222222222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 1 step 3 000100000000000000000000000000 fail ^ ^ ^ ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFHJKLMNPRSDEFHJKLMNPRSTUV SIDE 111111111111111222222222222222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 10 step 4 001000000000000000000000000000 fail ^ ^ ^ ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFHJKLMNPRSDEFHJKLMNPRSTUV SIDE 111111111111111222222222222222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 1 step 5 001100000000000000000000000000 fail ^ ^ ^ ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFHJKLMNPRSDEFHJKLMNPRSTUV SIDE 111111111111111222222222222222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 100 step 6 010000000000000000000000000000 fail ^ ^ ^ ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFHJKLMNPRSDEFHJKLMNPRSTUV SIDE 111111111111111222222222222222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 1 step 7 010100000000000000000000000000 fail ^ ^ ^ ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFHJKLMNPRSDEFHJKLMNPRSTUV SIDE 111111111111111222222222222222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 10 step 8 011000000000000000000000000000 fail ^ ^ ^ ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFHJKLMNPRSDEFHJKLMNPRSTUV SIDE 111111111111111222222222222222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 1 step 9 011100000000000000000000000000 fail ^ ^ ^ ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFHJKLMNPRSDEFHJKLMNPRSTUV SIDE 111111111111111222222222222222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 1000 step 10 100000000000000000000000000000 fail ^ ^ ^ ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFHJKLMNPRSDEFHJKLMNPRSTUV SIDE 111111111111111222222222222222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 1 step 11 100100000000000000000000000000 fail ^ ^ ^ ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFHJKLMNPRSDEFHJKLMNPRSTUV SIDE 111111111111111222222222222222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 10 step 12 101000000000000000000000000000 fail ^ ^ ^ ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFHJKLMNPRSDEFHJKLMNPRSTUV SIDE 111111111111111222222222222222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 1 step 13 101100000000000000000000000000 fail ^ ^ ^ ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFHJKLMNPRSDEFHJKLMNPRSTUV SIDE 111111111111111222222222222222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 100 step 14 110000000000000000000000000000 fail ^ ^ ^ ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFHJKLMNPRSDEFHJKLMNPRSTUV SIDE 111111111111111222222222222222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 1 step 15 110100000000000000000000000000 fail ^ ^ ^ ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFHJKLMNPRSDEFHJKLMNPRSTUV SIDE 111111111111111222222222222222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 10 step 16 111000000000000000000000000000 fail ^ ^ ^ ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFHJKLMNPRSDEFHJKLMNPRSTUV SIDE 111111111111111222222222222222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 1 step 17 111100000000000000000000000000 fail ^ ^ ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFHJKLMNPRSDEFHJKLMNPRSTUV SIDE 111111111111111222222222222222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 0000 step 18 000000000000000000000000000000 fail ^ ^ ^ ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFHJKLMNPRSDEFHJKLMNPRSTUV SIDE 111111111111111222222222222222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: step 19 000000000000000000000000000000 fail ^ ^ ^ ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFHJKLMNPRSDEFHJKLMNPRSTUV SIDE 111111111111111222222222222222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 1 step 20 000000001000000000000000000000 fail ^ ^ ^ ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFHJKLMNPRSDEFHJKLMNPRSTUV SIDE 111111111111111222222222222222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 10 step 21 000000010000000000000000000000 fail ^ ^ ^ ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFHJKLMNPRSDEFHJKLMNPRSTUV SIDE 111111111111111222222222222222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 1 step 22 000000011000000000000000000000 fail ^ ^ ^ ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFHJKLMNPRSDEFHJKLMNPRSTUV SIDE 111111111111111222222222222222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 100 step 23 000000100000000000000000000000 fail ^ ^ ^ ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFHJKLMNPRSDEFHJKLMNPRSTUV SIDE 111111111111111222222222222222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 1 step 24 000000101000000000000000000000 fail ^ ^ ^ ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFHJKLMNPRSDEFHJKLMNPRSTUV SIDE 111111111111111222222222222222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 10 step 25 000000110000000000000000000000 fail ^ ^ ^ ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFHJKLMNPRSDEFHJKLMNPRSTUV SIDE 111111111111111222222222222222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 1 step 26 000000111000000000000000000000 fail ^ ^ ^ ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFHJKLMNPRSDEFHJKLMNPRSTUV SIDE 111111111111111222222222222222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 1000 step 27 000001000000000000000000000000 fail ^ ^ ^ ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFHJKLMNPRSDEFHJKLMNPRSTUV SIDE 111111111111111222222222222222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 1 step 28 000001001000000000000000000000 fail ^ ^ ^ ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFHJKLMNPRSDEFHJKLMNPRSTUV SIDE 111111111111111222222222222222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 10 step 29 000001010000000000000000000000 fail ^ ^ ^ ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFHJKLMNPRSDEFHJKLMNPRSTUV SIDE 111111111111111222222222222222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 1 step 30 000001011000000000000000000000 fail ^ ^ ^ ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFHJKLMNPRSDEFHJKLMNPRSTUV SIDE 111111111111111222222222222222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 100 step 31 000001100000000000000000000000 fail ^ ^ ^ ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFHJKLMNPRSDEFHJKLMNPRSTUV SIDE 111111111111111222222222222222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 1 step 32 000001101000000000000000000000 fail ^ ^ ^ ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFHJKLMNPRSDEFHJKLMNPRSTUV SIDE 111111111111111222222222222222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 10 step 33 000001110000000000000000000000 fail ^ ^ ^ ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFHJKLMNPRSDEFHJKLMNPRSTUV SIDE 111111111111111222222222222222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 1 step 34 000001111000000000000000000000 fail ^ ^ ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFHJKLMNPRSDEFHJKLMNPRSTUV SIDE 111111111111111222222222222222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 0000 step 35 000000000000000000000000000000 fail ^ ^ ^ ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFHJKLMNPRSDEFHJKLMNPRSTUV SIDE 111111111111111222222222222222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: step 36 000000000000000000000000000000 fail ^ ^ ^ ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFHJKLMNPRSDEFHJKLMNPRSTUV SIDE 111111111111111222222222222222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 1 step 37 000000000000010000000000000000 fail ^ ^ ^ ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFHJKLMNPRSDEFHJKLMNPRSTUV SIDE 111111111111111222222222222222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 10 step 38 000000000000100000000000000000 fail ^ ^ ^ ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFHJKLMNPRSDEFHJKLMNPRSTUV SIDE 111111111111111222222222222222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 1 step 39 000000000000110000000000000000 fail ^ ^ ^ ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFHJKLMNPRSDEFHJKLMNPRSTUV SIDE 111111111111111222222222222222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 100 step 40 000000000001000000000000000000 fail ^ ^ ^ ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFHJKLMNPRSDEFHJKLMNPRSTUV SIDE 111111111111111222222222222222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 1 step 41 000000000001010000000000000000 fail ^ ^ ^ ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFHJKLMNPRSDEFHJKLMNPRSTUV SIDE 111111111111111222222222222222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 10 step 42 000000000001100000000000000000 fail ^ ^ ^ ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFHJKLMNPRSDEFHJKLMNPRSTUV SIDE 111111111111111222222222222222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 1 step 43 000000000001110000000000000000 fail ^ ^ ^ ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFHJKLMNPRSDEFHJKLMNPRSTUV SIDE 111111111111111222222222222222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 1000 step 44 000000000010000000000000000000 fail ^ ^ ^ ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFHJKLMNPRSDEFHJKLMNPRSTUV SIDE 111111111111111222222222222222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 1 step 45 000000000010010000000000000000 fail ^ ^ ^ ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFHJKLMNPRSDEFHJKLMNPRSTUV SIDE 111111111111111222222222222222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 10 step 46 000000000010100000000000000000 fail ^ ^ ^ ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFHJKLMNPRSDEFHJKLMNPRSTUV SIDE 111111111111111222222222222222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 1 step 47 000000000010110000000000000000 fail ^ ^ ^ ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFHJKLMNPRSDEFHJKLMNPRSTUV SIDE 111111111111111222222222222222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 100 step 48 000000000011000000000000000000 fail ^ ^ ^ ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFHJKLMNPRSDEFHJKLMNPRSTUV SIDE 111111111111111222222222222222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 1 step 49 000000000011010000000000000000 fail ^ ^ ^ ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFHJKLMNPRSDEFHJKLMNPRSTUV SIDE 111111111111111222222222222222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 10 step 50 000000000011100000000000000000 fail ^ ^ ^ ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFHJKLMNPRSDEFHJKLMNPRSTUV SIDE 111111111111111222222222222222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 1 step 51 000000000011110000000000000000 fail ^ ^ ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFHJKLMNPRSDEFHJKLMNPRSTUV SIDE 111111111111111222222222222222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 0000 step 52 000000000000000000000000000000 fail ^ ^ ^ ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFHJKLMNPRSDEFHJKLMNPRSTUV SIDE 111111111111111222222222222222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: step 53 000000000000000000000000000000 fail ^ ^ ^ ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFHJKLMNPRSDEFHJKLMNPRSTUV SIDE 111111111111111222222222222222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 1 step 54 000000000000000000100000000000 fail ^ ^ ^ ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFHJKLMNPRSDEFHJKLMNPRSTUV SIDE 111111111111111222222222222222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 10 step 55 000000000000000001000000000000 fail ^ ^ ^ ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFHJKLMNPRSDEFHJKLMNPRSTUV SIDE 111111111111111222222222222222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 1 step 56 000000000000000001100000000000 fail ^ ^ ^ ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFHJKLMNPRSDEFHJKLMNPRSTUV SIDE 111111111111111222222222222222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 100 step 57 000000000000000010000000000000 fail ^ ^ ^ ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFHJKLMNPRSDEFHJKLMNPRSTUV SIDE 111111111111111222222222222222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 1 step 58 000000000000000010100000000000 fail ^ ^ ^ ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFHJKLMNPRSDEFHJKLMNPRSTUV SIDE 111111111111111222222222222222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 10 step 59 000000000000000011000000000000 fail ^ ^ ^ ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFHJKLMNPRSDEFHJKLMNPRSTUV SIDE 111111111111111222222222222222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 1 step 60 000000000000000011100000000000 fail ^ ^ ^ ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFHJKLMNPRSDEFHJKLMNPRSTUV SIDE 111111111111111222222222222222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 1000 step 61 000000000000000100000000000000 fail ^ ^ ^ ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFHJKLMNPRSDEFHJKLMNPRSTUV SIDE 111111111111111222222222222222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 1 step 62 000000000000000100100000000000 fail ^ ^ ^ ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFHJKLMNPRSDEFHJKLMNPRSTUV SIDE 111111111111111222222222222222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 10 step 63 000000000000000101000000000000 fail ^ ^ ^ ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFHJKLMNPRSDEFHJKLMNPRSTUV SIDE 111111111111111222222222222222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 1 step 64 000000000000000101100000000000 fail ^ ^ ^ ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFHJKLMNPRSDEFHJKLMNPRSTUV SIDE 111111111111111222222222222222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 100 step 65 000000000000000110000000000000 fail ^ ^ ^ ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFHJKLMNPRSDEFHJKLMNPRSTUV SIDE 111111111111111222222222222222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 1 step 66 000000000000000110100000000000 fail ^ ^ ^ ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFHJKLMNPRSDEFHJKLMNPRSTUV SIDE 111111111111111222222222222222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 10 step 67 000000000000000111000000000000 fail ^ ^ ^ ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFHJKLMNPRSDEFHJKLMNPRSTUV SIDE 111111111111111222222222222222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 1 step 68 000000000000000111100000000000 fail ^ ^ ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFHJKLMNPRSDEFHJKLMNPRSTUV SIDE 111111111111111222222222222222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 0000 step 69 000000000000000000000000000000 fail ^ ^ ^ ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFHJKLMNPRSDEFHJKLMNPRSTUV SIDE 111111111111111222222222222222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: step 70 000000000000000000000000000000 fail ^ ^ ^ ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFHJKLMNPRSDEFHJKLMNPRSTUV SIDE 111111111111111222222222222222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 1 step 71 000000000000000000000001000000 fail ^ ^ ^ ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFHJKLMNPRSDEFHJKLMNPRSTUV SIDE 111111111111111222222222222222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 10 step 72 000000000000000000000010000000 fail ^ ^ ^ ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFHJKLMNPRSDEFHJKLMNPRSTUV SIDE 111111111111111222222222222222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 1 step 73 000000000000000000000011000000 fail ^ ^ ^ ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFHJKLMNPRSDEFHJKLMNPRSTUV SIDE 111111111111111222222222222222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 100 step 74 000000000000000000000100000000 fail ^ ^ ^ ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFHJKLMNPRSDEFHJKLMNPRSTUV SIDE 111111111111111222222222222222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 1 step 75 000000000000000000000101000000 fail ^ ^ ^ ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFHJKLMNPRSDEFHJKLMNPRSTUV SIDE 111111111111111222222222222222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 10 step 76 000000000000000000000110000000 fail ^ ^ ^ ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFHJKLMNPRSDEFHJKLMNPRSTUV SIDE 111111111111111222222222222222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 1 step 77 000000000000000000000111000000 fail ^ ^ ^ ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFHJKLMNPRSDEFHJKLMNPRSTUV SIDE 111111111111111222222222222222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 1000 step 78 000000000000000000001000000000 fail ^ ^ ^ ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFHJKLMNPRSDEFHJKLMNPRSTUV SIDE 111111111111111222222222222222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 1 step 79 000000000000000000001001000000 fail ^ ^ ^ ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFHJKLMNPRSDEFHJKLMNPRSTUV SIDE 111111111111111222222222222222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 10 step 80 000000000000000000001010000000 fail ^ ^ ^ ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFHJKLMNPRSDEFHJKLMNPRSTUV SIDE 111111111111111222222222222222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 1 step 81 000000000000000000001011000000 fail ^ ^ ^ ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFHJKLMNPRSDEFHJKLMNPRSTUV SIDE 111111111111111222222222222222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 100 step 82 000000000000000000001100000000 fail ^ ^ ^ ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFHJKLMNPRSDEFHJKLMNPRSTUV SIDE 111111111111111222222222222222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 1 step 83 000000000000000000001101000000 fail ^ ^ ^ ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFHJKLMNPRSDEFHJKLMNPRSTUV SIDE 111111111111111222222222222222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 10 step 84 000000000000000000001110000000 fail ^ ^ ^ ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFHJKLMNPRSDEFHJKLMNPRSTUV SIDE 111111111111111222222222222222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 1 step 85 000000000000000000001111000000 fail ^ ^ ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFHJKLMNPRSDEFHJKLMNPRSTUV SIDE 111111111111111222222222222222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 0000 step 86 000000000000000000000000000000 fail ^ ^ ^ ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFHJKLMNPRSDEFHJKLMNPRSTUV SIDE 111111111111111222222222222222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: step 87 000000000000000000000000000000 fail ^ ^ ^ ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFHJKLMNPRSDEFHJKLMNPRSTUV SIDE 111111111111111222222222222222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 1 step 88 000000000000000000000000000010 fail ^ ^ ^ ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFHJKLMNPRSDEFHJKLMNPRSTUV SIDE 111111111111111222222222222222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 10 step 89 000000000000000000000000000100 fail ^ ^ ^ ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFHJKLMNPRSDEFHJKLMNPRSTUV SIDE 111111111111111222222222222222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 1 step 90 000000000000000000000000000110 fail ^ ^ ^ ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFHJKLMNPRSDEFHJKLMNPRSTUV SIDE 111111111111111222222222222222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 100 step 91 000000000000000000000000001000 fail ^ ^ ^ ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFHJKLMNPRSDEFHJKLMNPRSTUV SIDE 111111111111111222222222222222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 1 step 92 000000000000000000000000001010 fail ^ ^ ^ ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFHJKLMNPRSDEFHJKLMNPRSTUV SIDE 111111111111111222222222222222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 10 step 93 000000000000000000000000001100 fail ^ ^ ^ ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFHJKLMNPRSDEFHJKLMNPRSTUV SIDE 111111111111111222222222222222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 1 step 94 000000000000000000000000001110 fail ^ ^ ^ ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFHJKLMNPRSDEFHJKLMNPRSTUV SIDE 111111111111111222222222222222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 1000 step 95 000000000000000000000000010000 fail ^ ^ ^ ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFHJKLMNPRSDEFHJKLMNPRSTUV SIDE 111111111111111222222222222222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 1 step 96 000000000000000000000000010010 fail ^ ^ ^ ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFHJKLMNPRSDEFHJKLMNPRSTUV SIDE 111111111111111222222222222222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 10 step 97 000000000000000000000000010100 fail ^ ^ ^ ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFHJKLMNPRSDEFHJKLMNPRSTUV SIDE 111111111111111222222222222222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 1 step 98 000000000000000000000000010110 fail ^ ^ ^ ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFHJKLMNPRSDEFHJKLMNPRSTUV SIDE 111111111111111222222222222222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 100 step 99 000000000000000000000000011000 fail ^ ^ ^ ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFHJKLMNPRSDEFHJKLMNPRSTUV SIDE 111111111111111222222222222222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 1 step 100 000000000000000000000000011010 fail ^ ^ ^ ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFHJKLMNPRSDEFHJKLMNPRSTUV SIDE 111111111111111222222222222222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 10 step 101 000000000000000000000000011100 fail ^ ^ ^ ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFHJKLMNPRSDEFHJKLMNPRSTUV SIDE 111111111111111222222222222222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 1 step 102 000000000000000000000000011110 fail ^ ^ ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFHJKLMNPRSDEFHJKLMNPRSTUV SIDE 111111111111111222222222222222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 0000 step 103 000000000000000000000000000000 fail ^ ^ ^ ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFHJKLMNPRSDEFHJKLMNPRSTUV SIDE 111111111111111222222222222222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: step 104 000000000000000000000000000000 fail ^ ^ ^ ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFHJKLMNPRSDEFHJKLMNPRSTUV SIDE 111111111111111222222222222222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 1111 1111 1111 1111 111111111 step 105 111101111011110111101111111110 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFHJKLMNPRSDEFHJKLMNPRSTUV SIDE 111111111111111222222222222222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 0000 0 step 106 000001111011110111101111011110 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFHJKLMNPRSDEFHJKLMNPRSTUV SIDE 111111111111111222222222222222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 1 step 107 000101111011110111101111011110 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFHJKLMNPRSDEFHJKLMNPRSTUV SIDE 111111111111111222222222222222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 10 step 108 001001111011110111101111011110 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFHJKLMNPRSDEFHJKLMNPRSTUV SIDE 111111111111111222222222222222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 1 step 109 001101111011110111101111011110 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFHJKLMNPRSDEFHJKLMNPRSTUV SIDE 111111111111111222222222222222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 100 step 110 010001111011110111101111011110 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFHJKLMNPRSDEFHJKLMNPRSTUV SIDE 111111111111111222222222222222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 1 step 111 010101111011110111101111011110 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFHJKLMNPRSDEFHJKLMNPRSTUV SIDE 111111111111111222222222222222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 10 step 112 011001111011110111101111011110 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFHJKLMNPRSDEFHJKLMNPRSTUV SIDE 111111111111111222222222222222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 1 step 113 011101111011110111101111011110 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFHJKLMNPRSDEFHJKLMNPRSTUV SIDE 111111111111111222222222222222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 1000 step 114 100001111011110111101111011110 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFHJKLMNPRSDEFHJKLMNPRSTUV SIDE 111111111111111222222222222222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 1 step 115 100101111011110111101111011110 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFHJKLMNPRSDEFHJKLMNPRSTUV SIDE 111111111111111222222222222222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 10 step 116 101001111011110111101111011110 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFHJKLMNPRSDEFHJKLMNPRSTUV SIDE 111111111111111222222222222222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 1 step 117 101101111011110111101111011110 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFHJKLMNPRSDEFHJKLMNPRSTUV SIDE 111111111111111222222222222222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 100 step 118 110001111011110111101111011110 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFHJKLMNPRSDEFHJKLMNPRSTUV SIDE 111111111111111222222222222222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 1 step 119 110101111011110111101111011110 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFHJKLMNPRSDEFHJKLMNPRSTUV SIDE 111111111111111222222222222222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 10 step 120 111001111011110111101111011110 fail ^ step 121 111101111011110111101111011110 SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFHJKLMNPRSDEFHJKLMNPRSTUV SIDE 111111111111111222222222222222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 0000 step 122 111100000011110111101111011110 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFHJKLMNPRSDEFHJKLMNPRSTUV SIDE 111111111111111222222222222222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 1 step 123 111100001011110111101111011110 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFHJKLMNPRSDEFHJKLMNPRSTUV SIDE 111111111111111222222222222222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 10 step 124 111100010011110111101111011110 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFHJKLMNPRSDEFHJKLMNPRSTUV SIDE 111111111111111222222222222222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 1 step 125 111100011011110111101111011110 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFHJKLMNPRSDEFHJKLMNPRSTUV SIDE 111111111111111222222222222222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 100 step 126 111100100011110111101111011110 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFHJKLMNPRSDEFHJKLMNPRSTUV SIDE 111111111111111222222222222222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 1 step 127 111100101011110111101111011110 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFHJKLMNPRSDEFHJKLMNPRSTUV SIDE 111111111111111222222222222222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 10 step 128 111100110011110111101111011110 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFHJKLMNPRSDEFHJKLMNPRSTUV SIDE 111111111111111222222222222222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 1 step 129 111100111011110111101111011110 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFHJKLMNPRSDEFHJKLMNPRSTUV SIDE 111111111111111222222222222222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 1000 step 130 111101000011110111101111011110 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFHJKLMNPRSDEFHJKLMNPRSTUV SIDE 111111111111111222222222222222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 1 step 131 111101001011110111101111011110 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFHJKLMNPRSDEFHJKLMNPRSTUV SIDE 111111111111111222222222222222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 10 step 132 111101010011110111101111011110 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFHJKLMNPRSDEFHJKLMNPRSTUV SIDE 111111111111111222222222222222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 1 step 133 111101011011110111101111011110 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFHJKLMNPRSDEFHJKLMNPRSTUV SIDE 111111111111111222222222222222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 100 step 134 111101100011110111101111011110 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFHJKLMNPRSDEFHJKLMNPRSTUV SIDE 111111111111111222222222222222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 1 step 135 111101101011110111101111011110 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFHJKLMNPRSDEFHJKLMNPRSTUV SIDE 111111111111111222222222222222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 10 step 136 111101110011110111101111011110 fail ^ step 137 111101111011110111101111011110 SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFHJKLMNPRSDEFHJKLMNPRSTUV SIDE 111111111111111222222222222222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 0000 step 138 111101111000000111101111011110 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFHJKLMNPRSDEFHJKLMNPRSTUV SIDE 111111111111111222222222222222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 1 step 139 111101111000010111101111011110 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFHJKLMNPRSDEFHJKLMNPRSTUV SIDE 111111111111111222222222222222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 10 step 140 111101111000100111101111011110 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFHJKLMNPRSDEFHJKLMNPRSTUV SIDE 111111111111111222222222222222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 1 step 141 111101111000110111101111011110 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFHJKLMNPRSDEFHJKLMNPRSTUV SIDE 111111111111111222222222222222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 100 step 142 111101111001000111101111011110 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFHJKLMNPRSDEFHJKLMNPRSTUV SIDE 111111111111111222222222222222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 1 step 143 111101111001010111101111011110 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFHJKLMNPRSDEFHJKLMNPRSTUV SIDE 111111111111111222222222222222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 10 step 144 111101111001100111101111011110 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFHJKLMNPRSDEFHJKLMNPRSTUV SIDE 111111111111111222222222222222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 1 step 145 111101111001110111101111011110 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFHJKLMNPRSDEFHJKLMNPRSTUV SIDE 111111111111111222222222222222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 1000 step 146 111101111010000111101111011110 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFHJKLMNPRSDEFHJKLMNPRSTUV SIDE 111111111111111222222222222222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 1 step 147 111101111010010111101111011110 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFHJKLMNPRSDEFHJKLMNPRSTUV SIDE 111111111111111222222222222222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 10 step 148 111101111010100111101111011110 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFHJKLMNPRSDEFHJKLMNPRSTUV SIDE 111111111111111222222222222222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 1 step 149 111101111010110111101111011110 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFHJKLMNPRSDEFHJKLMNPRSTUV SIDE 111111111111111222222222222222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 100 step 150 111101111011000111101111011110 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFHJKLMNPRSDEFHJKLMNPRSTUV SIDE 111111111111111222222222222222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 1 step 151 111101111011010111101111011110 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFHJKLMNPRSDEFHJKLMNPRSTUV SIDE 111111111111111222222222222222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 10 step 152 111101111011100111101111011110 fail ^ step 153 111101111011110111101111011110 SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFHJKLMNPRSDEFHJKLMNPRSTUV SIDE 111111111111111222222222222222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 0000 step 154 111101111011110000001111011110 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFHJKLMNPRSDEFHJKLMNPRSTUV SIDE 111111111111111222222222222222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 1 step 155 111101111011110000101111011110 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFHJKLMNPRSDEFHJKLMNPRSTUV SIDE 111111111111111222222222222222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 10 step 156 111101111011110001001111011110 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFHJKLMNPRSDEFHJKLMNPRSTUV SIDE 111111111111111222222222222222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 1 step 157 111101111011110001101111011110 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFHJKLMNPRSDEFHJKLMNPRSTUV SIDE 111111111111111222222222222222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 100 step 158 111101111011110010001111011110 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFHJKLMNPRSDEFHJKLMNPRSTUV SIDE 111111111111111222222222222222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 1 step 159 111101111011110010101111011110 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFHJKLMNPRSDEFHJKLMNPRSTUV SIDE 111111111111111222222222222222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 10 step 160 111101111011110011001111011110 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFHJKLMNPRSDEFHJKLMNPRSTUV SIDE 111111111111111222222222222222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 1 step 161 111101111011110011101111011110 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFHJKLMNPRSDEFHJKLMNPRSTUV SIDE 111111111111111222222222222222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 1000 step 162 111101111011110100001111011110 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFHJKLMNPRSDEFHJKLMNPRSTUV SIDE 111111111111111222222222222222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 1 step 163 111101111011110100101111011110 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFHJKLMNPRSDEFHJKLMNPRSTUV SIDE 111111111111111222222222222222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 10 step 164 111101111011110101001111011110 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFHJKLMNPRSDEFHJKLMNPRSTUV SIDE 111111111111111222222222222222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 1 step 165 111101111011110101101111011110 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFHJKLMNPRSDEFHJKLMNPRSTUV SIDE 111111111111111222222222222222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 100 step 166 111101111011110110001111011110 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFHJKLMNPRSDEFHJKLMNPRSTUV SIDE 111111111111111222222222222222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 1 step 167 111101111011110110101111011110 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFHJKLMNPRSDEFHJKLMNPRSTUV SIDE 111111111111111222222222222222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 10 step 168 111101111011110111001111011110 fail ^ step 169 111101111011110111101111011110 SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFHJKLMNPRSDEFHJKLMNPRSTUV SIDE 111111111111111222222222222222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 0000 step 170 111101111011110111100000011110 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFHJKLMNPRSDEFHJKLMNPRSTUV SIDE 111111111111111222222222222222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 1 step 171 111101111011110111100001011110 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFHJKLMNPRSDEFHJKLMNPRSTUV SIDE 111111111111111222222222222222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 10 step 172 111101111011110111100010011110 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFHJKLMNPRSDEFHJKLMNPRSTUV SIDE 111111111111111222222222222222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 1 step 173 111101111011110111100011011110 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFHJKLMNPRSDEFHJKLMNPRSTUV SIDE 111111111111111222222222222222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 100 step 174 111101111011110111100100011110 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFHJKLMNPRSDEFHJKLMNPRSTUV SIDE 111111111111111222222222222222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 1 step 175 111101111011110111100101011110 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFHJKLMNPRSDEFHJKLMNPRSTUV SIDE 111111111111111222222222222222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 10 step 176 111101111011110111100110011110 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFHJKLMNPRSDEFHJKLMNPRSTUV SIDE 111111111111111222222222222222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 1 step 177 111101111011110111100111011110 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFHJKLMNPRSDEFHJKLMNPRSTUV SIDE 111111111111111222222222222222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 1000 step 178 111101111011110111101000011110 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFHJKLMNPRSDEFHJKLMNPRSTUV SIDE 111111111111111222222222222222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 1 step 179 111101111011110111101001011110 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFHJKLMNPRSDEFHJKLMNPRSTUV SIDE 111111111111111222222222222222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 10 step 180 111101111011110111101010011110 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFHJKLMNPRSDEFHJKLMNPRSTUV SIDE 111111111111111222222222222222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 1 step 181 111101111011110111101011011110 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFHJKLMNPRSDEFHJKLMNPRSTUV SIDE 111111111111111222222222222222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 100 step 182 111101111011110111101100011110 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFHJKLMNPRSDEFHJKLMNPRSTUV SIDE 111111111111111222222222222222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 1 step 183 111101111011110111101101011110 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFHJKLMNPRSDEFHJKLMNPRSTUV SIDE 111111111111111222222222222222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 10 step 184 111101111011110111101110011110 fail ^ step 185 111101111011110111101111011110 SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFHJKLMNPRSDEFHJKLMNPRSTUV SIDE 111111111111111222222222222222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 0000 step 186 111101111011110111101111000000 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFHJKLMNPRSDEFHJKLMNPRSTUV SIDE 111111111111111222222222222222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 1 step 187 111101111011110111101111000010 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFHJKLMNPRSDEFHJKLMNPRSTUV SIDE 111111111111111222222222222222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 10 step 188 111101111011110111101111000100 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFHJKLMNPRSDEFHJKLMNPRSTUV SIDE 111111111111111222222222222222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 1 step 189 111101111011110111101111000110 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFHJKLMNPRSDEFHJKLMNPRSTUV SIDE 111111111111111222222222222222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 100 step 190 111101111011110111101111001000 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFHJKLMNPRSDEFHJKLMNPRSTUV SIDE 111111111111111222222222222222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 1 step 191 111101111011110111101111001010 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFHJKLMNPRSDEFHJKLMNPRSTUV SIDE 111111111111111222222222222222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 10 step 192 111101111011110111101111001100 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFHJKLMNPRSDEFHJKLMNPRSTUV SIDE 111111111111111222222222222222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 1 step 193 111101111011110111101111001110 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFHJKLMNPRSDEFHJKLMNPRSTUV SIDE 111111111111111222222222222222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 1000 step 194 111101111011110111101111010000 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFHJKLMNPRSDEFHJKLMNPRSTUV SIDE 111111111111111222222222222222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 1 step 195 111101111011110111101111010010 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFHJKLMNPRSDEFHJKLMNPRSTUV SIDE 111111111111111222222222222222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 10 step 196 111101111011110111101111010100 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFHJKLMNPRSDEFHJKLMNPRSTUV SIDE 111111111111111222222222222222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 1 step 197 111101111011110111101111010110 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFHJKLMNPRSDEFHJKLMNPRSTUV SIDE 111111111111111222222222222222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 100 step 198 111101111011110111101111011000 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFHJKLMNPRSDEFHJKLMNPRSTUV SIDE 111111111111111222222222222222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 1 step 199 111101111011110111101111011010 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFHJKLMNPRSDEFHJKLMNPRSTUV SIDE 111111111111111222222222222222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 10 step 200 111101111011110111101111011100 fail ^ step 201 111101111011110111101111011110 step 202 111101111011110111101111011110 test 5: *** FAIL *************************** 195 steps failed SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFHJKLMNPRSDEFHJKLMNPRSTUV SIDE 111111111111111222222222222222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO this fail O O O O O O all fails O O O O O O was hi 111111111111111111111111111111 rising ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ falling vvvvvvvvvvvvvvvvvvvvvvvvvvvvvv was lo 000000000000000000000000000000 total fails 5, total passes 0 space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C toggle comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFHJKLMNPRSDEFHJKLMNPRSTUV SIDE 111111111111111222222222222222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO all fails O O O O O O was lo 000000000000000000000000000000 falling vvvvvvvvvvvvvvvvvvvvvvvvvvvvvv rising ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ was hi 111111111111111111111111111111 total fails 5, total passes 0 Main menu Mon Jul 27 15:25:48 2015 test file is: tests\m617.tst delay is: 0 trigger is: 1 1 read test file 2 set test delay 3 set test trigger 4 run test 5 output loading test 8 diags 9 exit ***************************** UUT power is OFF * ***************************** Main menu Mon Jul 27 15:25:50 2015 test file is: tests\m617.tst delay is: 0 trigger is: 1 1 read test file 2 set test delay 3 set test trigger 4 run test 5 output loading test 8 diags 9 exit UUT power is okay Mon Jul 27 15:25:58 2015 space single step O run once (one test, all steps) F run, stop on fail G go (run tests N run, stop on fail, no print S scope (run, no print) C toggle comment printout + increase speed (less delay) - decrease speed (more delay)(slower) Q quit test scope (run, no print) pppppppppppppppppppppppppppppppppppppppppppppp space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C toggle comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFHJKLMNPRSDEFHJKLMNPRSTUV SIDE 111111111111111222222222222222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO all fails was lo 000000000000000000000000000000 falling vvvvvvvvvvvvvvvvvvvvvvvvvvvvvv rising ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ was hi 111111111111111111111111111111 total fails 0, total passes 46 Main menu Mon Jul 27 15:26:09 2015 test file is: tests\m617.tst delay is: 0 trigger is: 1 1 read test file 2 set test delay 3 set test trigger 4 run test 5 output loading test 8 diags 9 exit UUT power is okay Mon Jul 27 15:32:39 2015 space single step O run once (one test, all steps) F run, stop on fail G go (run tests N run, stop on fail, no print S scope (run, no print) C toggle comment printout + increase speed (less delay) - decrease speed (more delay)(slower) Q quit test step 1 000010000100001000010000100001 step 2 000010000100001000010000100001 step 3 000110000100001000010000100001 step 4 001010000100001000010000100001 SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFHJKLMNPRSDEFHJKLMNPRSTUV SIDE 111111111111111222222222222222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 10 step 5 001100000100001000010000100001 fail ^ step 6 010010000100001000010000100001 step 7 010110000100001000010000100001 step 8 011010000100001000010000100001 SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFHJKLMNPRSDEFHJKLMNPRSTUV SIDE 111111111111111222222222222222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 10 step 9 011100000100001000010000100001 fail ^ step 10 100010000100001000010000100001 step 11 100110000100001000010000100001 step 12 101010000100001000010000100001 SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFHJKLMNPRSDEFHJKLMNPRSTUV SIDE 111111111111111222222222222222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 10 step 13 101100000100001000010000100001 fail ^ step 14 110010000100001000010000100001 step 15 110110000100001000010000100001 step 16 111010000100001000010000100001 step 17 111100000100001000010000100001 step 18 000010000100001000010000100001 step 19 000010000100001000010000100001 step 20 000010001100001000010000100001 step 21 000010010100001000010000100001 step 22 000010011100001000010000100001 step 23 000010100100001000010000100001 step 24 000010101100001000010000100001 step 25 000010110100001000010000100001 step 26 000010111100001000010000100001 step 27 000011000100001000010000100001 step 28 000011001100001000010000100001 step 29 000011010100001000010000100001 step 30 000011011100001000010000100001 step 31 000011100100001000010000100001 step 32 000011101100001000010000100001 step 33 000011110100001000010000100001 step 34 000011111000001000010000100001 step 35 000010000100001000010000100001 step 36 000010000100001000010000100001 step 37 000010000100011000010000100001 step 38 000010000100101000010000100001 step 39 000010000100111000010000100001 step 40 000010000101001000010000100001 step 41 000010000101011000010000100001 step 42 000010000101101000010000100001 step 43 000010000101111000010000100001 step 44 000010000110001000010000100001 step 45 000010000110011000010000100001 step 46 000010000110101000010000100001 step 47 000010000110111000010000100001 step 48 000010000111001000010000100001 step 49 000010000111011000010000100001 step 50 000010000111101000010000100001 step 51 000010000111110000010000100001 step 52 000010000100001000010000100001 step 53 000010000100001000010000100001 step 54 000010000100001000110000100001 step 55 000010000100001001010000100001 step 56 000010000100001001110000100001 step 57 000010000100001010010000100001 step 58 000010000100001010110000100001 step 59 000010000100001011010000100001 step 60 000010000100001011110000100001 step 61 000010000100001100010000100001 step 62 000010000100001100110000100001 step 63 000010000100001101010000100001 step 64 000010000100001101110000100001 step 65 000010000100001110010000100001 step 66 000010000100001110110000100001 step 67 000010000100001111010000100001 step 68 000010000100001111100000100001 step 69 000010000100001000010000100001 step 70 000010000100001000010000100001 step 71 000010000100001000010001100001 step 72 000010000100001000010010100001 step 73 000010000100001000010011100001 step 74 000010000100001000010100100001 step 75 000010000100001000010101100001 step 76 000010000100001000010110100001 step 77 000010000100001000010111100001 step 78 000010000100001000011000100001 step 79 000010000100001000011001100001 step 80 000010000100001000011010100001 step 81 000010000100001000011011100001 step 82 000010000100001000011100100001 step 83 000010000100001000011101100001 step 84 000010000100001000011110100001 step 85 000010000100001000011111000001 step 86 000010000100001000010000100001 step 87 000010000100001000010000100001 step 88 000010000100001000010000100011 step 89 000010000100001000010000100101 step 90 000010000100001000010000100111 step 91 000010000100001000010000101001 step 92 000010000100001000010000101011 step 93 000010000100001000010000101101 step 94 000010000100001000010000101111 step 95 000010000100001000010000110001 step 96 000010000100001000010000110011 step 97 000010000100001000010000110101 step 98 000010000100001000010000110111 step 99 000010000100001000010000111001 step 100 000010000100001000010000111011 step 101 000010000100001000010000111101 step 102 000010000100001000010000111110 step 103 000010000100001000010000100001 step 104 000010000100001000010000100001 step 105 111101111011110111101111011110 step 106 000011111011110111101111011110 step 107 000111111011110111101111011110 step 108 001011111011110111101111011110 SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFHJKLMNPRSDEFHJKLMNPRSTUV SIDE 111111111111111222222222222222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 10 step 109 001101111011110111101111011110 fail ^ step 110 010011111011110111101111011110 step 111 010111111011110111101111011110 step 112 011011111011110111101111011110 SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFHJKLMNPRSDEFHJKLMNPRSTUV SIDE 111111111111111222222222222222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 10 step 113 011101111011110111101111011110 fail ^ step 114 100011111011110111101111011110 step 115 100111111011110111101111011110 step 116 101011111011110111101111011110 SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFHJKLMNPRSDEFHJKLMNPRSTUV SIDE 111111111111111222222222222222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 10 step 117 101101111011110111101111011110 fail ^ step 118 110011111011110111101111011110 step 119 110111111011110111101111011110 step 120 111011111011110111101111011110 step 121 111101111011110111101111011110 step 122 111100000111110111101111011110 step 123 111100001111110111101111011110 step 124 111100010111110111101111011110 step 125 111100011111110111101111011110 step 126 111100100111110111101111011110 step 127 111100101111110111101111011110 step 128 111100110111110111101111011110 step 129 111100111111110111101111011110 step 130 111101000111110111101111011110 step 131 111101001111110111101111011110 step 132 111101010111110111101111011110 step 133 111101011111110111101111011110 step 134 111101100111110111101111011110 step 135 111101101111110111101111011110 step 136 111101110111110111101111011110 step 137 111101111011110111101111011110 step 138 111101111000001111101111011110 step 139 111101111000011111101111011110 step 140 111101111000101111101111011110 step 141 111101111000111111101111011110 step 142 111101111001001111101111011110 step 143 111101111001011111101111011110 step 144 111101111001101111101111011110 step 145 111101111001111111101111011110 step 146 111101111010001111101111011110 step 147 111101111010011111101111011110 step 148 111101111010101111101111011110 step 149 111101111010111111101111011110 step 150 111101111011001111101111011110 step 151 111101111011011111101111011110 step 152 111101111011101111101111011110 step 153 111101111011110111101111011110 step 154 111101111011110000011111011110 step 155 111101111011110000111111011110 step 156 111101111011110001011111011110 step 157 111101111011110001111111011110 step 158 111101111011110010011111011110 step 159 111101111011110010111111011110 step 160 111101111011110011011111011110 step 161 111101111011110011111111011110 step 162 111101111011110100011111011110 step 163 111101111011110100111111011110 step 164 111101111011110101011111011110 step 165 111101111011110101111111011110 step 166 111101111011110110011111011110 step 167 111101111011110110111111011110 step 168 111101111011110111011111011110 step 169 111101111011110111101111011110 step 170 111101111011110111100000111110 step 171 111101111011110111100001111110 step 172 111101111011110111100010111110 step 173 111101111011110111100011111110 step 174 111101111011110111100100111110 step 175 111101111011110111100101111110 step 176 111101111011110111100110111110 step 177 111101111011110111100111111110 step 178 111101111011110111101000111110 step 179 111101111011110111101001111110 step 180 111101111011110111101010111110 step 181 111101111011110111101011111110 step 182 111101111011110111101100111110 step 183 111101111011110111101101111110 step 184 111101111011110111101110111110 step 185 111101111011110111101111011110 step 186 111101111011110111101111000001 step 187 111101111011110111101111000011 step 188 111101111011110111101111000101 step 189 111101111011110111101111000111 step 190 111101111011110111101111001001 step 191 111101111011110111101111001011 step 192 111101111011110111101111001101 step 193 111101111011110111101111001111 step 194 111101111011110111101111010001 step 195 111101111011110111101111010011 step 196 111101111011110111101111010101 step 197 111101111011110111101111010111 step 198 111101111011110111101111011001 step 199 111101111011110111101111011011 step 200 111101111011110111101111011101 step 201 111101111011110111101111011110 step 202 111101111011110111101111011110 test 1: *** FAIL *************************** 6 steps failed SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFHJKLMNPRSDEFHJKLMNPRSTUV SIDE 111111111111111222222222222222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO this fail O all fails O was hi 111111111111111111111111111111 rising ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ falling vvvvvvvvvvvvvvvvvvvvvvvvvvvvvv was lo 000000000000000000000000000000 total fails 1, total passes 0 space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C toggle comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit step 1 000010000100001000010000100001 step 2 000010000100001000010000100001 step 3 000110000100001000010000100001 step 4 001010000100001000010000100001 SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFHJKLMNPRSDEFHJKLMNPRSTUV SIDE 111111111111111222222222222222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 10 step 5 001100000100001000010000100001 fail ^ space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C toggle comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit step 6 010010000100001000010000100001 step 7 010110000100001000010000100001 step 8 011010000100001000010000100001 SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFHJKLMNPRSDEFHJKLMNPRSTUV SIDE 111111111111111222222222222222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 10 step 9 011100000100001000010000100001 fail ^ space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C toggle comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit step 10 100010000100001000010000100001 step 11 100110000100001000010000100001 step 12 101010000100001000010000100001 SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFHJKLMNPRSDEFHJKLMNPRSTUV SIDE 111111111111111222222222222222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 10 step 13 101100000100001000010000100001 fail ^ space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C toggle comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit step 14 110010000100001000010000100001 step 15 110110000100001000010000100001 step 16 111010000100001000010000100001 step 17 111100000100001000010000100001 step 18 000010000100001000010000100001 step 19 000010000100001000010000100001 step 20 000010001100001000010000100001 step 21 000010010100001000010000100001 step 22 000010011100001000010000100001 step 23 000010100100001000010000100001 step 24 000010101100001000010000100001 step 25 000010110100001000010000100001 step 26 000010111100001000010000100001 step 27 000011000100001000010000100001 step 28 000011001100001000010000100001 step 29 000011010100001000010000100001 step 30 000011011100001000010000100001 step 31 000011100100001000010000100001 step 32 000011101100001000010000100001 step 33 000011110100001000010000100001 step 34 000011111000001000010000100001 step 35 000010000100001000010000100001 step 36 000010000100001000010000100001 step 37 000010000100011000010000100001 step 38 000010000100101000010000100001 step 39 000010000100111000010000100001 step 40 000010000101001000010000100001 step 41 000010000101011000010000100001 step 42 000010000101101000010000100001 step 43 000010000101111000010000100001 step 44 000010000110001000010000100001 step 45 000010000110011000010000100001 step 46 000010000110101000010000100001 step 47 000010000110111000010000100001 step 48 000010000111001000010000100001 step 49 000010000111011000010000100001 step 50 000010000111101000010000100001 step 51 000010000111110000010000100001 step 52 000010000100001000010000100001 step 53 000010000100001000010000100001 step 54 000010000100001000110000100001 step 55 000010000100001001010000100001 step 56 000010000100001001110000100001 step 57 000010000100001010010000100001 step 58 000010000100001010110000100001 step 59 000010000100001011010000100001 step 60 000010000100001011110000100001 step 61 000010000100001100010000100001 step 62 000010000100001100110000100001 step 63 000010000100001101010000100001 step 64 000010000100001101110000100001 step 65 000010000100001110010000100001 step 66 000010000100001110110000100001 step 67 000010000100001111010000100001 step 68 000010000100001111100000100001 step 69 000010000100001000010000100001 step 70 000010000100001000010000100001 step 71 000010000100001000010001100001 step 72 000010000100001000010010100001 step 73 000010000100001000010011100001 step 74 000010000100001000010100100001 step 75 000010000100001000010101100001 step 76 000010000100001000010110100001 step 77 000010000100001000010111100001 step 78 000010000100001000011000100001 step 79 000010000100001000011001100001 step 80 000010000100001000011010100001 step 81 000010000100001000011011100001 step 82 000010000100001000011100100001 step 83 000010000100001000011101100001 step 84 000010000100001000011110100001 step 85 000010000100001000011111000001 step 86 000010000100001000010000100001 step 87 000010000100001000010000100001 step 88 000010000100001000010000100011 step 89 000010000100001000010000100101 step 90 000010000100001000010000100111 step 91 000010000100001000010000101001 step 92 000010000100001000010000101011 step 93 000010000100001000010000101101 step 94 000010000100001000010000101111 step 95 000010000100001000010000110001 step 96 000010000100001000010000110011 step 97 000010000100001000010000110101 step 98 000010000100001000010000110111 step 99 000010000100001000010000111001 step 100 000010000100001000010000111011 step 101 000010000100001000010000111101 step 102 000010000100001000010000111110 step 103 000010000100001000010000100001 step 104 000010000100001000010000100001 step 105 111101111011110111101111011110 step 106 000011111011110111101111011110 step 107 000111111011110111101111011110 step 108 001011111011110111101111011110 SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFHJKLMNPRSDEFHJKLMNPRSTUV SIDE 111111111111111222222222222222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 10 step 109 001101111011110111101111011110 fail ^ space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C toggle comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit step 110 010011111011110111101111011110 step 111 010111111011110111101111011110 step 112 011011111011110111101111011110 SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFHJKLMNPRSDEFHJKLMNPRSTUV SIDE 111111111111111222222222222222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 10 step 113 011101111011110111101111011110 fail ^ space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C toggle comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit step 114 100011111011110111101111011110 step 115 100111111011110111101111011110 step 116 101011111011110111101111011110 SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFHJKLMNPRSDEFHJKLMNPRSTUV SIDE 111111111111111222222222222222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 10 step 117 101101111011110111101111011110 fail ^ space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C toggle comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit step 118 110011111011110111101111011110 step 119 110111111011110111101111011110 step 120 111011111011110111101111011110 step 121 111101111011110111101111011110 step 122 111100000111110111101111011110 step 123 111100001111110111101111011110 step 124 111100010111110111101111011110 step 125 111100011111110111101111011110 step 126 111100100111110111101111011110 step 127 111100101111110111101111011110 step 128 111100110111110111101111011110 step 129 111100111111110111101111011110 step 130 111101000111110111101111011110 step 131 111101001111110111101111011110 step 132 111101010111110111101111011110 step 133 111101011111110111101111011110 step 134 111101100111110111101111011110 step 135 111101101111110111101111011110 step 136 111101110111110111101111011110 step 137 111101111011110111101111011110 step 138 111101111000001111101111011110 step 139 111101111000011111101111011110 step 140 111101111000101111101111011110 step 141 111101111000111111101111011110 step 142 111101111001001111101111011110 step 143 111101111001011111101111011110 step 144 111101111001101111101111011110 step 145 111101111001111111101111011110 step 146 111101111010001111101111011110 step 147 111101111010011111101111011110 step 148 111101111010101111101111011110 step 149 111101111010111111101111011110 step 150 111101111011001111101111011110 step 151 111101111011011111101111011110 step 152 111101111011101111101111011110 step 153 111101111011110111101111011110 step 154 111101111011110000011111011110 step 155 111101111011110000111111011110 step 156 111101111011110001011111011110 step 157 111101111011110001111111011110 step 158 111101111011110010011111011110 step 159 111101111011110010111111011110 step 160 111101111011110011011111011110 step 161 111101111011110011111111011110 step 162 111101111011110100011111011110 step 163 111101111011110100111111011110 step 164 111101111011110101011111011110 step 165 111101111011110101111111011110 step 166 111101111011110110011111011110 step 167 111101111011110110111111011110 step 168 111101111011110111011111011110 step 169 111101111011110111101111011110 step 170 111101111011110111100000111110 step 171 111101111011110111100001111110 step 172 111101111011110111100010111110 step 173 111101111011110111100011111110 step 174 111101111011110111100100111110 step 175 111101111011110111100101111110 step 176 111101111011110111100110111110 step 177 111101111011110111100111111110 step 178 111101111011110111101000111110 step 179 111101111011110111101001111110 step 180 111101111011110111101010111110 step 181 111101111011110111101011111110 step 182 111101111011110111101100111110 step 183 111101111011110111101101111110 step 184 111101111011110111101110111110 step 185 111101111011110111101111011110 step 186 111101111011110111101111000001 step 187 111101111011110111101111000011 step 188 111101111011110111101111000101 step 189 111101111011110111101111000111 step 190 111101111011110111101111001001 step 191 111101111011110111101111001011 step 192 111101111011110111101111001101 step 193 111101111011110111101111001111 step 194 111101111011110111101111010001 step 195 111101111011110111101111010011 step 196 111101111011110111101111010101 step 197 111101111011110111101111010111 step 198 111101111011110111101111011001 step 199 111101111011110111101111011011 step 200 111101111011110111101111011101 step 201 111101111011110111101111011110 step 202 111101111011110111101111011110 test 2: *** FAIL *************************** 6 steps failed SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFHJKLMNPRSDEFHJKLMNPRSTUV SIDE 111111111111111222222222222222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO this fail O all fails O was hi 111111111111111111111111111111 rising ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ falling vvvvvvvvvvvvvvvvvvvvvvvvvvvvvv was lo 000000000000000000000000000000 total fails 2, total passes 0 step 1 000010000100001000010000100001 step 2 000010000100001000010000100001 step 3 000110000100001000010000100001 step 4 001010000100001000010000100001 SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFHJKLMNPRSDEFHJKLMNPRSTUV SIDE 111111111111111222222222222222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 10 step 5 001100000100001000010000100001 fail ^ space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C toggle comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit step 6 010010000100001000010000100001 step 7 010110000100001000010000100001 step 8 011010000100001000010000100001 SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFHJKLMNPRSDEFHJKLMNPRSTUV SIDE 111111111111111222222222222222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 10 step 9 011100000100001000010000100001 fail ^ space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C toggle comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit step 10 100010000100001000010000100001 step 11 100110000100001000010000100001 step 12 101010000100001000010000100001 SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFHJKLMNPRSDEFHJKLMNPRSTUV SIDE 111111111111111222222222222222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 10 step 13 101100000100001000010000100001 fail ^ space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C toggle comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit step 14 110010000100001000010000100001 step 15 110110000100001000010000100001 step 16 111010000100001000010000100001 step 17 111100000100001000010000100001 step 18 000010000100001000010000100001 step 19 000010000100001000010000100001 step 20 000010001100001000010000100001 step 21 000010010100001000010000100001 step 22 000010011100001000010000100001 step 23 000010100100001000010000100001 step 24 000010101100001000010000100001 step 25 000010110100001000010000100001 step 26 000010111100001000010000100001 step 27 000011000100001000010000100001 step 28 000011001100001000010000100001 step 29 000011010100001000010000100001 step 30 000011011100001000010000100001 step 31 000011100100001000010000100001 step 32 000011101100001000010000100001 step 33 000011110100001000010000100001 step 34 000011111000001000010000100001 step 35 000010000100001000010000100001 step 36 000010000100001000010000100001 step 37 000010000100011000010000100001 step 38 000010000100101000010000100001 step 39 000010000100111000010000100001 step 40 000010000101001000010000100001 step 41 000010000101011000010000100001 step 42 000010000101101000010000100001 step 43 000010000101111000010000100001 step 44 000010000110001000010000100001 step 45 000010000110011000010000100001 step 46 000010000110101000010000100001 step 47 000010000110111000010000100001 step 48 000010000111001000010000100001 step 49 000010000111011000010000100001 step 50 000010000111101000010000100001 step 51 000010000111110000010000100001 step 52 000010000100001000010000100001 step 53 000010000100001000010000100001 step 54 000010000100001000110000100001 step 55 000010000100001001010000100001 step 56 000010000100001001110000100001 step 57 000010000100001010010000100001 step 58 000010000100001010110000100001 step 59 000010000100001011010000100001 step 60 000010000100001011110000100001 step 61 000010000100001100010000100001 step 62 000010000100001100110000100001 step 63 000010000100001101010000100001 step 64 000010000100001101110000100001 step 65 000010000100001110010000100001 step 66 000010000100001110110000100001 step 67 000010000100001111010000100001 step 68 000010000100001111100000100001 step 69 000010000100001000010000100001 step 70 000010000100001000010000100001 step 71 000010000100001000010001100001 step 72 000010000100001000010010100001 step 73 000010000100001000010011100001 step 74 000010000100001000010100100001 step 75 000010000100001000010101100001 step 76 000010000100001000010110100001 step 77 000010000100001000010111100001 step 78 000010000100001000011000100001 step 79 000010000100001000011001100001 step 80 000010000100001000011010100001 step 81 000010000100001000011011100001 step 82 000010000100001000011100100001 step 83 000010000100001000011101100001 step 84 000010000100001000011110100001 step 85 000010000100001000011111000001 step 86 000010000100001000010000100001 step 87 000010000100001000010000100001 step 88 000010000100001000010000100011 step 89 000010000100001000010000100101 step 90 000010000100001000010000100111 step 91 000010000100001000010000101001 step 92 000010000100001000010000101011 step 93 000010000100001000010000101101 step 94 000010000100001000010000101111 step 95 000010000100001000010000110001 step 96 000010000100001000010000110011 step 97 000010000100001000010000110101 step 98 000010000100001000010000110111 step 99 000010000100001000010000111001 step 100 000010000100001000010000111011 step 101 000010000100001000010000111101 step 102 000010000100001000010000111110 step 103 000010000100001000010000100001 step 104 000010000100001000010000100001 step 105 111101111011110111101111011110 step 106 000011111011110111101111011110 step 107 000111111011110111101111011110 step 108 001011111011110111101111011110 SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFHJKLMNPRSDEFHJKLMNPRSTUV SIDE 111111111111111222222222222222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 10 step 109 001101111011110111101111011110 fail ^ space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C toggle comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit step 110 010011111011110111101111011110 step 111 010111111011110111101111011110 step 112 011011111011110111101111011110 SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFHJKLMNPRSDEFHJKLMNPRSTUV SIDE 111111111111111222222222222222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 10 step 113 011101111011110111101111011110 fail ^ space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C toggle comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit step 114 100011111011110111101111011110 step 115 100111111011110111101111011110 step 116 101011111011110111101111011110 SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFHJKLMNPRSDEFHJKLMNPRSTUV SIDE 111111111111111222222222222222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 10 step 117 101101111011110111101111011110 fail ^ step 118 110011111011110111101111011110 step 119 110111111011110111101111011110 step 120 111011111011110111101111011110 step 121 111101111011110111101111011110 step 122 111100000111110111101111011110 step 123 111100001111110111101111011110 step 124 111100010111110111101111011110 step 125 111100011111110111101111011110 step 126 111100100111110111101111011110 step 127 111100101111110111101111011110 step 128 111100110111110111101111011110 step 129 111100111111110111101111011110 step 130 111101000111110111101111011110 step 131 111101001111110111101111011110 step 132 111101010111110111101111011110 step 133 111101011111110111101111011110 step 134 111101100111110111101111011110 step 135 111101101111110111101111011110 step 136 111101110111110111101111011110 step 137 111101111011110111101111011110 step 138 111101111000001111101111011110 step 139 111101111000011111101111011110 step 140 111101111000101111101111011110 step 141 111101111000111111101111011110 step 142 111101111001001111101111011110 step 143 111101111001011111101111011110 step 144 111101111001101111101111011110 step 145 111101111001111111101111011110 step 146 111101111010001111101111011110 step 147 111101111010011111101111011110 step 148 111101111010101111101111011110 step 149 111101111010111111101111011110 step 150 111101111011001111101111011110 step 151 111101111011011111101111011110 step 152 111101111011101111101111011110 step 153 111101111011110111101111011110 step 154 111101111011110000011111011110 step 155 111101111011110000111111011110 step 156 111101111011110001011111011110 step 157 111101111011110001111111011110 step 158 111101111011110010011111011110 step 159 111101111011110010111111011110 step 160 111101111011110011011111011110 step 161 111101111011110011111111011110 step 162 111101111011110100011111011110 step 163 111101111011110100111111011110 step 164 111101111011110101011111011110 step 165 111101111011110101111111011110 step 166 111101111011110110011111011110 step 167 111101111011110110111111011110 step 168 111101111011110111011111011110 step 169 111101111011110111101111011110 step 170 111101111011110111100000111110 step 171 111101111011110111100001111110 step 172 111101111011110111100010111110 step 173 111101111011110111100011111110 step 174 111101111011110111100100111110 step 175 111101111011110111100101111110 step 176 111101111011110111100110111110 step 177 111101111011110111100111111110 step 178 111101111011110111101000111110 step 179 111101111011110111101001111110 step 180 111101111011110111101010111110 step 181 111101111011110111101011111110 step 182 111101111011110111101100111110 step 183 111101111011110111101101111110 step 184 111101111011110111101110111110 step 185 111101111011110111101111011110 step 186 111101111011110111101111000001 step 187 111101111011110111101111000011 step 188 111101111011110111101111000101 step 189 111101111011110111101111000111 step 190 111101111011110111101111001001 step 191 111101111011110111101111001011 step 192 111101111011110111101111001101 step 193 111101111011110111101111001111 step 194 111101111011110111101111010001 step 195 111101111011110111101111010011 step 196 111101111011110111101111010101 step 197 111101111011110111101111010111 step 198 111101111011110111101111011001 step 199 111101111011110111101111011011 step 200 111101111011110111101111011101 step 201 111101111011110111101111011110 step 202 111101111011110111101111011110 test 3: *** FAIL *************************** 6 steps failed SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFHJKLMNPRSDEFHJKLMNPRSTUV SIDE 111111111111111222222222222222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO this fail O all fails O was hi 111111111111111111111111111111 rising ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ falling vvvvvvvvvvvvvvvvvvvvvvvvvvvvvv was lo 000000000000000000000000000000 total fails 3, total passes 0 space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C toggle comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit step 1 000010000100001000010000100001 step 2 000010000100001000010000100001 step 3 000110000100001000010000100001 step 4 001010000100001000010000100001 SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFHJKLMNPRSDEFHJKLMNPRSTUV SIDE 111111111111111222222222222222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 10 step 5 001100000100001000010000100001 fail ^ step 6 010010000100001000010000100001 step 7 010110000100001000010000100001 step 8 011010000100001000010000100001 SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFHJKLMNPRSDEFHJKLMNPRSTUV SIDE 111111111111111222222222222222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 10 step 9 011100000100001000010000100001 fail ^ step 10 100010000100001000010000100001 step 11 100110000100001000010000100001 step 12 101010000100001000010000100001 SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFHJKLMNPRSDEFHJKLMNPRSTUV SIDE 111111111111111222222222222222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 10 step 13 101100000100001000010000100001 fail ^ step 14 110010000100001000010000100001 step 15 110110000100001000010000100001 step 16 111010000100001000010000100001 step 17 111100000100001000010000100001 step 18 000010000100001000010000100001 step 19 000010000100001000010000100001 step 20 000010001100001000010000100001 step 21 000010010100001000010000100001 step 22 000010011100001000010000100001 step 23 000010100100001000010000100001 step 24 000010101100001000010000100001 step 25 000010110100001000010000100001 step 26 000010111100001000010000100001 step 27 000011000100001000010000100001 step 28 000011001100001000010000100001 step 29 000011010100001000010000100001 step 30 000011011100001000010000100001 step 31 000011100100001000010000100001 step 32 000011101100001000010000100001 step 33 000011110100001000010000100001 step 34 000011111000001000010000100001 step 35 000010000100001000010000100001 step 36 000010000100001000010000100001 step 37 000010000100011000010000100001 step 38 000010000100101000010000100001 step 39 000010000100111000010000100001 step 40 000010000101001000010000100001 step 41 000010000101011000010000100001 step 42 000010000101101000010000100001 step 43 000010000101111000010000100001 step 44 000010000110001000010000100001 step 45 000010000110011000010000100001 step 46 000010000110101000010000100001 step 47 000010000110111000010000100001 step 48 000010000111001000010000100001 step 49 000010000111011000010000100001 step 50 000010000111101000010000100001 step 51 000010000111110000010000100001 step 52 000010000100001000010000100001 step 53 000010000100001000010000100001 step 54 000010000100001000110000100001 step 55 000010000100001001010000100001 step 56 000010000100001001110000100001 step 57 000010000100001010010000100001 step 58 000010000100001010110000100001 step 59 000010000100001011010000100001 step 60 000010000100001011110000100001 step 61 000010000100001100010000100001 step 62 000010000100001100110000100001 step 63 000010000100001101010000100001 step 64 000010000100001101110000100001 step 65 000010000100001110010000100001 step 66 000010000100001110110000100001 step 67 000010000100001111010000100001 step 68 000010000100001111100000100001 step 69 000010000100001000010000100001 step 70 000010000100001000010000100001 step 71 000010000100001000010001100001 step 72 000010000100001000010010100001 step 73 000010000100001000010011100001 step 74 000010000100001000010100100001 step 75 000010000100001000010101100001 step 76 000010000100001000010110100001 step 77 000010000100001000010111100001 step 78 000010000100001000011000100001 step 79 000010000100001000011001100001 step 80 000010000100001000011010100001 step 81 000010000100001000011011100001 step 82 000010000100001000011100100001 step 83 000010000100001000011101100001 step 84 000010000100001000011110100001 step 85 000010000100001000011111000001 step 86 000010000100001000010000100001 step 87 000010000100001000010000100001 step 88 000010000100001000010000100011 step 89 000010000100001000010000100101 step 90 000010000100001000010000100111 step 91 000010000100001000010000101001 step 92 000010000100001000010000101011 step 93 000010000100001000010000101101 step 94 000010000100001000010000101111 step 95 000010000100001000010000110001 step 96 000010000100001000010000110011 step 97 000010000100001000010000110101 step 98 000010000100001000010000110111 step 99 000010000100001000010000111001 step 100 000010000100001000010000111011 step 101 000010000100001000010000111101 step 102 000010000100001000010000111110 step 103 000010000100001000010000100001 step 104 000010000100001000010000100001 step 105 111101111011110111101111011110 step 106 000011111011110111101111011110 step 107 000111111011110111101111011110 step 108 001011111011110111101111011110 SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFHJKLMNPRSDEFHJKLMNPRSTUV SIDE 111111111111111222222222222222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 10 step 109 001101111011110111101111011110 fail ^ step 110 010011111011110111101111011110 step 111 010111111011110111101111011110 step 112 011011111011110111101111011110 SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFHJKLMNPRSDEFHJKLMNPRSTUV SIDE 111111111111111222222222222222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 10 step 113 011101111011110111101111011110 fail ^ step 114 100011111011110111101111011110 step 115 100111111011110111101111011110 step 116 101011111011110111101111011110 SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFHJKLMNPRSDEFHJKLMNPRSTUV SIDE 111111111111111222222222222222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 10 step 117 101101111011110111101111011110 fail ^ step 118 110011111011110111101111011110 step 119 110111111011110111101111011110 step 120 111011111011110111101111011110 step 121 111101111011110111101111011110 step 122 111100000111110111101111011110 step 123 111100001111110111101111011110 step 124 111100010111110111101111011110 step 125 111100011111110111101111011110 step 126 111100100111110111101111011110 step 127 111100101111110111101111011110 step 128 111100110111110111101111011110 step 129 111100111111110111101111011110 step 130 111101000111110111101111011110 step 131 111101001111110111101111011110 step 132 111101010111110111101111011110 step 133 111101011111110111101111011110 step 134 111101100111110111101111011110 step 135 111101101111110111101111011110 step 136 111101110111110111101111011110 step 137 111101111011110111101111011110 step 138 111101111000001111101111011110 step 139 111101111000011111101111011110 step 140 111101111000101111101111011110 step 141 111101111000111111101111011110 step 142 111101111001001111101111011110 step 143 111101111001011111101111011110 step 144 111101111001101111101111011110 step 145 111101111001111111101111011110 step 146 111101111010001111101111011110 step 147 111101111010011111101111011110 step 148 111101111010101111101111011110 step 149 111101111010111111101111011110 step 150 111101111011001111101111011110 step 151 111101111011011111101111011110 step 152 111101111011101111101111011110 step 153 111101111011110111101111011110 step 154 111101111011110000011111011110 step 155 111101111011110000111111011110 step 156 111101111011110001011111011110 step 157 111101111011110001111111011110 step 158 111101111011110010011111011110 step 159 111101111011110010111111011110 step 160 111101111011110011011111011110 step 161 111101111011110011111111011110 step 162 111101111011110100011111011110 step 163 111101111011110100111111011110 step 164 111101111011110101011111011110 step 165 111101111011110101111111011110 step 166 111101111011110110011111011110 step 167 111101111011110110111111011110 step 168 111101111011110111011111011110 step 169 111101111011110111101111011110 step 170 111101111011110111100000111110 step 171 111101111011110111100001111110 step 172 111101111011110111100010111110 step 173 111101111011110111100011111110 step 174 111101111011110111100100111110 step 175 111101111011110111100101111110 step 176 111101111011110111100110111110 step 177 111101111011110111100111111110 step 178 111101111011110111101000111110 step 179 111101111011110111101001111110 step 180 111101111011110111101010111110 step 181 111101111011110111101011111110 step 182 111101111011110111101100111110 step 183 111101111011110111101101111110 step 184 111101111011110111101110111110 step 185 111101111011110111101111011110 step 186 111101111011110111101111000001 step 187 111101111011110111101111000011 step 188 111101111011110111101111000101 step 189 111101111011110111101111000111 step 190 111101111011110111101111001001 step 191 111101111011110111101111001011 step 192 111101111011110111101111001101 step 193 111101111011110111101111001111 step 194 111101111011110111101111010001 step 195 111101111011110111101111010011 step 196 111101111011110111101111010101 step 197 111101111011110111101111010111 step 198 111101111011110111101111011001 step 199 111101111011110111101111011011 step 200 111101111011110111101111011101 step 201 111101111011110111101111011110 step 202 111101111011110111101111011110 test 4: *** FAIL *************************** 6 steps failed SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFHJKLMNPRSDEFHJKLMNPRSTUV SIDE 111111111111111222222222222222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO this fail O all fails O was hi 111111111111111111111111111111 rising ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ falling vvvvvvvvvvvvvvvvvvvvvvvvvvvvvv was lo 000000000000000000000000000000 total fails 4, total passes 0 space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C toggle comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFHJKLMNPRSDEFHJKLMNPRSTUV SIDE 111111111111111222222222222222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO all fails O was lo 000000000000000000000000000000 falling vvvvvvvvvvvvvvvvvvvvvvvvvvvvvv rising ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ was hi 111111111111111111111111111111 total fails 4, total passes 0 Main menu Mon Jul 27 15:36:43 2015 test file is: tests\m617.tst delay is: 0 trigger is: 1 1 read test file 2 set test delay 3 set test trigger 4 run test 5 output loading test 8 diags 9 exit UUT power is okay Mon Jul 27 15:37:06 2015 space single step O run once (one test, all steps) F run, stop on fail G go (run tests N run, stop on fail, no print S scope (run, no print) C toggle comment printout + increase speed (less delay) - decrease speed (more delay)(slower) Q quit test scope (run, no print) ppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppp space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C toggle comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFHJKLMNPRSDEFHJKLMNPRSTUV SIDE 111111111111111222222222222222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO all fails was lo 000000000000000000000000000000 falling vvvvvvvvvvvvvvvvvvvvvvvvvvvvvv rising ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ was hi 111111111111111111111111111111 total fails 0, total passes 71 Main menu Mon Jul 27 15:37:16 2015 test file is: tests\m617.tst delay is: 0 trigger is: 1 1 read test file 2 set test delay 3 set test trigger 4 run test 5 output loading test 8 diags 9 exit UUT power is okay Mon Jul 27 15:38:27 2015 space single step O run once (one test, all steps) F run, stop on fail G go (run tests N run, stop on fail, no print S scope (run, no print) C toggle comment printout + increase speed (less delay) - decrease speed (more delay)(slower) Q quit test scope (run, no print) pppppppppppppppppppppppppppppppppppppppppppppp space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C toggle comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFHJKLMNPRSDEFHJKLMNPRSTUV SIDE 111111111111111222222222222222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO all fails was lo 000000000000000000000000000000 falling vvvvvvvvvvvvvvvvvvvvvvvvvvvvvv rising ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ was hi 111111111111111111111111111111 total fails 0, total passes 46 Main menu Mon Jul 27 15:38:33 2015 test file is: tests\m617.tst delay is: 0 trigger is: 1 1 read test file 2 set test delay 3 set test trigger 4 run test 5 output loading test 8 diags 9 exit UUT power is okay Mon Jul 27 15:39:36 2015 space single step O run once (one test, all steps) F run, stop on fail G go (run tests N run, stop on fail, no print S scope (run, no print) C toggle comment printout + increase speed (less delay) - decrease speed (more delay)(slower) Q quit test scope (run, no print) ppppppppppppppppppppppppppppppppppppppppppppppp space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C toggle comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFHJKLMNPRSDEFHJKLMNPRSTUV SIDE 111111111111111222222222222222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO all fails was lo 000000000000000000000000000000 falling vvvvvvvvvvvvvvvvvvvvvvvvvvvvvv rising ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ was hi 111111111111111111111111111111 total fails 0, total passes 47 Main menu Mon Jul 27 15:39:42 2015 test file is: tests\m617.tst delay is: 0 trigger is: 1 1 read test file 2 set test delay 3 set test trigger 4 run test 5 output loading test 8 diags 9 exit UUT power is okay Mon Jul 27 15:41:47 2015 space single step O run once (one test, all steps) F run, stop on fail G go (run tests N run, stop on fail, no print S scope (run, no print) C toggle comment printout + increase speed (less delay) - decrease speed (more delay)(slower) Q quit test scope (run, no print) ppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppp pppppppppppppppppppppppppppppppppppppppppppppppppppp space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C toggle comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFHJKLMNPRSDEFHJKLMNPRSTUV SIDE 111111111111111222222222222222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO all fails was lo 000000000000000000000000000000 falling vvvvvvvvvvvvvvvvvvvvvvvvvvvvvv rising ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ was hi 111111111111111111111111111111 total fails 0, total passes 131 Main menu Mon Jul 27 15:42:01 2015 test file is: tests\m617.tst delay is: 0 trigger is: 1 1 read test file 2 set test delay 3 set test trigger 4 run test 5 output loading test 8 diags 9 exit exiting