tester- PDP8 card tester via printer port version 0.85 June 4, 2015 mapping[] is verified Main menu Mon Jul 27 17:31:22 2015 test file is: delay is: 0 trigger is: 1 1 read test file 2 set test delay 3 set test trigger 4 run test 5 output loading test 8 diags 9 exit Enter test file name? trying to open test file: tests\m222.new reading test file: tests\m222.new comment: M222 PCB REV B SCHEMATIC REV A LINC TAPE REGISTERS comment: comment: TERMINOLOGY- SIGNALS REFER TO VOL4 M222 SCHEMATIC. comment: comment: BUT... comment: comment: DEC USES AND-NOR GATES TO ROUTE THE ADDER A AND B INPUTS, SO... comment: DEC RENAMED THE ADDER TO NEGATIVE LOGIC TERMS (I.E. A-N + B-N + C-N -> SUM-N, C1-N). comment: (NOT THE 7482 DATASHEET NAMES OF A + B + C -> SUM, C1). comment: comment: SO, WITH ALL 'AND ENABLES' LOW, THE AND-NOR OUTPUTS = HIGH. comment: WITH C-L HIGH, THE ADDER OUTPUT IS SUM-N=1, C1-N=1; comment: THE INVERTED ADDER OUTPUT IS LOW (TAPE BUS). comment: AND THERE IS NO CARRY (C1-N IS HI). comment: comment: THE TWO ADDERS, TWO REGISTER BITS, ETC ARE LABELED BIT 2 (EVEN, MSB) AND BIT 3 (ODD, LSB). comment: THE ADDERS ARE REFERRED TO AS 'ADDER2' (MSB) AND 'ADDER3' (LSB). comment: comment: POWER PINS: comment: AA2 +5V comment: AT1 GROUND comment: AC2 GROUND comment: BA2 +5V comment: BT1 GROUND comment: BC2 GROUND comment: comment: (ALL PINS ARE USED). comment: comment: pins: PINS pins: 1 I BA1 CARRY IN-N, (TO E9-5 7482 C0) C-N TO ADDER2 pins: 2 I AL2 AND-NOR ENABLE: TAC TAC3 TO PIN BB2 (TO ADDER3) TAC2 TO PIN AN2 (TO ADDER2) pins: 3 I AP1 AND-NOR ENABLE: TMA SETUP (TMAS)3 TO PIN BB2 (TO ADDER3), (TMAS)3 TO PIN AN2 (TO ADDER2) pins: 4 I AS2 AND-NOR ENABLE: TMA TMA3 TO PIN BB2 (TO ADDER3), TMA2 TO PIN AN2 (TO ADDER2) pins: 5 I AL1 AND-NOR ENABLE: PIN AF2 TO PIN BB2 (TO ADDER3), PIN AM1 TO PIN AN2 (TO ADDER2) pins: 6 I AF2 AND-NOR INPUT (AL1 ENABLES) TO PIN BB2 (TO ADDER3). pins: 7 I AM1 AND-NOR INPUT (AL1 ENABLES) TO PIN AN2 (TO ADDER2) pins: 8 I AD2 AND-NOR ENABLE: RWB RWB3 TO PIN BB2 (TO ADDER3), RWB2 TO PIN AN2 (TO ADDER2) pins: 9 I AE2 AND-NOR ENABLE: PIN AE1 TO PIN BB2 (TO ADDER3), PIN AM2 TO PIN AN2 (TO ADDER2) pins: 10 I AE1 AND-NOR INPUT (AE2 ENABLES) TO PIN BB2 (TO ADDER3). pins: 11 I AM2 AND-NOR INPUT (AE2 ENABLES) TO PIN AN2 (TO ADDER2) pins: 12 I AC1 AND-NOR INPUT, AND WITH PIN AB2 TO PIN BB2 (TO ADDER3) pins: 13 I AB2 AND-NOR INPUT, AND WITH PIN AC1 TO PIN BB2 (TO ADDER3) pins: 14 I AF1 AND-NOR INPUT (AND WITH ITSELF) TO PIN BB2 (TO ADDER3) pins: 15 I AR2 AND-NOR INPUT, AND WITH PIN AS1 TO PIN AN2 (TO ADDER2) pins: 16 I AS1 AND-NOR INPUT, AND WITH PIN AR2 TO PIN AN2 (TO ADDER2) pins: 17 I AP2 AND-NOR INPUT (AND WITH ITSELF) TO PIN AN2 (TO ADDER2) pins: 18 I BK1 AND-NOR ENABLE: TB3 TO PIN BB1 (TO ADDER3), TB2 TO PIN BN1 (TO ADDER2) pins: 19 I BL1 AND-NOR ENABLE: PIN BE1 TO PIN BB1 (TO ADDER3), PIN BM1 TO PIN BN1 (TO ADDER2) pins: 20 I BE1 AND-NOR INPUT (BL1 ENABLES) TO PIN BB1 (TO ADDER3). pins: 21 I BM1 AND-NOR INPUT (BL1 ENABLES) TO PIN BN1 (TO ADDER2) pins: 22 I BF1 AND-NOR ENABLE: PIN BH1 TO PIN BB1 (TO ADDER3), PIN BR1 TO PIN BN1 (TO ADDER2) pins: 23 I BH1 AND-NOR INPUT (BF1 ENABLES): TO PIN BB1 (TO ADDER3), pins: 24 I BR1 AND-NOR INPUT (BF1 ENABLES): TO PIN BN1 (TO ADDER2) pins: 25 I BS1 AND-NOR ENABLE: PIN BC1 TO PIN BB1 (TO ADDER3), PIN BJ2 TO PIN BN1 (TO ADDER2) pins: 26 I BC1 AND-NOR INPUT (BS1 ENABLES): TO PIN BB1 (TO ADDER3), pins: 27 I BJ2 AND-NOR INPUT (BS1 ENABLES): TO PIN BN1 (TO ADDER2) pins: 28 I BL2 AND-NOR ENABLE: PIN BJ1 TO PIN BB1 (TO ADDER3), PIN BK2 TO PIN BN1 (TO ADDER2) pins: 29 I BJ1 AND-NOR INPUT (BL2 ENABLES): TO PIN BB1 (TO ADDER3), pins: 30 I BK2 AND-NOR INPUT (BL2 ENABLES): TO PIN BN1 (TO ADDER2) pins: 31 I BU1 AND-NOR ENABLE: PIN BH2 TO PIN BB1 (TO ADDER3), PIN BP2 TO PIN BN1 (TO ADDER2) pins: 32 I BH2 AND-NOR INPUT (BU1 ENABLES): TO PIN BB1 (TO ADDER3), pins: 33 I BP2 AND-NOR INPUT (BU1 ENABLES): TO PIN BN1 (TO ADDER2) pins: 34 I BN2 AND-NOR INPUT (AND WITH BM2): TO PIN BN1 (TO ADDER2) pins: 35 I BM2 AND-NOR INPUT (AND WITH BM2): TO PIN BN1 (TO ADDER2) pins: 36 O BB2 AND-NOR OUTPUT, (DRIVES E9-2 7482 A1) TO ADDER3 INPUT pins: 37 O BB1 AND-NOR OUTPUT, (DRIVES E9-3 7482 B1) TO ADDER3 INPUT pins: 38 O BN1 AND-NOR OUTPUT, (DRIVES E9-14 7482 A2) TO ADDER2 INPUT pins: 39 O AN2 AND-NOR OUTPUT, (DRIVES E9-13 7482 B2) TO ADDER2 INPUT pins: 40 O AV2 CARRY OUT-N (E9-10 7482 C2) pins: 41 O BV2 TAPE BUS 2 OUTPUT (INVERTED ADDER2 SUM-N (E9-12 7482 SUM2) pins: 42 O BR2 TAPE BUS 3 OUTPUT (INVERTED ADDER3 SUM-N (E9-1 7482 SUM1) pins: 43 I AK1 LOAD TMA SETUP (FROM TAPE BUS) (RISING EDGE CLOCK) pins: 44 O AR1 TMA SETUP 2 pins: 45 O AH1 TMA SETUP 3 pins: 46 I AU2 LOAD TMA (FROM TAPE BUS) (RISING EDGE CLOCK) pins: 47 O AT2 TMA 2 pins: 48 O AD1 TMA 3 pins: 49 I AJ1 LOAD TBN (FROM TAPE BUS) (RISING EDGE CLOCK) pins: 50 O AU1 TBN 2 pins: 51 O AK2 TBN 3 pins: 52 I AA1 LOAD TAC (FROM TAPE BUS) (RISING EDGE CLOCK) pins: 53 O AN1 TAC 2 pins: 54 O AJ2 TAC 2-N pins: 55 O AH2 TAC 3 pins: 56 O AB1 TAC 3-N pins: 57 I BT2 LOAD TB (FROM TAPE BUS) (RISING EDGE CLOCK) pins: 58 O BP1 TB 2 pins: 59 O BD1 TB 3 pins: 60 I BF2 LOAD RWB (FROM TB) (JAMS CLEAR,SET) pins: 61 I BS2 PHASE (SELECTS POLARITY OF RWB OUT, 0 -> INVERTED) pins: 62 O BV1 RWB OUT (=RWB 2 IF PHASE=1; =RWB 2-N IF PHASE=0) pins: 63 O BD2 RWB 3 pins: 64 I BE2 SHIFT RWB (SHIFTS PIN AV1 INTO RWB 3, SHIFTS RWB3 TO RWB2) (RISING CLOCK) pins: 65 I AV1 RWB IN (SHIFTED INTO RWB 2) pins: 66 O BU2 +3.5V pins: direction: IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIOOOOOOOIOOIOOIOOIOOOOIOOIIOOIIO comment: ; all registers are unknown comment: ; turn on C0, PHASE comment: ; with no ENABLES, BUS2,BUS3 is 11, C2 is 1 test 1: 1000000000000000000000000000000000011111000XX0XX0XX0XXXX0XX01XX001 comment: comment: ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; comment: ; comment: ; set all registers LOW comment: ; comment: ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; comment: comment: ; load TMA SETUP from tape bus (00) test 2: 100 test 3: 0 comment: ; load TMA from tape bus (00) test 4: 100 test 5: 0 comment: ; load TBN from tape bus (00) test 6: 100 test 7: 0 comment: ; load TAC from tape bus (00) test 8: 10101 test 9: 0 comment: ; load TB from tape bus (00) test 10: 100 test 11: 0 comment: ; load RWB from TB (JAMS CLEAR AND PRESET) test 12: 1 00 test 13: 0 comment: ; (no change) test 14: 100000000000000000000000000000000001111100000000000001010000100001 comment: comment: comment: ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; comment: ; comment: ; set all registers HIGH comment: ; comment: ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; comment: comment: ; set pin AF1 (AND with itself) to clear pin BB2 (AND-NOR output) and set pin BR2 TAPE BUS 3 OUTPUT test 15: 1 0 1 comment: ; set pin AP2 (AND with itself) to clear pin AN2 (AND-NOR output) and set pin BV2 TAPE BUS 2 OUTPUT test 16: 1 0 1 comment: comment: comment: ; load TMA SETUP from tape bus (11) test 17: 111 test 18: 0 comment: ; load TMA from tape bus (11) test 19: 111 test 20: 0 comment: ; load TBN from tape bus (11) test 21: 111 test 22: 0 comment: ; load TAC from tape bus (11) test 23: 11010 test 24: 0 comment: ; load TB from tape bus (11) test 25: 111 test 26: 0 comment: ; load RWB from TB (JAMS CLEAR AND PRESET) test 27: 1 11 test 28: 0 comment: ; clear pin AF1 (AND with itself) to set pin BB2 (AND-NOR output) and clear pin BR2 TAPE BUS 3 OUTPUT test 29: 0 1 0 comment: ; clear pin AP2 (AND with itself) to set pin AN2 (AND-NOR output) and clear pin BV2 TAPE BUS 2 OUTPUT test 30: 0 1 0 comment: ; (no change) test 31: 100000000000000000000000000000000001111100011011011010100110111001 comment: comment: comment: ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; comment: ; comment: ; test AND-NOR logic comment: ; comment: ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; comment: comment: ; (all registers are HIGH) comment: ; set all pins HIGH except ENABLES comment: comment: ; set pin AF2 HIGH test 32: 1 comment: ; set pin AM1 HIGH test 33: 1 comment: ; set pin AE1 HIGH test 34: 1 comment: ; set pin AM2 HIGH test 35: 1 comment: ; set pin AB2 HIGH test 36: 1 comment: ; set pin AS1 HIGH test 37: 1 comment: ; set pin BE1 HIGH test 38: 1 comment: ; set pin BM1 HIGH test 39: 1 comment: ; set pin BH1 HIGH test 40: 1 comment: ; set pin BR1 HIGH test 41: 1 comment: ; set pin BC1 HIGH test 42: 1 comment: ; set pin BJ2 HIGH test 43: 1 comment: ; set pin BJ1 HIGH test 44: 1 comment: ; set pin BK2 HIGH test 45: 1 comment: ; set pin BH2 HIGH test 46: 1 comment: ; set pin BP2 HIGH test 47: 1 comment: ; set pin BN2 HIGH test 48: 1 comment: ; toggle each ENABLE comment: comment: ; set pin AL2 to clear pin BB2 and pin AN2 AND-NOR OUTPUTS and set TAPE BUS 2 OUTPUT and TAPE BUS 3 OUTPUT test 49: 1 0 0 11 test 50: 0 1 1 00 comment: ; set pin AP1 to clear pin BB2 and pin AN2 AND-NOR OUTPUTS and set TAPE BUS 2 OUTPUT and TAPE BUS 3 OUTPUT test 51: 1 0 0 11 test 52: 0 1 1 00 comment: ; set pin AS2 to clear pin BB2 and pin AN2 AND-NOR OUTPUTS and set TAPE BUS 2 OUTPUT and TAPE BUS 3 OUTPUT test 53: 1 0 0 11 test 54: 0 1 1 00 comment: ; set pin AL1 to clear pin BB2 and pin AN2 AND-NOR OUTPUTS and set TAPE BUS 2 OUTPUT and TAPE BUS 3 OUTPUT test 55: 1 0 0 11 test 56: 0 1 1 00 comment: ; set pin AL1 to clear pin BB2 and pin AN2 AND-NOR OUTPUTS and set TAPE BUS 2 OUTPUT and TAPE BUS 3 OUTPUT test 57: 1 0 0 11 test 58: 0 1 1 00 comment: ; set pin AE2 to clear pin BB2 and pin AN2 AND-NOR OUTPUTS and set TAPE BUS 2 OUTPUT and TAPE BUS 3 OUTPUT test 59: 1 0 0 11 test 60: 0 1 1 00 comment: ; set pin AC1 to clear pin BB2 and set TAPE BUS 3 OUTPUT test 61: 1 0 1 test 62: 0 1 0 comment: ; set pin AF1 to clear pin BB2 and set TAPE BUS 3 OUTPUT test 63: 1 0 1 test 64: 0 1 0 comment: ; set pin AR2 to clear pin AN2 AND-NOR OUTPUTS and set TAPE BUS 2 OUTPUT test 65: 1 0 1 test 66: 0 1 0 comment: ; set pin AP2 to clear pin AN2 AND-NOR OUTPUTS and set TAPE BUS 2 OUTPUT test 67: 1 0 1 test 68: 0 1 0 comment: comment: ; set pin BK1 to clear pin BB1 and pin BN1 AND-NOR OUTPUTS and set TAPE BUS 2 OUTPUT and TAPE BUS 3 OUTPUT test 69: 1 00 11 test 70: 0 11 00 comment: ; set pin BL1 to clear pin BB1 and pin BN1 AND-NOR OUTPUTS and set TAPE BUS 2 OUTPUT and TAPE BUS 3 OUTPUT test 71: 1 00 11 test 72: 0 11 00 comment: ; set pin BF1 to clear pin BB1 and pin BN1 AND-NOR OUTPUTS and set TAPE BUS 2 OUTPUT and TAPE BUS 3 OUTPUT test 73: 1 00 11 test 74: 0 11 00 comment: ; set pin BS1 to clear pin BB1 and pin BN1 AND-NOR OUTPUTS and set TAPE BUS 2 OUTPUT and TAPE BUS 3 OUTPUT test 75: 1 00 11 test 76: 0 11 00 comment: ; set pin BL2 to clear pin BB1 and pin BN1 AND-NOR OUTPUTS and set TAPE BUS 2 OUTPUT and TAPE BUS 3 OUTPUT test 77: 1 00 11 test 78: 0 11 00 comment: ; set pin BU1 to clear pin BB1 and pin BN1 AND-NOR OUTPUTS and set TAPE BUS 2 OUTPUT and TAPE BUS 3 OUTPUT test 79: 1 00 11 test 80: 0 11 00 comment: ; set pin BM2 to clear pin BB1 and TAPE BUS 3 OUTPUT test 81: 1 0 1 test 82: 0 1 0 comment: comment: ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; comment: ; test shifting the RWB comment: ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; comment: comment: comment: comment: ; shift in 0, expect 10 test 83: 1010 test 84: 0 comment: ; shift in 0, expect 00 test 85: 0010 test 86: 0 comment: ; shift in 0, expect 00 test 87: 0010 test 88: 0 comment: ; shift in 1, expect 01 test 89: 0111 test 90: 0 comment: ; shift in 1, expect 11 test 91: 1111 test 92: 0 comment: ; shift in 1, expect 11 test 93: 1111 test 94: 0 comment: ; shift in 0, expect 10 test 95: 1010 test 96: 0 comment: ; shift in 1, expect 01 test 97: 0111 test 98: 0 comment: ; shift in 0, expect 10 test 99: 1010 test 100: 0 'test step' is too long expected 'test step' (66 columns of '0','1','X', or ' ') bad test file Main menu Mon Jul 27 17:31:30 2015 test file is: delay is: 0 trigger is: 1 1 read test file 2 set test delay 3 set test trigger 4 run test 5 output loading test 8 diags 9 exit exiting tester- PDP8 card tester via printer port version 0.85 June 4, 2015 mapping[] is verified Main menu Mon Jul 27 17:33:13 2015 test file is: delay is: 0 trigger is: 1 1 read test file 2 set test delay 3 set test trigger 4 run test 5 output loading test 8 diags 9 exit Enter test file name? trying to open test file: tests\m222.tst could not open test file. valid test files are: reverting back to test file: Main menu Mon Jul 27 17:33:17 2015 test file is: delay is: 0 trigger is: 1 1 read test file 2 set test delay 3 set test trigger 4 run test 5 output loading test 8 diags 9 exit there is no test file Main menu Mon Jul 27 17:33:19 2015 test file is: delay is: 0 trigger is: 1 1 read test file 2 set test delay 3 set test trigger 4 run test 5 output loading test 8 diags 9 exit key is 0x0073 Main menu Mon Jul 27 17:33:20 2015 test file is: delay is: 0 trigger is: 1 1 read test file 2 set test delay 3 set test trigger 4 run test 5 output loading test 8 diags 9 exit Enter test file name? trying to open test file: tests\m222.new reading test file: tests\m222.new comment: M222 PCB REV B SCHEMATIC REV A LINC TAPE REGISTERS comment: comment: TERMINOLOGY- SIGNALS REFER TO VOL4 M222 SCHEMATIC. comment: comment: BUT... comment: comment: DEC USES AND-NOR GATES TO ROUTE THE ADDER A AND B INPUTS, SO... comment: DEC RENAMED THE ADDER TO NEGATIVE LOGIC TERMS (I.E. A-N + B-N + C-N -> SUM-N, C1-N). comment: (NOT THE 7482 DATASHEET NAMES OF A + B + C -> SUM, C1). comment: comment: SO, WITH ALL 'AND ENABLES' LOW, THE AND-NOR OUTPUTS = HIGH. comment: WITH C-L HIGH, THE ADDER OUTPUT IS SUM-N=1, C1-N=1; comment: THE INVERTED ADDER OUTPUT IS LOW (TAPE BUS). comment: AND THERE IS NO CARRY (C1-N IS HI). comment: comment: THE TWO ADDERS, TWO REGISTER BITS, ETC ARE LABELED BIT 2 (EVEN, MSB) AND BIT 3 (ODD, LSB). comment: THE ADDERS ARE REFERRED TO AS 'ADDER2' (MSB) AND 'ADDER3' (LSB). comment: comment: POWER PINS: comment: AA2 +5V comment: AT1 GROUND comment: AC2 GROUND comment: BA2 +5V comment: BT1 GROUND comment: BC2 GROUND comment: comment: (ALL PINS ARE USED). comment: comment: pins: PINS pins: 1 I BA1 CARRY IN-N, (TO E9-5 7482 C0) C-N TO ADDER2 pins: 2 I AL2 AND-NOR ENABLE: TAC TAC3 TO PIN BB2 (TO ADDER3) TAC2 TO PIN AN2 (TO ADDER2) pins: 3 I AP1 AND-NOR ENABLE: TMA SETUP (TMAS)3 TO PIN BB2 (TO ADDER3), (TMAS)3 TO PIN AN2 (TO ADDER2) pins: 4 I AS2 AND-NOR ENABLE: TMA TMA3 TO PIN BB2 (TO ADDER3), TMA2 TO PIN AN2 (TO ADDER2) pins: 5 I AL1 AND-NOR ENABLE: PIN AF2 TO PIN BB2 (TO ADDER3), PIN AM1 TO PIN AN2 (TO ADDER2) pins: 6 I AF2 AND-NOR INPUT (AL1 ENABLES) TO PIN BB2 (TO ADDER3). pins: 7 I AM1 AND-NOR INPUT (AL1 ENABLES) TO PIN AN2 (TO ADDER2) pins: 8 I AD2 AND-NOR ENABLE: RWB RWB3 TO PIN BB2 (TO ADDER3), RWB2 TO PIN AN2 (TO ADDER2) pins: 9 I AE2 AND-NOR ENABLE: PIN AE1 TO PIN BB2 (TO ADDER3), PIN AM2 TO PIN AN2 (TO ADDER2) pins: 10 I AE1 AND-NOR INPUT (AE2 ENABLES) TO PIN BB2 (TO ADDER3). pins: 11 I AM2 AND-NOR INPUT (AE2 ENABLES) TO PIN AN2 (TO ADDER2) pins: 12 I AC1 AND-NOR INPUT, AND WITH PIN AB2 TO PIN BB2 (TO ADDER3) pins: 13 I AB2 AND-NOR INPUT, AND WITH PIN AC1 TO PIN BB2 (TO ADDER3) pins: 14 I AF1 AND-NOR INPUT (AND WITH ITSELF) TO PIN BB2 (TO ADDER3) pins: 15 I AR2 AND-NOR INPUT, AND WITH PIN AS1 TO PIN AN2 (TO ADDER2) pins: 16 I AS1 AND-NOR INPUT, AND WITH PIN AR2 TO PIN AN2 (TO ADDER2) pins: 17 I AP2 AND-NOR INPUT (AND WITH ITSELF) TO PIN AN2 (TO ADDER2) pins: 18 I BK1 AND-NOR ENABLE: TB3 TO PIN BB1 (TO ADDER3), TB2 TO PIN BN1 (TO ADDER2) pins: 19 I BL1 AND-NOR ENABLE: PIN BE1 TO PIN BB1 (TO ADDER3), PIN BM1 TO PIN BN1 (TO ADDER2) pins: 20 I BE1 AND-NOR INPUT (BL1 ENABLES) TO PIN BB1 (TO ADDER3). pins: 21 I BM1 AND-NOR INPUT (BL1 ENABLES) TO PIN BN1 (TO ADDER2) pins: 22 I BF1 AND-NOR ENABLE: PIN BH1 TO PIN BB1 (TO ADDER3), PIN BR1 TO PIN BN1 (TO ADDER2) pins: 23 I BH1 AND-NOR INPUT (BF1 ENABLES): TO PIN BB1 (TO ADDER3), pins: 24 I BR1 AND-NOR INPUT (BF1 ENABLES): TO PIN BN1 (TO ADDER2) pins: 25 I BS1 AND-NOR ENABLE: PIN BC1 TO PIN BB1 (TO ADDER3), PIN BJ2 TO PIN BN1 (TO ADDER2) pins: 26 I BC1 AND-NOR INPUT (BS1 ENABLES): TO PIN BB1 (TO ADDER3), pins: 27 I BJ2 AND-NOR INPUT (BS1 ENABLES): TO PIN BN1 (TO ADDER2) pins: 28 I BL2 AND-NOR ENABLE: PIN BJ1 TO PIN BB1 (TO ADDER3), PIN BK2 TO PIN BN1 (TO ADDER2) pins: 29 I BJ1 AND-NOR INPUT (BL2 ENABLES): TO PIN BB1 (TO ADDER3), pins: 30 I BK2 AND-NOR INPUT (BL2 ENABLES): TO PIN BN1 (TO ADDER2) pins: 31 I BU1 AND-NOR ENABLE: PIN BH2 TO PIN BB1 (TO ADDER3), PIN BP2 TO PIN BN1 (TO ADDER2) pins: 32 I BH2 AND-NOR INPUT (BU1 ENABLES): TO PIN BB1 (TO ADDER3), pins: 33 I BP2 AND-NOR INPUT (BU1 ENABLES): TO PIN BN1 (TO ADDER2) pins: 34 I BN2 AND-NOR INPUT (AND WITH BM2): TO PIN BN1 (TO ADDER2) pins: 35 I BM2 AND-NOR INPUT (AND WITH BM2): TO PIN BN1 (TO ADDER2) pins: 36 O BB2 AND-NOR OUTPUT, (DRIVES E9-2 7482 A1) TO ADDER3 INPUT pins: 37 O BB1 AND-NOR OUTPUT, (DRIVES E9-3 7482 B1) TO ADDER3 INPUT pins: 38 O BN1 AND-NOR OUTPUT, (DRIVES E9-14 7482 A2) TO ADDER2 INPUT pins: 39 O AN2 AND-NOR OUTPUT, (DRIVES E9-13 7482 B2) TO ADDER2 INPUT pins: 40 O AV2 CARRY OUT-N (E9-10 7482 C2) pins: 41 O BV2 TAPE BUS 2 OUTPUT (INVERTED ADDER2 SUM-N (E9-12 7482 SUM2) pins: 42 O BR2 TAPE BUS 3 OUTPUT (INVERTED ADDER3 SUM-N (E9-1 7482 SUM1) pins: 43 I AK1 LOAD TMA SETUP (FROM TAPE BUS) (RISING EDGE CLOCK) pins: 44 O AR1 TMA SETUP 2 pins: 45 O AH1 TMA SETUP 3 pins: 46 I AU2 LOAD TMA (FROM TAPE BUS) (RISING EDGE CLOCK) pins: 47 O AT2 TMA 2 pins: 48 O AD1 TMA 3 pins: 49 I AJ1 LOAD TBN (FROM TAPE BUS) (RISING EDGE CLOCK) pins: 50 O AU1 TBN 2 pins: 51 O AK2 TBN 3 pins: 52 I AA1 LOAD TAC (FROM TAPE BUS) (RISING EDGE CLOCK) pins: 53 O AN1 TAC 2 pins: 54 O AJ2 TAC 2-N pins: 55 O AH2 TAC 3 pins: 56 O AB1 TAC 3-N pins: 57 I BT2 LOAD TB (FROM TAPE BUS) (RISING EDGE CLOCK) pins: 58 O BP1 TB 2 pins: 59 O BD1 TB 3 pins: 60 I BF2 LOAD RWB (FROM TB) (JAMS CLEAR,SET) pins: 61 I BS2 PHASE (SELECTS POLARITY OF RWB OUT, 0 -> INVERTED) pins: 62 O BV1 RWB OUT (=RWB 2 IF PHASE=1; =RWB 2-N IF PHASE=0) pins: 63 O BD2 RWB 3 pins: 64 I BE2 SHIFT RWB (SHIFTS PIN AV1 INTO RWB 3, SHIFTS RWB3 TO RWB2) (RISING CLOCK) pins: 65 I AV1 RWB IN (SHIFTED INTO RWB 2) pins: 66 O BU2 +3.5V pins: direction: IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIOOOOOOOIOOIOOIOOIOOOOIOOIIOOIIO comment: ; all registers are unknown comment: ; turn on C0, PHASE comment: ; with no ENABLES, BUS2,BUS3 is 11, C2 is 1 test 1: 1000000000000000000000000000000000011111000XX0XX0XX0XXXX0XX01XX001 comment: comment: ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; comment: ; comment: ; set all registers LOW comment: ; comment: ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; comment: comment: ; load TMA SETUP from tape bus (00) test 2: 100 test 3: 0 comment: ; load TMA from tape bus (00) test 4: 100 test 5: 0 comment: ; load TBN from tape bus (00) test 6: 100 test 7: 0 comment: ; load TAC from tape bus (00) test 8: 10101 test 9: 0 comment: ; load TB from tape bus (00) test 10: 100 test 11: 0 comment: ; load RWB from TB (JAMS CLEAR AND PRESET) test 12: 1 00 test 13: 0 comment: ; (no change) test 14: 100000000000000000000000000000000001111100000000000001010000100001 comment: comment: comment: ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; comment: ; comment: ; set all registers HIGH comment: ; comment: ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; comment: comment: ; set pin AF1 (AND with itself) to clear pin BB2 (AND-NOR output) and set pin BR2 TAPE BUS 3 OUTPUT test 15: 1 0 1 comment: ; set pin AP2 (AND with itself) to clear pin AN2 (AND-NOR output) and set pin BV2 TAPE BUS 2 OUTPUT test 16: 1 0 1 comment: comment: comment: ; load TMA SETUP from tape bus (11) test 17: 111 test 18: 0 comment: ; load TMA from tape bus (11) test 19: 111 test 20: 0 comment: ; load TBN from tape bus (11) test 21: 111 test 22: 0 comment: ; load TAC from tape bus (11) test 23: 11010 test 24: 0 comment: ; load TB from tape bus (11) test 25: 111 test 26: 0 comment: ; load RWB from TB (JAMS CLEAR AND PRESET) test 27: 1 11 test 28: 0 comment: ; clear pin AF1 (AND with itself) to set pin BB2 (AND-NOR output) and clear pin BR2 TAPE BUS 3 OUTPUT test 29: 0 1 0 comment: ; clear pin AP2 (AND with itself) to set pin AN2 (AND-NOR output) and clear pin BV2 TAPE BUS 2 OUTPUT test 30: 0 1 0 comment: ; (no change) test 31: 100000000000000000000000000000000001111100011011011010100110111001 comment: comment: comment: ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; comment: ; comment: ; test AND-NOR logic comment: ; comment: ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; comment: comment: ; (all registers are HIGH) comment: ; set all pins HIGH except ENABLES comment: comment: ; set pin AF2 HIGH test 32: 1 comment: ; set pin AM1 HIGH test 33: 1 comment: ; set pin AE1 HIGH test 34: 1 comment: ; set pin AM2 HIGH test 35: 1 comment: ; set pin AB2 HIGH test 36: 1 comment: ; set pin AS1 HIGH test 37: 1 comment: ; set pin BE1 HIGH test 38: 1 comment: ; set pin BM1 HIGH test 39: 1 comment: ; set pin BH1 HIGH test 40: 1 comment: ; set pin BR1 HIGH test 41: 1 comment: ; set pin BC1 HIGH test 42: 1 comment: ; set pin BJ2 HIGH test 43: 1 comment: ; set pin BJ1 HIGH test 44: 1 comment: ; set pin BK2 HIGH test 45: 1 comment: ; set pin BH2 HIGH test 46: 1 comment: ; set pin BP2 HIGH test 47: 1 comment: ; set pin BN2 HIGH test 48: 1 comment: ; toggle each ENABLE comment: comment: ; set pin AL2 to clear pin BB2 and pin AN2 AND-NOR OUTPUTS and set TAPE BUS 2 OUTPUT and TAPE BUS 3 OUTPUT test 49: 1 0 0 11 test 50: 0 1 1 00 comment: ; set pin AP1 to clear pin BB2 and pin AN2 AND-NOR OUTPUTS and set TAPE BUS 2 OUTPUT and TAPE BUS 3 OUTPUT test 51: 1 0 0 11 test 52: 0 1 1 00 comment: ; set pin AS2 to clear pin BB2 and pin AN2 AND-NOR OUTPUTS and set TAPE BUS 2 OUTPUT and TAPE BUS 3 OUTPUT test 53: 1 0 0 11 test 54: 0 1 1 00 comment: ; set pin AL1 to clear pin BB2 and pin AN2 AND-NOR OUTPUTS and set TAPE BUS 2 OUTPUT and TAPE BUS 3 OUTPUT test 55: 1 0 0 11 test 56: 0 1 1 00 comment: ; set pin AL1 to clear pin BB2 and pin AN2 AND-NOR OUTPUTS and set TAPE BUS 2 OUTPUT and TAPE BUS 3 OUTPUT test 57: 1 0 0 11 test 58: 0 1 1 00 comment: ; set pin AE2 to clear pin BB2 and pin AN2 AND-NOR OUTPUTS and set TAPE BUS 2 OUTPUT and TAPE BUS 3 OUTPUT test 59: 1 0 0 11 test 60: 0 1 1 00 comment: ; set pin AC1 to clear pin BB2 and set TAPE BUS 3 OUTPUT test 61: 1 0 1 test 62: 0 1 0 comment: ; set pin AF1 to clear pin BB2 and set TAPE BUS 3 OUTPUT test 63: 1 0 1 test 64: 0 1 0 comment: ; set pin AR2 to clear pin AN2 AND-NOR OUTPUTS and set TAPE BUS 2 OUTPUT test 65: 1 0 1 test 66: 0 1 0 comment: ; set pin AP2 to clear pin AN2 AND-NOR OUTPUTS and set TAPE BUS 2 OUTPUT test 67: 1 0 1 test 68: 0 1 0 comment: comment: ; set pin BK1 to clear pin BB1 and pin BN1 AND-NOR OUTPUTS and set TAPE BUS 2 OUTPUT and TAPE BUS 3 OUTPUT test 69: 1 00 11 test 70: 0 11 00 comment: ; set pin BL1 to clear pin BB1 and pin BN1 AND-NOR OUTPUTS and set TAPE BUS 2 OUTPUT and TAPE BUS 3 OUTPUT test 71: 1 00 11 test 72: 0 11 00 comment: ; set pin BF1 to clear pin BB1 and pin BN1 AND-NOR OUTPUTS and set TAPE BUS 2 OUTPUT and TAPE BUS 3 OUTPUT test 73: 1 00 11 test 74: 0 11 00 comment: ; set pin BS1 to clear pin BB1 and pin BN1 AND-NOR OUTPUTS and set TAPE BUS 2 OUTPUT and TAPE BUS 3 OUTPUT test 75: 1 00 11 test 76: 0 11 00 comment: ; set pin BL2 to clear pin BB1 and pin BN1 AND-NOR OUTPUTS and set TAPE BUS 2 OUTPUT and TAPE BUS 3 OUTPUT test 77: 1 00 11 test 78: 0 11 00 comment: ; set pin BU1 to clear pin BB1 and pin BN1 AND-NOR OUTPUTS and set TAPE BUS 2 OUTPUT and TAPE BUS 3 OUTPUT test 79: 1 00 11 test 80: 0 11 00 comment: ; set pin BM2 to clear pin BB1 and TAPE BUS 3 OUTPUT test 81: 1 0 1 test 82: 0 1 0 comment: comment: ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; comment: ; test shifting the RWB comment: ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; comment: comment: comment: comment: ; shift in 0, expect 10 test 83: 1010 test 84: 0 comment: ; shift in 0, expect 00 test 85: 0010 test 86: 0 comment: ; shift in 0, expect 00 test 87: 0010 test 88: 0 comment: ; shift in 1, expect 01 test 89: 0111 test 90: 0 comment: ; shift in 1, expect 11 test 91: 1111 test 92: 0 comment: ; shift in 1, expect 11 test 93: 1111 test 94: 0 comment: ; shift in 0, expect 10 test 95: 1010 test 96: 0 comment: ; shift in 1, expect 01 test 97: 0111 test 98: 0 comment: ; shift in 0, expect 10 test 99: 1010 test 100: 0 comment: ; shift in 1, expect 01 test 101: 0111 test 102: 0 comment: ; shift in 1, expect 10 test 103: 1011 test 104: 0 comment: ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; comment: ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; comment: ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; comment: ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; comment: ; needs work comment: ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; comment: ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; comment: ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; comment: ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; end: END summary column 1: offset 2, mask 0x2000 column 2: offset 1, mask 0x0002 column 3: offset 1, mask 0x0800 column 4: offset 1, mask 0x0040 column 5: offset 1, mask 0x4000 column 6: offset 0, mask 0x0004 column 7: offset 1, mask 0x2000 column 8: offset 0, mask 0x0010 column 9: offset 0, mask 0x0008 column 10: offset 0, mask 0x0800 column 11: offset 1, mask 0x0004 column 12: offset 0, mask 0x2000 column 13: offset 0, mask 0x0040 column 14: offset 0, mask 0x0400 column 15: offset 1, mask 0x0020 column 16: offset 1, mask 0x0200 column 17: offset 1, mask 0x0010 column 18: offset 3, mask 0x2000 column 19: offset 3, mask 0x1000 column 20: offset 2, mask 0x0200 column 21: offset 3, mask 0x0800 column 22: offset 2, mask 0x0100 column 23: offset 3, mask 0x8000 column 24: offset 3, mask 0x0100 column 25: offset 4, mask 0x8000 column 26: offset 2, mask 0x0800 column 27: offset 3, mask 0x0002 column 28: offset 3, mask 0x0008 column 29: offset 3, mask 0x4000 column 30: offset 3, mask 0x0004 column 31: offset 4, mask 0x2000 column 32: offset 3, mask 0x0001 column 33: offset 3, mask 0x0040 column 34: offset 3, mask 0x0020 column 35: offset 3, mask 0x0010 column 36: offset 2, mask 0x0008 column 37: offset 2, mask 0x1000 column 38: offset 3, mask 0x0400 column 39: offset 1, mask 0x0008 column 40: offset 2, mask 0x0002 column 41: offset 4, mask 0x0008 column 42: offset 3, mask 0x0080 column 43: offset 1, mask 0x8000 column 44: offset 1, mask 0x0400 column 45: offset 0, mask 0x0200 column 46: offset 2, mask 0x0001 column 47: offset 1, mask 0x0080 column 48: offset 0, mask 0x1000 column 49: offset 0, mask 0x0100 column 50: offset 2, mask 0x8000 column 51: offset 1, mask 0x0001 column 52: offset 0, mask 0x8000 column 53: offset 1, mask 0x1000 column 54: offset 0, mask 0x0001 column 55: offset 0, mask 0x0002 column 56: offset 0, mask 0x4000 column 57: offset 4, mask 0x0002 column 58: offset 3, mask 0x0200 column 59: offset 2, mask 0x0400 column 60: offset 2, mask 0x0080 column 61: offset 4, mask 0x0001 column 62: offset 4, mask 0x1000 column 63: offset 2, mask 0x0020 column 64: offset 2, mask 0x0040 column 65: offset 2, mask 0x4000 column 66: offset 4, mask 0x0004 direction bits (1=input) 0x52A3 0x1589 0x943A 0x0680 0x50FC pullup bits (1=pullup) 0x0000 0x0000 0x0000 0x0000 0x0000 test step out_data dont care 1: 0x0000 0x0008 0x300A 0x0400 0x0005 0x5203 0x1481 0x8420 0x0200 0x1000 2: 0x0000 0x8008 0x300A 0x0400 0x0005 0x5003 0x1081 0x8420 0x0200 0x1000 3: 0x0000 0x0008 0x300A 0x0400 0x0005 0x5003 0x1081 0x8420 0x0200 0x1000 4: 0x0000 0x0008 0x300B 0x0400 0x0005 0x4003 0x1001 0x8420 0x0200 0x1000 5: 0x0000 0x0008 0x300A 0x0400 0x0005 0x4003 0x1001 0x8420 0x0200 0x1000 6: 0x0100 0x0008 0x300A 0x0400 0x0005 0x4003 0x1000 0x0420 0x0200 0x1000 7: 0x0000 0x0008 0x300A 0x0400 0x0005 0x4003 0x1000 0x0420 0x0200 0x1000 8: 0xC001 0x0008 0x300A 0x0400 0x0005 0x0000 0x0000 0x0420 0x0200 0x1000 9: 0x4001 0x0008 0x300A 0x0400 0x0005 0x0000 0x0000 0x0420 0x0200 0x1000 10: 0x4001 0x0008 0x300A 0x0400 0x0007 0x0000 0x0000 0x0020 0x0000 0x1000 11: 0x4001 0x0008 0x300A 0x0400 0x0005 0x0000 0x0000 0x0020 0x0000 0x1000 12: 0x4001 0x0008 0x308A 0x0400 0x0005 13: 0x4001 0x0008 0x300A 0x0400 0x0005 14: 0x4001 0x0008 0x300A 0x0400 0x0005 15: 0x4401 0x0008 0x3002 0x0480 0x0005 16: 0x4401 0x0010 0x3002 0x0480 0x000D 17: 0x4601 0x8410 0x3002 0x0480 0x000D 18: 0x4601 0x0410 0x3002 0x0480 0x000D 19: 0x5601 0x0490 0x3003 0x0480 0x000D 20: 0x5601 0x0490 0x3002 0x0480 0x000D 21: 0x5701 0x0491 0xB002 0x0480 0x000D 22: 0x5601 0x0491 0xB002 0x0480 0x000D 23: 0x9602 0x1491 0xB002 0x0480 0x000D 24: 0x1602 0x1491 0xB002 0x0480 0x000D 25: 0x1602 0x1491 0xB402 0x0680 0x000F 26: 0x1602 0x1491 0xB402 0x0680 0x000D 27: 0x1602 0x1491 0xB4A2 0x0680 0x100D 28: 0x1602 0x1491 0xB422 0x0680 0x100D 29: 0x1202 0x1491 0xB42A 0x0600 0x100D 30: 0x1202 0x1489 0xB42A 0x0600 0x1005 31: 0x1202 0x1489 0xB42A 0x0600 0x1005 32: 0x1206 0x1489 0xB42A 0x0600 0x1005 33: 0x1206 0x3489 0xB42A 0x0600 0x1005 34: 0x1A06 0x3489 0xB42A 0x0600 0x1005 35: 0x1A06 0x348D 0xB42A 0x0600 0x1005 36: 0x1A46 0x348D 0xB42A 0x0600 0x1005 37: 0x1A46 0x368D 0xB42A 0x0600 0x1005 38: 0x1A46 0x368D 0xB62A 0x0600 0x1005 39: 0x1A46 0x368D 0xB62A 0x0E00 0x1005 40: 0x1A46 0x368D 0xB62A 0x8E00 0x1005 41: 0x1A46 0x368D 0xB62A 0x8F00 0x1005 42: 0x1A46 0x368D 0xBE2A 0x8F00 0x1005 43: 0x1A46 0x368D 0xBE2A 0x8F02 0x1005 44: 0x1A46 0x368D 0xBE2A 0xCF02 0x1005 45: 0x1A46 0x368D 0xBE2A 0xCF06 0x1005 46: 0x1A46 0x368D 0xBE2A 0xCF07 0x1005 47: 0x1A46 0x368D 0xBE2A 0xCF47 0x1005 48: 0x1A46 0x368D 0xBE2A 0xCF67 0x1005 49: 0x1A46 0x3687 0xBE22 0xCFE7 0x100D 50: 0x1A46 0x368D 0xBE2A 0xCF67 0x1005 51: 0x1A46 0x3E85 0xBE22 0xCFE7 0x100D 52: 0x1A46 0x368D 0xBE2A 0xCF67 0x1005 53: 0x1A46 0x36C5 0xBE22 0xCFE7 0x100D 54: 0x1A46 0x368D 0xBE2A 0xCF67 0x1005 55: 0x1A46 0x7685 0xBE22 0xCFE7 0x100D 56: 0x1A46 0x368D 0xBE2A 0xCF67 0x1005 57: 0x1A56 0x3685 0xBE22 0xCFE7 0x100D 58: 0x1A46 0x368D 0xBE2A 0xCF67 0x1005 59: 0x1A4E 0x3685 0xBE22 0xCFE7 0x100D 60: 0x1A46 0x368D 0xBE2A 0xCF67 0x1005 61: 0x3A46 0x368D 0xBE22 0xCFE7 0x1005 62: 0x1A46 0x368D 0xBE2A 0xCF67 0x1005 63: 0x1E46 0x368D 0xBE22 0xCFE7 0x1005 64: 0x1A46 0x368D 0xBE2A 0xCF67 0x1005 65: 0x1A46 0x36A5 0xBE2A 0xCF67 0x100D 66: 0x1A46 0x368D 0xBE2A 0xCF67 0x1005 67: 0x1A46 0x3695 0xBE2A 0xCF67 0x100D 68: 0x1A46 0x368D 0xBE2A 0xCF67 0x1005 69: 0x1A46 0x368D 0xAE2A 0xEBE7 0x100D 70: 0x1A46 0x368D 0xBE2A 0xCF67 0x1005 71: 0x1A46 0x368D 0xAE2A 0xDBE7 0x100D 72: 0x1A46 0x368D 0xBE2A 0xCF67 0x1005 73: 0x1A46 0x368D 0xAF2A 0xCBE7 0x100D 74: 0x1A46 0x368D 0xBE2A 0xCF67 0x1005 75: 0x1A46 0x368D 0xAE2A 0xCBE7 0x900D 76: 0x1A46 0x368D 0xBE2A 0xCF67 0x1005 77: 0x1A46 0x368D 0xAE2A 0xCBEF 0x100D 78: 0x1A46 0x368D 0xBE2A 0xCF67 0x1005 79: 0x1A46 0x368D 0xAE2A 0xCBE7 0x300D 80: 0x1A46 0x368D 0xBE2A 0xCF67 0x1005 81: 0x1A46 0x368D 0xBE2A 0xCB77 0x100D 82: 0x1A46 0x368D 0xBE2A 0xCF67 0x1005 83: 0x1A46 0x368D 0xBE4A 0xCF67 0x1005 84: 0x1A46 0x368D 0xBE0A 0xCF67 0x1005 85: 0x1A46 0x368D 0xBE4A 0xCF67 0x0005 86: 0x1A46 0x368D 0xBE0A 0xCF67 0x0005 87: 0x1A46 0x368D 0xBE4A 0xCF67 0x0005 88: 0x1A46 0x368D 0xBE0A 0xCF67 0x0005 89: 0x1A46 0x368D 0xFE6A 0xCF67 0x0005 90: 0x1A46 0x368D 0xFE2A 0xCF67 0x0005 91: 0x1A46 0x368D 0xFE6A 0xCF67 0x1005 92: 0x1A46 0x368D 0xFE2A 0xCF67 0x1005 93: 0x1A46 0x368D 0xFE6A 0xCF67 0x1005 94: 0x1A46 0x368D 0xFE2A 0xCF67 0x1005 95: 0x1A46 0x368D 0xBE4A 0xCF67 0x1005 96: 0x1A46 0x368D 0xBE0A 0xCF67 0x1005 97: 0x1A46 0x368D 0xFE6A 0xCF67 0x0005 98: 0x1A46 0x368D 0xFE2A 0xCF67 0x0005 99: 0x1A46 0x368D 0xBE4A 0xCF67 0x1005 100: 0x1A46 0x368D 0xBE0A 0xCF67 0x1005 101: 0x1A46 0x368D 0xFE6A 0xCF67 0x0005 102: 0x1A46 0x368D 0xFE2A 0xCF67 0x0005 103: 0x1A46 0x368D 0xFE4A 0xCF67 0x1005 104: 0x1A46 0x368D 0xFE0A 0xCF67 0x1005 PINs used (in edge connector order) (G=ground,P=power) SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBB LETTER ABCDEFHJKLMNPRSTUVABCDEFHJKLMNPRSTUVABCDEFHJKLMNPRSTUVABCDEFHJKLMNPRSTUV SIDE 111111111111111111222222222222222222111111111111111111222222222222222222 USAGE IOIOIIOIIIIOIOIGOIPIGIIIOOOIIOIIIOIOIOIOIIIIIIIOOIIGIOPOGOIIIIIIIIIOIIOO UUT has 44 inputs UUT has 22 outputs contains 66 pins/columns 0 pins are not used contains 104 'test steps' M222 PCB REV B SCHEMATIC REV A LINC TAPE REGISTERS TERMINOLOGY- SIGNALS REFER TO VOL4 M222 SCHEMATIC. BUT... DEC USES AND-NOR GATES TO ROUTE THE ADDER A AND B INPUTS, SO... DEC RENAMED THE ADDER TO NEGATIVE LOGIC TERMS (I.E. A-N + B-N + C-N -> SUM-N, C1-N). (NOT THE 7482 DATASHEET NAMES OF A + B + C -> SUM, C1). SO, WITH ALL 'AND ENABLES' LOW, THE AND-NOR OUTPUTS = HIGH. WITH C-L HIGH, THE ADDER OUTPUT IS SUM-N=1, C1-N=1; THE INVERTED ADDER OUTPUT IS LOW (TAPE BUS). AND THERE IS NO CARRY (C1-N IS HI). THE TWO ADDERS, TWO REGISTER BITS, ETC ARE LABELED BIT 2 (EVEN, MSB) AND BIT 3 (ODD, LSB). THE ADDERS ARE REFERRED TO AS 'ADDER2' (MSB) AND 'ADDER3' (LSB). POWER PINS: AA2 +5V AT1 GROUND AC2 GROUND BA2 +5V BT1 GROUND BC2 GROUND (ALL PINS ARE USED). PINS Main menu Mon Jul 27 17:33:34 2015 test file is: tests\m222.new delay is: 0 trigger is: 1 1 read test file 2 set test delay 3 set test trigger 4 run test 5 output loading test 8 diags 9 exit UUT power is okay Mon Jul 27 17:33:37 2015 space single step O run once (one test, all steps) F run, stop on fail G go (run tests N run, stop on fail, no print S scope (run, no print) C toggle comment printout + increase speed (less delay) - decrease speed (more delay)(slower) Q quit test scope (run, no print) FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C toggle comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT BAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBAABBAAAAAAAAAAAAAABBBBBBBBAB LETTER ALPSLFMDEEMCBFRSPKLEMFHRSCJLJKUHPNMBBNNVVRKRHUTDJUKANJHBTPDFSVDEVU SIDE 121212122121212121111111112212122222112222111221112112212112212212 DIRECTION IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIOOOOOOOIOOIOOIOOIOOOOIOOIIOOIIO all fails OO was lo 00000000000000000000000000000000000000 00000000000000000000 0000 falling vvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvv vvvvvvvvvvvvvvvvvvvv vvvv rising ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ ^^^^^^^^^^^^^^^^^^^^ ^^^^ was hi 111111111111111111111111111111111111111111111111111111111111111111 total fails 57, total passes 0 Main menu Mon Jul 27 17:33:43 2015 test file is: tests\m222.new delay is: 0 trigger is: 1 1 read test file 2 set test delay 3 set test trigger 4 run test 5 output loading test 8 diags 9 exit UUT power is okay Mon Jul 27 17:33:45 2015 space single step O run once (one test, all steps) F run, stop on fail G go (run tests N run, stop on fail, no print S scope (run, no print) C toggle comment printout + increase speed (less delay) - decrease speed (more delay)(slower) Q quit test step 1 100000000000000000000000000000000001111100001001000001010010101001 step 2 100000000000000000000000000000000001111100100001000001010010101001 step 3 100000000000000000000000000000000001111100000001000001010010101001 step 4 100000000000000000000000000000000001111100000100000001010010101001 step 5 100000000000000000000000000000000001111100000000000001010010101001 step 6 100000000000000000000000000000000001111100000000100001010010101001 step 7 100000000000000000000000000000000001111100000000000001010010101001 step 8 100000000000000000000000000000000001111100000000000101010010101001 step 9 100000000000000000000000000000000001111100000000000001010010101001 step 10 100000000000000000000000000000000001111100000000000001011000101001 step 11 100000000000000000000000000000000001111100000000000001010000101001 step 12 100000000000000000000000000000000001111100000000000001010001100001 step 13 100000000000000000000000000000000001111100000000000001010000100001 step 14 100000000000000000000000000000000001111100000000000001010000100001 step 15 100000000000010000000000000000000000111101000000000001010000100001 step 16 100000000000010010000000000000000000110111000000000001010000100001 step 17 100000000000010010000000000000000000110111111000000001010000100001 step 18 100000000000010010000000000000000000110111011000000001010000100001 step 19 100000000000010010000000000000000000110111011111000001010000100001 step 20 100000000000010010000000000000000000110111011011000001010000100001 step 21 100000000000010010000000000000000000110111011011111001010000100001 step 22 100000000000010010000000000000000000110111011011011001010000100001 step 23 100000000000010010000000000000000000110111011011011110100000100001 step 24 100000000000010010000000000000000000110111011011011010100000100001 step 25 100000000000010010000000000000000000110111011011011010101110100001 step 26 100000000000010010000000000000000000110111011011011010100110100001 step 27 100000000000010010000000000000000000110111011011011010100111111001 step 28 100000000000010010000000000000000000110111011011011010100110111001 step 29 100000000000000010000000000000000001110110011011011010100110111001 step 30 100000000000000000000000000000000001111100011011011010100110111001 step 31 100000000000000000000000000000000001111100011011011010100110111001 step 32 100001000000000000000000000000000001111100011011011010100110111001 step 33 100001100000000000000000000000000001111100011011011010100110111001 step 34 100001100100000000000000000000000001111100011011011010100110111001 step 35 100001100110000000000000000000000001111100011011011010100110111001 step 36 100001100110100000000000000000000001111100011011011010100110111001 step 37 100001100110100100000000000000000001111100011011011010100110111001 step 38 100001100110100100010000000000000001111100011011011010100110111001 step 39 100001100110100100011000000000000001111100011011011010100110111001 step 40 100001100110100100011010000000000001111100011011011010100110111001 step 41 100001100110100100011011000000000001111100011011011010100110111001 step 42 100001100110100100011011010000000001111100011011011010100110111001 step 43 100001100110100100011011011000000001111100011011011010100110111001 step 44 100001100110100100011011011010000001111100011011011010100110111001 step 45 100001100110100100011011011011000001111100011011011010100110111001 step 46 100001100110100100011011011011010001111100011011011010100110111001 step 47 100001100110100100011011011011011001111100011011011010100110111001 step 48 100001100110100100011011011011011101111100011011011010100110111001 step 49 110001100110100100011011011011011100110111011011011010100110111001 step 50 100001100110100100011011011011011101111100011011011010100110111001 step 51 101001100110100100011011011011011100110111011011011010100110111001 step 52 100001100110100100011011011011011101111100011011011010100110111001 step 53 100101100110100100011011011011011100110111011011011010100110111001 step 54 100001100110100100011011011011011101111100011011011010100110111001 step 55 100011100110100100011011011011011100110111011011011010100110111001 step 56 100001100110100100011011011011011101111100011011011010100110111001 step 57 100001110110100100011011011011011100110111011011011010100110111001 step 58 100001100110100100011011011011011101111100011011011010100110111001 step 59 100001101110100100011011011011011100110111011011011010100110111001 step 60 100001100110100100011011011011011101111100011011011010100110111001 step 61 100001100111100100011011011011011100111101011011011010100110111001 step 62 100001100110100100011011011011011101111100011011011010100110111001 step 63 100001100110110100011011011011011100111101011011011010100110111001 step 64 100001100110100100011011011011011101111100011011011010100110111001 step 65 100001100110101100011011011011011101110110011011011010100110111001 step 66 100001100110100100011011011011011101111100011011011010100110111001 step 67 100001100110100110011011011011011101110110011011011010100110111001 step 68 100001100110100100011011011011011101111100011011011010100110111001 step 69 100001100110100101011011011011011101001111011011011010100110111001 step 70 100001100110100100011011011011011101111100011011011010100110111001 step 71 100001100110100100111011011011011101001111011011011010100110111001 step 72 100001100110100100011011011011011101111100011011011010100110111001 step 73 100001100110100100011111011011011101001111011011011010100110111001 step 74 100001100110100100011011011011011101111100011011011010100110111001 step 75 100001100110100100011011111011011101001111011011011010100110111001 step 76 100001100110100100011011011011011101111100011011011010100110111001 step 77 100001100110100100011011011111011101001111011011011010100110111001 step 78 100001100110100100011011011011011101111100011011011010100110111001 step 79 100001100110100100011011011011111101001111011011011010100110111001 step 80 100001100110100100011011011011011101111100011011011010100110111001 step 81 100001100110100100011011011011011111101110011011011010100110111001 step 82 100001100110100100011011011011011101111100011011011010100110111001 step 83 100001100110100100011011011011011101111100011011011010100110110101 step 84 100001100110100100011011011011011101111100011011011010100110110001 step 85 100001100110100100011011011011011101111100011011011010100110100101 step 86 100001100110100100011011011011011101111100011011011010100110100001 step 87 100001100110100100011011011011011101111100011011011010100110100101 step 88 100001100110100100011011011011011101111100011011011010100110100001 SLOT BAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBAABBAAAAAAAAAAAAAABBBBBBBBAB LETTER ALPSLFMDEEMCBFRSPKLEMFHRSCJLJKUHPNMBBNNVVRKRHUTDJUKANJHBTPDFSVDEVU SIDE 121212122121212121111111112212122222112222111221112112212112212212 DIRECTION IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIOOOOOOOIOOIOOIOOIOOOOIOOIIOOIIO changed: 11 step 89 100001100110100100011011011011011101111100011011011010100110100111 fail ^ space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C toggle comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit comment_flag is 1 space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C toggle comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT BAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBAABBAAAAAAAAAAAAAABBBBBBBBAB LETTER ALPSLFMDEEMCBFRSPKLEMFHRSCJLJKUHPNMBBNNVVRKRHUTDJUKANJHBTPDFSVDEVU SIDE 121212122121212121111111112212122222112222111221112112212112212212 DIRECTION IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIOOOOOOOIOOIOOIOOIOOOOIOOIIOOIIO source: 0 changed: 0 step 90 100001100110100100011011011011011101111100011011011010100110100011 fail ^ space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C toggle comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT BAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBAABBAAAAAAAAAAAAAABBBBBBBBAB LETTER ALPSLFMDEEMCBFRSPKLEMFHRSCJLJKUHPNMBBNNVVRKRHUTDJUKANJHBTPDFSVDEVU SIDE 121212122121212121111111112212122222112222111221112112212112212212 DIRECTION IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIOOOOOOOIOOIOOIOOIOOOOIOOIIOOIIO source: ; shift in 1, expect 11 source: 1111 changed: 11 step 91 100001100110100100011011011011011101111100011011011010100110101111 fail ^ space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C toggle comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT BAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBAABBAAAAAAAAAAAAAABBBBBBBBAB LETTER ALPSLFMDEEMCBFRSPKLEMFHRSCJLJKUHPNMBBNNVVRKRHUTDJUKANJHBTPDFSVDEVU SIDE 121212122121212121111111112212122222112222111221112112212112212212 DIRECTION IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIOOOOOOOIOOIOOIOOIOOOOIOOIIOOIIO source: 0 changed: 0 step 92 100001100110100100011011011011011101111100011011011010100110101011 fail ^ space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C toggle comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit source: ; shift in 1, expect 11 source: 1111 changed: 1 1 step 93 100001100110100100011011011011011101111100011011011010100110111111 source: 0 changed: 0 step 94 100001100110100100011011011011011101111100011011011010100110111011 SLOT BAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBAABBAAAAAAAAAAAAAABBBBBBBBAB LETTER ALPSLFMDEEMCBFRSPKLEMFHRSCJLJKUHPNMBBNNVVRKRHUTDJUKANJHBTPDFSVDEVU SIDE 121212122121212121111111112212122222112222111221112112212112212212 DIRECTION IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIOOOOOOOIOOIOOIOOIOOOOIOOIIOOIIO source: ; shift in 0, expect 10 source: 1010 changed: 10 step 95 100001100110100100011011011011011101111100011011011010100110111101 fail ^ space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C toggle comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT BAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBAABBAAAAAAAAAAAAAABBBBBBBBAB LETTER ALPSLFMDEEMCBFRSPKLEMFHRSCJLJKUHPNMBBNNVVRKRHUTDJUKANJHBTPDFSVDEVU SIDE 121212122121212121111111112212122222112222111221112112212112212212 DIRECTION IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIOOOOOOOIOOIOOIOOIOOOOIOOIIOOIIO source: 0 changed: 0 step 96 100001100110100100011011011011011101111100011011011010100110111001 fail ^ space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C toggle comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT BAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBAABBAAAAAAAAAAAAAABBBBBBBBAB LETTER ALPSLFMDEEMCBFRSPKLEMFHRSCJLJKUHPNMBBNNVVRKRHUTDJUKANJHBTPDFSVDEVU SIDE 121212122121212121111111112212122222112222111221112112212112212212 DIRECTION IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIOOOOOOOIOOIOOIOOIOOOOIOOIIOOIIO source: ; shift in 1, expect 01 source: 0111 changed: 011 step 97 100001100110100100011011011011011101111100011011011010100110110111 fail ^^ space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C toggle comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT BAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBAABBAAAAAAAAAAAAAABBBBBBBBAB LETTER ALPSLFMDEEMCBFRSPKLEMFHRSCJLJKUHPNMBBNNVVRKRHUTDJUKANJHBTPDFSVDEVU SIDE 121212122121212121111111112212122222112222111221112112212112212212 DIRECTION IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIOOOOOOOIOOIOOIOOIOOOOIOOIIOOIIO source: 0 changed: 0 step 98 100001100110100100011011011011011101111100011011011010100110110011 fail ^^ space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C toggle comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT BAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBAABBAAAAAAAAAAAAAABBBBBBBBAB LETTER ALPSLFMDEEMCBFRSPKLEMFHRSCJLJKUHPNMBBNNVVRKRHUTDJUKANJHBTPDFSVDEVU SIDE 121212122121212121111111112212122222112222111221112112212112212212 DIRECTION IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIOOOOOOOIOOIOOIOOIOOOOIOOIIOOIIO source: ; shift in 0, expect 10 source: 1010 changed: 0110 step 99 100001100110100100011011011011011101111100011011011010100110101101 fail ^^ space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C toggle comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT BAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBAABBAAAAAAAAAAAAAABBBBBBBBAB LETTER ALPSLFMDEEMCBFRSPKLEMFHRSCJLJKUHPNMBBNNVVRKRHUTDJUKANJHBTPDFSVDEVU SIDE 121212122121212121111111112212122222112222111221112112212112212212 DIRECTION IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIOOOOOOOIOOIOOIOOIOOOOIOOIIOOIIO source: 0 changed: 0 step 100 100001100110100100011011011011011101111100011011011010100110101001 fail ^^ space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C toggle comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT BAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBAABBAAAAAAAAAAAAAABBBBBBBBAB LETTER ALPSLFMDEEMCBFRSPKLEMFHRSCJLJKUHPNMBBNNVVRKRHUTDJUKANJHBTPDFSVDEVU SIDE 121212122121212121111111112212122222112222111221112112212112212212 DIRECTION IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIOOOOOOOIOOIOOIOOIOOOOIOOIIOOIIO source: ; shift in 1, expect 01 source: 0111 changed: 1011 step 101 100001100110100100011011011011011101111100011011011010100110110111 fail ^^ space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C toggle comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT BAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBAABBAAAAAAAAAAAAAABBBBBBBBAB LETTER ALPSLFMDEEMCBFRSPKLEMFHRSCJLJKUHPNMBBNNVVRKRHUTDJUKANJHBTPDFSVDEVU SIDE 121212122121212121111111112212122222112222111221112112212112212212 DIRECTION IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIOOOOOOOIOOIOOIOOIOOOOIOOIIOOIIO source: 0 changed: 0 step 102 100001100110100100011011011011011101111100011011011010100110110011 fail ^^ space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C toggle comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT BAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBAABBAAAAAAAAAAAAAABBBBBBBBAB LETTER ALPSLFMDEEMCBFRSPKLEMFHRSCJLJKUHPNMBBNNVVRKRHUTDJUKANJHBTPDFSVDEVU SIDE 121212122121212121111111112212122222112222111221112112212112212212 DIRECTION IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIOOOOOOOIOOIOOIOOIOOOOIOOIIOOIIO source: ; shift in 1, expect 10 source: 1011 changed: 011 step 103 100001100110100100011011011011011101111100011011011010100110101111 fail ^^ space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C toggle comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT BAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBAABBAAAAAAAAAAAAAABBBBBBBBAB LETTER ALPSLFMDEEMCBFRSPKLEMFHRSCJLJKUHPNMBBNNVVRKRHUTDJUKANJHBTPDFSVDEVU SIDE 121212122121212121111111112212122222112222111221112112212112212212 DIRECTION IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIOOOOOOOIOOIOOIOOIOOOOIOOIIOOIIO source: 0 changed: 0 step 104 100001100110100100011011011011011101111100011011011010100110101011 fail ^^ test 1: *** FAIL *************************** 14 steps failed SLOT BAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBAABBAAAAAAAAAAAAAABBBBBBBBAB LETTER ALPSLFMDEEMCBFRSPKLEMFHRSCJLJKUHPNMBBNNVVRKRHUTDJUKANJHBTPDFSVDEVU SIDE 121212122121212121111111112212122222112222111221112112212112212212 DIRECTION IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIOOOOOOOIOOIOOIOOIOOOOIOOIIOOIIO this fail OO all fails OO was hi 111111111111111111111111111111111111111111111111111111111111111111 rising ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ ^^^^^^^^^^^^^ ^ ^^^^ ^^^^ falling vvvv vv v vv vvv v v v v vvvvv vvv vv vv v v vv vv vvvv was lo 00000000000000000000000000000000000000 00000000000000000000 0000 total fails 1, total passes 0 space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C toggle comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit source: ; all registers are unknown source: ; turn on C0, PHASE source: ; with no ENABLES, BUS2,BUS3 is 11, C2 is 1 source: 1000000000000000000000000000000000011111000XX0XX0XX0XXXX0XX01XX001 changed: 00 00 0 0 00 00 00 00 000 0 step 1 100000000000000000000000000000000001111100011011011010100110101001 source: source: ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; source: ; source: ; set all registers LOW source: ; source: ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; source: source: ; load TMA SETUP from tape bus (00) source: 100 changed: 100 step 2 100000000000000000000000000000000001111100100011011010100110101001 source: 0 changed: 0 step 3 100000000000000000000000000000000001111100000011011010100110101001 source: ; load TMA from tape bus (00) source: 100 changed: 100 step 4 100000000000000000000000000000000001111100000100011010100110101001 source: 0 changed: 0 step 5 100000000000000000000000000000000001111100000000011010100110101001 source: ; load TBN from tape bus (00) source: 100 changed: 100 step 6 100000000000000000000000000000000001111100000000100010100110101001 source: 0 changed: 0 step 7 100000000000000000000000000000000001111100000000000010100110101001 source: ; load TAC from tape bus (00) source: 10101 changed: 10101 step 8 100000000000000000000000000000000001111100000000000101010110101001 source: 0 changed: 0 step 9 100000000000000000000000000000000001111100000000000001010110101001 source: ; load TB from tape bus (00) source: 100 changed: 100 step 10 100000000000000000000000000000000001111100000000000001011000101001 source: 0 changed: 0 step 11 100000000000000000000000000000000001111100000000000001010000101001 source: ; load RWB from TB (JAMS CLEAR AND PRESET) source: 1 00 changed: 1 0 step 12 100000000000000000000000000000000001111100000000000001010001100001 source: 0 changed: 0 step 13 100000000000000000000000000000000001111100000000000001010000100001 source: ; (no change) source: 100000000000000000000000000000000001111100000000000001010000100001 changed: step 14 100000000000000000000000000000000001111100000000000001010000100001 source: source: source: ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; source: ; source: ; set all registers HIGH source: ; source: ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; source: source: ; set pin AF1 (AND with itself) to clear pin BB2 (AND-NOR output) and set pin BR2 TAPE BUS 3 OUTPUT source: 1 0 1 changed: 1 0 1 step 15 100000000000010000000000000000000000111101000000000001010000100001 source: ; set pin AP2 (AND with itself) to clear pin AN2 (AND-NOR output) and set pin BV2 TAPE BUS 2 OUTPUT source: 1 0 1 changed: 1 0 1 step 16 100000000000010010000000000000000000110111000000000001010000100001 source: source: source: ; load TMA SETUP from tape bus (11) source: 111 changed: 111 step 17 100000000000010010000000000000000000110111111000000001010000100001 source: 0 changed: 0 step 18 100000000000010010000000000000000000110111011000000001010000100001 source: ; load TMA from tape bus (11) source: 111 changed: 111 step 19 100000000000010010000000000000000000110111011111000001010000100001 space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C toggle comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit source: 0 changed: 0 step 20 100000000000010010000000000000000000110111011011000001010000100001 source: ; load TBN from tape bus (11) source: 111 changed: 111 step 21 100000000000010010000000000000000000110111011011111001010000100001 source: 0 changed: 0 step 22 100000000000010010000000000000000000110111011011011001010000100001 source: ; load TAC from tape bus (11) source: 11010 changed: 11010 step 23 100000000000010010000000000000000000110111011011011110100000100001 source: 0 changed: 0 step 24 100000000000010010000000000000000000110111011011011010100000100001 source: ; load TB from tape bus (11) source: 111 changed: 111 step 25 100000000000010010000000000000000000110111011011011010101110100001 source: 0 changed: 0 step 26 100000000000010010000000000000000000110111011011011010100110100001 source: ; load RWB from TB (JAMS CLEAR AND PRESET) source: 1 11 changed: 1 11 step 27 100000000000010010000000000000000000110111011011011010100111111001 source: 0 changed: 0 step 28 100000000000010010000000000000000000110111011011011010100110111001 source: ; clear pin AF1 (AND with itself) to set pin BB2 (AND-NOR output) and clear pin BR2 TAPE BUS 3 OUTPUT source: 0 1 0 changed: 0 1 0 step 29 100000000000000010000000000000000001110110011011011010100110111001 source: ; clear pin AP2 (AND with itself) to set pin AN2 (AND-NOR output) and clear pin BV2 TAPE BUS 2 OUTPUT source: 0 1 0 changed: 0 1 0 step 30 100000000000000000000000000000000001111100011011011010100110111001 source: ; (no change) source: 100000000000000000000000000000000001111100011011011010100110111001 changed: step 31 100000000000000000000000000000000001111100011011011010100110111001 source: source: source: ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; source: ; source: ; test AND-NOR logic source: ; source: ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; source: source: ; (all registers are HIGH) source: ; set all pins HIGH except ENABLES source: source: ; set pin AF2 HIGH source: 1 changed: 1 step 32 100001000000000000000000000000000001111100011011011010100110111001 source: ; set pin AM1 HIGH source: 1 changed: 1 step 33 100001100000000000000000000000000001111100011011011010100110111001 source: ; set pin AE1 HIGH source: 1 changed: 1 step 34 100001100100000000000000000000000001111100011011011010100110111001 source: ; set pin AM2 HIGH source: 1 changed: 1 step 35 100001100110000000000000000000000001111100011011011010100110111001 source: ; set pin AB2 HIGH source: 1 changed: 1 step 36 100001100110100000000000000000000001111100011011011010100110111001 source: ; set pin AS1 HIGH source: 1 changed: 1 step 37 100001100110100100000000000000000001111100011011011010100110111001 source: ; set pin BE1 HIGH source: 1 changed: 1 step 38 100001100110100100010000000000000001111100011011011010100110111001 source: ; set pin BM1 HIGH source: 1 changed: 1 step 39 100001100110100100011000000000000001111100011011011010100110111001 source: ; set pin BH1 HIGH source: 1 changed: 1 step 40 100001100110100100011010000000000001111100011011011010100110111001 source: ; set pin BR1 HIGH source: 1 changed: 1 step 41 100001100110100100011011000000000001111100011011011010100110111001 source: ; set pin BC1 HIGH source: 1 changed: 1 step 42 100001100110100100011011010000000001111100011011011010100110111001 source: ; set pin BJ2 HIGH source: 1 changed: 1 step 43 100001100110100100011011011000000001111100011011011010100110111001 source: ; set pin BJ1 HIGH source: 1 changed: 1 step 44 100001100110100100011011011010000001111100011011011010100110111001 source: ; set pin BK2 HIGH source: 1 changed: 1 step 45 100001100110100100011011011011000001111100011011011010100110111001 source: ; set pin BH2 HIGH source: 1 changed: 1 step 46 100001100110100100011011011011010001111100011011011010100110111001 source: ; set pin BP2 HIGH source: 1 changed: 1 step 47 100001100110100100011011011011011001111100011011011010100110111001 source: ; set pin BN2 HIGH source: 1 changed: 1 step 48 100001100110100100011011011011011101111100011011011010100110111001 source: ; toggle each ENABLE source: source: ; set pin AL2 to clear pin BB2 and pin AN2 AND-NOR OUTPUTS and set TAPE BUS 2 OUTPUT and TAPE BUS 3 OUTPUT source: 1 0 0 11 changed: 1 0 0 11 step 49 110001100110100100011011011011011100110111011011011010100110111001 source: 0 1 1 00 changed: 0 1 1 00 step 50 100001100110100100011011011011011101111100011011011010100110111001 source: ; set pin AP1 to clear pin BB2 and pin AN2 AND-NOR OUTPUTS and set TAPE BUS 2 OUTPUT and TAPE BUS 3 OUTPUT source: 1 0 0 11 changed: 1 0 0 11 step 51 101001100110100100011011011011011100110111011011011010100110111001 source: 0 1 1 00 changed: 0 1 1 00 step 52 100001100110100100011011011011011101111100011011011010100110111001 source: ; set pin AS2 to clear pin BB2 and pin AN2 AND-NOR OUTPUTS and set TAPE BUS 2 OUTPUT and TAPE BUS 3 OUTPUT source: 1 0 0 11 changed: 1 0 0 11 step 53 100101100110100100011011011011011100110111011011011010100110111001 source: 0 1 1 00 changed: 0 1 1 00 step 54 100001100110100100011011011011011101111100011011011010100110111001 source: ; set pin AL1 to clear pin BB2 and pin AN2 AND-NOR OUTPUTS and set TAPE BUS 2 OUTPUT and TAPE BUS 3 OUTPUT source: 1 0 0 11 changed: 1 0 0 11 step 55 100011100110100100011011011011011100110111011011011010100110111001 source: 0 1 1 00 changed: 0 1 1 00 step 56 100001100110100100011011011011011101111100011011011010100110111001 source: ; set pin AL1 to clear pin BB2 and pin AN2 AND-NOR OUTPUTS and set TAPE BUS 2 OUTPUT and TAPE BUS 3 OUTPUT source: 1 0 0 11 changed: 1 0 0 11 step 57 100001110110100100011011011011011100110111011011011010100110111001 source: 0 1 1 00 changed: 0 1 1 00 step 58 100001100110100100011011011011011101111100011011011010100110111001 source: ; set pin AE2 to clear pin BB2 and pin AN2 AND-NOR OUTPUTS and set TAPE BUS 2 OUTPUT and TAPE BUS 3 OUTPUT source: 1 0 0 11 changed: 1 0 0 11 step 59 100001101110100100011011011011011100110111011011011010100110111001 source: 0 1 1 00 changed: 0 1 1 00 step 60 100001100110100100011011011011011101111100011011011010100110111001 source: ; set pin AC1 to clear pin BB2 and set TAPE BUS 3 OUTPUT source: 1 0 1 changed: 1 0 1 step 61 100001100111100100011011011011011100111101011011011010100110111001 source: 0 1 0 changed: 0 1 0 step 62 100001100110100100011011011011011101111100011011011010100110111001 source: ; set pin AF1 to clear pin BB2 and set TAPE BUS 3 OUTPUT source: 1 0 1 changed: 1 0 1 step 63 100001100110110100011011011011011100111101011011011010100110111001 source: 0 1 0 changed: 0 1 0 step 64 100001100110100100011011011011011101111100011011011010100110111001 source: ; set pin AR2 to clear pin AN2 AND-NOR OUTPUTS and set TAPE BUS 2 OUTPUT source: 1 0 1 changed: 1 0 1 step 65 100001100110101100011011011011011101110110011011011010100110111001 source: 0 1 0 changed: 0 1 0 step 66 100001100110100100011011011011011101111100011011011010100110111001 source: ; set pin AP2 to clear pin AN2 AND-NOR OUTPUTS and set TAPE BUS 2 OUTPUT source: 1 0 1 changed: 1 0 1 step 67 100001100110100110011011011011011101110110011011011010100110111001 source: 0 1 0 changed: 0 1 0 step 68 100001100110100100011011011011011101111100011011011010100110111001 source: source: ; set pin BK1 to clear pin BB1 and pin BN1 AND-NOR OUTPUTS and set TAPE BUS 2 OUTPUT and TAPE BUS 3 OUTPUT source: 1 00 11 changed: 1 00 11 step 69 100001100110100101011011011011011101001111011011011010100110111001 source: 0 11 00 changed: 0 11 00 step 70 100001100110100100011011011011011101111100011011011010100110111001 source: ; set pin BL1 to clear pin BB1 and pin BN1 AND-NOR OUTPUTS and set TAPE BUS 2 OUTPUT and TAPE BUS 3 OUTPUT source: 1 00 11 changed: 1 00 11 step 71 100001100110100100111011011011011101001111011011011010100110111001 source: 0 11 00 changed: 0 11 00 step 72 100001100110100100011011011011011101111100011011011010100110111001 source: ; set pin BF1 to clear pin BB1 and pin BN1 AND-NOR OUTPUTS and set TAPE BUS 2 OUTPUT and TAPE BUS 3 OUTPUT source: 1 00 11 changed: 1 00 11 step 73 100001100110100100011111011011011101001111011011011010100110111001 source: 0 11 00 changed: 0 11 00 step 74 100001100110100100011011011011011101111100011011011010100110111001 source: ; set pin BS1 to clear pin BB1 and pin BN1 AND-NOR OUTPUTS and set TAPE BUS 2 OUTPUT and TAPE BUS 3 OUTPUT source: 1 00 11 changed: 1 00 11 step 75 100001100110100100011011111011011101001111011011011010100110111001 source: 0 11 00 changed: 0 11 00 step 76 100001100110100100011011011011011101111100011011011010100110111001 source: ; set pin BL2 to clear pin BB1 and pin BN1 AND-NOR OUTPUTS and set TAPE BUS 2 OUTPUT and TAPE BUS 3 OUTPUT source: 1 00 11 changed: 1 00 11 step 77 100001100110100100011011011111011101001111011011011010100110111001 source: 0 11 00 changed: 0 11 00 step 78 100001100110100100011011011011011101111100011011011010100110111001 source: ; set pin BU1 to clear pin BB1 and pin BN1 AND-NOR OUTPUTS and set TAPE BUS 2 OUTPUT and TAPE BUS 3 OUTPUT source: 1 00 11 changed: 1 00 11 step 79 100001100110100100011011011011111101001111011011011010100110111001 source: 0 11 00 changed: 0 11 00 step 80 100001100110100100011011011011011101111100011011011010100110111001 source: ; set pin BM2 to clear pin BB1 and TAPE BUS 3 OUTPUT source: 1 0 1 changed: 1 0 1 step 81 100001100110100100011011011011011111101110011011011010100110111001 source: 0 1 0 changed: 0 1 0 step 82 100001100110100100011011011011011101111100011011011010100110111001 source: source: ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; source: ; test shifting the RWB source: ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; source: source: source: source: ; shift in 0, expect 10 source: 1010 changed: 01 step 83 100001100110100100011011011011011101111100011011011010100110110101 source: 0 changed: 0 step 84 100001100110100100011011011011011101111100011011011010100110110001 source: ; shift in 0, expect 00 source: 0010 changed: 0 1 step 85 100001100110100100011011011011011101111100011011011010100110100101 source: 0 changed: 0 step 86 100001100110100100011011011011011101111100011011011010100110100001 source: ; shift in 0, expect 00 source: 0010 changed: 1 step 87 100001100110100100011011011011011101111100011011011010100110100101 source: 0 changed: 0 step 88 100001100110100100011011011011011101111100011011011010100110100001 SLOT BAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBAABBAAAAAAAAAAAAAABBBBBBBBAB LETTER ALPSLFMDEEMCBFRSPKLEMFHRSCJLJKUHPNMBBNNVVRKRHUTDJUKANJHBTPDFSVDEVU SIDE 121212122121212121111111112212122222112222111221112112212112212212 DIRECTION IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIOOOOOOOIOOIOOIOOIOOOOIOOIIOOIIO source: ; shift in 1, expect 01 source: 0111 changed: 11 step 89 100001100110100100011011011011011101111100011011011010100110100111 fail ^ space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C toggle comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT BAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBAABBAAAAAAAAAAAAAABBBBBBBBAB LETTER ALPSLFMDEEMCBFRSPKLEMFHRSCJLJKUHPNMBBNNVVRKRHUTDJUKANJHBTPDFSVDEVU SIDE 121212122121212121111111112212122222112222111221112112212112212212 DIRECTION IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIOOOOOOOIOOIOOIOOIOOOOIOOIIOOIIO source: 0 changed: 0 step 90 100001100110100100011011011011011101111100011011011010100110100011 fail ^ space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C toggle comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT BAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBAABBAAAAAAAAAAAAAABBBBBBBBAB LETTER ALPSLFMDEEMCBFRSPKLEMFHRSCJLJKUHPNMBBNNVVRKRHUTDJUKANJHBTPDFSVDEVU SIDE 121212122121212121111111112212122222112222111221112112212112212212 DIRECTION IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIOOOOOOOIOOIOOIOOIOOOOIOOIIOOIIO source: ; shift in 1, expect 11 source: 1111 changed: 11 step 91 100001100110100100011011011011011101111100011011011010100110101111 fail ^ space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C toggle comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT BAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBAABBAAAAAAAAAAAAAABBBBBBBBAB LETTER ALPSLFMDEEMCBFRSPKLEMFHRSCJLJKUHPNMBBNNVVRKRHUTDJUKANJHBTPDFSVDEVU SIDE 121212122121212121111111112212122222112222111221112112212112212212 DIRECTION IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIOOOOOOOIOOIOOIOOIOOOOIOOIIOOIIO source: 0 changed: 0 step 92 100001100110100100011011011011011101111100011011011010100110101011 fail ^ space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C toggle comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit source: ; shift in 1, expect 11 source: 1111 changed: 1 1 step 93 100001100110100100011011011011011101111100011011011010100110111111 source: 0 changed: 0 step 94 100001100110100100011011011011011101111100011011011010100110111011 SLOT BAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBAABBAAAAAAAAAAAAAABBBBBBBBAB LETTER ALPSLFMDEEMCBFRSPKLEMFHRSCJLJKUHPNMBBNNVVRKRHUTDJUKANJHBTPDFSVDEVU SIDE 121212122121212121111111112212122222112222111221112112212112212212 DIRECTION IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIOOOOOOOIOOIOOIOOIOOOOIOOIIOOIIO source: ; shift in 0, expect 10 source: 1010 changed: 10 step 95 100001100110100100011011011011011101111100011011011010100110111101 fail ^ space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C toggle comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT BAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBAABBAAAAAAAAAAAAAABBBBBBBBAB LETTER ALPSLFMDEEMCBFRSPKLEMFHRSCJLJKUHPNMBBNNVVRKRHUTDJUKANJHBTPDFSVDEVU SIDE 121212122121212121111111112212122222112222111221112112212112212212 DIRECTION IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIOOOOOOOIOOIOOIOOIOOOOIOOIIOOIIO source: 0 changed: 0 step 96 100001100110100100011011011011011101111100011011011010100110111001 fail ^ space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C toggle comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT BAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBAABBAAAAAAAAAAAAAABBBBBBBBAB LETTER ALPSLFMDEEMCBFRSPKLEMFHRSCJLJKUHPNMBBNNVVRKRHUTDJUKANJHBTPDFSVDEVU SIDE 121212122121212121111111112212122222112222111221112112212112212212 DIRECTION IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIOOOOOOOIOOIOOIOOIOOOOIOOIIOOIIO source: ; shift in 1, expect 01 source: 0111 changed: 011 step 97 100001100110100100011011011011011101111100011011011010100110110111 fail ^^ space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C toggle comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT BAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBAABBAAAAAAAAAAAAAABBBBBBBBAB LETTER ALPSLFMDEEMCBFRSPKLEMFHRSCJLJKUHPNMBBNNVVRKRHUTDJUKANJHBTPDFSVDEVU SIDE 121212122121212121111111112212122222112222111221112112212112212212 DIRECTION IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIOOOOOOOIOOIOOIOOIOOOOIOOIIOOIIO source: 0 changed: 0 step 98 100001100110100100011011011011011101111100011011011010100110110011 fail ^^ space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C toggle comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT BAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBAABBAAAAAAAAAAAAAABBBBBBBBAB LETTER ALPSLFMDEEMCBFRSPKLEMFHRSCJLJKUHPNMBBNNVVRKRHUTDJUKANJHBTPDFSVDEVU SIDE 121212122121212121111111112212122222112222111221112112212112212212 DIRECTION IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIOOOOOOOIOOIOOIOOIOOOOIOOIIOOIIO source: ; shift in 0, expect 10 source: 1010 changed: 0110 step 99 100001100110100100011011011011011101111100011011011010100110101101 fail ^^ space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C toggle comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT BAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBAABBAAAAAAAAAAAAAABBBBBBBBAB LETTER ALPSLFMDEEMCBFRSPKLEMFHRSCJLJKUHPNMBBNNVVRKRHUTDJUKANJHBTPDFSVDEVU SIDE 121212122121212121111111112212122222112222111221112112212112212212 DIRECTION IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIOOOOOOOIOOIOOIOOIOOOOIOOIIOOIIO source: 0 changed: 0 step 100 100001100110100100011011011011011101111100011011011010100110101001 fail ^^ space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C toggle comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT BAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBAABBAAAAAAAAAAAAAABBBBBBBBAB LETTER ALPSLFMDEEMCBFRSPKLEMFHRSCJLJKUHPNMBBNNVVRKRHUTDJUKANJHBTPDFSVDEVU SIDE 121212122121212121111111112212122222112222111221112112212112212212 DIRECTION IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIOOOOOOOIOOIOOIOOIOOOOIOOIIOOIIO source: ; shift in 1, expect 01 source: 0111 changed: 00000 00 00 00 0 00 0110 step 101 100001100110100100011011011011011100000000000000000010000000100110 fail ^^^^^ ^^ ^^ ^^ ^ ^^ ^ ^ space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C toggle comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT BAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBAABBAAAAAAAAAAAAAABBBBBBBBAB LETTER ALPSLFMDEEMCBFRSPKLEMFHRSCJLJKUHPNMBBNNVVRKRHUTDJUKANJHBTPDFSVDEVU SIDE 121212122121212121111111112212122222112222111221112112212112212212 DIRECTION IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIOOOOOOOIOOIOOIOOIOOOOIOOIIOOIIO all fails OOOOO OO OO OO O OO OO O was lo 00000000000000000000000000000000000000000000000000000000000 00000 falling vvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvv vvvvv rising ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ ^^^^^^^^^^^^^^^^^^^^ ^^^^ was hi 111111111111111111111111111111111111111111111111111111111111111111 total fails 1, total passes 0 Main menu Mon Jul 27 17:34:40 2015 test file is: tests\m222.new delay is: 0 trigger is: 1 1 read test file 2 set test delay 3 set test trigger 4 run test 5 output loading test 8 diags 9 exit UUT power is okay Mon Jul 27 17:34:56 2015 space single step O run once (one test, all steps) F run, stop on fail G go (run tests N run, stop on fail, no print S scope (run, no print) C toggle comment printout + increase speed (less delay) - decrease speed (more delay)(slower) Q quit test step 1 100000000000000000000000000000000001111100010011011010100110111001 step 2 100000000000000000000000000000000001111100100011011010100110111001 step 3 100000000000000000000000000000000001111100000011011010100110111001 step 4 100000000000000000000000000000000001111100000100011010100110111001 step 5 100000000000000000000000000000000001111100000000011010100110111001 step 6 100000000000000000000000000000000001111100000000100010100110111001 step 7 100000000000000000000000000000000001111100000000000010100110111001 step 8 100000000000000000000000000000000001111100000000000101010110111001 step 9 100000000000000000000000000000000001111100000000000001010110111001 step 10 100000000000000000000000000000000001111100000000000001011000111001 step 11 100000000000000000000000000000000001111100000000000001010000111001 step 12 100000000000000000000000000000000001111100000000000001010001100001 step 13 100000000000000000000000000000000001111100000000000001010000100001 step 14 100000000000000000000000000000000001111100000000000001010000100001 step 15 100000000000010000000000000000000000111101000000000001010000100001 step 16 100000000000010010000000000000000000110111000000000001010000100001 step 17 100000000000010010000000000000000000110111111000000001010000100001 step 18 100000000000010010000000000000000000110111011000000001010000100001 step 19 100000000000010010000000000000000000110111011111000001010000100001 step 20 100000000000010010000000000000000000110111011011000001010000100001 step 21 100000000000010010000000000000000000110111011011111001010000100001 step 22 100000000000010010000000000000000000110111011011011001010000100001 step 23 100000000000010010000000000000000000110111011011011110100000100001 step 24 100000000000010010000000000000000000110111011011011010100000100001 step 25 100000000000010010000000000000000000110111011011011010101110100001 step 26 100000000000010010000000000000000000110111011011011010100110100001 step 27 100000000000010010000000000000000000110111011011011010100111111001 step 28 100000000000010010000000000000000000110111011011011010100110111001 step 29 100000000000000010000000000000000001110110011011011010100110111001 step 30 100000000000000000000000000000000001111100011011011010100110111001 step 31 100000000000000000000000000000000001111100011011011010100110111001 step 32 100001000000000000000000000000000001111100011011011010100110111001 step 33 100001100000000000000000000000000001111100011011011010100110111001 step 34 100001100100000000000000000000000001111100011011011010100110111001 step 35 100001100110000000000000000000000001111100011011011010100110111001 step 36 100001100110100000000000000000000001111100011011011010100110111001 step 37 100001100110100100000000000000000001111100011011011010100110111001 step 38 100001100110100100010000000000000001111100011011011010100110111001 step 39 100001100110100100011000000000000001111100011011011010100110111001 step 40 100001100110100100011010000000000001111100011011011010100110111001 step 41 100001100110100100011011000000000001111100011011011010100110111001 step 42 100001100110100100011011010000000001111100011011011010100110111001 step 43 100001100110100100011011011000000001111100011011011010100110111001 step 44 100001100110100100011011011010000001111100011011011010100110111001 step 45 100001100110100100011011011011000001111100011011011010100110111001 step 46 100001100110100100011011011011010001111100011011011010100110111001 step 47 100001100110100100011011011011011001111100011011011010100110111001 step 48 100001100110100100011011011011011101111100011011011010100110111001 step 49 110001100110100100011011011011011100110111011011011010100110111001 step 50 100001100110100100011011011011011101111100011011011010100110111001 step 51 101001100110100100011011011011011100110111011011011010100110111001 step 52 100001100110100100011011011011011101111100011011011010100110111001 step 53 100101100110100100011011011011011100110111011011011010100110111001 step 54 100001100110100100011011011011011101111100011011011010100110111001 step 55 100011100110100100011011011011011100110111011011011010100110111001 step 56 100001100110100100011011011011011101111100011011011010100110111001 step 57 100001110110100100011011011011011100110111011011011010100110111001 step 58 100001100110100100011011011011011101111100011011011010100110111001 step 59 100001101110100100011011011011011100110111011011011010100110111001 step 60 100001100110100100011011011011011101111100011011011010100110111001 step 61 100001100111100100011011011011011100111101011011011010100110111001 step 62 100001100110100100011011011011011101111100011011011010100110111001 step 63 100001100110110100011011011011011100111101011011011010100110111001 step 64 100001100110100100011011011011011101111100011011011010100110111001 step 65 100001100110101100011011011011011101110110011011011010100110111001 step 66 100001100110100100011011011011011101111100011011011010100110111001 step 67 100001100110100110011011011011011101110110011011011010100110111001 step 68 100001100110100100011011011011011101111100011011011010100110111001 step 69 100001100110100101011011011011011101001111011011011010100110111001 step 70 100001100110100100011011011011011101111100011011011010100110111001 step 71 100001100110100100111011011011011101001111011011011010100110111001 step 72 100001100110100100011011011011011101111100011011011010100110111001 step 73 100001100110100100011111011011011101001111011011011010100110111001 step 74 100001100110100100011011011011011101111100011011011010100110111001 step 75 100001100110100100011011111011011101001111011011011010100110111001 step 76 100001100110100100011011011011011101111100011011011010100110111001 step 77 100001100110100100011011011111011101001111011011011010100110111001 step 78 100001100110100100011011011011011101111100011011011010100110111001 step 79 100001100110100100011011011011111101001111011011011010100110111001 step 80 100001100110100100011011011011011101111100011011011010100110111001 step 81 100001100110100100011011011011011111101110011011011010100110111001 step 82 100001100110100100011011011011011101111100011011011010100110111001 step 83 100001100110100100011011011011011101111100011011011010100110110101 step 84 100001100110100100011011011011011101111100011011011010100110110001 step 85 100001100110100100011011011011011101111100011011011010100110100101 step 86 100001100110100100011011011011011101111100011011011010100110100001 step 87 100001100110100100011011011011011101111100011011011010100110100101 step 88 100001100110100100011011011011011101111100011011011010100110100001 SLOT BAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBAABBAAAAAAAAAAAAAABBBBBBBBAB LETTER ALPSLFMDEEMCBFRSPKLEMFHRSCJLJKUHPNMBBNNVVRKRHUTDJUKANJHBTPDFSVDEVU SIDE 121212122121212121111111112212122222112222111221112112212112212212 DIRECTION IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIOOOOOOOIOOIOOIOOIOOOOIOOIIOOIIO changed: 11 step 89 100001100110100100011011011011011101111100011011011010100110100111 fail ^ space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C toggle comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT BAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBAABBAAAAAAAAAAAAAABBBBBBBBAB LETTER ALPSLFMDEEMCBFRSPKLEMFHRSCJLJKUHPNMBBNNVVRKRHUTDJUKANJHBTPDFSVDEVU SIDE 121212122121212121111111112212122222112222111221112112212112212212 DIRECTION IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIOOOOOOOIOOIOOIOOIOOOOIOOIIOOIIO all fails O was lo 00000000000000000000000000000000000000 00000000000000000000 0000 falling vvvv vv v vv vvv v v v v vvvvv vvvv vvvvvvvvvvvvvvv vvv rising ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ ^^^^^^^^^^^^^^^^^^^^ ^^^^ was hi 111111111111111111111111111111111111111111111111111111111111111111 total fails 0, total passes 0 Main menu Mon Jul 27 17:35:09 2015 test file is: tests\m222.new delay is: 0 trigger is: 1 1 read test file 2 set test delay 3 set test trigger 4 run test 5 output loading test 8 diags 9 exit exiting tester- PDP8 card tester via printer port version 0.85 June 4, 2015 mapping[] is verified Main menu Mon Jul 27 17:37:23 2015 test file is: delay is: 0 trigger is: 1 1 read test file 2 set test delay 3 set test trigger 4 run test 5 output loading test 8 diags 9 exit Enter test file name? trying to open test file: tests\m222.new reading test file: tests\m222.new comment: M222 PCB REV B SCHEMATIC REV A LINC TAPE REGISTERS comment: comment: TERMINOLOGY- SIGNALS REFER TO VOL4 M222 SCHEMATIC. comment: comment: BUT... comment: comment: DEC USES AND-NOR GATES TO ROUTE THE ADDER A AND B INPUTS, SO... comment: DEC RENAMED THE ADDER TO NEGATIVE LOGIC TERMS (I.E. A-N + B-N + C-N -> SUM-N, C1-N). comment: (NOT THE 7482 DATASHEET NAMES OF A + B + C -> SUM, C1). comment: comment: SO, WITH ALL 'AND ENABLES' LOW, THE AND-NOR OUTPUTS = HIGH. comment: WITH C-L HIGH, THE ADDER OUTPUT IS SUM-N=1, C1-N=1; comment: THE INVERTED ADDER OUTPUT IS LOW (TAPE BUS). comment: AND THERE IS NO CARRY (C1-N IS HI). comment: comment: THE TWO ADDERS, TWO REGISTER BITS, ETC ARE LABELED BIT 2 (EVEN, MSB) AND BIT 3 (ODD, LSB). comment: THE ADDERS ARE REFERRED TO AS 'ADDER2' (MSB) AND 'ADDER3' (LSB). comment: comment: POWER PINS: comment: AA2 +5V comment: AT1 GROUND comment: AC2 GROUND comment: BA2 +5V comment: BT1 GROUND comment: BC2 GROUND comment: comment: (ALL PINS ARE USED). comment: comment: pins: PINS pins: 1 I BA1 CARRY IN-N, (TO E9-5 7482 C0) C-N TO ADDER2 pins: 2 I AL2 AND-NOR ENABLE: TAC TAC3 TO PIN BB2 (TO ADDER3) TAC2 TO PIN AN2 (TO ADDER2) pins: 3 I AP1 AND-NOR ENABLE: TMA SETUP (TMAS)3 TO PIN BB2 (TO ADDER3), (TMAS)3 TO PIN AN2 (TO ADDER2) pins: 4 I AS2 AND-NOR ENABLE: TMA TMA3 TO PIN BB2 (TO ADDER3), TMA2 TO PIN AN2 (TO ADDER2) pins: 5 I AL1 AND-NOR ENABLE: PIN AF2 TO PIN BB2 (TO ADDER3), PIN AM1 TO PIN AN2 (TO ADDER2) pins: 6 I AF2 AND-NOR INPUT (AL1 ENABLES) TO PIN BB2 (TO ADDER3). pins: 7 I AM1 AND-NOR INPUT (AL1 ENABLES) TO PIN AN2 (TO ADDER2) pins: 8 I AD2 AND-NOR ENABLE: RWB RWB3 TO PIN BB2 (TO ADDER3), RWB2 TO PIN AN2 (TO ADDER2) pins: 9 I AE2 AND-NOR ENABLE: PIN AE1 TO PIN BB2 (TO ADDER3), PIN AM2 TO PIN AN2 (TO ADDER2) pins: 10 I AE1 AND-NOR INPUT (AE2 ENABLES) TO PIN BB2 (TO ADDER3). pins: 11 I AM2 AND-NOR INPUT (AE2 ENABLES) TO PIN AN2 (TO ADDER2) pins: 12 I AC1 AND-NOR INPUT, AND WITH PIN AB2 TO PIN BB2 (TO ADDER3) pins: 13 I AB2 AND-NOR INPUT, AND WITH PIN AC1 TO PIN BB2 (TO ADDER3) pins: 14 I AF1 AND-NOR INPUT (AND WITH ITSELF) TO PIN BB2 (TO ADDER3) pins: 15 I AR2 AND-NOR INPUT, AND WITH PIN AS1 TO PIN AN2 (TO ADDER2) pins: 16 I AS1 AND-NOR INPUT, AND WITH PIN AR2 TO PIN AN2 (TO ADDER2) pins: 17 I AP2 AND-NOR INPUT (AND WITH ITSELF) TO PIN AN2 (TO ADDER2) pins: 18 I BK1 AND-NOR ENABLE: TB3 TO PIN BB1 (TO ADDER3), TB2 TO PIN BN1 (TO ADDER2) pins: 19 I BL1 AND-NOR ENABLE: PIN BE1 TO PIN BB1 (TO ADDER3), PIN BM1 TO PIN BN1 (TO ADDER2) pins: 20 I BE1 AND-NOR INPUT (BL1 ENABLES) TO PIN BB1 (TO ADDER3). pins: 21 I BM1 AND-NOR INPUT (BL1 ENABLES) TO PIN BN1 (TO ADDER2) pins: 22 I BF1 AND-NOR ENABLE: PIN BH1 TO PIN BB1 (TO ADDER3), PIN BR1 TO PIN BN1 (TO ADDER2) pins: 23 I BH1 AND-NOR INPUT (BF1 ENABLES): TO PIN BB1 (TO ADDER3), pins: 24 I BR1 AND-NOR INPUT (BF1 ENABLES): TO PIN BN1 (TO ADDER2) pins: 25 I BS1 AND-NOR ENABLE: PIN BC1 TO PIN BB1 (TO ADDER3), PIN BJ2 TO PIN BN1 (TO ADDER2) pins: 26 I BC1 AND-NOR INPUT (BS1 ENABLES): TO PIN BB1 (TO ADDER3), pins: 27 I BJ2 AND-NOR INPUT (BS1 ENABLES): TO PIN BN1 (TO ADDER2) pins: 28 I BL2 AND-NOR ENABLE: PIN BJ1 TO PIN BB1 (TO ADDER3), PIN BK2 TO PIN BN1 (TO ADDER2) pins: 29 I BJ1 AND-NOR INPUT (BL2 ENABLES): TO PIN BB1 (TO ADDER3), pins: 30 I BK2 AND-NOR INPUT (BL2 ENABLES): TO PIN BN1 (TO ADDER2) pins: 31 I BU1 AND-NOR ENABLE: PIN BH2 TO PIN BB1 (TO ADDER3), PIN BP2 TO PIN BN1 (TO ADDER2) pins: 32 I BH2 AND-NOR INPUT (BU1 ENABLES): TO PIN BB1 (TO ADDER3), pins: 33 I BP2 AND-NOR INPUT (BU1 ENABLES): TO PIN BN1 (TO ADDER2) pins: 34 I BN2 AND-NOR INPUT (AND WITH BM2): TO PIN BN1 (TO ADDER2) pins: 35 I BM2 AND-NOR INPUT (AND WITH BM2): TO PIN BN1 (TO ADDER2) pins: 36 O BB2 AND-NOR OUTPUT, (DRIVES E9-2 7482 A1) TO ADDER3 INPUT pins: 37 O BB1 AND-NOR OUTPUT, (DRIVES E9-3 7482 B1) TO ADDER3 INPUT pins: 38 O BN1 AND-NOR OUTPUT, (DRIVES E9-14 7482 A2) TO ADDER2 INPUT pins: 39 O AN2 AND-NOR OUTPUT, (DRIVES E9-13 7482 B2) TO ADDER2 INPUT pins: 40 O AV2 CARRY OUT-N (E9-10 7482 C2) pins: 41 O BV2 TAPE BUS 2 OUTPUT (INVERTED ADDER2 SUM-N (E9-12 7482 SUM2) pins: 42 O BR2 TAPE BUS 3 OUTPUT (INVERTED ADDER3 SUM-N (E9-1 7482 SUM1) pins: 43 I AK1 LOAD TMA SETUP (FROM TAPE BUS) (RISING EDGE CLOCK) pins: 44 O AR1 TMA SETUP 2 pins: 45 O AH1 TMA SETUP 3 pins: 46 I AU2 LOAD TMA (FROM TAPE BUS) (RISING EDGE CLOCK) pins: 47 O AT2 TMA 2 pins: 48 O AD1 TMA 3 pins: 49 I AJ1 LOAD TBN (FROM TAPE BUS) (RISING EDGE CLOCK) pins: 50 O AU1 TBN 2 pins: 51 O AK2 TBN 3 pins: 52 I AA1 LOAD TAC (FROM TAPE BUS) (RISING EDGE CLOCK) pins: 53 O AN1 TAC 2 pins: 54 O AJ2 TAC 2-N pins: 55 O AH2 TAC 3 pins: 56 O AB1 TAC 3-N pins: 57 I BT2 LOAD TB (FROM TAPE BUS) (RISING EDGE CLOCK) pins: 58 O BP1 TB 2 pins: 59 O BD1 TB 3 pins: 60 I BF2 LOAD RWB (FROM TB) (JAMS CLEAR,SET) pins: 61 I BS2 PHASE (SELECTS POLARITY OF RWB OUT, 0 -> INVERTED) pins: 62 O BV1 RWB OUT (=RWB 2 IF PHASE=1; =RWB 2-N IF PHASE=0) pins: 63 O BD2 RWB 3 pins: 64 I BE2 SHIFT RWB (SHIFTS PIN AV1 INTO RWB 3, SHIFTS RWB3 TO RWB2) (RISING CLOCK) pins: 65 I AV1 RWB IN (SHIFTED INTO RWB 2) pins: 66 O BU2 +3.5V pins: direction: IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIOOOOOOOIOOIOOIOOIOOOOIOOIIOOIIO comment: ; all registers are unknown comment: ; turn on C0, PHASE comment: ; with no ENABLES, BUS2,BUS3 is 11, C2 is 1 test 1: 1000000000000000000000000000000000011111000XX0XX0XX0XXXX0XX01XX001 comment: comment: ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; comment: ; comment: ; set all registers LOW comment: ; comment: ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; comment: comment: ; load TMA SETUP from tape bus (00) test 2: 100 test 3: 0 comment: ; load TMA from tape bus (00) test 4: 100 test 5: 0 comment: ; load TBN from tape bus (00) test 6: 100 test 7: 0 comment: ; load TAC from tape bus (00) test 8: 10101 test 9: 0 comment: ; load TB from tape bus (00) test 10: 100 test 11: 0 comment: ; load RWB from TB (JAMS CLEAR AND PRESET) test 12: 1 00 test 13: 0 comment: ; (no change) test 14: 100000000000000000000000000000000001111100000000000001010000100001 comment: comment: comment: ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; comment: ; comment: ; set all registers HIGH comment: ; comment: ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; comment: comment: ; set pin AF1 (AND with itself) to clear pin BB2 (AND-NOR output) and set pin BR2 TAPE BUS 3 OUTPUT test 15: 1 0 1 comment: ; set pin AP2 (AND with itself) to clear pin AN2 (AND-NOR output) and set pin BV2 TAPE BUS 2 OUTPUT test 16: 1 0 1 comment: comment: comment: ; load TMA SETUP from tape bus (11) test 17: 111 test 18: 0 comment: ; load TMA from tape bus (11) test 19: 111 test 20: 0 comment: ; load TBN from tape bus (11) test 21: 111 test 22: 0 comment: ; load TAC from tape bus (11) test 23: 11010 test 24: 0 comment: ; load TB from tape bus (11) test 25: 111 test 26: 0 comment: ; load RWB from TB (JAMS CLEAR AND PRESET) test 27: 1 11 test 28: 0 comment: ; clear pin AF1 (AND with itself) to set pin BB2 (AND-NOR output) and clear pin BR2 TAPE BUS 3 OUTPUT test 29: 0 1 0 comment: ; clear pin AP2 (AND with itself) to set pin AN2 (AND-NOR output) and clear pin BV2 TAPE BUS 2 OUTPUT test 30: 0 1 0 comment: ; (no change) test 31: 100000000000000000000000000000000001111100011011011010100110111001 comment: comment: comment: ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; comment: ; comment: ; test AND-NOR logic comment: ; comment: ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; comment: comment: ; (all registers are HIGH) comment: ; set all pins HIGH except ENABLES comment: comment: ; set pin AF2 HIGH test 32: 1 comment: ; set pin AM1 HIGH test 33: 1 comment: ; set pin AE1 HIGH test 34: 1 comment: ; set pin AM2 HIGH test 35: 1 comment: ; set pin AB2 HIGH test 36: 1 comment: ; set pin AS1 HIGH test 37: 1 comment: ; set pin BE1 HIGH test 38: 1 comment: ; set pin BM1 HIGH test 39: 1 comment: ; set pin BH1 HIGH test 40: 1 comment: ; set pin BR1 HIGH test 41: 1 comment: ; set pin BC1 HIGH test 42: 1 comment: ; set pin BJ2 HIGH test 43: 1 comment: ; set pin BJ1 HIGH test 44: 1 comment: ; set pin BK2 HIGH test 45: 1 comment: ; set pin BH2 HIGH test 46: 1 comment: ; set pin BP2 HIGH test 47: 1 comment: ; set pin BN2 HIGH test 48: 1 comment: ; toggle each ENABLE comment: comment: ; set pin AL2 to clear pin BB2 and pin AN2 AND-NOR OUTPUTS and set TAPE BUS 2 OUTPUT and TAPE BUS 3 OUTPUT test 49: 1 0 0 11 test 50: 0 1 1 00 comment: ; set pin AP1 to clear pin BB2 and pin AN2 AND-NOR OUTPUTS and set TAPE BUS 2 OUTPUT and TAPE BUS 3 OUTPUT test 51: 1 0 0 11 test 52: 0 1 1 00 comment: ; set pin AS2 to clear pin BB2 and pin AN2 AND-NOR OUTPUTS and set TAPE BUS 2 OUTPUT and TAPE BUS 3 OUTPUT test 53: 1 0 0 11 test 54: 0 1 1 00 comment: ; set pin AL1 to clear pin BB2 and pin AN2 AND-NOR OUTPUTS and set TAPE BUS 2 OUTPUT and TAPE BUS 3 OUTPUT test 55: 1 0 0 11 test 56: 0 1 1 00 comment: ; set pin AL1 to clear pin BB2 and pin AN2 AND-NOR OUTPUTS and set TAPE BUS 2 OUTPUT and TAPE BUS 3 OUTPUT test 57: 1 0 0 11 test 58: 0 1 1 00 comment: ; set pin AE2 to clear pin BB2 and pin AN2 AND-NOR OUTPUTS and set TAPE BUS 2 OUTPUT and TAPE BUS 3 OUTPUT test 59: 1 0 0 11 test 60: 0 1 1 00 comment: ; set pin AC1 to clear pin BB2 and set TAPE BUS 3 OUTPUT test 61: 1 0 1 test 62: 0 1 0 comment: ; set pin AF1 to clear pin BB2 and set TAPE BUS 3 OUTPUT test 63: 1 0 1 test 64: 0 1 0 comment: ; set pin AR2 to clear pin AN2 AND-NOR OUTPUTS and set TAPE BUS 2 OUTPUT test 65: 1 0 1 test 66: 0 1 0 comment: ; set pin AP2 to clear pin AN2 AND-NOR OUTPUTS and set TAPE BUS 2 OUTPUT test 67: 1 0 1 test 68: 0 1 0 comment: comment: ; set pin BK1 to clear pin BB1 and pin BN1 AND-NOR OUTPUTS and set TAPE BUS 2 OUTPUT and TAPE BUS 3 OUTPUT test 69: 1 00 11 test 70: 0 11 00 comment: ; set pin BL1 to clear pin BB1 and pin BN1 AND-NOR OUTPUTS and set TAPE BUS 2 OUTPUT and TAPE BUS 3 OUTPUT test 71: 1 00 11 test 72: 0 11 00 comment: ; set pin BF1 to clear pin BB1 and pin BN1 AND-NOR OUTPUTS and set TAPE BUS 2 OUTPUT and TAPE BUS 3 OUTPUT test 73: 1 00 11 test 74: 0 11 00 comment: ; set pin BS1 to clear pin BB1 and pin BN1 AND-NOR OUTPUTS and set TAPE BUS 2 OUTPUT and TAPE BUS 3 OUTPUT test 75: 1 00 11 test 76: 0 11 00 comment: ; set pin BL2 to clear pin BB1 and pin BN1 AND-NOR OUTPUTS and set TAPE BUS 2 OUTPUT and TAPE BUS 3 OUTPUT test 77: 1 00 11 test 78: 0 11 00 comment: ; set pin BU1 to clear pin BB1 and pin BN1 AND-NOR OUTPUTS and set TAPE BUS 2 OUTPUT and TAPE BUS 3 OUTPUT test 79: 1 00 11 test 80: 0 11 00 comment: ; set pin BM2 to clear pin BB1 and TAPE BUS 3 OUTPUT test 81: 1 0 1 test 82: 0 1 0 comment: comment: ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; comment: ; test shifting the RWB comment: ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; comment: comment: comment: comment: ; shift in 0, expect 10 test 83: 1010 test 84: 0 comment: ; shift in 0, expect 00 test 85: 0010 test 86: 0 comment: ; shift in 0, expect 00 test 87: 0010 test 88: 0 comment: ; shift in 1, expect 01 test 89: 0111 test 90: 0 comment: ; shift in 1, expect 11 test 91: 1111 test 92: 0 comment: ; shift in 1, expect 11 test 93: 1111 test 94: 0 comment: ; shift in 0, expect 10 test 95: 1010 test 96: 0 comment: ; shift in 1, expect 01 test 97: 0111 test 98: 0 comment: ; shift in 0, expect 10 test 99: 1010 test 100: 0 comment: ; shift in 1, expect 01 test 101: 0111 test 102: 0 comment: ; shift in 1, expect 10 test 103: 1011 test 104: 0 comment: ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; comment: ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; comment: ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; comment: ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; comment: ; needs work comment: ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; comment: ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; comment: ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; comment: ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; end: END summary column 1: offset 2, mask 0x2000 column 2: offset 1, mask 0x0002 column 3: offset 1, mask 0x0800 column 4: offset 1, mask 0x0040 column 5: offset 1, mask 0x4000 column 6: offset 0, mask 0x0004 column 7: offset 1, mask 0x2000 column 8: offset 0, mask 0x0010 column 9: offset 0, mask 0x0008 column 10: offset 0, mask 0x0800 column 11: offset 1, mask 0x0004 column 12: offset 0, mask 0x2000 column 13: offset 0, mask 0x0040 column 14: offset 0, mask 0x0400 column 15: offset 1, mask 0x0020 column 16: offset 1, mask 0x0200 column 17: offset 1, mask 0x0010 column 18: offset 3, mask 0x2000 column 19: offset 3, mask 0x1000 column 20: offset 2, mask 0x0200 column 21: offset 3, mask 0x0800 column 22: offset 2, mask 0x0100 column 23: offset 3, mask 0x8000 column 24: offset 3, mask 0x0100 column 25: offset 4, mask 0x8000 column 26: offset 2, mask 0x0800 column 27: offset 3, mask 0x0002 column 28: offset 3, mask 0x0008 column 29: offset 3, mask 0x4000 column 30: offset 3, mask 0x0004 column 31: offset 4, mask 0x2000 column 32: offset 3, mask 0x0001 column 33: offset 3, mask 0x0040 column 34: offset 3, mask 0x0020 column 35: offset 3, mask 0x0010 column 36: offset 2, mask 0x0008 column 37: offset 2, mask 0x1000 column 38: offset 3, mask 0x0400 column 39: offset 1, mask 0x0008 column 40: offset 2, mask 0x0002 column 41: offset 4, mask 0x0008 column 42: offset 3, mask 0x0080 column 43: offset 1, mask 0x8000 column 44: offset 1, mask 0x0400 column 45: offset 0, mask 0x0200 column 46: offset 2, mask 0x0001 column 47: offset 1, mask 0x0080 column 48: offset 0, mask 0x1000 column 49: offset 0, mask 0x0100 column 50: offset 2, mask 0x8000 column 51: offset 1, mask 0x0001 column 52: offset 0, mask 0x8000 column 53: offset 1, mask 0x1000 column 54: offset 0, mask 0x0001 column 55: offset 0, mask 0x0002 column 56: offset 0, mask 0x4000 column 57: offset 4, mask 0x0002 column 58: offset 3, mask 0x0200 column 59: offset 2, mask 0x0400 column 60: offset 2, mask 0x0080 column 61: offset 4, mask 0x0001 column 62: offset 4, mask 0x1000 column 63: offset 2, mask 0x0020 column 64: offset 2, mask 0x0040 column 65: offset 2, mask 0x4000 column 66: offset 4, mask 0x0004 direction bits (1=input) 0x52A3 0x1589 0x943A 0x0680 0x50FC pullup bits (1=pullup) 0x0000 0x0000 0x0000 0x0000 0x0000 test step out_data dont care 1: 0x0000 0x0008 0x300A 0x0400 0x0005 0x5203 0x1481 0x8420 0x0200 0x1000 2: 0x0000 0x8008 0x300A 0x0400 0x0005 0x5003 0x1081 0x8420 0x0200 0x1000 3: 0x0000 0x0008 0x300A 0x0400 0x0005 0x5003 0x1081 0x8420 0x0200 0x1000 4: 0x0000 0x0008 0x300B 0x0400 0x0005 0x4003 0x1001 0x8420 0x0200 0x1000 5: 0x0000 0x0008 0x300A 0x0400 0x0005 0x4003 0x1001 0x8420 0x0200 0x1000 6: 0x0100 0x0008 0x300A 0x0400 0x0005 0x4003 0x1000 0x0420 0x0200 0x1000 7: 0x0000 0x0008 0x300A 0x0400 0x0005 0x4003 0x1000 0x0420 0x0200 0x1000 8: 0xC001 0x0008 0x300A 0x0400 0x0005 0x0000 0x0000 0x0420 0x0200 0x1000 9: 0x4001 0x0008 0x300A 0x0400 0x0005 0x0000 0x0000 0x0420 0x0200 0x1000 10: 0x4001 0x0008 0x300A 0x0400 0x0007 0x0000 0x0000 0x0020 0x0000 0x1000 11: 0x4001 0x0008 0x300A 0x0400 0x0005 0x0000 0x0000 0x0020 0x0000 0x1000 12: 0x4001 0x0008 0x308A 0x0400 0x0005 13: 0x4001 0x0008 0x300A 0x0400 0x0005 14: 0x4001 0x0008 0x300A 0x0400 0x0005 15: 0x4401 0x0008 0x3002 0x0480 0x0005 16: 0x4401 0x0010 0x3002 0x0480 0x000D 17: 0x4601 0x8410 0x3002 0x0480 0x000D 18: 0x4601 0x0410 0x3002 0x0480 0x000D 19: 0x5601 0x0490 0x3003 0x0480 0x000D 20: 0x5601 0x0490 0x3002 0x0480 0x000D 21: 0x5701 0x0491 0xB002 0x0480 0x000D 22: 0x5601 0x0491 0xB002 0x0480 0x000D 23: 0x9602 0x1491 0xB002 0x0480 0x000D 24: 0x1602 0x1491 0xB002 0x0480 0x000D 25: 0x1602 0x1491 0xB402 0x0680 0x000F 26: 0x1602 0x1491 0xB402 0x0680 0x000D 27: 0x1602 0x1491 0xB4A2 0x0680 0x100D 28: 0x1602 0x1491 0xB422 0x0680 0x100D 29: 0x1202 0x1491 0xB42A 0x0600 0x100D 30: 0x1202 0x1489 0xB42A 0x0600 0x1005 31: 0x1202 0x1489 0xB42A 0x0600 0x1005 32: 0x1206 0x1489 0xB42A 0x0600 0x1005 33: 0x1206 0x3489 0xB42A 0x0600 0x1005 34: 0x1A06 0x3489 0xB42A 0x0600 0x1005 35: 0x1A06 0x348D 0xB42A 0x0600 0x1005 36: 0x1A46 0x348D 0xB42A 0x0600 0x1005 37: 0x1A46 0x368D 0xB42A 0x0600 0x1005 38: 0x1A46 0x368D 0xB62A 0x0600 0x1005 39: 0x1A46 0x368D 0xB62A 0x0E00 0x1005 40: 0x1A46 0x368D 0xB62A 0x8E00 0x1005 41: 0x1A46 0x368D 0xB62A 0x8F00 0x1005 42: 0x1A46 0x368D 0xBE2A 0x8F00 0x1005 43: 0x1A46 0x368D 0xBE2A 0x8F02 0x1005 44: 0x1A46 0x368D 0xBE2A 0xCF02 0x1005 45: 0x1A46 0x368D 0xBE2A 0xCF06 0x1005 46: 0x1A46 0x368D 0xBE2A 0xCF07 0x1005 47: 0x1A46 0x368D 0xBE2A 0xCF47 0x1005 48: 0x1A46 0x368D 0xBE2A 0xCF67 0x1005 49: 0x1A46 0x3687 0xBE22 0xCFE7 0x100D 50: 0x1A46 0x368D 0xBE2A 0xCF67 0x1005 51: 0x1A46 0x3E85 0xBE22 0xCFE7 0x100D 52: 0x1A46 0x368D 0xBE2A 0xCF67 0x1005 53: 0x1A46 0x36C5 0xBE22 0xCFE7 0x100D 54: 0x1A46 0x368D 0xBE2A 0xCF67 0x1005 55: 0x1A46 0x7685 0xBE22 0xCFE7 0x100D 56: 0x1A46 0x368D 0xBE2A 0xCF67 0x1005 57: 0x1A56 0x3685 0xBE22 0xCFE7 0x100D 58: 0x1A46 0x368D 0xBE2A 0xCF67 0x1005 59: 0x1A4E 0x3685 0xBE22 0xCFE7 0x100D 60: 0x1A46 0x368D 0xBE2A 0xCF67 0x1005 61: 0x3A46 0x368D 0xBE22 0xCFE7 0x1005 62: 0x1A46 0x368D 0xBE2A 0xCF67 0x1005 63: 0x1E46 0x368D 0xBE22 0xCFE7 0x1005 64: 0x1A46 0x368D 0xBE2A 0xCF67 0x1005 65: 0x1A46 0x36A5 0xBE2A 0xCF67 0x100D 66: 0x1A46 0x368D 0xBE2A 0xCF67 0x1005 67: 0x1A46 0x3695 0xBE2A 0xCF67 0x100D 68: 0x1A46 0x368D 0xBE2A 0xCF67 0x1005 69: 0x1A46 0x368D 0xAE2A 0xEBE7 0x100D 70: 0x1A46 0x368D 0xBE2A 0xCF67 0x1005 71: 0x1A46 0x368D 0xAE2A 0xDBE7 0x100D 72: 0x1A46 0x368D 0xBE2A 0xCF67 0x1005 73: 0x1A46 0x368D 0xAF2A 0xCBE7 0x100D 74: 0x1A46 0x368D 0xBE2A 0xCF67 0x1005 75: 0x1A46 0x368D 0xAE2A 0xCBE7 0x900D 76: 0x1A46 0x368D 0xBE2A 0xCF67 0x1005 77: 0x1A46 0x368D 0xAE2A 0xCBEF 0x100D 78: 0x1A46 0x368D 0xBE2A 0xCF67 0x1005 79: 0x1A46 0x368D 0xAE2A 0xCBE7 0x300D 80: 0x1A46 0x368D 0xBE2A 0xCF67 0x1005 81: 0x1A46 0x368D 0xBE2A 0xCB77 0x100D 82: 0x1A46 0x368D 0xBE2A 0xCF67 0x1005 83: 0x1A46 0x368D 0xBE4A 0xCF67 0x1005 84: 0x1A46 0x368D 0xBE0A 0xCF67 0x1005 85: 0x1A46 0x368D 0xBE4A 0xCF67 0x0005 86: 0x1A46 0x368D 0xBE0A 0xCF67 0x0005 87: 0x1A46 0x368D 0xBE4A 0xCF67 0x0005 88: 0x1A46 0x368D 0xBE0A 0xCF67 0x0005 89: 0x1A46 0x368D 0xFE6A 0xCF67 0x0005 90: 0x1A46 0x368D 0xFE2A 0xCF67 0x0005 91: 0x1A46 0x368D 0xFE6A 0xCF67 0x1005 92: 0x1A46 0x368D 0xFE2A 0xCF67 0x1005 93: 0x1A46 0x368D 0xFE6A 0xCF67 0x1005 94: 0x1A46 0x368D 0xFE2A 0xCF67 0x1005 95: 0x1A46 0x368D 0xBE4A 0xCF67 0x1005 96: 0x1A46 0x368D 0xBE0A 0xCF67 0x1005 97: 0x1A46 0x368D 0xFE6A 0xCF67 0x0005 98: 0x1A46 0x368D 0xFE2A 0xCF67 0x0005 99: 0x1A46 0x368D 0xBE4A 0xCF67 0x1005 100: 0x1A46 0x368D 0xBE0A 0xCF67 0x1005 101: 0x1A46 0x368D 0xFE6A 0xCF67 0x0005 102: 0x1A46 0x368D 0xFE2A 0xCF67 0x0005 103: 0x1A46 0x368D 0xFE4A 0xCF67 0x1005 104: 0x1A46 0x368D 0xFE0A 0xCF67 0x1005 PINs used (in edge connector order) (G=ground,P=power) SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBB LETTER ABCDEFHJKLMNPRSTUVABCDEFHJKLMNPRSTUVABCDEFHJKLMNPRSTUVABCDEFHJKLMNPRSTUV SIDE 111111111111111111222222222222222222111111111111111111222222222222222222 USAGE IOIOIIOIIIIOIOIGOIPIGIIIOOOIIOIIIOIOIOIOIIIIIIIOOIIGIOPOGOIIIIIIIIIOIIOO UUT has 44 inputs UUT has 22 outputs contains 66 pins/columns 0 pins are not used contains 104 'test steps' M222 PCB REV B SCHEMATIC REV A LINC TAPE REGISTERS TERMINOLOGY- SIGNALS REFER TO VOL4 M222 SCHEMATIC. BUT... DEC USES AND-NOR GATES TO ROUTE THE ADDER A AND B INPUTS, SO... DEC RENAMED THE ADDER TO NEGATIVE LOGIC TERMS (I.E. A-N + B-N + C-N -> SUM-N, C1-N). (NOT THE 7482 DATASHEET NAMES OF A + B + C -> SUM, C1). SO, WITH ALL 'AND ENABLES' LOW, THE AND-NOR OUTPUTS = HIGH. WITH C-L HIGH, THE ADDER OUTPUT IS SUM-N=1, C1-N=1; THE INVERTED ADDER OUTPUT IS LOW (TAPE BUS). AND THERE IS NO CARRY (C1-N IS HI). THE TWO ADDERS, TWO REGISTER BITS, ETC ARE LABELED BIT 2 (EVEN, MSB) AND BIT 3 (ODD, LSB). THE ADDERS ARE REFERRED TO AS 'ADDER2' (MSB) AND 'ADDER3' (LSB). POWER PINS: AA2 +5V AT1 GROUND AC2 GROUND BA2 +5V BT1 GROUND BC2 GROUND (ALL PINS ARE USED). PINS Main menu Mon Jul 27 17:37:29 2015 test file is: tests\m222.new delay is: 0 trigger is: 1 1 read test file 2 set test delay 3 set test trigger 4 run test 5 output loading test 8 diags 9 exit UUT power is okay Mon Jul 27 17:37:32 2015 space single step O run once (one test, all steps) F run, stop on fail G go (run tests N run, stop on fail, no print S scope (run, no print) C toggle comment printout + increase speed (less delay) - decrease speed (more delay)(slower) Q quit test step 1 100000000000000000000000000000000001111100010011011010100110111001 step 2 100000000000000000000000000000000001111100100011011010100110111001 step 3 100000000000000000000000000000000001111100000011011010100110111001 step 4 100000000000000000000000000000000001111100000100011010100110111001 step 5 100000000000000000000000000000000001111100000000011010100110111001 step 6 100000000000000000000000000000000001111100000000100010100110111001 step 7 100000000000000000000000000000000001111100000000000010100110111001 step 8 100000000000000000000000000000000001111100000000000101010110111001 step 9 100000000000000000000000000000000001111100000000000001010110111001 step 10 100000000000000000000000000000000001111100000000000001011000111001 step 11 100000000000000000000000000000000001111100000000000001010000111001 step 12 100000000000000000000000000000000001111100000000000001010001100001 step 13 100000000000000000000000000000000001111100000000000001010000100001 step 14 100000000000000000000000000000000001111100000000000001010000100001 step 15 100000000000010000000000000000000000111101000000000001010000100001 step 16 100000000000010010000000000000000000110111000000000001010000100001 step 17 100000000000010010000000000000000000110111111000000001010000100001 step 18 100000000000010010000000000000000000110111011000000001010000100001 step 19 100000000000010010000000000000000000110111011111000001010000100001 step 20 100000000000010010000000000000000000110111011011000001010000100001 step 21 100000000000010010000000000000000000110111011011111001010000100001 step 22 100000000000010010000000000000000000110111011011011001010000100001 step 23 100000000000010010000000000000000000110111011011011110100000100001 step 24 100000000000010010000000000000000000110111011011011010100000100001 step 25 100000000000010010000000000000000000110111011011011010101110100001 step 26 100000000000010010000000000000000000110111011011011010100110100001 step 27 100000000000010010000000000000000000110111011011011010100111111001 step 28 100000000000010010000000000000000000110111011011011010100110111001 step 29 100000000000000010000000000000000001110110011011011010100110111001 step 30 100000000000000000000000000000000001111100011011011010100110111001 step 31 100000000000000000000000000000000001111100011011011010100110111001 step 32 100001000000000000000000000000000001111100011011011010100110111001 step 33 100001100000000000000000000000000001111100011011011010100110111001 step 34 100001100100000000000000000000000001111100011011011010100110111001 step 35 100001100110000000000000000000000001111100011011011010100110111001 step 36 100001100110100000000000000000000001111100011011011010100110111001 step 37 100001100110100100000000000000000001111100011011011010100110111001 step 38 100001100110100100010000000000000001111100011011011010100110111001 step 39 100001100110100100011000000000000001111100011011011010100110111001 step 40 100001100110100100011010000000000001111100011011011010100110111001 step 41 100001100110100100011011000000000001111100011011011010100110111001 step 42 100001100110100100011011010000000001111100011011011010100110111001 step 43 100001100110100100011011011000000001111100011011011010100110111001 step 44 100001100110100100011011011010000001111100011011011010100110111001 step 45 100001100110100100011011011011000001111100011011011010100110111001 step 46 100001100110100100011011011011010001111100011011011010100110111001 step 47 100001100110100100011011011011011001111100011011011010100110111001 step 48 100001100110100100011011011011011101111100011011011010100110111001 step 49 110001100110100100011011011011011100110111011011011010100110111001 step 50 100001100110100100011011011011011101111100011011011010100110111001 step 51 101001100110100100011011011011011100110111011011011010100110111001 step 52 100001100110100100011011011011011101111100011011011010100110111001 step 53 100101100110100100011011011011011100110111011011011010100110111001 step 54 100001100110100100011011011011011101111100011011011010100110111001 step 55 100011100110100100011011011011011100110111011011011010100110111001 step 56 100001100110100100011011011011011101111100011011011010100110111001 step 57 100001110110100100011011011011011100110111011011011010100110111001 step 58 100001100110100100011011011011011101111100011011011010100110111001 step 59 100001101110100100011011011011011100110111011011011010100110111001 step 60 100001100110100100011011011011011101111100011011011010100110111001 step 61 100001100111100100011011011011011100111101011011011010100110111001 step 62 100001100110100100011011011011011101111100011011011010100110111001 step 63 100001100110110100011011011011011100111101011011011010100110111001 step 64 100001100110100100011011011011011101111100011011011010100110111001 step 65 100001100110101100011011011011011101110110011011011010100110111001 step 66 100001100110100100011011011011011101111100011011011010100110111001 step 67 100001100110100110011011011011011101110110011011011010100110111001 step 68 100001100110100100011011011011011101111100011011011010100110111001 step 69 100001100110100101011011011011011101001111011011011010100110111001 step 70 100001100110100100011011011011011101111100011011011010100110111001 step 71 100001100110100100111011011011011101001111011011011010100110111001 step 72 100001100110100100011011011011011101111100011011011010100110111001 step 73 100001100110100100011111011011011101001111011011011010100110111001 step 74 100001100110100100011011011011011101111100011011011010100110111001 step 75 100001100110100100011011111011011101001111011011011010100110111001 step 76 100001100110100100011011011011011101111100011011011010100110111001 step 77 100001100110100100011011011111011101001111011011011010100110111001 step 78 100001100110100100011011011011011101111100011011011010100110111001 step 79 100001100110100100011011011011111101001111011011011010100110111001 step 80 100001100110100100011011011011011101111100011011011010100110111001 step 81 100001100110100100011011011011011111101110011011011010100110111001 step 82 100001100110100100011011011011011101111100011011011010100110111001 step 83 100001100110100100011011011011011101111100011011011010100110110101 step 84 100001100110100100011011011011011101111100011011011010100110110001 step 85 100001100110100100011011011011011101111100011011011010100110100101 step 86 100001100110100100011011011011011101111100011011011010100110100001 step 87 100001100110100100011011011011011101111100011011011010100110100101 step 88 100001100110100100011011011011011101111100011011011010100110100001 SLOT BAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBAABBAAAAAAAAAAAAAABBBBBBBBAB LETTER ALPSLFMDEEMCBFRSPKLEMFHRSCJLJKUHPNMBBNNVVRKRHUTDJUKANJHBTPDFSVDEVU SIDE 121212122121212121111111112212122222112222111221112112212112212212 DIRECTION IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIOOOOOOOIOOIOOIOOIOOOOIOOIIOOIIO changed: 11 step 89 100001100110100100011011011011011101111100011011011010100110100111 fail ^ space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C toggle comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit comment_flag is 1 space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C toggle comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT BAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBAABBAAAAAAAAAAAAAABBBBBBBBAB LETTER ALPSLFMDEEMCBFRSPKLEMFHRSCJLJKUHPNMBBNNVVRKRHUTDJUKANJHBTPDFSVDEVU SIDE 121212122121212121111111112212122222112222111221112112212112212212 DIRECTION IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIOOOOOOOIOOIOOIOOIOOOOIOOIIOOIIO all fails O was lo 00000000000000000000000000000000000000 00000000000000000000 0000 falling vvvv vv v vv vvv v v v v vvvvv vvvv vvvvvvvvvvvvvvv vvv rising ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ ^^^^^^^^^^^^^^^^^^^^ ^^^^ was hi 111111111111111111111111111111111111111111111111111111111111111111 total fails 0, total passes 0 Main menu Mon Jul 27 17:37:39 2015 test file is: tests\m222.new delay is: 0 trigger is: 1 1 read test file 2 set test delay 3 set test trigger 4 run test 5 output loading test 8 diags 9 exit UUT power is okay Mon Jul 27 17:37:43 2015 space single step O run once (one test, all steps) F run, stop on fail G go (run tests N run, stop on fail, no print S scope (run, no print) C toggle comment printout + increase speed (less delay) - decrease speed (more delay)(slower) Q quit test step 1 100000000000000000000000000000000001111100010011011010100110111001 step 2 100000000000000000000000000000000001111100100011011010100110111001 step 3 100000000000000000000000000000000001111100000011011010100110111001 step 4 100000000000000000000000000000000001111100000100011010100110111001 step 5 100000000000000000000000000000000001111100000000011010100110111001 step 6 100000000000000000000000000000000001111100000000100010100110111001 step 7 100000000000000000000000000000000001111100000000000010100110111001 step 8 100000000000000000000000000000000001111100000000000101010110111001 step 9 100000000000000000000000000000000001111100000000000001010110111001 step 10 100000000000000000000000000000000001111100000000000001011000111001 step 11 100000000000000000000000000000000001111100000000000001010000111001 step 12 100000000000000000000000000000000001111100000000000001010001100001 step 13 100000000000000000000000000000000001111100000000000001010000100001 step 14 100000000000000000000000000000000001111100000000000001010000100001 step 15 100000000000010000000000000000000000111101000000000001010000100001 step 16 100000000000010010000000000000000000110111000000000001010000100001 step 17 100000000000010010000000000000000000110111111000000001010000100001 step 18 100000000000010010000000000000000000110111011000000001010000100001 step 19 100000000000010010000000000000000000110111011111000001010000100001 step 20 100000000000010010000000000000000000110111011011000001010000100001 step 21 100000000000010010000000000000000000110111011011111001010000100001 step 22 100000000000010010000000000000000000110111011011011001010000100001 step 23 100000000000010010000000000000000000110111011011011110100000100001 step 24 100000000000010010000000000000000000110111011011011010100000100001 step 25 100000000000010010000000000000000000110111011011011010101110100001 step 26 100000000000010010000000000000000000110111011011011010100110100001 step 27 100000000000010010000000000000000000110111011011011010100111111001 step 28 100000000000010010000000000000000000110111011011011010100110111001 step 29 100000000000000010000000000000000001110110011011011010100110111001 step 30 100000000000000000000000000000000001111100011011011010100110111001 step 31 100000000000000000000000000000000001111100011011011010100110111001 step 32 100001000000000000000000000000000001111100011011011010100110111001 step 33 100001100000000000000000000000000001111100011011011010100110111001 step 34 100001100100000000000000000000000001111100011011011010100110111001 step 35 100001100110000000000000000000000001111100011011011010100110111001 step 36 100001100110100000000000000000000001111100011011011010100110111001 step 37 100001100110100100000000000000000001111100011011011010100110111001 step 38 100001100110100100010000000000000001111100011011011010100110111001 step 39 100001100110100100011000000000000001111100011011011010100110111001 step 40 100001100110100100011010000000000001111100011011011010100110111001 step 41 100001100110100100011011000000000001111100011011011010100110111001 step 42 100001100110100100011011010000000001111100011011011010100110111001 step 43 100001100110100100011011011000000001111100011011011010100110111001 step 44 100001100110100100011011011010000001111100011011011010100110111001 step 45 100001100110100100011011011011000001111100011011011010100110111001 step 46 100001100110100100011011011011010001111100011011011010100110111001 step 47 100001100110100100011011011011011001111100011011011010100110111001 step 48 100001100110100100011011011011011101111100011011011010100110111001 step 49 110001100110100100011011011011011100110111011011011010100110111001 step 50 100001100110100100011011011011011101111100011011011010100110111001 step 51 101001100110100100011011011011011100110111011011011010100110111001 step 52 100001100110100100011011011011011101111100011011011010100110111001 step 53 100101100110100100011011011011011100110111011011011010100110111001 step 54 100001100110100100011011011011011101111100011011011010100110111001 step 55 100011100110100100011011011011011100110111011011011010100110111001 step 56 100001100110100100011011011011011101111100011011011010100110111001 step 57 100001110110100100011011011011011100110111011011011010100110111001 step 58 100001100110100100011011011011011101111100011011011010100110111001 step 59 100001101110100100011011011011011100110111011011011010100110111001 step 60 100001100110100100011011011011011101111100011011011010100110111001 step 61 100001100111100100011011011011011100111101011011011010100110111001 step 62 100001100110100100011011011011011101111100011011011010100110111001 step 63 100001100110110100011011011011011100111101011011011010100110111001 step 64 100001100110100100011011011011011101111100011011011010100110111001 step 65 100001100110101100011011011011011101110110011011011010100110111001 step 66 100001100110100100011011011011011101111100011011011010100110111001 step 67 100001100110100110011011011011011101110110011011011010100110111001 step 68 100001100110100100011011011011011101111100011011011010100110111001 step 69 100001100110100101011011011011011101001111011011011010100110111001 step 70 100001100110100100011011011011011101111100011011011010100110111001 step 71 100001100110100100111011011011011101001111011011011010100110111001 step 72 100001100110100100011011011011011101111100011011011010100110111001 step 73 100001100110100100011111011011011101001111011011011010100110111001 step 74 100001100110100100011011011011011101111100011011011010100110111001 step 75 100001100110100100011011111011011101001111011011011010100110111001 step 76 100001100110100100011011011011011101111100011011011010100110111001 step 77 100001100110100100011011011111011101001111011011011010100110111001 step 78 100001100110100100011011011011011101111100011011011010100110111001 step 79 100001100110100100011011011011111101001111011011011010100110111001 step 80 100001100110100100011011011011011101111100011011011010100110111001 step 81 100001100110100100011011011011011111101110011011011010100110111001 step 82 100001100110100100011011011011011101111100011011011010100110111001 step 83 100001100110100100011011011011011101111100011011011010100110110101 step 84 100001100110100100011011011011011101111100011011011010100110110001 step 85 100001100110100100011011011011011101111100011011011010100110100101 step 86 100001100110100100011011011011011101111100011011011010100110100001 step 87 100001100110100100011011011011011101111100011011011010100110100101 step 88 100001100110100100011011011011011101111100011011011010100110100001 SLOT BAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBAABBAAAAAAAAAAAAAABBBBBBBBAB LETTER ALPSLFMDEEMCBFRSPKLEMFHRSCJLJKUHPNMBBNNVVRKRHUTDJUKANJHBTPDFSVDEVU SIDE 121212122121212121111111112212122222112222111221112112212112212212 DIRECTION IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIOOOOOOOIOOIOOIOOIOOOOIOOIIOOIIO changed: 11 step 89 100001100110100100011011011011011101111100011011011010100110100111 fail ^ space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C toggle comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit comment_flag is 1 space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C toggle comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT BAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBAABBAAAAAAAAAAAAAABBBBBBBBAB LETTER ALPSLFMDEEMCBFRSPKLEMFHRSCJLJKUHPNMBBNNVVRKRHUTDJUKANJHBTPDFSVDEVU SIDE 121212122121212121111111112212122222112222111221112112212112212212 DIRECTION IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIOOOOOOOIOOIOOIOOIOOOOIOOIIOOIIO source: 0 changed: 0 step 90 100001100110100100011011011011011101111100011011011010100110100011 fail ^ SLOT BAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBAABBAAAAAAAAAAAAAABBBBBBBBAB LETTER ALPSLFMDEEMCBFRSPKLEMFHRSCJLJKUHPNMBBNNVVRKRHUTDJUKANJHBTPDFSVDEVU SIDE 121212122121212121111111112212122222112222111221112112212112212212 DIRECTION IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIOOOOOOOIOOIOOIOOIOOOOIOOIIOOIIO source: ; shift in 1, expect 11 source: 1111 changed: 11 step 91 100001100110100100011011011011011101111100011011011010100110101111 fail ^ SLOT BAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBAABBAAAAAAAAAAAAAABBBBBBBBAB LETTER ALPSLFMDEEMCBFRSPKLEMFHRSCJLJKUHPNMBBNNVVRKRHUTDJUKANJHBTPDFSVDEVU SIDE 121212122121212121111111112212122222112222111221112112212112212212 DIRECTION IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIOOOOOOOIOOIOOIOOIOOOOIOOIIOOIIO source: 0 changed: 0 step 92 100001100110100100011011011011011101111100011011011010100110101011 fail ^ source: ; shift in 1, expect 11 source: 1111 changed: 1 1 step 93 100001100110100100011011011011011101111100011011011010100110111111 source: 0 changed: 0 step 94 100001100110100100011011011011011101111100011011011010100110111011 SLOT BAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBAABBAAAAAAAAAAAAAABBBBBBBBAB LETTER ALPSLFMDEEMCBFRSPKLEMFHRSCJLJKUHPNMBBNNVVRKRHUTDJUKANJHBTPDFSVDEVU SIDE 121212122121212121111111112212122222112222111221112112212112212212 DIRECTION IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIOOOOOOOIOOIOOIOOIOOOOIOOIIOOIIO source: ; shift in 0, expect 10 source: 1010 changed: 10 step 95 100001100110100100011011011011011101111100011011011010100110111101 fail ^ SLOT BAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBAABBAAAAAAAAAAAAAABBBBBBBBAB LETTER ALPSLFMDEEMCBFRSPKLEMFHRSCJLJKUHPNMBBNNVVRKRHUTDJUKANJHBTPDFSVDEVU SIDE 121212122121212121111111112212122222112222111221112112212112212212 DIRECTION IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIOOOOOOOIOOIOOIOOIOOOOIOOIIOOIIO source: 0 changed: 0 step 96 100001100110100100011011011011011101111100011011011010100110111001 fail ^ SLOT BAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBAABBAAAAAAAAAAAAAABBBBBBBBAB LETTER ALPSLFMDEEMCBFRSPKLEMFHRSCJLJKUHPNMBBNNVVRKRHUTDJUKANJHBTPDFSVDEVU SIDE 121212122121212121111111112212122222112222111221112112212112212212 DIRECTION IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIOOOOOOOIOOIOOIOOIOOOOIOOIIOOIIO source: ; shift in 1, expect 01 source: 0111 changed: 011 step 97 100001100110100100011011011011011101111100011011011010100110110111 fail ^^ SLOT BAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBAABBAAAAAAAAAAAAAABBBBBBBBAB LETTER ALPSLFMDEEMCBFRSPKLEMFHRSCJLJKUHPNMBBNNVVRKRHUTDJUKANJHBTPDFSVDEVU SIDE 121212122121212121111111112212122222112222111221112112212112212212 DIRECTION IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIOOOOOOOIOOIOOIOOIOOOOIOOIIOOIIO source: 0 changed: 0 step 98 100001100110100100011011011011011101111100011011011010100110110011 fail ^^ SLOT BAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBAABBAAAAAAAAAAAAAABBBBBBBBAB LETTER ALPSLFMDEEMCBFRSPKLEMFHRSCJLJKUHPNMBBNNVVRKRHUTDJUKANJHBTPDFSVDEVU SIDE 121212122121212121111111112212122222112222111221112112212112212212 DIRECTION IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIOOOOOOOIOOIOOIOOIOOOOIOOIIOOIIO source: ; shift in 0, expect 10 source: 1010 changed: 0110 step 99 100001100110100100011011011011011101111100011011011010100110101101 fail ^^ SLOT BAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBAABBAAAAAAAAAAAAAABBBBBBBBAB LETTER ALPSLFMDEEMCBFRSPKLEMFHRSCJLJKUHPNMBBNNVVRKRHUTDJUKANJHBTPDFSVDEVU SIDE 121212122121212121111111112212122222112222111221112112212112212212 DIRECTION IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIOOOOOOOIOOIOOIOOIOOOOIOOIIOOIIO source: 0 changed: 0 step 100 100001100110100100011011011011011101111100011011011010100110101001 fail ^^ SLOT BAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBAABBAAAAAAAAAAAAAABBBBBBBBAB LETTER ALPSLFMDEEMCBFRSPKLEMFHRSCJLJKUHPNMBBNNVVRKRHUTDJUKANJHBTPDFSVDEVU SIDE 121212122121212121111111112212122222112222111221112112212112212212 DIRECTION IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIOOOOOOOIOOIOOIOOIOOOOIOOIIOOIIO source: ; shift in 1, expect 01 source: 0111 changed: 1011 step 101 100001100110100100011011011011011101111100011011011010100110110111 fail ^^ SLOT BAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBAABBAAAAAAAAAAAAAABBBBBBBBAB LETTER ALPSLFMDEEMCBFRSPKLEMFHRSCJLJKUHPNMBBNNVVRKRHUTDJUKANJHBTPDFSVDEVU SIDE 121212122121212121111111112212122222112222111221112112212112212212 DIRECTION IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIOOOOOOOIOOIOOIOOIOOOOIOOIIOOIIO source: 0 changed: 0 step 102 100001100110100100011011011011011101111100011011011010100110110011 fail ^^ SLOT BAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBAABBAAAAAAAAAAAAAABBBBBBBBAB LETTER ALPSLFMDEEMCBFRSPKLEMFHRSCJLJKUHPNMBBNNVVRKRHUTDJUKANJHBTPDFSVDEVU SIDE 121212122121212121111111112212122222112222111221112112212112212212 DIRECTION IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIOOOOOOOIOOIOOIOOIOOOOIOOIIOOIIO source: ; shift in 1, expect 10 source: 1011 changed: 011 step 103 100001100110100100011011011011011101111100011011011010100110101111 fail ^^ SLOT BAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBAABBAAAAAAAAAAAAAABBBBBBBBAB LETTER ALPSLFMDEEMCBFRSPKLEMFHRSCJLJKUHPNMBBNNVVRKRHUTDJUKANJHBTPDFSVDEVU SIDE 121212122121212121111111112212122222112222111221112112212112212212 DIRECTION IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIOOOOOOOIOOIOOIOOIOOOOIOOIIOOIIO source: 0 changed: 0 step 104 100001100110100100011011011011011101111100011011011010100110101011 fail ^^ test 1: *** FAIL *************************** 14 steps failed SLOT BAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBAABBAAAAAAAAAAAAAABBBBBBBBAB LETTER ALPSLFMDEEMCBFRSPKLEMFHRSCJLJKUHPNMBBNNVVRKRHUTDJUKANJHBTPDFSVDEVU SIDE 121212122121212121111111112212122222112222111221112112212112212212 DIRECTION IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIOOOOOOOIOOIOOIOOIOOOOIOOIIOOIIO this fail OO all fails OO was hi 111111111111111111111111111111111111111111111111111111111111111111 rising ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ ^^^^^^^^^^^^^^^^^^^^ ^^^^ falling vvvv vv v vv vvv v v v v vvvvv vvvv vvvvvvvvvvvvvvv vvvv was lo 00000000000000000000000000000000000000 00000000000000000000 0000 total fails 1, total passes 0 space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C toggle comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit source: ; all registers are unknown source: ; turn on C0, PHASE source: ; with no ENABLES, BUS2,BUS3 is 11, C2 is 1 source: 1000000000000000000000000000000000011111000XX0XX0XX0XXXX0XX01XX001 changed: 00 00 0 0 00 00 00 00 000 0 step 1 100000000000000000000000000000000001111100011011011010100110101001 source: source: ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; source: ; source: ; set all registers LOW source: ; source: ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; source: source: ; load TMA SETUP from tape bus (00) source: 100 changed: 100 step 2 100000000000000000000000000000000001111100100011011010100110101001 source: 0 changed: 0 step 3 100000000000000000000000000000000001111100000011011010100110101001 source: ; load TMA from tape bus (00) source: 100 changed: 100 step 4 100000000000000000000000000000000001111100000100011010100110101001 source: 0 changed: 0 step 5 100000000000000000000000000000000001111100000000011010100110101001 source: ; load TBN from tape bus (00) source: 100 changed: 100 step 6 100000000000000000000000000000000001111100000000100010100110101001 source: 0 changed: 0 step 7 100000000000000000000000000000000001111100000000000010100110101001 source: ; load TAC from tape bus (00) source: 10101 changed: 10101 step 8 100000000000000000000000000000000001111100000000000101010110101001 source: 0 changed: 0 step 9 100000000000000000000000000000000001111100000000000001010110101001 source: ; load TB from tape bus (00) source: 100 changed: 100 step 10 100000000000000000000000000000000001111100000000000001011000101001 source: 0 changed: 0 step 11 100000000000000000000000000000000001111100000000000001010000101001 source: ; load RWB from TB (JAMS CLEAR AND PRESET) source: 1 00 changed: 1 0 step 12 100000000000000000000000000000000001111100000000000001010001100001 source: 0 changed: 0 step 13 100000000000000000000000000000000001111100000000000001010000100001 source: ; (no change) source: 100000000000000000000000000000000001111100000000000001010000100001 changed: step 14 100000000000000000000000000000000001111100000000000001010000100001 source: source: source: ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; source: ; source: ; set all registers HIGH source: ; source: ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; source: source: ; set pin AF1 (AND with itself) to clear pin BB2 (AND-NOR output) and set pin BR2 TAPE BUS 3 OUTPUT source: 1 0 1 changed: 1 0 1 step 15 100000000000010000000000000000000000111101000000000001010000100001 source: ; set pin AP2 (AND with itself) to clear pin AN2 (AND-NOR output) and set pin BV2 TAPE BUS 2 OUTPUT source: 1 0 1 changed: 1 0 1 step 16 100000000000010010000000000000000000110111000000000001010000100001 source: source: source: ; load TMA SETUP from tape bus (11) source: 111 changed: 111 step 17 100000000000010010000000000000000000110111111000000001010000100001 source: 0 changed: 0 step 18 100000000000010010000000000000000000110111011000000001010000100001 source: ; load TMA from tape bus (11) source: 111 changed: 111 step 19 100000000000010010000000000000000000110111011111000001010000100001 source: 0 changed: 0 step 20 100000000000010010000000000000000000110111011011000001010000100001 source: ; load TBN from tape bus (11) source: 111 changed: 111 step 21 100000000000010010000000000000000000110111011011111001010000100001 source: 0 changed: 0 step 22 100000000000010010000000000000000000110111011011011001010000100001 source: ; load TAC from tape bus (11) source: 11010 changed: 11010 step 23 100000000000010010000000000000000000110111011011011110100000100001 source: 0 changed: 0 step 24 100000000000010010000000000000000000110111011011011010100000100001 source: ; load TB from tape bus (11) source: 111 changed: 111 step 25 100000000000010010000000000000000000110111011011011010101110100001 source: 0 changed: 0 step 26 100000000000010010000000000000000000110111011011011010100110100001 source: ; load RWB from TB (JAMS CLEAR AND PRESET) source: 1 11 changed: 1 11 step 27 100000000000010010000000000000000000110111011011011010100111111001 source: 0 changed: 0 step 28 100000000000010010000000000000000000110111011011011010100110111001 source: ; clear pin AF1 (AND with itself) to set pin BB2 (AND-NOR output) and clear pin BR2 TAPE BUS 3 OUTPUT source: 0 1 0 changed: 0 1 0 step 29 100000000000000010000000000000000001110110011011011010100110111001 source: ; clear pin AP2 (AND with itself) to set pin AN2 (AND-NOR output) and clear pin BV2 TAPE BUS 2 OUTPUT source: 0 1 0 changed: 0 1 0 step 30 100000000000000000000000000000000001111100011011011010100110111001 source: ; (no change) source: 100000000000000000000000000000000001111100011011011010100110111001 changed: step 31 100000000000000000000000000000000001111100011011011010100110111001 source: source: source: ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; source: ; source: ; test AND-NOR logic source: ; source: ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; source: source: ; (all registers are HIGH) source: ; set all pins HIGH except ENABLES source: source: ; set pin AF2 HIGH source: 1 changed: 1 step 32 100001000000000000000000000000000001111100011011011010100110111001 source: ; set pin AM1 HIGH source: 1 changed: 1 step 33 100001100000000000000000000000000001111100011011011010100110111001 source: ; set pin AE1 HIGH source: 1 changed: 1 step 34 100001100100000000000000000000000001111100011011011010100110111001 source: ; set pin AM2 HIGH source: 1 changed: 1 step 35 100001100110000000000000000000000001111100011011011010100110111001 source: ; set pin AB2 HIGH source: 1 changed: 1 step 36 100001100110100000000000000000000001111100011011011010100110111001 source: ; set pin AS1 HIGH source: 1 changed: 1 step 37 100001100110100100000000000000000001111100011011011010100110111001 source: ; set pin BE1 HIGH source: 1 changed: 1 step 38 100001100110100100010000000000000001111100011011011010100110111001 source: ; set pin BM1 HIGH source: 1 changed: 1 step 39 100001100110100100011000000000000001111100011011011010100110111001 source: ; set pin BH1 HIGH source: 1 changed: 1 step 40 100001100110100100011010000000000001111100011011011010100110111001 source: ; set pin BR1 HIGH source: 1 changed: 1 step 41 100001100110100100011011000000000001111100011011011010100110111001 source: ; set pin BC1 HIGH source: 1 changed: 1 step 42 100001100110100100011011010000000001111100011011011010100110111001 source: ; set pin BJ2 HIGH source: 1 changed: 1 step 43 100001100110100100011011011000000001111100011011011010100110111001 source: ; set pin BJ1 HIGH source: 1 changed: 1 step 44 100001100110100100011011011010000001111100011011011010100110111001 source: ; set pin BK2 HIGH source: 1 changed: 1 step 45 100001100110100100011011011011000001111100011011011010100110111001 source: ; set pin BH2 HIGH source: 1 changed: 1 step 46 100001100110100100011011011011010001111100011011011010100110111001 source: ; set pin BP2 HIGH source: 1 changed: 1 step 47 100001100110100100011011011011011001111100011011011010100110111001 source: ; set pin BN2 HIGH source: 1 changed: 1 step 48 100001100110100100011011011011011101111100011011011010100110111001 source: ; toggle each ENABLE source: source: ; set pin AL2 to clear pin BB2 and pin AN2 AND-NOR OUTPUTS and set TAPE BUS 2 OUTPUT and TAPE BUS 3 OUTPUT source: 1 0 0 11 changed: 1 0 0 11 step 49 110001100110100100011011011011011100110111011011011010100110111001 source: 0 1 1 00 changed: 0 1 1 00 step 50 100001100110100100011011011011011101111100011011011010100110111001 source: ; set pin AP1 to clear pin BB2 and pin AN2 AND-NOR OUTPUTS and set TAPE BUS 2 OUTPUT and TAPE BUS 3 OUTPUT source: 1 0 0 11 changed: 1 0 0 11 step 51 101001100110100100011011011011011100110111011011011010100110111001 source: 0 1 1 00 changed: 0 1 1 00 step 52 100001100110100100011011011011011101111100011011011010100110111001 source: ; set pin AS2 to clear pin BB2 and pin AN2 AND-NOR OUTPUTS and set TAPE BUS 2 OUTPUT and TAPE BUS 3 OUTPUT source: 1 0 0 11 changed: 1 0 0 11 step 53 100101100110100100011011011011011100110111011011011010100110111001 source: 0 1 1 00 changed: 0 1 1 00 step 54 100001100110100100011011011011011101111100011011011010100110111001 source: ; set pin AL1 to clear pin BB2 and pin AN2 AND-NOR OUTPUTS and set TAPE BUS 2 OUTPUT and TAPE BUS 3 OUTPUT source: 1 0 0 11 changed: 1 0 0 11 step 55 100011100110100100011011011011011100110111011011011010100110111001 source: 0 1 1 00 changed: 0 1 1 00 step 56 100001100110100100011011011011011101111100011011011010100110111001 source: ; set pin AL1 to clear pin BB2 and pin AN2 AND-NOR OUTPUTS and set TAPE BUS 2 OUTPUT and TAPE BUS 3 OUTPUT source: 1 0 0 11 changed: 1 0 0 11 step 57 100001110110100100011011011011011100110111011011011010100110111001 source: 0 1 1 00 changed: 0 1 1 00 step 58 100001100110100100011011011011011101111100011011011010100110111001 source: ; set pin AE2 to clear pin BB2 and pin AN2 AND-NOR OUTPUTS and set TAPE BUS 2 OUTPUT and TAPE BUS 3 OUTPUT source: 1 0 0 11 changed: 1 0 0 11 step 59 100001101110100100011011011011011100110111011011011010100110111001 source: 0 1 1 00 changed: 0 1 1 00 step 60 100001100110100100011011011011011101111100011011011010100110111001 source: ; set pin AC1 to clear pin BB2 and set TAPE BUS 3 OUTPUT source: 1 0 1 changed: 1 0 1 step 61 100001100111100100011011011011011100111101011011011010100110111001 source: 0 1 0 changed: 0 1 0 step 62 100001100110100100011011011011011101111100011011011010100110111001 source: ; set pin AF1 to clear pin BB2 and set TAPE BUS 3 OUTPUT source: 1 0 1 changed: 1 0 1 step 63 100001100110110100011011011011011100111101011011011010100110111001 source: 0 1 0 changed: 0 1 0 step 64 100001100110100100011011011011011101111100011011011010100110111001 source: ; set pin AR2 to clear pin AN2 AND-NOR OUTPUTS and set TAPE BUS 2 OUTPUT source: 1 0 1 changed: 1 0 1 step 65 100001100110101100011011011011011101110110011011011010100110111001 source: 0 1 0 changed: 0 1 0 step 66 100001100110100100011011011011011101111100011011011010100110111001 source: ; set pin AP2 to clear pin AN2 AND-NOR OUTPUTS and set TAPE BUS 2 OUTPUT source: 1 0 1 changed: 1 0 1 step 67 100001100110100110011011011011011101110110011011011010100110111001 source: 0 1 0 changed: 0 1 0 step 68 100001100110100100011011011011011101111100011011011010100110111001 source: source: ; set pin BK1 to clear pin BB1 and pin BN1 AND-NOR OUTPUTS and set TAPE BUS 2 OUTPUT and TAPE BUS 3 OUTPUT source: 1 00 11 changed: 1 00 11 step 69 100001100110100101011011011011011101001111011011011010100110111001 source: 0 11 00 changed: 0 11 00 step 70 100001100110100100011011011011011101111100011011011010100110111001 source: ; set pin BL1 to clear pin BB1 and pin BN1 AND-NOR OUTPUTS and set TAPE BUS 2 OUTPUT and TAPE BUS 3 OUTPUT source: 1 00 11 changed: 1 00 11 step 71 100001100110100100111011011011011101001111011011011010100110111001 source: 0 11 00 changed: 0 11 00 step 72 100001100110100100011011011011011101111100011011011010100110111001 source: ; set pin BF1 to clear pin BB1 and pin BN1 AND-NOR OUTPUTS and set TAPE BUS 2 OUTPUT and TAPE BUS 3 OUTPUT source: 1 00 11 changed: 1 00 11 step 73 100001100110100100011111011011011101001111011011011010100110111001 source: 0 11 00 changed: 0 11 00 step 74 100001100110100100011011011011011101111100011011011010100110111001 source: ; set pin BS1 to clear pin BB1 and pin BN1 AND-NOR OUTPUTS and set TAPE BUS 2 OUTPUT and TAPE BUS 3 OUTPUT source: 1 00 11 changed: 1 00 11 step 75 100001100110100100011011111011011101001111011011011010100110111001 source: 0 11 00 changed: 0 11 00 step 76 100001100110100100011011011011011101111100011011011010100110111001 source: ; set pin BL2 to clear pin BB1 and pin BN1 AND-NOR OUTPUTS and set TAPE BUS 2 OUTPUT and TAPE BUS 3 OUTPUT source: 1 00 11 changed: 1 00 11 step 77 100001100110100100011011011111011101001111011011011010100110111001 source: 0 11 00 changed: 0 11 00 step 78 100001100110100100011011011011011101111100011011011010100110111001 source: ; set pin BU1 to clear pin BB1 and pin BN1 AND-NOR OUTPUTS and set TAPE BUS 2 OUTPUT and TAPE BUS 3 OUTPUT source: 1 00 11 changed: 1 00 11 step 79 100001100110100100011011011011111101001111011011011010100110111001 source: 0 11 00 changed: 0 11 00 step 80 100001100110100100011011011011011101111100011011011010100110111001 source: ; set pin BM2 to clear pin BB1 and TAPE BUS 3 OUTPUT source: 1 0 1 changed: 1 0 1 step 81 100001100110100100011011011011011111101110011011011010100110111001 source: 0 1 0 changed: 0 1 0 step 82 100001100110100100011011011011011101111100011011011010100110111001 source: source: ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; source: ; test shifting the RWB source: ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; source: source: source: source: ; shift in 0, expect 10 source: 1010 changed: 01 step 83 100001100110100100011011011011011101111100011011011010100110110101 source: 0 changed: 0 step 84 100001100110100100011011011011011101111100011011011010100110110001 source: ; shift in 0, expect 00 source: 0010 changed: 0 1 step 85 100001100110100100011011011011011101111100011011011010100110100101 source: 0 changed: 0 step 86 100001100110100100011011011011011101111100011011011010100110100001 source: ; shift in 0, expect 00 source: 0010 changed: 1 step 87 100001100110100100011011011011011101111100011011011010100110100101 source: 0 changed: 0 step 88 100001100110100100011011011011011101111100011011011010100110100001 SLOT BAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBAABBAAAAAAAAAAAAAABBBBBBBBAB LETTER ALPSLFMDEEMCBFRSPKLEMFHRSCJLJKUHPNMBBNNVVRKRHUTDJUKANJHBTPDFSVDEVU SIDE 121212122121212121111111112212122222112222111221112112212112212212 DIRECTION IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIOOOOOOOIOOIOOIOOIOOOOIOOIIOOIIO source: ; shift in 1, expect 01 source: 0111 changed: 11 step 89 100001100110100100011011011011011101111100011011011010100110100111 fail ^ space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C toggle comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT BAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBAABBAAAAAAAAAAAAAABBBBBBBBAB LETTER ALPSLFMDEEMCBFRSPKLEMFHRSCJLJKUHPNMBBNNVVRKRHUTDJUKANJHBTPDFSVDEVU SIDE 121212122121212121111111112212122222112222111221112112212112212212 DIRECTION IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIOOOOOOOIOOIOOIOOIOOOOIOOIIOOIIO all fails OO was lo 00000000000000000000000000000000000000 00000000000000000000 0000 falling vvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvv vvvvvvvvvvvvvvvvvvvv vvvv rising ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ ^^^^^^^^^^^^^^^^^^^^ ^^^^ was hi 111111111111111111111111111111111111111111111111111111111111111111 total fails 1, total passes 0 Main menu Mon Jul 27 17:41:26 2015 test file is: tests\m222.new delay is: 0 trigger is: 1 1 read test file 2 set test delay 3 set test trigger 4 run test 5 output loading test 8 diags 9 exit UUT power is okay Mon Jul 27 17:41:40 2015 space single step O run once (one test, all steps) F run, stop on fail G go (run tests N run, stop on fail, no print S scope (run, no print) C toggle comment printout + increase speed (less delay) - decrease speed (more delay)(slower) Q quit test step 1 100000000000000000000000000000000001111100010011011010100110111001 step 2 100000000000000000000000000000000001111100100011011010100110111001 step 3 100000000000000000000000000000000001111100000011011010100110111001 step 4 100000000000000000000000000000000001111100000100011010100110111001 step 5 100000000000000000000000000000000001111100000000011010100110111001 step 6 100000000000000000000000000000000001111100000000100010100110111001 step 7 100000000000000000000000000000000001111100000000000010100110111001 step 8 100000000000000000000000000000000001111100000000000101010110111001 step 9 100000000000000000000000000000000001111100000000000001010110111001 step 10 100000000000000000000000000000000001111100000000000001011000111001 step 11 100000000000000000000000000000000001111100000000000001010000111001 step 12 100000000000000000000000000000000001111100000000000001010001100001 step 13 100000000000000000000000000000000001111100000000000001010000100001 step 14 100000000000000000000000000000000001111100000000000001010000100001 step 15 100000000000010000000000000000000000111101000000000001010000100001 step 16 100000000000010010000000000000000000110111000000000001010000100001 step 17 100000000000010010000000000000000000110111111000000001010000100001 step 18 100000000000010010000000000000000000110111011000000001010000100001 step 19 100000000000010010000000000000000000110111011111000001010000100001 step 20 100000000000010010000000000000000000110111011011000001010000100001 step 21 100000000000010010000000000000000000110111011011111001010000100001 step 22 100000000000010010000000000000000000110111011011011001010000100001 step 23 100000000000010010000000000000000000110111011011011110100000100001 step 24 100000000000010010000000000000000000110111011011011010100000100001 step 25 100000000000010010000000000000000000110111011011011010101110100001 step 26 100000000000010010000000000000000000110111011011011010100110100001 step 27 100000000000010010000000000000000000110111011011011010100111111001 step 28 100000000000010010000000000000000000110111011011011010100110111001 step 29 100000000000000010000000000000000001110110011011011010100110111001 step 30 100000000000000000000000000000000001111100011011011010100110111001 step 31 100000000000000000000000000000000001111100011011011010100110111001 step 32 100001000000000000000000000000000001111100011011011010100110111001 step 33 100001100000000000000000000000000001111100011011011010100110111001 step 34 100001100100000000000000000000000001111100011011011010100110111001 step 35 100001100110000000000000000000000001111100011011011010100110111001 step 36 100001100110100000000000000000000001111100011011011010100110111001 step 37 100001100110100100000000000000000001111100011011011010100110111001 step 38 100001100110100100010000000000000001111100011011011010100110111001 step 39 100001100110100100011000000000000001111100011011011010100110111001 step 40 100001100110100100011010000000000001111100011011011010100110111001 step 41 100001100110100100011011000000000001111100011011011010100110111001 step 42 100001100110100100011011010000000001111100011011011010100110111001 step 43 100001100110100100011011011000000001111100011011011010100110111001 step 44 100001100110100100011011011010000001111100011011011010100110111001 step 45 100001100110100100011011011011000001111100011011011010100110111001 step 46 100001100110100100011011011011010001111100011011011010100110111001 step 47 100001100110100100011011011011011001111100011011011010100110111001 step 48 100001100110100100011011011011011101111100011011011010100110111001 step 49 110001100110100100011011011011011100110111011011011010100110111001 step 50 100001100110100100011011011011011101111100011011011010100110111001 step 51 101001100110100100011011011011011100110111011011011010100110111001 step 52 100001100110100100011011011011011101111100011011011010100110111001 step 53 100101100110100100011011011011011100110111011011011010100110111001 step 54 100001100110100100011011011011011101111100011011011010100110111001 step 55 100011100110100100011011011011011100110111011011011010100110111001 step 56 100001100110100100011011011011011101111100011011011010100110111001 step 57 100001110110100100011011011011011100110111011011011010100110111001 step 58 100001100110100100011011011011011101111100011011011010100110111001 step 59 100001101110100100011011011011011100110111011011011010100110111001 step 60 100001100110100100011011011011011101111100011011011010100110111001 step 61 100001100111100100011011011011011100111101011011011010100110111001 step 62 100001100110100100011011011011011101111100011011011010100110111001 step 63 100001100110110100011011011011011100111101011011011010100110111001 step 64 100001100110100100011011011011011101111100011011011010100110111001 step 65 100001100110101100011011011011011101110110011011011010100110111001 step 66 100001100110100100011011011011011101111100011011011010100110111001 step 67 100001100110100110011011011011011101110110011011011010100110111001 step 68 100001100110100100011011011011011101111100011011011010100110111001 step 69 100001100110100101011011011011011101001111011011011010100110111001 step 70 100001100110100100011011011011011101111100011011011010100110111001 step 71 100001100110100100111011011011011101001111011011011010100110111001 step 72 100001100110100100011011011011011101111100011011011010100110111001 step 73 100001100110100100011111011011011101001111011011011010100110111001 step 74 100001100110100100011011011011011101111100011011011010100110111001 step 75 100001100110100100011011111011011101001111011011011010100110111001 step 76 100001100110100100011011011011011101111100011011011010100110111001 step 77 100001100110100100011011011111011101001111011011011010100110111001 step 78 100001100110100100011011011011011101111100011011011010100110111001 step 79 100001100110100100011011011011111101001111011011011010100110111001 step 80 100001100110100100011011011011011101111100011011011010100110111001 step 81 100001100110100100011011011011011111101110011011011010100110111001 step 82 100001100110100100011011011011011101111100011011011010100110111001 step 83 100001100110100100011011011011011101111100011011011010100110110101 step 84 100001100110100100011011011011011101111100011011011010100110110001 step 85 100001100110100100011011011011011101111100011011011010100110100101 step 86 100001100110100100011011011011011101111100011011011010100110100001 step 87 100001100110100100011011011011011101111100011011011010100110100101 step 88 100001100110100100011011011011011101111100011011011010100110100001 SLOT BAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBAABBAAAAAAAAAAAAAABBBBBBBBAB LETTER ALPSLFMDEEMCBFRSPKLEMFHRSCJLJKUHPNMBBNNVVRKRHUTDJUKANJHBTPDFSVDEVU SIDE 121212122121212121111111112212122222112222111221112112212112212212 DIRECTION IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIOOOOOOOIOOIOOIOOIOOOOIOOIIOOIIO changed: 11 step 89 100001100110100100011011011011011101111100011011011010100110100111 fail ^ space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C toggle comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT BAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBAABBAAAAAAAAAAAAAABBBBBBBBAB LETTER ALPSLFMDEEMCBFRSPKLEMFHRSCJLJKUHPNMBBNNVVRKRHUTDJUKANJHBTPDFSVDEVU SIDE 121212122121212121111111112212122222112222111221112112212112212212 DIRECTION IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIOOOOOOOIOOIOOIOOIOOOOIOOIIOOIIO all fails O was lo 00000000000000000000000000000000000000 00000000000000000000 0000 falling vvvv vv v vv vvv v v v v vvvvv vvvv vvvvvvvvvvvvvvv vvv rising ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ ^^^^^^^^^^^^^^^^^^^^ ^^^^ was hi 111111111111111111111111111111111111111111111111111111111111111111 total fails 0, total passes 0 Main menu Mon Jul 27 17:41:49 2015 test file is: tests\m222.new delay is: 0 trigger is: 1 1 read test file 2 set test delay 3 set test trigger 4 run test 5 output loading test 8 diags 9 exit exiting tester- PDP8 card tester via printer port version 0.85 June 4, 2015 mapping[] is verified Main menu Sat Aug 01 11:42:35 2015 test file is: delay is: 0 trigger is: 1 1 read test file 2 set test delay 3 set test trigger 4 run test 5 output loading test 8 diags 9 exit key is 0x0067 Main menu Sat Aug 01 11:42:36 2015 test file is: delay is: 0 trigger is: 1 1 read test file 2 set test delay 3 set test trigger 4 run test 5 output loading test 8 diags 9 exit Enter test file name? trying to open test file: tests\g221.tst reading test file: tests\g221.tst comment: G221 REV D SCHEMATIC REV B PCB MEMORY SELECTOR (3-7440) comment: comment: NOTES 7440 outputs (active low) are not at connector (drive transistors) comment: but can be 'clipped' at the 1.5K resistors that connect comment: 7440 outputs to PNP base (emitters are 3.2V) comment: output 00 is at the top (pin A is top) comment: output 01 is next comment: output 10 is next comment: output 11 is at the bottom (pin V is bottom) comment: comment: comment: comment: Note: "P" for PULLUP OUTPUTS on the open collector outputs; comment: POWER SINK- is driven low. comment: output reads 0.74volts (low) when active comment: comment: TODO: still need a way to test POWER SOURCE diodes, pull downs comment: comment: comment: pins: PINS pins: 1 I AD2 ENABLE 1 (ENABLE 1 HI) AND (ENABLE 2 HI) -> ENABLED pins: 2 I AE2 ENABLE 2 (ENABLE 1 HI) AND (ENABLE 2 HI) -> ENABLED pins: 3 I AH2 A1 (HIGH BIT) pins: 4 I AF2 A0 (LOW BIT) pins: 5 I AT2 POWER SOURCE+/SINK- INPUT (+ DIODES TO NPN C; - DIODES TO NPN EMITTER) pins: 6 I AV2 POWER -30V (USED AS SINK) (ALWAYS DRIVE LOW) pins: 7 P AJ2 OUTPUT 00 NPN COLLECTOR (DIODE TO SOURCE+) pins: 8 O AK2 OUTPUT 00 NPN EMITTER (DIODE TO SINK-) pins: 9 P AL2 OUTPUT 01 NPN COLLECTOR (DIODE TO SOURCE+) pins: 10 O AM2 OUTPUT 01 NPN EMITTER (DIODE TO SINK-) pins: 11 P AN2 OUTPUT 10 NPN COLLECTOR (DIODE TO SOURCE+) pins: 12 O AP2 OUTPUT 10 NPN EMITTER (DIODE TO SINK-) pins: 13 P AR2 OUTPUT 11 NPN COLLECTOR (DIODE TO SOURCE+) pins: 14 O AS2 OUTPUT 11 NPN EMITTER (DIODE TO SINK-) pins: direction: IIIIIIPOPOPOPO comment: ; turn on OUTPUT 00 test 1: 1100000X1X1X1X comment: ; turn on OUTPUT 01 test 2: 01 1 0 1 1 comment: ; turn on OUTPUT 10 test 3: 10 1 1 0 1 comment: ; turn on OUTPUT 11 test 4: 11 1 1 1 0 comment: ; all ouputs off test 5: 1000 1 1 1 1 test 6: 01 test 7: 10 test 8: 11 test 9: 0100 test 10: 01 test 11: 10 test 12: 11 test 13: 0000 test 14: 01 test 15: 10 test 16: 11 end: END summary column 1: offset 0, mask 0x0010 column 2: offset 0, mask 0x0008 column 3: offset 0, mask 0x0002 column 4: offset 0, mask 0x0004 column 5: offset 1, mask 0x0080 column 6: offset 2, mask 0x0002 column 7: offset 0, mask 0x0001 column 8: offset 1, mask 0x0001 column 9: offset 1, mask 0x0002 column 10: offset 1, mask 0x0004 column 11: offset 1, mask 0x0008 column 12: offset 1, mask 0x0010 column 13: offset 1, mask 0x0020 column 14: offset 1, mask 0x0040 direction bits (1=input) 0xFFE1 0xFF7F 0xFFF9 0xFFFF 0xF0FF pullup bits (1=pullup) 0x0001 0x002A 0x0000 0x0000 0x0000 test step out_data dont care 1: 0x0018 0x002A 0x0000 0x0000 0x0000 0x0000 0x0055 0x0000 0x0000 0x0000 2: 0x001D 0x0028 0x0000 0x0000 0x0000 0x0000 0x0055 0x0000 0x0000 0x0000 3: 0x001B 0x0022 0x0000 0x0000 0x0000 0x0000 0x0055 0x0000 0x0000 0x0000 4: 0x001F 0x000A 0x0000 0x0000 0x0000 0x0000 0x0055 0x0000 0x0000 0x0000 5: 0x0011 0x002A 0x0000 0x0000 0x0000 0x0000 0x0055 0x0000 0x0000 0x0000 6: 0x0015 0x002A 0x0000 0x0000 0x0000 0x0000 0x0055 0x0000 0x0000 0x0000 7: 0x0013 0x002A 0x0000 0x0000 0x0000 0x0000 0x0055 0x0000 0x0000 0x0000 8: 0x0017 0x002A 0x0000 0x0000 0x0000 0x0000 0x0055 0x0000 0x0000 0x0000 9: 0x0009 0x002A 0x0000 0x0000 0x0000 0x0000 0x0055 0x0000 0x0000 0x0000 10: 0x000D 0x002A 0x0000 0x0000 0x0000 0x0000 0x0055 0x0000 0x0000 0x0000 11: 0x000B 0x002A 0x0000 0x0000 0x0000 0x0000 0x0055 0x0000 0x0000 0x0000 12: 0x000F 0x002A 0x0000 0x0000 0x0000 0x0000 0x0055 0x0000 0x0000 0x0000 13: 0x0001 0x002A 0x0000 0x0000 0x0000 0x0000 0x0055 0x0000 0x0000 0x0000 14: 0x0005 0x002A 0x0000 0x0000 0x0000 0x0000 0x0055 0x0000 0x0000 0x0000 15: 0x0003 0x002A 0x0000 0x0000 0x0000 0x0000 0x0055 0x0000 0x0000 0x0000 16: 0x0007 0x002A 0x0000 0x0000 0x0000 0x0000 0x0055 0x0000 0x0000 0x0000 PINs used (in edge connector order) (G=ground,P=power) SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBB LETTER ABCDEFHJKLMNPRSTUVABCDEFHJKLMNPRSTUVABCDEFHJKLMNPRSTUVABCDEFHJKLMNPRSTUV SIDE 111111111111111111222222222222222222111111111111111111222222222222222222 USAGE G P GIIIIPOPOPOPOI I G P G UUT has 6 inputs UUT has 8 outputs contains 14 pins/columns 52 pins are not used contains 16 'test steps' G221 REV D SCHEMATIC REV B PCB MEMORY SELECTOR (3-7440) NOTES 7440 outputs (active low) are not at connector (drive transistors) but can be 'clipped' at the 1.5K resistors that connect 7440 outputs to PNP base (emitters are 3.2V) output 00 is at the top (pin A is top) output 01 is next output 10 is next output 11 is at the bottom (pin V is bottom) Note: "P" for PULLUP OUTPUTS on the open collector outputs; POWER SINK- is driven low. output reads 0.74volts (low) when active TODO: still need a way to test POWER SOURCE diodes, pull downs PINS Main menu Sat Aug 01 11:42:42 2015 test file is: tests\g221.tst delay is: 0 trigger is: 1 1 read test file 2 set test delay 3 set test trigger 4 run test 5 output loading test 8 diags 9 exit UUT power is okay Sat Aug 01 11:42:45 2015 space single step O run once (one test, all steps) F run, stop on fail G go (run tests N run, stop on fail, no print S scope (run, no print) C toggle comment printout + increase speed (less delay) - decrease speed (more delay)(slower) Q quit test scope (run, no print) ppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppp ppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppp ppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppp ppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppp ppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppp ppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppp ppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppp pppppppppppppppppppppppppppppppp space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C toggle comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit scope (run, no print) ppppppppppppppppppppppppppppppppppppppppppppppp ppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppp ppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppp ppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppp ppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppp ppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppp ppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppp ppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppp pppppppppppppppppppppppppppppppppppppppppppppppppppppppp space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C toggle comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAAAAAAAAAAAAA LETTER DEHFTVJKLMNPRS SIDE 22222222222222 DIRECTION IIIIIIPOPOPOPO all fails was lo 00000000000000 falling vvvv v v v v rising ^^^^ ^ ^ ^ ^ was hi 1111 1 1 1 1 total fails 0, total passes 1241 Main menu Sat Aug 01 11:43:30 2015 test file is: tests\g221.tst delay is: 0 trigger is: 1 1 read test file 2 set test delay 3 set test trigger 4 run test 5 output loading test 8 diags 9 exit ***************************** UUT power is OFF * ***************************** Main menu Sat Aug 01 11:43:38 2015 test file is: tests\g221.tst delay is: 0 trigger is: 1 1 read test file 2 set test delay 3 set test trigger 4 run test 5 output loading test 8 diags 9 exit UUT power is okay Sat Aug 01 11:43:40 2015 space single step O run once (one test, all steps) F run, stop on fail G go (run tests N run, stop on fail, no print S scope (run, no print) C toggle comment printout + increase speed (less delay) - decrease speed (more delay)(slower) Q quit test scope (run, no print) ppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppp ppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppp ppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppp ppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppp ppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppp ppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppp ppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppp ppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppp ppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppp space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C toggle comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAAAAAAAAAAAAA LETTER DEHFTVJKLMNPRS SIDE 22222222222222 DIRECTION IIIIIIPOPOPOPO all fails was lo 00000000000000 falling vvvv v v v v rising ^^^^ ^ ^ ^ ^ was hi 1111 1 1 1 1 total fails 0, total passes 703 Main menu Sat Aug 01 11:43:49 2015 test file is: tests\g221.tst delay is: 0 trigger is: 1 1 read test file 2 set test delay 3 set test trigger 4 run test 5 output loading test 8 diags 9 exit exiting tester- PDP8 card tester via printer port version 0.85 June 4, 2015 mapping[] is verified Main menu Sat Aug 01 11:44:08 2015 test file is: delay is: 0 trigger is: 1 1 read test file 2 set test delay 3 set test trigger 4 run test 5 output loading test 8 diags 9 exit Enter test file name? trying to open test file: tests\g221.tst reading test file: tests\g221.tst comment: G221 REV D SCHEMATIC REV B PCB MEMORY SELECTOR (3-7440) comment: comment: NOTES 7440 outputs (active low) are not at connector (drive transistors) comment: but can be 'clipped' at the 1.5K resistors that connect comment: 7440 outputs to PNP base (emitters are 3.2V) comment: output 00 is at the top (pin A is top) comment: output 01 is next comment: output 10 is next comment: output 11 is at the bottom (pin V is bottom) comment: comment: comment: comment: Note: "P" for PULLUP OUTPUTS on the open collector outputs; comment: POWER SINK- is driven low. comment: output reads 0.74volts (low) when active comment: comment: TODO: still need a way to test POWER SOURCE diodes, pull downs comment: comment: comment: pins: PINS pins: 1 I AD2 ENABLE 1 (ENABLE 1 HI) AND (ENABLE 2 HI) -> ENABLED pins: 2 I AE2 ENABLE 2 (ENABLE 1 HI) AND (ENABLE 2 HI) -> ENABLED pins: 3 I AH2 A1 (HIGH BIT) pins: 4 I AF2 A0 (LOW BIT) pins: 5 I AT2 POWER SOURCE+/SINK- INPUT (+ DIODES TO NPN C; - DIODES TO NPN EMITTER) pins: 6 I AV2 POWER -30V (USED AS SINK) (ALWAYS DRIVE LOW) pins: 7 P AJ2 OUTPUT 00 NPN COLLECTOR (DIODE TO SOURCE+) pins: 8 O AK2 OUTPUT 00 NPN EMITTER (DIODE TO SINK-) pins: 9 P AL2 OUTPUT 01 NPN COLLECTOR (DIODE TO SOURCE+) pins: 10 O AM2 OUTPUT 01 NPN EMITTER (DIODE TO SINK-) pins: 11 P AN2 OUTPUT 10 NPN COLLECTOR (DIODE TO SOURCE+) pins: 12 O AP2 OUTPUT 10 NPN EMITTER (DIODE TO SINK-) pins: 13 P AR2 OUTPUT 11 NPN COLLECTOR (DIODE TO SOURCE+) pins: 14 O AS2 OUTPUT 11 NPN EMITTER (DIODE TO SINK-) pins: direction: IIIIIIPOPOPOPO comment: ; turn on OUTPUT 00 test 1: 1100000X1X1X1X comment: ; turn on OUTPUT 01 test 2: 01 1 0 1 1 comment: ; turn on OUTPUT 10 test 3: 10 1 1 0 1 comment: ; turn on OUTPUT 11 test 4: 11 1 1 1 0 comment: ; all ouputs off test 5: 1000 1 1 1 1 test 6: 01 test 7: 10 test 8: 11 test 9: 0100 test 10: 01 test 11: 10 test 12: 11 test 13: 0000 test 14: 01 test 15: 10 test 16: 11 end: END summary column 1: offset 0, mask 0x0010 column 2: offset 0, mask 0x0008 column 3: offset 0, mask 0x0002 column 4: offset 0, mask 0x0004 column 5: offset 1, mask 0x0080 column 6: offset 2, mask 0x0002 column 7: offset 0, mask 0x0001 column 8: offset 1, mask 0x0001 column 9: offset 1, mask 0x0002 column 10: offset 1, mask 0x0004 column 11: offset 1, mask 0x0008 column 12: offset 1, mask 0x0010 column 13: offset 1, mask 0x0020 column 14: offset 1, mask 0x0040 direction bits (1=input) 0xFFE1 0xFF7F 0xFFF9 0xFFFF 0xF0FF pullup bits (1=pullup) 0x0001 0x002A 0x0000 0x0000 0x0000 test step out_data dont care 1: 0x0018 0x002A 0x0000 0x0000 0x0000 0x0000 0x0055 0x0000 0x0000 0x0000 2: 0x001D 0x0028 0x0000 0x0000 0x0000 0x0000 0x0055 0x0000 0x0000 0x0000 3: 0x001B 0x0022 0x0000 0x0000 0x0000 0x0000 0x0055 0x0000 0x0000 0x0000 4: 0x001F 0x000A 0x0000 0x0000 0x0000 0x0000 0x0055 0x0000 0x0000 0x0000 5: 0x0011 0x002A 0x0000 0x0000 0x0000 0x0000 0x0055 0x0000 0x0000 0x0000 6: 0x0015 0x002A 0x0000 0x0000 0x0000 0x0000 0x0055 0x0000 0x0000 0x0000 7: 0x0013 0x002A 0x0000 0x0000 0x0000 0x0000 0x0055 0x0000 0x0000 0x0000 8: 0x0017 0x002A 0x0000 0x0000 0x0000 0x0000 0x0055 0x0000 0x0000 0x0000 9: 0x0009 0x002A 0x0000 0x0000 0x0000 0x0000 0x0055 0x0000 0x0000 0x0000 10: 0x000D 0x002A 0x0000 0x0000 0x0000 0x0000 0x0055 0x0000 0x0000 0x0000 11: 0x000B 0x002A 0x0000 0x0000 0x0000 0x0000 0x0055 0x0000 0x0000 0x0000 12: 0x000F 0x002A 0x0000 0x0000 0x0000 0x0000 0x0055 0x0000 0x0000 0x0000 13: 0x0001 0x002A 0x0000 0x0000 0x0000 0x0000 0x0055 0x0000 0x0000 0x0000 14: 0x0005 0x002A 0x0000 0x0000 0x0000 0x0000 0x0055 0x0000 0x0000 0x0000 15: 0x0003 0x002A 0x0000 0x0000 0x0000 0x0000 0x0055 0x0000 0x0000 0x0000 16: 0x0007 0x002A 0x0000 0x0000 0x0000 0x0000 0x0055 0x0000 0x0000 0x0000 PINs used (in edge connector order) (G=ground,P=power) SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBB LETTER ABCDEFHJKLMNPRSTUVABCDEFHJKLMNPRSTUVABCDEFHJKLMNPRSTUVABCDEFHJKLMNPRSTUV SIDE 111111111111111111222222222222222222111111111111111111222222222222222222 USAGE G P GIIIIPOPOPOPOI I G P G UUT has 6 inputs UUT has 8 outputs contains 14 pins/columns 52 pins are not used contains 16 'test steps' G221 REV D SCHEMATIC REV B PCB MEMORY SELECTOR (3-7440) NOTES 7440 outputs (active low) are not at connector (drive transistors) but can be 'clipped' at the 1.5K resistors that connect 7440 outputs to PNP base (emitters are 3.2V) output 00 is at the top (pin A is top) output 01 is next output 10 is next output 11 is at the bottom (pin V is bottom) Note: "P" for PULLUP OUTPUTS on the open collector outputs; POWER SINK- is driven low. output reads 0.74volts (low) when active TODO: still need a way to test POWER SOURCE diodes, pull downs PINS Main menu Sat Aug 01 11:44:12 2015 test file is: tests\g221.tst delay is: 0 trigger is: 1 1 read test file 2 set test delay 3 set test trigger 4 run test 5 output loading test 8 diags 9 exit UUT power is okay Sat Aug 01 11:44:14 2015 space single step O run once (one test, all steps) F run, stop on fail G go (run tests N run, stop on fail, no print S scope (run, no print) C toggle comment printout + increase speed (less delay) - decrease speed (more delay)(slower) Q quit test scope (run, no print) ppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppp ppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppp ppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppp ppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppp ppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppp ppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppp ppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppp ppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppp ppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppp ppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppp ppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppp ppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppp ppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppp ppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppp ppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppp ppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppp pppppppppppppppppppppppppppppppppp space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C toggle comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAAAAAAAAAAAAA LETTER DEHFTVJKLMNPRS SIDE 22222222222222 DIRECTION IIIIIIPOPOPOPO all fails was lo 00000000000000 falling vvvv v v v v rising ^^^^ ^ ^ ^ ^ was hi 1111 1 1 1 1 total fails 0, total passes 1298 Main menu Sat Aug 01 11:44:28 2015 test file is: tests\g221.tst delay is: 0 trigger is: 1 1 read test file 2 set test delay 3 set test trigger 4 run test 5 output loading test 8 diags 9 exit key is 0x0030 Main menu Sat Aug 01 11:44:33 2015 test file is: tests\g221.tst delay is: 0 trigger is: 1 1 read test file 2 set test delay 3 set test trigger 4 run test 5 output loading test 8 diags 9 exit exiting tester- PDP8 card tester via printer port version 0.85 June 4, 2015 mapping[] is verified Main menu Mon Aug 10 15:12:44 2015 test file is: delay is: 0 trigger is: 1 1 read test file 2 set test delay 3 set test trigger 4 run test 5 output loading test 8 diags 9 exit Enter test file name? trying to open test file: tests\m113.tst reading test file: tests\m113.tst comment: M113 10 2-input NAND comment: pins: PINS pins: 1 I AA1 E1-1 pins: 2 I AB1 E1-2 pins: 3 O AC1 E1-3 pins: 4 I AD1 E1-4 pins: 5 I AE1 E1-5 pins: 6 O AF1 E1-6 pins: 7 I AD2 E1-13 pins: 8 I AE2 E1-12 pins: 9 O AF2 E1-11 pins: 10 I AH1 E3-4 pins: 11 I AJ1 E3-5 pins: 12 O AK1 E3-6 pins: 13 I AH2 E3-10 pins: 14 I AJ2 E3-9 pins: 15 O AK2 E3-8 pins: 16 I AL1 E2-1 pins: 17 I AM1 E2-2 pins: 18 O AN1 E2-3 pins: 19 I AL2 E3-10 pins: 20 I AM2 E3-9 pins: 21 O AN2 E3-8 pins: 22 I AP1 E2-4 pins: 23 I AR1 E2-5 pins: 24 O AS1 E2-6 pins: 25 I AP2 E2-13 pins: 26 I AR2 E2-12 pins: 27 O AS2 E2-11 pins: 28 I AT2 E2-10 pins: 29 I AU2 E2-9 pins: 30 O AV2 E2-8 pins: direction: IIOIIOIIOIIOIIOIIOIIOIIOIIOIIO test 1: 001001001001001001001001001001 test 2: 110110110110110110110110110110 test 3: 011 test 4: 001 test 5: 101 test 6: 110 test 7: 011 test 8: 001 test 9: 101 test 10: 110 test 11: 011 test 12: 001 test 13: 101 test 14: 110 test 15: 011 test 16: 001 test 17: 101 test 18: 110 test 19: 011 test 20: 001 test 21: 101 test 22: 110 test 23: 011 test 24: 001 test 25: 101 test 26: 110 test 27: 011 test 28: 001 test 29: 101 test 30: 110 test 31: 011 test 32: 001 test 33: 101 test 34: 110 test 35: 011 test 36: 001 test 37: 101 test 38: 110 test 39: 011 test 40: 001 test 41: 101 test 42: 110 test 43: 001001001001001001001001001001 test 44: 011 test 45: 110 test 46: 101 test 47: 001 test 48: 011 test 49: 110 test 50: 101 test 51: 001 test 52: 011 test 53: 110 test 54: 101 test 55: 001 test 56: 011 test 57: 110 test 58: 101 test 59: 001 test 60: 011 test 61: 110 test 62: 101 test 63: 001 test 64: 011 test 65: 110 test 66: 101 test 67: 001 test 68: 011 test 69: 110 test 70: 101 test 71: 001 test 72: 011 test 73: 110 test 74: 101 test 75: 001 test 76: 011 test 77: 110 test 78: 101 test 79: 001 test 80: 011 test 81: 110 test 82: 101 test 83: 001 end: END summary column 1: offset 0, mask 0x8000 column 2: offset 0, mask 0x4000 column 3: offset 0, mask 0x2000 column 4: offset 0, mask 0x1000 column 5: offset 0, mask 0x0800 column 6: offset 0, mask 0x0400 column 7: offset 0, mask 0x0010 column 8: offset 0, mask 0x0008 column 9: offset 0, mask 0x0004 column 10: offset 0, mask 0x0200 column 11: offset 0, mask 0x0100 column 12: offset 1, mask 0x8000 column 13: offset 0, mask 0x0002 column 14: offset 0, mask 0x0001 column 15: offset 1, mask 0x0001 column 16: offset 1, mask 0x4000 column 17: offset 1, mask 0x2000 column 18: offset 1, mask 0x1000 column 19: offset 1, mask 0x0002 column 20: offset 1, mask 0x0004 column 21: offset 1, mask 0x0008 column 22: offset 1, mask 0x0800 column 23: offset 1, mask 0x0400 column 24: offset 1, mask 0x0200 column 25: offset 1, mask 0x0010 column 26: offset 1, mask 0x0020 column 27: offset 1, mask 0x0040 column 28: offset 1, mask 0x0080 column 29: offset 2, mask 0x0001 column 30: offset 2, mask 0x0002 direction bits (1=input) 0x24E4 0x9349 0xFFFA 0xFFFF 0xF0FF pullup bits (1=pullup) 0x0000 0x0000 0x0000 0x0000 0x0000 test step out_data dont care 1: 0x2404 0x9249 0x0002 0x0000 0x0000 2: 0xDB1B 0x6CB6 0x0001 0x0000 0x0000 3: 0x7B1B 0x6CB6 0x0001 0x0000 0x0000 4: 0x3B1B 0x6CB6 0x0001 0x0000 0x0000 5: 0xBB1B 0x6CB6 0x0001 0x0000 0x0000 6: 0xDB1B 0x6CB6 0x0001 0x0000 0x0000 7: 0xCF1B 0x6CB6 0x0001 0x0000 0x0000 8: 0xC71B 0x6CB6 0x0001 0x0000 0x0000 9: 0xD71B 0x6CB6 0x0001 0x0000 0x0000 10: 0xDB1B 0x6CB6 0x0001 0x0000 0x0000 11: 0xDB0F 0x6CB6 0x0001 0x0000 0x0000 12: 0xDB07 0x6CB6 0x0001 0x0000 0x0000 13: 0xDB17 0x6CB6 0x0001 0x0000 0x0000 14: 0xDB1B 0x6CB6 0x0001 0x0000 0x0000 15: 0xD91B 0xECB6 0x0001 0x0000 0x0000 16: 0xD81B 0xECB6 0x0001 0x0000 0x0000 17: 0xDA1B 0xECB6 0x0001 0x0000 0x0000 18: 0xDB1B 0x6CB6 0x0001 0x0000 0x0000 19: 0xDB19 0x6CB7 0x0001 0x0000 0x0000 20: 0xDB18 0x6CB7 0x0001 0x0000 0x0000 21: 0xDB1A 0x6CB7 0x0001 0x0000 0x0000 22: 0xDB1B 0x6CB6 0x0001 0x0000 0x0000 23: 0xDB1B 0x3CB6 0x0001 0x0000 0x0000 24: 0xDB1B 0x1CB6 0x0001 0x0000 0x0000 25: 0xDB1B 0x5CB6 0x0001 0x0000 0x0000 26: 0xDB1B 0x6CB6 0x0001 0x0000 0x0000 27: 0xDB1B 0x6CBC 0x0001 0x0000 0x0000 28: 0xDB1B 0x6CB8 0x0001 0x0000 0x0000 29: 0xDB1B 0x6CBA 0x0001 0x0000 0x0000 30: 0xDB1B 0x6CB6 0x0001 0x0000 0x0000 31: 0xDB1B 0x66B6 0x0001 0x0000 0x0000 32: 0xDB1B 0x62B6 0x0001 0x0000 0x0000 33: 0xDB1B 0x6AB6 0x0001 0x0000 0x0000 34: 0xDB1B 0x6CB6 0x0001 0x0000 0x0000 35: 0xDB1B 0x6CE6 0x0001 0x0000 0x0000 36: 0xDB1B 0x6CC6 0x0001 0x0000 0x0000 37: 0xDB1B 0x6CD6 0x0001 0x0000 0x0000 38: 0xDB1B 0x6CB6 0x0001 0x0000 0x0000 39: 0xDB1B 0x6C36 0x0003 0x0000 0x0000 40: 0xDB1B 0x6C36 0x0002 0x0000 0x0000 41: 0xDB1B 0x6CB6 0x0002 0x0000 0x0000 42: 0xDB1B 0x6CB6 0x0001 0x0000 0x0000 43: 0x2404 0x9249 0x0002 0x0000 0x0000 44: 0x6404 0x9249 0x0002 0x0000 0x0000 45: 0xC404 0x9249 0x0002 0x0000 0x0000 46: 0xA404 0x9249 0x0002 0x0000 0x0000 47: 0x2404 0x9249 0x0002 0x0000 0x0000 48: 0x2C04 0x9249 0x0002 0x0000 0x0000 49: 0x3804 0x9249 0x0002 0x0000 0x0000 50: 0x3404 0x9249 0x0002 0x0000 0x0000 51: 0x2404 0x9249 0x0002 0x0000 0x0000 52: 0x240C 0x9249 0x0002 0x0000 0x0000 53: 0x2418 0x9249 0x0002 0x0000 0x0000 54: 0x2414 0x9249 0x0002 0x0000 0x0000 55: 0x2404 0x9249 0x0002 0x0000 0x0000 56: 0x2504 0x9249 0x0002 0x0000 0x0000 57: 0x2704 0x1249 0x0002 0x0000 0x0000 58: 0x2604 0x9249 0x0002 0x0000 0x0000 59: 0x2404 0x9249 0x0002 0x0000 0x0000 60: 0x2405 0x9249 0x0002 0x0000 0x0000 61: 0x2407 0x9248 0x0002 0x0000 0x0000 62: 0x2406 0x9249 0x0002 0x0000 0x0000 63: 0x2404 0x9249 0x0002 0x0000 0x0000 64: 0x2404 0xB249 0x0002 0x0000 0x0000 65: 0x2404 0xE249 0x0002 0x0000 0x0000 66: 0x2404 0xD249 0x0002 0x0000 0x0000 67: 0x2404 0x9249 0x0002 0x0000 0x0000 68: 0x2404 0x924D 0x0002 0x0000 0x0000 69: 0x2404 0x9247 0x0002 0x0000 0x0000 70: 0x2404 0x924B 0x0002 0x0000 0x0000 71: 0x2404 0x9249 0x0002 0x0000 0x0000 72: 0x2404 0x9649 0x0002 0x0000 0x0000 73: 0x2404 0x9C49 0x0002 0x0000 0x0000 74: 0x2404 0x9A49 0x0002 0x0000 0x0000 75: 0x2404 0x9249 0x0002 0x0000 0x0000 76: 0x2404 0x9269 0x0002 0x0000 0x0000 77: 0x2404 0x9239 0x0002 0x0000 0x0000 78: 0x2404 0x9259 0x0002 0x0000 0x0000 79: 0x2404 0x9249 0x0002 0x0000 0x0000 80: 0x2404 0x9249 0x0003 0x0000 0x0000 81: 0x2404 0x92C9 0x0001 0x0000 0x0000 82: 0x2404 0x92C9 0x0002 0x0000 0x0000 83: 0x2404 0x9249 0x0002 0x0000 0x0000 PINs used (in edge connector order) (G=ground,P=power) SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBB LETTER ABCDEFHJKLMNPRSTUVABCDEFHJKLMNPRSTUVABCDEFHJKLMNPRSTUVABCDEFHJKLMNPRSTUV SIDE 111111111111111111222222222222222222111111111111111111222222222222222222 USAGE IIOIIOIIOIIOIIOG P GIIOIIOIIOIIOIIO G P G UUT has 20 inputs UUT has 10 outputs contains 30 pins/columns 36 pins are not used contains 83 'test steps' M113 10 2-input NAND PINS Main menu Mon Aug 10 15:12:50 2015 test file is: tests\m113.tst delay is: 0 trigger is: 1 1 read test file 2 set test delay 3 set test trigger 4 run test 5 output loading test 8 diags 9 exit UUT power is okay Mon Aug 10 15:12:57 2015 space single step O run once (one test, all steps) F run, stop on fail G go (run tests N run, stop on fail, no print S scope (run, no print) C toggle comment printout + increase speed (less delay) - decrease speed (more delay)(slower) Q quit test scope (run, no print) ppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppp ppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppp ppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppp ppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppp ppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppp pppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppp space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C toggle comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFDEFHJKHJKLMNLMNPRSPRSTUV SIDE 111111222111222111222111222222 DIRECTION IIOIIOIIOIIOIIOIIOIIOIIOIIOIIO all fails was lo 000000000000000000000000000000 falling vvvvvvvvvvvvvvvvvvvvvvvvvvvvvv rising ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ was hi 111111111111111111111111111111 total fails 0, total passes 469 Main menu Mon Aug 10 15:13:24 2015 test file is: tests\m113.tst delay is: 0 trigger is: 1 1 read test file 2 set test delay 3 set test trigger 4 run test 5 output loading test 8 diags 9 exit ***************************** UUT power is OFF * ***************************** Main menu Mon Aug 10 15:14:57 2015 test file is: tests\m113.tst delay is: 0 trigger is: 1 1 read test file 2 set test delay 3 set test trigger 4 run test 5 output loading test 8 diags 9 exit UUT power is okay Mon Aug 10 15:15:00 2015 space single step O run once (one test, all steps) F run, stop on fail G go (run tests N run, stop on fail, no print S scope (run, no print) C toggle comment printout + increase speed (less delay) - decrease speed (more delay)(slower) Q quit test scope (run, no print) ppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppp ppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppp ppppppppppppppppppppppppppppppppppppppppppppppppppp space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C toggle comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFDEFHJKHJKLMNLMNPRSPRSTUV SIDE 111111222111222111222111222222 DIRECTION IIOIIOIIOIIOIIOIIOIIOIIOIIOIIO all fails was lo 000000000000000000000000000000 falling vvvvvvvvvvvvvvvvvvvvvvvvvvvvvv rising ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ was hi 111111111111111111111111111111 total fails 0, total passes 209 Main menu Mon Aug 10 15:15:11 2015 test file is: tests\m113.tst delay is: 0 trigger is: 1 1 read test file 2 set test delay 3 set test trigger 4 run test 5 output loading test 8 diags 9 exit UUT power is okay Mon Aug 10 15:17:15 2015 space single step O run once (one test, all steps) F run, stop on fail G go (run tests N run, stop on fail, no print S scope (run, no print) C toggle comment printout + increase speed (less delay) - decrease speed (more delay)(slower) Q quit test scope (run, no print) ppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppp ppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppp ppppppppppppppppppp space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C toggle comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFDEFHJKHJKLMNLMNPRSPRSTUV SIDE 111111222111222111222111222222 DIRECTION IIOIIOIIOIIOIIOIIOIIOIIOIIOIIO all fails was lo 000000000000000000000000000000 falling vvvvvvvvvvvvvvvvvvvvvvvvvvvvvv rising ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ was hi 111111111111111111111111111111 total fails 0, total passes 177 Main menu Mon Aug 10 15:17:25 2015 test file is: tests\m113.tst delay is: 0 trigger is: 1 1 read test file 2 set test delay 3 set test trigger 4 run test 5 output loading test 8 diags 9 exit Enter test file name? trying to open test file: tests\m117.tst reading test file: tests\m117.tst comment: M117 REV 3 6 4-input NAND comment: pins: PINS pins: 1 I AA1 E1-13 pins: 2 I AB1 E1-12 pins: 3 I AC1 E1-10 pins: 4 I AD1 E1-9 pins: 5 O AE1 E1-8 pins: 6 I AF1 E2-13 pins: 7 I AH1 E2-12 pins: 8 I AJ1 E2-10 pins: 9 I AK1 E2-9 pins: 10 O AL1 E2-8 pins: 11 I AM1 E3-13 pins: 12 I AN1 E3-12 pins: 13 I AP1 E3-10 pins: 14 I AR1 E3-9 pins: 15 O AS1 E3-8 pins: 16 I AD2 E1-5 pins: 17 I AE2 E1-4 pins: 18 I AF2 E1-2 pins: 19 I AH2 E1-1 pins: 20 O AJ2 E1-6 pins: 21 I AK2 E2-5 pins: 22 I AL2 E2-4 pins: 23 I AM2 E2-2 pins: 24 I AN2 E2-1 pins: 25 O AP2 E2-6 pins: 26 I AR2 E3-1 pins: 27 I AS2 E3-2 pins: 28 I AT2 E3-4 pins: 29 I AU2 E3-5 pins: 30 O AV2 E3-6 pins: direction: IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO test 1: 000010000100001000010000100001 test 2: 00001 test 3: 00011 test 4: 00101 test 5: 00111 test 6: 01001 test 7: 01011 test 8: 01101 test 9: 01111 test 10: 10001 test 11: 10011 test 12: 10101 test 13: 10111 test 14: 11001 test 15: 11011 test 16: 11101 test 17: 11110 test 18: 00001 test 19: 00001 test 20: 00011 test 21: 00101 test 22: 00111 test 23: 01001 test 24: 01011 test 25: 01101 test 26: 01111 test 27: 10001 test 28: 10011 test 29: 10101 test 30: 10111 test 31: 11001 test 32: 11011 test 33: 11101 test 34: 11110 test 35: 00001 test 36: 00001 test 37: 00011 test 38: 00101 test 39: 00111 test 40: 01001 test 41: 01011 test 42: 01101 test 43: 01111 test 44: 10001 test 45: 10011 test 46: 10101 test 47: 10111 test 48: 11001 test 49: 11011 test 50: 11101 test 51: 11110 test 52: 00001 test 53: 00001 test 54: 00011 test 55: 00101 test 56: 00111 test 57: 01001 test 58: 01011 test 59: 01101 test 60: 01111 test 61: 10001 test 62: 10011 test 63: 10101 test 64: 10111 test 65: 11001 test 66: 11011 test 67: 11101 test 68: 11110 test 69: 00001 test 70: 00001 test 71: 00011 test 72: 00101 test 73: 00111 test 74: 01001 test 75: 01011 test 76: 01101 test 77: 01111 test 78: 10001 test 79: 10011 test 80: 10101 test 81: 10111 test 82: 11001 test 83: 11011 test 84: 11101 test 85: 11110 test 86: 00001 test 87: 00001 test 88: 00011 test 89: 00101 test 90: 00111 test 91: 01001 test 92: 01011 test 93: 01101 test 94: 01111 test 95: 10001 test 96: 10011 test 97: 10101 test 98: 10111 test 99: 11001 test 100: 11011 test 101: 11101 test 102: 11110 test 103: 00001 test 104: 000010000100001000010000100001 test 105: 111101111011110111101111011110 test 106: 00001 test 107: 00011 test 108: 00101 test 109: 00111 test 110: 01001 test 111: 01011 test 112: 01101 test 113: 01111 test 114: 10001 test 115: 10011 test 116: 10101 test 117: 10111 test 118: 11001 test 119: 11011 test 120: 11101 test 121: 11110 test 122: 00001 test 123: 00011 test 124: 00101 test 125: 00111 test 126: 01001 test 127: 01011 test 128: 01101 test 129: 01111 test 130: 10001 test 131: 10011 test 132: 10101 test 133: 10111 test 134: 11001 test 135: 11011 test 136: 11101 test 137: 11110 test 138: 00001 test 139: 00011 test 140: 00101 test 141: 00111 test 142: 01001 test 143: 01011 test 144: 01101 test 145: 01111 test 146: 10001 test 147: 10011 test 148: 10101 test 149: 10111 test 150: 11001 test 151: 11011 test 152: 11101 test 153: 11110 test 154: 00001 test 155: 00011 test 156: 00101 test 157: 00111 test 158: 01001 test 159: 01011 test 160: 01101 test 161: 01111 test 162: 10001 test 163: 10011 test 164: 10101 test 165: 10111 test 166: 11001 test 167: 11011 test 168: 11101 test 169: 11110 test 170: 00001 test 171: 00011 test 172: 00101 test 173: 00111 test 174: 01001 test 175: 01011 test 176: 01101 test 177: 01111 test 178: 10001 test 179: 10011 test 180: 10101 test 181: 10111 test 182: 11001 test 183: 11011 test 184: 11101 test 185: 11110 test 186: 00001 test 187: 00011 test 188: 00101 test 189: 00111 test 190: 01001 test 191: 01011 test 192: 01101 test 193: 01111 test 194: 10001 test 195: 10011 test 196: 10101 test 197: 10111 test 198: 11001 test 199: 11011 test 200: 11101 test 201: 11110 test 202: 111101111011110111101111011110 end: END summary column 1: offset 0, mask 0x8000 column 2: offset 0, mask 0x4000 column 3: offset 0, mask 0x2000 column 4: offset 0, mask 0x1000 column 5: offset 0, mask 0x0800 column 6: offset 0, mask 0x0400 column 7: offset 0, mask 0x0200 column 8: offset 0, mask 0x0100 column 9: offset 1, mask 0x8000 column 10: offset 1, mask 0x4000 column 11: offset 1, mask 0x2000 column 12: offset 1, mask 0x1000 column 13: offset 1, mask 0x0800 column 14: offset 1, mask 0x0400 column 15: offset 1, mask 0x0200 column 16: offset 0, mask 0x0010 column 17: offset 0, mask 0x0008 column 18: offset 0, mask 0x0004 column 19: offset 0, mask 0x0002 column 20: offset 0, mask 0x0001 column 21: offset 1, mask 0x0001 column 22: offset 1, mask 0x0002 column 23: offset 1, mask 0x0004 column 24: offset 1, mask 0x0008 column 25: offset 1, mask 0x0010 column 26: offset 1, mask 0x0020 column 27: offset 1, mask 0x0040 column 28: offset 1, mask 0x0080 column 29: offset 2, mask 0x0001 column 30: offset 2, mask 0x0002 direction bits (1=input) 0x08E1 0x4310 0xFFFA 0xFFFF 0xF0FF pullup bits (1=pullup) 0x0000 0x0000 0x0000 0x0000 0x0000 test step out_data dont care 1: 0x0801 0x4210 0x0002 0x0000 0x0000 2: 0x0801 0x4210 0x0002 0x0000 0x0000 3: 0x1801 0x4210 0x0002 0x0000 0x0000 4: 0x2801 0x4210 0x0002 0x0000 0x0000 5: 0x3801 0x4210 0x0002 0x0000 0x0000 6: 0x4801 0x4210 0x0002 0x0000 0x0000 7: 0x5801 0x4210 0x0002 0x0000 0x0000 8: 0x6801 0x4210 0x0002 0x0000 0x0000 9: 0x7801 0x4210 0x0002 0x0000 0x0000 10: 0x8801 0x4210 0x0002 0x0000 0x0000 11: 0x9801 0x4210 0x0002 0x0000 0x0000 12: 0xA801 0x4210 0x0002 0x0000 0x0000 13: 0xB801 0x4210 0x0002 0x0000 0x0000 14: 0xC801 0x4210 0x0002 0x0000 0x0000 15: 0xD801 0x4210 0x0002 0x0000 0x0000 16: 0xE801 0x4210 0x0002 0x0000 0x0000 17: 0xF001 0x4210 0x0002 0x0000 0x0000 18: 0x0801 0x4210 0x0002 0x0000 0x0000 19: 0x0801 0x4210 0x0002 0x0000 0x0000 20: 0x0801 0xC210 0x0002 0x0000 0x0000 21: 0x0901 0x4210 0x0002 0x0000 0x0000 22: 0x0901 0xC210 0x0002 0x0000 0x0000 23: 0x0A01 0x4210 0x0002 0x0000 0x0000 24: 0x0A01 0xC210 0x0002 0x0000 0x0000 25: 0x0B01 0x4210 0x0002 0x0000 0x0000 26: 0x0B01 0xC210 0x0002 0x0000 0x0000 27: 0x0C01 0x4210 0x0002 0x0000 0x0000 28: 0x0C01 0xC210 0x0002 0x0000 0x0000 29: 0x0D01 0x4210 0x0002 0x0000 0x0000 30: 0x0D01 0xC210 0x0002 0x0000 0x0000 31: 0x0E01 0x4210 0x0002 0x0000 0x0000 32: 0x0E01 0xC210 0x0002 0x0000 0x0000 33: 0x0F01 0x4210 0x0002 0x0000 0x0000 34: 0x0F01 0x8210 0x0002 0x0000 0x0000 35: 0x0801 0x4210 0x0002 0x0000 0x0000 36: 0x0801 0x4210 0x0002 0x0000 0x0000 37: 0x0801 0x4610 0x0002 0x0000 0x0000 38: 0x0801 0x4A10 0x0002 0x0000 0x0000 39: 0x0801 0x4E10 0x0002 0x0000 0x0000 40: 0x0801 0x5210 0x0002 0x0000 0x0000 41: 0x0801 0x5610 0x0002 0x0000 0x0000 42: 0x0801 0x5A10 0x0002 0x0000 0x0000 43: 0x0801 0x5E10 0x0002 0x0000 0x0000 44: 0x0801 0x6210 0x0002 0x0000 0x0000 45: 0x0801 0x6610 0x0002 0x0000 0x0000 46: 0x0801 0x6A10 0x0002 0x0000 0x0000 47: 0x0801 0x6E10 0x0002 0x0000 0x0000 48: 0x0801 0x7210 0x0002 0x0000 0x0000 49: 0x0801 0x7610 0x0002 0x0000 0x0000 50: 0x0801 0x7A10 0x0002 0x0000 0x0000 51: 0x0801 0x7C10 0x0002 0x0000 0x0000 52: 0x0801 0x4210 0x0002 0x0000 0x0000 53: 0x0801 0x4210 0x0002 0x0000 0x0000 54: 0x0803 0x4210 0x0002 0x0000 0x0000 55: 0x0805 0x4210 0x0002 0x0000 0x0000 56: 0x0807 0x4210 0x0002 0x0000 0x0000 57: 0x0809 0x4210 0x0002 0x0000 0x0000 58: 0x080B 0x4210 0x0002 0x0000 0x0000 59: 0x080D 0x4210 0x0002 0x0000 0x0000 60: 0x080F 0x4210 0x0002 0x0000 0x0000 61: 0x0811 0x4210 0x0002 0x0000 0x0000 62: 0x0813 0x4210 0x0002 0x0000 0x0000 63: 0x0815 0x4210 0x0002 0x0000 0x0000 64: 0x0817 0x4210 0x0002 0x0000 0x0000 65: 0x0819 0x4210 0x0002 0x0000 0x0000 66: 0x081B 0x4210 0x0002 0x0000 0x0000 67: 0x081D 0x4210 0x0002 0x0000 0x0000 68: 0x081E 0x4210 0x0002 0x0000 0x0000 69: 0x0801 0x4210 0x0002 0x0000 0x0000 70: 0x0801 0x4210 0x0002 0x0000 0x0000 71: 0x0801 0x4218 0x0002 0x0000 0x0000 72: 0x0801 0x4214 0x0002 0x0000 0x0000 73: 0x0801 0x421C 0x0002 0x0000 0x0000 74: 0x0801 0x4212 0x0002 0x0000 0x0000 75: 0x0801 0x421A 0x0002 0x0000 0x0000 76: 0x0801 0x4216 0x0002 0x0000 0x0000 77: 0x0801 0x421E 0x0002 0x0000 0x0000 78: 0x0801 0x4211 0x0002 0x0000 0x0000 79: 0x0801 0x4219 0x0002 0x0000 0x0000 80: 0x0801 0x4215 0x0002 0x0000 0x0000 81: 0x0801 0x421D 0x0002 0x0000 0x0000 82: 0x0801 0x4213 0x0002 0x0000 0x0000 83: 0x0801 0x421B 0x0002 0x0000 0x0000 84: 0x0801 0x4217 0x0002 0x0000 0x0000 85: 0x0801 0x420F 0x0002 0x0000 0x0000 86: 0x0801 0x4210 0x0002 0x0000 0x0000 87: 0x0801 0x4210 0x0002 0x0000 0x0000 88: 0x0801 0x4210 0x0003 0x0000 0x0000 89: 0x0801 0x4290 0x0002 0x0000 0x0000 90: 0x0801 0x4290 0x0003 0x0000 0x0000 91: 0x0801 0x4250 0x0002 0x0000 0x0000 92: 0x0801 0x4250 0x0003 0x0000 0x0000 93: 0x0801 0x42D0 0x0002 0x0000 0x0000 94: 0x0801 0x42D0 0x0003 0x0000 0x0000 95: 0x0801 0x4230 0x0002 0x0000 0x0000 96: 0x0801 0x4230 0x0003 0x0000 0x0000 97: 0x0801 0x42B0 0x0002 0x0000 0x0000 98: 0x0801 0x42B0 0x0003 0x0000 0x0000 99: 0x0801 0x4270 0x0002 0x0000 0x0000 100: 0x0801 0x4270 0x0003 0x0000 0x0000 101: 0x0801 0x42F0 0x0002 0x0000 0x0000 102: 0x0801 0x42F0 0x0001 0x0000 0x0000 103: 0x0801 0x4210 0x0002 0x0000 0x0000 104: 0x0801 0x4210 0x0002 0x0000 0x0000 105: 0xF71E 0xBCEF 0x0001 0x0000 0x0000 106: 0x0F1E 0xBCEF 0x0001 0x0000 0x0000 107: 0x1F1E 0xBCEF 0x0001 0x0000 0x0000 108: 0x2F1E 0xBCEF 0x0001 0x0000 0x0000 109: 0x3F1E 0xBCEF 0x0001 0x0000 0x0000 110: 0x4F1E 0xBCEF 0x0001 0x0000 0x0000 111: 0x5F1E 0xBCEF 0x0001 0x0000 0x0000 112: 0x6F1E 0xBCEF 0x0001 0x0000 0x0000 113: 0x7F1E 0xBCEF 0x0001 0x0000 0x0000 114: 0x8F1E 0xBCEF 0x0001 0x0000 0x0000 115: 0x9F1E 0xBCEF 0x0001 0x0000 0x0000 116: 0xAF1E 0xBCEF 0x0001 0x0000 0x0000 117: 0xBF1E 0xBCEF 0x0001 0x0000 0x0000 118: 0xCF1E 0xBCEF 0x0001 0x0000 0x0000 119: 0xDF1E 0xBCEF 0x0001 0x0000 0x0000 120: 0xEF1E 0xBCEF 0x0001 0x0000 0x0000 121: 0xF71E 0xBCEF 0x0001 0x0000 0x0000 122: 0xF01E 0x7CEF 0x0001 0x0000 0x0000 123: 0xF01E 0xFCEF 0x0001 0x0000 0x0000 124: 0xF11E 0x7CEF 0x0001 0x0000 0x0000 125: 0xF11E 0xFCEF 0x0001 0x0000 0x0000 126: 0xF21E 0x7CEF 0x0001 0x0000 0x0000 127: 0xF21E 0xFCEF 0x0001 0x0000 0x0000 128: 0xF31E 0x7CEF 0x0001 0x0000 0x0000 129: 0xF31E 0xFCEF 0x0001 0x0000 0x0000 130: 0xF41E 0x7CEF 0x0001 0x0000 0x0000 131: 0xF41E 0xFCEF 0x0001 0x0000 0x0000 132: 0xF51E 0x7CEF 0x0001 0x0000 0x0000 133: 0xF51E 0xFCEF 0x0001 0x0000 0x0000 134: 0xF61E 0x7CEF 0x0001 0x0000 0x0000 135: 0xF61E 0xFCEF 0x0001 0x0000 0x0000 136: 0xF71E 0x7CEF 0x0001 0x0000 0x0000 137: 0xF71E 0xBCEF 0x0001 0x0000 0x0000 138: 0xF71E 0x82EF 0x0001 0x0000 0x0000 139: 0xF71E 0x86EF 0x0001 0x0000 0x0000 140: 0xF71E 0x8AEF 0x0001 0x0000 0x0000 141: 0xF71E 0x8EEF 0x0001 0x0000 0x0000 142: 0xF71E 0x92EF 0x0001 0x0000 0x0000 143: 0xF71E 0x96EF 0x0001 0x0000 0x0000 144: 0xF71E 0x9AEF 0x0001 0x0000 0x0000 145: 0xF71E 0x9EEF 0x0001 0x0000 0x0000 146: 0xF71E 0xA2EF 0x0001 0x0000 0x0000 147: 0xF71E 0xA6EF 0x0001 0x0000 0x0000 148: 0xF71E 0xAAEF 0x0001 0x0000 0x0000 149: 0xF71E 0xAEEF 0x0001 0x0000 0x0000 150: 0xF71E 0xB2EF 0x0001 0x0000 0x0000 151: 0xF71E 0xB6EF 0x0001 0x0000 0x0000 152: 0xF71E 0xBAEF 0x0001 0x0000 0x0000 153: 0xF71E 0xBCEF 0x0001 0x0000 0x0000 154: 0xF701 0xBCEF 0x0001 0x0000 0x0000 155: 0xF703 0xBCEF 0x0001 0x0000 0x0000 156: 0xF705 0xBCEF 0x0001 0x0000 0x0000 157: 0xF707 0xBCEF 0x0001 0x0000 0x0000 158: 0xF709 0xBCEF 0x0001 0x0000 0x0000 159: 0xF70B 0xBCEF 0x0001 0x0000 0x0000 160: 0xF70D 0xBCEF 0x0001 0x0000 0x0000 161: 0xF70F 0xBCEF 0x0001 0x0000 0x0000 162: 0xF711 0xBCEF 0x0001 0x0000 0x0000 163: 0xF713 0xBCEF 0x0001 0x0000 0x0000 164: 0xF715 0xBCEF 0x0001 0x0000 0x0000 165: 0xF717 0xBCEF 0x0001 0x0000 0x0000 166: 0xF719 0xBCEF 0x0001 0x0000 0x0000 167: 0xF71B 0xBCEF 0x0001 0x0000 0x0000 168: 0xF71D 0xBCEF 0x0001 0x0000 0x0000 169: 0xF71E 0xBCEF 0x0001 0x0000 0x0000 170: 0xF71E 0xBCF0 0x0001 0x0000 0x0000 171: 0xF71E 0xBCF8 0x0001 0x0000 0x0000 172: 0xF71E 0xBCF4 0x0001 0x0000 0x0000 173: 0xF71E 0xBCFC 0x0001 0x0000 0x0000 174: 0xF71E 0xBCF2 0x0001 0x0000 0x0000 175: 0xF71E 0xBCFA 0x0001 0x0000 0x0000 176: 0xF71E 0xBCF6 0x0001 0x0000 0x0000 177: 0xF71E 0xBCFE 0x0001 0x0000 0x0000 178: 0xF71E 0xBCF1 0x0001 0x0000 0x0000 179: 0xF71E 0xBCF9 0x0001 0x0000 0x0000 180: 0xF71E 0xBCF5 0x0001 0x0000 0x0000 181: 0xF71E 0xBCFD 0x0001 0x0000 0x0000 182: 0xF71E 0xBCF3 0x0001 0x0000 0x0000 183: 0xF71E 0xBCFB 0x0001 0x0000 0x0000 184: 0xF71E 0xBCF7 0x0001 0x0000 0x0000 185: 0xF71E 0xBCEF 0x0001 0x0000 0x0000 186: 0xF71E 0xBC0F 0x0002 0x0000 0x0000 187: 0xF71E 0xBC0F 0x0003 0x0000 0x0000 188: 0xF71E 0xBC8F 0x0002 0x0000 0x0000 189: 0xF71E 0xBC8F 0x0003 0x0000 0x0000 190: 0xF71E 0xBC4F 0x0002 0x0000 0x0000 191: 0xF71E 0xBC4F 0x0003 0x0000 0x0000 192: 0xF71E 0xBCCF 0x0002 0x0000 0x0000 193: 0xF71E 0xBCCF 0x0003 0x0000 0x0000 194: 0xF71E 0xBC2F 0x0002 0x0000 0x0000 195: 0xF71E 0xBC2F 0x0003 0x0000 0x0000 196: 0xF71E 0xBCAF 0x0002 0x0000 0x0000 197: 0xF71E 0xBCAF 0x0003 0x0000 0x0000 198: 0xF71E 0xBC6F 0x0002 0x0000 0x0000 199: 0xF71E 0xBC6F 0x0003 0x0000 0x0000 200: 0xF71E 0xBCEF 0x0002 0x0000 0x0000 201: 0xF71E 0xBCEF 0x0001 0x0000 0x0000 202: 0xF71E 0xBCEF 0x0001 0x0000 0x0000 PINs used (in edge connector order) (G=ground,P=power) SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBB LETTER ABCDEFHJKLMNPRSTUVABCDEFHJKLMNPRSTUVABCDEFHJKLMNPRSTUVABCDEFHJKLMNPRSTUV SIDE 111111111111111111222222222222222222111111111111111111222222222222222222 USAGE IIIIOIIIIOIIIIOG P GIIIIOIIIIOIIIIO G P G UUT has 24 inputs UUT has 6 outputs contains 30 pins/columns 36 pins are not used contains 202 'test steps' M117 REV 3 6 4-input NAND PINS Main menu Mon Aug 10 15:19:08 2015 test file is: tests\m117.tst delay is: 0 trigger is: 1 1 read test file 2 set test delay 3 set test trigger 4 run test 5 output loading test 8 diags 9 exit ***************************** UUT power is OFF * ***************************** Main menu Mon Aug 10 15:19:10 2015 test file is: tests\m117.tst delay is: 0 trigger is: 1 1 read test file 2 set test delay 3 set test trigger 4 run test 5 output loading test 8 diags 9 exit UUT power is okay Mon Aug 10 15:19:12 2015 space single step O run once (one test, all steps) F run, stop on fail G go (run tests N run, stop on fail, no print S scope (run, no print) C toggle comment printout + increase speed (less delay) - decrease speed (more delay)(slower) Q quit test scope (run, no print) ppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppp ppppp space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C toggle comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFHJKLMNPRSDEFHJKLMNPRSTUV SIDE 111111111111111222222222222222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO all fails was lo 000000000000000000000000000000 falling vvvvvvvvvvvvvvvvvvvvvvvvvvvvvv rising ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ was hi 111111111111111111111111111111 total fails 0, total passes 84 Main menu Mon Aug 10 15:19:21 2015 test file is: tests\m117.tst delay is: 0 trigger is: 1 1 read test file 2 set test delay 3 set test trigger 4 run test 5 output loading test 8 diags 9 exit UUT power is okay Mon Aug 10 15:20:15 2015 space single step O run once (one test, all steps) F run, stop on fail G go (run tests N run, stop on fail, no print S scope (run, no print) C toggle comment printout + increase speed (less delay) - decrease speed (more delay)(slower) Q quit test scope (run, no print) ppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppp ppp space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C toggle comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFHJKLMNPRSDEFHJKLMNPRSTUV SIDE 111111111111111222222222222222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO all fails was lo 000000000000000000000000000000 falling vvvvvvvvvvvvvvvvvvvvvvvvvvvvvv rising ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ was hi 111111111111111111111111111111 total fails 0, total passes 82 Main menu Mon Aug 10 15:20:25 2015 test file is: tests\m117.tst delay is: 0 trigger is: 1 1 read test file 2 set test delay 3 set test trigger 4 run test 5 output loading test 8 diags 9 exit Enter test file name? trying to open test file: tests\m302.tst could not open test file. valid test files are: reverting back to test file: tests\m117.tst Main menu Mon Aug 10 15:27:49 2015 test file is: tests\m117.tst delay is: 0 trigger is: 1 1 read test file 2 set test delay 3 set test trigger 4 run test 5 output loading test 8 diags 9 exit Enter test file name? trying to open test file: tests\m302.tst could not open test file. valid test files are: reverting back to test file: tests\m117.tst Main menu Mon Aug 10 15:28:16 2015 test file is: tests\m117.tst delay is: 0 trigger is: 1 1 read test file 2 set test delay 3 set test trigger 4 run test 5 output loading test 8 diags 9 exit key is 0x0030 Main menu Mon Aug 10 15:34:48 2015 test file is: tests\m117.tst delay is: 0 trigger is: 1 1 read test file 2 set test delay 3 set test trigger 4 run test 5 output loading test 8 diags 9 exit exiting tester- PDP8 card tester via printer port version 0.85 June 4, 2015 mapping[] is verified Main menu Mon Aug 10 15:42:26 2015 test file is: delay is: 0 trigger is: 1 1 read test file 2 set test delay 3 set test trigger 4 run test 5 output loading test 8 diags 9 exit Enter test file name? trying to open test file: tests\m117.tst reading test file: tests\m117.tst comment: M117 REV 3 6 4-input NAND comment: pins: PINS pins: 1 I AA1 E1-13 pins: 2 I AB1 E1-12 pins: 3 I AC1 E1-10 pins: 4 I AD1 E1-9 pins: 5 O AE1 E1-8 pins: 6 I AF1 E2-13 pins: 7 I AH1 E2-12 pins: 8 I AJ1 E2-10 pins: 9 I AK1 E2-9 pins: 10 O AL1 E2-8 pins: 11 I AM1 E3-13 pins: 12 I AN1 E3-12 pins: 13 I AP1 E3-10 pins: 14 I AR1 E3-9 pins: 15 O AS1 E3-8 pins: 16 I AD2 E1-5 pins: 17 I AE2 E1-4 pins: 18 I AF2 E1-2 pins: 19 I AH2 E1-1 pins: 20 O AJ2 E1-6 pins: 21 I AK2 E2-5 pins: 22 I AL2 E2-4 pins: 23 I AM2 E2-2 pins: 24 I AN2 E2-1 pins: 25 O AP2 E2-6 pins: 26 I AR2 E3-1 pins: 27 I AS2 E3-2 pins: 28 I AT2 E3-4 pins: 29 I AU2 E3-5 pins: 30 O AV2 E3-6 pins: direction: IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO test 1: 000010000100001000010000100001 test 2: 00001 test 3: 00011 test 4: 00101 test 5: 00111 test 6: 01001 test 7: 01011 test 8: 01101 test 9: 01111 test 10: 10001 test 11: 10011 test 12: 10101 test 13: 10111 test 14: 11001 test 15: 11011 test 16: 11101 test 17: 11110 test 18: 00001 test 19: 00001 test 20: 00011 test 21: 00101 test 22: 00111 test 23: 01001 test 24: 01011 test 25: 01101 test 26: 01111 test 27: 10001 test 28: 10011 test 29: 10101 test 30: 10111 test 31: 11001 test 32: 11011 test 33: 11101 test 34: 11110 test 35: 00001 test 36: 00001 test 37: 00011 test 38: 00101 test 39: 00111 test 40: 01001 test 41: 01011 test 42: 01101 test 43: 01111 test 44: 10001 test 45: 10011 test 46: 10101 test 47: 10111 test 48: 11001 test 49: 11011 test 50: 11101 test 51: 11110 test 52: 00001 test 53: 00001 test 54: 00011 test 55: 00101 test 56: 00111 test 57: 01001 test 58: 01011 test 59: 01101 test 60: 01111 test 61: 10001 test 62: 10011 test 63: 10101 test 64: 10111 test 65: 11001 test 66: 11011 test 67: 11101 test 68: 11110 test 69: 00001 test 70: 00001 test 71: 00011 test 72: 00101 test 73: 00111 test 74: 01001 test 75: 01011 test 76: 01101 test 77: 01111 test 78: 10001 test 79: 10011 test 80: 10101 test 81: 10111 test 82: 11001 test 83: 11011 test 84: 11101 test 85: 11110 test 86: 00001 test 87: 00001 test 88: 00011 test 89: 00101 test 90: 00111 test 91: 01001 test 92: 01011 test 93: 01101 test 94: 01111 test 95: 10001 test 96: 10011 test 97: 10101 test 98: 10111 test 99: 11001 test 100: 11011 test 101: 11101 test 102: 11110 test 103: 00001 test 104: 000010000100001000010000100001 test 105: 111101111011110111101111011110 test 106: 00001 test 107: 00011 test 108: 00101 test 109: 00111 test 110: 01001 test 111: 01011 test 112: 01101 test 113: 01111 test 114: 10001 test 115: 10011 test 116: 10101 test 117: 10111 test 118: 11001 test 119: 11011 test 120: 11101 test 121: 11110 test 122: 00001 test 123: 00011 test 124: 00101 test 125: 00111 test 126: 01001 test 127: 01011 test 128: 01101 test 129: 01111 test 130: 10001 test 131: 10011 test 132: 10101 test 133: 10111 test 134: 11001 test 135: 11011 test 136: 11101 test 137: 11110 test 138: 00001 test 139: 00011 test 140: 00101 test 141: 00111 test 142: 01001 test 143: 01011 test 144: 01101 test 145: 01111 test 146: 10001 test 147: 10011 test 148: 10101 test 149: 10111 test 150: 11001 test 151: 11011 test 152: 11101 test 153: 11110 test 154: 00001 test 155: 00011 test 156: 00101 test 157: 00111 test 158: 01001 test 159: 01011 test 160: 01101 test 161: 01111 test 162: 10001 test 163: 10011 test 164: 10101 test 165: 10111 test 166: 11001 test 167: 11011 test 168: 11101 test 169: 11110 test 170: 00001 test 171: 00011 test 172: 00101 test 173: 00111 test 174: 01001 test 175: 01011 test 176: 01101 test 177: 01111 test 178: 10001 test 179: 10011 test 180: 10101 test 181: 10111 test 182: 11001 test 183: 11011 test 184: 11101 test 185: 11110 test 186: 00001 test 187: 00011 test 188: 00101 test 189: 00111 test 190: 01001 test 191: 01011 test 192: 01101 test 193: 01111 test 194: 10001 test 195: 10011 test 196: 10101 test 197: 10111 test 198: 11001 test 199: 11011 test 200: 11101 test 201: 11110 test 202: 111101111011110111101111011110 end: END summary column 1: offset 0, mask 0x8000 column 2: offset 0, mask 0x4000 column 3: offset 0, mask 0x2000 column 4: offset 0, mask 0x1000 column 5: offset 0, mask 0x0800 column 6: offset 0, mask 0x0400 column 7: offset 0, mask 0x0200 column 8: offset 0, mask 0x0100 column 9: offset 1, mask 0x8000 column 10: offset 1, mask 0x4000 column 11: offset 1, mask 0x2000 column 12: offset 1, mask 0x1000 column 13: offset 1, mask 0x0800 column 14: offset 1, mask 0x0400 column 15: offset 1, mask 0x0200 column 16: offset 0, mask 0x0010 column 17: offset 0, mask 0x0008 column 18: offset 0, mask 0x0004 column 19: offset 0, mask 0x0002 column 20: offset 0, mask 0x0001 column 21: offset 1, mask 0x0001 column 22: offset 1, mask 0x0002 column 23: offset 1, mask 0x0004 column 24: offset 1, mask 0x0008 column 25: offset 1, mask 0x0010 column 26: offset 1, mask 0x0020 column 27: offset 1, mask 0x0040 column 28: offset 1, mask 0x0080 column 29: offset 2, mask 0x0001 column 30: offset 2, mask 0x0002 direction bits (1=input) 0x08E1 0x4310 0xFFFA 0xFFFF 0xF0FF pullup bits (1=pullup) 0x0000 0x0000 0x0000 0x0000 0x0000 test step out_data dont care 1: 0x0801 0x4210 0x0002 0x0000 0x0000 2: 0x0801 0x4210 0x0002 0x0000 0x0000 3: 0x1801 0x4210 0x0002 0x0000 0x0000 4: 0x2801 0x4210 0x0002 0x0000 0x0000 5: 0x3801 0x4210 0x0002 0x0000 0x0000 6: 0x4801 0x4210 0x0002 0x0000 0x0000 7: 0x5801 0x4210 0x0002 0x0000 0x0000 8: 0x6801 0x4210 0x0002 0x0000 0x0000 9: 0x7801 0x4210 0x0002 0x0000 0x0000 10: 0x8801 0x4210 0x0002 0x0000 0x0000 11: 0x9801 0x4210 0x0002 0x0000 0x0000 12: 0xA801 0x4210 0x0002 0x0000 0x0000 13: 0xB801 0x4210 0x0002 0x0000 0x0000 14: 0xC801 0x4210 0x0002 0x0000 0x0000 15: 0xD801 0x4210 0x0002 0x0000 0x0000 16: 0xE801 0x4210 0x0002 0x0000 0x0000 17: 0xF001 0x4210 0x0002 0x0000 0x0000 18: 0x0801 0x4210 0x0002 0x0000 0x0000 19: 0x0801 0x4210 0x0002 0x0000 0x0000 20: 0x0801 0xC210 0x0002 0x0000 0x0000 21: 0x0901 0x4210 0x0002 0x0000 0x0000 22: 0x0901 0xC210 0x0002 0x0000 0x0000 23: 0x0A01 0x4210 0x0002 0x0000 0x0000 24: 0x0A01 0xC210 0x0002 0x0000 0x0000 25: 0x0B01 0x4210 0x0002 0x0000 0x0000 26: 0x0B01 0xC210 0x0002 0x0000 0x0000 27: 0x0C01 0x4210 0x0002 0x0000 0x0000 28: 0x0C01 0xC210 0x0002 0x0000 0x0000 29: 0x0D01 0x4210 0x0002 0x0000 0x0000 30: 0x0D01 0xC210 0x0002 0x0000 0x0000 31: 0x0E01 0x4210 0x0002 0x0000 0x0000 32: 0x0E01 0xC210 0x0002 0x0000 0x0000 33: 0x0F01 0x4210 0x0002 0x0000 0x0000 34: 0x0F01 0x8210 0x0002 0x0000 0x0000 35: 0x0801 0x4210 0x0002 0x0000 0x0000 36: 0x0801 0x4210 0x0002 0x0000 0x0000 37: 0x0801 0x4610 0x0002 0x0000 0x0000 38: 0x0801 0x4A10 0x0002 0x0000 0x0000 39: 0x0801 0x4E10 0x0002 0x0000 0x0000 40: 0x0801 0x5210 0x0002 0x0000 0x0000 41: 0x0801 0x5610 0x0002 0x0000 0x0000 42: 0x0801 0x5A10 0x0002 0x0000 0x0000 43: 0x0801 0x5E10 0x0002 0x0000 0x0000 44: 0x0801 0x6210 0x0002 0x0000 0x0000 45: 0x0801 0x6610 0x0002 0x0000 0x0000 46: 0x0801 0x6A10 0x0002 0x0000 0x0000 47: 0x0801 0x6E10 0x0002 0x0000 0x0000 48: 0x0801 0x7210 0x0002 0x0000 0x0000 49: 0x0801 0x7610 0x0002 0x0000 0x0000 50: 0x0801 0x7A10 0x0002 0x0000 0x0000 51: 0x0801 0x7C10 0x0002 0x0000 0x0000 52: 0x0801 0x4210 0x0002 0x0000 0x0000 53: 0x0801 0x4210 0x0002 0x0000 0x0000 54: 0x0803 0x4210 0x0002 0x0000 0x0000 55: 0x0805 0x4210 0x0002 0x0000 0x0000 56: 0x0807 0x4210 0x0002 0x0000 0x0000 57: 0x0809 0x4210 0x0002 0x0000 0x0000 58: 0x080B 0x4210 0x0002 0x0000 0x0000 59: 0x080D 0x4210 0x0002 0x0000 0x0000 60: 0x080F 0x4210 0x0002 0x0000 0x0000 61: 0x0811 0x4210 0x0002 0x0000 0x0000 62: 0x0813 0x4210 0x0002 0x0000 0x0000 63: 0x0815 0x4210 0x0002 0x0000 0x0000 64: 0x0817 0x4210 0x0002 0x0000 0x0000 65: 0x0819 0x4210 0x0002 0x0000 0x0000 66: 0x081B 0x4210 0x0002 0x0000 0x0000 67: 0x081D 0x4210 0x0002 0x0000 0x0000 68: 0x081E 0x4210 0x0002 0x0000 0x0000 69: 0x0801 0x4210 0x0002 0x0000 0x0000 70: 0x0801 0x4210 0x0002 0x0000 0x0000 71: 0x0801 0x4218 0x0002 0x0000 0x0000 72: 0x0801 0x4214 0x0002 0x0000 0x0000 73: 0x0801 0x421C 0x0002 0x0000 0x0000 74: 0x0801 0x4212 0x0002 0x0000 0x0000 75: 0x0801 0x421A 0x0002 0x0000 0x0000 76: 0x0801 0x4216 0x0002 0x0000 0x0000 77: 0x0801 0x421E 0x0002 0x0000 0x0000 78: 0x0801 0x4211 0x0002 0x0000 0x0000 79: 0x0801 0x4219 0x0002 0x0000 0x0000 80: 0x0801 0x4215 0x0002 0x0000 0x0000 81: 0x0801 0x421D 0x0002 0x0000 0x0000 82: 0x0801 0x4213 0x0002 0x0000 0x0000 83: 0x0801 0x421B 0x0002 0x0000 0x0000 84: 0x0801 0x4217 0x0002 0x0000 0x0000 85: 0x0801 0x420F 0x0002 0x0000 0x0000 86: 0x0801 0x4210 0x0002 0x0000 0x0000 87: 0x0801 0x4210 0x0002 0x0000 0x0000 88: 0x0801 0x4210 0x0003 0x0000 0x0000 89: 0x0801 0x4290 0x0002 0x0000 0x0000 90: 0x0801 0x4290 0x0003 0x0000 0x0000 91: 0x0801 0x4250 0x0002 0x0000 0x0000 92: 0x0801 0x4250 0x0003 0x0000 0x0000 93: 0x0801 0x42D0 0x0002 0x0000 0x0000 94: 0x0801 0x42D0 0x0003 0x0000 0x0000 95: 0x0801 0x4230 0x0002 0x0000 0x0000 96: 0x0801 0x4230 0x0003 0x0000 0x0000 97: 0x0801 0x42B0 0x0002 0x0000 0x0000 98: 0x0801 0x42B0 0x0003 0x0000 0x0000 99: 0x0801 0x4270 0x0002 0x0000 0x0000 100: 0x0801 0x4270 0x0003 0x0000 0x0000 101: 0x0801 0x42F0 0x0002 0x0000 0x0000 102: 0x0801 0x42F0 0x0001 0x0000 0x0000 103: 0x0801 0x4210 0x0002 0x0000 0x0000 104: 0x0801 0x4210 0x0002 0x0000 0x0000 105: 0xF71E 0xBCEF 0x0001 0x0000 0x0000 106: 0x0F1E 0xBCEF 0x0001 0x0000 0x0000 107: 0x1F1E 0xBCEF 0x0001 0x0000 0x0000 108: 0x2F1E 0xBCEF 0x0001 0x0000 0x0000 109: 0x3F1E 0xBCEF 0x0001 0x0000 0x0000 110: 0x4F1E 0xBCEF 0x0001 0x0000 0x0000 111: 0x5F1E 0xBCEF 0x0001 0x0000 0x0000 112: 0x6F1E 0xBCEF 0x0001 0x0000 0x0000 113: 0x7F1E 0xBCEF 0x0001 0x0000 0x0000 114: 0x8F1E 0xBCEF 0x0001 0x0000 0x0000 115: 0x9F1E 0xBCEF 0x0001 0x0000 0x0000 116: 0xAF1E 0xBCEF 0x0001 0x0000 0x0000 117: 0xBF1E 0xBCEF 0x0001 0x0000 0x0000 118: 0xCF1E 0xBCEF 0x0001 0x0000 0x0000 119: 0xDF1E 0xBCEF 0x0001 0x0000 0x0000 120: 0xEF1E 0xBCEF 0x0001 0x0000 0x0000 121: 0xF71E 0xBCEF 0x0001 0x0000 0x0000 122: 0xF01E 0x7CEF 0x0001 0x0000 0x0000 123: 0xF01E 0xFCEF 0x0001 0x0000 0x0000 124: 0xF11E 0x7CEF 0x0001 0x0000 0x0000 125: 0xF11E 0xFCEF 0x0001 0x0000 0x0000 126: 0xF21E 0x7CEF 0x0001 0x0000 0x0000 127: 0xF21E 0xFCEF 0x0001 0x0000 0x0000 128: 0xF31E 0x7CEF 0x0001 0x0000 0x0000 129: 0xF31E 0xFCEF 0x0001 0x0000 0x0000 130: 0xF41E 0x7CEF 0x0001 0x0000 0x0000 131: 0xF41E 0xFCEF 0x0001 0x0000 0x0000 132: 0xF51E 0x7CEF 0x0001 0x0000 0x0000 133: 0xF51E 0xFCEF 0x0001 0x0000 0x0000 134: 0xF61E 0x7CEF 0x0001 0x0000 0x0000 135: 0xF61E 0xFCEF 0x0001 0x0000 0x0000 136: 0xF71E 0x7CEF 0x0001 0x0000 0x0000 137: 0xF71E 0xBCEF 0x0001 0x0000 0x0000 138: 0xF71E 0x82EF 0x0001 0x0000 0x0000 139: 0xF71E 0x86EF 0x0001 0x0000 0x0000 140: 0xF71E 0x8AEF 0x0001 0x0000 0x0000 141: 0xF71E 0x8EEF 0x0001 0x0000 0x0000 142: 0xF71E 0x92EF 0x0001 0x0000 0x0000 143: 0xF71E 0x96EF 0x0001 0x0000 0x0000 144: 0xF71E 0x9AEF 0x0001 0x0000 0x0000 145: 0xF71E 0x9EEF 0x0001 0x0000 0x0000 146: 0xF71E 0xA2EF 0x0001 0x0000 0x0000 147: 0xF71E 0xA6EF 0x0001 0x0000 0x0000 148: 0xF71E 0xAAEF 0x0001 0x0000 0x0000 149: 0xF71E 0xAEEF 0x0001 0x0000 0x0000 150: 0xF71E 0xB2EF 0x0001 0x0000 0x0000 151: 0xF71E 0xB6EF 0x0001 0x0000 0x0000 152: 0xF71E 0xBAEF 0x0001 0x0000 0x0000 153: 0xF71E 0xBCEF 0x0001 0x0000 0x0000 154: 0xF701 0xBCEF 0x0001 0x0000 0x0000 155: 0xF703 0xBCEF 0x0001 0x0000 0x0000 156: 0xF705 0xBCEF 0x0001 0x0000 0x0000 157: 0xF707 0xBCEF 0x0001 0x0000 0x0000 158: 0xF709 0xBCEF 0x0001 0x0000 0x0000 159: 0xF70B 0xBCEF 0x0001 0x0000 0x0000 160: 0xF70D 0xBCEF 0x0001 0x0000 0x0000 161: 0xF70F 0xBCEF 0x0001 0x0000 0x0000 162: 0xF711 0xBCEF 0x0001 0x0000 0x0000 163: 0xF713 0xBCEF 0x0001 0x0000 0x0000 164: 0xF715 0xBCEF 0x0001 0x0000 0x0000 165: 0xF717 0xBCEF 0x0001 0x0000 0x0000 166: 0xF719 0xBCEF 0x0001 0x0000 0x0000 167: 0xF71B 0xBCEF 0x0001 0x0000 0x0000 168: 0xF71D 0xBCEF 0x0001 0x0000 0x0000 169: 0xF71E 0xBCEF 0x0001 0x0000 0x0000 170: 0xF71E 0xBCF0 0x0001 0x0000 0x0000 171: 0xF71E 0xBCF8 0x0001 0x0000 0x0000 172: 0xF71E 0xBCF4 0x0001 0x0000 0x0000 173: 0xF71E 0xBCFC 0x0001 0x0000 0x0000 174: 0xF71E 0xBCF2 0x0001 0x0000 0x0000 175: 0xF71E 0xBCFA 0x0001 0x0000 0x0000 176: 0xF71E 0xBCF6 0x0001 0x0000 0x0000 177: 0xF71E 0xBCFE 0x0001 0x0000 0x0000 178: 0xF71E 0xBCF1 0x0001 0x0000 0x0000 179: 0xF71E 0xBCF9 0x0001 0x0000 0x0000 180: 0xF71E 0xBCF5 0x0001 0x0000 0x0000 181: 0xF71E 0xBCFD 0x0001 0x0000 0x0000 182: 0xF71E 0xBCF3 0x0001 0x0000 0x0000 183: 0xF71E 0xBCFB 0x0001 0x0000 0x0000 184: 0xF71E 0xBCF7 0x0001 0x0000 0x0000 185: 0xF71E 0xBCEF 0x0001 0x0000 0x0000 186: 0xF71E 0xBC0F 0x0002 0x0000 0x0000 187: 0xF71E 0xBC0F 0x0003 0x0000 0x0000 188: 0xF71E 0xBC8F 0x0002 0x0000 0x0000 189: 0xF71E 0xBC8F 0x0003 0x0000 0x0000 190: 0xF71E 0xBC4F 0x0002 0x0000 0x0000 191: 0xF71E 0xBC4F 0x0003 0x0000 0x0000 192: 0xF71E 0xBCCF 0x0002 0x0000 0x0000 193: 0xF71E 0xBCCF 0x0003 0x0000 0x0000 194: 0xF71E 0xBC2F 0x0002 0x0000 0x0000 195: 0xF71E 0xBC2F 0x0003 0x0000 0x0000 196: 0xF71E 0xBCAF 0x0002 0x0000 0x0000 197: 0xF71E 0xBCAF 0x0003 0x0000 0x0000 198: 0xF71E 0xBC6F 0x0002 0x0000 0x0000 199: 0xF71E 0xBC6F 0x0003 0x0000 0x0000 200: 0xF71E 0xBCEF 0x0002 0x0000 0x0000 201: 0xF71E 0xBCEF 0x0001 0x0000 0x0000 202: 0xF71E 0xBCEF 0x0001 0x0000 0x0000 PINs used (in edge connector order) (G=ground,P=power) SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBB LETTER ABCDEFHJKLMNPRSTUVABCDEFHJKLMNPRSTUVABCDEFHJKLMNPRSTUVABCDEFHJKLMNPRSTUV SIDE 111111111111111111222222222222222222111111111111111111222222222222222222 USAGE IIIIOIIIIOIIIIOG P GIIIIOIIIIOIIIIO G P G UUT has 24 inputs UUT has 6 outputs contains 30 pins/columns 36 pins are not used contains 202 'test steps' M117 REV 3 6 4-input NAND PINS Main menu Mon Aug 10 15:42:31 2015 test file is: tests\m117.tst delay is: 0 trigger is: 1 1 read test file 2 set test delay 3 set test trigger 4 run test 5 output loading test 8 diags 9 exit UUT power is okay Mon Aug 10 15:42:35 2015 space single step O run once (one test, all steps) F run, stop on fail G go (run tests N run, stop on fail, no print S scope (run, no print) C toggle comment printout + increase speed (less delay) - decrease speed (more delay)(slower) Q quit test scope (run, no print) ppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppp space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C toggle comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFHJKLMNPRSDEFHJKLMNPRSTUV SIDE 111111111111111222222222222222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO all fails was lo 000000000000000000000000000000 falling vvvvvvvvvvvvvvvvvvvvvvvvvvvvvv rising ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ was hi 111111111111111111111111111111 total fails 0, total passes 75 Main menu Mon Aug 10 15:42:45 2015 test file is: tests\m117.tst delay is: 0 trigger is: 1 1 read test file 2 set test delay 3 set test trigger 4 run test 5 output loading test 8 diags 9 exit Enter test file name? trying to open test file: tests\m217.tst could not open test file. valid test files are: reverting back to test file: tests\m117.tst Main menu Mon Aug 10 15:44:21 2015 test file is: tests\m117.tst delay is: 0 trigger is: 1 1 read test file 2 set test delay 3 set test trigger 4 run test 5 output loading test 8 diags 9 exit Enter test file name? trying to open test file: tests\m360.tst could not open test file. valid test files are: reverting back to test file: tests\m117.tst Main menu Mon Aug 10 15:48:55 2015 test file is: tests\m117.tst delay is: 0 trigger is: 1 1 read test file 2 set test delay 3 set test trigger 4 run test 5 output loading test 8 diags 9 exit key is 0x000D Main menu Mon Aug 10 16:08:35 2015 test file is: tests\m117.tst delay is: 0 trigger is: 1 1 read test file 2 set test delay 3 set test trigger 4 run test 5 output loading test 8 diags 9 exit Enter test file name? trying to open test file: tests\M360.NEW reading test file: tests\M360.NEW comment: M360 SCHEMATIC REV B, PCB REV B VARIABLE DELAY LINE comment: comment: USE SINGLE STEP AND DMM. comment: USE OSCILLOSCOPE TO SEE PULSES. comment: MANUALLY CHANGE DELAY POT USING OSCILLOSCOPE. comment: pins: PINS pins: 1 I AP2 INPUT 1 pins: 2 I AR2 INPUT 2 pins: 3 O AS2 PULSE OUTPUT ON (INPUT 1 AND INPUT 2) RISING EDGE pins: 4 P AT2 INVERTED PULSE OUTPUT (OPEN DRAIN) pins: 5 I AU2 INVERTER INPUT pins: 6 P AV2 INVERTER OUTPUT (OPEN DRAIN) pins: direction: IIOPIP comment: ; INITAL OFF test 1: 000101 comment: ; NO PULSES test 2: 01 test 3: 00 test 4: 10 comment: ; PULSE test 5: 11XX comment: ;AGAIN WITH INVERTER ON comment: ; INITAL OFF test 6: 000110 comment: ; NO PULSES test 7: 01 test 8: 00 test 9: 10 comment: ; PULSE test 10: 11XX comment: ; BACK TO INITAL CONDITIONS test 11: 000101 end: END summary column 1: offset 1, mask 0x0010 column 2: offset 1, mask 0x0020 column 3: offset 1, mask 0x0040 column 4: offset 1, mask 0x0080 column 5: offset 2, mask 0x0001 column 6: offset 2, mask 0x0002 direction bits (1=input) 0xFFFF 0xFFCF 0xFFFA 0xFFFF 0xF0FF pullup bits (1=pullup) 0x0000 0x0080 0x0002 0x0000 0x0000 test step out_data dont care 1: 0x0000 0x0080 0x0002 0x0000 0x0000 2: 0x0000 0x00A0 0x0002 0x0000 0x0000 3: 0x0000 0x0080 0x0002 0x0000 0x0000 4: 0x0000 0x0090 0x0002 0x0000 0x0000 5: 0x0000 0x0030 0x0002 0x0000 0x0000 0x0000 0x00C0 0x0000 0x0000 0x0000 6: 0x0000 0x0080 0x0001 0x0000 0x0000 7: 0x0000 0x00A0 0x0001 0x0000 0x0000 8: 0x0000 0x0080 0x0001 0x0000 0x0000 9: 0x0000 0x0090 0x0001 0x0000 0x0000 10: 0x0000 0x0030 0x0001 0x0000 0x0000 0x0000 0x00C0 0x0000 0x0000 0x0000 11: 0x0000 0x0080 0x0002 0x0000 0x0000 PINs used (in edge connector order) (G=ground,P=power) SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBB LETTER ABCDEFHJKLMNPRSTUVABCDEFHJKLMNPRSTUVABCDEFHJKLMNPRSTUVABCDEFHJKLMNPRSTUV SIDE 111111111111111111222222222222222222111111111111111111222222222222222222 USAGE G P G IIOPIP G P G UUT has 3 inputs UUT has 3 outputs contains 6 pins/columns 60 pins are not used contains 11 'test steps' M360 SCHEMATIC REV B, PCB REV B VARIABLE DELAY LINE USE SINGLE STEP AND DMM. USE OSCILLOSCOPE TO SEE PULSES. MANUALLY CHANGE DELAY POT USING OSCILLOSCOPE. PINS Main menu Mon Aug 10 16:08:40 2015 test file is: tests\M360.NEW delay is: 0 trigger is: 1 1 read test file 2 set test delay 3 set test trigger 4 run test 5 output loading test 8 diags 9 exit UUT power is okay Mon Aug 10 16:08:52 2015 space single step O run once (one test, all steps) F run, stop on fail G go (run tests N run, stop on fail, no print S scope (run, no print) C toggle comment printout + increase speed (less delay) - decrease speed (more delay)(slower) Q quit test scope (run, no print) ppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppp ppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppp ppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppp ppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppp ppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppp ppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppp ppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppp ppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppp ppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppp ppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppp ppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppp ppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppp ppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppp ppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppp ppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppp ppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppp ppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppp pppppppppppppppppppppppppppppppppppppppppppppppppppppppppppp space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C toggle comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAAAAA LETTER PRSTUV SIDE 222222 DIRECTION IIOPIP all fails was lo 000 00 falling vv vv rising ^^ ^^ was hi 11 111 total fails 0, total passes 1403 Main menu Mon Aug 10 16:09:11 2015 test file is: tests\M360.NEW delay is: 0 trigger is: 1 1 read test file 2 set test delay 3 set test trigger 4 run test 5 output loading test 8 diags 9 exit exiting tester- PDP8 card tester via printer port version 0.85 June 4, 2015 mapping[] is verified Main menu Mon Aug 10 16:09:34 2015 test file is: delay is: 0 trigger is: 1 1 read test file 2 set test delay 3 set test trigger 4 run test 5 output loading test 8 diags 9 exit Enter test file name? trying to open test file: tests\M360.NEW reading test file: tests\M360.NEW comment: M360 SCHEMATIC REV B, PCB REV B VARIABLE DELAY LINE comment: comment: USE SINGLE STEP AND DMM. comment: USE OSCILLOSCOPE TO SEE PULSES. comment: MANUALLY CHANGE DELAY POT USING OSCILLOSCOPE. comment: pins: PINS pins: 1 I AP2 INPUT 1 pins: 2 I AR2 INPUT 2 pins: 3 O AS2 PULSE OUTPUT ON (INPUT 1 AND INPUT 2) RISING EDGE pins: 4 P AT2 INVERTED PULSE OUTPUT (OPEN DRAIN) pins: 5 I AU2 INVERTER INPUT pins: 6 P AV2 INVERTER OUTPUT (OPEN DRAIN) pins: direction: IIOPIP comment: ; INITAL OFF test 1: 000101 comment: ; NO PULSES test 2: 01 test 3: 00 test 4: 10 comment: ; PULSE test 5: 11XX comment: ;AGAIN WITH INVERTER ON comment: ; INITAL OFF test 6: 000110 comment: ; NO PULSES test 7: 01 test 8: 00 test 9: 10 comment: ; PULSE test 10: 11XX comment: ; BACK TO INITAL CONDITIONS test 11: 000101 end: END summary column 1: offset 1, mask 0x0010 column 2: offset 1, mask 0x0020 column 3: offset 1, mask 0x0040 column 4: offset 1, mask 0x0080 column 5: offset 2, mask 0x0001 column 6: offset 2, mask 0x0002 direction bits (1=input) 0xFFFF 0xFFCF 0xFFFA 0xFFFF 0xF0FF pullup bits (1=pullup) 0x0000 0x0080 0x0002 0x0000 0x0000 test step out_data dont care 1: 0x0000 0x0080 0x0002 0x0000 0x0000 2: 0x0000 0x00A0 0x0002 0x0000 0x0000 3: 0x0000 0x0080 0x0002 0x0000 0x0000 4: 0x0000 0x0090 0x0002 0x0000 0x0000 5: 0x0000 0x0030 0x0002 0x0000 0x0000 0x0000 0x00C0 0x0000 0x0000 0x0000 6: 0x0000 0x0080 0x0001 0x0000 0x0000 7: 0x0000 0x00A0 0x0001 0x0000 0x0000 8: 0x0000 0x0080 0x0001 0x0000 0x0000 9: 0x0000 0x0090 0x0001 0x0000 0x0000 10: 0x0000 0x0030 0x0001 0x0000 0x0000 0x0000 0x00C0 0x0000 0x0000 0x0000 11: 0x0000 0x0080 0x0002 0x0000 0x0000 PINs used (in edge connector order) (G=ground,P=power) SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBB LETTER ABCDEFHJKLMNPRSTUVABCDEFHJKLMNPRSTUVABCDEFHJKLMNPRSTUVABCDEFHJKLMNPRSTUV SIDE 111111111111111111222222222222222222111111111111111111222222222222222222 USAGE G P G IIOPIP G P G UUT has 3 inputs UUT has 3 outputs contains 6 pins/columns 60 pins are not used contains 11 'test steps' M360 SCHEMATIC REV B, PCB REV B VARIABLE DELAY LINE USE SINGLE STEP AND DMM. USE OSCILLOSCOPE TO SEE PULSES. MANUALLY CHANGE DELAY POT USING OSCILLOSCOPE. PINS Main menu Mon Aug 10 16:09:41 2015 test file is: tests\M360.NEW delay is: 0 trigger is: 1 1 read test file 2 set test delay 3 set test trigger 4 run test 5 output loading test 8 diags 9 exit Enter test file name? trying to open test file: tests\M360.NEW reading test file: tests\M360.NEW comment: M360 SCHEMATIC REV B, PCB REV B VARIABLE DELAY LINE comment: comment: USE SINGLE STEP AND DMM. comment: USE OSCILLOSCOPE TO SEE PULSES. comment: MANUALLY CHANGE DELAY POT USING OSCILLOSCOPE. comment: pins: PINS pins: 1 I AP2 INPUT 1 pins: 2 I AR2 INPUT 2 pins: 3 O AS2 PULSE OUTPUT ON (INPUT 1 AND INPUT 2) RISING EDGE pins: 4 P AT2 INVERTED PULSE OUTPUT (OPEN DRAIN) pins: 5 I AU2 INVERTER INPUT pins: 6 P AV2 INVERTER OUTPUT (OPEN DRAIN) pins: direction: IIOPIP comment: ; INITAL OFF test 1: 000101 comment: ; NO PULSES test 2: 01 test 3: 00 test 4: 10 comment: ; PULSE (SO FAST, IT WLL BE OVER BEFORE TESTED) test 5: 1101 comment: ;AGAIN WITH INVERTER ON comment: ; INITAL OFF test 6: 000110 comment: ; NO PULSES test 7: 01 test 8: 00 test 9: 10 comment: ; PULSE (SO FAST, IT WLL BE OVER BEFORE TESTED) test 10: 1101 comment: ; BACK TO INITAL CONDITIONS test 11: 000101 end: END summary column 1: offset 1, mask 0x0010 column 2: offset 1, mask 0x0020 column 3: offset 1, mask 0x0040 column 4: offset 1, mask 0x0080 column 5: offset 2, mask 0x0001 column 6: offset 2, mask 0x0002 direction bits (1=input) 0xFFFF 0xFFCF 0xFFFA 0xFFFF 0xF0FF pullup bits (1=pullup) 0x0000 0x0080 0x0002 0x0000 0x0000 test step out_data dont care 1: 0x0000 0x0080 0x0002 0x0000 0x0000 2: 0x0000 0x00A0 0x0002 0x0000 0x0000 3: 0x0000 0x0080 0x0002 0x0000 0x0000 4: 0x0000 0x0090 0x0002 0x0000 0x0000 5: 0x0000 0x00B0 0x0002 0x0000 0x0000 6: 0x0000 0x0080 0x0001 0x0000 0x0000 7: 0x0000 0x00A0 0x0001 0x0000 0x0000 8: 0x0000 0x0080 0x0001 0x0000 0x0000 9: 0x0000 0x0090 0x0001 0x0000 0x0000 10: 0x0000 0x00B0 0x0001 0x0000 0x0000 11: 0x0000 0x0080 0x0002 0x0000 0x0000 PINs used (in edge connector order) (G=ground,P=power) SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBB LETTER ABCDEFHJKLMNPRSTUVABCDEFHJKLMNPRSTUVABCDEFHJKLMNPRSTUVABCDEFHJKLMNPRSTUV SIDE 111111111111111111222222222222222222111111111111111111222222222222222222 USAGE G P G IIOPIP G P G UUT has 3 inputs UUT has 3 outputs contains 6 pins/columns 60 pins are not used contains 11 'test steps' M360 SCHEMATIC REV B, PCB REV B VARIABLE DELAY LINE USE SINGLE STEP AND DMM. USE OSCILLOSCOPE TO SEE PULSES. MANUALLY CHANGE DELAY POT USING OSCILLOSCOPE. PINS Main menu Mon Aug 10 16:11:46 2015 test file is: tests\M360.NEW delay is: 0 trigger is: 1 1 read test file 2 set test delay 3 set test trigger 4 run test 5 output loading test 8 diags 9 exit ***************************** UUT power is OFF * ***************************** Main menu Mon Aug 10 16:12:05 2015 test file is: tests\M360.NEW delay is: 0 trigger is: 1 1 read test file 2 set test delay 3 set test trigger 4 run test 5 output loading test 8 diags 9 exit UUT power is okay Mon Aug 10 16:12:07 2015 space single step O run once (one test, all steps) F run, stop on fail G go (run tests N run, stop on fail, no print S scope (run, no print) C toggle comment printout + increase speed (less delay) - decrease speed (more delay)(slower) Q quit test scope (run, no print) ppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppp ppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppp ppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppp ppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppp ppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppp ppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppp ppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppp ppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppp ppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppp ppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppp ppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppp ppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppp ppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppp ppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppp ppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppp ppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppp ppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppp ppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppp ppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppp ppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppp ppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppp ppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppp ppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppp ppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppp ppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppp ppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppp ppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppp ppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppp ppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppp ppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppp ppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppp ppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppp ppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppp ppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppp ppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppp ppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppp ppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppp ppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppp ppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppp ppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppp ppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppp ppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppp ppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppp ppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppp ppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppp ppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppp ppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppp ppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppp ppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppp ppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppp ppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppp pppppppppppppppppppppppppppppppppppppppppppppppppppppppp space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C toggle comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit failure mode analysis: space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C toggle comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit up to this point: PINS that are always low 3 O AS2 PULSE OUTPUT ON (INPUT 1 AND INPUT 2) RISING EDGE PINS that are always high 4 P AT2 INVERTED PULSE OUTPUT (OPEN DRAIN) space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C toggle comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit scope (run, no print) ppppppppppppppppppppppp ppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppp ppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppp ppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppp ppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppp ppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppp ppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppp 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ppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppp ppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppp ppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppp ppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppp ppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppp ppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppp ppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppp ppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppp ppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppp ppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppp ppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppp ppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppp ppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppp ppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppp ppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppp ppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppp ppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppp ppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppp ppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppp pppppppppppppppppppppppppppppppppppppppppppppppppppppppppp space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C toggle comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C toggle comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAAAAA LETTER PRSTUV SIDE 222222 DIRECTION IIOPIP all fails was lo 000 00 falling vv vv rising ^^ ^^ was hi 11 111 total fails 0, total passes 47853 Main menu Mon Aug 10 16:17:27 2015 test file is: tests\M360.NEW delay is: 0 trigger is: 1 1 read test file 2 set test delay 3 set test trigger 4 run test 5 output loading test 8 diags 9 exit Enter test file name? trying to open test file: tests\M360.NEW reading test file: tests\M360.NEW comment: M360 SCHEMATIC REV B, PCB REV B VARIABLE DELAY LINE comment: comment: USE SINGLE STEP AND DMM. comment: USE OSCILLOSCOPE TO SEE PULSES. comment: MANUALLY CHANGE DELAY POT USING OSCILLOSCOPE. comment: pins: PINS pins: 1 I AP2 INPUT 1 pins: 2 I AR2 INPUT 2 pins: 3 O AS2 PULSE OUTPUT ON (INPUT 1 AND INPUT 2) RISING EDGE pins: 4 P AT2 INVERTED PULSE OUTPUT (OPEN DRAIN) pins: 5 I AU2 INVERTER INPUT pins: 6 P AV2 INVERTER OUTPUT (OPEN DRAIN) pins: direction: IIOPIP comment: ; INITAL OFF test 1: 000101 comment: ; NO PULSES test 2: 01 test 3: 00 test 4: 10 comment: ; PULSE (SO FAST, IT WLL BE OVER BEFORE TESTED) test 5: 1101 comment: ;AGAIN WITH INVERTER ON comment: ; INITAL OFF test 6: 000110 comment: ; NO PULSES test 7: 01 test 8: 00 test 9: 10 comment: ; PULSE (SO FAST, IT WLL BE OVER BEFORE TESTED) test 10: 1101 comment: ; BACK TO INITAL CONDITIONS test 11: 000101 end: END summary column 1: offset 1, mask 0x0010 column 2: offset 1, mask 0x0020 column 3: offset 1, mask 0x0040 column 4: offset 1, mask 0x0080 column 5: offset 2, mask 0x0001 column 6: offset 2, mask 0x0002 direction bits (1=input) 0xFFFF 0xFFCF 0xFFFA 0xFFFF 0xF0FF pullup bits (1=pullup) 0x0000 0x0080 0x0002 0x0000 0x0000 test step out_data dont care 1: 0x0000 0x0080 0x0002 0x0000 0x0000 2: 0x0000 0x00A0 0x0002 0x0000 0x0000 3: 0x0000 0x0080 0x0002 0x0000 0x0000 4: 0x0000 0x0090 0x0002 0x0000 0x0000 5: 0x0000 0x00B0 0x0002 0x0000 0x0000 6: 0x0000 0x0080 0x0001 0x0000 0x0000 7: 0x0000 0x00A0 0x0001 0x0000 0x0000 8: 0x0000 0x0080 0x0001 0x0000 0x0000 9: 0x0000 0x0090 0x0001 0x0000 0x0000 10: 0x0000 0x00B0 0x0001 0x0000 0x0000 11: 0x0000 0x0080 0x0002 0x0000 0x0000 PINs used (in edge connector order) (G=ground,P=power) SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBB LETTER ABCDEFHJKLMNPRSTUVABCDEFHJKLMNPRSTUVABCDEFHJKLMNPRSTUVABCDEFHJKLMNPRSTUV SIDE 111111111111111111222222222222222222111111111111111111222222222222222222 USAGE G P G IIOPIP G P G UUT has 3 inputs UUT has 3 outputs contains 6 pins/columns 60 pins are not used contains 11 'test steps' M360 SCHEMATIC REV B, PCB REV B VARIABLE DELAY LINE USE SINGLE STEP AND DMM. USE OSCILLOSCOPE TO SEE PULSES. MANUALLY CHANGE DELAY POT USING OSCILLOSCOPE. PINS Main menu Mon Aug 10 16:17:51 2015 test file is: tests\M360.NEW delay is: 0 trigger is: 1 1 read test file 2 set test delay 3 set test trigger 4 run test 5 output loading test 8 diags 9 exit exiting tester- PDP8 card tester via printer port version 0.85 June 4, 2015 mapping[] is verified Main menu Mon Aug 10 16:21:31 2015 test file is: delay is: 0 trigger is: 1 1 read test file 2 set test delay 3 set test trigger 4 run test 5 output loading test 8 diags 9 exit Enter test file name? trying to open test file: tests\M360.NEW reading test file: tests\M360.NEW comment: M360 SCHEMATIC REV B, PCB REV B VARIABLE DELAY LINE comment: comment: USE SINGLE STEP AND DMM. comment: USE OSCILLOSCOPE TO SEE PULSES. comment: TRIGGER ON STEP 5, OBSERVE AS2 POSITIVE PULSE, AT2 NEGATIVE PULSE comment: TRIGGER ON STEP 10, OBSERVE AS2 POSITIVE PULSE, AT2 NEGATIVE PULSE comment: MANUALLY CHANGE DELAY ADJUSTMENT, OBSERVE WITH OSCILLOSCOPE. comment: pins: PINS pins: 1 I AP2 INPUT 1 pins: 2 I AR2 INPUT 2 pins: 3 O AS2 PULSE OUTPUT ON (INPUT 1 AND INPUT 2) RISING EDGE pins: 4 P AT2 INVERTED PULSE OUTPUT (OPEN DRAIN) pins: 5 I AU2 INVERTER INPUT pins: 6 P AV2 INVERTER OUTPUT (OPEN DRAIN) pins: direction: IIOPIP comment: ; INITAL OFF test 1: 000101 comment: ; NO PULSES test 2: 01 test 3: 00 test 4: 10 comment: ; PULSE (SO FAST, IT WLL BE OVER BEFORE TESTED) test 5: 1101 comment: ;AGAIN WITH INVERTER ON comment: ; INITAL OFF test 6: 000110 comment: ; NO PULSES test 7: 01 test 8: 00 test 9: 10 comment: ; PULSE (SO FAST, IT WLL BE OVER BEFORE TESTED) test 10: 1101 comment: ; BACK TO INITAL CONDITIONS test 11: 000101 end: END summary column 1: offset 1, mask 0x0010 column 2: offset 1, mask 0x0020 column 3: offset 1, mask 0x0040 column 4: offset 1, mask 0x0080 column 5: offset 2, mask 0x0001 column 6: offset 2, mask 0x0002 direction bits (1=input) 0xFFFF 0xFFCF 0xFFFA 0xFFFF 0xF0FF pullup bits (1=pullup) 0x0000 0x0080 0x0002 0x0000 0x0000 test step out_data dont care 1: 0x0000 0x0080 0x0002 0x0000 0x0000 2: 0x0000 0x00A0 0x0002 0x0000 0x0000 3: 0x0000 0x0080 0x0002 0x0000 0x0000 4: 0x0000 0x0090 0x0002 0x0000 0x0000 5: 0x0000 0x00B0 0x0002 0x0000 0x0000 6: 0x0000 0x0080 0x0001 0x0000 0x0000 7: 0x0000 0x00A0 0x0001 0x0000 0x0000 8: 0x0000 0x0080 0x0001 0x0000 0x0000 9: 0x0000 0x0090 0x0001 0x0000 0x0000 10: 0x0000 0x00B0 0x0001 0x0000 0x0000 11: 0x0000 0x0080 0x0002 0x0000 0x0000 PINs used (in edge connector order) (G=ground,P=power) SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBB LETTER ABCDEFHJKLMNPRSTUVABCDEFHJKLMNPRSTUVABCDEFHJKLMNPRSTUVABCDEFHJKLMNPRSTUV SIDE 111111111111111111222222222222222222111111111111111111222222222222222222 USAGE G P G IIOPIP G P G UUT has 3 inputs UUT has 3 outputs contains 6 pins/columns 60 pins are not used contains 11 'test steps' M360 SCHEMATIC REV B, PCB REV B VARIABLE DELAY LINE USE SINGLE STEP AND DMM. USE OSCILLOSCOPE TO SEE PULSES. TRIGGER ON STEP 5, OBSERVE AS2 POSITIVE PULSE, AT2 NEGATIVE PULSE TRIGGER ON STEP 10, OBSERVE AS2 POSITIVE PULSE, AT2 NEGATIVE PULSE MANUALLY CHANGE DELAY ADJUSTMENT, OBSERVE WITH OSCILLOSCOPE. PINS Main menu Mon Aug 10 16:21:34 2015 test file is: tests\M360.NEW delay is: 0 trigger is: 1 1 read test file 2 set test delay 3 set test trigger 4 run test 5 output loading test 8 diags 9 exit Enter test trigger (1 to 11)? setting test delay to: 5 Main menu Mon Aug 10 16:21:50 2015 test file is: tests\M360.NEW delay is: 0 trigger is: 5 1 read test file 2 set test delay 3 set test trigger 4 run test 5 output loading test 8 diags 9 exit UUT power is okay Mon Aug 10 16:21:53 2015 space single step O run once (one test, all steps) F run, stop on fail G go (run tests N run, stop on fail, no print S scope (run, no print) C toggle comment printout + increase speed (less delay) - decrease speed (more delay)(slower) Q quit test scope (run, no print) ppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppp ppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppp ppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppp 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ppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppp ppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppp ppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppp ppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppp ppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppp ppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppp ppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppp ppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppp ppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppp ppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppp ppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppp ppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppp pppppppppppppppp space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C toggle comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAAAAA LETTER PRSTUV SIDE 222222 DIRECTION IIOPIP all fails was lo 000 00 falling vv vv rising ^^ ^^ was hi 11 111 total fails 0, total passes 10681 Main menu Mon Aug 10 16:23:00 2015 test file is: tests\M360.NEW delay is: 0 trigger is: 5 1 read test file 2 set test delay 3 set test trigger 4 run test 5 output loading test 8 diags 9 exit Enter test file name? trying to open test file: tests\M360.NEW reading test file: tests\M360.NEW comment: M360 SCHEMATIC REV B, PCB REV B VARIABLE DELAY LINE comment: comment: USE SINGLE STEP AND DMM. comment: USE OSCILLOSCOPE TO SEE PULSES. comment: TRIGGER ON STEP 5, OBSERVE AS2 POSITIVE PULSE, AT2 NEGATIVE PULSE comment: TRIGGER ON STEP 10, OBSERVE AS2 POSITIVE PULSE, AT2 NEGATIVE PULSE comment: MANUALLY CHANGE DELAY ADJUSTMENT, OBSERVE WITH OSCILLOSCOPE. comment: pins: PINS pins: 1 I AP2 INPUT 1 pins: 2 I AR2 INPUT 2 pins: 3 O AS2 PULSE OUTPUT ON (INPUT 1 AND INPUT 2) RISING EDGE pins: 4 P AT2 INVERTED PULSE OUTPUT (OPEN DRAIN) pins: 5 I AU2 INVERTER INPUT pins: 6 P AV2 INVERTER OUTPUT (OPEN DRAIN) pins: direction: IIOPIP comment: ; INITAL OFF test 1: 000101 comment: ; NO PULSES test 2: 01 test 3: 00 test 4: 10 comment: ; PULSE (SO FAST, IT WLL BE OVER BEFORE TESTED) test 5: 1101 comment: ;AGAIN WITH INVERTER ON comment: ; INITAL OFF test 6: 000110 comment: ; NO PULSES test 7: 01 test 8: 00 test 9: 10 comment: ; PULSE (SO FAST, IT WLL BE OVER BEFORE TESTED) test 10: 1101 comment: ; BACK TO INITAL CONDITIONS test 11: 000101 end: END summary column 1: offset 1, mask 0x0010 column 2: offset 1, mask 0x0020 column 3: offset 1, mask 0x0040 column 4: offset 1, mask 0x0080 column 5: offset 2, mask 0x0001 column 6: offset 2, mask 0x0002 direction bits (1=input) 0xFFFF 0xFFCF 0xFFFA 0xFFFF 0xF0FF pullup bits (1=pullup) 0x0000 0x0080 0x0002 0x0000 0x0000 test step out_data dont care 1: 0x0000 0x0080 0x0002 0x0000 0x0000 2: 0x0000 0x00A0 0x0002 0x0000 0x0000 3: 0x0000 0x0080 0x0002 0x0000 0x0000 4: 0x0000 0x0090 0x0002 0x0000 0x0000 5: 0x0000 0x00B0 0x0002 0x0000 0x0000 6: 0x0000 0x0080 0x0001 0x0000 0x0000 7: 0x0000 0x00A0 0x0001 0x0000 0x0000 8: 0x0000 0x0080 0x0001 0x0000 0x0000 9: 0x0000 0x0090 0x0001 0x0000 0x0000 10: 0x0000 0x00B0 0x0001 0x0000 0x0000 11: 0x0000 0x0080 0x0002 0x0000 0x0000 PINs used (in edge connector order) (G=ground,P=power) SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBB LETTER ABCDEFHJKLMNPRSTUVABCDEFHJKLMNPRSTUVABCDEFHJKLMNPRSTUVABCDEFHJKLMNPRSTUV SIDE 111111111111111111222222222222222222111111111111111111222222222222222222 USAGE G P G IIOPIP G P G UUT has 3 inputs UUT has 3 outputs contains 6 pins/columns 60 pins are not used contains 11 'test steps' M360 SCHEMATIC REV B, PCB REV B VARIABLE DELAY LINE USE SINGLE STEP AND DMM. USE OSCILLOSCOPE TO SEE PULSES. TRIGGER ON STEP 5, OBSERVE AS2 POSITIVE PULSE, AT2 NEGATIVE PULSE TRIGGER ON STEP 10, OBSERVE AS2 POSITIVE PULSE, AT2 NEGATIVE PULSE MANUALLY CHANGE DELAY ADJUSTMENT, OBSERVE WITH OSCILLOSCOPE. PINS Main menu Mon Aug 10 16:23:06 2015 test file is: tests\M360.NEW delay is: 0 trigger is: 5 1 read test file 2 set test delay 3 set test trigger 4 run test 5 output loading test 8 diags 9 exit UUT power is okay Mon Aug 10 16:24:07 2015 space single step O run once (one test, all steps) F run, stop on fail G go (run tests N run, stop on fail, no print S scope (run, no print) C toggle comment printout + increase speed (less delay) - decrease speed (more delay)(slower) Q quit test scope (run, no print) ppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppp ppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppp ppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppp ppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppp ppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppp ppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppp 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ppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppp ppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppp ppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppp ppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppp ppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppp ppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppp ppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppp ppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppp ppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppp ppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppp ppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppp ppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppp ppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppp ppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppp ppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppp ppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppp ppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppp ppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppp ppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppp ppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppp ppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppp ppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppp ppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppp ppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppp ppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppp ppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppp ppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppp ppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppp ppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppp ppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppp ppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppp ppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppp ppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppp ppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppp ppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppp ppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppp ppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppp ppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppp ppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppp ppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppp ppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppp ppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppp ppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppp ppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppp ppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppp ppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppp ppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppp ppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppp ppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppp ppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppp ppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppp ppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppp ppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppp ppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppp ppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppp ppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppp ppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppp ppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppp ppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppp ppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppp ppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppp ppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppp ppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppp ppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppp ppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppp ppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppp ppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppp ppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppp ppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppp ppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppp ppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppp ppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppp ppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppp ppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppp ppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppp ppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppp ppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppp ppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppp ppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppp ppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppp ppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppp ppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppp ppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppp ppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppp ppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppp ppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppp ppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppp ppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppp ppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppp ppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppp ppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppp ppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppp pppppppppppppppppppp space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C toggle comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit step 6 000110 step 7 010110 step 8 000110 step 9 100110 step 10 110110 step 11 000101 test 77915: pass SLOT AAAAAA LETTER PRSTUV SIDE 222222 DIRECTION IIOPIP this fail all fails I was hi 11 111 rising ^^ ^^ falling vv vv was lo 000 00 total fails 1, total passes 77914 space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C toggle comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit step 1 000101 step 2 010101 step 3 000101 step 4 100101 step 5 110101 step 6 000110 step 7 010110 step 8 000110 step 9 100110 step 10 110110 step 11 000101 test 77916: pass SLOT AAAAAA LETTER PRSTUV SIDE 222222 DIRECTION IIOPIP this fail all fails I was hi 11 111 rising ^^ ^^ falling vv vv was lo 000 00 total fails 1, total passes 77915 space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C toggle comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit step 1 000101 step 2 010101 step 3 000101 step 4 100101 step 5 110101 step 6 000110 step 7 010110 step 8 000110 step 9 100110 step 10 110110 step 11 000101 test 77917: pass SLOT AAAAAA LETTER PRSTUV SIDE 222222 DIRECTION IIOPIP this fail all fails I was hi 11 111 rising ^^ ^^ falling vv vv was lo 000 00 total fails 1, total passes 77916 space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C toggle comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit step 1 000101 step 2 010101 step 3 000101 step 4 100101 step 5 110101 step 6 000110 step 7 010110 step 8 000110 step 9 100110 step 10 110110 step 11 000101 test 77918: pass SLOT AAAAAA LETTER PRSTUV SIDE 222222 DIRECTION IIOPIP this fail all fails I was hi 11 111 rising ^^ ^^ falling vv vv was lo 000 00 total fails 1, total passes 77917 space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C toggle comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit step 1 000101 step 2 010101 step 3 000101 step 4 100101 step 5 110101 step 6 000110 step 7 010110 step 8 000110 step 9 100110 step 10 110110 step 11 000101 test 77919: pass SLOT AAAAAA LETTER PRSTUV SIDE 222222 DIRECTION IIOPIP this fail all fails I was hi 11 111 rising ^^ ^^ falling vv vv was lo 000 00 total fails 1, total passes 77918 space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C toggle comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit step 1 000101 step 2 010101 step 3 000101 step 4 100101 step 5 110101 step 6 000110 step 7 010110 step 8 000110 step 9 100110 step 10 110110 step 11 000101 test 77920: pass SLOT AAAAAA LETTER PRSTUV SIDE 222222 DIRECTION IIOPIP this fail all fails I was hi 11 111 rising ^^ ^^ falling vv vv was lo 000 00 total fails 1, total passes 77919 space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C toggle comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit step 1 000101 step 2 010101 step 3 000101 step 4 100101 step 5 110101 step 6 000110 step 7 010110 step 8 000110 step 9 100110 step 10 110110 step 11 000101 test 77921: pass SLOT AAAAAA LETTER PRSTUV SIDE 222222 DIRECTION IIOPIP this fail all fails I was hi 11 111 rising ^^ ^^ falling vv vv was lo 000 00 total fails 1, total passes 77920 space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C toggle comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit step 1 000101 step 2 010101 step 3 000101 step 4 100101 step 5 110101 step 6 000110 step 7 010110 step 8 000110 step 9 100110 step 10 110110 step 11 000101 test 77922: pass SLOT AAAAAA LETTER PRSTUV SIDE 222222 DIRECTION IIOPIP this fail all fails I was hi 11 111 rising ^^ ^^ falling vv vv was lo 000 00 total fails 1, total passes 77921 space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C toggle comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit step 1 000101 step 2 010101 step 3 000101 step 4 100101 step 5 110101 step 6 000110 step 7 010110 step 8 000110 step 9 100110 step 10 110110 step 11 000101 test 77923: pass SLOT AAAAAA LETTER PRSTUV SIDE 222222 DIRECTION IIOPIP this fail all fails I was hi 11 111 rising ^^ ^^ falling vv vv was lo 000 00 total fails 1, total passes 77922 space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C toggle comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit comment_flag is 1 space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C toggle comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit source: ; INITAL OFF source: 000101 changed: step 1 000101 source: ; NO PULSES source: 01 changed: 1 step 2 010101 source: 00 changed: 0 step 3 000101 source: 10 changed: 1 step 4 100101 source: ; PULSE (SO FAST, IT WLL BE OVER BEFORE TESTED) source: 1101 changed: 1 step 5 110101 source: ;AGAIN WITH INVERTER ON source: ; INITAL OFF source: 000110 changed: 00 10 step 6 000110 source: ; NO PULSES source: 01 changed: 1 step 7 010110 source: 00 changed: 0 step 8 000110 source: 10 changed: 1 step 9 100110 source: ; PULSE (SO FAST, IT WLL BE OVER BEFORE TESTED) source: 1101 changed: 1 step 10 110110 source: ; BACK TO INITAL CONDITIONS source: 000101 changed: 00 01 step 11 000101 test 77924: pass SLOT AAAAAA LETTER PRSTUV SIDE 222222 DIRECTION IIOPIP this fail all fails I was hi 11 111 rising ^^ ^^ falling vv vv was lo 000 00 total fails 1, total passes 77923 space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C toggle comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit 1 I AP2 INPUT 1 2 I AR2 INPUT 2 5 I AU2 INVERTER INPUT 6 P AV2 INVERTER OUTPUT (OPEN DRAIN) space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C toggle comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAAAAA LETTER PRSTUV SIDE 222222 DIRECTION IIOPIP source: ; INITAL OFF source: 000101 changed: step 1 000101 okay space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C toggle comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAAAAA LETTER PRSTUV SIDE 222222 DIRECTION IIOPIP source: ; NO PULSES source: 01 changed: 1 step 2 010101 okay space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C toggle comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAAAAA LETTER PRSTUV SIDE 222222 DIRECTION IIOPIP source: 00 changed: 0 step 3 000101 okay space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C toggle comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAAAAA LETTER PRSTUV SIDE 222222 DIRECTION IIOPIP source: 10 changed: 1 step 4 100101 okay space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C toggle comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAAAAA LETTER PRSTUV SIDE 222222 DIRECTION IIOPIP source: ; PULSE (SO FAST, IT WLL BE OVER BEFORE TESTED) source: 1101 changed: 1 step 5 110101 okay space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C toggle comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit scope (run, no print) ppppppppppppppppppppppppppppppppppppppppppppppppppppppppppp ppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppp ppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppp 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ppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppp ppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppp ppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppp ppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppp ppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppp ppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppp ppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppp ppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppp ppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppp ppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppp ppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppp ppppppppppppppppppppppppppppppppppppppppppppppppppppppppppp space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C toggle comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAAAAA LETTER PRSTUV SIDE 222222 DIRECTION IIOPIP all fails I was lo 000 00 falling vv vv rising ^^ ^^ was hi 11 111 total fails 1, total passes 104664 Main menu Mon Aug 10 16:38:34 2015 test file is: tests\M360.NEW delay is: 0 trigger is: 5 1 read test file 2 set test delay 3 set test trigger 4 run test 5 output loading test 8 diags 9 exit Enter test file name? trying to open test file: tests\M360.NEW reading test file: tests\M360.NEW comment: M360 SCHEMATIC REV B, PCB REV B VARIABLE DELAY LINE comment: comment: USE SINGLE STEP AND DMM. comment: USE OSCILLOSCOPE TO SEE PULSES. comment: TRIGGER ON STEP 5, OBSERVE AS2 POSITIVE PULSE, AT2 NEGATIVE PULSE comment: TRIGGER ON STEP 10, OBSERVE AS2 POSITIVE PULSE, AT2 NEGATIVE PULSE comment: MANUALLY CHANGE DELAY ADJUSTMENT, OBSERVE WITH OSCILLOSCOPE. comment: pins: PINS pins: 1 I AP2 INPUT 1 pins: 2 I AR2 INPUT 2 pins: 3 O AS2 POSITIVE 100 NS PULSE OUTPUT WHEN (INPUT 1 AND INPUT 2) RISING EDGE pins: 4 P AT2 NEGATIVE OF AS2, NEGATIVE 5 US PULSE OUTPUT (FAST DOWN, RC UP) (OPEN DRAIN) pins: 5 I AU2 INVERTER INPUT pins: 6 P AV2 INVERTER OUTPUT (OPEN DRAIN) pins: direction: IIOPIP comment: ; INITAL OFF test 1: 000101 comment: ; NO PULSES test 2: 01 test 3: 00 test 4: 10 comment: ; PULSE (SO FAST, IT WLL BE OVER BEFORE TESTED) test 5: 1101 comment: ;AGAIN WITH INVERTER ON comment: ; INITAL OFF test 6: 000110 comment: ; NO PULSES test 7: 01 test 8: 00 test 9: 10 comment: ; PULSE (SO FAST, IT WLL BE OVER BEFORE TESTED) test 10: 1101 comment: ; BACK TO INITAL CONDITIONS test 11: 000101 end: END summary column 1: offset 1, mask 0x0010 column 2: offset 1, mask 0x0020 column 3: offset 1, mask 0x0040 column 4: offset 1, mask 0x0080 column 5: offset 2, mask 0x0001 column 6: offset 2, mask 0x0002 direction bits (1=input) 0xFFFF 0xFFCF 0xFFFA 0xFFFF 0xF0FF pullup bits (1=pullup) 0x0000 0x0080 0x0002 0x0000 0x0000 test step out_data dont care 1: 0x0000 0x0080 0x0002 0x0000 0x0000 2: 0x0000 0x00A0 0x0002 0x0000 0x0000 3: 0x0000 0x0080 0x0002 0x0000 0x0000 4: 0x0000 0x0090 0x0002 0x0000 0x0000 5: 0x0000 0x00B0 0x0002 0x0000 0x0000 6: 0x0000 0x0080 0x0001 0x0000 0x0000 7: 0x0000 0x00A0 0x0001 0x0000 0x0000 8: 0x0000 0x0080 0x0001 0x0000 0x0000 9: 0x0000 0x0090 0x0001 0x0000 0x0000 10: 0x0000 0x00B0 0x0001 0x0000 0x0000 11: 0x0000 0x0080 0x0002 0x0000 0x0000 PINs used (in edge connector order) (G=ground,P=power) SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBB LETTER ABCDEFHJKLMNPRSTUVABCDEFHJKLMNPRSTUVABCDEFHJKLMNPRSTUVABCDEFHJKLMNPRSTUV SIDE 111111111111111111222222222222222222111111111111111111222222222222222222 USAGE G P G IIOPIP G P G UUT has 3 inputs UUT has 3 outputs contains 6 pins/columns 60 pins are not used contains 11 'test steps' M360 SCHEMATIC REV B, PCB REV B VARIABLE DELAY LINE USE SINGLE STEP AND DMM. USE OSCILLOSCOPE TO SEE PULSES. TRIGGER ON STEP 5, OBSERVE AS2 POSITIVE PULSE, AT2 NEGATIVE PULSE TRIGGER ON STEP 10, OBSERVE AS2 POSITIVE PULSE, AT2 NEGATIVE PULSE MANUALLY CHANGE DELAY ADJUSTMENT, OBSERVE WITH OSCILLOSCOPE. PINS Main menu Mon Aug 10 16:38:50 2015 test file is: tests\M360.NEW delay is: 0 trigger is: 5 1 read test file 2 set test delay 3 set test trigger 4 run test 5 output loading test 8 diags 9 exit Enter test trigger (1 to 11)? setting test delay to: 5 Main menu Mon Aug 10 16:38:55 2015 test file is: tests\M360.NEW delay is: 0 trigger is: 5 1 read test file 2 set test delay 3 set test trigger 4 run test 5 output loading test 8 diags 9 exit UUT power is okay Mon Aug 10 16:38:57 2015 space single step O run once (one test, all steps) F run, stop on fail G go (run tests N run, stop on fail, no print S scope (run, no print) C toggle comment printout + increase speed (less delay) - decrease speed (more delay)(slower) Q quit test scope (run, no print) ppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppp ppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppp ppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppp 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ppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppp ppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppp ppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppp ppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppp ppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppp ppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppp ppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppp ppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppp ppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppp ppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppp ppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppp ppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppp ppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppp ppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppp space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C toggle comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAAAAA LETTER PRSTUV SIDE 222222 DIRECTION IIOPIP all fails was lo 000 00 falling vv vv rising ^^ ^^ was hi 11 111 total fails 0, total passes 36411 Main menu Mon Aug 10 16:42:39 2015 test file is: tests\M360.NEW delay is: 0 trigger is: 5 1 read test file 2 set test delay 3 set test trigger 4 run test 5 output loading test 8 diags 9 exit Enter test trigger (1 to 11)? setting test delay to: 10 Main menu Mon Aug 10 16:42:44 2015 test file is: tests\M360.NEW delay is: 0 trigger is: 10 1 read test file 2 set test delay 3 set test trigger 4 run test 5 output loading test 8 diags 9 exit UUT power is okay Mon Aug 10 16:42:46 2015 space single step O run once (one test, all steps) F run, stop on fail G go (run tests N run, stop on fail, no print S scope (run, no print) C toggle comment printout + increase speed (less delay) - decrease speed (more delay)(slower) Q quit test scope (run, no print) ppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppp ppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppp ppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppp ppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppp ppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppp ppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppp ppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppp ppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppp ppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppp pppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppp space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C toggle comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAAAAA LETTER PRSTUV SIDE 222222 DIRECTION IIOPIP all fails was lo 000 00 falling vv vv rising ^^ ^^ was hi 11 111 total fails 0, total passes 789 Main menu Mon Aug 10 16:42:53 2015 test file is: tests\M360.NEW delay is: 0 trigger is: 10 1 read test file 2 set test delay 3 set test trigger 4 run test 5 output loading test 8 diags 9 exit Enter test file name? trying to open test file: tests\M360.TST reading test file: tests\M360.TST comment: M360 SCHEMATIC REV B, PCB REV B VARIABLE DELAY LINE comment: comment: USE SINGLE STEP AND DMM. comment: USE OSCILLOSCOPE TO SEE PULSES. comment: TRIGGER ON STEP 5, OBSERVE AS2 POSITIVE PULSE, AT2 NEGATIVE PULSE comment: TRIGGER ON STEP 10, OBSERVE AS2 POSITIVE PULSE, AT2 NEGATIVE PULSE comment: MANUALLY CHANGE DELAY ADJUSTMENT, OBSERVE WITH OSCILLOSCOPE. comment: pins: PINS pins: 1 I AP2 INPUT 1 pins: 2 I AR2 INPUT 2 pins: 3 O AS2 POSITIVE 100 NS PULSE OUTPUT WHEN (INPUT 1 AND INPUT 2) RISING EDGE pins: 4 P AT2 NEGATIVE OF AS2, NEGATIVE 5 US PULSE OUTPUT (FAST DOWN, RC UP) (OPEN DRAIN) pins: 5 I AU2 INVERTER INPUT pins: 6 P AV2 INVERTER OUTPUT (OPEN DRAIN) pins: direction: IIOPIP comment: ; INITAL OFF test 1: 000101 comment: ; NO PULSES test 2: 01 test 3: 00 test 4: 10 comment: ; PULSE (SO FAST, IT WLL BE OVER BEFORE TESTED) test 5: 1101 comment: ;AGAIN WITH INVERTER ON comment: ; INITAL OFF test 6: 000110 comment: ; NO PULSES test 7: 01 test 8: 00 test 9: 10 comment: ; PULSE (SO FAST, IT WLL BE OVER BEFORE TESTED) test 10: 1101 comment: ; BACK TO INITAL CONDITIONS test 11: 000101 end: END summary column 1: offset 1, mask 0x0010 column 2: offset 1, mask 0x0020 column 3: offset 1, mask 0x0040 column 4: offset 1, mask 0x0080 column 5: offset 2, mask 0x0001 column 6: offset 2, mask 0x0002 direction bits (1=input) 0xFFFF 0xFFCF 0xFFFA 0xFFFF 0xF0FF pullup bits (1=pullup) 0x0000 0x0080 0x0002 0x0000 0x0000 test step out_data dont care 1: 0x0000 0x0080 0x0002 0x0000 0x0000 2: 0x0000 0x00A0 0x0002 0x0000 0x0000 3: 0x0000 0x0080 0x0002 0x0000 0x0000 4: 0x0000 0x0090 0x0002 0x0000 0x0000 5: 0x0000 0x00B0 0x0002 0x0000 0x0000 6: 0x0000 0x0080 0x0001 0x0000 0x0000 7: 0x0000 0x00A0 0x0001 0x0000 0x0000 8: 0x0000 0x0080 0x0001 0x0000 0x0000 9: 0x0000 0x0090 0x0001 0x0000 0x0000 10: 0x0000 0x00B0 0x0001 0x0000 0x0000 11: 0x0000 0x0080 0x0002 0x0000 0x0000 PINs used (in edge connector order) (G=ground,P=power) SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBB LETTER ABCDEFHJKLMNPRSTUVABCDEFHJKLMNPRSTUVABCDEFHJKLMNPRSTUVABCDEFHJKLMNPRSTUV SIDE 111111111111111111222222222222222222111111111111111111222222222222222222 USAGE G P G IIOPIP G P G UUT has 3 inputs UUT has 3 outputs contains 6 pins/columns 60 pins are not used contains 11 'test steps' M360 SCHEMATIC REV B, PCB REV B VARIABLE DELAY LINE USE SINGLE STEP AND DMM. USE OSCILLOSCOPE TO SEE PULSES. TRIGGER ON STEP 5, OBSERVE AS2 POSITIVE PULSE, AT2 NEGATIVE PULSE TRIGGER ON STEP 10, OBSERVE AS2 POSITIVE PULSE, AT2 NEGATIVE PULSE MANUALLY CHANGE DELAY ADJUSTMENT, OBSERVE WITH OSCILLOSCOPE. PINS Main menu Mon Aug 10 16:43:19 2015 test file is: tests\M360.TST delay is: 0 trigger is: 10 1 read test file 2 set test delay 3 set test trigger 4 run test 5 output loading test 8 diags 9 exit UUT power is okay Mon Aug 10 16:43:21 2015 space single step O run once (one test, all steps) F run, stop on fail G go (run tests N run, stop on fail, no print S scope (run, no print) C toggle comment printout + increase speed (less delay) - decrease speed (more delay)(slower) Q quit test scope (run, no print) ppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppp ppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppp ppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppp ppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppp ppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppp ppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppp ppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppp ppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppp ppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppp ppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppp ppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppp ppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppp ppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppp ppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppp ppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppp ppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppp ppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppp ppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppp ppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppp pppppppppppppppppppppppppppppppp space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C toggle comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAAAAA LETTER PRSTUV SIDE 222222 DIRECTION IIOPIP all fails was lo 000 00 falling vv vv rising ^^ ^^ was hi 11 111 total fails 0, total passes 1533 Main menu Mon Aug 10 16:43:35 2015 test file is: tests\M360.TST delay is: 0 trigger is: 10 1 read test file 2 set test delay 3 set test trigger 4 run test 5 output loading test 8 diags 9 exit UUT power is okay Mon Aug 10 16:46:25 2015 space single step O run once (one test, all steps) F run, stop on fail G go (run tests N run, stop on fail, no print S scope (run, no print) C toggle comment printout + increase speed (less delay) - decrease speed (more delay)(slower) Q quit test scope (run, no print) ppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppp ppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppp ppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppp ppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppp ppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppp ppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppp ppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppp ppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppp ppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppp ppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppp 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ppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppp ppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppp ppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppp ppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppp ppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppp ppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppp ppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppp ppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppp ppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppp ppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppp ppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppp ppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppp ppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppp ppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppp ppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppp ppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppp ppppppppppppppppppppppppppppp space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C toggle comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAAAAA LETTER PRSTUV SIDE 222222 DIRECTION IIOPIP all fails OP P was lo 000000 falling vvvvvv rising ^^^^^^ was hi 111111 total fails 4796, total passes 36155 Main menu Mon Aug 10 16:50:34 2015 test file is: tests\M360.TST delay is: 0 trigger is: 10 1 read test file 2 set test delay 3 set test trigger 4 run test 5 output loading test 8 diags 9 exit exiting tester- PDP8 card tester via printer port version 0.85 June 4, 2015 mapping[] is verified Main menu Mon Aug 10 16:51:55 2015 test file is: delay is: 0 trigger is: 1 1 read test file 2 set test delay 3 set test trigger 4 run test 5 output loading test 8 diags 9 exit key is 0x0030 Main menu Mon Aug 10 16:51:58 2015 test file is: delay is: 0 trigger is: 1 1 read test file 2 set test delay 3 set test trigger 4 run test 5 output loading test 8 diags 9 exit exiting tester- PDP8 card tester via printer port version 0.85 June 4, 2015 mapping[] is verified Main menu Mon Aug 10 17:00:18 2015 test file is: delay is: 0 trigger is: 1 1 read test file 2 set test delay 3 set test trigger 4 run test 5 output loading test 8 diags 9 exit Enter test file name? trying to open test file: tests\x could not open test file. valid test files are: reverting back to test file: Main menu Mon Aug 10 17:00:21 2015 test file is: delay is: 0 trigger is: 1 1 read test file 2 set test delay 3 set test trigger 4 run test 5 output loading test 8 diags 9 exit key is 0x0020 Main menu Mon Aug 10 17:00:35 2015 test file is: delay is: 0 trigger is: 1 1 read test file 2 set test delay 3 set test trigger 4 run test 5 output loading test 8 diags 9 exit exiting tester- PDP8 card tester via printer port version 0.85 June 4, 2015 mapping[] is verified Main menu Thu Aug 20 15:31:34 2015 test file is: delay is: 0 trigger is: 1 1 read test file 2 set test delay 3 set test trigger 4 run test 5 output loading test 8 diags 9 exit key is 0x006D Main menu Thu Aug 20 15:31:35 2015 test file is: delay is: 0 trigger is: 1 1 read test file 2 set test delay 3 set test trigger 4 run test tester- PDP8 card tester via printer port version 0.85 June 4, 2015 mapping[] is verified Main menu Thu Aug 20 15:31:51 2015 test file is: delay is: 0 trigger is: 1 1 read test file 2 set test delay 3 set test trigger 4 run test 5 output loading test 8 diags 9 exit Enter test file name? trying to open test file: tests\m222.tst reading test file: tests\m222.tst comment: M222 PCB REV B SCHEMATIC REV A LINC TAPE REGISTERS comment: comment: TERMINOLOGY- SIGNALS REFER TO VOL4 M222 SCHEMATIC. comment: comment: BUT... comment: comment: DEC USES AND-NOR GATES TO ROUTE THE ADDER A AND B INPUTS, SO... comment: DEC RENAMED THE ADDER TO NEGATIVE LOGIC TERMS (I.E. A-N + B-N + C-N -> SUM-N, C1-N). comment: (NOT THE 7482 DATASHEET NAMES OF A + B + C -> SUM, C1). comment: comment: SO, WITH ALL 'AND ENABLES' LOW, THE AND-NOR OUTPUTS = HIGH. comment: WITH C-L HIGH, THE ADDER OUTPUT IS SUM-N=1, C1-N=1; comment: THE INVERTED ADDER OUTPUT IS LOW (TAPE BUS). comment: AND THERE IS NO CARRY (C1-N IS HI). comment: comment: THE TWO ADDERS, TWO REGISTER BITS, ETC ARE LABELED BIT 2 (EVEN, MSB) AND BIT 3 (ODD, LSB). comment: THE ADDERS ARE REFERRED TO AS 'ADDER2' (MSB) AND 'ADDER3' (LSB). comment: comment: POWER PINS: comment: AA2 +5V comment: AT1 GROUND comment: AC2 GROUND comment: BA2 +5V comment: BT1 GROUND comment: BC2 GROUND comment: comment: (ALL PINS ARE USED). comment: comment: pins: PINS pins: 1 I BA1 CARRY IN-N, (TO E9-5 7482 C0) C-N TO ADDER2 pins: 2 I AL2 AND-NOR ENABLE: TAC TAC3 TO PIN BB2 (TO ADDER3) TAC2 TO PIN AN2 (TO ADDER2) pins: 3 I AP1 AND-NOR ENABLE: TMA SETUP (TMAS)3 TO PIN BB2 (TO ADDER3), (TMAS)3 TO PIN AN2 (TO ADDER2) pins: 4 I AS2 AND-NOR ENABLE: TMA TMA3 TO PIN BB2 (TO ADDER3), TMA2 TO PIN AN2 (TO ADDER2) pins: 5 I AL1 AND-NOR ENABLE: PIN AF2 TO PIN BB2 (TO ADDER3), PIN AM1 TO PIN AN2 (TO ADDER2) pins: 6 I AF2 AND-NOR INPUT (AL1 ENABLES) TO PIN BB2 (TO ADDER3). pins: 7 I AM1 AND-NOR INPUT (AL1 ENABLES) TO PIN AN2 (TO ADDER2) pins: 8 I AD2 AND-NOR ENABLE: RWB RWB3 TO PIN BB2 (TO ADDER3), RWB2 TO PIN AN2 (TO ADDER2) pins: 9 I AE2 AND-NOR ENABLE: PIN AE1 TO PIN BB2 (TO ADDER3), PIN AM2 TO PIN AN2 (TO ADDER2) pins: 10 I AE1 AND-NOR INPUT (AE2 ENABLES) TO PIN BB2 (TO ADDER3). pins: 11 I AM2 AND-NOR INPUT (AE2 ENABLES) TO PIN AN2 (TO ADDER2) pins: 12 I AC1 AND-NOR INPUT, AND WITH PIN AB2 TO PIN BB2 (TO ADDER3) pins: 13 I AB2 AND-NOR INPUT, AND WITH PIN AC1 TO PIN BB2 (TO ADDER3) pins: 14 I AF1 AND-NOR INPUT (AND WITH ITSELF) TO PIN BB2 (TO ADDER3) pins: 15 I AR2 AND-NOR INPUT, AND WITH PIN AS1 TO PIN AN2 (TO ADDER2) pins: 16 I AS1 AND-NOR INPUT, AND WITH PIN AR2 TO PIN AN2 (TO ADDER2) pins: 17 I AP2 AND-NOR INPUT (AND WITH ITSELF) TO PIN AN2 (TO ADDER2) pins: 18 I BK1 AND-NOR ENABLE: TB3 TO PIN BB1 (TO ADDER3), TB2 TO PIN BN1 (TO ADDER2) pins: 19 I BL1 AND-NOR ENABLE: PIN BE1 TO PIN BB1 (TO ADDER3), PIN BM1 TO PIN BN1 (TO ADDER2) pins: 20 I BE1 AND-NOR INPUT (BL1 ENABLES) TO PIN BB1 (TO ADDER3). pins: 21 I BM1 AND-NOR INPUT (BL1 ENABLES) TO PIN BN1 (TO ADDER2) pins: 22 I BF1 AND-NOR ENABLE: PIN BH1 TO PIN BB1 (TO ADDER3), PIN BR1 TO PIN BN1 (TO ADDER2) pins: 23 I BH1 AND-NOR INPUT (BF1 ENABLES): TO PIN BB1 (TO ADDER3), pins: 24 I BR1 AND-NOR INPUT (BF1 ENABLES): TO PIN BN1 (TO ADDER2) pins: 25 I BS1 AND-NOR ENABLE: PIN BC1 TO PIN BB1 (TO ADDER3), PIN BJ2 TO PIN BN1 (TO ADDER2) pins: 26 I BC1 AND-NOR INPUT (BS1 ENABLES): TO PIN BB1 (TO ADDER3), pins: 27 I BJ2 AND-NOR INPUT (BS1 ENABLES): TO PIN BN1 (TO ADDER2) pins: 28 I BL2 AND-NOR ENABLE: PIN BJ1 TO PIN BB1 (TO ADDER3), PIN BK2 TO PIN BN1 (TO ADDER2) pins: 29 I BJ1 AND-NOR INPUT (BL2 ENABLES): TO PIN BB1 (TO ADDER3), pins: 30 I BK2 AND-NOR INPUT (BL2 ENABLES): TO PIN BN1 (TO ADDER2) pins: 31 I BU1 AND-NOR ENABLE: PIN BH2 TO PIN BB1 (TO ADDER3), PIN BP2 TO PIN BN1 (TO ADDER2) pins: 32 I BH2 AND-NOR INPUT (BU1 ENABLES): TO PIN BB1 (TO ADDER3), pins: 33 I BP2 AND-NOR INPUT (BU1 ENABLES): TO PIN BN1 (TO ADDER2) pins: 34 I BN2 AND-NOR INPUT (AND WITH BM2): TO PIN BN1 (TO ADDER2) pins: 35 I BM2 AND-NOR INPUT (AND WITH BM2): TO PIN BN1 (TO ADDER2) pins: 36 O BB2 AND-NOR OUTPUT, (DRIVES E9-2 7482 A1) TO ADDER3 INPUT pins: 37 O BB1 AND-NOR OUTPUT, (DRIVES E9-3 7482 B1) TO ADDER3 INPUT pins: 38 O BN1 AND-NOR OUTPUT, (DRIVES E9-14 7482 A2) TO ADDER2 INPUT pins: 39 O AN2 AND-NOR OUTPUT, (DRIVES E9-13 7482 B2) TO ADDER2 INPUT pins: 40 O AV2 CARRY OUT-N (E9-10 7482 C2) pins: 41 O BV2 TAPE BUS 2 OUTPUT (INVERTED ADDER2 SUM-N (E9-12 7482 SUM2) pins: 42 O BR2 TAPE BUS 3 OUTPUT (INVERTED ADDER3 SUM-N (E9-1 7482 SUM1) pins: 43 I AK1 LOAD TMA SETUP (FROM TAPE BUS) (RISING EDGE CLOCK) pins: 44 O AR1 TMA SETUP 2 pins: 45 O AH1 TMA SETUP 3 pins: 46 I AU2 LOAD TMA (FROM TAPE BUS) (RISING EDGE CLOCK) pins: 47 O AT2 TMA 2 pins: 48 O AD1 TMA 3 pins: 49 I AJ1 LOAD TBN (FROM TAPE BUS) (RISING EDGE CLOCK) pins: 50 O AU1 TBN 2 pins: 51 O AK2 TBN 3 pins: 52 I AA1 LOAD TAC (FROM TAPE BUS) (RISING EDGE CLOCK) pins: 53 O AN1 TAC 2 pins: 54 O AJ2 TAC 2-N pins: 55 O AH2 TAC 3 pins: 56 O AB1 TAC 3-N pins: 57 I BT2 LOAD TB (FROM TAPE BUS) (RISING EDGE CLOCK) pins: 58 O BP1 TB 2 pins: 59 O BD1 TB 3 pins: 60 I BF2 LOAD RWB (FROM TB) (JAMS CLEAR,SET) pins: 61 I BS2 PHASE (SELECTS POLARITY OF RWB OUT, 0 -> INVERTED) pins: 62 O BV1 RWB OUT (=RWB 2 IF PHASE=1; =RWB 2-N IF PHASE=0) pins: 63 O BD2 RWB 3 pins: 64 I BE2 SHIFT RWB (SHIFTS PIN AV1 INTO RWB 3, SHIFTS RWB3 TO RWB2) (RISING CLOCK) pins: 65 I AV1 RWB IN (SHIFTED INTO RWB 2) pins: 66 O BU2 +3.5V pins: direction: IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIOOOOOOOIOOIOOIOOIOOOOIOOIIOOIIO comment: ; all registers are unknown comment: ; turn on C0, PHASE comment: ; with no ENABLES, BUS2,BUS3 is 11, C2 is 1 test 1: 1000000000000000000000000000000000011111000XX0XX0XX0XXXX0XX01XX001 comment: comment: ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; comment: ; comment: ; set all registers LOW comment: ; comment: ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; comment: comment: ; load TMA SETUP from tape bus (00) test 2: 100 test 3: 0 comment: ; load TMA from tape bus (00) test 4: 100 test 5: 0 comment: ; load TBN from tape bus (00) test 6: 100 test 7: 0 comment: ; load TAC from tape bus (00) test 8: 10101 test 9: 0 comment: ; load TB from tape bus (00) test 10: 100 test 11: 0 comment: ; load RWB from TB (JAMS CLEAR AND PRESET) test 12: 1 00 test 13: 0 comment: ; (no change) test 14: 100000000000000000000000000000000001111100000000000001010000100001 comment: comment: comment: ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; comment: ; comment: ; set all registers HIGH comment: ; comment: ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; comment: comment: ; set pin AF1 (AND with itself) to clear pin BB2 (AND-NOR output) and set pin BR2 TAPE BUS 3 OUTPUT test 15: 1 0 1 comment: ; set pin AP2 (AND with itself) to clear pin AN2 (AND-NOR output) and set pin BV2 TAPE BUS 2 OUTPUT test 16: 1 0 1 comment: comment: comment: ; load TMA SETUP from tape bus (11) test 17: 111 test 18: 0 comment: ; load TMA from tape bus (11) test 19: 111 test 20: 0 comment: ; load TBN from tape bus (11) test 21: 111 test 22: 0 comment: ; load TAC from tape bus (11) test 23: 11010 test 24: 0 comment: ; load TB from tape bus (11) test 25: 111 test 26: 0 comment: ; load RWB from TB (JAMS CLEAR AND PRESET) test 27: 1 11 test 28: 0 comment: ; clear pin AF1 (AND with itself) to set pin BB2 (AND-NOR output) and clear pin BR2 TAPE BUS 3 OUTPUT test 29: 0 1 0 comment: ; clear pin AP2 (AND with itself) to set pin AN2 (AND-NOR output) and clear pin BV2 TAPE BUS 2 OUTPUT test 30: 0 1 0 comment: ; (no change) test 31: 100000000000000000000000000000000001111100011011011010100110111001 comment: comment: comment: ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; comment: ; comment: ; test AND-NOR logic comment: ; comment: ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; comment: comment: ; (all registers are HIGH) comment: ; set all pins HIGH except ENABLES comment: comment: ; set pin AF2 HIGH test 32: 1 comment: ; set pin AM1 HIGH test 33: 1 comment: ; set pin AE1 HIGH test 34: 1 comment: ; set pin AM2 HIGH test 35: 1 comment: ; set pin AB2 HIGH test 36: 1 comment: ; set pin AS1 HIGH test 37: 1 comment: ; set pin BE1 HIGH test 38: 1 comment: ; set pin BM1 HIGH test 39: 1 comment: ; set pin BH1 HIGH test 40: 1 comment: ; set pin BR1 HIGH test 41: 1 comment: ; set pin BC1 HIGH test 42: 1 comment: ; set pin BJ2 HIGH test 43: 1 comment: ; set pin BJ1 HIGH test 44: 1 comment: ; set pin BK2 HIGH test 45: 1 comment: ; set pin BH2 HIGH test 46: 1 comment: ; set pin BP2 HIGH test 47: 1 comment: ; set pin BN2 HIGH test 48: 1 comment: ; toggle each ENABLE comment: comment: ; set pin AL2 to clear pin BB2 and pin AN2 AND-NOR OUTPUTS and set TAPE BUS 2 OUTPUT and TAPE BUS 3 OUTPUT test 49: 1 0 0 11 test 50: 0 1 1 00 comment: ; set pin AP1 to clear pin BB2 and pin AN2 AND-NOR OUTPUTS and set TAPE BUS 2 OUTPUT and TAPE BUS 3 OUTPUT test 51: 1 0 0 11 test 52: 0 1 1 00 comment: ; set pin AS2 to clear pin BB2 and pin AN2 AND-NOR OUTPUTS and set TAPE BUS 2 OUTPUT and TAPE BUS 3 OUTPUT test 53: 1 0 0 11 test 54: 0 1 1 00 comment: ; set pin AL1 to clear pin BB2 and pin AN2 AND-NOR OUTPUTS and set TAPE BUS 2 OUTPUT and TAPE BUS 3 OUTPUT test 55: 1 0 0 11 test 56: 0 1 1 00 comment: ; set pin AL1 to clear pin BB2 and pin AN2 AND-NOR OUTPUTS and set TAPE BUS 2 OUTPUT and TAPE BUS 3 OUTPUT test 57: 1 0 0 11 test 58: 0 1 1 00 comment: ; set pin AE2 to clear pin BB2 and pin AN2 AND-NOR OUTPUTS and set TAPE BUS 2 OUTPUT and TAPE BUS 3 OUTPUT test 59: 1 0 0 11 test 60: 0 1 1 00 comment: ; set pin AC1 to clear pin BB2 and set TAPE BUS 3 OUTPUT test 61: 1 0 1 test 62: 0 1 0 comment: ; set pin AF1 to clear pin BB2 and set TAPE BUS 3 OUTPUT test 63: 1 0 1 test 64: 0 1 0 comment: ; set pin AR2 to clear pin AN2 AND-NOR OUTPUTS and set TAPE BUS 2 OUTPUT test 65: 1 0 1 test 66: 0 1 0 comment: ; set pin AP2 to clear pin AN2 AND-NOR OUTPUTS and set TAPE BUS 2 OUTPUT test 67: 1 0 1 test 68: 0 1 0 comment: comment: ; set pin BK1 to clear pin BB1 and pin BN1 AND-NOR OUTPUTS and set TAPE BUS 2 OUTPUT and TAPE BUS 3 OUTPUT test 69: 1 00 11 test 70: 0 11 00 comment: ; set pin BL1 to clear pin BB1 and pin BN1 AND-NOR OUTPUTS and set TAPE BUS 2 OUTPUT and TAPE BUS 3 OUTPUT test 71: 1 00 11 test 72: 0 11 00 comment: ; set pin BF1 to clear pin BB1 and pin BN1 AND-NOR OUTPUTS and set TAPE BUS 2 OUTPUT and TAPE BUS 3 OUTPUT test 73: 1 00 11 test 74: 0 11 00 comment: ; set pin BS1 to clear pin BB1 and pin BN1 AND-NOR OUTPUTS and set TAPE BUS 2 OUTPUT and TAPE BUS 3 OUTPUT test 75: 1 00 11 test 76: 0 11 00 comment: ; set pin BL2 to clear pin BB1 and pin BN1 AND-NOR OUTPUTS and set TAPE BUS 2 OUTPUT and TAPE BUS 3 OUTPUT test 77: 1 00 11 test 78: 0 11 00 comment: ; set pin BU1 to clear pin BB1 and pin BN1 AND-NOR OUTPUTS and set TAPE BUS 2 OUTPUT and TAPE BUS 3 OUTPUT test 79: 1 00 11 test 80: 0 11 00 comment: ; set pin BM2 to clear pin BB1 and TAPE BUS 3 OUTPUT test 81: 1 0 1 test 82: 0 1 0 comment: comment: comment: ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; comment: ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; comment: ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; comment: ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; comment: ; needs work comment: ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; comment: ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; comment: ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; comment: ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; end: END summary column 1: offset 2, mask 0x2000 column 2: offset 1, mask 0x0002 column 3: offset 1, mask 0x0800 column 4: offset 1, mask 0x0040 column 5: offset 1, mask 0x4000 column 6: offset 0, mask 0x0004 column 7: offset 1, mask 0x2000 column 8: offset 0, mask 0x0010 column 9: offset 0, mask 0x0008 column 10: offset 0, mask 0x0800 column 11: offset 1, mask 0x0004 column 12: offset 0, mask 0x2000 column 13: offset 0, mask 0x0040 column 14: offset 0, mask 0x0400 column 15: offset 1, mask 0x0020 column 16: offset 1, mask 0x0200 column 17: offset 1, mask 0x0010 column 18: offset 3, mask 0x2000 column 19: offset 3, mask 0x1000 column 20: offset 2, mask 0x0200 column 21: offset 3, mask 0x0800 column 22: offset 2, mask 0x0100 column 23: offset 3, mask 0x8000 column 24: offset 3, mask 0x0100 column 25: offset 4, mask 0x8000 column 26: offset 2, mask 0x0800 column 27: offset 3, mask 0x0002 column 28: offset 3, mask 0x0008 column 29: offset 3, mask 0x4000 column 30: offset 3, mask 0x0004 column 31: offset 4, mask 0x2000 column 32: offset 3, mask 0x0001 column 33: offset 3, mask 0x0040 column 34: offset 3, mask 0x0020 column 35: offset 3, mask 0x0010 column 36: offset 2, mask 0x0008 column 37: offset 2, mask 0x1000 column 38: offset 3, mask 0x0400 column 39: offset 1, mask 0x0008 column 40: offset 2, mask 0x0002 column 41: offset 4, mask 0x0008 column 42: offset 3, mask 0x0080 column 43: offset 1, mask 0x8000 column 44: offset 1, mask 0x0400 column 45: offset 0, mask 0x0200 column 46: offset 2, mask 0x0001 column 47: offset 1, mask 0x0080 column 48: offset 0, mask 0x1000 column 49: offset 0, mask 0x0100 column 50: offset 2, mask 0x8000 column 51: offset 1, mask 0x0001 column 52: offset 0, mask 0x8000 column 53: offset 1, mask 0x1000 column 54: offset 0, mask 0x0001 column 55: offset 0, mask 0x0002 column 56: offset 0, mask 0x4000 column 57: offset 4, mask 0x0002 column 58: offset 3, mask 0x0200 column 59: offset 2, mask 0x0400 column 60: offset 2, mask 0x0080 column 61: offset 4, mask 0x0001 column 62: offset 4, mask 0x1000 column 63: offset 2, mask 0x0020 column 64: offset 2, mask 0x0040 column 65: offset 2, mask 0x4000 column 66: offset 4, mask 0x0004 direction bits (1=input) 0x52A3 0x1589 0x943A 0x0680 0x50FC pullup bits (1=pullup) 0x0000 0x0000 0x0000 0x0000 0x0000 test step out_data dont care 1: 0x0000 0x0008 0x300A 0x0400 0x0005 0x5203 0x1481 0x8420 0x0200 0x1000 2: 0x0000 0x8008 0x300A 0x0400 0x0005 0x5003 0x1081 0x8420 0x0200 0x1000 3: 0x0000 0x0008 0x300A 0x0400 0x0005 0x5003 0x1081 0x8420 0x0200 0x1000 4: 0x0000 0x0008 0x300B 0x0400 0x0005 0x4003 0x1001 0x8420 0x0200 0x1000 5: 0x0000 0x0008 0x300A 0x0400 0x0005 0x4003 0x1001 0x8420 0x0200 0x1000 6: 0x0100 0x0008 0x300A 0x0400 0x0005 0x4003 0x1000 0x0420 0x0200 0x1000 7: 0x0000 0x0008 0x300A 0x0400 0x0005 0x4003 0x1000 0x0420 0x0200 0x1000 8: 0xC001 0x0008 0x300A 0x0400 0x0005 0x0000 0x0000 0x0420 0x0200 0x1000 9: 0x4001 0x0008 0x300A 0x0400 0x0005 0x0000 0x0000 0x0420 0x0200 0x1000 10: 0x4001 0x0008 0x300A 0x0400 0x0007 0x0000 0x0000 0x0020 0x0000 0x1000 11: 0x4001 0x0008 0x300A 0x0400 0x0005 0x0000 0x0000 0x0020 0x0000 0x1000 12: 0x4001 0x0008 0x308A 0x0400 0x0005 13: 0x4001 0x0008 0x300A 0x0400 0x0005 14: 0x4001 0x0008 0x300A 0x0400 0x0005 15: 0x4401 0x0008 0x3002 0x0480 0x0005 16: 0x4401 0x0010 0x3002 0x0480 0x000D 17: 0x4601 0x8410 0x3002 0x0480 0x000D 18: 0x4601 0x0410 0x3002 0x0480 0x000D 19: 0x5601 0x0490 0x3003 0x0480 0x000D 20: 0x5601 0x0490 0x3002 0x0480 0x000D 21: 0x5701 0x0491 0xB002 0x0480 0x000D 22: 0x5601 0x0491 0xB002 0x0480 0x000D 23: 0x9602 0x1491 0xB002 0x0480 0x000D 24: 0x1602 0x1491 0xB002 0x0480 0x000D 25: 0x1602 0x1491 0xB402 0x0680 0x000F 26: 0x1602 0x1491 0xB402 0x0680 0x000D 27: 0x1602 0x1491 0xB4A2 0x0680 0x100D 28: 0x1602 0x1491 0xB422 0x0680 0x100D 29: 0x1202 0x1491 0xB42A 0x0600 0x100D 30: 0x1202 0x1489 0xB42A 0x0600 0x1005 31: 0x1202 0x1489 0xB42A 0x0600 0x1005 32: 0x1206 0x1489 0xB42A 0x0600 0x1005 33: 0x1206 0x3489 0xB42A 0x0600 0x1005 34: 0x1A06 0x3489 0xB42A 0x0600 0x1005 35: 0x1A06 0x348D 0xB42A 0x0600 0x1005 36: 0x1A46 0x348D 0xB42A 0x0600 0x1005 37: 0x1A46 0x368D 0xB42A 0x0600 0x1005 38: 0x1A46 0x368D 0xB62A 0x0600 0x1005 39: 0x1A46 0x368D 0xB62A 0x0E00 0x1005 40: 0x1A46 0x368D 0xB62A 0x8E00 0x1005 41: 0x1A46 0x368D 0xB62A 0x8F00 0x1005 42: 0x1A46 0x368D 0xBE2A 0x8F00 0x1005 43: 0x1A46 0x368D 0xBE2A 0x8F02 0x1005 44: 0x1A46 0x368D 0xBE2A 0xCF02 0x1005 45: 0x1A46 0x368D 0xBE2A 0xCF06 0x1005 46: 0x1A46 0x368D 0xBE2A 0xCF07 0x1005 47: 0x1A46 0x368D 0xBE2A 0xCF47 0x1005 48: 0x1A46 0x368D 0xBE2A 0xCF67 0x1005 49: 0x1A46 0x3687 0xBE22 0xCFE7 0x100D 50: 0x1A46 0x368D 0xBE2A 0xCF67 0x1005 51: 0x1A46 0x3E85 0xBE22 0xCFE7 0x100D 52: 0x1A46 0x368D 0xBE2A 0xCF67 0x1005 53: 0x1A46 0x36C5 0xBE22 0xCFE7 0x100D 54: 0x1A46 0x368D 0xBE2A 0xCF67 0x1005 55: 0x1A46 0x7685 0xBE22 0xCFE7 0x100D 56: 0x1A46 0x368D 0xBE2A 0xCF67 0x1005 57: 0x1A56 0x3685 0xBE22 0xCFE7 0x100D 58: 0x1A46 0x368D 0xBE2A 0xCF67 0x1005 59: 0x1A4E 0x3685 0xBE22 0xCFE7 0x100D 60: 0x1A46 0x368D 0xBE2A 0xCF67 0x1005 61: 0x3A46 0x368D 0xBE22 0xCFE7 0x1005 62: 0x1A46 0x368D 0xBE2A 0xCF67 0x1005 63: 0x1E46 0x368D 0xBE22 0xCFE7 0x1005 64: 0x1A46 0x368D 0xBE2A 0xCF67 0x1005 65: 0x1A46 0x36A5 0xBE2A 0xCF67 0x100D 66: 0x1A46 0x368D 0xBE2A 0xCF67 0x1005 67: 0x1A46 0x3695 0xBE2A 0xCF67 0x100D 68: 0x1A46 0x368D 0xBE2A 0xCF67 0x1005 69: 0x1A46 0x368D 0xAE2A 0xEBE7 0x100D 70: 0x1A46 0x368D 0xBE2A 0xCF67 0x1005 71: 0x1A46 0x368D 0xAE2A 0xDBE7 0x100D 72: 0x1A46 0x368D 0xBE2A 0xCF67 0x1005 73: 0x1A46 0x368D 0xAF2A 0xCBE7 0x100D 74: 0x1A46 0x368D 0xBE2A 0xCF67 0x1005 75: 0x1A46 0x368D 0xAE2A 0xCBE7 0x900D 76: 0x1A46 0x368D 0xBE2A 0xCF67 0x1005 77: 0x1A46 0x368D 0xAE2A 0xCBEF 0x100D 78: 0x1A46 0x368D 0xBE2A 0xCF67 0x1005 79: 0x1A46 0x368D 0xAE2A 0xCBE7 0x300D 80: 0x1A46 0x368D 0xBE2A 0xCF67 0x1005 81: 0x1A46 0x368D 0xBE2A 0xCB77 0x100D 82: 0x1A46 0x368D 0xBE2A 0xCF67 0x1005 PINs used (in edge connector order) (G=ground,P=power) SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBB LETTER ABCDEFHJKLMNPRSTUVABCDEFHJKLMNPRSTUVABCDEFHJKLMNPRSTUVABCDEFHJKLMNPRSTUV SIDE 111111111111111111222222222222222222111111111111111111222222222222222222 USAGE IOIOIIOIIIIOIOIGOIPIGIIIOOOIIOIIIOIOIOIOIIIIIIIOOIIGIOPOGOIIIIIIIIIOIIOO UUT has 44 inputs UUT has 22 outputs contains 66 pins/columns 0 pins are not used contains 82 'test steps' M222 PCB REV B SCHEMATIC REV A LINC TAPE REGISTERS TERMINOLOGY- SIGNALS REFER TO VOL4 M222 SCHEMATIC. BUT... DEC USES AND-NOR GATES TO ROUTE THE ADDER A AND B INPUTS, SO... DEC RENAMED THE ADDER TO NEGATIVE LOGIC TERMS (I.E. A-N + B-N + C-N -> SUM-N, C1-N). (NOT THE 7482 DATASHEET NAMES OF A + B + C -> SUM, C1). SO, WITH ALL 'AND ENABLES' LOW, THE AND-NOR OUTPUTS = HIGH. WITH C-L HIGH, THE ADDER OUTPUT IS SUM-N=1, C1-N=1; THE INVERTED ADDER OUTPUT IS LOW (TAPE BUS). AND THERE IS NO CARRY (C1-N IS HI). THE TWO ADDERS, TWO REGISTER BITS, ETC ARE LABELED BIT 2 (EVEN, MSB) AND BIT 3 (ODD, LSB). THE ADDERS ARE REFERRED TO AS 'ADDER2' (MSB) AND 'ADDER3' (LSB). POWER PINS: AA2 +5V AT1 GROUND AC2 GROUND BA2 +5V BT1 GROUND BC2 GROUND (ALL PINS ARE USED). PINS Main menu Thu Aug 20 15:31:57 2015 test file is: tests\m222.tst delay is: 0 trigger is: 1 1 read test file 2 set test delay 3 set test trigger 4 run test 5 output loading test 8 diags 9 exit UUT power is okay Thu Aug 20 15:31:59 2015 space single step O run once (one test, all steps) F run, stop on fail G go (run tests N run, stop on fail, no print S scope (run, no print) C toggle comment printout + increase speed (less delay) - decrease speed (more delay)(slower) Q quit test scope (run, no print) ppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppp pppppppppppppppppppppppppppppppppppppppp space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C toggle comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C toggle comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C toggle comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C toggle comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT BAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBAABBAAAAAAAAAAAAAABBBBBBBBAB LETTER ALPSLFMDEEMCBFRSPKLEMFHRSCJLJKUHPNMBBNNVVRKRHUTDJUKANJHBTPDFSVDEVU SIDE 121212122121212121111111112212122222112222111221112112212112212212 DIRECTION IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIOOOOOOOIOOIOOIOOIOOOOIOOIIOOIIO all fails was lo 00000000000000000000000000000000000000 00000000000000000000 0000 falling vvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvv vvvvvvvvvvvvvvvvvvvv vv rising ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ ^^^^^^^^^^^^^^^^^^^^ ^^ was hi 111111111111111111111111111111111111111111111111111111111111111 1 total fails 0, total passes 119 Main menu Thu Aug 20 15:32:46 2015 test file is: tests\m222.tst delay is: 0 trigger is: 1 1 read test file 2 set test delay 3 set test trigger 4 run test 5 output loading test 8 diags 9 exit UUT power is okay Thu Aug 20 15:32:49 2015 space single step O run once (one test, all steps) F run, stop on fail G go (run tests N run, stop on fail, no print S scope (run, no print) C toggle comment printout + increase speed (less delay) - decrease speed (more delay)(slower) Q quit test scope (run, no print) ppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppp space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C toggle comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT BAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBAABBAAAAAAAAAAAAAABBBBBBBBAB LETTER ALPSLFMDEEMCBFRSPKLEMFHRSCJLJKUHPNMBBNNVVRKRHUTDJUKANJHBTPDFSVDEVU SIDE 121212122121212121111111112212122222112222111221112112212112212212 DIRECTION IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIOOOOOOOIOOIOOIOOIOOOOIOOIIOOIIO all fails was lo 00000000000000000000000000000000000000 00000000000000000000 0000 falling vvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvv vvvvvvvvvvvvvvvvvvvv vv rising ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ ^^^^^^^^^^^^^^^^^^^^ ^^ was hi 111111111111111111111111111111111111111111111111111111111111111 1 total fails 0, total passes 65 Main menu Thu Aug 20 15:32:56 2015 test file is: tests\m222.tst delay is: 0 trigger is: 1 1 read test file 2 set test delay 3 set test trigger 4 run test 5 output loading test 8 diags 9 exit UUT power is okay Thu Aug 20 15:33:22 2015 space single step O run once (one test, all steps) F run, stop on fail G go (run tests N run, stop on fail, no print S scope (run, no print) C toggle comment printout + increase speed (less delay) - decrease speed (more delay)(slower) Q quit test scope (run, no print) ppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppp pppppppppp space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C toggle comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT BAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBAABBAAAAAAAAAAAAAABBBBBBBBAB LETTER ALPSLFMDEEMCBFRSPKLEMFHRSCJLJKUHPNMBBNNVVRKRHUTDJUKANJHBTPDFSVDEVU SIDE 121212122121212121111111112212122222112222111221112112212112212212 DIRECTION IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIOOOOOOOIOOIOOIOOIOOOOIOOIIOOIIO all fails was lo 00000000000000000000000000000000000000 00000000000000000000 0000 falling vvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvv vvvvvvvvvvvvvvvvvvvv vv rising ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ ^^^^^^^^^^^^^^^^^^^^ ^^ was hi 111111111111111111111111111111111111111111111111111111111111111 1 total fails 0, total passes 89 Main menu Thu Aug 20 15:33:28 2015 test file is: tests\m222.tst delay is: 0 trigger is: 1 1 read test file 2 set test delay 3 set test trigger 4 run test 5 output loading test 8 diags 9 exit UUT power is okay Thu Aug 20 15:33:54 2015 space single step O run once (one test, all steps) F run, stop on fail G go (run tests N run, stop on fail, no print S scope (run, no print) C toggle comment printout + increase speed (less delay) - decrease speed (more delay)(slower) Q quit test scope (run, no print) ppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppp ppppppppppFppppppppppppppppppppppppppppppppppppppppppppppppppp space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C toggle comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT BAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBAABBAAAAAAAAAAAAAABBBBBBBBAB LETTER ALPSLFMDEEMCBFRSPKLEMFHRSCJLJKUHPNMBBNNVVRKRHUTDJUKANJHBTPDFSVDEVU SIDE 121212122121212121111111112212122222112222111221112112212112212212 DIRECTION IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIOOOOOOOIOOIOOIOOIOOOOIOOIIOOIIO all fails I I I II O O O O I was lo 00000000000000000000000000000000000000 00000000000000000000 0000 falling vvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvv vvvvvvvvvvvvvvvvvvvv vv v rising ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ ^^^^^^^^^^^^^^^^^^^^ ^^ ^ was hi 111111111111111111111111111111111111111111111111111111111111111 11 total fails 1, total passes 140 Main menu Thu Aug 20 15:34:03 2015 test file is: tests\m222.tst delay is: 0 trigger is: 1 1 read test file 2 set test delay 3 set test trigger 4 run test 5 output loading test 8 diags 9 exit UUT power is okay Thu Aug 20 15:34:12 2015 space single step O run once (one test, all steps) F run, stop on fail G go (run tests N run, stop on fail, no print S scope (run, no print) C toggle comment printout + increase speed (less delay) - decrease speed (more delay)(slower) Q quit test scope (run, no print) ppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppp p space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C toggle comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C toggle comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT BAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBAABBAAAAAAAAAAAAAABBBBBBBBAB LETTER ALPSLFMDEEMCBFRSPKLEMFHRSCJLJKUHPNMBBNNVVRKRHUTDJUKANJHBTPDFSVDEVU SIDE 121212122121212121111111112212122222112222111221112112212112212212 DIRECTION IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIOOOOOOOIOOIOOIOOIOOOOIOOIIOOIIO all fails was lo 00000000000000000000000000000000000000 00000000000000000000 0000 falling vvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvv vvvvvvvvvvvvvvvvvvvv vv rising ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ ^^^^^^^^^^^^^^^^^^^^ ^^ was hi 111111111111111111111111111111111111111111111111111111111111111 1 total fails 0, total passes 80 Main menu Thu Aug 20 15:34:21 2015 test file is: tests\m222.tst delay is: 0 trigger is: 1 1 read test file 2 set test delay 3 set test trigger 4 run test 5 output loading test 8 diags 9 exit UUT power is okay Thu Aug 20 15:34:52 2015 space single step O run once (one test, all steps) F run, stop on fail G go (run tests N run, stop on fail, no print S scope (run, no print) C toggle comment printout + increase speed (less delay) - decrease speed (more delay)(slower) Q quit test scope (run, no print) FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C toggle comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit step 55 100011100110100100011011011011011100110111011011011010100110111001 step 56 100001100110100100011011011011011101111100011011011010100110111001 step 57 100001110110100100011011011011011100110111011011011010100110111001 step 58 100001100110100100011011011011011101111100011011011010100110111001 step 59 100001101110100100011011011011011100110111011011011010100110111001 step 60 100001100110100100011011011011011101111100011011011010100110111001 step 61 100001100111100100011011011011011100111101011011011010100110111001 step 62 100001100110100100011011011011011101111100011011011010100110111001 step 63 100001100110110100011011011011011100111101011011011010100110111001 step 64 100001100110100100011011011011011101111100011011011010100110111001 step 65 100001100110101100011011011011011101110110011011011010100110111001 step 66 100001100110100100011011011011011101111100011011011010100110111001 step 67 100001100110100110011011011011011101110110011011011010100110111001 step 68 100001100110100100011011011011011101111100011011011010100110111001 step 69 100001100110100101011011011011011101001111011011011010100110111001 SLOT BAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBAABBAAAAAAAAAAAAAABBBBBBBBAB LETTER ALPSLFMDEEMCBFRSPKLEMFHRSCJLJKUHPNMBBNNVVRKRHUTDJUKANJHBTPDFSVDEVU SIDE 121212122121212121111111112212122222112222111221112112212112212212 DIRECTION IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIOOOOOOOIOOIOOIOOIOOOOIOOIIOOIIO changed: 0 1 00 step 70 100001100110100100011011011011011101011100011011011010100110111001 fail ^ step 71 100001100110100100111011011011011101001111011011011010100110111001 SLOT BAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBAABBAAAAAAAAAAAAAABBBBBBBBAB LETTER ALPSLFMDEEMCBFRSPKLEMFHRSCJLJKUHPNMBBNNVVRKRHUTDJUKANJHBTPDFSVDEVU SIDE 121212122121212121111111112212122222112222111221112112212112212212 DIRECTION IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIOOOOOOOIOOIOOIOOIOOOOIOOIIOOIIO changed: 0 1 00 step 72 100001100110100100011011011011011101011100011011011010100110111001 fail ^ step 73 100001100110100100011111011011011101001111011011011010100110111001 SLOT BAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBAABBAAAAAAAAAAAAAABBBBBBBBAB LETTER ALPSLFMDEEMCBFRSPKLEMFHRSCJLJKUHPNMBBNNVVRKRHUTDJUKANJHBTPDFSVDEVU SIDE 121212122121212121111111112212122222112222111221112112212112212212 DIRECTION IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIOOOOOOOIOOIOOIOOIOOOOIOOIIOOIIO changed: 0 1 00 step 74 100001100110100100011011011011011101011100011011011010100110111001 fail ^ step 75 100001100110100100011011111011011101001111011011011010100110111001 SLOT BAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBAABBAAAAAAAAAAAAAABBBBBBBBAB LETTER ALPSLFMDEEMCBFRSPKLEMFHRSCJLJKUHPNMBBNNVVRKRHUTDJUKANJHBTPDFSVDEVU SIDE 121212122121212121111111112212122222112222111221112112212112212212 DIRECTION IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIOOOOOOOIOOIOOIOOIOOOOIOOIIOOIIO changed: 0 1 00 step 76 100001100110100100011011011011011101011100011011011010100110111001 fail ^ SLOT BAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBAABBAAAAAAAAAAAAAABBBBBBBBAB LETTER ALPSLFMDEEMCBFRSPKLEMFHRSCJLJKUHPNMBBNNVVRKRHUTDJUKANJHBTPDFSVDEVU SIDE 121212122121212121111111112212122222112222111221112112212112212212 DIRECTION IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIOOOOOOOIOOIOOIOOIOOOOIOOIIOOIIO changed: 1 0 1 step 77 100001100110100100011011011111011101001110011011011010100110111001 fail ^ SLOT BAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBAABBAAAAAAAAAAAAAABBBBBBBBAB LETTER ALPSLFMDEEMCBFRSPKLEMFHRSCJLJKUHPNMBBNNVVRKRHUTDJUKANJHBTPDFSVDEVU SIDE 121212122121212121111111112212122222112222111221112112212112212212 DIRECTION IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIOOOOOOOIOOIOOIOOIOOOOIOOIIOOIIO changed: 0 1 0 step 78 100001100110100100011011011011011101011100011011011010100110111001 fail ^ SLOT BAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBAABBAAAAAAAAAAAAAABBBBBBBBAB LETTER ALPSLFMDEEMCBFRSPKLEMFHRSCJLJKUHPNMBBNNVVRKRHUTDJUKANJHBTPDFSVDEVU SIDE 121212122121212121111111112212122222112222111221112112212112212212 DIRECTION IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIOOOOOOOIOOIOOIOOIOOOOIOOIIOOIIO changed: 1 0 1 step 79 100001100110100100011011011011111101001110011011011010100110111001 fail ^ SLOT BAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBAABBAAAAAAAAAAAAAABBBBBBBBAB LETTER ALPSLFMDEEMCBFRSPKLEMFHRSCJLJKUHPNMBBNNVVRKRHUTDJUKANJHBTPDFSVDEVU SIDE 121212122121212121111111112212122222112222111221112112212112212212 DIRECTION IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIOOOOOOOIOOIOOIOOIOOOOIOOIIOOIIO changed: 0 1 0 step 80 100001100110100100011011011011011101011100011011011010100110111001 fail ^ SLOT BAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBAABBAAAAAAAAAAAAAABBBBBBBBAB LETTER ALPSLFMDEEMCBFRSPKLEMFHRSCJLJKUHPNMBBNNVVRKRHUTDJUKANJHBTPDFSVDEVU SIDE 121212122121212121111111112212122222112222111221112112212112212212 DIRECTION IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIOOOOOOOIOOIOOIOOIOOOOIOOIIOOIIO changed: 1 0 1 step 81 100001100110100100011011011011011111001110011011011010100110111001 fail ^ SLOT BAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBAABBAAAAAAAAAAAAAABBBBBBBBAB LETTER ALPSLFMDEEMCBFRSPKLEMFHRSCJLJKUHPNMBBNNVVRKRHUTDJUKANJHBTPDFSVDEVU SIDE 121212122121212121111111112212122222112222111221112112212112212212 DIRECTION IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIOOOOOOOIOOIOOIOOIOOOOIOOIIOOIIO changed: 0 1 0 step 82 100001100110100100011011011011011101011100011011011010100110111001 fail ^ test 66: *** FAIL *************************** 10 steps failed SLOT BAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBAABBAAAAAAAAAAAAAABBBBBBBBAB LETTER ALPSLFMDEEMCBFRSPKLEMFHRSCJLJKUHPNMBBNNVVRKRHUTDJUKANJHBTPDFSVDEVU SIDE 121212122121212121111111112212122222112222111221112112212112212212 DIRECTION IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIOOOOOOOIOOIOOIOOIOOOOIOOIIOOIIO this fail O O all fails O O was hi 111111111111111111111111111111111111111111111111111111111111111 1 rising ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ ^^^^^^^^^^^^^^^^^^^^ ^^ falling vvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvv vvvvvvvvvvvvvvvvvvvv vv was lo 00000000000000000000000000000000000000 00000000000000000000 0000 total fails 66, total passes 0 space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C toggle comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit step 1 100000000000000000000000000000000001111100011011011010100110111001 step 2 100000000000000000000000000000000001111100100011011010100110111001 step 3 100000000000000000000000000000000001111100000011011010100110111001 step 4 100000000000000000000000000000000001111100000100011010100110111001 step 5 100000000000000000000000000000000001111100000000011010100110111001 step 6 100000000000000000000000000000000001111100000000100010100110111001 step 7 100000000000000000000000000000000001111100000000000010100110111001 step 8 100000000000000000000000000000000001111100000000000101010110111001 step 9 100000000000000000000000000000000001111100000000000001010110111001 step 10 100000000000000000000000000000000001111100000000000001011000111001 step 11 100000000000000000000000000000000001111100000000000001010000111001 step 12 100000000000000000000000000000000001111100000000000001010001100001 step 13 100000000000000000000000000000000001111100000000000001010000100001 step 14 100000000000000000000000000000000001111100000000000001010000100001 step 15 100000000000010000000000000000000000111101000000000001010000100001 step 16 100000000000010010000000000000000000110111000000000001010000100001 step 17 100000000000010010000000000000000000110111111000000001010000100001 step 18 100000000000010010000000000000000000110111011000000001010000100001 step 19 100000000000010010000000000000000000110111011111000001010000100001 step 20 100000000000010010000000000000000000110111011011000001010000100001 step 21 100000000000010010000000000000000000110111011011111001010000100001 step 22 100000000000010010000000000000000000110111011011011001010000100001 step 23 100000000000010010000000000000000000110111011011011110100000100001 step 24 100000000000010010000000000000000000110111011011011010100000100001 step 25 100000000000010010000000000000000000110111011011011010101110100001 step 26 100000000000010010000000000000000000110111011011011010100110100001 step 27 100000000000010010000000000000000000110111011011011010100111111001 step 28 100000000000010010000000000000000000110111011011011010100110111001 step 29 100000000000000010000000000000000001110110011011011010100110111001 step 30 100000000000000000000000000000000001111100011011011010100110111001 step 31 100000000000000000000000000000000001111100011011011010100110111001 step 32 100001000000000000000000000000000001111100011011011010100110111001 step 33 100001100000000000000000000000000001111100011011011010100110111001 step 34 100001100100000000000000000000000001111100011011011010100110111001 step 35 100001100110000000000000000000000001111100011011011010100110111001 step 36 100001100110100000000000000000000001111100011011011010100110111001 step 37 100001100110100100000000000000000001111100011011011010100110111001 step 38 100001100110100100010000000000000001111100011011011010100110111001 step 39 100001100110100100011000000000000001111100011011011010100110111001 step 40 100001100110100100011010000000000001111100011011011010100110111001 step 41 100001100110100100011011000000000001111100011011011010100110111001 step 42 100001100110100100011011010000000001111100011011011010100110111001 step 43 100001100110100100011011011000000001111100011011011010100110111001 step 44 100001100110100100011011011010000001111100011011011010100110111001 step 45 100001100110100100011011011011000001111100011011011010100110111001 step 46 100001100110100100011011011011010001111100011011011010100110111001 step 47 100001100110100100011011011011011001111100011011011010100110111001 step 48 100001100110100100011011011011011101111100011011011010100110111001 step 49 110001100110100100011011011011011100110111011011011010100110111001 step 50 100001100110100100011011011011011101111100011011011010100110111001 step 51 101001100110100100011011011011011100110111011011011010100110111001 step 52 100001100110100100011011011011011101111100011011011010100110111001 step 53 100101100110100100011011011011011100110111011011011010100110111001 step 54 100001100110100100011011011011011101111100011011011010100110111001 step 55 100011100110100100011011011011011100110111011011011010100110111001 step 56 100001100110100100011011011011011101111100011011011010100110111001 step 57 100001110110100100011011011011011100110111011011011010100110111001 step 58 100001100110100100011011011011011101111100011011011010100110111001 step 59 100001101110100100011011011011011100110111011011011010100110111001 step 60 100001100110100100011011011011011101111100011011011010100110111001 step 61 100001100111100100011011011011011100111101011011011010100110111001 step 62 100001100110100100011011011011011101111100011011011010100110111001 step 63 100001100110110100011011011011011100111101011011011010100110111001 step 64 100001100110100100011011011011011101111100011011011010100110111001 step 65 100001100110101100011011011011011101110110011011011010100110111001 step 66 100001100110100100011011011011011101111100011011011010100110111001 step 67 100001100110100110011011011011011101110110011011011010100110111001 step 68 100001100110100100011011011011011101111100011011011010100110111001 step 69 100001100110100101011011011011011101001111011011011010100110111001 SLOT BAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBAABBAAAAAAAAAAAAAABBBBBBBBAB LETTER ALPSLFMDEEMCBFRSPKLEMFHRSCJLJKUHPNMBBNNVVRKRHUTDJUKANJHBTPDFSVDEVU SIDE 121212122121212121111111112212122222112222111221112112212112212212 DIRECTION IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIOOOOOOOIOOIOOIOOIOOOOIOOIIOOIIO changed: 0 1 00 step 70 100001100110100100011011011011011101011100011011011010100110111001 fail ^ step 71 100001100110100100111011011011011101001111011011011010100110111001 SLOT BAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBAABBAAAAAAAAAAAAAABBBBBBBBAB LETTER ALPSLFMDEEMCBFRSPKLEMFHRSCJLJKUHPNMBBNNVVRKRHUTDJUKANJHBTPDFSVDEVU SIDE 121212122121212121111111112212122222112222111221112112212112212212 DIRECTION IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIOOOOOOOIOOIOOIOOIOOOOIOOIIOOIIO changed: 0 1 00 step 72 100001100110100100011011011011011101011100011011011010100110111001 fail ^ step 73 100001100110100100011111011011011101001111011011011010100110111001 SLOT BAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBAABBAAAAAAAAAAAAAABBBBBBBBAB LETTER ALPSLFMDEEMCBFRSPKLEMFHRSCJLJKUHPNMBBNNVVRKRHUTDJUKANJHBTPDFSVDEVU SIDE 121212122121212121111111112212122222112222111221112112212112212212 DIRECTION IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIOOOOOOOIOOIOOIOOIOOOOIOOIIOOIIO changed: 0 1 00 step 74 100001100110100100011011011011011101011100011011011010100110111001 fail ^ step 75 100001100110100100011011111011011101001111011011011010100110111001 SLOT BAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBAABBAAAAAAAAAAAAAABBBBBBBBAB LETTER ALPSLFMDEEMCBFRSPKLEMFHRSCJLJKUHPNMBBNNVVRKRHUTDJUKANJHBTPDFSVDEVU SIDE 121212122121212121111111112212122222112222111221112112212112212212 DIRECTION IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIOOOOOOOIOOIOOIOOIOOOOIOOIIOOIIO changed: 0 1 00 step 76 100001100110100100011011011011011101011100011011011010100110111001 fail ^ SLOT BAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBAABBAAAAAAAAAAAAAABBBBBBBBAB LETTER ALPSLFMDEEMCBFRSPKLEMFHRSCJLJKUHPNMBBNNVVRKRHUTDJUKANJHBTPDFSVDEVU SIDE 121212122121212121111111112212122222112222111221112112212112212212 DIRECTION IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIOOOOOOOIOOIOOIOOIOOOOIOOIIOOIIO changed: 1 0 1 step 77 100001100110100100011011011111011101001110011011011010100110111001 fail ^ SLOT BAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBAABBAAAAAAAAAAAAAABBBBBBBBAB LETTER ALPSLFMDEEMCBFRSPKLEMFHRSCJLJKUHPNMBBNNVVRKRHUTDJUKANJHBTPDFSVDEVU SIDE 121212122121212121111111112212122222112222111221112112212112212212 DIRECTION IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIOOOOOOOIOOIOOIOOIOOOOIOOIIOOIIO changed: 0 1 0 step 78 100001100110100100011011011011011101011100011011011010100110111001 fail ^ SLOT BAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBAABBAAAAAAAAAAAAAABBBBBBBBAB LETTER ALPSLFMDEEMCBFRSPKLEMFHRSCJLJKUHPNMBBNNVVRKRHUTDJUKANJHBTPDFSVDEVU SIDE 121212122121212121111111112212122222112222111221112112212112212212 DIRECTION IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIOOOOOOOIOOIOOIOOIOOOOIOOIIOOIIO changed: 1 0 1 step 79 100001100110100100011011011011111101001110011011011010100110111001 fail ^ SLOT BAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBAABBAAAAAAAAAAAAAABBBBBBBBAB LETTER ALPSLFMDEEMCBFRSPKLEMFHRSCJLJKUHPNMBBNNVVRKRHUTDJUKANJHBTPDFSVDEVU SIDE 121212122121212121111111112212122222112222111221112112212112212212 DIRECTION IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIOOOOOOOIOOIOOIOOIOOOOIOOIIOOIIO changed: 0 1 0 step 80 100001100110100100011011011011011101011100011011011010100110111001 fail ^ SLOT BAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBAABBAAAAAAAAAAAAAABBBBBBBBAB LETTER ALPSLFMDEEMCBFRSPKLEMFHRSCJLJKUHPNMBBNNVVRKRHUTDJUKANJHBTPDFSVDEVU SIDE 121212122121212121111111112212122222112222111221112112212112212212 DIRECTION IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIOOOOOOOIOOIOOIOOIOOOOIOOIIOOIIO changed: 1 0 1 step 81 100001100110100100011011011011011111001110011011011010100110111001 fail ^ SLOT BAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBAABBAAAAAAAAAAAAAABBBBBBBBAB LETTER ALPSLFMDEEMCBFRSPKLEMFHRSCJLJKUHPNMBBNNVVRKRHUTDJUKANJHBTPDFSVDEVU SIDE 121212122121212121111111112212122222112222111221112112212112212212 DIRECTION IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIOOOOOOOIOOIOOIOOIOOOOIOOIIOOIIO changed: 0 1 0 step 82 100001100110100100011011011011011101011100011011011010100110111001 fail ^ test 67: *** FAIL *************************** 10 steps failed SLOT BAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBAABBAAAAAAAAAAAAAABBBBBBBBAB LETTER ALPSLFMDEEMCBFRSPKLEMFHRSCJLJKUHPNMBBNNVVRKRHUTDJUKANJHBTPDFSVDEVU SIDE 121212122121212121111111112212122222112222111221112112212112212212 DIRECTION IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIOOOOOOOIOOIOOIOOIOOOOIOOIIOOIIO this fail O O all fails O O was hi 111111111111111111111111111111111111111111111111111111111111111 1 rising ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ ^^^^^^^^^^^^^^^^^^^^ ^^ falling vvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvv vvvvvvvvvvvvvvvvvvvv vv was lo 00000000000000000000000000000000000000 00000000000000000000 0000 total fails 67, total passes 0 space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C toggle comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit step 1 100000000000000000000000000000000001111100011011011010100110111001 step 2 100000000000000000000000000000000001111100100011011010100110111001 step 3 100000000000000000000000000000000001111100000011011010100110111001 step 4 100000000000000000000000000000000001111100000100011010100110111001 step 5 100000000000000000000000000000000001111100000000011010100110111001 step 6 100000000000000000000000000000000001111100000000100010100110111001 step 7 100000000000000000000000000000000001111100000000000010100110111001 step 8 100000000000000000000000000000000001111100000000000101010110111001 step 9 100000000000000000000000000000000001111100000000000001010110111001 step 10 100000000000000000000000000000000001111100000000000001011000111001 step 11 100000000000000000000000000000000001111100000000000001010000111001 step 12 100000000000000000000000000000000001111100000000000001010001100001 step 13 100000000000000000000000000000000001111100000000000001010000100001 step 14 100000000000000000000000000000000001111100000000000001010000100001 step 15 100000000000010000000000000000000000111101000000000001010000100001 step 16 100000000000010010000000000000000000110111000000000001010000100001 step 17 100000000000010010000000000000000000110111111000000001010000100001 step 18 100000000000010010000000000000000000110111011000000001010000100001 step 19 100000000000010010000000000000000000110111011111000001010000100001 step 20 100000000000010010000000000000000000110111011011000001010000100001 step 21 100000000000010010000000000000000000110111011011111001010000100001 step 22 100000000000010010000000000000000000110111011011011001010000100001 step 23 100000000000010010000000000000000000110111011011011110100000100001 step 24 100000000000010010000000000000000000110111011011011010100000100001 step 25 100000000000010010000000000000000000110111011011011010101110100001 step 26 100000000000010010000000000000000000110111011011011010100110100001 step 27 100000000000010010000000000000000000110111011011011010100111111001 step 28 100000000000010010000000000000000000110111011011011010100110111001 step 29 100000000000000010000000000000000001110110011011011010100110111001 step 30 100000000000000000000000000000000001111100011011011010100110111001 step 31 100000000000000000000000000000000001111100011011011010100110111001 step 32 100001000000000000000000000000000001111100011011011010100110111001 step 33 100001100000000000000000000000000001111100011011011010100110111001 step 34 100001100100000000000000000000000001111100011011011010100110111001 step 35 100001100110000000000000000000000001111100011011011010100110111001 step 36 100001100110100000000000000000000001111100011011011010100110111001 step 37 100001100110100100000000000000000001111100011011011010100110111001 step 38 100001100110100100010000000000000001111100011011011010100110111001 step 39 100001100110100100011000000000000001111100011011011010100110111001 step 40 100001100110100100011010000000000001111100011011011010100110111001 step 41 100001100110100100011011000000000001111100011011011010100110111001 step 42 100001100110100100011011010000000001111100011011011010100110111001 step 43 100001100110100100011011011000000001111100011011011010100110111001 step 44 100001100110100100011011011010000001111100011011011010100110111001 step 45 100001100110100100011011011011000001111100011011011010100110111001 step 46 100001100110100100011011011011010001111100011011011010100110111001 step 47 100001100110100100011011011011011001111100011011011010100110111001 step 48 100001100110100100011011011011011101111100011011011010100110111001 step 49 110001100110100100011011011011011100110111011011011010100110111001 step 50 100001100110100100011011011011011101111100011011011010100110111001 step 51 101001100110100100011011011011011100110111011011011010100110111001 step 52 100001100110100100011011011011011101111100011011011010100110111001 step 53 100101100110100100011011011011011100110111011011011010100110111001 step 54 100001100110100100011011011011011101111100011011011010100110111001 step 55 100011100110100100011011011011011100110111011011011010100110111001 step 56 100001100110100100011011011011011101111100011011011010100110111001 step 57 100001110110100100011011011011011100110111011011011010100110111001 step 58 100001100110100100011011011011011101111100011011011010100110111001 step 59 100001101110100100011011011011011100110111011011011010100110111001 step 60 100001100110100100011011011011011101111100011011011010100110111001 step 61 100001100111100100011011011011011100111101011011011010100110111001 step 62 100001100110100100011011011011011101111100011011011010100110111001 step 63 100001100110110100011011011011011100111101011011011010100110111001 step 64 100001100110100100011011011011011101111100011011011010100110111001 step 65 100001100110101100011011011011011101110110011011011010100110111001 step 66 100001100110100100011011011011011101111100011011011010100110111001 step 67 100001100110100110011011011011011101110110011011011010100110111001 step 68 100001100110100100011011011011011101111100011011011010100110111001 step 69 100001100110100101011011011011011101001111011011011010100110111001 SLOT BAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBAABBAAAAAAAAAAAAAABBBBBBBBAB LETTER ALPSLFMDEEMCBFRSPKLEMFHRSCJLJKUHPNMBBNNVVRKRHUTDJUKANJHBTPDFSVDEVU SIDE 121212122121212121111111112212122222112222111221112112212112212212 DIRECTION IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIOOOOOOOIOOIOOIOOIOOOOIOOIIOOIIO changed: 0 1 00 step 70 100001100110100100011011011011011101011100011011011010100110111001 fail ^ step 71 100001100110100100111011011011011101001111011011011010100110111001 SLOT BAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBAABBAAAAAAAAAAAAAABBBBBBBBAB LETTER ALPSLFMDEEMCBFRSPKLEMFHRSCJLJKUHPNMBBNNVVRKRHUTDJUKANJHBTPDFSVDEVU SIDE 121212122121212121111111112212122222112222111221112112212112212212 DIRECTION IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIOOOOOOOIOOIOOIOOIOOOOIOOIIOOIIO changed: 0 1 00 step 72 100001100110100100011011011011011101011100011011011010100110111001 fail ^ step 73 100001100110100100011111011011011101001111011011011010100110111001 SLOT BAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBAABBAAAAAAAAAAAAAABBBBBBBBAB LETTER ALPSLFMDEEMCBFRSPKLEMFHRSCJLJKUHPNMBBNNVVRKRHUTDJUKANJHBTPDFSVDEVU SIDE 121212122121212121111111112212122222112222111221112112212112212212 DIRECTION IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIOOOOOOOIOOIOOIOOIOOOOIOOIIOOIIO changed: 0 1 00 step 74 100001100110100100011011011011011101011100011011011010100110111001 fail ^ step 75 100001100110100100011011111011011101001111011011011010100110111001 SLOT BAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBAABBAAAAAAAAAAAAAABBBBBBBBAB LETTER ALPSLFMDEEMCBFRSPKLEMFHRSCJLJKUHPNMBBNNVVRKRHUTDJUKANJHBTPDFSVDEVU SIDE 121212122121212121111111112212122222112222111221112112212112212212 DIRECTION IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIOOOOOOOIOOIOOIOOIOOOOIOOIIOOIIO changed: 0 1 00 step 76 100001100110100100011011011011011101011100011011011010100110111001 fail ^ SLOT BAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBAABBAAAAAAAAAAAAAABBBBBBBBAB LETTER ALPSLFMDEEMCBFRSPKLEMFHRSCJLJKUHPNMBBNNVVRKRHUTDJUKANJHBTPDFSVDEVU SIDE 121212122121212121111111112212122222112222111221112112212112212212 DIRECTION IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIOOOOOOOIOOIOOIOOIOOOOIOOIIOOIIO changed: 1 0 1 step 77 100001100110100100011011011111011101001110011011011010100110111001 fail ^ SLOT BAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBAABBAAAAAAAAAAAAAABBBBBBBBAB LETTER ALPSLFMDEEMCBFRSPKLEMFHRSCJLJKUHPNMBBNNVVRKRHUTDJUKANJHBTPDFSVDEVU SIDE 121212122121212121111111112212122222112222111221112112212112212212 DIRECTION IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIOOOOOOOIOOIOOIOOIOOOOIOOIIOOIIO changed: 0 1 0 step 78 100001100110100100011011011011011101011100011011011010100110111001 fail ^ SLOT BAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBAABBAAAAAAAAAAAAAABBBBBBBBAB LETTER ALPSLFMDEEMCBFRSPKLEMFHRSCJLJKUHPNMBBNNVVRKRHUTDJUKANJHBTPDFSVDEVU SIDE 121212122121212121111111112212122222112222111221112112212112212212 DIRECTION IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIOOOOOOOIOOIOOIOOIOOOOIOOIIOOIIO changed: 1 0 1 step 79 100001100110100100011011011011111101001110011011011010100110111001 fail ^ SLOT BAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBAABBAAAAAAAAAAAAAABBBBBBBBAB LETTER ALPSLFMDEEMCBFRSPKLEMFHRSCJLJKUHPNMBBNNVVRKRHUTDJUKANJHBTPDFSVDEVU SIDE 121212122121212121111111112212122222112222111221112112212112212212 DIRECTION IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIOOOOOOOIOOIOOIOOIOOOOIOOIIOOIIO changed: 0 1 0 step 80 100001100110100100011011011011011101011100011011011010100110111001 fail ^ SLOT BAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBAABBAAAAAAAAAAAAAABBBBBBBBAB LETTER ALPSLFMDEEMCBFRSPKLEMFHRSCJLJKUHPNMBBNNVVRKRHUTDJUKANJHBTPDFSVDEVU SIDE 121212122121212121111111112212122222112222111221112112212112212212 DIRECTION IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIOOOOOOOIOOIOOIOOIOOOOIOOIIOOIIO changed: 1 0 1 step 81 100001100110100100011011011011011111001110011011011010100110111001 fail ^ SLOT BAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBAABBAAAAAAAAAAAAAABBBBBBBBAB LETTER ALPSLFMDEEMCBFRSPKLEMFHRSCJLJKUHPNMBBNNVVRKRHUTDJUKANJHBTPDFSVDEVU SIDE 121212122121212121111111112212122222112222111221112112212112212212 DIRECTION IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIOOOOOOOIOOIOOIOOIOOOOIOOIIOOIIO changed: 0 1 0 step 82 100001100110100100011011011011011101011100011011011010100110111001 fail ^ test 68: *** FAIL *************************** 10 steps failed SLOT BAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBAABBAAAAAAAAAAAAAABBBBBBBBAB LETTER ALPSLFMDEEMCBFRSPKLEMFHRSCJLJKUHPNMBBNNVVRKRHUTDJUKANJHBTPDFSVDEVU SIDE 121212122121212121111111112212122222112222111221112112212112212212 DIRECTION IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIOOOOOOOIOOIOOIOOIOOOOIOOIIOOIIO this fail O O all fails O O was hi 111111111111111111111111111111111111111111111111111111111111111 1 rising ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ ^^^^^^^^^^^^^^^^^^^^ ^^ falling vvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvv vvvvvvvvvvvvvvvvvvvv vv was lo 00000000000000000000000000000000000000 00000000000000000000 0000 total fails 68, total passes 0 space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C toggle comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit step 1 100000000000000000000000000000000001111100011011011010100110111001 step 2 100000000000000000000000000000000001111100100011011010100110111001 step 3 100000000000000000000000000000000001111100000011011010100110111001 step 4 100000000000000000000000000000000001111100000100011010100110111001 step 5 100000000000000000000000000000000001111100000000011010100110111001 step 6 100000000000000000000000000000000001111100000000100010100110111001 step 7 100000000000000000000000000000000001111100000000000010100110111001 step 8 100000000000000000000000000000000001111100000000000101010110111001 step 9 100000000000000000000000000000000001111100000000000001010110111001 step 10 100000000000000000000000000000000001111100000000000001011000111001 step 11 100000000000000000000000000000000001111100000000000001010000111001 step 12 100000000000000000000000000000000001111100000000000001010001100001 step 13 100000000000000000000000000000000001111100000000000001010000100001 step 14 100000000000000000000000000000000001111100000000000001010000100001 step 15 100000000000010000000000000000000000111101000000000001010000100001 step 16 100000000000010010000000000000000000110111000000000001010000100001 step 17 100000000000010010000000000000000000110111111000000001010000100001 step 18 100000000000010010000000000000000000110111011000000001010000100001 step 19 100000000000010010000000000000000000110111011111000001010000100001 step 20 100000000000010010000000000000000000110111011011000001010000100001 step 21 100000000000010010000000000000000000110111011011111001010000100001 step 22 100000000000010010000000000000000000110111011011011001010000100001 step 23 100000000000010010000000000000000000110111011011011110100000100001 step 24 100000000000010010000000000000000000110111011011011010100000100001 step 25 100000000000010010000000000000000000110111011011011010101110100001 step 26 100000000000010010000000000000000000110111011011011010100110100001 step 27 100000000000010010000000000000000000110111011011011010100111111001 step 28 100000000000010010000000000000000000110111011011011010100110111001 step 29 100000000000000010000000000000000001110110011011011010100110111001 step 30 100000000000000000000000000000000001111100011011011010100110111001 step 31 100000000000000000000000000000000001111100011011011010100110111001 step 32 100001000000000000000000000000000001111100011011011010100110111001 step 33 100001100000000000000000000000000001111100011011011010100110111001 step 34 100001100100000000000000000000000001111100011011011010100110111001 step 35 100001100110000000000000000000000001111100011011011010100110111001 step 36 100001100110100000000000000000000001111100011011011010100110111001 step 37 100001100110100100000000000000000001111100011011011010100110111001 step 38 100001100110100100010000000000000001111100011011011010100110111001 step 39 100001100110100100011000000000000001111100011011011010100110111001 step 40 100001100110100100011010000000000001111100011011011010100110111001 step 41 100001100110100100011011000000000001111100011011011010100110111001 step 42 100001100110100100011011010000000001111100011011011010100110111001 step 43 100001100110100100011011011000000001111100011011011010100110111001 step 44 100001100110100100011011011010000001111100011011011010100110111001 step 45 100001100110100100011011011011000001111100011011011010100110111001 step 46 100001100110100100011011011011010001111100011011011010100110111001 step 47 100001100110100100011011011011011001111100011011011010100110111001 step 48 100001100110100100011011011011011101111100011011011010100110111001 step 49 110001100110100100011011011011011100110111011011011010100110111001 step 50 100001100110100100011011011011011101111100011011011010100110111001 step 51 101001100110100100011011011011011100110111011011011010100110111001 step 52 100001100110100100011011011011011101111100011011011010100110111001 step 53 100101100110100100011011011011011100110111011011011010100110111001 step 54 100001100110100100011011011011011101111100011011011010100110111001 step 55 100011100110100100011011011011011100110111011011011010100110111001 step 56 100001100110100100011011011011011101111100011011011010100110111001 step 57 100001110110100100011011011011011100110111011011011010100110111001 step 58 100001100110100100011011011011011101111100011011011010100110111001 step 59 100001101110100100011011011011011100110111011011011010100110111001 step 60 100001100110100100011011011011011101111100011011011010100110111001 step 61 100001100111100100011011011011011100111101011011011010100110111001 step 62 100001100110100100011011011011011101111100011011011010100110111001 step 63 100001100110110100011011011011011100111101011011011010100110111001 step 64 100001100110100100011011011011011101111100011011011010100110111001 step 65 100001100110101100011011011011011101110110011011011010100110111001 step 66 100001100110100100011011011011011101111100011011011010100110111001 step 67 100001100110100110011011011011011101110110011011011010100110111001 step 68 100001100110100100011011011011011101111100011011011010100110111001 step 69 100001100110100101011011011011011101001111011011011010100110111001 SLOT BAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBAABBAAAAAAAAAAAAAABBBBBBBBAB LETTER ALPSLFMDEEMCBFRSPKLEMFHRSCJLJKUHPNMBBNNVVRKRHUTDJUKANJHBTPDFSVDEVU SIDE 121212122121212121111111112212122222112222111221112112212112212212 DIRECTION IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIOOOOOOOIOOIOOIOOIOOOOIOOIIOOIIO changed: 0 1 00 step 70 100001100110100100011011011011011101011100011011011010100110111001 fail ^ step 71 100001100110100100111011011011011101001111011011011010100110111001 SLOT BAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBAABBAAAAAAAAAAAAAABBBBBBBBAB LETTER ALPSLFMDEEMCBFRSPKLEMFHRSCJLJKUHPNMBBNNVVRKRHUTDJUKANJHBTPDFSVDEVU SIDE 121212122121212121111111112212122222112222111221112112212112212212 DIRECTION IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIOOOOOOOIOOIOOIOOIOOOOIOOIIOOIIO changed: 0 1 00 step 72 100001100110100100011011011011011101011100011011011010100110111001 fail ^ step 73 100001100110100100011111011011011101001111011011011010100110111001 SLOT BAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBAABBAAAAAAAAAAAAAABBBBBBBBAB LETTER ALPSLFMDEEMCBFRSPKLEMFHRSCJLJKUHPNMBBNNVVRKRHUTDJUKANJHBTPDFSVDEVU SIDE 121212122121212121111111112212122222112222111221112112212112212212 DIRECTION IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIOOOOOOOIOOIOOIOOIOOOOIOOIIOOIIO changed: 0 1 00 step 74 100001100110100100011011011011011101011100011011011010100110111001 fail ^ step 75 100001100110100100011011111011011101001111011011011010100110111001 SLOT BAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBAABBAAAAAAAAAAAAAABBBBBBBBAB LETTER ALPSLFMDEEMCBFRSPKLEMFHRSCJLJKUHPNMBBNNVVRKRHUTDJUKANJHBTPDFSVDEVU SIDE 121212122121212121111111112212122222112222111221112112212112212212 DIRECTION IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIOOOOOOOIOOIOOIOOIOOOOIOOIIOOIIO changed: 0 1 00 step 76 100001100110100100011011011011011101011100011011011010100110111001 fail ^ SLOT BAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBAABBAAAAAAAAAAAAAABBBBBBBBAB LETTER ALPSLFMDEEMCBFRSPKLEMFHRSCJLJKUHPNMBBNNVVRKRHUTDJUKANJHBTPDFSVDEVU SIDE 121212122121212121111111112212122222112222111221112112212112212212 DIRECTION IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIOOOOOOOIOOIOOIOOIOOOOIOOIIOOIIO changed: 1 0 1 step 77 100001100110100100011011011111011101001110011011011010100110111001 fail ^ SLOT BAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBAABBAAAAAAAAAAAAAABBBBBBBBAB LETTER ALPSLFMDEEMCBFRSPKLEMFHRSCJLJKUHPNMBBNNVVRKRHUTDJUKANJHBTPDFSVDEVU SIDE 121212122121212121111111112212122222112222111221112112212112212212 DIRECTION IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIOOOOOOOIOOIOOIOOIOOOOIOOIIOOIIO changed: 0 1 0 step 78 100001100110100100011011011011011101011100011011011010100110111001 fail ^ SLOT BAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBAABBAAAAAAAAAAAAAABBBBBBBBAB LETTER ALPSLFMDEEMCBFRSPKLEMFHRSCJLJKUHPNMBBNNVVRKRHUTDJUKANJHBTPDFSVDEVU SIDE 121212122121212121111111112212122222112222111221112112212112212212 DIRECTION IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIOOOOOOOIOOIOOIOOIOOOOIOOIIOOIIO changed: 1 0 1 step 79 100001100110100100011011011011111101001110011011011010100110111001 fail ^ SLOT BAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBAABBAAAAAAAAAAAAAABBBBBBBBAB LETTER ALPSLFMDEEMCBFRSPKLEMFHRSCJLJKUHPNMBBNNVVRKRHUTDJUKANJHBTPDFSVDEVU SIDE 121212122121212121111111112212122222112222111221112112212112212212 DIRECTION IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIOOOOOOOIOOIOOIOOIOOOOIOOIIOOIIO changed: 0 1 0 step 80 100001100110100100011011011011011101011100011011011010100110111001 fail ^ SLOT BAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBAABBAAAAAAAAAAAAAABBBBBBBBAB LETTER ALPSLFMDEEMCBFRSPKLEMFHRSCJLJKUHPNMBBNNVVRKRHUTDJUKANJHBTPDFSVDEVU SIDE 121212122121212121111111112212122222112222111221112112212112212212 DIRECTION IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIOOOOOOOIOOIOOIOOIOOOOIOOIIOOIIO changed: 1 0 1 step 81 100001100110100100011011011011011111001110011011011010100110111001 fail ^ SLOT BAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBAABBAAAAAAAAAAAAAABBBBBBBBAB LETTER ALPSLFMDEEMCBFRSPKLEMFHRSCJLJKUHPNMBBNNVVRKRHUTDJUKANJHBTPDFSVDEVU SIDE 121212122121212121111111112212122222112222111221112112212112212212 DIRECTION IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIOOOOOOOIOOIOOIOOIOOOOIOOIIOOIIO changed: 0 1 0 step 82 100001100110100100011011011011011101011100011011011010100110111001 fail ^ test 69: *** FAIL *************************** 10 steps failed SLOT BAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBAABBAAAAAAAAAAAAAABBBBBBBBAB LETTER ALPSLFMDEEMCBFRSPKLEMFHRSCJLJKUHPNMBBNNVVRKRHUTDJUKANJHBTPDFSVDEVU SIDE 121212122121212121111111112212122222112222111221112112212112212212 DIRECTION IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIOOOOOOOIOOIOOIOOIOOOOIOOIIOOIIO this fail O O all fails O O was hi 111111111111111111111111111111111111111111111111111111111111111 1 rising ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ ^^^^^^^^^^^^^^^^^^^^ ^^ falling vvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvv vvvvvvvvvvvvvvvvvvvv vv was lo 00000000000000000000000000000000000000 00000000000000000000 0000 total fails 69, total passes 0 space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C toggle comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT BAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBAABBAAAAAAAAAAAAAABBBBBBBBAB LETTER ALPSLFMDEEMCBFRSPKLEMFHRSCJLJKUHPNMBBNNVVRKRHUTDJUKANJHBTPDFSVDEVU SIDE 121212122121212121111111112212122222112222111221112112212112212212 DIRECTION IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIOOOOOOOIOOIOOIOOIOOOOIOOIIOOIIO all fails O O was lo 00000000000000000000000000000000000000 00000000000000000000 0000 falling vvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvv vvvvvvvvvvvvvvvvvvvv vv rising ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ ^^^^^^^^^^^^^^^^^^^^ ^^ was hi 111111111111111111111111111111111111111111111111111111111111111 1 total fails 69, total passes 0 Main menu Thu Aug 20 15:35:17 2015 test file is: tests\m222.tst delay is: 0 trigger is: 1 1 read test file 2 set test delay 3 set test trigger 4 run test 5 output loading test 8 diags 9 exit UUT power is okay Thu Aug 20 15:35:45 2015 space single step O run once (one test, all steps) F run, stop on fail G go (run tests N run, stop on fail, no print S scope (run, no print) C toggle comment printout + increase speed (less delay) - decrease speed (more delay)(slower) Q quit test scope (run, no print) FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C toggle comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit step 5 100000000000000000000000000000000001111100000000011010100110111001 step 6 100000000000000000000000000000000001111100000000100010100110111001 step 7 100000000000000000000000000000000001111100000000000010100110111001 step 8 100000000000000000000000000000000001111100000000000101010110111001 step 9 100000000000000000000000000000000001111100000000000001010110111001 step 10 100000000000000000000000000000000001111100000000000001011000111001 step 11 100000000000000000000000000000000001111100000000000001010000111001 step 12 100000000000000000000000000000000001111100000000000001010001100001 step 13 100000000000000000000000000000000001111100000000000001010000100001 step 14 100000000000000000000000000000000001111100000000000001010000100001 step 15 100000000000010000000000000000000000111101000000000001010000100001 step 16 100000000000010010000000000000000000110111000000000001010000100001 step 17 100000000000010010000000000000000000110111111000000001010000100001 step 18 100000000000010010000000000000000000110111011000000001010000100001 step 19 100000000000010010000000000000000000110111011111000001010000100001 step 20 100000000000010010000000000000000000110111011011000001010000100001 step 21 100000000000010010000000000000000000110111011011111001010000100001 step 22 100000000000010010000000000000000000110111011011011001010000100001 step 23 100000000000010010000000000000000000110111011011011110100000100001 step 24 100000000000010010000000000000000000110111011011011010100000100001 step 25 100000000000010010000000000000000000110111011011011010101110100001 step 26 100000000000010010000000000000000000110111011011011010100110100001 step 27 100000000000010010000000000000000000110111011011011010100111111001 step 28 100000000000010010000000000000000000110111011011011010100110111001 step 29 100000000000000010000000000000000001110110011011011010100110111001 step 30 100000000000000000000000000000000001111100011011011010100110111001 step 31 100000000000000000000000000000000001111100011011011010100110111001 step 32 100001000000000000000000000000000001111100011011011010100110111001 step 33 100001100000000000000000000000000001111100011011011010100110111001 step 34 100001100100000000000000000000000001111100011011011010100110111001 step 35 100001100110000000000000000000000001111100011011011010100110111001 step 36 100001100110100000000000000000000001111100011011011010100110111001 step 37 100001100110100100000000000000000001111100011011011010100110111001 step 38 100001100110100100010000000000000001111100011011011010100110111001 step 39 100001100110100100011000000000000001111100011011011010100110111001 step 40 100001100110100100011010000000000001111100011011011010100110111001 step 41 100001100110100100011011000000000001111100011011011010100110111001 step 42 100001100110100100011011010000000001111100011011011010100110111001 step 43 100001100110100100011011011000000001111100011011011010100110111001 step 44 100001100110100100011011011010000001111100011011011010100110111001 step 45 100001100110100100011011011011000001111100011011011010100110111001 SLOT BAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBAABBAAAAAAAAAAAAAABBBBBBBBAB LETTER ALPSLFMDEEMCBFRSPKLEMFHRSCJLJKUHPNMBBNNVVRKRHUTDJUKANJHBTPDFSVDEVU SIDE 121212122121212121111111112212122222112222111221112112212112212212 DIRECTION IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIOOOOOOOIOOIOOIOOIOOOOIOOIIOOIIO changed: 1 0 1 step 46 100001100110100100011011011011010001011101011011011010100110111001 fail ^ ^ SLOT BAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBAABBAAAAAAAAAAAAAABBBBBBBBAB LETTER ALPSLFMDEEMCBFRSPKLEMFHRSCJLJKUHPNMBBNNVVRKRHUTDJUKANJHBTPDFSVDEVU SIDE 121212122121212121111111112212122222112222111221112112212112212212 DIRECTION IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIOOOOOOOIOOIOOIOOIOOOOIOOIIOOIIO changed: 1 0 1 step 47 100001100110100100011011011011011001001111011011011010100110111001 fail ^^ ^^ SLOT BAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBAABBAAAAAAAAAAAAAABBBBBBBBAB LETTER ALPSLFMDEEMCBFRSPKLEMFHRSCJLJKUHPNMBBNNVVRKRHUTDJUKANJHBTPDFSVDEVU SIDE 121212122121212121111111112212122222112222111221112112212112212212 DIRECTION IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIOOOOOOOIOOIOOIOOIOOOOIOOIIOOIIO changed: 1 step 48 100001100110100100011011011011011101001111011011011010100110111001 fail ^^ ^^ SLOT BAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBAABBAAAAAAAAAAAAAABBBBBBBBAB LETTER ALPSLFMDEEMCBFRSPKLEMFHRSCJLJKUHPNMBBNNVVRKRHUTDJUKANJHBTPDFSVDEVU SIDE 121212122121212121111111112212122222112222111221112112212112212212 DIRECTION IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIOOOOOOOIOOIOOIOOIOOOOIOOIIOOIIO changed: 1 0 00 0 step 49 110001100110100100011011011011011100000010011011011010100110111001 fail ^^ ^ ^ SLOT BAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBAABBAAAAAAAAAAAAAABBBBBBBBAB LETTER ALPSLFMDEEMCBFRSPKLEMFHRSCJLJKUHPNMBBNNVVRKRHUTDJUKANJHBTPDFSVDEVU SIDE 121212122121212121111111112212122222112222111221112112212112212212 DIRECTION IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIOOOOOOOIOOIOOIOOIOOOOIOOIIOOIIO changed: 0 1 11 1 step 50 100001100110100100011011011011011101001111011011011010100110111001 fail ^^ ^^ SLOT BAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBAABBAAAAAAAAAAAAAABBBBBBBBAB LETTER ALPSLFMDEEMCBFRSPKLEMFHRSCJLJKUHPNMBBNNVVRKRHUTDJUKANJHBTPDFSVDEVU SIDE 121212122121212121111111112212122222112222111221112112212112212212 DIRECTION IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIOOOOOOOIOOIOOIOOIOOOOIOOIIOOIIO changed: 1 0 00 0 step 51 101001100110100100011011011011011100000010011011011010100110111001 fail ^^ ^ ^ SLOT BAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBAABBAAAAAAAAAAAAAABBBBBBBBAB LETTER ALPSLFMDEEMCBFRSPKLEMFHRSCJLJKUHPNMBBNNVVRKRHUTDJUKANJHBTPDFSVDEVU SIDE 121212122121212121111111112212122222112222111221112112212112212212 DIRECTION IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIOOOOOOOIOOIOOIOOIOOOOIOOIIOOIIO changed: 0 1 11 1 step 52 100001100110100100011011011011011101001111011011011010100110111001 fail ^^ ^^ SLOT BAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBAABBAAAAAAAAAAAAAABBBBBBBBAB LETTER ALPSLFMDEEMCBFRSPKLEMFHRSCJLJKUHPNMBBNNVVRKRHUTDJUKANJHBTPDFSVDEVU SIDE 121212122121212121111111112212122222112222111221112112212112212212 DIRECTION IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIOOOOOOOIOOIOOIOOIOOOOIOOIIOOIIO changed: 1 0 00 0 step 53 100101100110100100011011011011011100000010011011011010100110111001 fail ^^ ^ ^ SLOT BAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBAABBAAAAAAAAAAAAAABBBBBBBBAB LETTER ALPSLFMDEEMCBFRSPKLEMFHRSCJLJKUHPNMBBNNVVRKRHUTDJUKANJHBTPDFSVDEVU SIDE 121212122121212121111111112212122222112222111221112112212112212212 DIRECTION IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIOOOOOOOIOOIOOIOOIOOOOIOOIIOOIIO changed: 0 1 11 1 step 54 100001100110100100011011011011011101001111011011011010100110111001 fail ^^ ^^ SLOT BAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBAABBAAAAAAAAAAAAAABBBBBBBBAB LETTER ALPSLFMDEEMCBFRSPKLEMFHRSCJLJKUHPNMBBNNVVRKRHUTDJUKANJHBTPDFSVDEVU SIDE 121212122121212121111111112212122222112222111221112112212112212212 DIRECTION IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIOOOOOOOIOOIOOIOOIOOOOIOOIIOOIIO changed: 1 0 00 0 step 55 100011100110100100011011011011011100000010011011011010100110111001 fail ^^ ^ ^ SLOT BAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBAABBAAAAAAAAAAAAAABBBBBBBBAB LETTER ALPSLFMDEEMCBFRSPKLEMFHRSCJLJKUHPNMBBNNVVRKRHUTDJUKANJHBTPDFSVDEVU SIDE 121212122121212121111111112212122222112222111221112112212112212212 DIRECTION IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIOOOOOOOIOOIOOIOOIOOOOIOOIIOOIIO changed: 0 1 11 1 step 56 100001100110100100011011011011011101001111011011011010100110111001 fail ^^ ^^ SLOT BAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBAABBAAAAAAAAAAAAAABBBBBBBBAB LETTER ALPSLFMDEEMCBFRSPKLEMFHRSCJLJKUHPNMBBNNVVRKRHUTDJUKANJHBTPDFSVDEVU SIDE 121212122121212121111111112212122222112222111221112112212112212212 DIRECTION IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIOOOOOOOIOOIOOIOOIOOOOIOOIIOOIIO changed: 1 0 00 0 step 57 100001110110100100011011011011011100000010011011011010100110111001 fail ^^ ^ ^ SLOT BAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBAABBAAAAAAAAAAAAAABBBBBBBBAB LETTER ALPSLFMDEEMCBFRSPKLEMFHRSCJLJKUHPNMBBNNVVRKRHUTDJUKANJHBTPDFSVDEVU SIDE 121212122121212121111111112212122222112222111221112112212112212212 DIRECTION IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIOOOOOOOIOOIOOIOOIOOOOIOOIIOOIIO changed: 0 1 11 1 step 58 100001100110100100011011011011011101001111011011011010100110111001 fail ^^ ^^ SLOT BAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBAABBAAAAAAAAAAAAAABBBBBBBBAB LETTER ALPSLFMDEEMCBFRSPKLEMFHRSCJLJKUHPNMBBNNVVRKRHUTDJUKANJHBTPDFSVDEVU SIDE 121212122121212121111111112212122222112222111221112112212112212212 DIRECTION IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIOOOOOOOIOOIOOIOOIOOOOIOOIIOOIIO changed: 1 0 00 0 step 59 100001101110100100011011011011011100000010011011011010100110111001 fail ^^ ^ ^ SLOT BAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBAABBAAAAAAAAAAAAAABBBBBBBBAB LETTER ALPSLFMDEEMCBFRSPKLEMFHRSCJLJKUHPNMBBNNVVRKRHUTDJUKANJHBTPDFSVDEVU SIDE 121212122121212121111111112212122222112222111221112112212112212212 DIRECTION IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIOOOOOOOIOOIOOIOOIOOOOIOOIIOOIIO changed: 0 1 11 1 step 60 100001100110100100011011011011011101001111011011011010100110111001 fail ^^ ^^ SLOT BAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBAABBAAAAAAAAAAAAAABBBBBBBBAB LETTER ALPSLFMDEEMCBFRSPKLEMFHRSCJLJKUHPNMBBNNVVRKRHUTDJUKANJHBTPDFSVDEVU SIDE 121212122121212121111111112212122222112222111221112112212112212212 DIRECTION IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIOOOOOOOIOOIOOIOOIOOOOIOOIIOOIIO changed: 1 0 000 step 61 100001100111100100011011011011011100001000011011011010100110111001 fail ^^ ^ ^ SLOT BAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBAABBAAAAAAAAAAAAAABBBBBBBBAB LETTER ALPSLFMDEEMCBFRSPKLEMFHRSCJLJKUHPNMBBNNVVRKRHUTDJUKANJHBTPDFSVDEVU SIDE 121212122121212121111111112212122222112222111221112112212112212212 DIRECTION IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIOOOOOOOIOOIOOIOOIOOOOIOOIIOOIIO changed: 0 1 111 step 62 100001100110100100011011011011011101001111011011011010100110111001 fail ^^ ^^ SLOT BAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBAABBAAAAAAAAAAAAAABBBBBBBBAB LETTER ALPSLFMDEEMCBFRSPKLEMFHRSCJLJKUHPNMBBNNVVRKRHUTDJUKANJHBTPDFSVDEVU SIDE 121212122121212121111111112212122222112222111221112112212112212212 DIRECTION IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIOOOOOOOIOOIOOIOOIOOOOIOOIIOOIIO changed: 1 0 000 step 63 100001100110110100011011011011011100001000011011011010100110111001 fail ^^ ^ ^ SLOT BAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBAABBAAAAAAAAAAAAAABBBBBBBBAB LETTER ALPSLFMDEEMCBFRSPKLEMFHRSCJLJKUHPNMBBNNVVRKRHUTDJUKANJHBTPDFSVDEVU SIDE 121212122121212121111111112212122222112222111221112112212112212212 DIRECTION IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIOOOOOOOIOOIOOIOOIOOOOIOOIIOOIIO changed: 0 1 111 step 64 100001100110100100011011011011011101001111011011011010100110111001 fail ^^ ^^ SLOT BAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBAABBAAAAAAAAAAAAAABBBBBBBBAB LETTER ALPSLFMDEEMCBFRSPKLEMFHRSCJLJKUHPNMBBNNVVRKRHUTDJUKANJHBTPDFSVDEVU SIDE 121212122121212121111111112212122222112222111221112112212112212212 DIRECTION IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIOOOOOOOIOOIOOIOOIOOOOIOOIIOOIIO changed: 1 000 step 65 100001100110101100011011011011011101000001011011011010100110111001 fail ^^ ^^^ SLOT BAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBAABBAAAAAAAAAAAAAABBBBBBBBAB LETTER ALPSLFMDEEMCBFRSPKLEMFHRSCJLJKUHPNMBBNNVVRKRHUTDJUKANJHBTPDFSVDEVU SIDE 121212122121212121111111112212122222112222111221112112212112212212 DIRECTION IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIOOOOOOOIOOIOOIOOIOOOOIOOIIOOIIO changed: 0 111 step 66 100001100110100100011011011011011101001111011011011010100110111001 fail ^^ ^^ SLOT BAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBAABBAAAAAAAAAAAAAABBBBBBBBAB LETTER ALPSLFMDEEMCBFRSPKLEMFHRSCJLJKUHPNMBBNNVVRKRHUTDJUKANJHBTPDFSVDEVU SIDE 121212122121212121111111112212122222112222111221112112212112212212 DIRECTION IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIOOOOOOOIOOIOOIOOIOOOOIOOIIOOIIO changed: 1 000 step 67 100001100110100110011011011011011101000001011011011010100110111001 fail ^^ ^^^ SLOT BAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBAABBAAAAAAAAAAAAAABBBBBBBBAB LETTER ALPSLFMDEEMCBFRSPKLEMFHRSCJLJKUHPNMBBNNVVRKRHUTDJUKANJHBTPDFSVDEVU SIDE 121212122121212121111111112212122222112222111221112112212112212212 DIRECTION IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIOOOOOOOIOOIOOIOOIOOOOIOOIIOOIIO changed: 0 111 step 68 100001100110100100011011011011011101001111011011011010100110111001 fail ^^ ^^ step 69 100001100110100101011011011011011101001111011011011010100110111001 SLOT BAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBAABBAAAAAAAAAAAAAABBBBBBBBAB LETTER ALPSLFMDEEMCBFRSPKLEMFHRSCJLJKUHPNMBBNNVVRKRHUTDJUKANJHBTPDFSVDEVU SIDE 121212122121212121111111112212122222112222111221112112212112212212 DIRECTION IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIOOOOOOOIOOIOOIOOIOOOOIOOIIOOIIO changed: 0 step 70 100001100110100100011011011011011101001111011011011010100110111001 fail ^^ ^^ step 71 100001100110100100111011011011011101001111011011011010100110111001 SLOT BAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBAABBAAAAAAAAAAAAAABBBBBBBBAB LETTER ALPSLFMDEEMCBFRSPKLEMFHRSCJLJKUHPNMBBNNVVRKRHUTDJUKANJHBTPDFSVDEVU SIDE 121212122121212121111111112212122222112222111221112112212112212212 DIRECTION IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIOOOOOOOIOOIOOIOOIOOOOIOOIIOOIIO changed: 0 step 72 100001100110100100011011011011011101001111011011011010100110111001 fail ^^ ^^ step 73 100001100110100100011111011011011101001111011011011010100110111001 SLOT BAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBAABBAAAAAAAAAAAAAABBBBBBBBAB LETTER ALPSLFMDEEMCBFRSPKLEMFHRSCJLJKUHPNMBBNNVVRKRHUTDJUKANJHBTPDFSVDEVU SIDE 121212122121212121111111112212122222112222111221112112212112212212 DIRECTION IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIOOOOOOOIOOIOOIOOIOOOOIOOIIOOIIO changed: 0 step 74 100001100110100100011011011011011101001111011011011010100110111001 fail ^^ ^^ step 75 100001100110100100011011111011011101001111011011011010100110111001 SLOT BAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBAABBAAAAAAAAAAAAAABBBBBBBBAB LETTER ALPSLFMDEEMCBFRSPKLEMFHRSCJLJKUHPNMBBNNVVRKRHUTDJUKANJHBTPDFSVDEVU SIDE 121212122121212121111111112212122222112222111221112112212112212212 DIRECTION IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIOOOOOOOIOOIOOIOOIOOOOIOOIIOOIIO changed: 0 step 76 100001100110100100011011011011011101001111011011011010100110111001 fail ^^ ^^ step 77 100001100110100100011011011111011101001111011011011010100110111001 SLOT BAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBAABBAAAAAAAAAAAAAABBBBBBBBAB LETTER ALPSLFMDEEMCBFRSPKLEMFHRSCJLJKUHPNMBBNNVVRKRHUTDJUKANJHBTPDFSVDEVU SIDE 121212122121212121111111112212122222112222111221112112212112212212 DIRECTION IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIOOOOOOOIOOIOOIOOIOOOOIOOIIOOIIO changed: 0 step 78 100001100110100100011011011011011101001111011011011010100110111001 fail ^^ ^^ step 79 100001100110100100011011011011111101001111011011011010100110111001 SLOT BAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBAABBAAAAAAAAAAAAAABBBBBBBBAB LETTER ALPSLFMDEEMCBFRSPKLEMFHRSCJLJKUHPNMBBNNVVRKRHUTDJUKANJHBTPDFSVDEVU SIDE 121212122121212121111111112212122222112222111221112112212112212212 DIRECTION IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIOOOOOOOIOOIOOIOOIOOOOIOOIIOOIIO changed: 0 step 80 100001100110100100011011011011011101001111011011011010100110111001 fail ^^ ^^ SLOT BAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBAABBAAAAAAAAAAAAAABBBBBBBBAB LETTER ALPSLFMDEEMCBFRSPKLEMFHRSCJLJKUHPNMBBNNVVRKRHUTDJUKANJHBTPDFSVDEVU SIDE 121212122121212121111111112212122222112222111221112112212112212212 DIRECTION IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIOOOOOOOIOOIOOIOOIOOOOIOOIIOOIIO changed: 1 step 81 100001100110100100011011011011011111001111011011011010100110111001 fail ^ ^ SLOT BAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBAABBAAAAAAAAAAAAAABBBBBBBBAB LETTER ALPSLFMDEEMCBFRSPKLEMFHRSCJLJKUHPNMBBNNVVRKRHUTDJUKANJHBTPDFSVDEVU SIDE 121212122121212121111111112212122222112222111221112112212112212212 DIRECTION IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIOOOOOOOIOOIOOIOOIOOOOIOOIIOOIIO changed: 0 step 82 100001100110100100011011011011011101001111011011011010100110111001 fail ^^ ^^ test 54: *** FAIL *************************** 31 steps failed SLOT BAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBAABBAAAAAAAAAAAAAABBBBBBBBAB LETTER ALPSLFMDEEMCBFRSPKLEMFHRSCJLJKUHPNMBBNNVVRKRHUTDJUKANJHBTPDFSVDEVU SIDE 121212122121212121111111112212122222112222111221112112212112212212 DIRECTION IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIOOOOOOOIOOIOOIOOIOOOOIOOIIOOIIO this fail OO OOO all fails OO OOO was hi 111111111111111111111111111111111111111111111111111111111111111 1 rising ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ ^^ falling vvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvv vv was lo 00000000000000000000000000000000000000000000000000000000000 0000 total fails 54, total passes 0 space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C toggle comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit step 1 100000000000000000000000000000000001111100011011011010100110111001 step 2 100000000000000000000000000000000001111100100011011010100110111001 step 3 100000000000000000000000000000000001111100000011011010100110111001 step 4 100000000000000000000000000000000001111100000100011010100110111001 step 5 100000000000000000000000000000000001111100000000011010100110111001 step 6 100000000000000000000000000000000001111100000000100010100110111001 step 7 100000000000000000000000000000000001111100000000000010100110111001 step 8 100000000000000000000000000000000001111100000000000101010110111001 step 9 100000000000000000000000000000000001111100000000000001010110111001 step 10 100000000000000000000000000000000001111100000000000001011000111001 step 11 100000000000000000000000000000000001111100000000000001010000111001 step 12 100000000000000000000000000000000001111100000000000001010001100001 step 13 100000000000000000000000000000000001111100000000000001010000100001 step 14 100000000000000000000000000000000001111100000000000001010000100001 step 15 100000000000010000000000000000000000111101000000000001010000100001 step 16 100000000000010010000000000000000000110111000000000001010000100001 step 17 100000000000010010000000000000000000110111111000000001010000100001 step 18 100000000000010010000000000000000000110111011000000001010000100001 step 19 100000000000010010000000000000000000110111011111000001010000100001 step 20 100000000000010010000000000000000000110111011011000001010000100001 step 21 100000000000010010000000000000000000110111011011111001010000100001 step 22 100000000000010010000000000000000000110111011011011001010000100001 step 23 100000000000010010000000000000000000110111011011011110100000100001 step 24 100000000000010010000000000000000000110111011011011010100000100001 step 25 100000000000010010000000000000000000110111011011011010101110100001 step 26 100000000000010010000000000000000000110111011011011010100110100001 step 27 100000000000010010000000000000000000110111011011011010100111111001 step 28 100000000000010010000000000000000000110111011011011010100110111001 step 29 100000000000000010000000000000000001110110011011011010100110111001 step 30 100000000000000000000000000000000001111100011011011010100110111001 step 31 100000000000000000000000000000000001111100011011011010100110111001 step 32 100001000000000000000000000000000001111100011011011010100110111001 step 33 100001100000000000000000000000000001111100011011011010100110111001 step 34 100001100100000000000000000000000001111100011011011010100110111001 step 35 100001100110000000000000000000000001111100011011011010100110111001 step 36 100001100110100000000000000000000001111100011011011010100110111001 step 37 100001100110100100000000000000000001111100011011011010100110111001 step 38 100001100110100100010000000000000001111100011011011010100110111001 step 39 100001100110100100011000000000000001111100011011011010100110111001 step 40 100001100110100100011010000000000001111100011011011010100110111001 step 41 100001100110100100011011000000000001111100011011011010100110111001 step 42 100001100110100100011011010000000001111100011011011010100110111001 step 43 100001100110100100011011011000000001111100011011011010100110111001 step 44 100001100110100100011011011010000001111100011011011010100110111001 step 45 100001100110100100011011011011000001111100011011011010100110111001 SLOT BAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBAABBAAAAAAAAAAAAAABBBBBBBBAB LETTER ALPSLFMDEEMCBFRSPKLEMFHRSCJLJKUHPNMBBNNVVRKRHUTDJUKANJHBTPDFSVDEVU SIDE 121212122121212121111111112212122222112222111221112112212112212212 DIRECTION IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIOOOOOOOIOOIOOIOOIOOOOIOOIIOOIIO changed: 1 0 1 step 46 100001100110100100011011011011010001011101011011011010100110111001 fail ^ ^ SLOT BAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBAABBAAAAAAAAAAAAAABBBBBBBBAB LETTER ALPSLFMDEEMCBFRSPKLEMFHRSCJLJKUHPNMBBNNVVRKRHUTDJUKANJHBTPDFSVDEVU SIDE 121212122121212121111111112212122222112222111221112112212112212212 DIRECTION IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIOOOOOOOIOOIOOIOOIOOOOIOOIIOOIIO changed: 1 0 1 step 47 100001100110100100011011011011011001001111011011011010100110111001 fail ^^ ^^ SLOT BAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBAABBAAAAAAAAAAAAAABBBBBBBBAB LETTER ALPSLFMDEEMCBFRSPKLEMFHRSCJLJKUHPNMBBNNVVRKRHUTDJUKANJHBTPDFSVDEVU SIDE 121212122121212121111111112212122222112222111221112112212112212212 DIRECTION IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIOOOOOOOIOOIOOIOOIOOOOIOOIIOOIIO changed: 1 step 48 100001100110100100011011011011011101001111011011011010100110111001 fail ^^ ^^ SLOT BAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBAABBAAAAAAAAAAAAAABBBBBBBBAB LETTER ALPSLFMDEEMCBFRSPKLEMFHRSCJLJKUHPNMBBNNVVRKRHUTDJUKANJHBTPDFSVDEVU SIDE 121212122121212121111111112212122222112222111221112112212112212212 DIRECTION IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIOOOOOOOIOOIOOIOOIOOOOIOOIIOOIIO changed: 1 0 00 0 step 49 110001100110100100011011011011011100000010011011011010100110111001 fail ^^ ^ ^ SLOT BAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBAABBAAAAAAAAAAAAAABBBBBBBBAB LETTER ALPSLFMDEEMCBFRSPKLEMFHRSCJLJKUHPNMBBNNVVRKRHUTDJUKANJHBTPDFSVDEVU SIDE 121212122121212121111111112212122222112222111221112112212112212212 DIRECTION IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIOOOOOOOIOOIOOIOOIOOOOIOOIIOOIIO changed: 0 1 11 1 step 50 100001100110100100011011011011011101001111011011011010100110111001 fail ^^ ^^ SLOT BAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBAABBAAAAAAAAAAAAAABBBBBBBBAB LETTER ALPSLFMDEEMCBFRSPKLEMFHRSCJLJKUHPNMBBNNVVRKRHUTDJUKANJHBTPDFSVDEVU SIDE 121212122121212121111111112212122222112222111221112112212112212212 DIRECTION IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIOOOOOOOIOOIOOIOOIOOOOIOOIIOOIIO changed: 1 0 00 0 step 51 101001100110100100011011011011011100000010011011011010100110111001 fail ^^ ^ ^ SLOT BAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBAABBAAAAAAAAAAAAAABBBBBBBBAB LETTER ALPSLFMDEEMCBFRSPKLEMFHRSCJLJKUHPNMBBNNVVRKRHUTDJUKANJHBTPDFSVDEVU SIDE 121212122121212121111111112212122222112222111221112112212112212212 DIRECTION IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIOOOOOOOIOOIOOIOOIOOOOIOOIIOOIIO changed: 0 1 11 1 step 52 100001100110100100011011011011011101001111011011011010100110111001 fail ^^ ^^ SLOT BAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBAABBAAAAAAAAAAAAAABBBBBBBBAB LETTER ALPSLFMDEEMCBFRSPKLEMFHRSCJLJKUHPNMBBNNVVRKRHUTDJUKANJHBTPDFSVDEVU SIDE 121212122121212121111111112212122222112222111221112112212112212212 DIRECTION IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIOOOOOOOIOOIOOIOOIOOOOIOOIIOOIIO changed: 1 0 00 0 step 53 100101100110100100011011011011011100000010011011011010100110111001 fail ^^ ^ ^ SLOT BAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBAABBAAAAAAAAAAAAAABBBBBBBBAB LETTER ALPSLFMDEEMCBFRSPKLEMFHRSCJLJKUHPNMBBNNVVRKRHUTDJUKANJHBTPDFSVDEVU SIDE 121212122121212121111111112212122222112222111221112112212112212212 DIRECTION IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIOOOOOOOIOOIOOIOOIOOOOIOOIIOOIIO changed: 0 1 11 1 step 54 100001100110100100011011011011011101001111011011011010100110111001 fail ^^ ^^ SLOT BAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBAABBAAAAAAAAAAAAAABBBBBBBBAB LETTER ALPSLFMDEEMCBFRSPKLEMFHRSCJLJKUHPNMBBNNVVRKRHUTDJUKANJHBTPDFSVDEVU SIDE 121212122121212121111111112212122222112222111221112112212112212212 DIRECTION IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIOOOOOOOIOOIOOIOOIOOOOIOOIIOOIIO changed: 1 0 00 0 step 55 100011100110100100011011011011011100000010011011011010100110111001 fail ^^ ^ ^ SLOT BAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBAABBAAAAAAAAAAAAAABBBBBBBBAB LETTER ALPSLFMDEEMCBFRSPKLEMFHRSCJLJKUHPNMBBNNVVRKRHUTDJUKANJHBTPDFSVDEVU SIDE 121212122121212121111111112212122222112222111221112112212112212212 DIRECTION IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIOOOOOOOIOOIOOIOOIOOOOIOOIIOOIIO changed: 0 1 11 1 step 56 100001100110100100011011011011011101001111011011011010100110111001 fail ^^ ^^ SLOT BAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBAABBAAAAAAAAAAAAAABBBBBBBBAB LETTER ALPSLFMDEEMCBFRSPKLEMFHRSCJLJKUHPNMBBNNVVRKRHUTDJUKANJHBTPDFSVDEVU SIDE 121212122121212121111111112212122222112222111221112112212112212212 DIRECTION IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIOOOOOOOIOOIOOIOOIOOOOIOOIIOOIIO changed: 1 0 00 0 step 57 100001110110100100011011011011011100000010011011011010100110111001 fail ^^ ^ ^ SLOT BAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBAABBAAAAAAAAAAAAAABBBBBBBBAB LETTER ALPSLFMDEEMCBFRSPKLEMFHRSCJLJKUHPNMBBNNVVRKRHUTDJUKANJHBTPDFSVDEVU SIDE 121212122121212121111111112212122222112222111221112112212112212212 DIRECTION IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIOOOOOOOIOOIOOIOOIOOOOIOOIIOOIIO changed: 0 1 11 1 step 58 100001100110100100011011011011011101001111011011011010100110111001 fail ^^ ^^ SLOT BAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBAABBAAAAAAAAAAAAAABBBBBBBBAB LETTER ALPSLFMDEEMCBFRSPKLEMFHRSCJLJKUHPNMBBNNVVRKRHUTDJUKANJHBTPDFSVDEVU SIDE 121212122121212121111111112212122222112222111221112112212112212212 DIRECTION IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIOOOOOOOIOOIOOIOOIOOOOIOOIIOOIIO changed: 1 0 00 0 step 59 100001101110100100011011011011011100000010011011011010100110111001 fail ^^ ^ ^ SLOT BAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBAABBAAAAAAAAAAAAAABBBBBBBBAB LETTER ALPSLFMDEEMCBFRSPKLEMFHRSCJLJKUHPNMBBNNVVRKRHUTDJUKANJHBTPDFSVDEVU SIDE 121212122121212121111111112212122222112222111221112112212112212212 DIRECTION IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIOOOOOOOIOOIOOIOOIOOOOIOOIIOOIIO changed: 0 1 11 1 step 60 100001100110100100011011011011011101001111011011011010100110111001 fail ^^ ^^ SLOT BAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBAABBAAAAAAAAAAAAAABBBBBBBBAB LETTER ALPSLFMDEEMCBFRSPKLEMFHRSCJLJKUHPNMBBNNVVRKRHUTDJUKANJHBTPDFSVDEVU SIDE 121212122121212121111111112212122222112222111221112112212112212212 DIRECTION IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIOOOOOOOIOOIOOIOOIOOOOIOOIIOOIIO changed: 1 0 000 step 61 100001100111100100011011011011011100001000011011011010100110111001 fail ^^ ^ ^ SLOT BAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBAABBAAAAAAAAAAAAAABBBBBBBBAB LETTER ALPSLFMDEEMCBFRSPKLEMFHRSCJLJKUHPNMBBNNVVRKRHUTDJUKANJHBTPDFSVDEVU SIDE 121212122121212121111111112212122222112222111221112112212112212212 DIRECTION IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIOOOOOOOIOOIOOIOOIOOOOIOOIIOOIIO changed: 0 1 111 step 62 100001100110100100011011011011011101001111011011011010100110111001 fail ^^ ^^ SLOT BAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBAABBAAAAAAAAAAAAAABBBBBBBBAB LETTER ALPSLFMDEEMCBFRSPKLEMFHRSCJLJKUHPNMBBNNVVRKRHUTDJUKANJHBTPDFSVDEVU SIDE 121212122121212121111111112212122222112222111221112112212112212212 DIRECTION IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIOOOOOOOIOOIOOIOOIOOOOIOOIIOOIIO changed: 1 0 000 step 63 100001100110110100011011011011011100001000011011011010100110111001 fail ^^ ^ ^ SLOT BAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBAABBAAAAAAAAAAAAAABBBBBBBBAB LETTER ALPSLFMDEEMCBFRSPKLEMFHRSCJLJKUHPNMBBNNVVRKRHUTDJUKANJHBTPDFSVDEVU SIDE 121212122121212121111111112212122222112222111221112112212112212212 DIRECTION IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIOOOOOOOIOOIOOIOOIOOOOIOOIIOOIIO changed: 0 1 111 step 64 100001100110100100011011011011011101001111011011011010100110111001 fail ^^ ^^ SLOT BAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBAABBAAAAAAAAAAAAAABBBBBBBBAB LETTER ALPSLFMDEEMCBFRSPKLEMFHRSCJLJKUHPNMBBNNVVRKRHUTDJUKANJHBTPDFSVDEVU SIDE 121212122121212121111111112212122222112222111221112112212112212212 DIRECTION IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIOOOOOOOIOOIOOIOOIOOOOIOOIIOOIIO changed: 1 000 step 65 100001100110101100011011011011011101000001011011011010100110111001 fail ^^ ^^^ SLOT BAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBAABBAAAAAAAAAAAAAABBBBBBBBAB LETTER ALPSLFMDEEMCBFRSPKLEMFHRSCJLJKUHPNMBBNNVVRKRHUTDJUKANJHBTPDFSVDEVU SIDE 121212122121212121111111112212122222112222111221112112212112212212 DIRECTION IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIOOOOOOOIOOIOOIOOIOOOOIOOIIOOIIO changed: 0 111 step 66 100001100110100100011011011011011101001111011011011010100110111001 fail ^^ ^^ SLOT BAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBAABBAAAAAAAAAAAAAABBBBBBBBAB LETTER ALPSLFMDEEMCBFRSPKLEMFHRSCJLJKUHPNMBBNNVVRKRHUTDJUKANJHBTPDFSVDEVU SIDE 121212122121212121111111112212122222112222111221112112212112212212 DIRECTION IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIOOOOOOOIOOIOOIOOIOOOOIOOIIOOIIO changed: 1 000 step 67 100001100110100110011011011011011101000001011011011010100110111001 fail ^^ ^^^ SLOT BAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBAABBAAAAAAAAAAAAAABBBBBBBBAB LETTER ALPSLFMDEEMCBFRSPKLEMFHRSCJLJKUHPNMBBNNVVRKRHUTDJUKANJHBTPDFSVDEVU SIDE 121212122121212121111111112212122222112222111221112112212112212212 DIRECTION IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIOOOOOOOIOOIOOIOOIOOOOIOOIIOOIIO changed: 0 111 step 68 100001100110100100011011011011011101001111011011011010100110111001 fail ^^ ^^ step 69 100001100110100101011011011011011101001111011011011010100110111001 SLOT BAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBAABBAAAAAAAAAAAAAABBBBBBBBAB LETTER ALPSLFMDEEMCBFRSPKLEMFHRSCJLJKUHPNMBBNNVVRKRHUTDJUKANJHBTPDFSVDEVU SIDE 121212122121212121111111112212122222112222111221112112212112212212 DIRECTION IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIOOOOOOOIOOIOOIOOIOOOOIOOIIOOIIO changed: 0 step 70 100001100110100100011011011011011101001111011011011010100110111001 fail ^^ ^^ step 71 100001100110100100111011011011011101001111011011011010100110111001 SLOT BAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBAABBAAAAAAAAAAAAAABBBBBBBBAB LETTER ALPSLFMDEEMCBFRSPKLEMFHRSCJLJKUHPNMBBNNVVRKRHUTDJUKANJHBTPDFSVDEVU SIDE 121212122121212121111111112212122222112222111221112112212112212212 DIRECTION IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIOOOOOOOIOOIOOIOOIOOOOIOOIIOOIIO changed: 0 step 72 100001100110100100011011011011011101001111011011011010100110111001 fail ^^ ^^ step 73 100001100110100100011111011011011101001111011011011010100110111001 SLOT BAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBAABBAAAAAAAAAAAAAABBBBBBBBAB LETTER ALPSLFMDEEMCBFRSPKLEMFHRSCJLJKUHPNMBBNNVVRKRHUTDJUKANJHBTPDFSVDEVU SIDE 121212122121212121111111112212122222112222111221112112212112212212 DIRECTION IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIOOOOOOOIOOIOOIOOIOOOOIOOIIOOIIO changed: 0 step 74 100001100110100100011011011011011101001111011011011010100110111001 fail ^^ ^^ step 75 100001100110100100011011111011011101001111011011011010100110111001 SLOT BAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBAABBAAAAAAAAAAAAAABBBBBBBBAB LETTER ALPSLFMDEEMCBFRSPKLEMFHRSCJLJKUHPNMBBNNVVRKRHUTDJUKANJHBTPDFSVDEVU SIDE 121212122121212121111111112212122222112222111221112112212112212212 DIRECTION IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIOOOOOOOIOOIOOIOOIOOOOIOOIIOOIIO changed: 0 step 76 100001100110100100011011011011011101001111011011011010100110111001 fail ^^ ^^ step 77 100001100110100100011011011111011101001111011011011010100110111001 SLOT BAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBAABBAAAAAAAAAAAAAABBBBBBBBAB LETTER ALPSLFMDEEMCBFRSPKLEMFHRSCJLJKUHPNMBBNNVVRKRHUTDJUKANJHBTPDFSVDEVU SIDE 121212122121212121111111112212122222112222111221112112212112212212 DIRECTION IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIOOOOOOOIOOIOOIOOIOOOOIOOIIOOIIO changed: 0 step 78 100001100110100100011011011011011101001111011011011010100110111001 fail ^^ ^^ step 79 100001100110100100011011011011111101001111011011011010100110111001 SLOT BAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBAABBAAAAAAAAAAAAAABBBBBBBBAB LETTER ALPSLFMDEEMCBFRSPKLEMFHRSCJLJKUHPNMBBNNVVRKRHUTDJUKANJHBTPDFSVDEVU SIDE 121212122121212121111111112212122222112222111221112112212112212212 DIRECTION IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIOOOOOOOIOOIOOIOOIOOOOIOOIIOOIIO changed: 0 step 80 100001100110100100011011011011011101001111011011011010100110111001 fail ^^ ^^ SLOT BAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBAABBAAAAAAAAAAAAAABBBBBBBBAB LETTER ALPSLFMDEEMCBFRSPKLEMFHRSCJLJKUHPNMBBNNVVRKRHUTDJUKANJHBTPDFSVDEVU SIDE 121212122121212121111111112212122222112222111221112112212112212212 DIRECTION IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIOOOOOOOIOOIOOIOOIOOOOIOOIIOOIIO changed: 1 step 81 100001100110100100011011011011011111001111011011011010100110111001 fail ^ ^ SLOT BAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBAABBAAAAAAAAAAAAAABBBBBBBBAB LETTER ALPSLFMDEEMCBFRSPKLEMFHRSCJLJKUHPNMBBNNVVRKRHUTDJUKANJHBTPDFSVDEVU SIDE 121212122121212121111111112212122222112222111221112112212112212212 DIRECTION IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIOOOOOOOIOOIOOIOOIOOOOIOOIIOOIIO changed: 0 step 82 100001100110100100011011011011011101001111011011011010100110111001 fail ^^ ^^ test 55: *** FAIL *************************** 31 steps failed SLOT BAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBAABBAAAAAAAAAAAAAABBBBBBBBAB LETTER ALPSLFMDEEMCBFRSPKLEMFHRSCJLJKUHPNMBBNNVVRKRHUTDJUKANJHBTPDFSVDEVU SIDE 121212122121212121111111112212122222112222111221112112212112212212 DIRECTION IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIOOOOOOOIOOIOOIOOIOOOOIOOIIOOIIO this fail OO OOO all fails OO OOO was hi 111111111111111111111111111111111111111111111111111111111111111 1 rising ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ ^^ falling vvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvv vv was lo 00000000000000000000000000000000000000000000000000000000000 0000 total fails 55, total passes 0 space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C toggle comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit step 1 100000000000000000000000000000000001111100011011011010100110111001 step 2 100000000000000000000000000000000001111100100011011010100110111001 step 3 100000000000000000000000000000000001111100000011011010100110111001 step 4 100000000000000000000000000000000001111100000100011010100110111001 step 5 100000000000000000000000000000000001111100000000011010100110111001 step 6 100000000000000000000000000000000001111100000000100010100110111001 step 7 100000000000000000000000000000000001111100000000000010100110111001 step 8 100000000000000000000000000000000001111100000000000101010110111001 step 9 100000000000000000000000000000000001111100000000000001010110111001 step 10 100000000000000000000000000000000001111100000000000001011000111001 step 11 100000000000000000000000000000000001111100000000000001010000111001 step 12 100000000000000000000000000000000001111100000000000001010001100001 step 13 100000000000000000000000000000000001111100000000000001010000100001 step 14 100000000000000000000000000000000001111100000000000001010000100001 step 15 100000000000010000000000000000000000111101000000000001010000100001 step 16 100000000000010010000000000000000000110111000000000001010000100001 step 17 100000000000010010000000000000000000110111111000000001010000100001 step 18 100000000000010010000000000000000000110111011000000001010000100001 step 19 100000000000010010000000000000000000110111011111000001010000100001 step 20 100000000000010010000000000000000000110111011011000001010000100001 step 21 100000000000010010000000000000000000110111011011111001010000100001 step 22 100000000000010010000000000000000000110111011011011001010000100001 step 23 100000000000010010000000000000000000110111011011011110100000100001 step 24 100000000000010010000000000000000000110111011011011010100000100001 step 25 100000000000010010000000000000000000110111011011011010101110100001 step 26 100000000000010010000000000000000000110111011011011010100110100001 step 27 100000000000010010000000000000000000110111011011011010100111111001 step 28 100000000000010010000000000000000000110111011011011010100110111001 step 29 100000000000000010000000000000000001110110011011011010100110111001 step 30 100000000000000000000000000000000001111100011011011010100110111001 step 31 100000000000000000000000000000000001111100011011011010100110111001 step 32 100001000000000000000000000000000001111100011011011010100110111001 step 33 100001100000000000000000000000000001111100011011011010100110111001 step 34 100001100100000000000000000000000001111100011011011010100110111001 step 35 100001100110000000000000000000000001111100011011011010100110111001 step 36 100001100110100000000000000000000001111100011011011010100110111001 step 37 100001100110100100000000000000000001111100011011011010100110111001 step 38 100001100110100100010000000000000001111100011011011010100110111001 step 39 100001100110100100011000000000000001111100011011011010100110111001 step 40 100001100110100100011010000000000001111100011011011010100110111001 step 41 100001100110100100011011000000000001111100011011011010100110111001 step 42 100001100110100100011011010000000001111100011011011010100110111001 step 43 100001100110100100011011011000000001111100011011011010100110111001 step 44 100001100110100100011011011010000001111100011011011010100110111001 step 45 100001100110100100011011011011000001111100011011011010100110111001 SLOT BAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBAABBAAAAAAAAAAAAAABBBBBBBBAB LETTER ALPSLFMDEEMCBFRSPKLEMFHRSCJLJKUHPNMBBNNVVRKRHUTDJUKANJHBTPDFSVDEVU SIDE 121212122121212121111111112212122222112222111221112112212112212212 DIRECTION IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIOOOOOOOIOOIOOIOOIOOOOIOOIIOOIIO changed: 1 0 1 step 46 100001100110100100011011011011010001011101011011011010100110111001 fail ^ ^ SLOT BAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBAABBAAAAAAAAAAAAAABBBBBBBBAB LETTER ALPSLFMDEEMCBFRSPKLEMFHRSCJLJKUHPNMBBNNVVRKRHUTDJUKANJHBTPDFSVDEVU SIDE 121212122121212121111111112212122222112222111221112112212112212212 DIRECTION IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIOOOOOOOIOOIOOIOOIOOOOIOOIIOOIIO changed: 1 0 1 step 47 100001100110100100011011011011011001001111011011011010100110111001 fail ^^ ^^ SLOT BAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBAABBAAAAAAAAAAAAAABBBBBBBBAB LETTER ALPSLFMDEEMCBFRSPKLEMFHRSCJLJKUHPNMBBNNVVRKRHUTDJUKANJHBTPDFSVDEVU SIDE 121212122121212121111111112212122222112222111221112112212112212212 DIRECTION IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIOOOOOOOIOOIOOIOOIOOOOIOOIIOOIIO changed: 1 step 48 100001100110100100011011011011011101001111011011011010100110111001 fail ^^ ^^ SLOT BAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBAABBAAAAAAAAAAAAAABBBBBBBBAB LETTER ALPSLFMDEEMCBFRSPKLEMFHRSCJLJKUHPNMBBNNVVRKRHUTDJUKANJHBTPDFSVDEVU SIDE 121212122121212121111111112212122222112222111221112112212112212212 DIRECTION IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIOOOOOOOIOOIOOIOOIOOOOIOOIIOOIIO changed: 1 0 00 0 step 49 110001100110100100011011011011011100000010011011011010100110111001 fail ^^ ^ ^ SLOT BAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBAABBAAAAAAAAAAAAAABBBBBBBBAB LETTER ALPSLFMDEEMCBFRSPKLEMFHRSCJLJKUHPNMBBNNVVRKRHUTDJUKANJHBTPDFSVDEVU SIDE 121212122121212121111111112212122222112222111221112112212112212212 DIRECTION IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIOOOOOOOIOOIOOIOOIOOOOIOOIIOOIIO changed: 0 1 11 1 step 50 100001100110100100011011011011011101001111011011011010100110111001 fail ^^ ^^ SLOT BAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBAABBAAAAAAAAAAAAAABBBBBBBBAB LETTER ALPSLFMDEEMCBFRSPKLEMFHRSCJLJKUHPNMBBNNVVRKRHUTDJUKANJHBTPDFSVDEVU SIDE 121212122121212121111111112212122222112222111221112112212112212212 DIRECTION IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIOOOOOOOIOOIOOIOOIOOOOIOOIIOOIIO changed: 1 0 00 0 step 51 101001100110100100011011011011011100000010011011011010100110111001 fail ^^ ^ ^ SLOT BAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBAABBAAAAAAAAAAAAAABBBBBBBBAB LETTER ALPSLFMDEEMCBFRSPKLEMFHRSCJLJKUHPNMBBNNVVRKRHUTDJUKANJHBTPDFSVDEVU SIDE 121212122121212121111111112212122222112222111221112112212112212212 DIRECTION IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIOOOOOOOIOOIOOIOOIOOOOIOOIIOOIIO changed: 0 1 11 1 step 52 100001100110100100011011011011011101001111011011011010100110111001 fail ^^ ^^ SLOT BAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBAABBAAAAAAAAAAAAAABBBBBBBBAB LETTER ALPSLFMDEEMCBFRSPKLEMFHRSCJLJKUHPNMBBNNVVRKRHUTDJUKANJHBTPDFSVDEVU SIDE 121212122121212121111111112212122222112222111221112112212112212212 DIRECTION IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIOOOOOOOIOOIOOIOOIOOOOIOOIIOOIIO changed: 1 0 00 0 step 53 100101100110100100011011011011011100000010011011011010100110111001 fail ^^ ^ ^ SLOT BAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBAABBAAAAAAAAAAAAAABBBBBBBBAB LETTER ALPSLFMDEEMCBFRSPKLEMFHRSCJLJKUHPNMBBNNVVRKRHUTDJUKANJHBTPDFSVDEVU SIDE 121212122121212121111111112212122222112222111221112112212112212212 DIRECTION IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIOOOOOOOIOOIOOIOOIOOOOIOOIIOOIIO changed: 0 1 11 1 step 54 100001100110100100011011011011011101001111011011011010100110111001 fail ^^ ^^ SLOT BAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBAABBAAAAAAAAAAAAAABBBBBBBBAB LETTER ALPSLFMDEEMCBFRSPKLEMFHRSCJLJKUHPNMBBNNVVRKRHUTDJUKANJHBTPDFSVDEVU SIDE 121212122121212121111111112212122222112222111221112112212112212212 DIRECTION IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIOOOOOOOIOOIOOIOOIOOOOIOOIIOOIIO changed: 1 0 00 0 step 55 100011100110100100011011011011011100000010011011011010100110111001 fail ^^ ^ ^ SLOT BAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBAABBAAAAAAAAAAAAAABBBBBBBBAB LETTER ALPSLFMDEEMCBFRSPKLEMFHRSCJLJKUHPNMBBNNVVRKRHUTDJUKANJHBTPDFSVDEVU SIDE 121212122121212121111111112212122222112222111221112112212112212212 DIRECTION IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIOOOOOOOIOOIOOIOOIOOOOIOOIIOOIIO changed: 0 1 11 1 step 56 100001100110100100011011011011011101001111011011011010100110111001 fail ^^ ^^ SLOT BAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBAABBAAAAAAAAAAAAAABBBBBBBBAB LETTER ALPSLFMDEEMCBFRSPKLEMFHRSCJLJKUHPNMBBNNVVRKRHUTDJUKANJHBTPDFSVDEVU SIDE 121212122121212121111111112212122222112222111221112112212112212212 DIRECTION IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIOOOOOOOIOOIOOIOOIOOOOIOOIIOOIIO changed: 1 0 00 0 step 57 100001110110100100011011011011011100000010011011011010100110111001 fail ^^ ^ ^ SLOT BAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBAABBAAAAAAAAAAAAAABBBBBBBBAB LETTER ALPSLFMDEEMCBFRSPKLEMFHRSCJLJKUHPNMBBNNVVRKRHUTDJUKANJHBTPDFSVDEVU SIDE 121212122121212121111111112212122222112222111221112112212112212212 DIRECTION IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIOOOOOOOIOOIOOIOOIOOOOIOOIIOOIIO changed: 0 1 11 1 step 58 100001100110100100011011011011011101001111011011011010100110111001 fail ^^ ^^ SLOT BAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBAABBAAAAAAAAAAAAAABBBBBBBBAB LETTER ALPSLFMDEEMCBFRSPKLEMFHRSCJLJKUHPNMBBNNVVRKRHUTDJUKANJHBTPDFSVDEVU SIDE 121212122121212121111111112212122222112222111221112112212112212212 DIRECTION IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIOOOOOOOIOOIOOIOOIOOOOIOOIIOOIIO changed: 1 0 00 0 step 59 100001101110100100011011011011011100000010011011011010100110111001 fail ^^ ^ ^ SLOT BAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBAABBAAAAAAAAAAAAAABBBBBBBBAB LETTER ALPSLFMDEEMCBFRSPKLEMFHRSCJLJKUHPNMBBNNVVRKRHUTDJUKANJHBTPDFSVDEVU SIDE 121212122121212121111111112212122222112222111221112112212112212212 DIRECTION IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIOOOOOOOIOOIOOIOOIOOOOIOOIIOOIIO changed: 0 1 11 1 step 60 100001100110100100011011011011011101001111011011011010100110111001 fail ^^ ^^ SLOT BAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBAABBAAAAAAAAAAAAAABBBBBBBBAB LETTER ALPSLFMDEEMCBFRSPKLEMFHRSCJLJKUHPNMBBNNVVRKRHUTDJUKANJHBTPDFSVDEVU SIDE 121212122121212121111111112212122222112222111221112112212112212212 DIRECTION IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIOOOOOOOIOOIOOIOOIOOOOIOOIIOOIIO changed: 1 0 000 step 61 100001100111100100011011011011011100001000011011011010100110111001 fail ^^ ^ ^ SLOT BAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBAABBAAAAAAAAAAAAAABBBBBBBBAB LETTER ALPSLFMDEEMCBFRSPKLEMFHRSCJLJKUHPNMBBNNVVRKRHUTDJUKANJHBTPDFSVDEVU SIDE 121212122121212121111111112212122222112222111221112112212112212212 DIRECTION IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIOOOOOOOIOOIOOIOOIOOOOIOOIIOOIIO changed: 0 1 111 step 62 100001100110100100011011011011011101001111011011011010100110111001 fail ^^ ^^ SLOT BAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBAABBAAAAAAAAAAAAAABBBBBBBBAB LETTER ALPSLFMDEEMCBFRSPKLEMFHRSCJLJKUHPNMBBNNVVRKRHUTDJUKANJHBTPDFSVDEVU SIDE 121212122121212121111111112212122222112222111221112112212112212212 DIRECTION IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIOOOOOOOIOOIOOIOOIOOOOIOOIIOOIIO changed: 1 0 000 step 63 100001100110110100011011011011011100001000011011011010100110111001 fail ^^ ^ ^ SLOT BAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBAABBAAAAAAAAAAAAAABBBBBBBBAB LETTER ALPSLFMDEEMCBFRSPKLEMFHRSCJLJKUHPNMBBNNVVRKRHUTDJUKANJHBTPDFSVDEVU SIDE 121212122121212121111111112212122222112222111221112112212112212212 DIRECTION IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIOOOOOOOIOOIOOIOOIOOOOIOOIIOOIIO changed: 0 1 111 step 64 100001100110100100011011011011011101001111011011011010100110111001 fail ^^ ^^ SLOT BAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBAABBAAAAAAAAAAAAAABBBBBBBBAB LETTER ALPSLFMDEEMCBFRSPKLEMFHRSCJLJKUHPNMBBNNVVRKRHUTDJUKANJHBTPDFSVDEVU SIDE 121212122121212121111111112212122222112222111221112112212112212212 DIRECTION IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIOOOOOOOIOOIOOIOOIOOOOIOOIIOOIIO changed: 1 000 step 65 100001100110101100011011011011011101000001011011011010100110111001 fail ^^ ^^^ SLOT BAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBAABBAAAAAAAAAAAAAABBBBBBBBAB LETTER ALPSLFMDEEMCBFRSPKLEMFHRSCJLJKUHPNMBBNNVVRKRHUTDJUKANJHBTPDFSVDEVU SIDE 121212122121212121111111112212122222112222111221112112212112212212 DIRECTION IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIOOOOOOOIOOIOOIOOIOOOOIOOIIOOIIO changed: 0 111 step 66 100001100110100100011011011011011101001111011011011010100110111001 fail ^^ ^^ SLOT BAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBAABBAAAAAAAAAAAAAABBBBBBBBAB LETTER ALPSLFMDEEMCBFRSPKLEMFHRSCJLJKUHPNMBBNNVVRKRHUTDJUKANJHBTPDFSVDEVU SIDE 121212122121212121111111112212122222112222111221112112212112212212 DIRECTION IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIOOOOOOOIOOIOOIOOIOOOOIOOIIOOIIO changed: 1 000 step 67 100001100110100110011011011011011101000001011011011010100110111001 fail ^^ ^^^ SLOT BAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBAABBAAAAAAAAAAAAAABBBBBBBBAB LETTER ALPSLFMDEEMCBFRSPKLEMFHRSCJLJKUHPNMBBNNVVRKRHUTDJUKANJHBTPDFSVDEVU SIDE 121212122121212121111111112212122222112222111221112112212112212212 DIRECTION IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIOOOOOOOIOOIOOIOOIOOOOIOOIIOOIIO changed: 0 111 step 68 100001100110100100011011011011011101001111011011011010100110111001 fail ^^ ^^ step 69 100001100110100101011011011011011101001111011011011010100110111001 SLOT BAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBAABBAAAAAAAAAAAAAABBBBBBBBAB LETTER ALPSLFMDEEMCBFRSPKLEMFHRSCJLJKUHPNMBBNNVVRKRHUTDJUKANJHBTPDFSVDEVU SIDE 121212122121212121111111112212122222112222111221112112212112212212 DIRECTION IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIOOOOOOOIOOIOOIOOIOOOOIOOIIOOIIO changed: 0 step 70 100001100110100100011011011011011101001111011011011010100110111001 fail ^^ ^^ step 71 100001100110100100111011011011011101001111011011011010100110111001 SLOT BAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBAABBAAAAAAAAAAAAAABBBBBBBBAB LETTER ALPSLFMDEEMCBFRSPKLEMFHRSCJLJKUHPNMBBNNVVRKRHUTDJUKANJHBTPDFSVDEVU SIDE 121212122121212121111111112212122222112222111221112112212112212212 DIRECTION IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIOOOOOOOIOOIOOIOOIOOOOIOOIIOOIIO changed: 0 step 72 100001100110100100011011011011011101001111011011011010100110111001 fail ^^ ^^ step 73 100001100110100100011111011011011101001111011011011010100110111001 SLOT BAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBAABBAAAAAAAAAAAAAABBBBBBBBAB LETTER ALPSLFMDEEMCBFRSPKLEMFHRSCJLJKUHPNMBBNNVVRKRHUTDJUKANJHBTPDFSVDEVU SIDE 121212122121212121111111112212122222112222111221112112212112212212 DIRECTION IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIOOOOOOOIOOIOOIOOIOOOOIOOIIOOIIO changed: 0 step 74 100001100110100100011011011011011101001111011011011010100110111001 fail ^^ ^^ step 75 100001100110100100011011111011011101001111011011011010100110111001 SLOT BAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBAABBAAAAAAAAAAAAAABBBBBBBBAB LETTER ALPSLFMDEEMCBFRSPKLEMFHRSCJLJKUHPNMBBNNVVRKRHUTDJUKANJHBTPDFSVDEVU SIDE 121212122121212121111111112212122222112222111221112112212112212212 DIRECTION IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIOOOOOOOIOOIOOIOOIOOOOIOOIIOOIIO changed: 0 step 76 100001100110100100011011011011011101001111011011011010100110111001 fail ^^ ^^ step 77 100001100110100100011011011111011101001111011011011010100110111001 SLOT BAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBAABBAAAAAAAAAAAAAABBBBBBBBAB LETTER ALPSLFMDEEMCBFRSPKLEMFHRSCJLJKUHPNMBBNNVVRKRHUTDJUKANJHBTPDFSVDEVU SIDE 121212122121212121111111112212122222112222111221112112212112212212 DIRECTION IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIOOOOOOOIOOIOOIOOIOOOOIOOIIOOIIO changed: 0 step 78 100001100110100100011011011011011101001111011011011010100110111001 fail ^^ ^^ step 79 100001100110100100011011011011111101001111011011011010100110111001 SLOT BAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBAABBAAAAAAAAAAAAAABBBBBBBBAB LETTER ALPSLFMDEEMCBFRSPKLEMFHRSCJLJKUHPNMBBNNVVRKRHUTDJUKANJHBTPDFSVDEVU SIDE 121212122121212121111111112212122222112222111221112112212112212212 DIRECTION IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIOOOOOOOIOOIOOIOOIOOOOIOOIIOOIIO changed: 0 step 80 100001100110100100011011011011011101001111011011011010100110111001 fail ^^ ^^ SLOT BAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBAABBAAAAAAAAAAAAAABBBBBBBBAB LETTER ALPSLFMDEEMCBFRSPKLEMFHRSCJLJKUHPNMBBNNVVRKRHUTDJUKANJHBTPDFSVDEVU SIDE 121212122121212121111111112212122222112222111221112112212112212212 DIRECTION IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIOOOOOOOIOOIOOIOOIOOOOIOOIIOOIIO changed: 1 step 81 100001100110100100011011011011011111001111011011011010100110111001 fail ^ ^ SLOT BAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBAABBAAAAAAAAAAAAAABBBBBBBBAB LETTER ALPSLFMDEEMCBFRSPKLEMFHRSCJLJKUHPNMBBNNVVRKRHUTDJUKANJHBTPDFSVDEVU SIDE 121212122121212121111111112212122222112222111221112112212112212212 DIRECTION IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIOOOOOOOIOOIOOIOOIOOOOIOOIIOOIIO changed: 0 step 82 100001100110100100011011011011011101001111011011011010100110111001 fail ^^ ^^ test 56: *** FAIL *************************** 31 steps failed SLOT BAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBAABBAAAAAAAAAAAAAABBBBBBBBAB LETTER ALPSLFMDEEMCBFRSPKLEMFHRSCJLJKUHPNMBBNNVVRKRHUTDJUKANJHBTPDFSVDEVU SIDE 121212122121212121111111112212122222112222111221112112212112212212 DIRECTION IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIOOOOOOOIOOIOOIOOIOOOOIOOIIOOIIO this fail OO OOO all fails OO OOO was hi 111111111111111111111111111111111111111111111111111111111111111 1 rising ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ ^^ falling vvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvv vv was lo 00000000000000000000000000000000000000000000000000000000000 0000 total fails 56, total passes 0 space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C toggle comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT BAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBAABBAAAAAAAAAAAAAABBBBBBBBAB LETTER ALPSLFMDEEMCBFRSPKLEMFHRSCJLJKUHPNMBBNNVVRKRHUTDJUKANJHBTPDFSVDEVU SIDE 121212122121212121111111112212122222112222111221112112212112212212 DIRECTION IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIOOOOOOOIOOIOOIOOIOOOOIOOIIOOIIO all fails OO OOO was lo 00000000000000000000000000000000000000000000000000000000000 0000 falling vvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvv vv rising ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ ^^ was hi 111111111111111111111111111111111111111111111111111111111111111 1 total fails 56, total passes 0 Main menu Thu Aug 20 15:36:30 2015 test file is: tests\m222.tst delay is: 0 trigger is: 1 1 read test file 2 set test delay 3 set test trigger 4 run test 5 output loading test 8 diags 9 exit Enter test file name? trying to open test file: tests\m222.new reading test file: tests\m222.new comment: M222 PCB REV B SCHEMATIC REV A LINC TAPE REGISTERS comment: comment: TERMINOLOGY- SIGNALS REFER TO VOL4 M222 SCHEMATIC. comment: comment: BUT... comment: comment: DEC USES AND-NOR GATES TO ROUTE THE ADDER A AND B INPUTS, SO... comment: DEC RENAMED THE ADDER TO NEGATIVE LOGIC TERMS (I.E. A-N + B-N + C-N -> SUM-N, C1-N). comment: (NOT THE 7482 DATASHEET NAMES OF A + B + C -> SUM, C1). comment: comment: SO, WITH ALL 'AND ENABLES' LOW, THE AND-NOR OUTPUTS = HIGH. comment: WITH C-L HIGH, THE ADDER OUTPUT IS SUM-N=1, C1-N=1; comment: THE INVERTED ADDER OUTPUT IS LOW (TAPE BUS). comment: AND THERE IS NO CARRY (C1-N IS HI). comment: comment: THE TWO ADDERS, TWO REGISTER BITS, ETC ARE LABELED BIT 2 (EVEN, MSB) AND BIT 3 (ODD, LSB). comment: THE ADDERS ARE REFERRED TO AS 'ADDER2' (MSB) AND 'ADDER3' (LSB). comment: comment: POWER PINS: comment: AA2 +5V comment: AT1 GROUND comment: AC2 GROUND comment: BA2 +5V comment: BT1 GROUND comment: BC2 GROUND comment: comment: (ALL PINS ARE USED). comment: comment: pins: PINS pins: 1 I BA1 CARRY IN-N, (TO E9-5 7482 C0) C-N TO ADDER2 pins: 2 I AL2 AND-NOR ENABLE: TAC TAC3 TO PIN BB2 (TO ADDER3) TAC2 TO PIN AN2 (TO ADDER2) pins: 3 I AP1 AND-NOR ENABLE: TMA SETUP (TMAS)3 TO PIN BB2 (TO ADDER3), (TMAS)3 TO PIN AN2 (TO ADDER2) pins: 4 I AS2 AND-NOR ENABLE: TMA TMA3 TO PIN BB2 (TO ADDER3), TMA2 TO PIN AN2 (TO ADDER2) pins: 5 I AL1 AND-NOR ENABLE: PIN AF2 TO PIN BB2 (TO ADDER3), PIN AM1 TO PIN AN2 (TO ADDER2) pins: 6 I AF2 AND-NOR INPUT (AL1 ENABLES) TO PIN BB2 (TO ADDER3). pins: 7 I AM1 AND-NOR INPUT (AL1 ENABLES) TO PIN AN2 (TO ADDER2) pins: 8 I AD2 AND-NOR ENABLE: RWB RWB3 TO PIN BB2 (TO ADDER3), RWB2 TO PIN AN2 (TO ADDER2) pins: 9 I AE2 AND-NOR ENABLE: PIN AE1 TO PIN BB2 (TO ADDER3), PIN AM2 TO PIN AN2 (TO ADDER2) pins: 10 I AE1 AND-NOR INPUT (AE2 ENABLES) TO PIN BB2 (TO ADDER3). pins: 11 I AM2 AND-NOR INPUT (AE2 ENABLES) TO PIN AN2 (TO ADDER2) pins: 12 I AC1 AND-NOR INPUT, AND WITH PIN AB2 TO PIN BB2 (TO ADDER3) pins: 13 I AB2 AND-NOR INPUT, AND WITH PIN AC1 TO PIN BB2 (TO ADDER3) pins: 14 I AF1 AND-NOR INPUT (AND WITH ITSELF) TO PIN BB2 (TO ADDER3) pins: 15 I AR2 AND-NOR INPUT, AND WITH PIN AS1 TO PIN AN2 (TO ADDER2) pins: 16 I AS1 AND-NOR INPUT, AND WITH PIN AR2 TO PIN AN2 (TO ADDER2) pins: 17 I AP2 AND-NOR INPUT (AND WITH ITSELF) TO PIN AN2 (TO ADDER2) pins: 18 I BK1 AND-NOR ENABLE: TB3 TO PIN BB1 (TO ADDER3), TB2 TO PIN BN1 (TO ADDER2) pins: 19 I BL1 AND-NOR ENABLE: PIN BE1 TO PIN BB1 (TO ADDER3), PIN BM1 TO PIN BN1 (TO ADDER2) pins: 20 I BE1 AND-NOR INPUT (BL1 ENABLES) TO PIN BB1 (TO ADDER3). pins: 21 I BM1 AND-NOR INPUT (BL1 ENABLES) TO PIN BN1 (TO ADDER2) pins: 22 I BF1 AND-NOR ENABLE: PIN BH1 TO PIN BB1 (TO ADDER3), PIN BR1 TO PIN BN1 (TO ADDER2) pins: 23 I BH1 AND-NOR INPUT (BF1 ENABLES): TO PIN BB1 (TO ADDER3), pins: 24 I BR1 AND-NOR INPUT (BF1 ENABLES): TO PIN BN1 (TO ADDER2) pins: 25 I BS1 AND-NOR ENABLE: PIN BC1 TO PIN BB1 (TO ADDER3), PIN BJ2 TO PIN BN1 (TO ADDER2) pins: 26 I BC1 AND-NOR INPUT (BS1 ENABLES): TO PIN BB1 (TO ADDER3), pins: 27 I BJ2 AND-NOR INPUT (BS1 ENABLES): TO PIN BN1 (TO ADDER2) pins: 28 I BL2 AND-NOR ENABLE: PIN BJ1 TO PIN BB1 (TO ADDER3), PIN BK2 TO PIN BN1 (TO ADDER2) pins: 29 I BJ1 AND-NOR INPUT (BL2 ENABLES): TO PIN BB1 (TO ADDER3), pins: 30 I BK2 AND-NOR INPUT (BL2 ENABLES): TO PIN BN1 (TO ADDER2) pins: 31 I BU1 AND-NOR ENABLE: PIN BH2 TO PIN BB1 (TO ADDER3), PIN BP2 TO PIN BN1 (TO ADDER2) pins: 32 I BH2 AND-NOR INPUT (BU1 ENABLES): TO PIN BB1 (TO ADDER3), pins: 33 I BP2 AND-NOR INPUT (BU1 ENABLES): TO PIN BN1 (TO ADDER2) pins: 34 I BN2 AND-NOR INPUT (AND WITH BM2): TO PIN BN1 (TO ADDER2) pins: 35 I BM2 AND-NOR INPUT (AND WITH BM2): TO PIN BN1 (TO ADDER2) pins: 36 O BB2 AND-NOR OUTPUT, (DRIVES E9-2 7482 A1) TO ADDER3 INPUT pins: 37 O BB1 AND-NOR OUTPUT, (DRIVES E9-3 7482 B1) TO ADDER3 INPUT pins: 38 O BN1 AND-NOR OUTPUT, (DRIVES E9-14 7482 A2) TO ADDER2 INPUT pins: 39 O AN2 AND-NOR OUTPUT, (DRIVES E9-13 7482 B2) TO ADDER2 INPUT pins: 40 O AV2 CARRY OUT-N (E9-10 7482 C2) pins: 41 O BV2 TAPE BUS 2 OUTPUT (INVERTED ADDER2 SUM-N (E9-12 7482 SUM2) pins: 42 O BR2 TAPE BUS 3 OUTPUT (INVERTED ADDER3 SUM-N (E9-1 7482 SUM1) pins: 43 I AK1 LOAD TMA SETUP (FROM TAPE BUS) (RISING EDGE CLOCK) pins: 44 O AR1 TMA SETUP 2 pins: 45 O AH1 TMA SETUP 3 pins: 46 I AU2 LOAD TMA (FROM TAPE BUS) (RISING EDGE CLOCK) pins: 47 O AT2 TMA 2 pins: 48 O AD1 TMA 3 pins: 49 I AJ1 LOAD TBN (FROM TAPE BUS) (RISING EDGE CLOCK) pins: 50 O AU1 TBN 2 pins: 51 O AK2 TBN 3 pins: 52 I AA1 LOAD TAC (FROM TAPE BUS) (RISING EDGE CLOCK) pins: 53 O AN1 TAC 2 pins: 54 O AJ2 TAC 2-N pins: 55 O AH2 TAC 3 pins: 56 O AB1 TAC 3-N pins: 57 I BT2 LOAD TB (FROM TAPE BUS) (RISING EDGE CLOCK) pins: 58 O BP1 TB 2 pins: 59 O BD1 TB 3 pins: 60 I BF2 LOAD RWB (FROM TB) (JAMS CLEAR,SET) pins: 61 I BS2 PHASE (SELECTS POLARITY OF RWB OUT, 0 -> INVERTED) pins: 62 O BV1 RWB OUT (=RWB 2 IF PHASE=1; =RWB 2-N IF PHASE=0) pins: 63 O BD2 RWB 3 pins: 64 I BE2 SHIFT RWB (SHIFTS PIN AV1 INTO RWB 3, SHIFTS RWB3 TO RWB2) (RISING CLOCK) pins: 65 I AV1 RWB IN (SHIFTED INTO RWB 3) pins: 66 O BU2 +3.5V pins: direction: IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIOOOOOOOIOOIOOIOOIOOOOIOOIIOOIIO comment: ; all registers are unknown comment: ; turn on C0, PHASE comment: ; with no ENABLES, BUS2,BUS3 is 11, C2 is 1 test 1: 1000000000000000000000000000000000011111000XX0XX0XX0XXXX0XX01XX001 comment: comment: ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; comment: ; comment: ; set all registers LOW comment: ; comment: ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; comment: comment: ; load TMA SETUP from tape bus (00) test 2: 100 test 3: 0 comment: ; load TMA from tape bus (00) test 4: 100 test 5: 0 comment: ; load TBN from tape bus (00) test 6: 100 test 7: 0 comment: ; load TAC from tape bus (00) test 8: 10101 test 9: 0 comment: ; load TB from tape bus (00) test 10: 100 test 11: 0 comment: ; load RWB from TB (JAMS CLEAR AND PRESET) test 12: 1 00 test 13: 0 comment: ; (no change) test 14: 100000000000000000000000000000000001111100000000000001010000100001 comment: comment: comment: ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; comment: ; comment: ; set all registers HIGH comment: ; comment: ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; comment: comment: ; set pin AF1 (AND with itself) to clear pin BB2 (AND-NOR output) and set pin BR2 TAPE BUS 3 OUTPUT test 15: 1 0 1 comment: ; set pin AP2 (AND with itself) to clear pin AN2 (AND-NOR output) and set pin BV2 TAPE BUS 2 OUTPUT test 16: 1 0 1 comment: comment: comment: ; load TMA SETUP from tape bus (11) test 17: 111 test 18: 0 comment: ; load TMA from tape bus (11) test 19: 111 test 20: 0 comment: ; load TBN from tape bus (11) test 21: 111 test 22: 0 comment: ; load TAC from tape bus (11) test 23: 11010 test 24: 0 comment: ; load TB from tape bus (11) test 25: 111 test 26: 0 comment: ; load RWB from TB (JAMS CLEAR AND PRESET) test 27: 1 11 test 28: 0 comment: ; clear pin AF1 (AND with itself) to set pin BB2 (AND-NOR output) and clear pin BR2 TAPE BUS 3 OUTPUT test 29: 0 1 0 comment: ; clear pin AP2 (AND with itself) to set pin AN2 (AND-NOR output) and clear pin BV2 TAPE BUS 2 OUTPUT test 30: 0 1 0 comment: ; (no change) test 31: 100000000000000000000000000000000001111100011011011010100110111001 comment: comment: comment: ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; comment: ; comment: ; test AND-NOR logic comment: ; comment: ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; comment: comment: ; (all registers are HIGH) comment: ; set all pins HIGH except ENABLES comment: comment: ; set pin AF2 HIGH test 32: 1 comment: ; set pin AM1 HIGH test 33: 1 comment: ; set pin AE1 HIGH test 34: 1 comment: ; set pin AM2 HIGH test 35: 1 comment: ; set pin AB2 HIGH test 36: 1 comment: ; set pin AS1 HIGH test 37: 1 comment: ; set pin BE1 HIGH test 38: 1 comment: ; set pin BM1 HIGH test 39: 1 comment: ; set pin BH1 HIGH test 40: 1 comment: ; set pin BR1 HIGH test 41: 1 comment: ; set pin BC1 HIGH test 42: 1 comment: ; set pin BJ2 HIGH test 43: 1 comment: ; set pin BJ1 HIGH test 44: 1 comment: ; set pin BK2 HIGH test 45: 1 comment: ; set pin BH2 HIGH test 46: 1 comment: ; set pin BP2 HIGH test 47: 1 comment: ; set pin BN2 HIGH test 48: 1 comment: ; toggle each ENABLE comment: comment: ; set pin AL2 to clear pin BB2 and pin AN2 AND-NOR OUTPUTS and set TAPE BUS 2 OUTPUT and TAPE BUS 3 OUTPUT test 49: 1 0 0 11 test 50: 0 1 1 00 comment: ; set pin AP1 to clear pin BB2 and pin AN2 AND-NOR OUTPUTS and set TAPE BUS 2 OUTPUT and TAPE BUS 3 OUTPUT test 51: 1 0 0 11 test 52: 0 1 1 00 comment: ; set pin AS2 to clear pin BB2 and pin AN2 AND-NOR OUTPUTS and set TAPE BUS 2 OUTPUT and TAPE BUS 3 OUTPUT test 53: 1 0 0 11 test 54: 0 1 1 00 comment: ; set pin AL1 to clear pin BB2 and pin AN2 AND-NOR OUTPUTS and set TAPE BUS 2 OUTPUT and TAPE BUS 3 OUTPUT test 55: 1 0 0 11 test 56: 0 1 1 00 comment: ; set pin AL1 to clear pin BB2 and pin AN2 AND-NOR OUTPUTS and set TAPE BUS 2 OUTPUT and TAPE BUS 3 OUTPUT test 57: 1 0 0 11 test 58: 0 1 1 00 comment: ; set pin AE2 to clear pin BB2 and pin AN2 AND-NOR OUTPUTS and set TAPE BUS 2 OUTPUT and TAPE BUS 3 OUTPUT test 59: 1 0 0 11 test 60: 0 1 1 00 comment: ; set pin AC1 to clear pin BB2 and set TAPE BUS 3 OUTPUT test 61: 1 0 1 test 62: 0 1 0 comment: ; set pin AF1 to clear pin BB2 and set TAPE BUS 3 OUTPUT test 63: 1 0 1 test 64: 0 1 0 comment: ; set pin AR2 to clear pin AN2 AND-NOR OUTPUTS and set TAPE BUS 2 OUTPUT test 65: 1 0 1 test 66: 0 1 0 comment: ; set pin AP2 to clear pin AN2 AND-NOR OUTPUTS and set TAPE BUS 2 OUTPUT test 67: 1 0 1 test 68: 0 1 0 comment: comment: ; set pin BK1 to clear pin BB1 and pin BN1 AND-NOR OUTPUTS and set TAPE BUS 2 OUTPUT and TAPE BUS 3 OUTPUT test 69: 1 00 11 test 70: 0 11 00 comment: ; set pin BL1 to clear pin BB1 and pin BN1 AND-NOR OUTPUTS and set TAPE BUS 2 OUTPUT and TAPE BUS 3 OUTPUT test 71: 1 00 11 test 72: 0 11 00 comment: ; set pin BF1 to clear pin BB1 and pin BN1 AND-NOR OUTPUTS and set TAPE BUS 2 OUTPUT and TAPE BUS 3 OUTPUT test 73: 1 00 11 test 74: 0 11 00 comment: ; set pin BS1 to clear pin BB1 and pin BN1 AND-NOR OUTPUTS and set TAPE BUS 2 OUTPUT and TAPE BUS 3 OUTPUT test 75: 1 00 11 test 76: 0 11 00 comment: ; set pin BL2 to clear pin BB1 and pin BN1 AND-NOR OUTPUTS and set TAPE BUS 2 OUTPUT and TAPE BUS 3 OUTPUT test 77: 1 00 11 test 78: 0 11 00 comment: ; set pin BU1 to clear pin BB1 and pin BN1 AND-NOR OUTPUTS and set TAPE BUS 2 OUTPUT and TAPE BUS 3 OUTPUT test 79: 1 00 11 test 80: 0 11 00 comment: ; set pin BM2 to clear pin BB1 and TAPE BUS 3 OUTPUT test 81: 1 0 1 test 82: 0 1 0 comment: comment: ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; comment: ; test shifting the RWB comment: ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; comment: comment: comment: comment: ; shift in 0, expect 10 test 83: 1010 test 84: 0 comment: ; shift in 0, expect 00 test 85: 0010 test 86: 0 comment: ; shift in 0, expect 00 test 87: 0010 test 88: 0 comment: ; shift in 1, expect 01 test 89: 0111 test 90: 0 comment: ; shift in 1, expect 11 test 91: 1111 test 92: 0 comment: ; shift in 1, expect 11 test 93: 1111 test 94: 0 comment: ; shift in 0, expect 10 test 95: 1010 test 96: 0 comment: ; shift in 1, expect 01 test 97: 0111 test 98: 0 comment: ; shift in 0, expect 10 test 99: 1010 test 100: 0 comment: ; shift in 1, expect 01 test 101: 0111 test 102: 0 comment: ; shift in 1, expect 10 test 103: 1011 test 104: 0 comment: ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; comment: ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; comment: ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; comment: ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; comment: ; needs work comment: ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; comment: ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; comment: ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; comment: ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; end: END summary column 1: offset 2, mask 0x2000 column 2: offset 1, mask 0x0002 column 3: offset 1, mask 0x0800 column 4: offset 1, mask 0x0040 column 5: offset 1, mask 0x4000 column 6: offset 0, mask 0x0004 column 7: offset 1, mask 0x2000 column 8: offset 0, mask 0x0010 column 9: offset 0, mask 0x0008 column 10: offset 0, mask 0x0800 column 11: offset 1, mask 0x0004 column 12: offset 0, mask 0x2000 column 13: offset 0, mask 0x0040 column 14: offset 0, mask 0x0400 column 15: offset 1, mask 0x0020 column 16: offset 1, mask 0x0200 column 17: offset 1, mask 0x0010 column 18: offset 3, mask 0x2000 column 19: offset 3, mask 0x1000 column 20: offset 2, mask 0x0200 column 21: offset 3, mask 0x0800 column 22: offset 2, mask 0x0100 column 23: offset 3, mask 0x8000 column 24: offset 3, mask 0x0100 column 25: offset 4, mask 0x8000 column 26: offset 2, mask 0x0800 column 27: offset 3, mask 0x0002 column 28: offset 3, mask 0x0008 column 29: offset 3, mask 0x4000 column 30: offset 3, mask 0x0004 column 31: offset 4, mask 0x2000 column 32: offset 3, mask 0x0001 column 33: offset 3, mask 0x0040 column 34: offset 3, mask 0x0020 column 35: offset 3, mask 0x0010 column 36: offset 2, mask 0x0008 column 37: offset 2, mask 0x1000 column 38: offset 3, mask 0x0400 column 39: offset 1, mask 0x0008 column 40: offset 2, mask 0x0002 column 41: offset 4, mask 0x0008 column 42: offset 3, mask 0x0080 column 43: offset 1, mask 0x8000 column 44: offset 1, mask 0x0400 column 45: offset 0, mask 0x0200 column 46: offset 2, mask 0x0001 column 47: offset 1, mask 0x0080 column 48: offset 0, mask 0x1000 column 49: offset 0, mask 0x0100 column 50: offset 2, mask 0x8000 column 51: offset 1, mask 0x0001 column 52: offset 0, mask 0x8000 column 53: offset 1, mask 0x1000 column 54: offset 0, mask 0x0001 column 55: offset 0, mask 0x0002 column 56: offset 0, mask 0x4000 column 57: offset 4, mask 0x0002 column 58: offset 3, mask 0x0200 column 59: offset 2, mask 0x0400 column 60: offset 2, mask 0x0080 column 61: offset 4, mask 0x0001 column 62: offset 4, mask 0x1000 column 63: offset 2, mask 0x0020 column 64: offset 2, mask 0x0040 column 65: offset 2, mask 0x4000 column 66: offset 4, mask 0x0004 direction bits (1=input) 0x52A3 0x1589 0x943A 0x0680 0x50FC pullup bits (1=pullup) 0x0000 0x0000 0x0000 0x0000 0x0000 test step out_data dont care 1: 0x0000 0x0008 0x300A 0x0400 0x0005 0x5203 0x1481 0x8420 0x0200 0x1000 2: 0x0000 0x8008 0x300A 0x0400 0x0005 0x5003 0x1081 0x8420 0x0200 0x1000 3: 0x0000 0x0008 0x300A 0x0400 0x0005 0x5003 0x1081 0x8420 0x0200 0x1000 4: 0x0000 0x0008 0x300B 0x0400 0x0005 0x4003 0x1001 0x8420 0x0200 0x1000 5: 0x0000 0x0008 0x300A 0x0400 0x0005 0x4003 0x1001 0x8420 0x0200 0x1000 6: 0x0100 0x0008 0x300A 0x0400 0x0005 0x4003 0x1000 0x0420 0x0200 0x1000 7: 0x0000 0x0008 0x300A 0x0400 0x0005 0x4003 0x1000 0x0420 0x0200 0x1000 8: 0xC001 0x0008 0x300A 0x0400 0x0005 0x0000 0x0000 0x0420 0x0200 0x1000 9: 0x4001 0x0008 0x300A 0x0400 0x0005 0x0000 0x0000 0x0420 0x0200 0x1000 10: 0x4001 0x0008 0x300A 0x0400 0x0007 0x0000 0x0000 0x0020 0x0000 0x1000 11: 0x4001 0x0008 0x300A 0x0400 0x0005 0x0000 0x0000 0x0020 0x0000 0x1000 12: 0x4001 0x0008 0x308A 0x0400 0x0005 13: 0x4001 0x0008 0x300A 0x0400 0x0005 14: 0x4001 0x0008 0x300A 0x0400 0x0005 15: 0x4401 0x0008 0x3002 0x0480 0x0005 16: 0x4401 0x0010 0x3002 0x0480 0x000D 17: 0x4601 0x8410 0x3002 0x0480 0x000D 18: 0x4601 0x0410 0x3002 0x0480 0x000D 19: 0x5601 0x0490 0x3003 0x0480 0x000D 20: 0x5601 0x0490 0x3002 0x0480 0x000D 21: 0x5701 0x0491 0xB002 0x0480 0x000D 22: 0x5601 0x0491 0xB002 0x0480 0x000D 23: 0x9602 0x1491 0xB002 0x0480 0x000D 24: 0x1602 0x1491 0xB002 0x0480 0x000D 25: 0x1602 0x1491 0xB402 0x0680 0x000F 26: 0x1602 0x1491 0xB402 0x0680 0x000D 27: 0x1602 0x1491 0xB4A2 0x0680 0x100D 28: 0x1602 0x1491 0xB422 0x0680 0x100D 29: 0x1202 0x1491 0xB42A 0x0600 0x100D 30: 0x1202 0x1489 0xB42A 0x0600 0x1005 31: 0x1202 0x1489 0xB42A 0x0600 0x1005 32: 0x1206 0x1489 0xB42A 0x0600 0x1005 33: 0x1206 0x3489 0xB42A 0x0600 0x1005 34: 0x1A06 0x3489 0xB42A 0x0600 0x1005 35: 0x1A06 0x348D 0xB42A 0x0600 0x1005 36: 0x1A46 0x348D 0xB42A 0x0600 0x1005 37: 0x1A46 0x368D 0xB42A 0x0600 0x1005 38: 0x1A46 0x368D 0xB62A 0x0600 0x1005 39: 0x1A46 0x368D 0xB62A 0x0E00 0x1005 40: 0x1A46 0x368D 0xB62A 0x8E00 0x1005 41: 0x1A46 0x368D 0xB62A 0x8F00 0x1005 42: 0x1A46 0x368D 0xBE2A 0x8F00 0x1005 43: 0x1A46 0x368D 0xBE2A 0x8F02 0x1005 44: 0x1A46 0x368D 0xBE2A 0xCF02 0x1005 45: 0x1A46 0x368D 0xBE2A 0xCF06 0x1005 46: 0x1A46 0x368D 0xBE2A 0xCF07 0x1005 47: 0x1A46 0x368D 0xBE2A 0xCF47 0x1005 48: 0x1A46 0x368D 0xBE2A 0xCF67 0x1005 49: 0x1A46 0x3687 0xBE22 0xCFE7 0x100D 50: 0x1A46 0x368D 0xBE2A 0xCF67 0x1005 51: 0x1A46 0x3E85 0xBE22 0xCFE7 0x100D 52: 0x1A46 0x368D 0xBE2A 0xCF67 0x1005 53: 0x1A46 0x36C5 0xBE22 0xCFE7 0x100D 54: 0x1A46 0x368D 0xBE2A 0xCF67 0x1005 55: 0x1A46 0x7685 0xBE22 0xCFE7 0x100D 56: 0x1A46 0x368D 0xBE2A 0xCF67 0x1005 57: 0x1A56 0x3685 0xBE22 0xCFE7 0x100D 58: 0x1A46 0x368D 0xBE2A 0xCF67 0x1005 59: 0x1A4E 0x3685 0xBE22 0xCFE7 0x100D 60: 0x1A46 0x368D 0xBE2A 0xCF67 0x1005 61: 0x3A46 0x368D 0xBE22 0xCFE7 0x1005 62: 0x1A46 0x368D 0xBE2A 0xCF67 0x1005 63: 0x1E46 0x368D 0xBE22 0xCFE7 0x1005 64: 0x1A46 0x368D 0xBE2A 0xCF67 0x1005 65: 0x1A46 0x36A5 0xBE2A 0xCF67 0x100D 66: 0x1A46 0x368D 0xBE2A 0xCF67 0x1005 67: 0x1A46 0x3695 0xBE2A 0xCF67 0x100D 68: 0x1A46 0x368D 0xBE2A 0xCF67 0x1005 69: 0x1A46 0x368D 0xAE2A 0xEBE7 0x100D 70: 0x1A46 0x368D 0xBE2A 0xCF67 0x1005 71: 0x1A46 0x368D 0xAE2A 0xDBE7 0x100D 72: 0x1A46 0x368D 0xBE2A 0xCF67 0x1005 73: 0x1A46 0x368D 0xAF2A 0xCBE7 0x100D 74: 0x1A46 0x368D 0xBE2A 0xCF67 0x1005 75: 0x1A46 0x368D 0xAE2A 0xCBE7 0x900D 76: 0x1A46 0x368D 0xBE2A 0xCF67 0x1005 77: 0x1A46 0x368D 0xAE2A 0xCBEF 0x100D 78: 0x1A46 0x368D 0xBE2A 0xCF67 0x1005 79: 0x1A46 0x368D 0xAE2A 0xCBE7 0x300D 80: 0x1A46 0x368D 0xBE2A 0xCF67 0x1005 81: 0x1A46 0x368D 0xBE2A 0xCB77 0x100D 82: 0x1A46 0x368D 0xBE2A 0xCF67 0x1005 83: 0x1A46 0x368D 0xBE4A 0xCF67 0x1005 84: 0x1A46 0x368D 0xBE0A 0xCF67 0x1005 85: 0x1A46 0x368D 0xBE4A 0xCF67 0x0005 86: 0x1A46 0x368D 0xBE0A 0xCF67 0x0005 87: 0x1A46 0x368D 0xBE4A 0xCF67 0x0005 88: 0x1A46 0x368D 0xBE0A 0xCF67 0x0005 89: 0x1A46 0x368D 0xFE6A 0xCF67 0x0005 90: 0x1A46 0x368D 0xFE2A 0xCF67 0x0005 91: 0x1A46 0x368D 0xFE6A 0xCF67 0x1005 92: 0x1A46 0x368D 0xFE2A 0xCF67 0x1005 93: 0x1A46 0x368D 0xFE6A 0xCF67 0x1005 94: 0x1A46 0x368D 0xFE2A 0xCF67 0x1005 95: 0x1A46 0x368D 0xBE4A 0xCF67 0x1005 96: 0x1A46 0x368D 0xBE0A 0xCF67 0x1005 97: 0x1A46 0x368D 0xFE6A 0xCF67 0x0005 98: 0x1A46 0x368D 0xFE2A 0xCF67 0x0005 99: 0x1A46 0x368D 0xBE4A 0xCF67 0x1005 100: 0x1A46 0x368D 0xBE0A 0xCF67 0x1005 101: 0x1A46 0x368D 0xFE6A 0xCF67 0x0005 102: 0x1A46 0x368D 0xFE2A 0xCF67 0x0005 103: 0x1A46 0x368D 0xFE4A 0xCF67 0x1005 104: 0x1A46 0x368D 0xFE0A 0xCF67 0x1005 PINs used (in edge connector order) (G=ground,P=power) SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBB LETTER ABCDEFHJKLMNPRSTUVABCDEFHJKLMNPRSTUVABCDEFHJKLMNPRSTUVABCDEFHJKLMNPRSTUV SIDE 111111111111111111222222222222222222111111111111111111222222222222222222 USAGE IOIOIIOIIIIOIOIGOIPIGIIIOOOIIOIIIOIOIOIOIIIIIIIOOIIGIOPOGOIIIIIIIIIOIIOO UUT has 44 inputs UUT has 22 outputs contains 66 pins/columns 0 pins are not used contains 104 'test steps' M222 PCB REV B SCHEMATIC REV A LINC TAPE REGISTERS TERMINOLOGY- SIGNALS REFER TO VOL4 M222 SCHEMATIC. BUT... DEC USES AND-NOR GATES TO ROUTE THE ADDER A AND B INPUTS, SO... DEC RENAMED THE ADDER TO NEGATIVE LOGIC TERMS (I.E. A-N + B-N + C-N -> SUM-N, C1-N). (NOT THE 7482 DATASHEET NAMES OF A + B + C -> SUM, C1). SO, WITH ALL 'AND ENABLES' LOW, THE AND-NOR OUTPUTS = HIGH. WITH C-L HIGH, THE ADDER OUTPUT IS SUM-N=1, C1-N=1; THE INVERTED ADDER OUTPUT IS LOW (TAPE BUS). AND THERE IS NO CARRY (C1-N IS HI). THE TWO ADDERS, TWO REGISTER BITS, ETC ARE LABELED BIT 2 (EVEN, MSB) AND BIT 3 (ODD, LSB). THE ADDERS ARE REFERRED TO AS 'ADDER2' (MSB) AND 'ADDER3' (LSB). POWER PINS: AA2 +5V AT1 GROUND AC2 GROUND BA2 +5V BT1 GROUND BC2 GROUND (ALL PINS ARE USED). PINS Main menu Thu Aug 20 15:36:38 2015 test file is: tests\m222.new delay is: 0 trigger is: 1 1 read test file 2 set test delay 3 set test trigger 4 run test 5 output loading test 8 diags 9 exit UUT power is okay Thu Aug 20 15:36:40 2015 space single step O run once (one test, all steps) F run, stop on fail G go (run tests N run, stop on fail, no print S scope (run, no print) C toggle comment printout + increase speed (less delay) - decrease speed (more delay)(slower) Q quit test scope (run, no print) FFFFFFFFFFFFFFFFFFFFFFFFF space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C toggle comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit step 18 100000000000010010000000000000000000110111011000000001010000100001 step 19 100000000000010010000000000000000000110111011111000001010000100001 step 20 100000000000010010000000000000000000110111011011000001010000100001 step 21 100000000000010010000000000000000000110111011011111001010000100001 step 22 100000000000010010000000000000000000110111011011011001010000100001 step 23 100000000000010010000000000000000000110111011011011110100000100001 step 24 100000000000010010000000000000000000110111011011011010100000100001 step 25 100000000000010010000000000000000000110111011011011010101110100001 step 26 100000000000010010000000000000000000110111011011011010100110100001 step 27 100000000000010010000000000000000000110111011011011010100111111001 step 28 100000000000010010000000000000000000110111011011011010100110111001 step 29 100000000000000010000000000000000001110110011011011010100110111001 step 30 100000000000000000000000000000000001111100011011011010100110111001 step 31 100000000000000000000000000000000001111100011011011010100110111001 step 32 100001000000000000000000000000000001111100011011011010100110111001 step 33 100001100000000000000000000000000001111100011011011010100110111001 step 34 100001100100000000000000000000000001111100011011011010100110111001 step 35 100001100110000000000000000000000001111100011011011010100110111001 step 36 100001100110100000000000000000000001111100011011011010100110111001 step 37 100001100110100100000000000000000001111100011011011010100110111001 step 38 100001100110100100010000000000000001111100011011011010100110111001 step 39 100001100110100100011000000000000001111100011011011010100110111001 step 40 100001100110100100011010000000000001111100011011011010100110111001 step 41 100001100110100100011011000000000001111100011011011010100110111001 step 42 100001100110100100011011010000000001111100011011011010100110111001 step 43 100001100110100100011011011000000001111100011011011010100110111001 step 44 100001100110100100011011011010000001111100011011011010100110111001 step 45 100001100110100100011011011011000001111100011011011010100110111001 step 46 100001100110100100011011011011010001111100011011011010100110111001 step 47 100001100110100100011011011011011001111100011011011010100110111001 step 48 100001100110100100011011011011011101111100011011011010100110111001 step 49 110001100110100100011011011011011100110111011011011010100110111001 step 50 100001100110100100011011011011011101111100011011011010100110111001 step 51 101001100110100100011011011011011100110111011011011010100110111001 step 52 100001100110100100011011011011011101111100011011011010100110111001 step 53 100101100110100100011011011011011100110111011011011010100110111001 step 54 100001100110100100011011011011011101111100011011011010100110111001 step 55 100011100110100100011011011011011100110111011011011010100110111001 step 56 100001100110100100011011011011011101111100011011011010100110111001 step 57 100001110110100100011011011011011100110111011011011010100110111001 step 58 100001100110100100011011011011011101111100011011011010100110111001 step 59 100001101110100100011011011011011100110111011011011010100110111001 step 60 100001100110100100011011011011011101111100011011011010100110111001 step 61 100001100111100100011011011011011100111101011011011010100110111001 step 62 100001100110100100011011011011011101111100011011011010100110111001 step 63 100001100110110100011011011011011100111101011011011010100110111001 step 64 100001100110100100011011011011011101111100011011011010100110111001 step 65 100001100110101100011011011011011101110110011011011010100110111001 step 66 100001100110100100011011011011011101111100011011011010100110111001 step 67 100001100110100110011011011011011101110110011011011010100110111001 step 68 100001100110100100011011011011011101111100011011011010100110111001 step 69 100001100110100101011011011011011101001111011011011010100110111001 step 70 100001100110100100011011011011011101111100011011011010100110111001 step 71 100001100110100100111011011011011101001111011011011010100110111001 step 72 100001100110100100011011011011011101111100011011011010100110111001 step 73 100001100110100100011111011011011101001111011011011010100110111001 step 74 100001100110100100011011011011011101111100011011011010100110111001 step 75 100001100110100100011011111011011101001111011011011010100110111001 step 76 100001100110100100011011011011011101111100011011011010100110111001 step 77 100001100110100100011011011111011101001111011011011010100110111001 step 78 100001100110100100011011011011011101111100011011011010100110111001 step 79 100001100110100100011011011011111101001111011011011010100110111001 step 80 100001100110100100011011011011011101111100011011011010100110111001 step 81 100001100110100100011011011011011111101110011011011010100110111001 step 82 100001100110100100011011011011011101111100011011011010100110111001 step 83 100001100110100100011011011011011101111100011011011010100110110101 step 84 100001100110100100011011011011011101111100011011011010100110110001 step 85 100001100110100100011011011011011101111100011011011010100110100101 step 86 100001100110100100011011011011011101111100011011011010100110100001 step 87 100001100110100100011011011011011101111100011011011010100110100101 step 88 100001100110100100011011011011011101111100011011011010100110100001 SLOT BAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBAABBAAAAAAAAAAAAAABBBBBBBBAB LETTER ALPSLFMDEEMCBFRSPKLEMFHRSCJLJKUHPNMBBNNVVRKRHUTDJUKANJHBTPDFSVDEVU SIDE 121212122121212121111111112212122222112222111221112112212112212212 DIRECTION IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIOOOOOOOIOOIOOIOOIOOOOIOOIIOOIIO changed: 11 step 89 100001100110100100011011011011011101111100011011011010100110100111 fail ^ SLOT BAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBAABBAAAAAAAAAAAAAABBBBBBBBAB LETTER ALPSLFMDEEMCBFRSPKLEMFHRSCJLJKUHPNMBBNNVVRKRHUTDJUKANJHBTPDFSVDEVU SIDE 121212122121212121111111112212122222112222111221112112212112212212 DIRECTION IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIOOOOOOOIOOIOOIOOIOOOOIOOIIOOIIO changed: 0 step 90 100001100110100100011011011011011101111100011011011010100110100011 fail ^ SLOT BAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBAABBAAAAAAAAAAAAAABBBBBBBBAB LETTER ALPSLFMDEEMCBFRSPKLEMFHRSCJLJKUHPNMBBNNVVRKRHUTDJUKANJHBTPDFSVDEVU SIDE 121212122121212121111111112212122222112222111221112112212112212212 DIRECTION IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIOOOOOOOIOOIOOIOOIOOOOIOOIIOOIIO changed: 11 step 91 100001100110100100011011011011011101111100011011011010100110101111 fail ^ SLOT BAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBAABBAAAAAAAAAAAAAABBBBBBBBAB LETTER ALPSLFMDEEMCBFRSPKLEMFHRSCJLJKUHPNMBBNNVVRKRHUTDJUKANJHBTPDFSVDEVU SIDE 121212122121212121111111112212122222112222111221112112212112212212 DIRECTION IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIOOOOOOOIOOIOOIOOIOOOOIOOIIOOIIO changed: 0 step 92 100001100110100100011011011011011101111100011011011010100110101011 fail ^ step 93 100001100110100100011011011011011101111100011011011010100110111111 step 94 100001100110100100011011011011011101111100011011011010100110111011 SLOT BAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBAABBAAAAAAAAAAAAAABBBBBBBBAB LETTER ALPSLFMDEEMCBFRSPKLEMFHRSCJLJKUHPNMBBNNVVRKRHUTDJUKANJHBTPDFSVDEVU SIDE 121212122121212121111111112212122222112222111221112112212112212212 DIRECTION IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIOOOOOOOIOOIOOIOOIOOOOIOOIIOOIIO changed: 10 step 95 100001100110100100011011011011011101111100011011011010100110111101 fail ^ SLOT BAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBAABBAAAAAAAAAAAAAABBBBBBBBAB LETTER ALPSLFMDEEMCBFRSPKLEMFHRSCJLJKUHPNMBBNNVVRKRHUTDJUKANJHBTPDFSVDEVU SIDE 121212122121212121111111112212122222112222111221112112212112212212 DIRECTION IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIOOOOOOOIOOIOOIOOIOOOOIOOIIOOIIO changed: 0 step 96 100001100110100100011011011011011101111100011011011010100110111001 fail ^ SLOT BAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBAABBAAAAAAAAAAAAAABBBBBBBBAB LETTER ALPSLFMDEEMCBFRSPKLEMFHRSCJLJKUHPNMBBNNVVRKRHUTDJUKANJHBTPDFSVDEVU SIDE 121212122121212121111111112212122222112222111221112112212112212212 DIRECTION IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIOOOOOOOIOOIOOIOOIOOOOIOOIIOOIIO changed: 011 step 97 100001100110100100011011011011011101111100011011011010100110110111 fail ^^ SLOT BAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBAABBAAAAAAAAAAAAAABBBBBBBBAB LETTER ALPSLFMDEEMCBFRSPKLEMFHRSCJLJKUHPNMBBNNVVRKRHUTDJUKANJHBTPDFSVDEVU SIDE 121212122121212121111111112212122222112222111221112112212112212212 DIRECTION IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIOOOOOOOIOOIOOIOOIOOOOIOOIIOOIIO changed: 0 step 98 100001100110100100011011011011011101111100011011011010100110110011 fail ^^ SLOT BAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBAABBAAAAAAAAAAAAAABBBBBBBBAB LETTER ALPSLFMDEEMCBFRSPKLEMFHRSCJLJKUHPNMBBNNVVRKRHUTDJUKANJHBTPDFSVDEVU SIDE 121212122121212121111111112212122222112222111221112112212112212212 DIRECTION IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIOOOOOOOIOOIOOIOOIOOOOIOOIIOOIIO changed: 0110 step 99 100001100110100100011011011011011101111100011011011010100110101101 fail ^^ SLOT BAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBAABBAAAAAAAAAAAAAABBBBBBBBAB LETTER ALPSLFMDEEMCBFRSPKLEMFHRSCJLJKUHPNMBBNNVVRKRHUTDJUKANJHBTPDFSVDEVU SIDE 121212122121212121111111112212122222112222111221112112212112212212 DIRECTION IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIOOOOOOOIOOIOOIOOIOOOOIOOIIOOIIO changed: 0 step 100 100001100110100100011011011011011101111100011011011010100110101001 fail ^^ SLOT BAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBAABBAAAAAAAAAAAAAABBBBBBBBAB LETTER ALPSLFMDEEMCBFRSPKLEMFHRSCJLJKUHPNMBBNNVVRKRHUTDJUKANJHBTPDFSVDEVU SIDE 121212122121212121111111112212122222112222111221112112212112212212 DIRECTION IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIOOOOOOOIOOIOOIOOIOOOOIOOIIOOIIO changed: 1011 step 101 100001100110100100011011011011011101111100011011011010100110110111 fail ^^ SLOT BAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBAABBAAAAAAAAAAAAAABBBBBBBBAB LETTER ALPSLFMDEEMCBFRSPKLEMFHRSCJLJKUHPNMBBNNVVRKRHUTDJUKANJHBTPDFSVDEVU SIDE 121212122121212121111111112212122222112222111221112112212112212212 DIRECTION IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIOOOOOOOIOOIOOIOOIOOOOIOOIIOOIIO changed: 0 step 102 100001100110100100011011011011011101111100011011011010100110110011 fail ^^ SLOT BAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBAABBAAAAAAAAAAAAAABBBBBBBBAB LETTER ALPSLFMDEEMCBFRSPKLEMFHRSCJLJKUHPNMBBNNVVRKRHUTDJUKANJHBTPDFSVDEVU SIDE 121212122121212121111111112212122222112222111221112112212112212212 DIRECTION IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIOOOOOOOIOOIOOIOOIOOOOIOOIIOOIIO changed: 011 step 103 100001100110100100011011011011011101111100011011011010100110101111 fail ^^ SLOT BAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBAABBAAAAAAAAAAAAAABBBBBBBBAB LETTER ALPSLFMDEEMCBFRSPKLEMFHRSCJLJKUHPNMBBNNVVRKRHUTDJUKANJHBTPDFSVDEVU SIDE 121212122121212121111111112212122222112222111221112112212112212212 DIRECTION IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIOOOOOOOIOOIOOIOOIOOOOIOOIIOOIIO changed: 0 step 104 100001100110100100011011011011011101111100011011011010100110101011 fail ^^ test 26: *** FAIL *************************** 14 steps failed SLOT BAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBAABBAAAAAAAAAAAAAABBBBBBBBAB LETTER ALPSLFMDEEMCBFRSPKLEMFHRSCJLJKUHPNMBBNNVVRKRHUTDJUKANJHBTPDFSVDEVU SIDE 121212122121212121111111112212122222112222111221112112212112212212 DIRECTION IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIOOOOOOOIOOIOOIOOIOOOOIOOIIOOIIO this fail OO all fails OO was hi 111111111111111111111111111111111111111111111111111111111111111111 rising ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ ^^^^^^^^^^^^^^^^^^^^ ^^^^ falling vvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvv vvvvvvvvvvvvvvvvvvvv vvvv was lo 00000000000000000000000000000000000000 00000000000000000000 0000 total fails 26, total passes 0 space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C toggle comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit step 1 100000000000000000000000000000000001111100011011011010100110101001 step 2 100000000000000000000000000000000001111100100011011010100110101001 step 3 100000000000000000000000000000000001111100000011011010100110101001 step 4 100000000000000000000000000000000001111100000100011010100110101001 step 5 100000000000000000000000000000000001111100000000011010100110101001 step 6 100000000000000000000000000000000001111100000000100010100110101001 step 7 100000000000000000000000000000000001111100000000000010100110101001 step 8 100000000000000000000000000000000001111100000000000101010110101001 step 9 100000000000000000000000000000000001111100000000000001010110101001 step 10 100000000000000000000000000000000001111100000000000001011000101001 step 11 100000000000000000000000000000000001111100000000000001010000101001 step 12 100000000000000000000000000000000001111100000000000001010001100001 step 13 100000000000000000000000000000000001111100000000000001010000100001 step 14 100000000000000000000000000000000001111100000000000001010000100001 step 15 100000000000010000000000000000000000111101000000000001010000100001 step 16 100000000000010010000000000000000000110111000000000001010000100001 step 17 100000000000010010000000000000000000110111111000000001010000100001 step 18 100000000000010010000000000000000000110111011000000001010000100001 step 19 100000000000010010000000000000000000110111011111000001010000100001 step 20 100000000000010010000000000000000000110111011011000001010000100001 step 21 100000000000010010000000000000000000110111011011111001010000100001 step 22 100000000000010010000000000000000000110111011011011001010000100001 step 23 100000000000010010000000000000000000110111011011011110100000100001 step 24 100000000000010010000000000000000000110111011011011010100000100001 step 25 100000000000010010000000000000000000110111011011011010101110100001 step 26 100000000000010010000000000000000000110111011011011010100110100001 step 27 100000000000010010000000000000000000110111011011011010100111111001 step 28 100000000000010010000000000000000000110111011011011010100110111001 step 29 100000000000000010000000000000000001110110011011011010100110111001 step 30 100000000000000000000000000000000001111100011011011010100110111001 step 31 100000000000000000000000000000000001111100011011011010100110111001 step 32 100001000000000000000000000000000001111100011011011010100110111001 step 33 100001100000000000000000000000000001111100011011011010100110111001 step 34 100001100100000000000000000000000001111100011011011010100110111001 step 35 100001100110000000000000000000000001111100011011011010100110111001 step 36 100001100110100000000000000000000001111100011011011010100110111001 step 37 100001100110100100000000000000000001111100011011011010100110111001 step 38 100001100110100100010000000000000001111100011011011010100110111001 step 39 100001100110100100011000000000000001111100011011011010100110111001 step 40 100001100110100100011010000000000001111100011011011010100110111001 step 41 100001100110100100011011000000000001111100011011011010100110111001 step 42 100001100110100100011011010000000001111100011011011010100110111001 step 43 100001100110100100011011011000000001111100011011011010100110111001 step 44 100001100110100100011011011010000001111100011011011010100110111001 step 45 100001100110100100011011011011000001111100011011011010100110111001 step 46 100001100110100100011011011011010001111100011011011010100110111001 step 47 100001100110100100011011011011011001111100011011011010100110111001 step 48 100001100110100100011011011011011101111100011011011010100110111001 step 49 110001100110100100011011011011011100110111011011011010100110111001 step 50 100001100110100100011011011011011101111100011011011010100110111001 step 51 101001100110100100011011011011011100110111011011011010100110111001 step 52 100001100110100100011011011011011101111100011011011010100110111001 step 53 100101100110100100011011011011011100110111011011011010100110111001 step 54 100001100110100100011011011011011101111100011011011010100110111001 step 55 100011100110100100011011011011011100110111011011011010100110111001 step 56 100001100110100100011011011011011101111100011011011010100110111001 step 57 100001110110100100011011011011011100110111011011011010100110111001 step 58 100001100110100100011011011011011101111100011011011010100110111001 step 59 100001101110100100011011011011011100110111011011011010100110111001 step 60 100001100110100100011011011011011101111100011011011010100110111001 step 61 100001100111100100011011011011011100111101011011011010100110111001 step 62 100001100110100100011011011011011101111100011011011010100110111001 step 63 100001100110110100011011011011011100111101011011011010100110111001 step 64 100001100110100100011011011011011101111100011011011010100110111001 step 65 100001100110101100011011011011011101110110011011011010100110111001 step 66 100001100110100100011011011011011101111100011011011010100110111001 step 67 100001100110100110011011011011011101110110011011011010100110111001 step 68 100001100110100100011011011011011101111100011011011010100110111001 step 69 100001100110100101011011011011011101001111011011011010100110111001 step 70 100001100110100100011011011011011101111100011011011010100110111001 step 71 100001100110100100111011011011011101001111011011011010100110111001 step 72 100001100110100100011011011011011101111100011011011010100110111001 step 73 100001100110100100011111011011011101001111011011011010100110111001 step 74 100001100110100100011011011011011101111100011011011010100110111001 step 75 100001100110100100011011111011011101001111011011011010100110111001 step 76 100001100110100100011011011011011101111100011011011010100110111001 step 77 100001100110100100011011011111011101001111011011011010100110111001 step 78 100001100110100100011011011011011101111100011011011010100110111001 step 79 100001100110100100011011011011111101001111011011011010100110111001 step 80 100001100110100100011011011011011101111100011011011010100110111001 step 81 100001100110100100011011011011011111101110011011011010100110111001 step 82 100001100110100100011011011011011101111100011011011010100110111001 step 83 100001100110100100011011011011011101111100011011011010100110110101 step 84 100001100110100100011011011011011101111100011011011010100110110001 step 85 100001100110100100011011011011011101111100011011011010100110100101 step 86 100001100110100100011011011011011101111100011011011010100110100001 step 87 100001100110100100011011011011011101111100011011011010100110100101 step 88 100001100110100100011011011011011101111100011011011010100110100001 SLOT BAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBAABBAAAAAAAAAAAAAABBBBBBBBAB LETTER ALPSLFMDEEMCBFRSPKLEMFHRSCJLJKUHPNMBBNNVVRKRHUTDJUKANJHBTPDFSVDEVU SIDE 121212122121212121111111112212122222112222111221112112212112212212 DIRECTION IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIOOOOOOOIOOIOOIOOIOOOOIOOIIOOIIO changed: 11 step 89 100001100110100100011011011011011101111100011011011010100110100111 fail ^ SLOT BAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBAABBAAAAAAAAAAAAAABBBBBBBBAB LETTER ALPSLFMDEEMCBFRSPKLEMFHRSCJLJKUHPNMBBNNVVRKRHUTDJUKANJHBTPDFSVDEVU SIDE 121212122121212121111111112212122222112222111221112112212112212212 DIRECTION IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIOOOOOOOIOOIOOIOOIOOOOIOOIIOOIIO changed: 0 step 90 100001100110100100011011011011011101111100011011011010100110100011 fail ^ SLOT BAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBAABBAAAAAAAAAAAAAABBBBBBBBAB LETTER ALPSLFMDEEMCBFRSPKLEMFHRSCJLJKUHPNMBBNNVVRKRHUTDJUKANJHBTPDFSVDEVU SIDE 121212122121212121111111112212122222112222111221112112212112212212 DIRECTION IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIOOOOOOOIOOIOOIOOIOOOOIOOIIOOIIO changed: 11 step 91 100001100110100100011011011011011101111100011011011010100110101111 fail ^ SLOT BAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBAABBAAAAAAAAAAAAAABBBBBBBBAB LETTER ALPSLFMDEEMCBFRSPKLEMFHRSCJLJKUHPNMBBNNVVRKRHUTDJUKANJHBTPDFSVDEVU SIDE 121212122121212121111111112212122222112222111221112112212112212212 DIRECTION IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIOOOOOOOIOOIOOIOOIOOOOIOOIIOOIIO changed: 0 step 92 100001100110100100011011011011011101111100011011011010100110101011 fail ^ step 93 100001100110100100011011011011011101111100011011011010100110111111 step 94 100001100110100100011011011011011101111100011011011010100110111011 SLOT BAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBAABBAAAAAAAAAAAAAABBBBBBBBAB LETTER ALPSLFMDEEMCBFRSPKLEMFHRSCJLJKUHPNMBBNNVVRKRHUTDJUKANJHBTPDFSVDEVU SIDE 121212122121212121111111112212122222112222111221112112212112212212 DIRECTION IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIOOOOOOOIOOIOOIOOIOOOOIOOIIOOIIO changed: 10 step 95 100001100110100100011011011011011101111100011011011010100110111101 fail ^ SLOT BAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBAABBAAAAAAAAAAAAAABBBBBBBBAB LETTER ALPSLFMDEEMCBFRSPKLEMFHRSCJLJKUHPNMBBNNVVRKRHUTDJUKANJHBTPDFSVDEVU SIDE 121212122121212121111111112212122222112222111221112112212112212212 DIRECTION IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIOOOOOOOIOOIOOIOOIOOOOIOOIIOOIIO changed: 0 step 96 100001100110100100011011011011011101111100011011011010100110111001 fail ^ SLOT BAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBAABBAAAAAAAAAAAAAABBBBBBBBAB LETTER ALPSLFMDEEMCBFRSPKLEMFHRSCJLJKUHPNMBBNNVVRKRHUTDJUKANJHBTPDFSVDEVU SIDE 121212122121212121111111112212122222112222111221112112212112212212 DIRECTION IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIOOOOOOOIOOIOOIOOIOOOOIOOIIOOIIO changed: 011 step 97 100001100110100100011011011011011101111100011011011010100110110111 fail ^^ SLOT BAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBAABBAAAAAAAAAAAAAABBBBBBBBAB LETTER ALPSLFMDEEMCBFRSPKLEMFHRSCJLJKUHPNMBBNNVVRKRHUTDJUKANJHBTPDFSVDEVU SIDE 121212122121212121111111112212122222112222111221112112212112212212 DIRECTION IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIOOOOOOOIOOIOOIOOIOOOOIOOIIOOIIO changed: 0 step 98 100001100110100100011011011011011101111100011011011010100110110011 fail ^^ SLOT BAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBAABBAAAAAAAAAAAAAABBBBBBBBAB LETTER ALPSLFMDEEMCBFRSPKLEMFHRSCJLJKUHPNMBBNNVVRKRHUTDJUKANJHBTPDFSVDEVU SIDE 121212122121212121111111112212122222112222111221112112212112212212 DIRECTION IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIOOOOOOOIOOIOOIOOIOOOOIOOIIOOIIO changed: 0110 step 99 100001100110100100011011011011011101111100011011011010100110101101 fail ^^ SLOT BAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBAABBAAAAAAAAAAAAAABBBBBBBBAB LETTER ALPSLFMDEEMCBFRSPKLEMFHRSCJLJKUHPNMBBNNVVRKRHUTDJUKANJHBTPDFSVDEVU SIDE 121212122121212121111111112212122222112222111221112112212112212212 DIRECTION IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIOOOOOOOIOOIOOIOOIOOOOIOOIIOOIIO changed: 0 step 100 100001100110100100011011011011011101111100011011011010100110101001 fail ^^ SLOT BAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBAABBAAAAAAAAAAAAAABBBBBBBBAB LETTER ALPSLFMDEEMCBFRSPKLEMFHRSCJLJKUHPNMBBNNVVRKRHUTDJUKANJHBTPDFSVDEVU SIDE 121212122121212121111111112212122222112222111221112112212112212212 DIRECTION IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIOOOOOOOIOOIOOIOOIOOOOIOOIIOOIIO changed: 1011 step 101 100001100110100100011011011011011101111100011011011010100110110111 fail ^^ SLOT BAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBAABBAAAAAAAAAAAAAABBBBBBBBAB LETTER ALPSLFMDEEMCBFRSPKLEMFHRSCJLJKUHPNMBBNNVVRKRHUTDJUKANJHBTPDFSVDEVU SIDE 121212122121212121111111112212122222112222111221112112212112212212 DIRECTION IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIOOOOOOOIOOIOOIOOIOOOOIOOIIOOIIO changed: 0 step 102 100001100110100100011011011011011101111100011011011010100110110011 fail ^^ SLOT BAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBAABBAAAAAAAAAAAAAABBBBBBBBAB LETTER ALPSLFMDEEMCBFRSPKLEMFHRSCJLJKUHPNMBBNNVVRKRHUTDJUKANJHBTPDFSVDEVU SIDE 121212122121212121111111112212122222112222111221112112212112212212 DIRECTION IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIOOOOOOOIOOIOOIOOIOOOOIOOIIOOIIO changed: 011 step 103 100001100110100100011011011011011101111100011011011010100110101111 fail ^^ SLOT BAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBAABBAAAAAAAAAAAAAABBBBBBBBAB LETTER ALPSLFMDEEMCBFRSPKLEMFHRSCJLJKUHPNMBBNNVVRKRHUTDJUKANJHBTPDFSVDEVU SIDE 121212122121212121111111112212122222112222111221112112212112212212 DIRECTION IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIOOOOOOOIOOIOOIOOIOOOOIOOIIOOIIO changed: 0 step 104 100001100110100100011011011011011101111100011011011010100110101011 fail ^^ test 27: *** FAIL *************************** 14 steps failed SLOT BAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBAABBAAAAAAAAAAAAAABBBBBBBBAB LETTER ALPSLFMDEEMCBFRSPKLEMFHRSCJLJKUHPNMBBNNVVRKRHUTDJUKANJHBTPDFSVDEVU SIDE 121212122121212121111111112212122222112222111221112112212112212212 DIRECTION IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIOOOOOOOIOOIOOIOOIOOOOIOOIIOOIIO this fail OO all fails OO was hi 111111111111111111111111111111111111111111111111111111111111111111 rising ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ ^^^^^^^^^^^^^^^^^^^^ ^^^^ falling vvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvv vvvvvvvvvvvvvvvvvvvv vvvv was lo 00000000000000000000000000000000000000 00000000000000000000 0000 total fails 27, total passes 0 space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C toggle comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit step 1 100000000000000000000000000000000001111100011011011010100110101001 step 2 100000000000000000000000000000000001111100100011011010100110101001 step 3 100000000000000000000000000000000001111100000011011010100110101001 step 4 100000000000000000000000000000000001111100000100011010100110101001 step 5 100000000000000000000000000000000001111100000000011010100110101001 step 6 100000000000000000000000000000000001111100000000100010100110101001 step 7 100000000000000000000000000000000001111100000000000010100110101001 step 8 100000000000000000000000000000000001111100000000000101010110101001 step 9 100000000000000000000000000000000001111100000000000001010110101001 step 10 100000000000000000000000000000000001111100000000000001011000101001 step 11 100000000000000000000000000000000001111100000000000001010000101001 step 12 100000000000000000000000000000000001111100000000000001010001100001 step 13 100000000000000000000000000000000001111100000000000001010000100001 step 14 100000000000000000000000000000000001111100000000000001010000100001 step 15 100000000000010000000000000000000000111101000000000001010000100001 step 16 100000000000010010000000000000000000110111000000000001010000100001 step 17 100000000000010010000000000000000000110111111000000001010000100001 step 18 100000000000010010000000000000000000110111011000000001010000100001 step 19 100000000000010010000000000000000000110111011111000001010000100001 step 20 100000000000010010000000000000000000110111011011000001010000100001 step 21 100000000000010010000000000000000000110111011011111001010000100001 step 22 100000000000010010000000000000000000110111011011011001010000100001 step 23 100000000000010010000000000000000000110111011011011110100000100001 step 24 100000000000010010000000000000000000110111011011011010100000100001 step 25 100000000000010010000000000000000000110111011011011010101110100001 step 26 100000000000010010000000000000000000110111011011011010100110100001 step 27 100000000000010010000000000000000000110111011011011010100111111001 step 28 100000000000010010000000000000000000110111011011011010100110111001 step 29 100000000000000010000000000000000001110110011011011010100110111001 step 30 100000000000000000000000000000000001111100011011011010100110111001 step 31 100000000000000000000000000000000001111100011011011010100110111001 step 32 100001000000000000000000000000000001111100011011011010100110111001 step 33 100001100000000000000000000000000001111100011011011010100110111001 step 34 100001100100000000000000000000000001111100011011011010100110111001 step 35 100001100110000000000000000000000001111100011011011010100110111001 step 36 100001100110100000000000000000000001111100011011011010100110111001 step 37 100001100110100100000000000000000001111100011011011010100110111001 step 38 100001100110100100010000000000000001111100011011011010100110111001 step 39 100001100110100100011000000000000001111100011011011010100110111001 step 40 100001100110100100011010000000000001111100011011011010100110111001 step 41 100001100110100100011011000000000001111100011011011010100110111001 step 42 100001100110100100011011010000000001111100011011011010100110111001 step 43 100001100110100100011011011000000001111100011011011010100110111001 step 44 100001100110100100011011011010000001111100011011011010100110111001 step 45 100001100110100100011011011011000001111100011011011010100110111001 step 46 100001100110100100011011011011010001111100011011011010100110111001 step 47 100001100110100100011011011011011001111100011011011010100110111001 step 48 100001100110100100011011011011011101111100011011011010100110111001 step 49 110001100110100100011011011011011100110111011011011010100110111001 step 50 100001100110100100011011011011011101111100011011011010100110111001 step 51 101001100110100100011011011011011100110111011011011010100110111001 step 52 100001100110100100011011011011011101111100011011011010100110111001 step 53 100101100110100100011011011011011100110111011011011010100110111001 step 54 100001100110100100011011011011011101111100011011011010100110111001 step 55 100011100110100100011011011011011100110111011011011010100110111001 step 56 100001100110100100011011011011011101111100011011011010100110111001 step 57 100001110110100100011011011011011100110111011011011010100110111001 step 58 100001100110100100011011011011011101111100011011011010100110111001 step 59 100001101110100100011011011011011100110111011011011010100110111001 step 60 100001100110100100011011011011011101111100011011011010100110111001 step 61 100001100111100100011011011011011100111101011011011010100110111001 step 62 100001100110100100011011011011011101111100011011011010100110111001 step 63 100001100110110100011011011011011100111101011011011010100110111001 step 64 100001100110100100011011011011011101111100011011011010100110111001 step 65 100001100110101100011011011011011101110110011011011010100110111001 step 66 100001100110100100011011011011011101111100011011011010100110111001 step 67 100001100110100110011011011011011101110110011011011010100110111001 step 68 100001100110100100011011011011011101111100011011011010100110111001 step 69 100001100110100101011011011011011101001111011011011010100110111001 step 70 100001100110100100011011011011011101111100011011011010100110111001 step 71 100001100110100100111011011011011101001111011011011010100110111001 step 72 100001100110100100011011011011011101111100011011011010100110111001 step 73 100001100110100100011111011011011101001111011011011010100110111001 step 74 100001100110100100011011011011011101111100011011011010100110111001 step 75 100001100110100100011011111011011101001111011011011010100110111001 step 76 100001100110100100011011011011011101111100011011011010100110111001 step 77 100001100110100100011011011111011101001111011011011010100110111001 step 78 100001100110100100011011011011011101111100011011011010100110111001 step 79 100001100110100100011011011011111101001111011011011010100110111001 step 80 100001100110100100011011011011011101111100011011011010100110111001 step 81 100001100110100100011011011011011111101110011011011010100110111001 step 82 100001100110100100011011011011011101111100011011011010100110111001 step 83 100001100110100100011011011011011101111100011011011010100110110101 step 84 100001100110100100011011011011011101111100011011011010100110110001 step 85 100001100110100100011011011011011101111100011011011010100110100101 step 86 100001100110100100011011011011011101111100011011011010100110100001 step 87 100001100110100100011011011011011101111100011011011010100110100101 step 88 100001100110100100011011011011011101111100011011011010100110100001 SLOT BAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBAABBAAAAAAAAAAAAAABBBBBBBBAB LETTER ALPSLFMDEEMCBFRSPKLEMFHRSCJLJKUHPNMBBNNVVRKRHUTDJUKANJHBTPDFSVDEVU SIDE 121212122121212121111111112212122222112222111221112112212112212212 DIRECTION IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIOOOOOOOIOOIOOIOOIOOOOIOOIIOOIIO changed: 11 step 89 100001100110100100011011011011011101111100011011011010100110100111 fail ^ SLOT BAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBAABBAAAAAAAAAAAAAABBBBBBBBAB LETTER ALPSLFMDEEMCBFRSPKLEMFHRSCJLJKUHPNMBBNNVVRKRHUTDJUKANJHBTPDFSVDEVU SIDE 121212122121212121111111112212122222112222111221112112212112212212 DIRECTION IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIOOOOOOOIOOIOOIOOIOOOOIOOIIOOIIO changed: 0 step 90 100001100110100100011011011011011101111100011011011010100110100011 fail ^ SLOT BAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBAABBAAAAAAAAAAAAAABBBBBBBBAB LETTER ALPSLFMDEEMCBFRSPKLEMFHRSCJLJKUHPNMBBNNVVRKRHUTDJUKANJHBTPDFSVDEVU SIDE 121212122121212121111111112212122222112222111221112112212112212212 DIRECTION IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIOOOOOOOIOOIOOIOOIOOOOIOOIIOOIIO changed: 11 step 91 100001100110100100011011011011011101111100011011011010100110101111 fail ^ SLOT BAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBAABBAAAAAAAAAAAAAABBBBBBBBAB LETTER ALPSLFMDEEMCBFRSPKLEMFHRSCJLJKUHPNMBBNNVVRKRHUTDJUKANJHBTPDFSVDEVU SIDE 121212122121212121111111112212122222112222111221112112212112212212 DIRECTION IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIOOOOOOOIOOIOOIOOIOOOOIOOIIOOIIO changed: 0 step 92 100001100110100100011011011011011101111100011011011010100110101011 fail ^ step 93 100001100110100100011011011011011101111100011011011010100110111111 step 94 100001100110100100011011011011011101111100011011011010100110111011 SLOT BAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBAABBAAAAAAAAAAAAAABBBBBBBBAB LETTER ALPSLFMDEEMCBFRSPKLEMFHRSCJLJKUHPNMBBNNVVRKRHUTDJUKANJHBTPDFSVDEVU SIDE 121212122121212121111111112212122222112222111221112112212112212212 DIRECTION IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIOOOOOOOIOOIOOIOOIOOOOIOOIIOOIIO changed: 10 step 95 100001100110100100011011011011011101111100011011011010100110111101 fail ^ SLOT BAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBAABBAAAAAAAAAAAAAABBBBBBBBAB LETTER ALPSLFMDEEMCBFRSPKLEMFHRSCJLJKUHPNMBBNNVVRKRHUTDJUKANJHBTPDFSVDEVU SIDE 121212122121212121111111112212122222112222111221112112212112212212 DIRECTION IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIOOOOOOOIOOIOOIOOIOOOOIOOIIOOIIO changed: 0 step 96 100001100110100100011011011011011101111100011011011010100110111001 fail ^ SLOT BAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBAABBAAAAAAAAAAAAAABBBBBBBBAB LETTER ALPSLFMDEEMCBFRSPKLEMFHRSCJLJKUHPNMBBNNVVRKRHUTDJUKANJHBTPDFSVDEVU SIDE 121212122121212121111111112212122222112222111221112112212112212212 DIRECTION IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIOOOOOOOIOOIOOIOOIOOOOIOOIIOOIIO changed: 011 step 97 100001100110100100011011011011011101111100011011011010100110110111 fail ^^ SLOT BAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBAABBAAAAAAAAAAAAAABBBBBBBBAB LETTER ALPSLFMDEEMCBFRSPKLEMFHRSCJLJKUHPNMBBNNVVRKRHUTDJUKANJHBTPDFSVDEVU SIDE 121212122121212121111111112212122222112222111221112112212112212212 DIRECTION IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIOOOOOOOIOOIOOIOOIOOOOIOOIIOOIIO changed: 0 step 98 100001100110100100011011011011011101111100011011011010100110110011 fail ^^ SLOT BAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBAABBAAAAAAAAAAAAAABBBBBBBBAB LETTER ALPSLFMDEEMCBFRSPKLEMFHRSCJLJKUHPNMBBNNVVRKRHUTDJUKANJHBTPDFSVDEVU SIDE 121212122121212121111111112212122222112222111221112112212112212212 DIRECTION IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIOOOOOOOIOOIOOIOOIOOOOIOOIIOOIIO changed: 0110 step 99 100001100110100100011011011011011101111100011011011010100110101101 fail ^^ SLOT BAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBAABBAAAAAAAAAAAAAABBBBBBBBAB LETTER ALPSLFMDEEMCBFRSPKLEMFHRSCJLJKUHPNMBBNNVVRKRHUTDJUKANJHBTPDFSVDEVU SIDE 121212122121212121111111112212122222112222111221112112212112212212 DIRECTION IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIOOOOOOOIOOIOOIOOIOOOOIOOIIOOIIO changed: 0 step 100 100001100110100100011011011011011101111100011011011010100110101001 fail ^^ SLOT BAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBAABBAAAAAAAAAAAAAABBBBBBBBAB LETTER ALPSLFMDEEMCBFRSPKLEMFHRSCJLJKUHPNMBBNNVVRKRHUTDJUKANJHBTPDFSVDEVU SIDE 121212122121212121111111112212122222112222111221112112212112212212 DIRECTION IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIOOOOOOOIOOIOOIOOIOOOOIOOIIOOIIO changed: 1011 step 101 100001100110100100011011011011011101111100011011011010100110110111 fail ^^ SLOT BAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBAABBAAAAAAAAAAAAAABBBBBBBBAB LETTER ALPSLFMDEEMCBFRSPKLEMFHRSCJLJKUHPNMBBNNVVRKRHUTDJUKANJHBTPDFSVDEVU SIDE 121212122121212121111111112212122222112222111221112112212112212212 DIRECTION IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIOOOOOOOIOOIOOIOOIOOOOIOOIIOOIIO changed: 0 step 102 100001100110100100011011011011011101111100011011011010100110110011 fail ^^ SLOT BAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBAABBAAAAAAAAAAAAAABBBBBBBBAB LETTER ALPSLFMDEEMCBFRSPKLEMFHRSCJLJKUHPNMBBNNVVRKRHUTDJUKANJHBTPDFSVDEVU SIDE 121212122121212121111111112212122222112222111221112112212112212212 DIRECTION IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIOOOOOOOIOOIOOIOOIOOOOIOOIIOOIIO changed: 011 step 103 100001100110100100011011011011011101111100011011011010100110101111 fail ^^ SLOT BAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBAABBAAAAAAAAAAAAAABBBBBBBBAB LETTER ALPSLFMDEEMCBFRSPKLEMFHRSCJLJKUHPNMBBNNVVRKRHUTDJUKANJHBTPDFSVDEVU SIDE 121212122121212121111111112212122222112222111221112112212112212212 DIRECTION IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIOOOOOOOIOOIOOIOOIOOOOIOOIIOOIIO changed: 0 step 104 100001100110100100011011011011011101111100011011011010100110101011 fail ^^ test 28: *** FAIL *************************** 14 steps failed SLOT BAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBAABBAAAAAAAAAAAAAABBBBBBBBAB LETTER ALPSLFMDEEMCBFRSPKLEMFHRSCJLJKUHPNMBBNNVVRKRHUTDJUKANJHBTPDFSVDEVU SIDE 121212122121212121111111112212122222112222111221112112212112212212 DIRECTION IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIOOOOOOOIOOIOOIOOIOOOOIOOIIOOIIO this fail OO all fails OO was hi 111111111111111111111111111111111111111111111111111111111111111111 rising ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ ^^^^^^^^^^^^^^^^^^^^ ^^^^ falling vvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvv vvvvvvvvvvvvvvvvvvvv vvvv was lo 00000000000000000000000000000000000000 00000000000000000000 0000 total fails 28, total passes 0 space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C toggle comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit step 1 100000000000000000000000000000000001111100011011011010100110101001 step 2 100000000000000000000000000000000001111100100011011010100110101001 step 3 100000000000000000000000000000000001111100000011011010100110101001 step 4 100000000000000000000000000000000001111100000100011010100110101001 step 5 100000000000000000000000000000000001111100000000011010100110101001 step 6 100000000000000000000000000000000001111100000000100010100110101001 step 7 100000000000000000000000000000000001111100000000000010100110101001 step 8 100000000000000000000000000000000001111100000000000101010110101001 step 9 100000000000000000000000000000000001111100000000000001010110101001 step 10 100000000000000000000000000000000001111100000000000001011000101001 step 11 100000000000000000000000000000000001111100000000000001010000101001 step 12 100000000000000000000000000000000001111100000000000001010001100001 step 13 100000000000000000000000000000000001111100000000000001010000100001 step 14 100000000000000000000000000000000001111100000000000001010000100001 step 15 100000000000010000000000000000000000111101000000000001010000100001 step 16 100000000000010010000000000000000000110111000000000001010000100001 step 17 100000000000010010000000000000000000110111111000000001010000100001 step 18 100000000000010010000000000000000000110111011000000001010000100001 step 19 100000000000010010000000000000000000110111011111000001010000100001 step 20 100000000000010010000000000000000000110111011011000001010000100001 step 21 100000000000010010000000000000000000110111011011111001010000100001 step 22 100000000000010010000000000000000000110111011011011001010000100001 step 23 100000000000010010000000000000000000110111011011011110100000100001 step 24 100000000000010010000000000000000000110111011011011010100000100001 step 25 100000000000010010000000000000000000110111011011011010101110100001 step 26 100000000000010010000000000000000000110111011011011010100110100001 step 27 100000000000010010000000000000000000110111011011011010100111111001 step 28 100000000000010010000000000000000000110111011011011010100110111001 step 29 100000000000000010000000000000000001110110011011011010100110111001 step 30 100000000000000000000000000000000001111100011011011010100110111001 step 31 100000000000000000000000000000000001111100011011011010100110111001 step 32 100001000000000000000000000000000001111100011011011010100110111001 step 33 100001100000000000000000000000000001111100011011011010100110111001 step 34 100001100100000000000000000000000001111100011011011010100110111001 step 35 100001100110000000000000000000000001111100011011011010100110111001 step 36 100001100110100000000000000000000001111100011011011010100110111001 step 37 100001100110100100000000000000000001111100011011011010100110111001 step 38 100001100110100100010000000000000001111100011011011010100110111001 step 39 100001100110100100011000000000000001111100011011011010100110111001 step 40 100001100110100100011010000000000001111100011011011010100110111001 step 41 100001100110100100011011000000000001111100011011011010100110111001 step 42 100001100110100100011011010000000001111100011011011010100110111001 step 43 100001100110100100011011011000000001111100011011011010100110111001 step 44 100001100110100100011011011010000001111100011011011010100110111001 step 45 100001100110100100011011011011000001111100011011011010100110111001 step 46 100001100110100100011011011011010001111100011011011010100110111001 step 47 100001100110100100011011011011011001111100011011011010100110111001 step 48 100001100110100100011011011011011101111100011011011010100110111001 step 49 110001100110100100011011011011011100110111011011011010100110111001 step 50 100001100110100100011011011011011101111100011011011010100110111001 step 51 101001100110100100011011011011011100110111011011011010100110111001 step 52 100001100110100100011011011011011101111100011011011010100110111001 step 53 100101100110100100011011011011011100110111011011011010100110111001 step 54 100001100110100100011011011011011101111100011011011010100110111001 step 55 100011100110100100011011011011011100110111011011011010100110111001 step 56 100001100110100100011011011011011101111100011011011010100110111001 step 57 100001110110100100011011011011011100110111011011011010100110111001 step 58 100001100110100100011011011011011101111100011011011010100110111001 step 59 100001101110100100011011011011011100110111011011011010100110111001 step 60 100001100110100100011011011011011101111100011011011010100110111001 step 61 100001100111100100011011011011011100111101011011011010100110111001 step 62 100001100110100100011011011011011101111100011011011010100110111001 step 63 100001100110110100011011011011011100111101011011011010100110111001 step 64 100001100110100100011011011011011101111100011011011010100110111001 step 65 100001100110101100011011011011011101110110011011011010100110111001 step 66 100001100110100100011011011011011101111100011011011010100110111001 step 67 100001100110100110011011011011011101110110011011011010100110111001 step 68 100001100110100100011011011011011101111100011011011010100110111001 step 69 100001100110100101011011011011011101001111011011011010100110111001 step 70 100001100110100100011011011011011101111100011011011010100110111001 step 71 100001100110100100111011011011011101001111011011011010100110111001 step 72 100001100110100100011011011011011101111100011011011010100110111001 step 73 100001100110100100011111011011011101001111011011011010100110111001 step 74 100001100110100100011011011011011101111100011011011010100110111001 step 75 100001100110100100011011111011011101001111011011011010100110111001 step 76 100001100110100100011011011011011101111100011011011010100110111001 step 77 100001100110100100011011011111011101001111011011011010100110111001 step 78 100001100110100100011011011011011101111100011011011010100110111001 step 79 100001100110100100011011011011111101001111011011011010100110111001 step 80 100001100110100100011011011011011101111100011011011010100110111001 step 81 100001100110100100011011011011011111101110011011011010100110111001 step 82 100001100110100100011011011011011101111100011011011010100110111001 step 83 100001100110100100011011011011011101111100011011011010100110110101 step 84 100001100110100100011011011011011101111100011011011010100110110001 step 85 100001100110100100011011011011011101111100011011011010100110100101 step 86 100001100110100100011011011011011101111100011011011010100110100001 step 87 100001100110100100011011011011011101111100011011011010100110100101 step 88 100001100110100100011011011011011101111100011011011010100110100001 SLOT BAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBAABBAAAAAAAAAAAAAABBBBBBBBAB LETTER ALPSLFMDEEMCBFRSPKLEMFHRSCJLJKUHPNMBBNNVVRKRHUTDJUKANJHBTPDFSVDEVU SIDE 121212122121212121111111112212122222112222111221112112212112212212 DIRECTION IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIOOOOOOOIOOIOOIOOIOOOOIOOIIOOIIO changed: 11 step 89 100001100110100100011011011011011101111100011011011010100110100111 fail ^ SLOT BAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBAABBAAAAAAAAAAAAAABBBBBBBBAB LETTER ALPSLFMDEEMCBFRSPKLEMFHRSCJLJKUHPNMBBNNVVRKRHUTDJUKANJHBTPDFSVDEVU SIDE 121212122121212121111111112212122222112222111221112112212112212212 DIRECTION IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIOOOOOOOIOOIOOIOOIOOOOIOOIIOOIIO changed: 0 step 90 100001100110100100011011011011011101111100011011011010100110100011 fail ^ SLOT BAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBAABBAAAAAAAAAAAAAABBBBBBBBAB LETTER ALPSLFMDEEMCBFRSPKLEMFHRSCJLJKUHPNMBBNNVVRKRHUTDJUKANJHBTPDFSVDEVU SIDE 121212122121212121111111112212122222112222111221112112212112212212 DIRECTION IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIOOOOOOOIOOIOOIOOIOOOOIOOIIOOIIO changed: 11 step 91 100001100110100100011011011011011101111100011011011010100110101111 fail ^ SLOT BAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBAABBAAAAAAAAAAAAAABBBBBBBBAB LETTER ALPSLFMDEEMCBFRSPKLEMFHRSCJLJKUHPNMBBNNVVRKRHUTDJUKANJHBTPDFSVDEVU SIDE 121212122121212121111111112212122222112222111221112112212112212212 DIRECTION IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIOOOOOOOIOOIOOIOOIOOOOIOOIIOOIIO changed: 0 step 92 100001100110100100011011011011011101111100011011011010100110101011 fail ^ step 93 100001100110100100011011011011011101111100011011011010100110111111 step 94 100001100110100100011011011011011101111100011011011010100110111011 SLOT BAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBAABBAAAAAAAAAAAAAABBBBBBBBAB LETTER ALPSLFMDEEMCBFRSPKLEMFHRSCJLJKUHPNMBBNNVVRKRHUTDJUKANJHBTPDFSVDEVU SIDE 121212122121212121111111112212122222112222111221112112212112212212 DIRECTION IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIOOOOOOOIOOIOOIOOIOOOOIOOIIOOIIO changed: 10 step 95 100001100110100100011011011011011101111100011011011010100110111101 fail ^ SLOT BAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBAABBAAAAAAAAAAAAAABBBBBBBBAB LETTER ALPSLFMDEEMCBFRSPKLEMFHRSCJLJKUHPNMBBNNVVRKRHUTDJUKANJHBTPDFSVDEVU SIDE 121212122121212121111111112212122222112222111221112112212112212212 DIRECTION IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIOOOOOOOIOOIOOIOOIOOOOIOOIIOOIIO changed: 0 step 96 100001100110100100011011011011011101111100011011011010100110111001 fail ^ SLOT BAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBAABBAAAAAAAAAAAAAABBBBBBBBAB LETTER ALPSLFMDEEMCBFRSPKLEMFHRSCJLJKUHPNMBBNNVVRKRHUTDJUKANJHBTPDFSVDEVU SIDE 121212122121212121111111112212122222112222111221112112212112212212 DIRECTION IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIOOOOOOOIOOIOOIOOIOOOOIOOIIOOIIO changed: 011 step 97 100001100110100100011011011011011101111100011011011010100110110111 fail ^^ SLOT BAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBAABBAAAAAAAAAAAAAABBBBBBBBAB LETTER ALPSLFMDEEMCBFRSPKLEMFHRSCJLJKUHPNMBBNNVVRKRHUTDJUKANJHBTPDFSVDEVU SIDE 121212122121212121111111112212122222112222111221112112212112212212 DIRECTION IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIOOOOOOOIOOIOOIOOIOOOOIOOIIOOIIO changed: 0 step 98 100001100110100100011011011011011101111100011011011010100110110011 fail ^^ SLOT BAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBAABBAAAAAAAAAAAAAABBBBBBBBAB LETTER ALPSLFMDEEMCBFRSPKLEMFHRSCJLJKUHPNMBBNNVVRKRHUTDJUKANJHBTPDFSVDEVU SIDE 121212122121212121111111112212122222112222111221112112212112212212 DIRECTION IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIOOOOOOOIOOIOOIOOIOOOOIOOIIOOIIO changed: 0110 step 99 100001100110100100011011011011011101111100011011011010100110101101 fail ^^ SLOT BAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBAABBAAAAAAAAAAAAAABBBBBBBBAB LETTER ALPSLFMDEEMCBFRSPKLEMFHRSCJLJKUHPNMBBNNVVRKRHUTDJUKANJHBTPDFSVDEVU SIDE 121212122121212121111111112212122222112222111221112112212112212212 DIRECTION IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIOOOOOOOIOOIOOIOOIOOOOIOOIIOOIIO changed: 0 step 100 100001100110100100011011011011011101111100011011011010100110101001 fail ^^ SLOT BAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBAABBAAAAAAAAAAAAAABBBBBBBBAB LETTER ALPSLFMDEEMCBFRSPKLEMFHRSCJLJKUHPNMBBNNVVRKRHUTDJUKANJHBTPDFSVDEVU SIDE 121212122121212121111111112212122222112222111221112112212112212212 DIRECTION IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIOOOOOOOIOOIOOIOOIOOOOIOOIIOOIIO changed: 1011 step 101 100001100110100100011011011011011101111100011011011010100110110111 fail ^^ SLOT BAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBAABBAAAAAAAAAAAAAABBBBBBBBAB LETTER ALPSLFMDEEMCBFRSPKLEMFHRSCJLJKUHPNMBBNNVVRKRHUTDJUKANJHBTPDFSVDEVU SIDE 121212122121212121111111112212122222112222111221112112212112212212 DIRECTION IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIOOOOOOOIOOIOOIOOIOOOOIOOIIOOIIO changed: 0 step 102 100001100110100100011011011011011101111100011011011010100110110011 fail ^^ SLOT BAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBAABBAAAAAAAAAAAAAABBBBBBBBAB LETTER ALPSLFMDEEMCBFRSPKLEMFHRSCJLJKUHPNMBBNNVVRKRHUTDJUKANJHBTPDFSVDEVU SIDE 121212122121212121111111112212122222112222111221112112212112212212 DIRECTION IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIOOOOOOOIOOIOOIOOIOOOOIOOIIOOIIO changed: 011 step 103 100001100110100100011011011011011101111100011011011010100110101111 fail ^^ SLOT BAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBAABBAAAAAAAAAAAAAABBBBBBBBAB LETTER ALPSLFMDEEMCBFRSPKLEMFHRSCJLJKUHPNMBBNNVVRKRHUTDJUKANJHBTPDFSVDEVU SIDE 121212122121212121111111112212122222112222111221112112212112212212 DIRECTION IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIOOOOOOOIOOIOOIOOIOOOOIOOIIOOIIO changed: 0 step 104 100001100110100100011011011011011101111100011011011010100110101011 fail ^^ test 29: *** FAIL *************************** 14 steps failed SLOT BAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBAABBAAAAAAAAAAAAAABBBBBBBBAB LETTER ALPSLFMDEEMCBFRSPKLEMFHRSCJLJKUHPNMBBNNVVRKRHUTDJUKANJHBTPDFSVDEVU SIDE 121212122121212121111111112212122222112222111221112112212112212212 DIRECTION IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIOOOOOOOIOOIOOIOOIOOOOIOOIIOOIIO this fail OO all fails OO was hi 111111111111111111111111111111111111111111111111111111111111111111 rising ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ ^^^^^^^^^^^^^^^^^^^^ ^^^^ falling vvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvv vvvvvvvvvvvvvvvvvvvv vvvv was lo 00000000000000000000000000000000000000 00000000000000000000 0000 total fails 29, total passes 0 space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C toggle comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT BAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBAABBAAAAAAAAAAAAAABBBBBBBBAB LETTER ALPSLFMDEEMCBFRSPKLEMFHRSCJLJKUHPNMBBNNVVRKRHUTDJUKANJHBTPDFSVDEVU SIDE 121212122121212121111111112212122222112222111221112112212112212212 DIRECTION IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIOOOOOOOIOOIOOIOOIOOOOIOOIIOOIIO all fails OO was lo 00000000000000000000000000000000000000 00000000000000000000 0000 falling vvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvv vvvvvvvvvvvvvvvvvvvv vvvv rising ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ ^^^^^^^^^^^^^^^^^^^^ ^^^^ was hi 111111111111111111111111111111111111111111111111111111111111111111 total fails 29, total passes 0 Main menu Thu Aug 20 15:37:04 2015 test file is: tests\m222.new delay is: 0 trigger is: 1 1 read test file 2 set test delay 3 set test trigger 4 run test 5 output loading test 8 diags 9 exit UUT power is okay Thu Aug 20 15:37:26 2015 space single step O run once (one test, all steps) F run, stop on fail G go (run tests N run, stop on fail, no print S scope (run, no print) C toggle comment printout + increase speed (less delay) - decrease speed (more delay)(slower) Q quit test step 1 100000000000000000000000000000000001111100010011011010100110111001 step 2 100000000000000000000000000000000001111100100011011010100110111001 step 3 100000000000000000000000000000000001111100000011011010100110111001 step 4 100000000000000000000000000000000001111100000100011010100110111001 step 5 100000000000000000000000000000000001111100000000011010100110111001 step 6 100000000000000000000000000000000001111100000000100010100110111001 step 7 100000000000000000000000000000000001111100000000000010100110111001 step 8 100000000000000000000000000000000001111100000000000101010110111001 step 9 100000000000000000000000000000000001111100000000000001010110111001 step 10 100000000000000000000000000000000001111100000000000001011000111001 step 11 100000000000000000000000000000000001111100000000000001010000111001 step 12 100000000000000000000000000000000001111100000000000001010001100001 step 13 100000000000000000000000000000000001111100000000000001010000100001 step 14 100000000000000000000000000000000001111100000000000001010000100001 step 15 100000000000010000000000000000000000111101000000000001010000100001 step 16 100000000000010010000000000000000000110111000000000001010000100001 step 17 100000000000010010000000000000000000110111111000000001010000100001 step 18 100000000000010010000000000000000000110111011000000001010000100001 step 19 100000000000010010000000000000000000110111011111000001010000100001 step 20 100000000000010010000000000000000000110111011011000001010000100001 step 21 100000000000010010000000000000000000110111011011111001010000100001 step 22 100000000000010010000000000000000000110111011011011001010000100001 step 23 100000000000010010000000000000000000110111011011011110100000100001 step 24 100000000000010010000000000000000000110111011011011010100000100001 step 25 100000000000010010000000000000000000110111011011011010101110100001 step 26 100000000000010010000000000000000000110111011011011010100110100001 step 27 100000000000010010000000000000000000110111011011011010100111111001 step 28 100000000000010010000000000000000000110111011011011010100110111001 step 29 100000000000000010000000000000000001110110011011011010100110111001 step 30 100000000000000000000000000000000001111100011011011010100110111001 step 31 100000000000000000000000000000000001111100011011011010100110111001 step 32 100001000000000000000000000000000001111100011011011010100110111001 step 33 100001100000000000000000000000000001111100011011011010100110111001 step 34 100001100100000000000000000000000001111100011011011010100110111001 step 35 100001100110000000000000000000000001111100011011011010100110111001 step 36 100001100110100000000000000000000001111100011011011010100110111001 step 37 100001100110100100000000000000000001111100011011011010100110111001 step 38 100001100110100100010000000000000001111100011011011010100110111001 step 39 100001100110100100011000000000000001111100011011011010100110111001 step 40 100001100110100100011010000000000001111100011011011010100110111001 step 41 100001100110100100011011000000000001111100011011011010100110111001 step 42 100001100110100100011011010000000001111100011011011010100110111001 step 43 100001100110100100011011011000000001111100011011011010100110111001 step 44 100001100110100100011011011010000001111100011011011010100110111001 step 45 100001100110100100011011011011000001111100011011011010100110111001 step 46 100001100110100100011011011011010001111100011011011010100110111001 step 47 100001100110100100011011011011011001111100011011011010100110111001 step 48 100001100110100100011011011011011101111100011011011010100110111001 step 49 110001100110100100011011011011011100110111011011011010100110111001 step 50 100001100110100100011011011011011101111100011011011010100110111001 step 51 101001100110100100011011011011011100110111011011011010100110111001 step 52 100001100110100100011011011011011101111100011011011010100110111001 step 53 100101100110100100011011011011011100110111011011011010100110111001 step 54 100001100110100100011011011011011101111100011011011010100110111001 step 55 100011100110100100011011011011011100110111011011011010100110111001 step 56 100001100110100100011011011011011101111100011011011010100110111001 step 57 100001110110100100011011011011011100110111011011011010100110111001 step 58 100001100110100100011011011011011101111100011011011010100110111001 step 59 100001101110100100011011011011011100110111011011011010100110111001 step 60 100001100110100100011011011011011101111100011011011010100110111001 step 61 100001100111100100011011011011011100111101011011011010100110111001 step 62 100001100110100100011011011011011101111100011011011010100110111001 step 63 100001100110110100011011011011011100111101011011011010100110111001 step 64 100001100110100100011011011011011101111100011011011010100110111001 step 65 100001100110101100011011011011011101110110011011011010100110111001 step 66 100001100110100100011011011011011101111100011011011010100110111001 step 67 100001100110100110011011011011011101110110011011011010100110111001 step 68 100001100110100100011011011011011101111100011011011010100110111001 step 69 100001100110100101011011011011011101001111011011011010100110111001 step 70 100001100110100100011011011011011101111100011011011010100110111001 step 71 100001100110100100111011011011011101001111011011011010100110111001 step 72 100001100110100100011011011011011101111100011011011010100110111001 step 73 100001100110100100011111011011011101001111011011011010100110111001 step 74 100001100110100100011011011011011101111100011011011010100110111001 step 75 100001100110100100011011111011011101001111011011011010100110111001 step 76 100001100110100100011011011011011101111100011011011010100110111001 step 77 100001100110100100011011011111011101001111011011011010100110111001 step 78 100001100110100100011011011011011101111100011011011010100110111001 step 79 100001100110100100011011011011111101001111011011011010100110111001 step 80 100001100110100100011011011011011101111100011011011010100110111001 step 81 100001100110100100011011011011011111101110011011011010100110111001 step 82 100001100110100100011011011011011101111100011011011010100110111001 step 83 100001100110100100011011011011011101111100011011011010100110110101 step 84 100001100110100100011011011011011101111100011011011010100110110001 step 85 100001100110100100011011011011011101111100011011011010100110100101 step 86 100001100110100100011011011011011101111100011011011010100110100001 step 87 100001100110100100011011011011011101111100011011011010100110100101 step 88 100001100110100100011011011011011101111100011011011010100110100001 SLOT BAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBAABBAAAAAAAAAAAAAABBBBBBBBAB LETTER ALPSLFMDEEMCBFRSPKLEMFHRSCJLJKUHPNMBBNNVVRKRHUTDJUKANJHBTPDFSVDEVU SIDE 121212122121212121111111112212122222112222111221112112212112212212 DIRECTION IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIOOOOOOOIOOIOOIOOIOOOOIOOIIOOIIO changed: 11 step 89 100001100110100100011011011011011101111100011011011010100110100111 fail ^ SLOT BAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBAABBAAAAAAAAAAAAAABBBBBBBBAB LETTER ALPSLFMDEEMCBFRSPKLEMFHRSCJLJKUHPNMBBNNVVRKRHUTDJUKANJHBTPDFSVDEVU SIDE 121212122121212121111111112212122222112222111221112112212112212212 DIRECTION IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIOOOOOOOIOOIOOIOOIOOOOIOOIIOOIIO changed: 0 step 90 100001100110100100011011011011011101111100011011011010100110100011 fail ^ SLOT BAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBAABBAAAAAAAAAAAAAABBBBBBBBAB LETTER ALPSLFMDEEMCBFRSPKLEMFHRSCJLJKUHPNMBBNNVVRKRHUTDJUKANJHBTPDFSVDEVU SIDE 121212122121212121111111112212122222112222111221112112212112212212 DIRECTION IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIOOOOOOOIOOIOOIOOIOOOOIOOIIOOIIO changed: 11 step 91 100001100110100100011011011011011101111100011011011010100110101111 fail ^ SLOT BAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBAABBAAAAAAAAAAAAAABBBBBBBBAB LETTER ALPSLFMDEEMCBFRSPKLEMFHRSCJLJKUHPNMBBNNVVRKRHUTDJUKANJHBTPDFSVDEVU SIDE 121212122121212121111111112212122222112222111221112112212112212212 DIRECTION IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIOOOOOOOIOOIOOIOOIOOOOIOOIIOOIIO changed: 0 step 92 100001100110100100011011011011011101111100011011011010100110101011 fail ^ step 93 100001100110100100011011011011011101111100011011011010100110111111 step 94 100001100110100100011011011011011101111100011011011010100110111011 SLOT BAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBAABBAAAAAAAAAAAAAABBBBBBBBAB LETTER ALPSLFMDEEMCBFRSPKLEMFHRSCJLJKUHPNMBBNNVVRKRHUTDJUKANJHBTPDFSVDEVU SIDE 121212122121212121111111112212122222112222111221112112212112212212 DIRECTION IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIOOOOOOOIOOIOOIOOIOOOOIOOIIOOIIO changed: 10 step 95 100001100110100100011011011011011101111100011011011010100110111101 fail ^ SLOT BAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBAABBAAAAAAAAAAAAAABBBBBBBBAB LETTER ALPSLFMDEEMCBFRSPKLEMFHRSCJLJKUHPNMBBNNVVRKRHUTDJUKANJHBTPDFSVDEVU SIDE 121212122121212121111111112212122222112222111221112112212112212212 DIRECTION IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIOOOOOOOIOOIOOIOOIOOOOIOOIIOOIIO changed: 0 step 96 100001100110100100011011011011011101111100011011011010100110111001 fail ^ SLOT BAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBAABBAAAAAAAAAAAAAABBBBBBBBAB LETTER ALPSLFMDEEMCBFRSPKLEMFHRSCJLJKUHPNMBBNNVVRKRHUTDJUKANJHBTPDFSVDEVU SIDE 121212122121212121111111112212122222112222111221112112212112212212 DIRECTION IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIOOOOOOOIOOIOOIOOIOOOOIOOIIOOIIO changed: 011 step 97 100001100110100100011011011011011101111100011011011010100110110111 fail ^^ SLOT BAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBAABBAAAAAAAAAAAAAABBBBBBBBAB LETTER ALPSLFMDEEMCBFRSPKLEMFHRSCJLJKUHPNMBBNNVVRKRHUTDJUKANJHBTPDFSVDEVU SIDE 121212122121212121111111112212122222112222111221112112212112212212 DIRECTION IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIOOOOOOOIOOIOOIOOIOOOOIOOIIOOIIO changed: 0 step 98 100001100110100100011011011011011101111100011011011010100110110011 fail ^^ SLOT BAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBAABBAAAAAAAAAAAAAABBBBBBBBAB LETTER ALPSLFMDEEMCBFRSPKLEMFHRSCJLJKUHPNMBBNNVVRKRHUTDJUKANJHBTPDFSVDEVU SIDE 121212122121212121111111112212122222112222111221112112212112212212 DIRECTION IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIOOOOOOOIOOIOOIOOIOOOOIOOIIOOIIO changed: 0110 step 99 100001100110100100011011011011011101111100011011011010100110101101 fail ^^ SLOT BAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBAABBAAAAAAAAAAAAAABBBBBBBBAB LETTER ALPSLFMDEEMCBFRSPKLEMFHRSCJLJKUHPNMBBNNVVRKRHUTDJUKANJHBTPDFSVDEVU SIDE 121212122121212121111111112212122222112222111221112112212112212212 DIRECTION IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIOOOOOOOIOOIOOIOOIOOOOIOOIIOOIIO changed: 0 step 100 100001100110100100011011011011011101111100011011011010100110101001 fail ^^ SLOT BAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBAABBAAAAAAAAAAAAAABBBBBBBBAB LETTER ALPSLFMDEEMCBFRSPKLEMFHRSCJLJKUHPNMBBNNVVRKRHUTDJUKANJHBTPDFSVDEVU SIDE 121212122121212121111111112212122222112222111221112112212112212212 DIRECTION IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIOOOOOOOIOOIOOIOOIOOOOIOOIIOOIIO changed: 1011 step 101 100001100110100100011011011011011101111100011011011010100110110111 fail ^^ SLOT BAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBAABBAAAAAAAAAAAAAABBBBBBBBAB LETTER ALPSLFMDEEMCBFRSPKLEMFHRSCJLJKUHPNMBBNNVVRKRHUTDJUKANJHBTPDFSVDEVU SIDE 121212122121212121111111112212122222112222111221112112212112212212 DIRECTION IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIOOOOOOOIOOIOOIOOIOOOOIOOIIOOIIO changed: 0 step 102 100001100110100100011011011011011101111100011011011010100110110011 fail ^^ SLOT BAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBAABBAAAAAAAAAAAAAABBBBBBBBAB LETTER ALPSLFMDEEMCBFRSPKLEMFHRSCJLJKUHPNMBBNNVVRKRHUTDJUKANJHBTPDFSVDEVU SIDE 121212122121212121111111112212122222112222111221112112212112212212 DIRECTION IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIOOOOOOOIOOIOOIOOIOOOOIOOIIOOIIO changed: 011 step 103 100001100110100100011011011011011101111100011011011010100110101111 fail ^^ SLOT BAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBAABBAAAAAAAAAAAAAABBBBBBBBAB LETTER ALPSLFMDEEMCBFRSPKLEMFHRSCJLJKUHPNMBBNNVVRKRHUTDJUKANJHBTPDFSVDEVU SIDE 121212122121212121111111112212122222112222111221112112212112212212 DIRECTION IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIOOOOOOOIOOIOOIOOIOOOOIOOIIOOIIO changed: 0 step 104 100001100110100100011011011011011101111100011011011010100110101011 fail ^^ test 1: *** FAIL *************************** 14 steps failed SLOT BAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBAABBAAAAAAAAAAAAAABBBBBBBBAB LETTER ALPSLFMDEEMCBFRSPKLEMFHRSCJLJKUHPNMBBNNVVRKRHUTDJUKANJHBTPDFSVDEVU SIDE 121212122121212121111111112212122222112222111221112112212112212212 DIRECTION IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIOOOOOOOIOOIOOIOOIOOOOIOOIIOOIIO this fail OO all fails OO was hi 111111111111111111111111111111111111111111111111111111111111111111 rising ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ ^^^^^^^^^^^^^^^^^^^^ ^^^^ falling vvvv vv v vv vvv v v v v vvvvv vvvv vvvvvvvvvvvvvvv vvvv was lo 00000000000000000000000000000000000000 00000000000000000000 0000 total fails 1, total passes 0 space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C toggle comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit step 1 100000000000000000000000000000000001111100011011011010100110101001 step 2 100000000000000000000000000000000001111100100011011010100110101001 step 3 100000000000000000000000000000000001111100000011011010100110101001 step 4 100000000000000000000000000000000001111100000100011010100110101001 step 5 100000000000000000000000000000000001111100000000011010100110101001 step 6 100000000000000000000000000000000001111100000000100010100110101001 step 7 100000000000000000000000000000000001111100000000000010100110101001 step 8 100000000000000000000000000000000001111100000000000101010110101001 step 9 100000000000000000000000000000000001111100000000000001010110101001 step 10 100000000000000000000000000000000001111100000000000001011000101001 step 11 100000000000000000000000000000000001111100000000000001010000101001 step 12 100000000000000000000000000000000001111100000000000001010001100001 step 13 100000000000000000000000000000000001111100000000000001010000100001 step 14 100000000000000000000000000000000001111100000000000001010000100001 step 15 100000000000010000000000000000000000111101000000000001010000100001 step 16 100000000000010010000000000000000000110111000000000001010000100001 step 17 100000000000010010000000000000000000110111111000000001010000100001 step 18 100000000000010010000000000000000000110111011000000001010000100001 step 19 100000000000010010000000000000000000110111011111000001010000100001 step 20 100000000000010010000000000000000000110111011011000001010000100001 step 21 100000000000010010000000000000000000110111011011111001010000100001 step 22 100000000000010010000000000000000000110111011011011001010000100001 step 23 100000000000010010000000000000000000110111011011011110100000100001 step 24 100000000000010010000000000000000000110111011011011010100000100001 step 25 100000000000010010000000000000000000110111011011011010101110100001 step 26 100000000000010010000000000000000000110111011011011010100110100001 step 27 100000000000010010000000000000000000110111011011011010100111111001 step 28 100000000000010010000000000000000000110111011011011010100110111001 step 29 100000000000000010000000000000000001110110011011011010100110111001 step 30 100000000000000000000000000000000001111100011011011010100110111001 step 31 100000000000000000000000000000000001111100011011011010100110111001 step 32 100001000000000000000000000000000001111100011011011010100110111001 step 33 100001100000000000000000000000000001111100011011011010100110111001 step 34 100001100100000000000000000000000001111100011011011010100110111001 step 35 100001100110000000000000000000000001111100011011011010100110111001 step 36 100001100110100000000000000000000001111100011011011010100110111001 step 37 100001100110100100000000000000000001111100011011011010100110111001 step 38 100001100110100100010000000000000001111100011011011010100110111001 step 39 100001100110100100011000000000000001111100011011011010100110111001 step 40 100001100110100100011010000000000001111100011011011010100110111001 step 41 100001100110100100011011000000000001111100011011011010100110111001 step 42 100001100110100100011011010000000001111100011011011010100110111001 step 43 100001100110100100011011011000000001111100011011011010100110111001 step 44 100001100110100100011011011010000001111100011011011010100110111001 step 45 100001100110100100011011011011000001111100011011011010100110111001 step 46 100001100110100100011011011011010001111100011011011010100110111001 step 47 100001100110100100011011011011011001111100011011011010100110111001 step 48 100001100110100100011011011011011101111100011011011010100110111001 step 49 110001100110100100011011011011011100110111011011011010100110111001 step 50 100001100110100100011011011011011101111100011011011010100110111001 step 51 101001100110100100011011011011011100110111011011011010100110111001 step 52 100001100110100100011011011011011101111100011011011010100110111001 step 53 100101100110100100011011011011011100110111011011011010100110111001 step 54 100001100110100100011011011011011101111100011011011010100110111001 step 55 100011100110100100011011011011011100110111011011011010100110111001 step 56 100001100110100100011011011011011101111100011011011010100110111001 step 57 100001110110100100011011011011011100110111011011011010100110111001 step 58 100001100110100100011011011011011101111100011011011010100110111001 step 59 100001101110100100011011011011011100110111011011011010100110111001 step 60 100001100110100100011011011011011101111100011011011010100110111001 step 61 100001100111100100011011011011011100111101011011011010100110111001 step 62 100001100110100100011011011011011101111100011011011010100110111001 step 63 100001100110110100011011011011011100111101011011011010100110111001 step 64 100001100110100100011011011011011101111100011011011010100110111001 step 65 100001100110101100011011011011011101110110011011011010100110111001 step 66 100001100110100100011011011011011101111100011011011010100110111001 step 67 100001100110100110011011011011011101110110011011011010100110111001 step 68 100001100110100100011011011011011101111100011011011010100110111001 step 69 100001100110100101011011011011011101001111011011011010100110111001 step 70 100001100110100100011011011011011101111100011011011010100110111001 step 71 100001100110100100111011011011011101001111011011011010100110111001 step 72 100001100110100100011011011011011101111100011011011010100110111001 step 73 100001100110100100011111011011011101001111011011011010100110111001 step 74 100001100110100100011011011011011101111100011011011010100110111001 step 75 100001100110100100011011111011011101001111011011011010100110111001 step 76 100001100110100100011011011011011101111100011011011010100110111001 step 77 100001100110100100011011011111011101001111011011011010100110111001 step 78 100001100110100100011011011011011101111100011011011010100110111001 step 79 100001100110100100011011011011111101001111011011011010100110111001 step 80 100001100110100100011011011011011101111100011011011010100110111001 step 81 100001100110100100011011011011011111101110011011011010100110111001 step 82 100001100110100100011011011011011101111100011011011010100110111001 step 83 100001100110100100011011011011011101111100011011011010100110110101 step 84 100001100110100100011011011011011101111100011011011010100110110001 step 85 100001100110100100011011011011011101111100011011011010100110100101 step 86 100001100110100100011011011011011101111100011011011010100110100001 step 87 100001100110100100011011011011011101111100011011011010100110100101 step 88 100001100110100100011011011011011101111100011011011010100110100001 SLOT BAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBAABBAAAAAAAAAAAAAABBBBBBBBAB LETTER ALPSLFMDEEMCBFRSPKLEMFHRSCJLJKUHPNMBBNNVVRKRHUTDJUKANJHBTPDFSVDEVU SIDE 121212122121212121111111112212122222112222111221112112212112212212 DIRECTION IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIOOOOOOOIOOIOOIOOIOOOOIOOIIOOIIO changed: 11 step 89 100001100110100100011011011011011101111100011011011010100110100111 fail ^ SLOT BAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBAABBAAAAAAAAAAAAAABBBBBBBBAB LETTER ALPSLFMDEEMCBFRSPKLEMFHRSCJLJKUHPNMBBNNVVRKRHUTDJUKANJHBTPDFSVDEVU SIDE 121212122121212121111111112212122222112222111221112112212112212212 DIRECTION IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIOOOOOOOIOOIOOIOOIOOOOIOOIIOOIIO changed: 0 step 90 100001100110100100011011011011011101111100011011011010100110100011 fail ^ SLOT BAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBAABBAAAAAAAAAAAAAABBBBBBBBAB LETTER ALPSLFMDEEMCBFRSPKLEMFHRSCJLJKUHPNMBBNNVVRKRHUTDJUKANJHBTPDFSVDEVU SIDE 121212122121212121111111112212122222112222111221112112212112212212 DIRECTION IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIOOOOOOOIOOIOOIOOIOOOOIOOIIOOIIO changed: 11 step 91 100001100110100100011011011011011101111100011011011010100110101111 fail ^ SLOT BAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBAABBAAAAAAAAAAAAAABBBBBBBBAB LETTER ALPSLFMDEEMCBFRSPKLEMFHRSCJLJKUHPNMBBNNVVRKRHUTDJUKANJHBTPDFSVDEVU SIDE 121212122121212121111111112212122222112222111221112112212112212212 DIRECTION IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIOOOOOOOIOOIOOIOOIOOOOIOOIIOOIIO changed: 0 step 92 100001100110100100011011011011011101111100011011011010100110101011 fail ^ step 93 100001100110100100011011011011011101111100011011011010100110111111 step 94 100001100110100100011011011011011101111100011011011010100110111011 SLOT BAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBAABBAAAAAAAAAAAAAABBBBBBBBAB LETTER ALPSLFMDEEMCBFRSPKLEMFHRSCJLJKUHPNMBBNNVVRKRHUTDJUKANJHBTPDFSVDEVU SIDE 121212122121212121111111112212122222112222111221112112212112212212 DIRECTION IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIOOOOOOOIOOIOOIOOIOOOOIOOIIOOIIO changed: 10 step 95 100001100110100100011011011011011101111100011011011010100110111101 fail ^ SLOT BAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBAABBAAAAAAAAAAAAAABBBBBBBBAB LETTER ALPSLFMDEEMCBFRSPKLEMFHRSCJLJKUHPNMBBNNVVRKRHUTDJUKANJHBTPDFSVDEVU SIDE 121212122121212121111111112212122222112222111221112112212112212212 DIRECTION IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIOOOOOOOIOOIOOIOOIOOOOIOOIIOOIIO changed: 0 step 96 100001100110100100011011011011011101111100011011011010100110111001 fail ^ SLOT BAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBAABBAAAAAAAAAAAAAABBBBBBBBAB LETTER ALPSLFMDEEMCBFRSPKLEMFHRSCJLJKUHPNMBBNNVVRKRHUTDJUKANJHBTPDFSVDEVU SIDE 121212122121212121111111112212122222112222111221112112212112212212 DIRECTION IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIOOOOOOOIOOIOOIOOIOOOOIOOIIOOIIO changed: 011 step 97 100001100110100100011011011011011101111100011011011010100110110111 fail ^^ SLOT BAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBAABBAAAAAAAAAAAAAABBBBBBBBAB LETTER ALPSLFMDEEMCBFRSPKLEMFHRSCJLJKUHPNMBBNNVVRKRHUTDJUKANJHBTPDFSVDEVU SIDE 121212122121212121111111112212122222112222111221112112212112212212 DIRECTION IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIOOOOOOOIOOIOOIOOIOOOOIOOIIOOIIO changed: 0 step 98 100001100110100100011011011011011101111100011011011010100110110011 fail ^^ SLOT BAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBAABBAAAAAAAAAAAAAABBBBBBBBAB LETTER ALPSLFMDEEMCBFRSPKLEMFHRSCJLJKUHPNMBBNNVVRKRHUTDJUKANJHBTPDFSVDEVU SIDE 121212122121212121111111112212122222112222111221112112212112212212 DIRECTION IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIOOOOOOOIOOIOOIOOIOOOOIOOIIOOIIO changed: 0110 step 99 100001100110100100011011011011011101111100011011011010100110101101 fail ^^ SLOT BAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBAABBAAAAAAAAAAAAAABBBBBBBBAB LETTER ALPSLFMDEEMCBFRSPKLEMFHRSCJLJKUHPNMBBNNVVRKRHUTDJUKANJHBTPDFSVDEVU SIDE 121212122121212121111111112212122222112222111221112112212112212212 DIRECTION IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIOOOOOOOIOOIOOIOOIOOOOIOOIIOOIIO changed: 0 step 100 100001100110100100011011011011011101111100011011011010100110101001 fail ^^ SLOT BAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBAABBAAAAAAAAAAAAAABBBBBBBBAB LETTER ALPSLFMDEEMCBFRSPKLEMFHRSCJLJKUHPNMBBNNVVRKRHUTDJUKANJHBTPDFSVDEVU SIDE 121212122121212121111111112212122222112222111221112112212112212212 DIRECTION IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIOOOOOOOIOOIOOIOOIOOOOIOOIIOOIIO changed: 1011 step 101 100001100110100100011011011011011101111100011011011010100110110111 fail ^^ SLOT BAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBAABBAAAAAAAAAAAAAABBBBBBBBAB LETTER ALPSLFMDEEMCBFRSPKLEMFHRSCJLJKUHPNMBBNNVVRKRHUTDJUKANJHBTPDFSVDEVU SIDE 121212122121212121111111112212122222112222111221112112212112212212 DIRECTION IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIOOOOOOOIOOIOOIOOIOOOOIOOIIOOIIO changed: 0 step 102 100001100110100100011011011011011101111100011011011010100110110011 fail ^^ SLOT BAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBAABBAAAAAAAAAAAAAABBBBBBBBAB LETTER ALPSLFMDEEMCBFRSPKLEMFHRSCJLJKUHPNMBBNNVVRKRHUTDJUKANJHBTPDFSVDEVU SIDE 121212122121212121111111112212122222112222111221112112212112212212 DIRECTION IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIOOOOOOOIOOIOOIOOIOOOOIOOIIOOIIO changed: 011 step 103 100001100110100100011011011011011101111100011011011010100110101111 fail ^^ SLOT BAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBAABBAAAAAAAAAAAAAABBBBBBBBAB LETTER ALPSLFMDEEMCBFRSPKLEMFHRSCJLJKUHPNMBBNNVVRKRHUTDJUKANJHBTPDFSVDEVU SIDE 121212122121212121111111112212122222112222111221112112212112212212 DIRECTION IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIOOOOOOOIOOIOOIOOIOOOOIOOIIOOIIO changed: 0 step 104 100001100110100100011011011011011101111100011011011010100110101011 fail ^^ test 2: *** FAIL *************************** 14 steps failed SLOT BAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBAABBAAAAAAAAAAAAAABBBBBBBBAB LETTER ALPSLFMDEEMCBFRSPKLEMFHRSCJLJKUHPNMBBNNVVRKRHUTDJUKANJHBTPDFSVDEVU SIDE 121212122121212121111111112212122222112222111221112112212112212212 DIRECTION IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIOOOOOOOIOOIOOIOOIOOOOIOOIIOOIIO this fail OO all fails OO was hi 111111111111111111111111111111111111111111111111111111111111111111 rising ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ ^^^^^^^^^^^^^^^^^^^^ ^^^^ falling vvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvv vvvvvvvvvvvvvvvvvvvv vvvv was lo 00000000000000000000000000000000000000 00000000000000000000 0000 total fails 2, total passes 0 space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C toggle comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT BAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBAABBAAAAAAAAAAAAAABBBBBBBBAB LETTER ALPSLFMDEEMCBFRSPKLEMFHRSCJLJKUHPNMBBNNVVRKRHUTDJUKANJHBTPDFSVDEVU SIDE 121212122121212121111111112212122222112222111221112112212112212212 DIRECTION IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIOOOOOOOIOOIOOIOOIOOOOIOOIIOOIIO all fails OO was lo 00000000000000000000000000000000000000 00000000000000000000 0000 falling vvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvv vvvvvvvvvvvvvvvvvvvv vvvv rising ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ ^^^^^^^^^^^^^^^^^^^^ ^^^^ was hi 111111111111111111111111111111111111111111111111111111111111111111 total fails 2, total passes 0 Main menu Thu Aug 20 15:37:32 2015 test file is: tests\m222.new delay is: 0 trigger is: 1 1 read test file 2 set test delay 3 set test trigger 4 run test 5 output loading test 8 diags 9 exit UUT power is okay Thu Aug 20 15:37:58 2015 space single step O run once (one test, all steps) F run, stop on fail G go (run tests N run, stop on fail, no print S scope (run, no print) C toggle comment printout + increase speed (less delay) - decrease speed (more delay)(slower) Q quit test step 1 100000000000000000000000000000000001111100010011011010100000100001 step 2 100000000000000000000000000000000001111100100011011010100000100001 step 3 100000000000000000000000000000000001111100000011011010100000100001 step 4 100000000000000000000000000000000001111100000100011010100000100001 step 5 100000000000000000000000000000000001111100000000011010100000100001 step 6 100000000000000000000000000000000001111100000000100010100000100001 step 7 100000000000000000000000000000000001111100000000000010100000100001 step 8 100000000000000000000000000000000001111100000000000101010000100001 step 9 100000000000000000000000000000000001111100000000000001010000100001 step 10 100000000000000000000000000000000001111100000000000001011000100001 step 11 100000000000000000000000000000000001111100000000000001010000100001 step 12 100000000000000000000000000000000001111100000000000001010001100001 step 13 100000000000000000000000000000000001111100000000000001010000100001 step 14 100000000000000000000000000000000001111100000000000001010000100001 step 15 100000000000010000000000000000000000111101000000000001010000100001 step 16 100000000000010010000000000000000000110111000000000001010000100001 step 17 100000000000010010000000000000000000110111111000000001010000100001 step 18 100000000000010010000000000000000000110111011000000001010000100001 step 19 100000000000010010000000000000000000110111011111000001010000100001 step 20 100000000000010010000000000000000000110111011011000001010000100001 step 21 100000000000010010000000000000000000110111011011111001010000100001 step 22 100000000000010010000000000000000000110111011011011001010000100001 step 23 100000000000010010000000000000000000110111011011011110100000100001 step 24 100000000000010010000000000000000000110111011011011010100000100001 step 25 100000000000010010000000000000000000110111011011011010101110100001 step 26 100000000000010010000000000000000000110111011011011010100110100001 step 27 100000000000010010000000000000000000110111011011011010100111111001 step 28 100000000000010010000000000000000000110111011011011010100110111001 step 29 100000000000000010000000000000000001110110011011011010100110111001 step 30 100000000000000000000000000000000001111100011011011010100110111001 step 31 100000000000000000000000000000000001111100011011011010100110111001 step 32 100001000000000000000000000000000001111100011011011010100110111001 step 33 100001100000000000000000000000000001111100011011011010100110111001 step 34 100001100100000000000000000000000001111100011011011010100110111001 step 35 100001100110000000000000000000000001111100011011011010100110111001 step 36 100001100110100000000000000000000001111100011011011010100110111001 step 37 100001100110100100000000000000000001111100011011011010100110111001 step 38 100001100110100100010000000000000001111100011011011010100110111001 step 39 100001100110100100011000000000000001111100011011011010100110111001 step 40 100001100110100100011010000000000001111100011011011010100110111001 step 41 100001100110100100011011000000000001111100011011011010100110111001 step 42 100001100110100100011011010000000001111100011011011010100110111001 step 43 100001100110100100011011011000000001111100011011011010100110111001 step 44 100001100110100100011011011010000001111100011011011010100110111001 step 45 100001100110100100011011011011000001111100011011011010100110111001 step 46 100001100110100100011011011011010001111100011011011010100110111001 step 47 100001100110100100011011011011011001111100011011011010100110111001 step 48 100001100110100100011011011011011101111100011011011010100110111001 step 49 110001100110100100011011011011011100110111011011011010100110111001 step 50 100001100110100100011011011011011101111100011011011010100110111001 step 51 101001100110100100011011011011011100110111011011011010100110111001 step 52 100001100110100100011011011011011101111100011011011010100110111001 step 53 100101100110100100011011011011011100110111011011011010100110111001 step 54 100001100110100100011011011011011101111100011011011010100110111001 step 55 100011100110100100011011011011011100110111011011011010100110111001 step 56 100001100110100100011011011011011101111100011011011010100110111001 step 57 100001110110100100011011011011011100110111011011011010100110111001 step 58 100001100110100100011011011011011101111100011011011010100110111001 step 59 100001101110100100011011011011011100110111011011011010100110111001 step 60 100001100110100100011011011011011101111100011011011010100110111001 step 61 100001100111100100011011011011011100111101011011011010100110111001 step 62 100001100110100100011011011011011101111100011011011010100110111001 step 63 100001100110110100011011011011011100111101011011011010100110111001 step 64 100001100110100100011011011011011101111100011011011010100110111001 step 65 100001100110101100011011011011011101110110011011011010100110111001 step 66 100001100110100100011011011011011101111100011011011010100110111001 step 67 100001100110100110011011011011011101110110011011011010100110111001 step 68 100001100110100100011011011011011101111100011011011010100110111001 step 69 100001100110100101011011011011011101001111011011011010100110111001 step 70 100001100110100100011011011011011101111100011011011010100110111001 step 71 100001100110100100111011011011011101001111011011011010100110111001 step 72 100001100110100100011011011011011101111100011011011010100110111001 step 73 100001100110100100011111011011011101001111011011011010100110111001 step 74 100001100110100100011011011011011101111100011011011010100110111001 step 75 100001100110100100011011111011011101001111011011011010100110111001 step 76 100001100110100100011011011011011101111100011011011010100110111001 step 77 100001100110100100011011011111011101001111011011011010100110111001 step 78 100001100110100100011011011011011101111100011011011010100110111001 step 79 100001100110100100011011011011111101001111011011011010100110111001 step 80 100001100110100100011011011011011101111100011011011010100110111001 step 81 100001100110100100011011011011011111101110011011011010100110111001 step 82 100001100110100100011011011011011101111100011011011010100110111001 step 83 100001100110100100011011011011011101111100011011011010100110110101 step 84 100001100110100100011011011011011101111100011011011010100110110001 step 85 100001100110100100011011011011011101111100011011011010100110100101 step 86 100001100110100100011011011011011101111100011011011010100110100001 step 87 100001100110100100011011011011011101111100011011011010100110100101 step 88 100001100110100100011011011011011101111100011011011010100110100001 SLOT BAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBAABBAAAAAAAAAAAAAABBBBBBBBAB LETTER ALPSLFMDEEMCBFRSPKLEMFHRSCJLJKUHPNMBBNNVVRKRHUTDJUKANJHBTPDFSVDEVU SIDE 121212122121212121111111112212122222112222111221112112212112212212 DIRECTION IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIOOOOOOOIOOIOOIOOIOOOOIOOIIOOIIO changed: 11 step 89 100001100110100100011011011011011101111100011011011010100110100111 fail ^ SLOT BAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBAABBAAAAAAAAAAAAAABBBBBBBBAB LETTER ALPSLFMDEEMCBFRSPKLEMFHRSCJLJKUHPNMBBNNVVRKRHUTDJUKANJHBTPDFSVDEVU SIDE 121212122121212121111111112212122222112222111221112112212112212212 DIRECTION IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIOOOOOOOIOOIOOIOOIOOOOIOOIIOOIIO changed: 0 step 90 100001100110100100011011011011011101111100011011011010100110100011 fail ^ SLOT BAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBAABBAAAAAAAAAAAAAABBBBBBBBAB LETTER ALPSLFMDEEMCBFRSPKLEMFHRSCJLJKUHPNMBBNNVVRKRHUTDJUKANJHBTPDFSVDEVU SIDE 121212122121212121111111112212122222112222111221112112212112212212 DIRECTION IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIOOOOOOOIOOIOOIOOIOOOOIOOIIOOIIO changed: 11 step 91 100001100110100100011011011011011101111100011011011010100110101111 fail ^ SLOT BAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBAABBAAAAAAAAAAAAAABBBBBBBBAB LETTER ALPSLFMDEEMCBFRSPKLEMFHRSCJLJKUHPNMBBNNVVRKRHUTDJUKANJHBTPDFSVDEVU SIDE 121212122121212121111111112212122222112222111221112112212112212212 DIRECTION IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIOOOOOOOIOOIOOIOOIOOOOIOOIIOOIIO changed: 0 step 92 100001100110100100011011011011011101111100011011011010100110101011 fail ^ step 93 100001100110100100011011011011011101111100011011011010100110111111 step 94 100001100110100100011011011011011101111100011011011010100110111011 SLOT BAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBAABBAAAAAAAAAAAAAABBBBBBBBAB LETTER ALPSLFMDEEMCBFRSPKLEMFHRSCJLJKUHPNMBBNNVVRKRHUTDJUKANJHBTPDFSVDEVU SIDE 121212122121212121111111112212122222112222111221112112212112212212 DIRECTION IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIOOOOOOOIOOIOOIOOIOOOOIOOIIOOIIO changed: 10 step 95 100001100110100100011011011011011101111100011011011010100110111101 fail ^ SLOT BAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBAABBAAAAAAAAAAAAAABBBBBBBBAB LETTER ALPSLFMDEEMCBFRSPKLEMFHRSCJLJKUHPNMBBNNVVRKRHUTDJUKANJHBTPDFSVDEVU SIDE 121212122121212121111111112212122222112222111221112112212112212212 DIRECTION IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIOOOOOOOIOOIOOIOOIOOOOIOOIIOOIIO changed: 0 step 96 100001100110100100011011011011011101111100011011011010100110111001 fail ^ SLOT BAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBAABBAAAAAAAAAAAAAABBBBBBBBAB LETTER ALPSLFMDEEMCBFRSPKLEMFHRSCJLJKUHPNMBBNNVVRKRHUTDJUKANJHBTPDFSVDEVU SIDE 121212122121212121111111112212122222112222111221112112212112212212 DIRECTION IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIOOOOOOOIOOIOOIOOIOOOOIOOIIOOIIO changed: 011 step 97 100001100110100100011011011011011101111100011011011010100110110111 fail ^^ SLOT BAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBAABBAAAAAAAAAAAAAABBBBBBBBAB LETTER ALPSLFMDEEMCBFRSPKLEMFHRSCJLJKUHPNMBBNNVVRKRHUTDJUKANJHBTPDFSVDEVU SIDE 121212122121212121111111112212122222112222111221112112212112212212 DIRECTION IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIOOOOOOOIOOIOOIOOIOOOOIOOIIOOIIO changed: 0 step 98 100001100110100100011011011011011101111100011011011010100110110011 fail ^^ SLOT BAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBAABBAAAAAAAAAAAAAABBBBBBBBAB LETTER ALPSLFMDEEMCBFRSPKLEMFHRSCJLJKUHPNMBBNNVVRKRHUTDJUKANJHBTPDFSVDEVU SIDE 121212122121212121111111112212122222112222111221112112212112212212 DIRECTION IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIOOOOOOOIOOIOOIOOIOOOOIOOIIOOIIO changed: 0110 step 99 100001100110100100011011011011011101111100011011011010100110101101 fail ^^ SLOT BAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBAABBAAAAAAAAAAAAAABBBBBBBBAB LETTER ALPSLFMDEEMCBFRSPKLEMFHRSCJLJKUHPNMBBNNVVRKRHUTDJUKANJHBTPDFSVDEVU SIDE 121212122121212121111111112212122222112222111221112112212112212212 DIRECTION IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIOOOOOOOIOOIOOIOOIOOOOIOOIIOOIIO changed: 0 step 100 100001100110100100011011011011011101111100011011011010100110101001 fail ^^ SLOT BAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBAABBAAAAAAAAAAAAAABBBBBBBBAB LETTER ALPSLFMDEEMCBFRSPKLEMFHRSCJLJKUHPNMBBNNVVRKRHUTDJUKANJHBTPDFSVDEVU SIDE 121212122121212121111111112212122222112222111221112112212112212212 DIRECTION IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIOOOOOOOIOOIOOIOOIOOOOIOOIIOOIIO changed: 1011 step 101 100001100110100100011011011011011101111100011011011010100110110111 fail ^^ SLOT BAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBAABBAAAAAAAAAAAAAABBBBBBBBAB LETTER ALPSLFMDEEMCBFRSPKLEMFHRSCJLJKUHPNMBBNNVVRKRHUTDJUKANJHBTPDFSVDEVU SIDE 121212122121212121111111112212122222112222111221112112212112212212 DIRECTION IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIOOOOOOOIOOIOOIOOIOOOOIOOIIOOIIO changed: 0 step 102 100001100110100100011011011011011101111100011011011010100110110011 fail ^^ SLOT BAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBAABBAAAAAAAAAAAAAABBBBBBBBAB LETTER ALPSLFMDEEMCBFRSPKLEMFHRSCJLJKUHPNMBBNNVVRKRHUTDJUKANJHBTPDFSVDEVU SIDE 121212122121212121111111112212122222112222111221112112212112212212 DIRECTION IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIOOOOOOOIOOIOOIOOIOOOOIOOIIOOIIO changed: 011 step 103 100001100110100100011011011011011101111100011011011010100110101111 fail ^^ SLOT BAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBAABBAAAAAAAAAAAAAABBBBBBBBAB LETTER ALPSLFMDEEMCBFRSPKLEMFHRSCJLJKUHPNMBBNNVVRKRHUTDJUKANJHBTPDFSVDEVU SIDE 121212122121212121111111112212122222112222111221112112212112212212 DIRECTION IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIOOOOOOOIOOIOOIOOIOOOOIOOIIOOIIO changed: 0 step 104 100001100110100100011011011011011101111100011011011010100110101011 fail ^^ test 1: *** FAIL *************************** 14 steps failed SLOT BAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBAABBAAAAAAAAAAAAAABBBBBBBBAB LETTER ALPSLFMDEEMCBFRSPKLEMFHRSCJLJKUHPNMBBNNVVRKRHUTDJUKANJHBTPDFSVDEVU SIDE 121212122121212121111111112212122222112222111221112112212112212212 DIRECTION IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIOOOOOOOIOOIOOIOOIOOOOIOOIIOOIIO this fail OO all fails OO was hi 111111111111111111111111111111111111111111111111111111111111111111 rising ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ ^^^^^^^^^^^^^^^^^^^^ ^^^^ falling vvvv vv v vv vvv v v v v vvvvv vvvv vvvvvvvvvvvv v vvvv was lo 00000000000000000000000000000000000000 00000000000000000000 0000 total fails 1, total passes 0 space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C toggle comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit step 1 100000000000000000000000000000000001111100011011011010100110101001 step 2 100000000000000000000000000000000001111100100011011010100110101001 step 3 100000000000000000000000000000000001111100000011011010100110101001 step 4 100000000000000000000000000000000001111100000100011010100110101001 step 5 100000000000000000000000000000000001111100000000011010100110101001 step 6 100000000000000000000000000000000001111100000000100010100110101001 step 7 100000000000000000000000000000000001111100000000000010100110101001 step 8 100000000000000000000000000000000001111100000000000101010110101001 step 9 100000000000000000000000000000000001111100000000000001010110101001 step 10 100000000000000000000000000000000001111100000000000001011000101001 step 11 100000000000000000000000000000000001111100000000000001010000101001 step 12 100000000000000000000000000000000001111100000000000001010001100001 step 13 100000000000000000000000000000000001111100000000000001010000100001 step 14 100000000000000000000000000000000001111100000000000001010000100001 step 15 100000000000010000000000000000000000111101000000000001010000100001 step 16 100000000000010010000000000000000000110111000000000001010000100001 step 17 100000000000010010000000000000000000110111111000000001010000100001 step 18 100000000000010010000000000000000000110111011000000001010000100001 step 19 100000000000010010000000000000000000110111011111000001010000100001 step 20 100000000000010010000000000000000000110111011011000001010000100001 step 21 100000000000010010000000000000000000110111011011111001010000100001 step 22 100000000000010010000000000000000000110111011011011001010000100001 step 23 100000000000010010000000000000000000110111011011011110100000100001 step 24 100000000000010010000000000000000000110111011011011010100000100001 step 25 100000000000010010000000000000000000110111011011011010101110100001 step 26 100000000000010010000000000000000000110111011011011010100110100001 step 27 100000000000010010000000000000000000110111011011011010100111111001 step 28 100000000000010010000000000000000000110111011011011010100110111001 step 29 100000000000000010000000000000000001110110011011011010100110111001 step 30 100000000000000000000000000000000001111100011011011010100110111001 step 31 100000000000000000000000000000000001111100011011011010100110111001 step 32 100001000000000000000000000000000001111100011011011010100110111001 step 33 100001100000000000000000000000000001111100011011011010100110111001 step 34 100001100100000000000000000000000001111100011011011010100110111001 step 35 100001100110000000000000000000000001111100011011011010100110111001 step 36 100001100110100000000000000000000001111100011011011010100110111001 step 37 100001100110100100000000000000000001111100011011011010100110111001 step 38 100001100110100100010000000000000001111100011011011010100110111001 step 39 100001100110100100011000000000000001111100011011011010100110111001 step 40 100001100110100100011010000000000001111100011011011010100110111001 step 41 100001100110100100011011000000000001111100011011011010100110111001 step 42 100001100110100100011011010000000001111100011011011010100110111001 step 43 100001100110100100011011011000000001111100011011011010100110111001 step 44 100001100110100100011011011010000001111100011011011010100110111001 step 45 100001100110100100011011011011000001111100011011011010100110111001 step 46 100001100110100100011011011011010001111100011011011010100110111001 step 47 100001100110100100011011011011011001111100011011011010100110111001 step 48 100001100110100100011011011011011101111100011011011010100110111001 step 49 110001100110100100011011011011011100110111011011011010100110111001 step 50 100001100110100100011011011011011101111100011011011010100110111001 step 51 101001100110100100011011011011011100110111011011011010100110111001 step 52 100001100110100100011011011011011101111100011011011010100110111001 step 53 100101100110100100011011011011011100110111011011011010100110111001 step 54 100001100110100100011011011011011101111100011011011010100110111001 step 55 100011100110100100011011011011011100110111011011011010100110111001 step 56 100001100110100100011011011011011101111100011011011010100110111001 step 57 100001110110100100011011011011011100110111011011011010100110111001 step 58 100001100110100100011011011011011101111100011011011010100110111001 step 59 100001101110100100011011011011011100110111011011011010100110111001 step 60 100001100110100100011011011011011101111100011011011010100110111001 step 61 100001100111100100011011011011011100111101011011011010100110111001 step 62 100001100110100100011011011011011101111100011011011010100110111001 step 63 100001100110110100011011011011011100111101011011011010100110111001 step 64 100001100110100100011011011011011101111100011011011010100110111001 step 65 100001100110101100011011011011011101110110011011011010100110111001 step 66 100001100110100100011011011011011101111100011011011010100110111001 step 67 100001100110100110011011011011011101110110011011011010100110111001 step 68 100001100110100100011011011011011101111100011011011010100110111001 step 69 100001100110100101011011011011011101001111011011011010100110111001 step 70 100001100110100100011011011011011101111100011011011010100110111001 step 71 100001100110100100111011011011011101001111011011011010100110111001 step 72 100001100110100100011011011011011101111100011011011010100110111001 step 73 100001100110100100011111011011011101001111011011011010100110111001 step 74 100001100110100100011011011011011101111100011011011010100110111001 step 75 100001100110100100011011111011011101001111011011011010100110111001 step 76 100001100110100100011011011011011101111100011011011010100110111001 step 77 100001100110100100011011011111011101001111011011011010100110111001 step 78 100001100110100100011011011011011101111100011011011010100110111001 step 79 100001100110100100011011011011111101001111011011011010100110111001 step 80 100001100110100100011011011011011101111100011011011010100110111001 step 81 100001100110100100011011011011011111101110011011011010100110111001 step 82 100001100110100100011011011011011101111100011011011010100110111001 step 83 100001100110100100011011011011011101111100011011011010100110110101 step 84 100001100110100100011011011011011101111100011011011010100110110001 step 85 100001100110100100011011011011011101111100011011011010100110100101 step 86 100001100110100100011011011011011101111100011011011010100110100001 step 87 100001100110100100011011011011011101111100011011011010100110100101 step 88 100001100110100100011011011011011101111100011011011010100110100001 SLOT BAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBAABBAAAAAAAAAAAAAABBBBBBBBAB LETTER ALPSLFMDEEMCBFRSPKLEMFHRSCJLJKUHPNMBBNNVVRKRHUTDJUKANJHBTPDFSVDEVU SIDE 121212122121212121111111112212122222112222111221112112212112212212 DIRECTION IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIOOOOOOOIOOIOOIOOIOOOOIOOIIOOIIO changed: 11 step 89 100001100110100100011011011011011101111100011011011010100110100111 fail ^ SLOT BAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBAABBAAAAAAAAAAAAAABBBBBBBBAB LETTER ALPSLFMDEEMCBFRSPKLEMFHRSCJLJKUHPNMBBNNVVRKRHUTDJUKANJHBTPDFSVDEVU SIDE 121212122121212121111111112212122222112222111221112112212112212212 DIRECTION IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIOOOOOOOIOOIOOIOOIOOOOIOOIIOOIIO changed: 0 step 90 100001100110100100011011011011011101111100011011011010100110100011 fail ^ SLOT BAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBAABBAAAAAAAAAAAAAABBBBBBBBAB LETTER ALPSLFMDEEMCBFRSPKLEMFHRSCJLJKUHPNMBBNNVVRKRHUTDJUKANJHBTPDFSVDEVU SIDE 121212122121212121111111112212122222112222111221112112212112212212 DIRECTION IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIOOOOOOOIOOIOOIOOIOOOOIOOIIOOIIO changed: 11 step 91 100001100110100100011011011011011101111100011011011010100110101111 fail ^ SLOT BAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBAABBAAAAAAAAAAAAAABBBBBBBBAB LETTER ALPSLFMDEEMCBFRSPKLEMFHRSCJLJKUHPNMBBNNVVRKRHUTDJUKANJHBTPDFSVDEVU SIDE 121212122121212121111111112212122222112222111221112112212112212212 DIRECTION IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIOOOOOOOIOOIOOIOOIOOOOIOOIIOOIIO changed: 0 step 92 100001100110100100011011011011011101111100011011011010100110101011 fail ^ step 93 100001100110100100011011011011011101111100011011011010100110111111 step 94 100001100110100100011011011011011101111100011011011010100110111011 SLOT BAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBAABBAAAAAAAAAAAAAABBBBBBBBAB LETTER ALPSLFMDEEMCBFRSPKLEMFHRSCJLJKUHPNMBBNNVVRKRHUTDJUKANJHBTPDFSVDEVU SIDE 121212122121212121111111112212122222112222111221112112212112212212 DIRECTION IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIOOOOOOOIOOIOOIOOIOOOOIOOIIOOIIO changed: 10 step 95 100001100110100100011011011011011101111100011011011010100110111101 fail ^ SLOT BAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBAABBAAAAAAAAAAAAAABBBBBBBBAB LETTER ALPSLFMDEEMCBFRSPKLEMFHRSCJLJKUHPNMBBNNVVRKRHUTDJUKANJHBTPDFSVDEVU SIDE 121212122121212121111111112212122222112222111221112112212112212212 DIRECTION IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIOOOOOOOIOOIOOIOOIOOOOIOOIIOOIIO changed: 0 step 96 100001100110100100011011011011011101111100011011011010100110111001 fail ^ SLOT BAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBAABBAAAAAAAAAAAAAABBBBBBBBAB LETTER ALPSLFMDEEMCBFRSPKLEMFHRSCJLJKUHPNMBBNNVVRKRHUTDJUKANJHBTPDFSVDEVU SIDE 121212122121212121111111112212122222112222111221112112212112212212 DIRECTION IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIOOOOOOOIOOIOOIOOIOOOOIOOIIOOIIO changed: 011 step 97 100001100110100100011011011011011101111100011011011010100110110111 fail ^^ SLOT BAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBAABBAAAAAAAAAAAAAABBBBBBBBAB LETTER ALPSLFMDEEMCBFRSPKLEMFHRSCJLJKUHPNMBBNNVVRKRHUTDJUKANJHBTPDFSVDEVU SIDE 121212122121212121111111112212122222112222111221112112212112212212 DIRECTION IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIOOOOOOOIOOIOOIOOIOOOOIOOIIOOIIO changed: 0 step 98 100001100110100100011011011011011101111100011011011010100110110011 fail ^^ SLOT BAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBAABBAAAAAAAAAAAAAABBBBBBBBAB LETTER ALPSLFMDEEMCBFRSPKLEMFHRSCJLJKUHPNMBBNNVVRKRHUTDJUKANJHBTPDFSVDEVU SIDE 121212122121212121111111112212122222112222111221112112212112212212 DIRECTION IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIOOOOOOOIOOIOOIOOIOOOOIOOIIOOIIO changed: 0110 step 99 100001100110100100011011011011011101111100011011011010100110101101 fail ^^ SLOT BAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBAABBAAAAAAAAAAAAAABBBBBBBBAB LETTER ALPSLFMDEEMCBFRSPKLEMFHRSCJLJKUHPNMBBNNVVRKRHUTDJUKANJHBTPDFSVDEVU SIDE 121212122121212121111111112212122222112222111221112112212112212212 DIRECTION IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIOOOOOOOIOOIOOIOOIOOOOIOOIIOOIIO changed: 0 step 100 100001100110100100011011011011011101111100011011011010100110101001 fail ^^ SLOT BAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBAABBAAAAAAAAAAAAAABBBBBBBBAB LETTER ALPSLFMDEEMCBFRSPKLEMFHRSCJLJKUHPNMBBNNVVRKRHUTDJUKANJHBTPDFSVDEVU SIDE 121212122121212121111111112212122222112222111221112112212112212212 DIRECTION IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIOOOOOOOIOOIOOIOOIOOOOIOOIIOOIIO changed: 1011 step 101 100001100110100100011011011011011101111100011011011010100110110111 fail ^^ SLOT BAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBAABBAAAAAAAAAAAAAABBBBBBBBAB LETTER ALPSLFMDEEMCBFRSPKLEMFHRSCJLJKUHPNMBBNNVVRKRHUTDJUKANJHBTPDFSVDEVU SIDE 121212122121212121111111112212122222112222111221112112212112212212 DIRECTION IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIOOOOOOOIOOIOOIOOIOOOOIOOIIOOIIO changed: 0 step 102 100001100110100100011011011011011101111100011011011010100110110011 fail ^^ SLOT BAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBAABBAAAAAAAAAAAAAABBBBBBBBAB LETTER ALPSLFMDEEMCBFRSPKLEMFHRSCJLJKUHPNMBBNNVVRKRHUTDJUKANJHBTPDFSVDEVU SIDE 121212122121212121111111112212122222112222111221112112212112212212 DIRECTION IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIOOOOOOOIOOIOOIOOIOOOOIOOIIOOIIO changed: 011 step 103 100001100110100100011011011011011101111100011011011010100110101111 fail ^^ SLOT BAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBAABBAAAAAAAAAAAAAABBBBBBBBAB LETTER ALPSLFMDEEMCBFRSPKLEMFHRSCJLJKUHPNMBBNNVVRKRHUTDJUKANJHBTPDFSVDEVU SIDE 121212122121212121111111112212122222112222111221112112212112212212 DIRECTION IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIOOOOOOOIOOIOOIOOIOOOOIOOIIOOIIO changed: 0 step 104 100001100110100100011011011011011101111100011011011010100110101011 fail ^^ test 2: *** FAIL *************************** 14 steps failed SLOT BAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBAABBAAAAAAAAAAAAAABBBBBBBBAB LETTER ALPSLFMDEEMCBFRSPKLEMFHRSCJLJKUHPNMBBNNVVRKRHUTDJUKANJHBTPDFSVDEVU SIDE 121212122121212121111111112212122222112222111221112112212112212212 DIRECTION IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIOOOOOOOIOOIOOIOOIOOOOIOOIIOOIIO this fail OO all fails OO was hi 111111111111111111111111111111111111111111111111111111111111111111 rising ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ ^^^^^^^^^^^^^^^^^^^^ ^^^^ falling vvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvv vvvvvvvvvvvvvvvvvvvv vvvv was lo 00000000000000000000000000000000000000 00000000000000000000 0000 total fails 2, total passes 0 space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C toggle comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT BAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBAABBAAAAAAAAAAAAAABBBBBBBBAB LETTER ALPSLFMDEEMCBFRSPKLEMFHRSCJLJKUHPNMBBNNVVRKRHUTDJUKANJHBTPDFSVDEVU SIDE 121212122121212121111111112212122222112222111221112112212112212212 DIRECTION IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIOOOOOOOIOOIOOIOOIOOOOIOOIIOOIIO all fails OO was lo 00000000000000000000000000000000000000 00000000000000000000 0000 falling vvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvv vvvvvvvvvvvvvvvvvvvv vvvv rising ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ ^^^^^^^^^^^^^^^^^^^^ ^^^^ was hi 111111111111111111111111111111111111111111111111111111111111111111 total fails 2, total passes 0 Main menu Thu Aug 20 15:38:07 2015 test file is: tests\m222.new delay is: 0 trigger is: 1 1 read test file 2 set test delay 3 set test trigger 4 run test 5 output loading test 8 diags 9 exit UUT power is okay Thu Aug 20 15:38:26 2015 space single step O run once (one test, all steps) F run, stop on fail G go (run tests N run, stop on fail, no print S scope (run, no print) C toggle comment printout + increase speed (less delay) - decrease speed (more delay)(slower) Q quit test step 1 100000000000000000000000000000000001111100010011011010100100110001 step 2 100000000000000000000000000000000001111100100011011010100100110001 step 3 100000000000000000000000000000000001111100000011011010100100110001 step 4 100000000000000000000000000000000001111100000100011010100100110001 step 5 100000000000000000000000000000000001111100000000011010100100110001 step 6 100000000000000000000000000000000001111100000000100010100100110001 step 7 100000000000000000000000000000000001111100000000000010100100110001 step 8 100000000000000000000000000000000001111100000000000101010100110001 step 9 100000000000000000000000000000000001111100000000000001010100110001 step 10 100000000000000000000000000000000001111100000000000001011000110001 step 11 100000000000000000000000000000000001111100000000000001010000110001 step 12 100000000000000000000000000000000001111100000000000001010001100001 step 13 100000000000000000000000000000000001111100000000000001010000100001 step 14 100000000000000000000000000000000001111100000000000001010000100001 step 15 100000000000010000000000000000000000111101000000000001010000100001 step 16 100000000000010010000000000000000000110111000000000001010000100001 step 17 100000000000010010000000000000000000110111111000000001010000100001 step 18 100000000000010010000000000000000000110111011000000001010000100001 step 19 100000000000010010000000000000000000110111011111000001010000100001 step 20 100000000000010010000000000000000000110111011011000001010000100001 step 21 100000000000010010000000000000000000110111011011111001010000100001 step 22 100000000000010010000000000000000000110111011011011001010000100001 step 23 100000000000010010000000000000000000110111011011011110100000100001 step 24 100000000000010010000000000000000000110111011011011010100000100001 step 25 100000000000010010000000000000000000110111011011011010101110100001 step 26 100000000000010010000000000000000000110111011011011010100110100001 step 27 100000000000010010000000000000000000110111011011011010100111111001 step 28 100000000000010010000000000000000000110111011011011010100110111001 step 29 100000000000000010000000000000000001110110011011011010100110111001 step 30 100000000000000000000000000000000001111100011011011010100110111001 step 31 100000000000000000000000000000000001111100011011011010100110111001 step 32 100001000000000000000000000000000001111100011011011010100110111001 step 33 100001100000000000000000000000000001111100011011011010100110111001 step 34 100001100100000000000000000000000001111100011011011010100110111001 step 35 100001100110000000000000000000000001111100011011011010100110111001 step 36 100001100110100000000000000000000001111100011011011010100110111001 step 37 100001100110100100000000000000000001111100011011011010100110111001 step 38 100001100110100100010000000000000001111100011011011010100110111001 step 39 100001100110100100011000000000000001111100011011011010100110111001 step 40 100001100110100100011010000000000001111100011011011010100110111001 step 41 100001100110100100011011000000000001111100011011011010100110111001 step 42 100001100110100100011011010000000001111100011011011010100110111001 step 43 100001100110100100011011011000000001111100011011011010100110111001 step 44 100001100110100100011011011010000001111100011011011010100110111001 step 45 100001100110100100011011011011000001111100011011011010100110111001 step 46 100001100110100100011011011011010001111100011011011010100110111001 step 47 100001100110100100011011011011011001111100011011011010100110111001 step 48 100001100110100100011011011011011101111100011011011010100110111001 step 49 110001100110100100011011011011011100110111011011011010100110111001 step 50 100001100110100100011011011011011101111100011011011010100110111001 step 51 101001100110100100011011011011011100110111011011011010100110111001 step 52 100001100110100100011011011011011101111100011011011010100110111001 step 53 100101100110100100011011011011011100110111011011011010100110111001 step 54 100001100110100100011011011011011101111100011011011010100110111001 step 55 100011100110100100011011011011011100110111011011011010100110111001 step 56 100001100110100100011011011011011101111100011011011010100110111001 step 57 100001110110100100011011011011011100110111011011011010100110111001 step 58 100001100110100100011011011011011101111100011011011010100110111001 step 59 100001101110100100011011011011011100110111011011011010100110111001 step 60 100001100110100100011011011011011101111100011011011010100110111001 step 61 100001100111100100011011011011011100111101011011011010100110111001 step 62 100001100110100100011011011011011101111100011011011010100110111001 step 63 100001100110110100011011011011011100111101011011011010100110111001 step 64 100001100110100100011011011011011101111100011011011010100110111001 step 65 100001100110101100011011011011011101110110011011011010100110111001 step 66 100001100110100100011011011011011101111100011011011010100110111001 step 67 100001100110100110011011011011011101110110011011011010100110111001 step 68 100001100110100100011011011011011101111100011011011010100110111001 step 69 100001100110100101011011011011011101001111011011011010100110111001 step 70 100001100110100100011011011011011101111100011011011010100110111001 step 71 100001100110100100111011011011011101001111011011011010100110111001 step 72 100001100110100100011011011011011101111100011011011010100110111001 step 73 100001100110100100011111011011011101001111011011011010100110111001 step 74 100001100110100100011011011011011101111100011011011010100110111001 step 75 100001100110100100011011111011011101001111011011011010100110111001 step 76 100001100110100100011011011011011101111100011011011010100110111001 step 77 100001100110100100011011011111011101001111011011011010100110111001 step 78 100001100110100100011011011011011101111100011011011010100110111001 step 79 100001100110100100011011011011111101001111011011011010100110111001 step 80 100001100110100100011011011011011101111100011011011010100110111001 step 81 100001100110100100011011011011011111101110011011011010100110111001 step 82 100001100110100100011011011011011101111100011011011010100110111001 step 83 100001100110100100011011011011011101111100011011011010100110110101 step 84 100001100110100100011011011011011101111100011011011010100110110001 step 85 100001100110100100011011011011011101111100011011011010100110100101 step 86 100001100110100100011011011011011101111100011011011010100110100001 step 87 100001100110100100011011011011011101111100011011011010100110100101 step 88 100001100110100100011011011011011101111100011011011010100110100001 SLOT BAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBAABBAAAAAAAAAAAAAABBBBBBBBAB LETTER ALPSLFMDEEMCBFRSPKLEMFHRSCJLJKUHPNMBBNNVVRKRHUTDJUKANJHBTPDFSVDEVU SIDE 121212122121212121111111112212122222112222111221112112212112212212 DIRECTION IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIOOOOOOOIOOIOOIOOIOOOOIOOIIOOIIO changed: 11 step 89 100001100110100100011011011011011101111100011011011010100110100111 fail ^ SLOT BAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBAABBAAAAAAAAAAAAAABBBBBBBBAB LETTER ALPSLFMDEEMCBFRSPKLEMFHRSCJLJKUHPNMBBNNVVRKRHUTDJUKANJHBTPDFSVDEVU SIDE 121212122121212121111111112212122222112222111221112112212112212212 DIRECTION IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIOOOOOOOIOOIOOIOOIOOOOIOOIIOOIIO changed: 0 step 90 100001100110100100011011011011011101111100011011011010100110100011 fail ^ SLOT BAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBAABBAAAAAAAAAAAAAABBBBBBBBAB LETTER ALPSLFMDEEMCBFRSPKLEMFHRSCJLJKUHPNMBBNNVVRKRHUTDJUKANJHBTPDFSVDEVU SIDE 121212122121212121111111112212122222112222111221112112212112212212 DIRECTION IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIOOOOOOOIOOIOOIOOIOOOOIOOIIOOIIO changed: 11 step 91 100001100110100100011011011011011101111100011011011010100110101111 fail ^ SLOT BAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBAABBAAAAAAAAAAAAAABBBBBBBBAB LETTER ALPSLFMDEEMCBFRSPKLEMFHRSCJLJKUHPNMBBNNVVRKRHUTDJUKANJHBTPDFSVDEVU SIDE 121212122121212121111111112212122222112222111221112112212112212212 DIRECTION IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIOOOOOOOIOOIOOIOOIOOOOIOOIIOOIIO changed: 0 step 92 100001100110100100011011011011011101111100011011011010100110101011 fail ^ step 93 100001100110100100011011011011011101111100011011011010100110111111 step 94 100001100110100100011011011011011101111100011011011010100110111011 SLOT BAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBAABBAAAAAAAAAAAAAABBBBBBBBAB LETTER ALPSLFMDEEMCBFRSPKLEMFHRSCJLJKUHPNMBBNNVVRKRHUTDJUKANJHBTPDFSVDEVU SIDE 121212122121212121111111112212122222112222111221112112212112212212 DIRECTION IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIOOOOOOOIOOIOOIOOIOOOOIOOIIOOIIO changed: 10 step 95 100001100110100100011011011011011101111100011011011010100110111101 fail ^ SLOT BAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBAABBAAAAAAAAAAAAAABBBBBBBBAB LETTER ALPSLFMDEEMCBFRSPKLEMFHRSCJLJKUHPNMBBNNVVRKRHUTDJUKANJHBTPDFSVDEVU SIDE 121212122121212121111111112212122222112222111221112112212112212212 DIRECTION IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIOOOOOOOIOOIOOIOOIOOOOIOOIIOOIIO changed: 0 step 96 100001100110100100011011011011011101111100011011011010100110111001 fail ^ SLOT BAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBAABBAAAAAAAAAAAAAABBBBBBBBAB LETTER ALPSLFMDEEMCBFRSPKLEMFHRSCJLJKUHPNMBBNNVVRKRHUTDJUKANJHBTPDFSVDEVU SIDE 121212122121212121111111112212122222112222111221112112212112212212 DIRECTION IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIOOOOOOOIOOIOOIOOIOOOOIOOIIOOIIO changed: 011 step 97 100001100110100100011011011011011101111100011011011010100110110111 fail ^^ SLOT BAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBAABBAAAAAAAAAAAAAABBBBBBBBAB LETTER ALPSLFMDEEMCBFRSPKLEMFHRSCJLJKUHPNMBBNNVVRKRHUTDJUKANJHBTPDFSVDEVU SIDE 121212122121212121111111112212122222112222111221112112212112212212 DIRECTION IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIOOOOOOOIOOIOOIOOIOOOOIOOIIOOIIO changed: 0 step 98 100001100110100100011011011011011101111100011011011010100110110011 fail ^^ SLOT BAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBAABBAAAAAAAAAAAAAABBBBBBBBAB LETTER ALPSLFMDEEMCBFRSPKLEMFHRSCJLJKUHPNMBBNNVVRKRHUTDJUKANJHBTPDFSVDEVU SIDE 121212122121212121111111112212122222112222111221112112212112212212 DIRECTION IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIOOOOOOOIOOIOOIOOIOOOOIOOIIOOIIO changed: 0110 step 99 100001100110100100011011011011011101111100011011011010100110101101 fail ^^ SLOT BAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBAABBAAAAAAAAAAAAAABBBBBBBBAB LETTER ALPSLFMDEEMCBFRSPKLEMFHRSCJLJKUHPNMBBNNVVRKRHUTDJUKANJHBTPDFSVDEVU SIDE 121212122121212121111111112212122222112222111221112112212112212212 DIRECTION IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIOOOOOOOIOOIOOIOOIOOOOIOOIIOOIIO changed: 0 step 100 100001100110100100011011011011011101111100011011011010100110101001 fail ^^ SLOT BAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBAABBAAAAAAAAAAAAAABBBBBBBBAB LETTER ALPSLFMDEEMCBFRSPKLEMFHRSCJLJKUHPNMBBNNVVRKRHUTDJUKANJHBTPDFSVDEVU SIDE 121212122121212121111111112212122222112222111221112112212112212212 DIRECTION IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIOOOOOOOIOOIOOIOOIOOOOIOOIIOOIIO changed: 1011 step 101 100001100110100100011011011011011101111100011011011010100110110111 fail ^^ SLOT BAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBAABBAAAAAAAAAAAAAABBBBBBBBAB LETTER ALPSLFMDEEMCBFRSPKLEMFHRSCJLJKUHPNMBBNNVVRKRHUTDJUKANJHBTPDFSVDEVU SIDE 121212122121212121111111112212122222112222111221112112212112212212 DIRECTION IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIOOOOOOOIOOIOOIOOIOOOOIOOIIOOIIO changed: 0 step 102 100001100110100100011011011011011101111100011011011010100110110011 fail ^^ SLOT BAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBAABBAAAAAAAAAAAAAABBBBBBBBAB LETTER ALPSLFMDEEMCBFRSPKLEMFHRSCJLJKUHPNMBBNNVVRKRHUTDJUKANJHBTPDFSVDEVU SIDE 121212122121212121111111112212122222112222111221112112212112212212 DIRECTION IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIOOOOOOOIOOIOOIOOIOOOOIOOIIOOIIO changed: 011 step 103 100001100110100100011011011011011101111100011011011010100110101111 fail ^^ SLOT BAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBAABBAAAAAAAAAAAAAABBBBBBBBAB LETTER ALPSLFMDEEMCBFRSPKLEMFHRSCJLJKUHPNMBBNNVVRKRHUTDJUKANJHBTPDFSVDEVU SIDE 121212122121212121111111112212122222112222111221112112212112212212 DIRECTION IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIOOOOOOOIOOIOOIOOIOOOOIOOIIOOIIO changed: 0 step 104 100001100110100100011011011011011101111100011011011010100110101011 fail ^^ test 1: *** FAIL *************************** 14 steps failed SLOT BAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBAABBAAAAAAAAAAAAAABBBBBBBBAB LETTER ALPSLFMDEEMCBFRSPKLEMFHRSCJLJKUHPNMBBNNVVRKRHUTDJUKANJHBTPDFSVDEVU SIDE 121212122121212121111111112212122222112222111221112112212112212212 DIRECTION IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIOOOOOOOIOOIOOIOOIOOOOIOOIIOOIIO this fail OO all fails OO was hi 111111111111111111111111111111111111111111111111111111111111111111 rising ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ ^^^^^^^^^^^^^^^^^^^^ ^^^^ falling vvvv vv v vv vvv v v v v vvvvv vvvv vvvvvvvvvvvvv v vvvv was lo 00000000000000000000000000000000000000 00000000000000000000 0000 total fails 1, total passes 0 space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C toggle comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit step 1 100000000000000000000000000000000001111100011011011010100110101001 step 2 100000000000000000000000000000000001111100100011011010100110101001 step 3 100000000000000000000000000000000001111100000011011010100110101001 step 4 100000000000000000000000000000000001111100000100011010100110101001 step 5 100000000000000000000000000000000001111100000000011010100110101001 step 6 100000000000000000000000000000000001111100000000100010100110101001 step 7 100000000000000000000000000000000001111100000000000010100110101001 step 8 100000000000000000000000000000000001111100000000000101010110101001 step 9 100000000000000000000000000000000001111100000000000001010110101001 step 10 100000000000000000000000000000000001111100000000000001011000101001 step 11 100000000000000000000000000000000001111100000000000001010000101001 step 12 100000000000000000000000000000000001111100000000000001010001100001 step 13 100000000000000000000000000000000001111100000000000001010000100001 step 14 100000000000000000000000000000000001111100000000000001010000100001 step 15 100000000000010000000000000000000000111101000000000001010000100001 step 16 100000000000010010000000000000000000110111000000000001010000100001 step 17 100000000000010010000000000000000000110111111000000001010000100001 step 18 100000000000010010000000000000000000110111011000000001010000100001 step 19 100000000000010010000000000000000000110111011111000001010000100001 step 20 100000000000010010000000000000000000110111011011000001010000100001 step 21 100000000000010010000000000000000000110111011011111001010000100001 step 22 100000000000010010000000000000000000110111011011011001010000100001 step 23 100000000000010010000000000000000000110111011011011110100000100001 step 24 100000000000010010000000000000000000110111011011011010100000100001 step 25 100000000000010010000000000000000000110111011011011010101110100001 step 26 100000000000010010000000000000000000110111011011011010100110100001 step 27 100000000000010010000000000000000000110111011011011010100111111001 step 28 100000000000010010000000000000000000110111011011011010100110111001 step 29 100000000000000010000000000000000001110110011011011010100110111001 step 30 100000000000000000000000000000000001111100011011011010100110111001 step 31 100000000000000000000000000000000001111100011011011010100110111001 step 32 100001000000000000000000000000000001111100011011011010100110111001 step 33 100001100000000000000000000000000001111100011011011010100110111001 step 34 100001100100000000000000000000000001111100011011011010100110111001 step 35 100001100110000000000000000000000001111100011011011010100110111001 step 36 100001100110100000000000000000000001111100011011011010100110111001 step 37 100001100110100100000000000000000001111100011011011010100110111001 step 38 100001100110100100010000000000000001111100011011011010100110111001 step 39 100001100110100100011000000000000001111100011011011010100110111001 step 40 100001100110100100011010000000000001111100011011011010100110111001 step 41 100001100110100100011011000000000001111100011011011010100110111001 step 42 100001100110100100011011010000000001111100011011011010100110111001 step 43 100001100110100100011011011000000001111100011011011010100110111001 step 44 100001100110100100011011011010000001111100011011011010100110111001 step 45 100001100110100100011011011011000001111100011011011010100110111001 step 46 100001100110100100011011011011010001111100011011011010100110111001 step 47 100001100110100100011011011011011001111100011011011010100110111001 step 48 100001100110100100011011011011011101111100011011011010100110111001 step 49 110001100110100100011011011011011100110111011011011010100110111001 step 50 100001100110100100011011011011011101111100011011011010100110111001 step 51 101001100110100100011011011011011100110111011011011010100110111001 step 52 100001100110100100011011011011011101111100011011011010100110111001 step 53 100101100110100100011011011011011100110111011011011010100110111001 step 54 100001100110100100011011011011011101111100011011011010100110111001 step 55 100011100110100100011011011011011100110111011011011010100110111001 step 56 100001100110100100011011011011011101111100011011011010100110111001 step 57 100001110110100100011011011011011100110111011011011010100110111001 step 58 100001100110100100011011011011011101111100011011011010100110111001 step 59 100001101110100100011011011011011100110111011011011010100110111001 step 60 100001100110100100011011011011011101111100011011011010100110111001 step 61 100001100111100100011011011011011100111101011011011010100110111001 step 62 100001100110100100011011011011011101111100011011011010100110111001 step 63 100001100110110100011011011011011100111101011011011010100110111001 step 64 100001100110100100011011011011011101111100011011011010100110111001 step 65 100001100110101100011011011011011101110110011011011010100110111001 step 66 100001100110100100011011011011011101111100011011011010100110111001 step 67 100001100110100110011011011011011101110110011011011010100110111001 step 68 100001100110100100011011011011011101111100011011011010100110111001 step 69 100001100110100101011011011011011101001111011011011010100110111001 step 70 100001100110100100011011011011011101111100011011011010100110111001 step 71 100001100110100100111011011011011101001111011011011010100110111001 step 72 100001100110100100011011011011011101111100011011011010100110111001 step 73 100001100110100100011111011011011101001111011011011010100110111001 step 74 100001100110100100011011011011011101111100011011011010100110111001 step 75 100001100110100100011011111011011101001111011011011010100110111001 step 76 100001100110100100011011011011011101111100011011011010100110111001 step 77 100001100110100100011011011111011101001111011011011010100110111001 step 78 100001100110100100011011011011011101111100011011011010100110111001 step 79 100001100110100100011011011011111101001111011011011010100110111001 step 80 100001100110100100011011011011011101111100011011011010100110111001 step 81 100001100110100100011011011011011111101110011011011010100110111001 step 82 100001100110100100011011011011011101111100011011011010100110111001 step 83 100001100110100100011011011011011101111100011011011010100110110101 step 84 100001100110100100011011011011011101111100011011011010100110110001 step 85 100001100110100100011011011011011101111100011011011010100110100101 step 86 100001100110100100011011011011011101111100011011011010100110100001 step 87 100001100110100100011011011011011101111100011011011010100110100101 step 88 100001100110100100011011011011011101111100011011011010100110100001 SLOT BAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBAABBAAAAAAAAAAAAAABBBBBBBBAB LETTER ALPSLFMDEEMCBFRSPKLEMFHRSCJLJKUHPNMBBNNVVRKRHUTDJUKANJHBTPDFSVDEVU SIDE 121212122121212121111111112212122222112222111221112112212112212212 DIRECTION IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIOOOOOOOIOOIOOIOOIOOOOIOOIIOOIIO changed: 11 step 89 100001100110100100011011011011011101111100011011011010100110100111 fail ^ SLOT BAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBAABBAAAAAAAAAAAAAABBBBBBBBAB LETTER ALPSLFMDEEMCBFRSPKLEMFHRSCJLJKUHPNMBBNNVVRKRHUTDJUKANJHBTPDFSVDEVU SIDE 121212122121212121111111112212122222112222111221112112212112212212 DIRECTION IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIOOOOOOOIOOIOOIOOIOOOOIOOIIOOIIO changed: 0 step 90 100001100110100100011011011011011101111100011011011010100110100011 fail ^ SLOT BAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBAABBAAAAAAAAAAAAAABBBBBBBBAB LETTER ALPSLFMDEEMCBFRSPKLEMFHRSCJLJKUHPNMBBNNVVRKRHUTDJUKANJHBTPDFSVDEVU SIDE 121212122121212121111111112212122222112222111221112112212112212212 DIRECTION IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIOOOOOOOIOOIOOIOOIOOOOIOOIIOOIIO changed: 11 step 91 100001100110100100011011011011011101111100011011011010100110101111 fail ^ SLOT BAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBAABBAAAAAAAAAAAAAABBBBBBBBAB LETTER ALPSLFMDEEMCBFRSPKLEMFHRSCJLJKUHPNMBBNNVVRKRHUTDJUKANJHBTPDFSVDEVU SIDE 121212122121212121111111112212122222112222111221112112212112212212 DIRECTION IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIOOOOOOOIOOIOOIOOIOOOOIOOIIOOIIO changed: 0 step 92 100001100110100100011011011011011101111100011011011010100110101011 fail ^ step 93 100001100110100100011011011011011101111100011011011010100110111111 step 94 100001100110100100011011011011011101111100011011011010100110111011 SLOT BAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBAABBAAAAAAAAAAAAAABBBBBBBBAB LETTER ALPSLFMDEEMCBFRSPKLEMFHRSCJLJKUHPNMBBNNVVRKRHUTDJUKANJHBTPDFSVDEVU SIDE 121212122121212121111111112212122222112222111221112112212112212212 DIRECTION IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIOOOOOOOIOOIOOIOOIOOOOIOOIIOOIIO changed: 10 step 95 100001100110100100011011011011011101111100011011011010100110111101 fail ^ SLOT BAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBAABBAAAAAAAAAAAAAABBBBBBBBAB LETTER ALPSLFMDEEMCBFRSPKLEMFHRSCJLJKUHPNMBBNNVVRKRHUTDJUKANJHBTPDFSVDEVU SIDE 121212122121212121111111112212122222112222111221112112212112212212 DIRECTION IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIOOOOOOOIOOIOOIOOIOOOOIOOIIOOIIO changed: 0 step 96 100001100110100100011011011011011101111100011011011010100110111001 fail ^ SLOT BAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBAABBAAAAAAAAAAAAAABBBBBBBBAB LETTER ALPSLFMDEEMCBFRSPKLEMFHRSCJLJKUHPNMBBNNVVRKRHUTDJUKANJHBTPDFSVDEVU SIDE 121212122121212121111111112212122222112222111221112112212112212212 DIRECTION IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIOOOOOOOIOOIOOIOOIOOOOIOOIIOOIIO changed: 011 step 97 100001100110100100011011011011011101111100011011011010100110110111 fail ^^ SLOT BAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBAABBAAAAAAAAAAAAAABBBBBBBBAB LETTER ALPSLFMDEEMCBFRSPKLEMFHRSCJLJKUHPNMBBNNVVRKRHUTDJUKANJHBTPDFSVDEVU SIDE 121212122121212121111111112212122222112222111221112112212112212212 DIRECTION IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIOOOOOOOIOOIOOIOOIOOOOIOOIIOOIIO changed: 0 step 98 100001100110100100011011011011011101111100011011011010100110110011 fail ^^ SLOT BAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBAABBAAAAAAAAAAAAAABBBBBBBBAB LETTER ALPSLFMDEEMCBFRSPKLEMFHRSCJLJKUHPNMBBNNVVRKRHUTDJUKANJHBTPDFSVDEVU SIDE 121212122121212121111111112212122222112222111221112112212112212212 DIRECTION IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIOOOOOOOIOOIOOIOOIOOOOIOOIIOOIIO changed: 0110 step 99 100001100110100100011011011011011101111100011011011010100110101101 fail ^^ SLOT BAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBAABBAAAAAAAAAAAAAABBBBBBBBAB LETTER ALPSLFMDEEMCBFRSPKLEMFHRSCJLJKUHPNMBBNNVVRKRHUTDJUKANJHBTPDFSVDEVU SIDE 121212122121212121111111112212122222112222111221112112212112212212 DIRECTION IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIOOOOOOOIOOIOOIOOIOOOOIOOIIOOIIO changed: 0 step 100 100001100110100100011011011011011101111100011011011010100110101001 fail ^^ SLOT BAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBAABBAAAAAAAAAAAAAABBBBBBBBAB LETTER ALPSLFMDEEMCBFRSPKLEMFHRSCJLJKUHPNMBBNNVVRKRHUTDJUKANJHBTPDFSVDEVU SIDE 121212122121212121111111112212122222112222111221112112212112212212 DIRECTION IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIOOOOOOOIOOIOOIOOIOOOOIOOIIOOIIO changed: 1011 step 101 100001100110100100011011011011011101111100011011011010100110110111 fail ^^ SLOT BAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBAABBAAAAAAAAAAAAAABBBBBBBBAB LETTER ALPSLFMDEEMCBFRSPKLEMFHRSCJLJKUHPNMBBNNVVRKRHUTDJUKANJHBTPDFSVDEVU SIDE 121212122121212121111111112212122222112222111221112112212112212212 DIRECTION IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIOOOOOOOIOOIOOIOOIOOOOIOOIIOOIIO changed: 0 step 102 100001100110100100011011011011011101111100011011011010100110110011 fail ^^ SLOT BAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBAABBAAAAAAAAAAAAAABBBBBBBBAB LETTER ALPSLFMDEEMCBFRSPKLEMFHRSCJLJKUHPNMBBNNVVRKRHUTDJUKANJHBTPDFSVDEVU SIDE 121212122121212121111111112212122222112222111221112112212112212212 DIRECTION IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIOOOOOOOIOOIOOIOOIOOOOIOOIIOOIIO changed: 011 step 103 100001100110100100011011011011011101111100011011011010100110101111 fail ^^ SLOT BAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBAABBAAAAAAAAAAAAAABBBBBBBBAB LETTER ALPSLFMDEEMCBFRSPKLEMFHRSCJLJKUHPNMBBNNVVRKRHUTDJUKANJHBTPDFSVDEVU SIDE 121212122121212121111111112212122222112222111221112112212112212212 DIRECTION IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIOOOOOOOIOOIOOIOOIOOOOIOOIIOOIIO changed: 0 step 104 100001100110100100011011011011011101111100011011011010100110101011 fail ^^ test 2: *** FAIL *************************** 14 steps failed SLOT BAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBAABBAAAAAAAAAAAAAABBBBBBBBAB LETTER ALPSLFMDEEMCBFRSPKLEMFHRSCJLJKUHPNMBBNNVVRKRHUTDJUKANJHBTPDFSVDEVU SIDE 121212122121212121111111112212122222112222111221112112212112212212 DIRECTION IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIOOOOOOOIOOIOOIOOIOOOOIOOIIOOIIO this fail OO all fails OO was hi 111111111111111111111111111111111111111111111111111111111111111111 rising ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ ^^^^^^^^^^^^^^^^^^^^ ^^^^ falling vvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvv vvvvvvvvvvvvvvvvvvvv vvvv was lo 00000000000000000000000000000000000000 00000000000000000000 0000 total fails 2, total passes 0 space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C toggle comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit up to this point: PINS that are always low PINS that are always high 1 I BA1 CARRY IN-N, (TO E9-5 7482 C0) C-N TO ADDER2 40 O AV2 CARRY OUT-N (E9-10 7482 C2) 61 I BS2 PHASE (SELECTS POLARITY OF RWB OUT, 0 -> INVERTED) 66 O BU2 +3.5V space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C toggle comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit up to this point: PINS that are always low PINS that are always high 1 I BA1 CARRY IN-N, (TO E9-5 7482 C0) C-N TO ADDER2 40 O AV2 CARRY OUT-N (E9-10 7482 C2) 61 I BS2 PHASE (SELECTS POLARITY OF RWB OUT, 0 -> INVERTED) 66 O BU2 +3.5V space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C toggle comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit failure mode analysis: pin: 62 O BV1 RWB OUT (=RWB 2 IF PHASE=1; =RWB 2-N IF PHASE=0) SLOT BAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBAABBAAAAAAAAAAAAAABBBBBBBBAB LETTER ALPSLFMDEEMCBFRSPKLEMFHRSCJLJKUHPNMBBNNVVRKRHUTDJUKANJHBTPDFSVDEVU SIDE 121212122121212121111111112212122222112222111221112112212112212212 DIRECTION IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIOOOOOOOIOOIOOIOOIOOOOIOOIIOOIIO fails LO: 1 11 11 1 1 11 11 11 11 111 11111 11 11 11 1 1 11 1 1111 fails LO: 0000 00 0 00 000 0 0 0 0 0 000 0 0 0 0 00 0 00 fails HI: 1 11 11 1 1 11 11 11 11 111 11111 11 11 11 1 1 11 1 111 fails HI: 0000 00 0 00 000 0 0 0 0 0 000 0 0 0 0 00 0 00 pin: 63 O BD2 RWB 3 SLOT BAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBAABBAAAAAAAAAAAAAABBBBBBBBAB LETTER ALPSLFMDEEMCBFRSPKLEMFHRSCJLJKUHPNMBBNNVVRKRHUTDJUKANJHBTPDFSVDEVU SIDE 121212122121212121111111112212122222112222111221112112212112212212 DIRECTION IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIOOOOOOOIOOIOOIOOIOOOOIOOIIOOIIO fails LO: 1 11 11 1 1 11 11 11 11 111 11111 11 11 11 1 1 11 11 111 fails LO: 0000 00 0 00 000 0 0 0 0 0 000 0 0 0 0 00 0 0 0 fails HI: 1 11 11 1 1 11 11 11 11 111 11111 11 11 11 1 1 11 11 111 fails HI: 0000 00 0 00 000 0 0 0 0 0 000 0 0 0 0 00 0 0 00 space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C toggle comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT BAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBAABBAAAAAAAAAAAAAABBBBBBBBAB LETTER ALPSLFMDEEMCBFRSPKLEMFHRSCJLJKUHPNMBBNNVVRKRHUTDJUKANJHBTPDFSVDEVU SIDE 121212122121212121111111112212122222112222111221112112212112212212 DIRECTION IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIOOOOOOOIOOIOOIOOIOOOOIOOIIOOIIO all fails OO was lo 00000000000000000000000000000000000000 00000000000000000000 0000 falling vvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvv vvvvvvvvvvvvvvvvvvvv vvvv rising ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ ^^^^^^^^^^^^^^^^^^^^ ^^^^ was hi 111111111111111111111111111111111111111111111111111111111111111111 total fails 2, total passes 0 Main menu Thu Aug 20 15:40:01 2015 test file is: tests\m222.new delay is: 0 trigger is: 1 1 read test file 2 set test delay 3 set test trigger 4 run test 5 output loading test 8 diags 9 exit Enter test file name? trying to open test file: tests\m222.new reading test file: tests\m222.new comment: M222 PCB REV B SCHEMATIC REV A LINC TAPE REGISTERS comment: comment: TERMINOLOGY- SIGNALS REFER TO VOL4 M222 SCHEMATIC. comment: comment: BUT... comment: comment: DEC USES AND-NOR GATES TO ROUTE THE ADDER A AND B INPUTS, SO... comment: DEC RENAMED THE ADDER TO NEGATIVE LOGIC TERMS (I.E. A-N + B-N + C-N -> SUM-N, C1-N). comment: (NOT THE 7482 DATASHEET NAMES OF A + B + C -> SUM, C1). comment: comment: SO, WITH ALL 'AND ENABLES' LOW, THE AND-NOR OUTPUTS = HIGH. comment: WITH C-L HIGH, THE ADDER OUTPUT IS SUM-N=1, C1-N=1; comment: THE INVERTED ADDER OUTPUT IS LOW (TAPE BUS). comment: AND THERE IS NO CARRY (C1-N IS HI). comment: comment: THE TWO ADDERS, TWO REGISTER BITS, ETC ARE LABELED BIT 2 (EVEN, MSB) AND BIT 3 (ODD, LSB). comment: THE ADDERS ARE REFERRED TO AS 'ADDER2' (MSB) AND 'ADDER3' (LSB). comment: comment: POWER PINS: comment: AA2 +5V comment: AT1 GROUND comment: AC2 GROUND comment: BA2 +5V comment: BT1 GROUND comment: BC2 GROUND comment: comment: (ALL PINS ARE USED). comment: comment: pins: PINS pins: 1 I BA1 CARRY IN-N, (TO E9-5 7482 C0) C-N TO ADDER2 pins: 2 I AL2 AND-NOR ENABLE: TAC TAC3 TO PIN BB2 (TO ADDER3) TAC2 TO PIN AN2 (TO ADDER2) pins: 3 I AP1 AND-NOR ENABLE: TMA SETUP (TMAS)3 TO PIN BB2 (TO ADDER3), (TMAS)3 TO PIN AN2 (TO ADDER2) pins: 4 I AS2 AND-NOR ENABLE: TMA TMA3 TO PIN BB2 (TO ADDER3), TMA2 TO PIN AN2 (TO ADDER2) pins: 5 I AL1 AND-NOR ENABLE: PIN AF2 TO PIN BB2 (TO ADDER3), PIN AM1 TO PIN AN2 (TO ADDER2) pins: 6 I AF2 AND-NOR INPUT (AL1 ENABLES) TO PIN BB2 (TO ADDER3). pins: 7 I AM1 AND-NOR INPUT (AL1 ENABLES) TO PIN AN2 (TO ADDER2) pins: 8 I AD2 AND-NOR ENABLE: RWB RWB3 TO PIN BB2 (TO ADDER3), RWB2 TO PIN AN2 (TO ADDER2) pins: 9 I AE2 AND-NOR ENABLE: PIN AE1 TO PIN BB2 (TO ADDER3), PIN AM2 TO PIN AN2 (TO ADDER2) pins: 10 I AE1 AND-NOR INPUT (AE2 ENABLES) TO PIN BB2 (TO ADDER3). pins: 11 I AM2 AND-NOR INPUT (AE2 ENABLES) TO PIN AN2 (TO ADDER2) pins: 12 I AC1 AND-NOR INPUT, AND WITH PIN AB2 TO PIN BB2 (TO ADDER3) pins: 13 I AB2 AND-NOR INPUT, AND WITH PIN AC1 TO PIN BB2 (TO ADDER3) pins: 14 I AF1 AND-NOR INPUT (AND WITH ITSELF) TO PIN BB2 (TO ADDER3) pins: 15 I AR2 AND-NOR INPUT, AND WITH PIN AS1 TO PIN AN2 (TO ADDER2) pins: 16 I AS1 AND-NOR INPUT, AND WITH PIN AR2 TO PIN AN2 (TO ADDER2) pins: 17 I AP2 AND-NOR INPUT (AND WITH ITSELF) TO PIN AN2 (TO ADDER2) pins: 18 I BK1 AND-NOR ENABLE: TB3 TO PIN BB1 (TO ADDER3), TB2 TO PIN BN1 (TO ADDER2) pins: 19 I BL1 AND-NOR ENABLE: PIN BE1 TO PIN BB1 (TO ADDER3), PIN BM1 TO PIN BN1 (TO ADDER2) pins: 20 I BE1 AND-NOR INPUT (BL1 ENABLES) TO PIN BB1 (TO ADDER3). pins: 21 I BM1 AND-NOR INPUT (BL1 ENABLES) TO PIN BN1 (TO ADDER2) pins: 22 I BF1 AND-NOR ENABLE: PIN BH1 TO PIN BB1 (TO ADDER3), PIN BR1 TO PIN BN1 (TO ADDER2) pins: 23 I BH1 AND-NOR INPUT (BF1 ENABLES): TO PIN BB1 (TO ADDER3), pins: 24 I BR1 AND-NOR INPUT (BF1 ENABLES): TO PIN BN1 (TO ADDER2) pins: 25 I BS1 AND-NOR ENABLE: PIN BC1 TO PIN BB1 (TO ADDER3), PIN BJ2 TO PIN BN1 (TO ADDER2) pins: 26 I BC1 AND-NOR INPUT (BS1 ENABLES): TO PIN BB1 (TO ADDER3), pins: 27 I BJ2 AND-NOR INPUT (BS1 ENABLES): TO PIN BN1 (TO ADDER2) pins: 28 I BL2 AND-NOR ENABLE: PIN BJ1 TO PIN BB1 (TO ADDER3), PIN BK2 TO PIN BN1 (TO ADDER2) pins: 29 I BJ1 AND-NOR INPUT (BL2 ENABLES): TO PIN BB1 (TO ADDER3), pins: 30 I BK2 AND-NOR INPUT (BL2 ENABLES): TO PIN BN1 (TO ADDER2) pins: 31 I BU1 AND-NOR ENABLE: PIN BH2 TO PIN BB1 (TO ADDER3), PIN BP2 TO PIN BN1 (TO ADDER2) pins: 32 I BH2 AND-NOR INPUT (BU1 ENABLES): TO PIN BB1 (TO ADDER3), pins: 33 I BP2 AND-NOR INPUT (BU1 ENABLES): TO PIN BN1 (TO ADDER2) pins: 34 I BN2 AND-NOR INPUT (AND WITH BM2): TO PIN BN1 (TO ADDER2) pins: 35 I BM2 AND-NOR INPUT (AND WITH BM2): TO PIN BN1 (TO ADDER2) pins: 36 O BB2 AND-NOR OUTPUT, (DRIVES E9-2 7482 A1) TO ADDER3 INPUT pins: 37 O BB1 AND-NOR OUTPUT, (DRIVES E9-3 7482 B1) TO ADDER3 INPUT pins: 38 O BN1 AND-NOR OUTPUT, (DRIVES E9-14 7482 A2) TO ADDER2 INPUT pins: 39 O AN2 AND-NOR OUTPUT, (DRIVES E9-13 7482 B2) TO ADDER2 INPUT pins: 40 O AV2 CARRY OUT-N (E9-10 7482 C2) pins: 41 O BV2 TAPE BUS 2 OUTPUT (INVERTED ADDER2 SUM-N (E9-12 7482 SUM2) pins: 42 O BR2 TAPE BUS 3 OUTPUT (INVERTED ADDER3 SUM-N (E9-1 7482 SUM1) pins: 43 I AK1 LOAD TMA SETUP (FROM TAPE BUS) (RISING EDGE CLOCK) pins: 44 O AR1 TMA SETUP 2 pins: 45 O AH1 TMA SETUP 3 pins: 46 I AU2 LOAD TMA (FROM TAPE BUS) (RISING EDGE CLOCK) pins: 47 O AT2 TMA 2 pins: 48 O AD1 TMA 3 pins: 49 I AJ1 LOAD TBN (FROM TAPE BUS) (RISING EDGE CLOCK) pins: 50 O AU1 TBN 2 pins: 51 O AK2 TBN 3 pins: 52 I AA1 LOAD TAC (FROM TAPE BUS) (RISING EDGE CLOCK) pins: 53 O AN1 TAC 2 pins: 54 O AJ2 TAC 2-N pins: 55 O AH2 TAC 3 pins: 56 O AB1 TAC 3-N pins: 57 I BT2 LOAD TB (FROM TAPE BUS) (RISING EDGE CLOCK) pins: 58 O BP1 TB 2 pins: 59 O BD1 TB 3 pins: 60 I BF2 LOAD RWB (FROM TB) (JAMS CLEAR,SET) pins: 61 I BS2 PHASE (SELECTS POLARITY OF RWB OUT, 0 -> INVERTED) pins: 62 I AV1 RWB IN (SHIFTED INTO RWB 3) pins: 63 I BE2 SHIFT RWB (SHIFTS PIN AV1 INTO RWB 3, SHIFTS RWB3 TO RWB2) (RISING CLOCK) pins: 64 O BV1 RWB OUT (IF PHASE=1, =RWB 2; IF PHASE=0; =RWB 2-N) pins: 65 O BD2 RWB 3 pins: 66 O BU2 +3.5V pins: direction: IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIOOOOOOOIOOIOOIOOIOOOOIOOIIIIOOO comment: ; all registers are unknown comment: ; turn on C0, PHASE comment: ; with no ENABLES, BUS2,BUS3 is 11, C2 is 1 test 1: 1000000000000000000000000000000000011111000XX0XX0XX0XXXX0XX0110XX1 comment: comment: ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; comment: ; comment: ; set all registers LOW comment: ; comment: ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; comment: comment: ; load TMA SETUP from tape bus (00) test 2: 100 test 3: 0 comment: ; load TMA from tape bus (00) test 4: 100 test 5: 0 comment: ; load TBN from tape bus (00) test 6: 100 test 7: 0 comment: ; load TAC from tape bus (00) test 8: 10101 test 9: 0 comment: ; load TB from tape bus (00) test 10: 100 test 11: 0 comment: ; load RWB from TB (JAMS CLEAR AND PRESET) test 12: 1 00 test 13: 0 comment: ; (no change) test 14: 100000000000000000000000000000000001111100000000000001010000110001 comment: comment: comment: ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; comment: ; comment: ; set all registers HIGH comment: ; comment: ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; comment: comment: ; set pin AF1 (AND with itself) to clear pin BB2 (AND-NOR output) and set pin BR2 TAPE BUS 3 OUTPUT test 15: 1 0 1 comment: ; set pin AP2 (AND with itself) to clear pin AN2 (AND-NOR output) and set pin BV2 TAPE BUS 2 OUTPUT test 16: 1 0 1 comment: comment: comment: ; load TMA SETUP from tape bus (11) test 17: 111 test 18: 0 comment: ; load TMA from tape bus (11) test 19: 111 test 20: 0 comment: ; load TBN from tape bus (11) test 21: 111 test 22: 0 comment: ; load TAC from tape bus (11) test 23: 11010 test 24: 0 comment: ; load TB from tape bus (11) test 25: 111 test 26: 0 comment: ; load RWB from TB (JAMS CLEAR AND PRESET) test 27: 1 11 'test step' is too long expected 'test step' (66 columns of '0','1','X', or ' ') bad test file Main menu Thu Aug 20 16:33:59 2015 test file is: delay is: 0 trigger is: 1 1 read test file 2 set test delay 3 set test trigger 4 run test 5 output loading test 8 diags 9 exit Enter test file name? trying to open test file: tests\m222.new reading test file: tests\m222.new comment: M222 PCB REV B SCHEMATIC REV A LINC TAPE REGISTERS comment: comment: TERMINOLOGY- SIGNALS REFER TO VOL4 M222 SCHEMATIC. comment: comment: BUT... comment: comment: DEC USES AND-NOR GATES TO ROUTE THE ADDER A AND B INPUTS, SO... comment: DEC RENAMED THE ADDER TO NEGATIVE LOGIC TERMS (I.E. A-N + B-N + C-N -> SUM-N, C1-N). comment: (NOT THE 7482 DATASHEET NAMES OF A + B + C -> SUM, C1). comment: comment: SO, WITH ALL 'AND ENABLES' LOW, THE AND-NOR OUTPUTS = HIGH. comment: WITH C-L HIGH, THE ADDER OUTPUT IS SUM-N=1, C1-N=1; comment: THE INVERTED ADDER OUTPUT IS LOW (TAPE BUS). comment: AND THERE IS NO CARRY (C1-N IS HI). comment: comment: THE TWO ADDERS, TWO REGISTER BITS, ETC ARE LABELED BIT 2 (EVEN, MSB) AND BIT 3 (ODD, LSB). comment: THE ADDERS ARE REFERRED TO AS 'ADDER2' (MSB) AND 'ADDER3' (LSB). comment: comment: POWER PINS: comment: AA2 +5V comment: AT1 GROUND comment: AC2 GROUND comment: BA2 +5V comment: BT1 GROUND comment: BC2 GROUND comment: comment: (ALL PINS ARE USED). comment: comment: pins: PINS pins: 1 I BA1 CARRY IN-N, (TO E9-5 7482 C0) C-N TO ADDER2 pins: 2 I AL2 AND-NOR ENABLE: TAC TAC3 TO PIN BB2 (TO ADDER3) TAC2 TO PIN AN2 (TO ADDER2) pins: 3 I AP1 AND-NOR ENABLE: TMA SETUP (TMAS)3 TO PIN BB2 (TO ADDER3), (TMAS)3 TO PIN AN2 (TO ADDER2) pins: 4 I AS2 AND-NOR ENABLE: TMA TMA3 TO PIN BB2 (TO ADDER3), TMA2 TO PIN AN2 (TO ADDER2) pins: 5 I AL1 AND-NOR ENABLE: PIN AF2 TO PIN BB2 (TO ADDER3), PIN AM1 TO PIN AN2 (TO ADDER2) pins: 6 I AF2 AND-NOR INPUT (AL1 ENABLES) TO PIN BB2 (TO ADDER3). pins: 7 I AM1 AND-NOR INPUT (AL1 ENABLES) TO PIN AN2 (TO ADDER2) pins: 8 I AD2 AND-NOR ENABLE: RWB RWB3 TO PIN BB2 (TO ADDER3), RWB2 TO PIN AN2 (TO ADDER2) pins: 9 I AE2 AND-NOR ENABLE: PIN AE1 TO PIN BB2 (TO ADDER3), PIN AM2 TO PIN AN2 (TO ADDER2) pins: 10 I AE1 AND-NOR INPUT (AE2 ENABLES) TO PIN BB2 (TO ADDER3). pins: 11 I AM2 AND-NOR INPUT (AE2 ENABLES) TO PIN AN2 (TO ADDER2) pins: 12 I AC1 AND-NOR INPUT, AND WITH PIN AB2 TO PIN BB2 (TO ADDER3) pins: 13 I AB2 AND-NOR INPUT, AND WITH PIN AC1 TO PIN BB2 (TO ADDER3) pins: 14 I AF1 AND-NOR INPUT (AND WITH ITSELF) TO PIN BB2 (TO ADDER3) pins: 15 I AR2 AND-NOR INPUT, AND WITH PIN AS1 TO PIN AN2 (TO ADDER2) pins: 16 I AS1 AND-NOR INPUT, AND WITH PIN AR2 TO PIN AN2 (TO ADDER2) pins: 17 I AP2 AND-NOR INPUT (AND WITH ITSELF) TO PIN AN2 (TO ADDER2) pins: 18 I BK1 AND-NOR ENABLE: TB3 TO PIN BB1 (TO ADDER3), TB2 TO PIN BN1 (TO ADDER2) pins: 19 I BL1 AND-NOR ENABLE: PIN BE1 TO PIN BB1 (TO ADDER3), PIN BM1 TO PIN BN1 (TO ADDER2) pins: 20 I BE1 AND-NOR INPUT (BL1 ENABLES) TO PIN BB1 (TO ADDER3). pins: 21 I BM1 AND-NOR INPUT (BL1 ENABLES) TO PIN BN1 (TO ADDER2) pins: 22 I BF1 AND-NOR ENABLE: PIN BH1 TO PIN BB1 (TO ADDER3), PIN BR1 TO PIN BN1 (TO ADDER2) pins: 23 I BH1 AND-NOR INPUT (BF1 ENABLES): TO PIN BB1 (TO ADDER3), pins: 24 I BR1 AND-NOR INPUT (BF1 ENABLES): TO PIN BN1 (TO ADDER2) pins: 25 I BS1 AND-NOR ENABLE: PIN BC1 TO PIN BB1 (TO ADDER3), PIN BJ2 TO PIN BN1 (TO ADDER2) pins: 26 I BC1 AND-NOR INPUT (BS1 ENABLES): TO PIN BB1 (TO ADDER3), pins: 27 I BJ2 AND-NOR INPUT (BS1 ENABLES): TO PIN BN1 (TO ADDER2) pins: 28 I BL2 AND-NOR ENABLE: PIN BJ1 TO PIN BB1 (TO ADDER3), PIN BK2 TO PIN BN1 (TO ADDER2) pins: 29 I BJ1 AND-NOR INPUT (BL2 ENABLES): TO PIN BB1 (TO ADDER3), pins: 30 I BK2 AND-NOR INPUT (BL2 ENABLES): TO PIN BN1 (TO ADDER2) pins: 31 I BU1 AND-NOR ENABLE: PIN BH2 TO PIN BB1 (TO ADDER3), PIN BP2 TO PIN BN1 (TO ADDER2) pins: 32 I BH2 AND-NOR INPUT (BU1 ENABLES): TO PIN BB1 (TO ADDER3), pins: 33 I BP2 AND-NOR INPUT (BU1 ENABLES): TO PIN BN1 (TO ADDER2) pins: 34 I BN2 AND-NOR INPUT (AND WITH BM2): TO PIN BN1 (TO ADDER2) pins: 35 I BM2 AND-NOR INPUT (AND WITH BM2): TO PIN BN1 (TO ADDER2) pins: 36 O BB2 AND-NOR OUTPUT, (DRIVES E9-2 7482 A1) TO ADDER3 INPUT pins: 37 O BB1 AND-NOR OUTPUT, (DRIVES E9-3 7482 B1) TO ADDER3 INPUT pins: 38 O BN1 AND-NOR OUTPUT, (DRIVES E9-14 7482 A2) TO ADDER2 INPUT pins: 39 O AN2 AND-NOR OUTPUT, (DRIVES E9-13 7482 B2) TO ADDER2 INPUT pins: 40 O AV2 CARRY OUT-N (E9-10 7482 C2) pins: 41 O BV2 TAPE BUS 2 OUTPUT (INVERTED ADDER2 SUM-N (E9-12 7482 SUM2) pins: 42 O BR2 TAPE BUS 3 OUTPUT (INVERTED ADDER3 SUM-N (E9-1 7482 SUM1) pins: 43 I AK1 LOAD TMA SETUP (FROM TAPE BUS) (RISING EDGE CLOCK) pins: 44 O AR1 TMA SETUP 2 pins: 45 O AH1 TMA SETUP 3 pins: 46 I AU2 LOAD TMA (FROM TAPE BUS) (RISING EDGE CLOCK) pins: 47 O AT2 TMA 2 pins: 48 O AD1 TMA 3 pins: 49 I AJ1 LOAD TBN (FROM TAPE BUS) (RISING EDGE CLOCK) pins: 50 O AU1 TBN 2 pins: 51 O AK2 TBN 3 pins: 52 I AA1 LOAD TAC (FROM TAPE BUS) (RISING EDGE CLOCK) pins: 53 O AN1 TAC 2 pins: 54 O AJ2 TAC 2-N pins: 55 O AH2 TAC 3 pins: 56 O AB1 TAC 3-N pins: 57 I BT2 LOAD TB (FROM TAPE BUS) (RISING EDGE CLOCK) pins: 58 O BP1 TB 2 pins: 59 O BD1 TB 3 pins: 60 I BF2 LOAD RWB (FROM TB) (JAMS CLEAR,SET) pins: 61 I BS2 PHASE (SELECTS POLARITY OF RWB OUT, 0 -> INVERTED) pins: 62 I AV1 RWB IN (SHIFTED INTO RWB 3) pins: 63 I BE2 SHIFT RWB (SHIFTS PIN AV1 INTO RWB 3, SHIFTS RWB3 TO RWB2) (RISING CLOCK) pins: 64 O BV1 RWB OUT (IF PHASE=1, =RWB 2; IF PHASE=0; =RWB 2-N) pins: 65 O BD2 RWB 3 pins: 66 O BU2 +3.5V pins: direction: IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIOOOOOOOIOOIOOIOOIOOOOIOOIIIIOOO comment: ; all registers are unknown comment: ; turn on C0, PHASE comment: ; with no ENABLES, BUS2,BUS3 is 11, C2 is 1 test 1: 1000000000000000000000000000000000011111000XX0XX0XX0XXXX0XX0110XX1 comment: comment: ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; comment: ; comment: ; set all registers LOW comment: ; comment: ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; comment: comment: ; load TMA SETUP from tape bus (00) test 2: 100 test 3: 0 comment: ; load TMA from tape bus (00) test 4: 100 test 5: 0 comment: ; load TBN from tape bus (00) test 6: 100 test 7: 0 comment: ; load TAC from tape bus (00) test 8: 10101 test 9: 0 comment: ; load TB from tape bus (00) test 10: 100 test 11: 0 comment: ; load RWB from TB (JAMS CLEAR AND PRESET) test 12: 1 00 test 13: 0 comment: ; (no change) test 14: 100000000000000000000000000000000001111100000000000001010000110001 comment: comment: comment: ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; comment: ; comment: ; set all registers HIGH comment: ; comment: ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; comment: comment: ; set pin AF1 (AND with itself) to clear pin BB2 (AND-NOR output) and set pin BR2 TAPE BUS 3 OUTPUT test 15: 1 0 1 comment: ; set pin AP2 (AND with itself) to clear pin AN2 (AND-NOR output) and set pin BV2 TAPE BUS 2 OUTPUT test 16: 1 0 1 comment: comment: comment: ; load TMA SETUP from tape bus (11) test 17: 111 test 18: 0 comment: ; load TMA from tape bus (11) test 19: 111 test 20: 0 comment: ; load TBN from tape bus (11) test 21: 111 test 22: 0 comment: ; load TAC from tape bus (11) test 23: 11010 test 24: 0 comment: ; load TB from tape bus (11) test 25: 111 test 26: 0 comment: ; load RWB from TB (JAMS CLEAR AND PRESET) test 27: 1 11 test 28: 0 comment: ; clear pin AF1 (AND with itself) to set pin BB2 (AND-NOR output) and clear pin BR2 TAPE BUS 3 OUTPUT test 29: 0 1 0 comment: ; clear pin AP2 (AND with itself) to set pin AN2 (AND-NOR output) and clear pin BV2 TAPE BUS 2 OUTPUT test 30: 0 1 0 comment: ; (no change) test 31: 100000000000000000000000000000000001111100011011011010100110110111 comment: comment: comment: ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; comment: ; comment: ; test AND-NOR logic comment: ; comment: ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; comment: comment: ; (all registers are HIGH) comment: ; set all pins HIGH except ENABLES comment: comment: ; set pin AF2 HIGH test 32: 1 comment: ; set pin AM1 HIGH test 33: 1 comment: ; set pin AE1 HIGH test 34: 1 comment: ; set pin AM2 HIGH test 35: 1 comment: ; set pin AB2 HIGH test 36: 1 comment: ; set pin AS1 HIGH test 37: 1 comment: ; set pin BE1 HIGH test 38: 1 comment: ; set pin BM1 HIGH test 39: 1 comment: ; set pin BH1 HIGH test 40: 1 comment: ; set pin BR1 HIGH test 41: 1 comment: ; set pin BC1 HIGH test 42: 1 comment: ; set pin BJ2 HIGH test 43: 1 comment: ; set pin BJ1 HIGH test 44: 1 comment: ; set pin BK2 HIGH test 45: 1 comment: ; set pin BH2 HIGH test 46: 1 comment: ; set pin BP2 HIGH test 47: 1 comment: ; set pin BN2 HIGH test 48: 1 comment: ; toggle each ENABLE comment: comment: ; set pin AL2 to clear pin BB2 and pin AN2 AND-NOR OUTPUTS and set TAPE BUS 2 OUTPUT and TAPE BUS 3 OUTPUT test 49: 1 0 0 11 test 50: 0 1 1 00 comment: ; set pin AP1 to clear pin BB2 and pin AN2 AND-NOR OUTPUTS and set TAPE BUS 2 OUTPUT and TAPE BUS 3 OUTPUT test 51: 1 0 0 11 test 52: 0 1 1 00 comment: ; set pin AS2 to clear pin BB2 and pin AN2 AND-NOR OUTPUTS and set TAPE BUS 2 OUTPUT and TAPE BUS 3 OUTPUT test 53: 1 0 0 11 test 54: 0 1 1 00 comment: ; set pin AL1 to clear pin BB2 and pin AN2 AND-NOR OUTPUTS and set TAPE BUS 2 OUTPUT and TAPE BUS 3 OUTPUT test 55: 1 0 0 11 test 56: 0 1 1 00 comment: ; set pin AL1 to clear pin BB2 and pin AN2 AND-NOR OUTPUTS and set TAPE BUS 2 OUTPUT and TAPE BUS 3 OUTPUT test 57: 1 0 0 11 test 58: 0 1 1 00 comment: ; set pin AE2 to clear pin BB2 and pin AN2 AND-NOR OUTPUTS and set TAPE BUS 2 OUTPUT and TAPE BUS 3 OUTPUT test 59: 1 0 0 11 test 60: 0 1 1 00 comment: ; set pin AC1 to clear pin BB2 and set TAPE BUS 3 OUTPUT test 61: 1 0 1 test 62: 0 1 0 comment: ; set pin AF1 to clear pin BB2 and set TAPE BUS 3 OUTPUT test 63: 1 0 1 test 64: 0 1 0 comment: ; set pin AR2 to clear pin AN2 AND-NOR OUTPUTS and set TAPE BUS 2 OUTPUT test 65: 1 0 1 test 66: 0 1 0 comment: ; set pin AP2 to clear pin AN2 AND-NOR OUTPUTS and set TAPE BUS 2 OUTPUT test 67: 1 0 1 test 68: 0 1 0 comment: comment: ; set pin BK1 to clear pin BB1 and pin BN1 AND-NOR OUTPUTS and set TAPE BUS 2 OUTPUT and TAPE BUS 3 OUTPUT test 69: 1 00 11 test 70: 0 11 00 comment: ; set pin BL1 to clear pin BB1 and pin BN1 AND-NOR OUTPUTS and set TAPE BUS 2 OUTPUT and TAPE BUS 3 OUTPUT test 71: 1 00 11 test 72: 0 11 00 comment: ; set pin BF1 to clear pin BB1 and pin BN1 AND-NOR OUTPUTS and set TAPE BUS 2 OUTPUT and TAPE BUS 3 OUTPUT test 73: 1 00 11 test 74: 0 11 00 comment: ; set pin BS1 to clear pin BB1 and pin BN1 AND-NOR OUTPUTS and set TAPE BUS 2 OUTPUT and TAPE BUS 3 OUTPUT test 75: 1 00 11 test 76: 0 11 00 comment: ; set pin BL2 to clear pin BB1 and pin BN1 AND-NOR OUTPUTS and set TAPE BUS 2 OUTPUT and TAPE BUS 3 OUTPUT test 77: 1 00 11 test 78: 0 11 00 comment: ; set pin BU1 to clear pin BB1 and pin BN1 AND-NOR OUTPUTS and set TAPE BUS 2 OUTPUT and TAPE BUS 3 OUTPUT test 79: 1 00 11 test 80: 0 11 00 comment: ; set pin BM2 to clear pin BB1 and TAPE BUS 3 OUTPUT test 81: 1 0 1 test 82: 0 1 0 comment: ; no change test 83: 100000000000000000000000000000000001111100011011011010100110110111 comment: comment: ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; comment: ; test shifting the RWB comment: ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; comment: comment: test 84: 61 I BS2 PHASE (SELECTS POLARITY OF RWB OUT, 0 -> INVERTED) error: unexpect character: 0x36 6 error: expected '0', '1', or 'X' for test step test 85: 62 I AV1 RWB IN (SHIFTED INTO RWB 3) error: unexpect character: 0x36 6 error: expected '0', '1', or 'X' for test step test 86: 63 I BE2 SHIFT RWB (SHIFTS PIN AV1 INTO RWB 3, SHIFTS RWB3 TO RWB2) (RISING CLOCK) 'test step' is too long expected 'test step' (66 columns of '0','1','X', or ' ') bad test file Main menu Thu Aug 20 16:35:22 2015 test file is: delay is: 0 trigger is: 1 1 read test file 2 set test delay 3 set test trigger 4 run test 5 output loading test 8 diags 9 exit Enter test file name? trying to open test file: tests\m222.new reading test file: tests\m222.new comment: M222 PCB REV B SCHEMATIC REV A LINC TAPE REGISTERS comment: comment: TERMINOLOGY- SIGNALS REFER TO VOL4 M222 SCHEMATIC. comment: comment: BUT... comment: comment: DEC USES AND-NOR GATES TO ROUTE THE ADDER A AND B INPUTS, SO... comment: DEC RENAMED THE ADDER TO NEGATIVE LOGIC TERMS (I.E. A-N + B-N + C-N -> SUM-N, C1-N). comment: (NOT THE 7482 DATASHEET NAMES OF A + B + C -> SUM, C1). comment: comment: SO, WITH ALL 'AND ENABLES' LOW, THE AND-NOR OUTPUTS = HIGH. comment: WITH C-L HIGH, THE ADDER OUTPUT IS SUM-N=1, C1-N=1; comment: THE INVERTED ADDER OUTPUT IS LOW (TAPE BUS). comment: AND THERE IS NO CARRY (C1-N IS HI). comment: comment: THE TWO ADDERS, TWO REGISTER BITS, ETC ARE LABELED BIT 2 (EVEN, MSB) AND BIT 3 (ODD, LSB). comment: THE ADDERS ARE REFERRED TO AS 'ADDER2' (MSB) AND 'ADDER3' (LSB). comment: comment: POWER PINS: comment: AA2 +5V comment: AT1 GROUND comment: AC2 GROUND comment: BA2 +5V comment: BT1 GROUND comment: BC2 GROUND comment: comment: (ALL PINS ARE USED). comment: comment: pins: PINS pins: 1 I BA1 CARRY IN-N, (TO E9-5 7482 C0) C-N TO ADDER2 pins: 2 I AL2 AND-NOR ENABLE: TAC TAC3 TO PIN BB2 (TO ADDER3) TAC2 TO PIN AN2 (TO ADDER2) pins: 3 I AP1 AND-NOR ENABLE: TMA SETUP (TMAS)3 TO PIN BB2 (TO ADDER3), (TMAS)3 TO PIN AN2 (TO ADDER2) pins: 4 I AS2 AND-NOR ENABLE: TMA TMA3 TO PIN BB2 (TO ADDER3), TMA2 TO PIN AN2 (TO ADDER2) pins: 5 I AL1 AND-NOR ENABLE: PIN AF2 TO PIN BB2 (TO ADDER3), PIN AM1 TO PIN AN2 (TO ADDER2) pins: 6 I AF2 AND-NOR INPUT (AL1 ENABLES) TO PIN BB2 (TO ADDER3). pins: 7 I AM1 AND-NOR INPUT (AL1 ENABLES) TO PIN AN2 (TO ADDER2) pins: 8 I AD2 AND-NOR ENABLE: RWB RWB3 TO PIN BB2 (TO ADDER3), RWB2 TO PIN AN2 (TO ADDER2) pins: 9 I AE2 AND-NOR ENABLE: PIN AE1 TO PIN BB2 (TO ADDER3), PIN AM2 TO PIN AN2 (TO ADDER2) pins: 10 I AE1 AND-NOR INPUT (AE2 ENABLES) TO PIN BB2 (TO ADDER3). pins: 11 I AM2 AND-NOR INPUT (AE2 ENABLES) TO PIN AN2 (TO ADDER2) pins: 12 I AC1 AND-NOR INPUT, AND WITH PIN AB2 TO PIN BB2 (TO ADDER3) pins: 13 I AB2 AND-NOR INPUT, AND WITH PIN AC1 TO PIN BB2 (TO ADDER3) pins: 14 I AF1 AND-NOR INPUT (AND WITH ITSELF) TO PIN BB2 (TO ADDER3) pins: 15 I AR2 AND-NOR INPUT, AND WITH PIN AS1 TO PIN AN2 (TO ADDER2) pins: 16 I AS1 AND-NOR INPUT, AND WITH PIN AR2 TO PIN AN2 (TO ADDER2) pins: 17 I AP2 AND-NOR INPUT (AND WITH ITSELF) TO PIN AN2 (TO ADDER2) pins: 18 I BK1 AND-NOR ENABLE: TB3 TO PIN BB1 (TO ADDER3), TB2 TO PIN BN1 (TO ADDER2) pins: 19 I BL1 AND-NOR ENABLE: PIN BE1 TO PIN BB1 (TO ADDER3), PIN BM1 TO PIN BN1 (TO ADDER2) pins: 20 I BE1 AND-NOR INPUT (BL1 ENABLES) TO PIN BB1 (TO ADDER3). pins: 21 I BM1 AND-NOR INPUT (BL1 ENABLES) TO PIN BN1 (TO ADDER2) pins: 22 I BF1 AND-NOR ENABLE: PIN BH1 TO PIN BB1 (TO ADDER3), PIN BR1 TO PIN BN1 (TO ADDER2) pins: 23 I BH1 AND-NOR INPUT (BF1 ENABLES): TO PIN BB1 (TO ADDER3), pins: 24 I BR1 AND-NOR INPUT (BF1 ENABLES): TO PIN BN1 (TO ADDER2) pins: 25 I BS1 AND-NOR ENABLE: PIN BC1 TO PIN BB1 (TO ADDER3), PIN BJ2 TO PIN BN1 (TO ADDER2) pins: 26 I BC1 AND-NOR INPUT (BS1 ENABLES): TO PIN BB1 (TO ADDER3), pins: 27 I BJ2 AND-NOR INPUT (BS1 ENABLES): TO PIN BN1 (TO ADDER2) pins: 28 I BL2 AND-NOR ENABLE: PIN BJ1 TO PIN BB1 (TO ADDER3), PIN BK2 TO PIN BN1 (TO ADDER2) pins: 29 I BJ1 AND-NOR INPUT (BL2 ENABLES): TO PIN BB1 (TO ADDER3), pins: 30 I BK2 AND-NOR INPUT (BL2 ENABLES): TO PIN BN1 (TO ADDER2) pins: 31 I BU1 AND-NOR ENABLE: PIN BH2 TO PIN BB1 (TO ADDER3), PIN BP2 TO PIN BN1 (TO ADDER2) pins: 32 I BH2 AND-NOR INPUT (BU1 ENABLES): TO PIN BB1 (TO ADDER3), pins: 33 I BP2 AND-NOR INPUT (BU1 ENABLES): TO PIN BN1 (TO ADDER2) pins: 34 I BN2 AND-NOR INPUT (AND WITH BM2): TO PIN BN1 (TO ADDER2) pins: 35 I BM2 AND-NOR INPUT (AND WITH BM2): TO PIN BN1 (TO ADDER2) pins: 36 O BB2 AND-NOR OUTPUT, (DRIVES E9-2 7482 A1) TO ADDER3 INPUT pins: 37 O BB1 AND-NOR OUTPUT, (DRIVES E9-3 7482 B1) TO ADDER3 INPUT pins: 38 O BN1 AND-NOR OUTPUT, (DRIVES E9-14 7482 A2) TO ADDER2 INPUT pins: 39 O AN2 AND-NOR OUTPUT, (DRIVES E9-13 7482 B2) TO ADDER2 INPUT pins: 40 O AV2 CARRY OUT-N (E9-10 7482 C2) pins: 41 O BV2 TAPE BUS 2 OUTPUT (INVERTED ADDER2 SUM-N (E9-12 7482 SUM2) pins: 42 O BR2 TAPE BUS 3 OUTPUT (INVERTED ADDER3 SUM-N (E9-1 7482 SUM1) pins: 43 I AK1 LOAD TMA SETUP (FROM TAPE BUS) (RISING EDGE CLOCK) pins: 44 O AR1 TMA SETUP 2 pins: 45 O AH1 TMA SETUP 3 pins: 46 I AU2 LOAD TMA (FROM TAPE BUS) (RISING EDGE CLOCK) pins: 47 O AT2 TMA 2 pins: 48 O AD1 TMA 3 pins: 49 I AJ1 LOAD TBN (FROM TAPE BUS) (RISING EDGE CLOCK) pins: 50 O AU1 TBN 2 pins: 51 O AK2 TBN 3 pins: 52 I AA1 LOAD TAC (FROM TAPE BUS) (RISING EDGE CLOCK) pins: 53 O AN1 TAC 2 pins: 54 O AJ2 TAC 2-N pins: 55 O AH2 TAC 3 pins: 56 O AB1 TAC 3-N pins: 57 I BT2 LOAD TB (FROM TAPE BUS) (RISING EDGE CLOCK) pins: 58 O BP1 TB 2 pins: 59 O BD1 TB 3 pins: 60 I BF2 LOAD RWB (FROM TB) (JAMS CLEAR,SET) pins: 61 I BS2 PHASE (SELECTS POLARITY OF RWB OUT, 0 -> INVERTED) pins: 62 I AV1 RWB IN (SHIFTED INTO RWB 3) pins: 63 I BE2 SHIFT RWB (SHIFTS PIN AV1 INTO RWB 3, SHIFTS RWB3 TO RWB2) (RISING CLOCK) pins: 64 O BV1 RWB OUT (IF PHASE=1, =RWB 2; IF PHASE=0; =RWB 2-N) pins: 65 O BD2 RWB 3 pins: 66 O BU2 +3.5V pins: direction: IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIOOOOOOOIOOIOOIOOIOOOOIOOIIIIOOO comment: ; all registers are unknown comment: ; turn on C0, PHASE comment: ; with no ENABLES, BUS2,BUS3 is 11, C2 is 1 test 1: 1000000000000000000000000000000000011111000XX0XX0XX0XXXX0XX0110XX1 comment: comment: ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; comment: ; comment: ; set all registers LOW comment: ; comment: ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; comment: comment: ; load TMA SETUP from tape bus (00) test 2: 100 test 3: 0 comment: ; load TMA from tape bus (00) test 4: 100 test 5: 0 comment: ; load TBN from tape bus (00) test 6: 100 test 7: 0 comment: ; load TAC from tape bus (00) test 8: 10101 test 9: 0 comment: ; load TB from tape bus (00) test 10: 100 test 11: 0 comment: ; load RWB from TB (JAMS CLEAR AND PRESET) test 12: 1 00 test 13: 0 comment: ; (no change) test 14: 100000000000000000000000000000000001111100000000000001010000110001 comment: comment: comment: ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; comment: ; comment: ; set all registers HIGH comment: ; comment: ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; comment: comment: ; set pin AF1 (AND with itself) to clear pin BB2 (AND-NOR output) and set pin BR2 TAPE BUS 3 OUTPUT test 15: 1 0 1 comment: ; set pin AP2 (AND with itself) to clear pin AN2 (AND-NOR output) and set pin BV2 TAPE BUS 2 OUTPUT test 16: 1 0 1 comment: comment: comment: ; load TMA SETUP from tape bus (11) test 17: 111 test 18: 0 comment: ; load TMA from tape bus (11) test 19: 111 test 20: 0 comment: ; load TBN from tape bus (11) test 21: 111 test 22: 0 comment: ; load TAC from tape bus (11) test 23: 11010 test 24: 0 comment: ; load TB from tape bus (11) test 25: 111 test 26: 0 comment: ; load RWB from TB (JAMS CLEAR AND PRESET) test 27: 1 11 test 28: 0 comment: ; clear pin AF1 (AND with itself) to set pin BB2 (AND-NOR output) and clear pin BR2 TAPE BUS 3 OUTPUT test 29: 0 1 0 comment: ; clear pin AP2 (AND with itself) to set pin AN2 (AND-NOR output) and clear pin BV2 TAPE BUS 2 OUTPUT test 30: 0 1 0 comment: ; (no change) test 31: 100000000000000000000000000000000001111100011011011010100110110111 comment: comment: comment: ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; comment: ; comment: ; test AND-NOR logic comment: ; comment: ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; comment: comment: ; (all registers are HIGH) comment: ; set all pins HIGH except ENABLES comment: comment: ; set pin AF2 HIGH test 32: 1 comment: ; set pin AM1 HIGH test 33: 1 comment: ; set pin AE1 HIGH test 34: 1 comment: ; set pin AM2 HIGH test 35: 1 comment: ; set pin AB2 HIGH test 36: 1 comment: ; set pin AS1 HIGH test 37: 1 comment: ; set pin BE1 HIGH test 38: 1 comment: ; set pin BM1 HIGH test 39: 1 comment: ; set pin BH1 HIGH test 40: 1 comment: ; set pin BR1 HIGH test 41: 1 comment: ; set pin BC1 HIGH test 42: 1 comment: ; set pin BJ2 HIGH test 43: 1 comment: ; set pin BJ1 HIGH test 44: 1 comment: ; set pin BK2 HIGH test 45: 1 comment: ; set pin BH2 HIGH test 46: 1 comment: ; set pin BP2 HIGH test 47: 1 comment: ; set pin BN2 HIGH test 48: 1 comment: ; toggle each ENABLE comment: comment: ; set pin AL2 to clear pin BB2 and pin AN2 AND-NOR OUTPUTS and set TAPE BUS 2 OUTPUT and TAPE BUS 3 OUTPUT test 49: 1 0 0 11 test 50: 0 1 1 00 comment: ; set pin AP1 to clear pin BB2 and pin AN2 AND-NOR OUTPUTS and set TAPE BUS 2 OUTPUT and TAPE BUS 3 OUTPUT test 51: 1 0 0 11 test 52: 0 1 1 00 comment: ; set pin AS2 to clear pin BB2 and pin AN2 AND-NOR OUTPUTS and set TAPE BUS 2 OUTPUT and TAPE BUS 3 OUTPUT test 53: 1 0 0 11 test 54: 0 1 1 00 comment: ; set pin AL1 to clear pin BB2 and pin AN2 AND-NOR OUTPUTS and set TAPE BUS 2 OUTPUT and TAPE BUS 3 OUTPUT test 55: 1 0 0 11 test 56: 0 1 1 00 comment: ; set pin AL1 to clear pin BB2 and pin AN2 AND-NOR OUTPUTS and set TAPE BUS 2 OUTPUT and TAPE BUS 3 OUTPUT test 57: 1 0 0 11 test 58: 0 1 1 00 comment: ; set pin AE2 to clear pin BB2 and pin AN2 AND-NOR OUTPUTS and set TAPE BUS 2 OUTPUT and TAPE BUS 3 OUTPUT test 59: 1 0 0 11 test 60: 0 1 1 00 comment: ; set pin AC1 to clear pin BB2 and set TAPE BUS 3 OUTPUT test 61: 1 0 1 test 62: 0 1 0 comment: ; set pin AF1 to clear pin BB2 and set TAPE BUS 3 OUTPUT test 63: 1 0 1 test 64: 0 1 0 comment: ; set pin AR2 to clear pin AN2 AND-NOR OUTPUTS and set TAPE BUS 2 OUTPUT test 65: 1 0 1 test 66: 0 1 0 comment: ; set pin AP2 to clear pin AN2 AND-NOR OUTPUTS and set TAPE BUS 2 OUTPUT test 67: 1 0 1 test 68: 0 1 0 comment: comment: ; set pin BK1 to clear pin BB1 and pin BN1 AND-NOR OUTPUTS and set TAPE BUS 2 OUTPUT and TAPE BUS 3 OUTPUT test 69: 1 00 11 test 70: 0 11 00 comment: ; set pin BL1 to clear pin BB1 and pin BN1 AND-NOR OUTPUTS and set TAPE BUS 2 OUTPUT and TAPE BUS 3 OUTPUT test 71: 1 00 11 test 72: 0 11 00 comment: ; set pin BF1 to clear pin BB1 and pin BN1 AND-NOR OUTPUTS and set TAPE BUS 2 OUTPUT and TAPE BUS 3 OUTPUT test 73: 1 00 11 test 74: 0 11 00 comment: ; set pin BS1 to clear pin BB1 and pin BN1 AND-NOR OUTPUTS and set TAPE BUS 2 OUTPUT and TAPE BUS 3 OUTPUT test 75: 1 00 11 test 76: 0 11 00 comment: ; set pin BL2 to clear pin BB1 and pin BN1 AND-NOR OUTPUTS and set TAPE BUS 2 OUTPUT and TAPE BUS 3 OUTPUT test 77: 1 00 11 test 78: 0 11 00 comment: ; set pin BU1 to clear pin BB1 and pin BN1 AND-NOR OUTPUTS and set TAPE BUS 2 OUTPUT and TAPE BUS 3 OUTPUT test 79: 1 00 11 test 80: 0 11 00 comment: ; set pin BM2 to clear pin BB1 and TAPE BUS 3 OUTPUT test 81: 1 0 1 test 82: 0 1 0 comment: ; no change test 83: 100000000000000000000000000000000001111100011011011010100110110111 comment: comment: ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; comment: ; test shifting the RWB comment: ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; comment: comment: ; shift in 0, expect 10 test 84: 0 test 85: 110 test 86: 0 comment: ; toggle phase should toggle RWB 2 test 87: 0 0 test 88: 1 1 comment: comment: ; shift in 0, expect 00 test 89: 0 test 90: 100 test 91: 0 comment: ; toggle phase should toggle RWB 2 test 92: 0 1 test 93: 1 0 comment: comment: ; shift in 0, expect 00 test 94: 0 test 95: 100 test 96: 0 comment: ; shift in 1, expect 01 test 97: 1 test 98: 101 test 99: 0 comment: ; shift in 1, expect 11 test 100: 1 test 101: 111 test 102: 0 comment: ; shift in 1, expect 11 test 103: 1 test 104: 111 test 105: 0 comment: ; shift in 0, expect 10 test 106: 0 test 107: 110 test 108: 0 comment: ; shift in 1, expect 01 test 109: 1 test 110: 101 test 111: 0 comment: ; shift in 0, expect 10 test 112: 0 test 113: 110 test 114: 0 comment: ; shift in 1, expect 01 test 115: 0 test 116: 101 test 117: 0 comment: ; shift in 1, expect 10 test 118: 1 test 119: 110 test 120: 0 comment: ; shift in 1, expect 11 test 121: 1 test 122: 111 test 123: 0 comment: ; no change test 124: 100000000000000000000000000000000001111100011011011010100110110111 comment: comment: ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; comment: ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; comment: ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; comment: ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; comment: ; needs work (more adder tests, more register tests) comment: ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; comment: ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; comment: ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; comment: ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; end: END summary column 1: offset 2, mask 0x2000 column 2: offset 1, mask 0x0002 column 3: offset 1, mask 0x0800 column 4: offset 1, mask 0x0040 column 5: offset 1, mask 0x4000 column 6: offset 0, mask 0x0004 column 7: offset 1, mask 0x2000 column 8: offset 0, mask 0x0010 column 9: offset 0, mask 0x0008 column 10: offset 0, mask 0x0800 column 11: offset 1, mask 0x0004 column 12: offset 0, mask 0x2000 column 13: offset 0, mask 0x0040 column 14: offset 0, mask 0x0400 column 15: offset 1, mask 0x0020 column 16: offset 1, mask 0x0200 column 17: offset 1, mask 0x0010 column 18: offset 3, mask 0x2000 column 19: offset 3, mask 0x1000 column 20: offset 2, mask 0x0200 column 21: offset 3, mask 0x0800 column 22: offset 2, mask 0x0100 column 23: offset 3, mask 0x8000 column 24: offset 3, mask 0x0100 column 25: offset 4, mask 0x8000 column 26: offset 2, mask 0x0800 column 27: offset 3, mask 0x0002 column 28: offset 3, mask 0x0008 column 29: offset 3, mask 0x4000 column 30: offset 3, mask 0x0004 column 31: offset 4, mask 0x2000 column 32: offset 3, mask 0x0001 column 33: offset 3, mask 0x0040 column 34: offset 3, mask 0x0020 column 35: offset 3, mask 0x0010 column 36: offset 2, mask 0x0008 column 37: offset 2, mask 0x1000 column 38: offset 3, mask 0x0400 column 39: offset 1, mask 0x0008 column 40: offset 2, mask 0x0002 column 41: offset 4, mask 0x0008 column 42: offset 3, mask 0x0080 column 43: offset 1, mask 0x8000 column 44: offset 1, mask 0x0400 column 45: offset 0, mask 0x0200 column 46: offset 2, mask 0x0001 column 47: offset 1, mask 0x0080 column 48: offset 0, mask 0x1000 column 49: offset 0, mask 0x0100 column 50: offset 2, mask 0x8000 column 51: offset 1, mask 0x0001 column 52: offset 0, mask 0x8000 column 53: offset 1, mask 0x1000 column 54: offset 0, mask 0x0001 column 55: offset 0, mask 0x0002 column 56: offset 0, mask 0x4000 column 57: offset 4, mask 0x0002 column 58: offset 3, mask 0x0200 column 59: offset 2, mask 0x0400 column 60: offset 2, mask 0x0080 column 61: offset 4, mask 0x0001 column 62: offset 2, mask 0x4000 column 63: offset 2, mask 0x0040 column 64: offset 4, mask 0x1000 column 65: offset 2, mask 0x0020 column 66: offset 4, mask 0x0004 direction bits (1=input) 0x52A3 0x1589 0x943A 0x0680 0x50FC pullup bits (1=pullup) 0x0000 0x0000 0x0000 0x0000 0x0000 test step out_data dont care 1: 0x0000 0x0008 0x700A 0x0400 0x0005 0x5203 0x1481 0x8420 0x0200 0x1000 2: 0x0000 0x8008 0x700A 0x0400 0x0005 0x5003 0x1081 0x8420 0x0200 0x1000 3: 0x0000 0x0008 0x700A 0x0400 0x0005 0x5003 0x1081 0x8420 0x0200 0x1000 4: 0x0000 0x0008 0x700B 0x0400 0x0005 0x4003 0x1001 0x8420 0x0200 0x1000 5: 0x0000 0x0008 0x700A 0x0400 0x0005 0x4003 0x1001 0x8420 0x0200 0x1000 6: 0x0100 0x0008 0x700A 0x0400 0x0005 0x4003 0x1000 0x0420 0x0200 0x1000 7: 0x0000 0x0008 0x700A 0x0400 0x0005 0x4003 0x1000 0x0420 0x0200 0x1000 8: 0xC001 0x0008 0x700A 0x0400 0x0005 0x0000 0x0000 0x0420 0x0200 0x1000 9: 0x4001 0x0008 0x700A 0x0400 0x0005 0x0000 0x0000 0x0420 0x0200 0x1000 10: 0x4001 0x0008 0x700A 0x0400 0x0007 0x0000 0x0000 0x0020 0x0000 0x1000 11: 0x4001 0x0008 0x700A 0x0400 0x0005 0x0000 0x0000 0x0020 0x0000 0x1000 12: 0x4001 0x0008 0x708A 0x0400 0x0005 13: 0x4001 0x0008 0x700A 0x0400 0x0005 14: 0x4001 0x0008 0x700A 0x0400 0x0005 15: 0x4401 0x0008 0x7002 0x0480 0x0005 16: 0x4401 0x0010 0x7002 0x0480 0x000D 17: 0x4601 0x8410 0x7002 0x0480 0x000D 18: 0x4601 0x0410 0x7002 0x0480 0x000D 19: 0x5601 0x0490 0x7003 0x0480 0x000D 20: 0x5601 0x0490 0x7002 0x0480 0x000D 21: 0x5701 0x0491 0xF002 0x0480 0x000D 22: 0x5601 0x0491 0xF002 0x0480 0x000D 23: 0x9602 0x1491 0xF002 0x0480 0x000D 24: 0x1602 0x1491 0xF002 0x0480 0x000D 25: 0x1602 0x1491 0xF402 0x0680 0x000F 26: 0x1602 0x1491 0xF402 0x0680 0x000D 27: 0x1602 0x1491 0xF4A2 0x0680 0x100D 28: 0x1602 0x1491 0xF422 0x0680 0x100D 29: 0x1202 0x1491 0xF42A 0x0600 0x100D 30: 0x1202 0x1489 0xF42A 0x0600 0x1005 31: 0x1202 0x1489 0xF42A 0x0600 0x1005 32: 0x1206 0x1489 0xF42A 0x0600 0x1005 33: 0x1206 0x3489 0xF42A 0x0600 0x1005 34: 0x1A06 0x3489 0xF42A 0x0600 0x1005 35: 0x1A06 0x348D 0xF42A 0x0600 0x1005 36: 0x1A46 0x348D 0xF42A 0x0600 0x1005 37: 0x1A46 0x368D 0xF42A 0x0600 0x1005 38: 0x1A46 0x368D 0xF62A 0x0600 0x1005 39: 0x1A46 0x368D 0xF62A 0x0E00 0x1005 40: 0x1A46 0x368D 0xF62A 0x8E00 0x1005 41: 0x1A46 0x368D 0xF62A 0x8F00 0x1005 42: 0x1A46 0x368D 0xFE2A 0x8F00 0x1005 43: 0x1A46 0x368D 0xFE2A 0x8F02 0x1005 44: 0x1A46 0x368D 0xFE2A 0xCF02 0x1005 45: 0x1A46 0x368D 0xFE2A 0xCF06 0x1005 46: 0x1A46 0x368D 0xFE2A 0xCF07 0x1005 47: 0x1A46 0x368D 0xFE2A 0xCF47 0x1005 48: 0x1A46 0x368D 0xFE2A 0xCF67 0x1005 49: 0x1A46 0x3687 0xFE22 0xCFE7 0x100D 50: 0x1A46 0x368D 0xFE2A 0xCF67 0x1005 51: 0x1A46 0x3E85 0xFE22 0xCFE7 0x100D 52: 0x1A46 0x368D 0xFE2A 0xCF67 0x1005 53: 0x1A46 0x36C5 0xFE22 0xCFE7 0x100D 54: 0x1A46 0x368D 0xFE2A 0xCF67 0x1005 55: 0x1A46 0x7685 0xFE22 0xCFE7 0x100D 56: 0x1A46 0x368D 0xFE2A 0xCF67 0x1005 57: 0x1A56 0x3685 0xFE22 0xCFE7 0x100D 58: 0x1A46 0x368D 0xFE2A 0xCF67 0x1005 59: 0x1A4E 0x3685 0xFE22 0xCFE7 0x100D 60: 0x1A46 0x368D 0xFE2A 0xCF67 0x1005 61: 0x3A46 0x368D 0xFE22 0xCFE7 0x1005 62: 0x1A46 0x368D 0xFE2A 0xCF67 0x1005 63: 0x1E46 0x368D 0xFE22 0xCFE7 0x1005 64: 0x1A46 0x368D 0xFE2A 0xCF67 0x1005 65: 0x1A46 0x36A5 0xFE2A 0xCF67 0x100D 66: 0x1A46 0x368D 0xFE2A 0xCF67 0x1005 67: 0x1A46 0x3695 0xFE2A 0xCF67 0x100D 68: 0x1A46 0x368D 0xFE2A 0xCF67 0x1005 69: 0x1A46 0x368D 0xEE2A 0xEBE7 0x100D 70: 0x1A46 0x368D 0xFE2A 0xCF67 0x1005 71: 0x1A46 0x368D 0xEE2A 0xDBE7 0x100D 72: 0x1A46 0x368D 0xFE2A 0xCF67 0x1005 73: 0x1A46 0x368D 0xEF2A 0xCBE7 0x100D 74: 0x1A46 0x368D 0xFE2A 0xCF67 0x1005 75: 0x1A46 0x368D 0xEE2A 0xCBE7 0x900D 76: 0x1A46 0x368D 0xFE2A 0xCF67 0x1005 77: 0x1A46 0x368D 0xEE2A 0xCBEF 0x100D 78: 0x1A46 0x368D 0xFE2A 0xCF67 0x1005 79: 0x1A46 0x368D 0xEE2A 0xCBE7 0x300D 80: 0x1A46 0x368D 0xFE2A 0xCF67 0x1005 81: 0x1A46 0x368D 0xFE2A 0xCB77 0x100D 82: 0x1A46 0x368D 0xFE2A 0xCF67 0x1005 83: 0x1202 0x1489 0xF42A 0x0600 0x1005 84: 0x1202 0x1489 0xB42A 0x0600 0x1005 85: 0x1202 0x1489 0xB44A 0x0600 0x1005 86: 0x1202 0x1489 0xB40A 0x0600 0x1005 87: 0x1202 0x1489 0xB40A 0x0600 0x0004 88: 0x1202 0x1489 0xB40A 0x0600 0x1005 89: 0x1202 0x1489 0xB40A 0x0600 0x1005 90: 0x1202 0x1489 0xB44A 0x0600 0x0005 91: 0x1202 0x1489 0xB40A 0x0600 0x0005 92: 0x1202 0x1489 0xB40A 0x0600 0x1004 93: 0x1202 0x1489 0xB40A 0x0600 0x0005 94: 0x1202 0x1489 0xB40A 0x0600 0x0005 95: 0x1202 0x1489 0xB44A 0x0600 0x0005 96: 0x1202 0x1489 0xB40A 0x0600 0x0005 97: 0x1202 0x1489 0xF40A 0x0600 0x0005 98: 0x1202 0x1489 0xF46A 0x0600 0x0005 99: 0x1202 0x1489 0xF42A 0x0600 0x0005 100: 0x1202 0x1489 0xF42A 0x0600 0x0005 101: 0x1202 0x1489 0xF46A 0x0600 0x1005 102: 0x1202 0x1489 0xF42A 0x0600 0x1005 103: 0x1202 0x1489 0xF42A 0x0600 0x1005 104: 0x1202 0x1489 0xF46A 0x0600 0x1005 105: 0x1202 0x1489 0xF42A 0x0600 0x1005 106: 0x1202 0x1489 0xB42A 0x0600 0x1005 107: 0x1202 0x1489 0xB44A 0x0600 0x1005 108: 0x1202 0x1489 0xB40A 0x0600 0x1005 109: 0x1202 0x1489 0xF40A 0x0600 0x1005 110: 0x1202 0x1489 0xF46A 0x0600 0x0005 111: 0x1202 0x1489 0xF42A 0x0600 0x0005 112: 0x1202 0x1489 0xB42A 0x0600 0x0005 113: 0x1202 0x1489 0xB44A 0x0600 0x1005 114: 0x1202 0x1489 0xB40A 0x0600 0x1005 115: 0x1202 0x1489 0xB40A 0x0600 0x1005 116: 0x1202 0x1489 0xB46A 0x0600 0x0005 117: 0x1202 0x1489 0xB42A 0x0600 0x0005 118: 0x1202 0x1489 0xF42A 0x0600 0x0005 119: 0x1202 0x1489 0xF44A 0x0600 0x1005 120: 0x1202 0x1489 0xF40A 0x0600 0x1005 121: 0x1202 0x1489 0xF40A 0x0600 0x1005 122: 0x1202 0x1489 0xF46A 0x0600 0x1005 123: 0x1202 0x1489 0xF42A 0x0600 0x1005 124: 0x1202 0x1489 0xF42A 0x0600 0x1005 PINs used (in edge connector order) (G=ground,P=power) SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBB LETTER ABCDEFHJKLMNPRSTUVABCDEFHJKLMNPRSTUVABCDEFHJKLMNPRSTUVABCDEFHJKLMNPRSTUV SIDE 111111111111111111222222222222222222111111111111111111222222222222222222 USAGE IOIOIIOIIIIOIOIGOIPIGIIIOOOIIOIIIOIOIOIOIIIIIIIOOIIGIOPOGOIIIIIIIIIOIIOO UUT has 44 inputs UUT has 22 outputs contains 66 pins/columns 0 pins are not used contains 124 'test steps' M222 PCB REV B SCHEMATIC REV A LINC TAPE REGISTERS TERMINOLOGY- SIGNALS REFER TO VOL4 M222 SCHEMATIC. BUT... DEC USES AND-NOR GATES TO ROUTE THE ADDER A AND B INPUTS, SO... DEC RENAMED THE ADDER TO NEGATIVE LOGIC TERMS (I.E. A-N + B-N + C-N -> SUM-N, C1-N). (NOT THE 7482 DATASHEET NAMES OF A + B + C -> SUM, C1). SO, WITH ALL 'AND ENABLES' LOW, THE AND-NOR OUTPUTS = HIGH. WITH C-L HIGH, THE ADDER OUTPUT IS SUM-N=1, C1-N=1; THE INVERTED ADDER OUTPUT IS LOW (TAPE BUS). AND THERE IS NO CARRY (C1-N IS HI). THE TWO ADDERS, TWO REGISTER BITS, ETC ARE LABELED BIT 2 (EVEN, MSB) AND BIT 3 (ODD, LSB). THE ADDERS ARE REFERRED TO AS 'ADDER2' (MSB) AND 'ADDER3' (LSB). POWER PINS: AA2 +5V AT1 GROUND AC2 GROUND BA2 +5V BT1 GROUND BC2 GROUND (ALL PINS ARE USED). PINS Main menu Thu Aug 20 16:36:02 2015 test file is: tests\m222.new delay is: 0 trigger is: 1 1 read test file 2 set test delay 3 set test trigger 4 run test 5 output loading test 8 diags 9 exit UUT power is okay Thu Aug 20 16:36:07 2015 space single step O run once (one test, all steps) F run, stop on fail G go (run tests N run, stop on fail, no print S scope (run, no print) C toggle comment printout + increase speed (less delay) - decrease speed (more delay)(slower) Q quit test scope (run, no print) FFFFFFFFFFFFFFFFFFFFFFFFFFFFF space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C toggle comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C toggle comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit step 106 100000000000000000000000000000000001111100011011011010100110100111 step 107 100000000000000000000000000000000001111100011011011010100110101101 step 108 100000000000000000000000000000000001111100011011011010100110100101 step 109 100000000000000000000000000000000001111100011011011010100110110101 step 110 100000000000000000000000000000000001111100011011011010100110111011 step 111 100000000000000000000000000000000001111100011011011010100110110011 step 112 100000000000000000000000000000000001111100011011011010100110100011 step 113 100000000000000000000000000000000001111100011011011010100110101101 step 114 100000000000000000000000000000000001111100011011011010100110100101 step 115 100000000000000000000000000000000001111100011011011010100110100101 SLOT BAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBAABBAAAAAAAAAAAAAABBBBBABBBB LETTER ALPSLFMDEEMCBFRSPKLEMFHRSCJLJKUHPNMBBNNVVRKRHUTDJUKANJHBTPDFSVEVDU SIDE 121212122121212121111111112212122222112222111221112112212112212122 DIRECTION IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIOOOOOOOIOOIOOIOOIOOOOIOOIIIIOOO changed: 10 step 116 100000000000000000000000000000000001111100011011011010100110101001 fail ^ SLOT BAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBAABBAAAAAAAAAAAAAABBBBBABBBB LETTER ALPSLFMDEEMCBFRSPKLEMFHRSCJLJKUHPNMBBNNVVRKRHUTDJUKANJHBTPDFSVEVDU SIDE 121212122121212121111111112212122222112222111221112112212112212122 DIRECTION IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIOOOOOOOIOOIOOIOOIOOOOIOOIIIIOOO changed: 0 step 117 100000000000000000000000000000000001111100011011011010100110100001 fail ^ SLOT BAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBAABBAAAAAAAAAAAAAABBBBBABBBB LETTER ALPSLFMDEEMCBFRSPKLEMFHRSCJLJKUHPNMBBNNVVRKRHUTDJUKANJHBTPDFSVEVDU SIDE 121212122121212121111111112212122222112222111221112112212112212122 DIRECTION IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIOOOOOOOIOOIOOIOOIOOOOIOOIIIIOOO changed: 1 step 118 100000000000000000000000000000000001111100011011011010100110110001 fail ^ SLOT BAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBAABBAAAAAAAAAAAAAABBBBBABBBB LETTER ALPSLFMDEEMCBFRSPKLEMFHRSCJLJKUHPNMBBNNVVRKRHUTDJUKANJHBTPDFSVEVDU SIDE 121212122121212121111111112212122222112222111221112112212112212122 DIRECTION IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIOOOOOOOIOOIOOIOOIOOOOIOOIIIIOOO changed: 1 1 step 119 100000000000000000000000000000000001111100011011011010100110111011 fail ^^ SLOT BAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBAABBAAAAAAAAAAAAAABBBBBABBBB LETTER ALPSLFMDEEMCBFRSPKLEMFHRSCJLJKUHPNMBBNNVVRKRHUTDJUKANJHBTPDFSVEVDU SIDE 121212122121212121111111112212122222112222111221112112212112212122 DIRECTION IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIOOOOOOOIOOIOOIOOIOOOOIOOIIIIOOO changed: 0 step 120 100000000000000000000000000000000001111100011011011010100110110011 fail ^^ SLOT BAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBAABBAAAAAAAAAAAAAABBBBBABBBB LETTER ALPSLFMDEEMCBFRSPKLEMFHRSCJLJKUHPNMBBNNVVRKRHUTDJUKANJHBTPDFSVEVDU SIDE 121212122121212121111111112212122222112222111221112112212112212122 DIRECTION IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIOOOOOOOIOOIOOIOOIOOOOIOOIIIIOOO changed: step 121 100000000000000000000000000000000001111100011011011010100110110011 fail ^^ step 122 100000000000000000000000000000000001111100011011011010100110111111 step 123 100000000000000000000000000000000001111100011011011010100110110111 step 124 100000000000000000000000000000000001111100011011011010100110110111 test 30: *** FAIL *************************** 6 steps failed SLOT BAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBAABBAAAAAAAAAAAAAABBBBBABBBB LETTER ALPSLFMDEEMCBFRSPKLEMFHRSCJLJKUHPNMBBNNVVRKRHUTDJUKANJHBTPDFSVEVDU SIDE 121212122121212121111111112212122222112222111221112112212112212122 DIRECTION IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIOOOOOOOIOOIOOIOOIOOOOIOOIIIIOOO this fail OO all fails I I I O OO was hi 111111111111111111111111111111111111111111111111111111111111111111 rising ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ ^^^^^^^^^^^^^^^^^^^^^^^^^ falling vvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvv vvvvvvvvvvvvvvvvvvvvvvvvv was lo 00000000000000000000000000000000000000 0000000000000000000000000 total fails 30, total passes 0 space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C toggle comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit step 1 100000000000000000000000000000000001111100011011011010100110110111 step 2 100000000000000000000000000000000001111100100011011010100110110111 step 3 100000000000000000000000000000000001111100000011011010100110110111 step 4 100000000000000000000000000000000001111100000100011010100110110111 step 5 100000000000000000000000000000000001111100000000011010100110110111 step 6 100000000000000000000000000000000001111100000000100010100110110111 step 7 100000000000000000000000000000000001111100000000000010100110110111 step 8 100000000000000000000000000000000001111100000000000101010110110111 step 9 100000000000000000000000000000000001111100000000000001010110110111 step 10 100000000000000000000000000000000001111100000000000001011000110111 step 11 100000000000000000000000000000000001111100000000000001010000110111 step 12 100000000000000000000000000000000001111100000000000001010001110001 step 13 100000000000000000000000000000000001111100000000000001010000110001 step 14 100000000000000000000000000000000001111100000000000001010000110001 step 15 100000000000010000000000000000000000111101000000000001010000110001 step 16 100000000000010010000000000000000000110111000000000001010000110001 step 17 100000000000010010000000000000000000110111111000000001010000110001 step 18 100000000000010010000000000000000000110111011000000001010000110001 step 19 100000000000010010000000000000000000110111011111000001010000110001 step 20 100000000000010010000000000000000000110111011011000001010000110001 step 21 100000000000010010000000000000000000110111011011111001010000110001 step 22 100000000000010010000000000000000000110111011011011001010000110001 step 23 100000000000010010000000000000000000110111011011011110100000110001 step 24 100000000000010010000000000000000000110111011011011010100000110001 step 25 100000000000010010000000000000000000110111011011011010101110110001 step 26 100000000000010010000000000000000000110111011011011010100110110001 step 27 100000000000010010000000000000000000110111011011011010100111110111 step 28 100000000000010010000000000000000000110111011011011010100110110111 step 29 100000000000000010000000000000000001110110011011011010100110110111 step 30 100000000000000000000000000000000001111100011011011010100110110111 step 31 100000000000000000000000000000000001111100011011011010100110110111 step 32 100001000000000000000000000000000001111100011011011010100110110111 step 33 100001100000000000000000000000000001111100011011011010100110110111 step 34 100001100100000000000000000000000001111100011011011010100110110111 step 35 100001100110000000000000000000000001111100011011011010100110110111 step 36 100001100110100000000000000000000001111100011011011010100110110111 step 37 100001100110100100000000000000000001111100011011011010100110110111 step 38 100001100110100100010000000000000001111100011011011010100110110111 step 39 100001100110100100011000000000000001111100011011011010100110110111 step 40 100001100110100100011010000000000001111100011011011010100110110111 step 41 100001100110100100011011000000000001111100011011011010100110110111 step 42 100001100110100100011011010000000001111100011011011010100110110111 step 43 100001100110100100011011011000000001111100011011011010100110110111 step 44 100001100110100100011011011010000001111100011011011010100110110111 step 45 100001100110100100011011011011000001111100011011011010100110110111 step 46 100001100110100100011011011011010001111100011011011010100110110111 step 47 100001100110100100011011011011011001111100011011011010100110110111 step 48 100001100110100100011011011011011101111100011011011010100110110111 step 49 110001100110100100011011011011011100110111011011011010100110110111 step 50 100001100110100100011011011011011101111100011011011010100110110111 step 51 101001100110100100011011011011011100110111011011011010100110110111 step 52 100001100110100100011011011011011101111100011011011010100110110111 step 53 100101100110100100011011011011011100110111011011011010100110110111 step 54 100001100110100100011011011011011101111100011011011010100110110111 step 55 100011100110100100011011011011011100110111011011011010100110110111 step 56 100001100110100100011011011011011101111100011011011010100110110111 step 57 100001110110100100011011011011011100110111011011011010100110110111 step 58 100001100110100100011011011011011101111100011011011010100110110111 step 59 100001101110100100011011011011011100110111011011011010100110110111 step 60 100001100110100100011011011011011101111100011011011010100110110111 step 61 100001100111100100011011011011011100111101011011011010100110110111 step 62 100001100110100100011011011011011101111100011011011010100110110111 step 63 100001100110110100011011011011011100111101011011011010100110110111 step 64 100001100110100100011011011011011101111100011011011010100110110111 step 65 100001100110101100011011011011011101110110011011011010100110110111 step 66 100001100110100100011011011011011101111100011011011010100110110111 step 67 100001100110100110011011011011011101110110011011011010100110110111 step 68 100001100110100100011011011011011101111100011011011010100110110111 step 69 100001100110100101011011011011011101001111011011011010100110110111 step 70 100001100110100100011011011011011101111100011011011010100110110111 step 71 100001100110100100111011011011011101001111011011011010100110110111 step 72 100001100110100100011011011011011101111100011011011010100110110111 step 73 100001100110100100011111011011011101001111011011011010100110110111 step 74 100001100110100100011011011011011101111100011011011010100110110111 step 75 100001100110100100011011111011011101001111011011011010100110110111 step 76 100001100110100100011011011011011101111100011011011010100110110111 step 77 100001100110100100011011011111011101001111011011011010100110110111 step 78 100001100110100100011011011011011101111100011011011010100110110111 step 79 100001100110100100011011011011111101001111011011011010100110110111 step 80 100001100110100100011011011011011101111100011011011010100110110111 step 81 100001100110100100011011011011011111101110011011011010100110110111 step 82 100001100110100100011011011011011101111100011011011010100110110111 step 83 100000000000000000000000000000000001111100011011011010100110110111 step 84 100000000000000000000000000000000001111100011011011010100110100111 step 85 100000000000000000000000000000000001111100011011011010100110101101 step 86 100000000000000000000000000000000001111100011011011010100110100101 step 87 100000000000000000000000000000000001111100011011011010100110000001 step 88 100000000000000000000000000000000001111100011011011010100110100101 step 89 100000000000000000000000000000000001111100011011011010100110100101 step 90 100000000000000000000000000000000001111100011011011010100110101001 step 91 100000000000000000000000000000000001111100011011011010100110100001 step 92 100000000000000000000000000000000001111100011011011010100110000101 step 93 100000000000000000000000000000000001111100011011011010100110100001 step 94 100000000000000000000000000000000001111100011011011010100110100001 step 95 100000000000000000000000000000000001111100011011011010100110101001 step 96 100000000000000000000000000000000001111100011011011010100110100001 step 97 100000000000000000000000000000000001111100011011011010100110110001 step 98 100000000000000000000000000000000001111100011011011010100110111011 step 99 100000000000000000000000000000000001111100011011011010100110110011 step 100 100000000000000000000000000000000001111100011011011010100110110011 step 101 100000000000000000000000000000000001111100011011011010100110111111 step 102 100000000000000000000000000000000001111100011011011010100110110111 step 103 100000000000000000000000000000000001111100011011011010100110110111 step 104 100000000000000000000000000000000001111100011011011010100110111111 step 105 100000000000000000000000000000000001111100011011011010100110110111 step 106 100000000000000000000000000000000001111100011011011010100110100111 step 107 100000000000000000000000000000000001111100011011011010100110101101 step 108 100000000000000000000000000000000001111100011011011010100110100101 step 109 100000000000000000000000000000000001111100011011011010100110110101 step 110 100000000000000000000000000000000001111100011011011010100110111011 step 111 100000000000000000000000000000000001111100011011011010100110110011 step 112 100000000000000000000000000000000001111100011011011010100110100011 step 113 100000000000000000000000000000000001111100011011011010100110101101 step 114 100000000000000000000000000000000001111100011011011010100110100101 step 115 100000000000000000000000000000000001111100011011011010100110100101 SLOT BAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBAABBAAAAAAAAAAAAAABBBBBABBBB LETTER ALPSLFMDEEMCBFRSPKLEMFHRSCJLJKUHPNMBBNNVVRKRHUTDJUKANJHBTPDFSVEVDU SIDE 121212122121212121111111112212122222112222111221112112212112212122 DIRECTION IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIOOOOOOOIOOIOOIOOIOOOOIOOIIIIOOO changed: 10 step 116 100000000000000000000000000000000001111100011011011010100110101001 fail ^ SLOT BAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBAABBAAAAAAAAAAAAAABBBBBABBBB LETTER ALPSLFMDEEMCBFRSPKLEMFHRSCJLJKUHPNMBBNNVVRKRHUTDJUKANJHBTPDFSVEVDU SIDE 121212122121212121111111112212122222112222111221112112212112212122 DIRECTION IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIOOOOOOOIOOIOOIOOIOOOOIOOIIIIOOO changed: 0 step 117 100000000000000000000000000000000001111100011011011010100110100001 fail ^ SLOT BAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBAABBAAAAAAAAAAAAAABBBBBABBBB LETTER ALPSLFMDEEMCBFRSPKLEMFHRSCJLJKUHPNMBBNNVVRKRHUTDJUKANJHBTPDFSVEVDU SIDE 121212122121212121111111112212122222112222111221112112212112212122 DIRECTION IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIOOOOOOOIOOIOOIOOIOOOOIOOIIIIOOO changed: 1 step 118 100000000000000000000000000000000001111100011011011010100110110001 fail ^ SLOT BAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBAABBAAAAAAAAAAAAAABBBBBABBBB LETTER ALPSLFMDEEMCBFRSPKLEMFHRSCJLJKUHPNMBBNNVVRKRHUTDJUKANJHBTPDFSVEVDU SIDE 121212122121212121111111112212122222112222111221112112212112212122 DIRECTION IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIOOOOOOOIOOIOOIOOIOOOOIOOIIIIOOO changed: 1 1 step 119 100000000000000000000000000000000001111100011011011010100110111011 fail ^^ SLOT BAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBAABBAAAAAAAAAAAAAABBBBBABBBB LETTER ALPSLFMDEEMCBFRSPKLEMFHRSCJLJKUHPNMBBNNVVRKRHUTDJUKANJHBTPDFSVEVDU SIDE 121212122121212121111111112212122222112222111221112112212112212122 DIRECTION IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIOOOOOOOIOOIOOIOOIOOOOIOOIIIIOOO changed: 0 step 120 100000000000000000000000000000000001111100011011011010100110110011 fail ^^ SLOT BAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBAABBAAAAAAAAAAAAAABBBBBABBBB LETTER ALPSLFMDEEMCBFRSPKLEMFHRSCJLJKUHPNMBBNNVVRKRHUTDJUKANJHBTPDFSVEVDU SIDE 121212122121212121111111112212122222112222111221112112212112212122 DIRECTION IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIOOOOOOOIOOIOOIOOIOOOOIOOIIIIOOO changed: step 121 100000000000000000000000000000000001111100011011011010100110110011 fail ^^ step 122 100000000000000000000000000000000001111100011011011010100110111111 step 123 100000000000000000000000000000000001111100011011011010100110110111 step 124 100000000000000000000000000000000001111100011011011010100110110111 test 31: *** FAIL *************************** 6 steps failed SLOT BAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBAABBAAAAAAAAAAAAAABBBBBABBBB LETTER ALPSLFMDEEMCBFRSPKLEMFHRSCJLJKUHPNMBBNNVVRKRHUTDJUKANJHBTPDFSVEVDU SIDE 121212122121212121111111112212122222112222111221112112212112212122 DIRECTION IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIOOOOOOOIOOIOOIOOIOOOOIOOIIIIOOO this fail OO all fails I I I O OO was hi 111111111111111111111111111111111111111111111111111111111111111111 rising ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ ^^^^^^^^^^^^^^^^^^^^^^^^^ falling vvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvv vvvvvvvvvvvvvvvvvvvvvvvvv was lo 00000000000000000000000000000000000000 0000000000000000000000000 total fails 31, total passes 0 space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C toggle comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit step 1 100000000000000000000000000000000001111100011011011010100110110111 step 2 100000000000000000000000000000000001111100100011011010100110110111 step 3 100000000000000000000000000000000001111100000011011010100110110111 step 4 100000000000000000000000000000000001111100000100011010100110110111 step 5 100000000000000000000000000000000001111100000000011010100110110111 step 6 100000000000000000000000000000000001111100000000100010100110110111 step 7 100000000000000000000000000000000001111100000000000010100110110111 step 8 100000000000000000000000000000000001111100000000000101010110110111 step 9 100000000000000000000000000000000001111100000000000001010110110111 step 10 100000000000000000000000000000000001111100000000000001011000110111 step 11 100000000000000000000000000000000001111100000000000001010000110111 step 12 100000000000000000000000000000000001111100000000000001010001110001 step 13 100000000000000000000000000000000001111100000000000001010000110001 step 14 100000000000000000000000000000000001111100000000000001010000110001 step 15 100000000000010000000000000000000000111101000000000001010000110001 step 16 100000000000010010000000000000000000110111000000000001010000110001 step 17 100000000000010010000000000000000000110111111000000001010000110001 step 18 100000000000010010000000000000000000110111011000000001010000110001 step 19 100000000000010010000000000000000000110111011111000001010000110001 step 20 100000000000010010000000000000000000110111011011000001010000110001 step 21 100000000000010010000000000000000000110111011011111001010000110001 step 22 100000000000010010000000000000000000110111011011011001010000110001 step 23 100000000000010010000000000000000000110111011011011110100000110001 step 24 100000000000010010000000000000000000110111011011011010100000110001 step 25 100000000000010010000000000000000000110111011011011010101110110001 step 26 100000000000010010000000000000000000110111011011011010100110110001 step 27 100000000000010010000000000000000000110111011011011010100111110111 step 28 100000000000010010000000000000000000110111011011011010100110110111 step 29 100000000000000010000000000000000001110110011011011010100110110111 step 30 100000000000000000000000000000000001111100011011011010100110110111 step 31 100000000000000000000000000000000001111100011011011010100110110111 step 32 100001000000000000000000000000000001111100011011011010100110110111 step 33 100001100000000000000000000000000001111100011011011010100110110111 step 34 100001100100000000000000000000000001111100011011011010100110110111 step 35 100001100110000000000000000000000001111100011011011010100110110111 step 36 100001100110100000000000000000000001111100011011011010100110110111 step 37 100001100110100100000000000000000001111100011011011010100110110111 step 38 100001100110100100010000000000000001111100011011011010100110110111 step 39 100001100110100100011000000000000001111100011011011010100110110111 step 40 100001100110100100011010000000000001111100011011011010100110110111 step 41 100001100110100100011011000000000001111100011011011010100110110111 step 42 100001100110100100011011010000000001111100011011011010100110110111 step 43 100001100110100100011011011000000001111100011011011010100110110111 step 44 100001100110100100011011011010000001111100011011011010100110110111 step 45 100001100110100100011011011011000001111100011011011010100110110111 step 46 100001100110100100011011011011010001111100011011011010100110110111 step 47 100001100110100100011011011011011001111100011011011010100110110111 step 48 100001100110100100011011011011011101111100011011011010100110110111 step 49 110001100110100100011011011011011100110111011011011010100110110111 step 50 100001100110100100011011011011011101111100011011011010100110110111 step 51 101001100110100100011011011011011100110111011011011010100110110111 step 52 100001100110100100011011011011011101111100011011011010100110110111 step 53 100101100110100100011011011011011100110111011011011010100110110111 step 54 100001100110100100011011011011011101111100011011011010100110110111 step 55 100011100110100100011011011011011100110111011011011010100110110111 step 56 100001100110100100011011011011011101111100011011011010100110110111 step 57 100001110110100100011011011011011100110111011011011010100110110111 step 58 100001100110100100011011011011011101111100011011011010100110110111 step 59 100001101110100100011011011011011100110111011011011010100110110111 step 60 100001100110100100011011011011011101111100011011011010100110110111 step 61 100001100111100100011011011011011100111101011011011010100110110111 step 62 100001100110100100011011011011011101111100011011011010100110110111 step 63 100001100110110100011011011011011100111101011011011010100110110111 step 64 100001100110100100011011011011011101111100011011011010100110110111 step 65 100001100110101100011011011011011101110110011011011010100110110111 step 66 100001100110100100011011011011011101111100011011011010100110110111 step 67 100001100110100110011011011011011101110110011011011010100110110111 step 68 100001100110100100011011011011011101111100011011011010100110110111 step 69 100001100110100101011011011011011101001111011011011010100110110111 step 70 100001100110100100011011011011011101111100011011011010100110110111 step 71 100001100110100100111011011011011101001111011011011010100110110111 step 72 100001100110100100011011011011011101111100011011011010100110110111 step 73 100001100110100100011111011011011101001111011011011010100110110111 step 74 100001100110100100011011011011011101111100011011011010100110110111 step 75 100001100110100100011011111011011101001111011011011010100110110111 step 76 100001100110100100011011011011011101111100011011011010100110110111 step 77 100001100110100100011011011111011101001111011011011010100110110111 step 78 100001100110100100011011011011011101111100011011011010100110110111 step 79 100001100110100100011011011011111101001111011011011010100110110111 step 80 100001100110100100011011011011011101111100011011011010100110110111 step 81 100001100110100100011011011011011111101110011011011010100110110111 step 82 100001100110100100011011011011011101111100011011011010100110110111 step 83 100000000000000000000000000000000001111100011011011010100110110111 step 84 100000000000000000000000000000000001111100011011011010100110100111 step 85 100000000000000000000000000000000001111100011011011010100110101101 step 86 100000000000000000000000000000000001111100011011011010100110100101 step 87 100000000000000000000000000000000001111100011011011010100110000001 step 88 100000000000000000000000000000000001111100011011011010100110100101 step 89 100000000000000000000000000000000001111100011011011010100110100101 step 90 100000000000000000000000000000000001111100011011011010100110101001 step 91 100000000000000000000000000000000001111100011011011010100110100001 step 92 100000000000000000000000000000000001111100011011011010100110000101 step 93 100000000000000000000000000000000001111100011011011010100110100001 step 94 100000000000000000000000000000000001111100011011011010100110100001 step 95 100000000000000000000000000000000001111100011011011010100110101001 step 96 100000000000000000000000000000000001111100011011011010100110100001 step 97 100000000000000000000000000000000001111100011011011010100110110001 step 98 100000000000000000000000000000000001111100011011011010100110111011 step 99 100000000000000000000000000000000001111100011011011010100110110011 step 100 100000000000000000000000000000000001111100011011011010100110110011 step 101 100000000000000000000000000000000001111100011011011010100110111111 step 102 100000000000000000000000000000000001111100011011011010100110110111 step 103 100000000000000000000000000000000001111100011011011010100110110111 step 104 100000000000000000000000000000000001111100011011011010100110111111 step 105 100000000000000000000000000000000001111100011011011010100110110111 step 106 100000000000000000000000000000000001111100011011011010100110100111 step 107 100000000000000000000000000000000001111100011011011010100110101101 step 108 100000000000000000000000000000000001111100011011011010100110100101 step 109 100000000000000000000000000000000001111100011011011010100110110101 step 110 100000000000000000000000000000000001111100011011011010100110111011 step 111 100000000000000000000000000000000001111100011011011010100110110011 step 112 100000000000000000000000000000000001111100011011011010100110100011 step 113 100000000000000000000000000000000001111100011011011010100110101101 step 114 100000000000000000000000000000000001111100011011011010100110100101 step 115 100000000000000000000000000000000001111100011011011010100110100101 SLOT BAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBAABBAAAAAAAAAAAAAABBBBBABBBB LETTER ALPSLFMDEEMCBFRSPKLEMFHRSCJLJKUHPNMBBNNVVRKRHUTDJUKANJHBTPDFSVEVDU SIDE 121212122121212121111111112212122222112222111221112112212112212122 DIRECTION IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIOOOOOOOIOOIOOIOOIOOOOIOOIIIIOOO changed: 10 step 116 100000000000000000000000000000000001111100011011011010100110101001 fail ^ SLOT BAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBAABBAAAAAAAAAAAAAABBBBBABBBB LETTER ALPSLFMDEEMCBFRSPKLEMFHRSCJLJKUHPNMBBNNVVRKRHUTDJUKANJHBTPDFSVEVDU SIDE 121212122121212121111111112212122222112222111221112112212112212122 DIRECTION IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIOOOOOOOIOOIOOIOOIOOOOIOOIIIIOOO changed: 0 step 117 100000000000000000000000000000000001111100011011011010100110100001 fail ^ SLOT BAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBAABBAAAAAAAAAAAAAABBBBBABBBB LETTER ALPSLFMDEEMCBFRSPKLEMFHRSCJLJKUHPNMBBNNVVRKRHUTDJUKANJHBTPDFSVEVDU SIDE 121212122121212121111111112212122222112222111221112112212112212122 DIRECTION IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIOOOOOOOIOOIOOIOOIOOOOIOOIIIIOOO changed: 1 step 118 100000000000000000000000000000000001111100011011011010100110110001 fail ^ SLOT BAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBAABBAAAAAAAAAAAAAABBBBBABBBB LETTER ALPSLFMDEEMCBFRSPKLEMFHRSCJLJKUHPNMBBNNVVRKRHUTDJUKANJHBTPDFSVEVDU SIDE 121212122121212121111111112212122222112222111221112112212112212122 DIRECTION IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIOOOOOOOIOOIOOIOOIOOOOIOOIIIIOOO changed: 1 1 step 119 100000000000000000000000000000000001111100011011011010100110111011 fail ^^ SLOT BAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBAABBAAAAAAAAAAAAAABBBBBABBBB LETTER ALPSLFMDEEMCBFRSPKLEMFHRSCJLJKUHPNMBBNNVVRKRHUTDJUKANJHBTPDFSVEVDU SIDE 121212122121212121111111112212122222112222111221112112212112212122 DIRECTION IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIOOOOOOOIOOIOOIOOIOOOOIOOIIIIOOO changed: 0 step 120 100000000000000000000000000000000001111100011011011010100110110011 fail ^^ SLOT BAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBAABBAAAAAAAAAAAAAABBBBBABBBB LETTER ALPSLFMDEEMCBFRSPKLEMFHRSCJLJKUHPNMBBNNVVRKRHUTDJUKANJHBTPDFSVEVDU SIDE 121212122121212121111111112212122222112222111221112112212112212122 DIRECTION IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIOOOOOOOIOOIOOIOOIOOOOIOOIIIIOOO changed: step 121 100000000000000000000000000000000001111100011011011010100110110011 fail ^^ step 122 100000000000000000000000000000000001111100011011011010100110111111 step 123 100000000000000000000000000000000001111100011011011010100110110111 step 124 100000000000000000000000000000000001111100011011011010100110110111 test 32: *** FAIL *************************** 6 steps failed SLOT BAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBAABBAAAAAAAAAAAAAABBBBBABBBB LETTER ALPSLFMDEEMCBFRSPKLEMFHRSCJLJKUHPNMBBNNVVRKRHUTDJUKANJHBTPDFSVEVDU SIDE 121212122121212121111111112212122222112222111221112112212112212122 DIRECTION IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIOOOOOOOIOOIOOIOOIOOOOIOOIIIIOOO this fail OO all fails I I I O OO was hi 111111111111111111111111111111111111111111111111111111111111111111 rising ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ ^^^^^^^^^^^^^^^^^^^^^^^^^ falling vvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvv vvvvvvvvvvvvvvvvvvvvvvvvv was lo 00000000000000000000000000000000000000 0000000000000000000000000 total fails 32, total passes 0 space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C toggle comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit step 1 100000000000000000000000000000000001111100011011011010100110110111 step 2 100000000000000000000000000000000001111100100011011010100110110111 step 3 100000000000000000000000000000000001111100000011011010100110110111 step 4 100000000000000000000000000000000001111100000100011010100110110111 step 5 100000000000000000000000000000000001111100000000011010100110110111 step 6 100000000000000000000000000000000001111100000000100010100110110111 step 7 100000000000000000000000000000000001111100000000000010100110110111 step 8 100000000000000000000000000000000001111100000000000101010110110111 step 9 100000000000000000000000000000000001111100000000000001010110110111 step 10 100000000000000000000000000000000001111100000000000001011000110111 step 11 100000000000000000000000000000000001111100000000000001010000110111 step 12 100000000000000000000000000000000001111100000000000001010001110001 step 13 100000000000000000000000000000000001111100000000000001010000110001 step 14 100000000000000000000000000000000001111100000000000001010000110001 step 15 100000000000010000000000000000000000111101000000000001010000110001 step 16 100000000000010010000000000000000000110111000000000001010000110001 step 17 100000000000010010000000000000000000110111111000000001010000110001 step 18 100000000000010010000000000000000000110111011000000001010000110001 step 19 100000000000010010000000000000000000110111011111000001010000110001 step 20 100000000000010010000000000000000000110111011011000001010000110001 step 21 100000000000010010000000000000000000110111011011111001010000110001 step 22 100000000000010010000000000000000000110111011011011001010000110001 step 23 100000000000010010000000000000000000110111011011011110100000110001 step 24 100000000000010010000000000000000000110111011011011010100000110001 step 25 100000000000010010000000000000000000110111011011011010101110110001 step 26 100000000000010010000000000000000000110111011011011010100110110001 step 27 100000000000010010000000000000000000110111011011011010100111110111 step 28 100000000000010010000000000000000000110111011011011010100110110111 step 29 100000000000000010000000000000000001110110011011011010100110110111 step 30 100000000000000000000000000000000001111100011011011010100110110111 step 31 100000000000000000000000000000000001111100011011011010100110110111 step 32 100001000000000000000000000000000001111100011011011010100110110111 step 33 100001100000000000000000000000000001111100011011011010100110110111 step 34 100001100100000000000000000000000001111100011011011010100110110111 step 35 100001100110000000000000000000000001111100011011011010100110110111 step 36 100001100110100000000000000000000001111100011011011010100110110111 step 37 100001100110100100000000000000000001111100011011011010100110110111 step 38 100001100110100100010000000000000001111100011011011010100110110111 step 39 100001100110100100011000000000000001111100011011011010100110110111 step 40 100001100110100100011010000000000001111100011011011010100110110111 step 41 100001100110100100011011000000000001111100011011011010100110110111 step 42 100001100110100100011011010000000001111100011011011010100110110111 step 43 100001100110100100011011011000000001111100011011011010100110110111 step 44 100001100110100100011011011010000001111100011011011010100110110111 step 45 100001100110100100011011011011000001111100011011011010100110110111 step 46 100001100110100100011011011011010001111100011011011010100110110111 step 47 100001100110100100011011011011011001111100011011011010100110110111 step 48 100001100110100100011011011011011101111100011011011010100110110111 step 49 110001100110100100011011011011011100110111011011011010100110110111 step 50 100001100110100100011011011011011101111100011011011010100110110111 step 51 101001100110100100011011011011011100110111011011011010100110110111 step 52 100001100110100100011011011011011101111100011011011010100110110111 step 53 100101100110100100011011011011011100110111011011011010100110110111 step 54 100001100110100100011011011011011101111100011011011010100110110111 step 55 100011100110100100011011011011011100110111011011011010100110110111 step 56 100001100110100100011011011011011101111100011011011010100110110111 step 57 100001110110100100011011011011011100110111011011011010100110110111 step 58 100001100110100100011011011011011101111100011011011010100110110111 step 59 100001101110100100011011011011011100110111011011011010100110110111 step 60 100001100110100100011011011011011101111100011011011010100110110111 step 61 100001100111100100011011011011011100111101011011011010100110110111 step 62 100001100110100100011011011011011101111100011011011010100110110111 step 63 100001100110110100011011011011011100111101011011011010100110110111 step 64 100001100110100100011011011011011101111100011011011010100110110111 step 65 100001100110101100011011011011011101110110011011011010100110110111 step 66 100001100110100100011011011011011101111100011011011010100110110111 step 67 100001100110100110011011011011011101110110011011011010100110110111 step 68 100001100110100100011011011011011101111100011011011010100110110111 step 69 100001100110100101011011011011011101001111011011011010100110110111 step 70 100001100110100100011011011011011101111100011011011010100110110111 step 71 100001100110100100111011011011011101001111011011011010100110110111 step 72 100001100110100100011011011011011101111100011011011010100110110111 step 73 100001100110100100011111011011011101001111011011011010100110110111 step 74 100001100110100100011011011011011101111100011011011010100110110111 step 75 100001100110100100011011111011011101001111011011011010100110110111 step 76 100001100110100100011011011011011101111100011011011010100110110111 step 77 100001100110100100011011011111011101001111011011011010100110110111 step 78 100001100110100100011011011011011101111100011011011010100110110111 step 79 100001100110100100011011011011111101001111011011011010100110110111 step 80 100001100110100100011011011011011101111100011011011010100110110111 step 81 100001100110100100011011011011011111101110011011011010100110110111 step 82 100001100110100100011011011011011101111100011011011010100110110111 step 83 100000000000000000000000000000000001111100011011011010100110110111 step 84 100000000000000000000000000000000001111100011011011010100110100111 step 85 100000000000000000000000000000000001111100011011011010100110101101 step 86 100000000000000000000000000000000001111100011011011010100110100101 step 87 100000000000000000000000000000000001111100011011011010100110000001 step 88 100000000000000000000000000000000001111100011011011010100110100101 step 89 100000000000000000000000000000000001111100011011011010100110100101 step 90 100000000000000000000000000000000001111100011011011010100110101001 step 91 100000000000000000000000000000000001111100011011011010100110100001 step 92 100000000000000000000000000000000001111100011011011010100110000101 step 93 100000000000000000000000000000000001111100011011011010100110100001 step 94 100000000000000000000000000000000001111100011011011010100110100001 step 95 100000000000000000000000000000000001111100011011011010100110101001 step 96 100000000000000000000000000000000001111100011011011010100110100001 step 97 100000000000000000000000000000000001111100011011011010100110110001 step 98 100000000000000000000000000000000001111100011011011010100110111011 step 99 100000000000000000000000000000000001111100011011011010100110110011 step 100 100000000000000000000000000000000001111100011011011010100110110011 step 101 100000000000000000000000000000000001111100011011011010100110111111 step 102 100000000000000000000000000000000001111100011011011010100110110111 step 103 100000000000000000000000000000000001111100011011011010100110110111 step 104 100000000000000000000000000000000001111100011011011010100110111111 step 105 100000000000000000000000000000000001111100011011011010100110110111 step 106 100000000000000000000000000000000001111100011011011010100110100111 step 107 100000000000000000000000000000000001111100011011011010100110101101 step 108 100000000000000000000000000000000001111100011011011010100110100101 step 109 100000000000000000000000000000000001111100011011011010100110110101 step 110 100000000000000000000000000000000001111100011011011010100110111011 step 111 100000000000000000000000000000000001111100011011011010100110110011 step 112 100000000000000000000000000000000001111100011011011010100110100011 step 113 100000000000000000000000000000000001111100011011011010100110101101 step 114 100000000000000000000000000000000001111100011011011010100110100101 step 115 100000000000000000000000000000000001111100011011011010100110100101 SLOT BAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBAABBAAAAAAAAAAAAAABBBBBABBBB LETTER ALPSLFMDEEMCBFRSPKLEMFHRSCJLJKUHPNMBBNNVVRKRHUTDJUKANJHBTPDFSVEVDU SIDE 121212122121212121111111112212122222112222111221112112212112212122 DIRECTION IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIOOOOOOOIOOIOOIOOIOOOOIOOIIIIOOO changed: 10 step 116 100000000000000000000000000000000001111100011011011010100110101001 fail ^ SLOT BAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBAABBAAAAAAAAAAAAAABBBBBABBBB LETTER ALPSLFMDEEMCBFRSPKLEMFHRSCJLJKUHPNMBBNNVVRKRHUTDJUKANJHBTPDFSVEVDU SIDE 121212122121212121111111112212122222112222111221112112212112212122 DIRECTION IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIOOOOOOOIOOIOOIOOIOOOOIOOIIIIOOO changed: 0 step 117 100000000000000000000000000000000001111100011011011010100110100001 fail ^ SLOT BAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBAABBAAAAAAAAAAAAAABBBBBABBBB LETTER ALPSLFMDEEMCBFRSPKLEMFHRSCJLJKUHPNMBBNNVVRKRHUTDJUKANJHBTPDFSVEVDU SIDE 121212122121212121111111112212122222112222111221112112212112212122 DIRECTION IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIOOOOOOOIOOIOOIOOIOOOOIOOIIIIOOO changed: 1 step 118 100000000000000000000000000000000001111100011011011010100110110001 fail ^ SLOT BAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBAABBAAAAAAAAAAAAAABBBBBABBBB LETTER ALPSLFMDEEMCBFRSPKLEMFHRSCJLJKUHPNMBBNNVVRKRHUTDJUKANJHBTPDFSVEVDU SIDE 121212122121212121111111112212122222112222111221112112212112212122 DIRECTION IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIOOOOOOOIOOIOOIOOIOOOOIOOIIIIOOO changed: 1 1 step 119 100000000000000000000000000000000001111100011011011010100110111011 fail ^^ SLOT BAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBAABBAAAAAAAAAAAAAABBBBBABBBB LETTER ALPSLFMDEEMCBFRSPKLEMFHRSCJLJKUHPNMBBNNVVRKRHUTDJUKANJHBTPDFSVEVDU SIDE 121212122121212121111111112212122222112222111221112112212112212122 DIRECTION IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIOOOOOOOIOOIOOIOOIOOOOIOOIIIIOOO changed: 0 step 120 100000000000000000000000000000000001111100011011011010100110110011 fail ^^ SLOT BAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBAABBAAAAAAAAAAAAAABBBBBABBBB LETTER ALPSLFMDEEMCBFRSPKLEMFHRSCJLJKUHPNMBBNNVVRKRHUTDJUKANJHBTPDFSVEVDU SIDE 121212122121212121111111112212122222112222111221112112212112212122 DIRECTION IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIOOOOOOOIOOIOOIOOIOOOOIOOIIIIOOO changed: step 121 100000000000000000000000000000000001111100011011011010100110110011 fail ^^ step 122 100000000000000000000000000000000001111100011011011010100110111111 step 123 100000000000000000000000000000000001111100011011011010100110110111 step 124 100000000000000000000000000000000001111100011011011010100110110111 test 33: *** FAIL *************************** 6 steps failed SLOT BAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBAABBAAAAAAAAAAAAAABBBBBABBBB LETTER ALPSLFMDEEMCBFRSPKLEMFHRSCJLJKUHPNMBBNNVVRKRHUTDJUKANJHBTPDFSVEVDU SIDE 121212122121212121111111112212122222112222111221112112212112212122 DIRECTION IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIOOOOOOOIOOIOOIOOIOOOOIOOIIIIOOO this fail OO all fails I I I O OO was hi 111111111111111111111111111111111111111111111111111111111111111111 rising ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ ^^^^^^^^^^^^^^^^^^^^^^^^^ falling vvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvv vvvvvvvvvvvvvvvvvvvvvvvvv was lo 00000000000000000000000000000000000000 0000000000000000000000000 total fails 33, total passes 0 space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C toggle comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit step 1 100000000000000000000000000000000001111100011011011010100110110111 step 2 100000000000000000000000000000000001111100100011011010100110110111 step 3 100000000000000000000000000000000001111100000011011010100110110111 step 4 100000000000000000000000000000000001111100000100011010100110110111 step 5 100000000000000000000000000000000001111100000000011010100110110111 step 6 100000000000000000000000000000000001111100000000100010100110110111 step 7 100000000000000000000000000000000001111100000000000010100110110111 step 8 100000000000000000000000000000000001111100000000000101010110110111 step 9 100000000000000000000000000000000001111100000000000001010110110111 step 10 100000000000000000000000000000000001111100000000000001011000110111 step 11 100000000000000000000000000000000001111100000000000001010000110111 step 12 100000000000000000000000000000000001111100000000000001010001110001 step 13 100000000000000000000000000000000001111100000000000001010000110001 step 14 100000000000000000000000000000000001111100000000000001010000110001 step 15 100000000000010000000000000000000000111101000000000001010000110001 step 16 100000000000010010000000000000000000110111000000000001010000110001 step 17 100000000000010010000000000000000000110111111000000001010000110001 step 18 100000000000010010000000000000000000110111011000000001010000110001 step 19 100000000000010010000000000000000000110111011111000001010000110001 step 20 100000000000010010000000000000000000110111011011000001010000110001 step 21 100000000000010010000000000000000000110111011011111001010000110001 step 22 100000000000010010000000000000000000110111011011011001010000110001 step 23 100000000000010010000000000000000000110111011011011110100000110001 step 24 100000000000010010000000000000000000110111011011011010100000110001 step 25 100000000000010010000000000000000000110111011011011010101110110001 step 26 100000000000010010000000000000000000110111011011011010100110110001 step 27 100000000000010010000000000000000000110111011011011010100111110111 step 28 100000000000010010000000000000000000110111011011011010100110110111 step 29 100000000000000010000000000000000001110110011011011010100110110111 step 30 100000000000000000000000000000000001111100011011011010100110110111 step 31 100000000000000000000000000000000001111100011011011010100110110111 step 32 100001000000000000000000000000000001111100011011011010100110110111 step 33 100001100000000000000000000000000001111100011011011010100110110111 step 34 100001100100000000000000000000000001111100011011011010100110110111 step 35 100001100110000000000000000000000001111100011011011010100110110111 step 36 100001100110100000000000000000000001111100011011011010100110110111 step 37 100001100110100100000000000000000001111100011011011010100110110111 step 38 100001100110100100010000000000000001111100011011011010100110110111 step 39 100001100110100100011000000000000001111100011011011010100110110111 step 40 100001100110100100011010000000000001111100011011011010100110110111 step 41 100001100110100100011011000000000001111100011011011010100110110111 step 42 100001100110100100011011010000000001111100011011011010100110110111 step 43 100001100110100100011011011000000001111100011011011010100110110111 step 44 100001100110100100011011011010000001111100011011011010100110110111 step 45 100001100110100100011011011011000001111100011011011010100110110111 step 46 100001100110100100011011011011010001111100011011011010100110110111 step 47 100001100110100100011011011011011001111100011011011010100110110111 step 48 100001100110100100011011011011011101111100011011011010100110110111 step 49 110001100110100100011011011011011100110111011011011010100110110111 step 50 100001100110100100011011011011011101111100011011011010100110110111 step 51 101001100110100100011011011011011100110111011011011010100110110111 step 52 100001100110100100011011011011011101111100011011011010100110110111 step 53 100101100110100100011011011011011100110111011011011010100110110111 step 54 100001100110100100011011011011011101111100011011011010100110110111 step 55 100011100110100100011011011011011100110111011011011010100110110111 step 56 100001100110100100011011011011011101111100011011011010100110110111 step 57 100001110110100100011011011011011100110111011011011010100110110111 step 58 100001100110100100011011011011011101111100011011011010100110110111 step 59 100001101110100100011011011011011100110111011011011010100110110111 step 60 100001100110100100011011011011011101111100011011011010100110110111 step 61 100001100111100100011011011011011100111101011011011010100110110111 step 62 100001100110100100011011011011011101111100011011011010100110110111 step 63 100001100110110100011011011011011100111101011011011010100110110111 step 64 100001100110100100011011011011011101111100011011011010100110110111 step 65 100001100110101100011011011011011101110110011011011010100110110111 step 66 100001100110100100011011011011011101111100011011011010100110110111 step 67 100001100110100110011011011011011101110110011011011010100110110111 step 68 100001100110100100011011011011011101111100011011011010100110110111 step 69 100001100110100101011011011011011101001111011011011010100110110111 step 70 100001100110100100011011011011011101111100011011011010100110110111 step 71 100001100110100100111011011011011101001111011011011010100110110111 step 72 100001100110100100011011011011011101111100011011011010100110110111 step 73 100001100110100100011111011011011101001111011011011010100110110111 step 74 100001100110100100011011011011011101111100011011011010100110110111 step 75 100001100110100100011011111011011101001111011011011010100110110111 step 76 100001100110100100011011011011011101111100011011011010100110110111 step 77 100001100110100100011011011111011101001111011011011010100110110111 step 78 100001100110100100011011011011011101111100011011011010100110110111 step 79 100001100110100100011011011011111101001111011011011010100110110111 step 80 100001100110100100011011011011011101111100011011011010100110110111 step 81 100001100110100100011011011011011111101110011011011010100110110111 step 82 100001100110100100011011011011011101111100011011011010100110110111 step 83 100000000000000000000000000000000001111100011011011010100110110111 step 84 100000000000000000000000000000000001111100011011011010100110100111 step 85 100000000000000000000000000000000001111100011011011010100110101101 step 86 100000000000000000000000000000000001111100011011011010100110100101 step 87 100000000000000000000000000000000001111100011011011010100110000001 step 88 100000000000000000000000000000000001111100011011011010100110100101 step 89 100000000000000000000000000000000001111100011011011010100110100101 step 90 100000000000000000000000000000000001111100011011011010100110101001 step 91 100000000000000000000000000000000001111100011011011010100110100001 step 92 100000000000000000000000000000000001111100011011011010100110000101 step 93 100000000000000000000000000000000001111100011011011010100110100001 step 94 100000000000000000000000000000000001111100011011011010100110100001 step 95 100000000000000000000000000000000001111100011011011010100110101001 step 96 100000000000000000000000000000000001111100011011011010100110100001 step 97 100000000000000000000000000000000001111100011011011010100110110001 step 98 100000000000000000000000000000000001111100011011011010100110111011 step 99 100000000000000000000000000000000001111100011011011010100110110011 step 100 100000000000000000000000000000000001111100011011011010100110110011 step 101 100000000000000000000000000000000001111100011011011010100110111111 step 102 100000000000000000000000000000000001111100011011011010100110110111 step 103 100000000000000000000000000000000001111100011011011010100110110111 step 104 100000000000000000000000000000000001111100011011011010100110111111 step 105 100000000000000000000000000000000001111100011011011010100110110111 step 106 100000000000000000000000000000000001111100011011011010100110100111 step 107 100000000000000000000000000000000001111100011011011010100110101101 step 108 100000000000000000000000000000000001111100011011011010100110100101 step 109 100000000000000000000000000000000001111100011011011010100110110101 step 110 100000000000000000000000000000000001111100011011011010100110111011 step 111 100000000000000000000000000000000001111100011011011010100110110011 step 112 100000000000000000000000000000000001111100011011011010100110100011 step 113 100000000000000000000000000000000001111100011011011010100110101101 step 114 100000000000000000000000000000000001111100011011011010100110100101 step 115 100000000000000000000000000000000001111100011011011010100110100101 SLOT BAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBAABBAAAAAAAAAAAAAABBBBBABBBB LETTER ALPSLFMDEEMCBFRSPKLEMFHRSCJLJKUHPNMBBNNVVRKRHUTDJUKANJHBTPDFSVEVDU SIDE 121212122121212121111111112212122222112222111221112112212112212122 DIRECTION IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIOOOOOOOIOOIOOIOOIOOOOIOOIIIIOOO changed: 10 step 116 100000000000000000000000000000000001111100011011011010100110101001 fail ^ space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C toggle comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit comment_flag is 1 space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C toggle comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT BAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBAABBAAAAAAAAAAAAAABBBBBABBBB LETTER ALPSLFMDEEMCBFRSPKLEMFHRSCJLJKUHPNMBBNNVVRKRHUTDJUKANJHBTPDFSVEVDU SIDE 121212122121212121111111112212122222112222111221112112212112212122 DIRECTION IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIOOOOOOOIOOIOOIOOIOOOOIOOIIIIOOO source: 0 changed: 0 step 117 100000000000000000000000000000000001111100011011011010100110100001 fail ^ SLOT BAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBAABBAAAAAAAAAAAAAABBBBBABBBB LETTER ALPSLFMDEEMCBFRSPKLEMFHRSCJLJKUHPNMBBNNVVRKRHUTDJUKANJHBTPDFSVEVDU SIDE 121212122121212121111111112212122222112222111221112112212112212122 DIRECTION IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIOOOOOOOIOOIOOIOOIOOOOIOOIIIIOOO source: ; shift in 1, expect 10 source: 1 changed: 1 step 118 100000000000000000000000000000000001111100011011011010100110110001 fail ^ SLOT BAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBAABBAAAAAAAAAAAAAABBBBBABBBB LETTER ALPSLFMDEEMCBFRSPKLEMFHRSCJLJKUHPNMBBNNVVRKRHUTDJUKANJHBTPDFSVEVDU SIDE 121212122121212121111111112212122222112222111221112112212112212122 DIRECTION IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIOOOOOOOIOOIOOIOOIOOOOIOOIIIIOOO source: 110 changed: 1 1 step 119 100000000000000000000000000000000001111100011011011010100110111011 fail ^^ SLOT BAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBAABBAAAAAAAAAAAAAABBBBBABBBB LETTER ALPSLFMDEEMCBFRSPKLEMFHRSCJLJKUHPNMBBNNVVRKRHUTDJUKANJHBTPDFSVEVDU SIDE 121212122121212121111111112212122222112222111221112112212112212122 DIRECTION IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIOOOOOOOIOOIOOIOOIOOOOIOOIIIIOOO source: 0 changed: 0 step 120 100000000000000000000000000000000001111100011011011010100110110011 fail ^^ SLOT BAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBAABBAAAAAAAAAAAAAABBBBBABBBB LETTER ALPSLFMDEEMCBFRSPKLEMFHRSCJLJKUHPNMBBNNVVRKRHUTDJUKANJHBTPDFSVEVDU SIDE 121212122121212121111111112212122222112222111221112112212112212122 DIRECTION IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIOOOOOOOIOOIOOIOOIOOOOIOOIIIIOOO source: ; shift in 1, expect 11 source: 1 changed: step 121 100000000000000000000000000000000001111100011011011010100110110011 fail ^^ source: 111 changed: 11 step 122 100000000000000000000000000000000001111100011011011010100110111111 source: 0 changed: 0 step 123 100000000000000000000000000000000001111100011011011010100110110111 source: ; no change source: 100000000000000000000000000000000001111100011011011010100110110111 changed: step 124 100000000000000000000000000000000001111100011011011010100110110111 test 34: *** FAIL *************************** 6 steps failed SLOT BAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBAABBAAAAAAAAAAAAAABBBBBABBBB LETTER ALPSLFMDEEMCBFRSPKLEMFHRSCJLJKUHPNMBBNNVVRKRHUTDJUKANJHBTPDFSVEVDU SIDE 121212122121212121111111112212122222112222111221112112212112212122 DIRECTION IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIOOOOOOOIOOIOOIOOIOOOOIOOIIIIOOO this fail OO all fails I I I O OO was hi 111111111111111111111111111111111111111111111111111111111111111111 rising ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ ^^^^^^^^^^^^^^^^^^^^^^^^^ falling vvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvv vvvvvvvvvvvvvvvvvvvvvvvvv was lo 00000000000000000000000000000000000000 0000000000000000000000000 total fails 34, total passes 0 space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C toggle comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit source: ; all registers are unknown source: ; turn on C0, PHASE source: ; with no ENABLES, BUS2,BUS3 is 11, C2 is 1 source: 1000000000000000000000000000000000011111000XX0XX0XX0XXXX0XX0110XX1 changed: step 1 100000000000000000000000000000000001111100011011011010100110110111 source: source: ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; source: ; source: ; set all registers LOW source: ; source: ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; source: source: ; load TMA SETUP from tape bus (00) source: 100 changed: 100 step 2 100000000000000000000000000000000001111100100011011010100110110111 source: 0 changed: 0 step 3 100000000000000000000000000000000001111100000011011010100110110111 source: ; load TMA from tape bus (00) source: 100 changed: 100 step 4 100000000000000000000000000000000001111100000100011010100110110111 source: 0 changed: 0 step 5 100000000000000000000000000000000001111100000000011010100110110111 source: ; load TBN from tape bus (00) source: 100 changed: 100 step 6 100000000000000000000000000000000001111100000000100010100110110111 source: 0 changed: 0 step 7 100000000000000000000000000000000001111100000000000010100110110111 source: ; load TAC from tape bus (00) source: 10101 changed: 10101 step 8 100000000000000000000000000000000001111100000000000101010110110111 source: 0 changed: 0 step 9 100000000000000000000000000000000001111100000000000001010110110111 source: ; load TB from tape bus (00) source: 100 changed: 100 step 10 100000000000000000000000000000000001111100000000000001011000110111 source: 0 changed: 0 step 11 100000000000000000000000000000000001111100000000000001010000110111 source: ; load RWB from TB (JAMS CLEAR AND PRESET) source: 1 00 changed: 1 00 step 12 100000000000000000000000000000000001111100000000000001010001110001 source: 0 changed: 0 step 13 100000000000000000000000000000000001111100000000000001010000110001 source: ; (no change) source: 100000000000000000000000000000000001111100000000000001010000110001 changed: step 14 100000000000000000000000000000000001111100000000000001010000110001 source: source: source: ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; source: ; source: ; set all registers HIGH source: ; source: ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; source: source: ; set pin AF1 (AND with itself) to clear pin BB2 (AND-NOR output) and set pin BR2 TAPE BUS 3 OUTPUT source: 1 0 1 changed: 1 0 1 step 15 100000000000010000000000000000000000111101000000000001010000110001 source: ; set pin AP2 (AND with itself) to clear pin AN2 (AND-NOR output) and set pin BV2 TAPE BUS 2 OUTPUT source: 1 0 1 changed: 1 0 1 step 16 100000000000010010000000000000000000110111000000000001010000110001 source: source: source: ; load TMA SETUP from tape bus (11) source: 111 changed: 111 step 17 100000000000010010000000000000000000110111111000000001010000110001 source: 0 changed: 0 step 18 100000000000010010000000000000000000110111011000000001010000110001 source: ; load TMA from tape bus (11) source: 111 changed: 111 step 19 100000000000010010000000000000000000110111011111000001010000110001 source: 0 changed: 0 step 20 100000000000010010000000000000000000110111011011000001010000110001 source: ; load TBN from tape bus (11) source: 111 changed: 111 step 21 100000000000010010000000000000000000110111011011111001010000110001 source: 0 changed: 0 step 22 100000000000010010000000000000000000110111011011011001010000110001 source: ; load TAC from tape bus (11) source: 11010 changed: 11010 step 23 100000000000010010000000000000000000110111011011011110100000110001 source: 0 changed: 0 step 24 100000000000010010000000000000000000110111011011011010100000110001 source: ; load TB from tape bus (11) source: 111 changed: 111 step 25 100000000000010010000000000000000000110111011011011010101110110001 source: 0 changed: 0 step 26 100000000000010010000000000000000000110111011011011010100110110001 source: ; load RWB from TB (JAMS CLEAR AND PRESET) source: 1 11 changed: 1 11 step 27 100000000000010010000000000000000000110111011011011010100111110111 source: 0 changed: 0 step 28 100000000000010010000000000000000000110111011011011010100110110111 source: ; clear pin AF1 (AND with itself) to set pin BB2 (AND-NOR output) and clear pin BR2 TAPE BUS 3 OUTPUT source: 0 1 0 changed: 0 1 0 step 29 100000000000000010000000000000000001110110011011011010100110110111 source: ; clear pin AP2 (AND with itself) to set pin AN2 (AND-NOR output) and clear pin BV2 TAPE BUS 2 OUTPUT source: 0 1 0 changed: 0 1 0 step 30 100000000000000000000000000000000001111100011011011010100110110111 source: ; (no change) source: 100000000000000000000000000000000001111100011011011010100110110111 changed: step 31 100000000000000000000000000000000001111100011011011010100110110111 source: source: source: ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; source: ; source: ; test AND-NOR logic source: ; source: ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; source: source: ; (all registers are HIGH) source: ; set all pins HIGH except ENABLES source: source: ; set pin AF2 HIGH source: 1 changed: 1 step 32 100001000000000000000000000000000001111100011011011010100110110111 source: ; set pin AM1 HIGH source: 1 changed: 1 step 33 100001100000000000000000000000000001111100011011011010100110110111 source: ; set pin AE1 HIGH source: 1 changed: 1 step 34 100001100100000000000000000000000001111100011011011010100110110111 source: ; set pin AM2 HIGH source: 1 changed: 1 step 35 100001100110000000000000000000000001111100011011011010100110110111 source: ; set pin AB2 HIGH source: 1 changed: 1 step 36 100001100110100000000000000000000001111100011011011010100110110111 source: ; set pin AS1 HIGH source: 1 changed: 1 step 37 100001100110100100000000000000000001111100011011011010100110110111 source: ; set pin BE1 HIGH source: 1 changed: 1 step 38 100001100110100100010000000000000001111100011011011010100110110111 source: ; set pin BM1 HIGH source: 1 changed: 1 step 39 100001100110100100011000000000000001111100011011011010100110110111 source: ; set pin BH1 HIGH source: 1 changed: 1 step 40 100001100110100100011010000000000001111100011011011010100110110111 source: ; set pin BR1 HIGH source: 1 changed: 1 step 41 100001100110100100011011000000000001111100011011011010100110110111 source: ; set pin BC1 HIGH source: 1 changed: 1 step 42 100001100110100100011011010000000001111100011011011010100110110111 source: ; set pin BJ2 HIGH source: 1 changed: 1 step 43 100001100110100100011011011000000001111100011011011010100110110111 source: ; set pin BJ1 HIGH source: 1 changed: 1 step 44 100001100110100100011011011010000001111100011011011010100110110111 source: ; set pin BK2 HIGH source: 1 changed: 1 step 45 100001100110100100011011011011000001111100011011011010100110110111 source: ; set pin BH2 HIGH source: 1 changed: 1 step 46 100001100110100100011011011011010001111100011011011010100110110111 source: ; set pin BP2 HIGH source: 1 changed: 1 step 47 100001100110100100011011011011011001111100011011011010100110110111 source: ; set pin BN2 HIGH source: 1 changed: 1 step 48 100001100110100100011011011011011101111100011011011010100110110111 source: ; toggle each ENABLE source: source: ; set pin AL2 to clear pin BB2 and pin AN2 AND-NOR OUTPUTS and set TAPE BUS 2 OUTPUT and TAPE BUS 3 OUTPUT source: 1 0 0 11 changed: 1 0 0 11 step 49 110001100110100100011011011011011100110111011011011010100110110111 source: 0 1 1 00 changed: 0 1 1 00 step 50 100001100110100100011011011011011101111100011011011010100110110111 source: ; set pin AP1 to clear pin BB2 and pin AN2 AND-NOR OUTPUTS and set TAPE BUS 2 OUTPUT and TAPE BUS 3 OUTPUT source: 1 0 0 11 changed: 1 0 0 11 step 51 101001100110100100011011011011011100110111011011011010100110110111 source: 0 1 1 00 changed: 0 1 1 00 step 52 100001100110100100011011011011011101111100011011011010100110110111 source: ; set pin AS2 to clear pin BB2 and pin AN2 AND-NOR OUTPUTS and set TAPE BUS 2 OUTPUT and TAPE BUS 3 OUTPUT source: 1 0 0 11 changed: 1 0 0 11 step 53 100101100110100100011011011011011100110111011011011010100110110111 source: 0 1 1 00 changed: 0 1 1 00 step 54 100001100110100100011011011011011101111100011011011010100110110111 source: ; set pin AL1 to clear pin BB2 and pin AN2 AND-NOR OUTPUTS and set TAPE BUS 2 OUTPUT and TAPE BUS 3 OUTPUT source: 1 0 0 11 changed: 1 0 0 11 step 55 100011100110100100011011011011011100110111011011011010100110110111 source: 0 1 1 00 changed: 0 1 1 00 step 56 100001100110100100011011011011011101111100011011011010100110110111 source: ; set pin AL1 to clear pin BB2 and pin AN2 AND-NOR OUTPUTS and set TAPE BUS 2 OUTPUT and TAPE BUS 3 OUTPUT source: 1 0 0 11 changed: 1 0 0 11 step 57 100001110110100100011011011011011100110111011011011010100110110111 source: 0 1 1 00 changed: 0 1 1 00 step 58 100001100110100100011011011011011101111100011011011010100110110111 source: ; set pin AE2 to clear pin BB2 and pin AN2 AND-NOR OUTPUTS and set TAPE BUS 2 OUTPUT and TAPE BUS 3 OUTPUT source: 1 0 0 11 changed: 1 0 0 11 step 59 100001101110100100011011011011011100110111011011011010100110110111 source: 0 1 1 00 changed: 0 1 1 00 step 60 100001100110100100011011011011011101111100011011011010100110110111 source: ; set pin AC1 to clear pin BB2 and set TAPE BUS 3 OUTPUT source: 1 0 1 changed: 1 0 1 step 61 100001100111100100011011011011011100111101011011011010100110110111 source: 0 1 0 changed: 0 1 0 step 62 100001100110100100011011011011011101111100011011011010100110110111 source: ; set pin AF1 to clear pin BB2 and set TAPE BUS 3 OUTPUT source: 1 0 1 changed: 1 0 1 step 63 100001100110110100011011011011011100111101011011011010100110110111 source: 0 1 0 changed: 0 1 0 step 64 100001100110100100011011011011011101111100011011011010100110110111 source: ; set pin AR2 to clear pin AN2 AND-NOR OUTPUTS and set TAPE BUS 2 OUTPUT source: 1 0 1 changed: 1 0 1 step 65 100001100110101100011011011011011101110110011011011010100110110111 source: 0 1 0 changed: 0 1 0 step 66 100001100110100100011011011011011101111100011011011010100110110111 source: ; set pin AP2 to clear pin AN2 AND-NOR OUTPUTS and set TAPE BUS 2 OUTPUT source: 1 0 1 changed: 1 0 1 step 67 100001100110100110011011011011011101110110011011011010100110110111 source: 0 1 0 changed: 0 1 0 step 68 100001100110100100011011011011011101111100011011011010100110110111 source: source: ; set pin BK1 to clear pin BB1 and pin BN1 AND-NOR OUTPUTS and set TAPE BUS 2 OUTPUT and TAPE BUS 3 OUTPUT source: 1 00 11 changed: 1 00 11 step 69 100001100110100101011011011011011101001111011011011010100110110111 source: 0 11 00 changed: 0 11 00 step 70 100001100110100100011011011011011101111100011011011010100110110111 source: ; set pin BL1 to clear pin BB1 and pin BN1 AND-NOR OUTPUTS and set TAPE BUS 2 OUTPUT and TAPE BUS 3 OUTPUT source: 1 00 11 changed: 1 00 11 step 71 100001100110100100111011011011011101001111011011011010100110110111 source: 0 11 00 changed: 0 11 00 step 72 100001100110100100011011011011011101111100011011011010100110110111 source: ; set pin BF1 to clear pin BB1 and pin BN1 AND-NOR OUTPUTS and set TAPE BUS 2 OUTPUT and TAPE BUS 3 OUTPUT source: 1 00 11 changed: 1 00 11 step 73 100001100110100100011111011011011101001111011011011010100110110111 source: 0 11 00 changed: 0 11 00 step 74 100001100110100100011011011011011101111100011011011010100110110111 source: ; set pin BS1 to clear pin BB1 and pin BN1 AND-NOR OUTPUTS and set TAPE BUS 2 OUTPUT and TAPE BUS 3 OUTPUT source: 1 00 11 changed: 1 00 11 step 75 100001100110100100011011111011011101001111011011011010100110110111 source: 0 11 00 changed: 0 11 00 step 76 100001100110100100011011011011011101111100011011011010100110110111 source: ; set pin BL2 to clear pin BB1 and pin BN1 AND-NOR OUTPUTS and set TAPE BUS 2 OUTPUT and TAPE BUS 3 OUTPUT source: 1 00 11 changed: 1 00 11 step 77 100001100110100100011011011111011101001111011011011010100110110111 source: 0 11 00 changed: 0 11 00 step 78 100001100110100100011011011011011101111100011011011010100110110111 source: ; set pin BU1 to clear pin BB1 and pin BN1 AND-NOR OUTPUTS and set TAPE BUS 2 OUTPUT and TAPE BUS 3 OUTPUT source: 1 00 11 changed: 1 00 11 step 79 100001100110100100011011011011111101001111011011011010100110110111 source: 0 11 00 changed: 0 11 00 step 80 100001100110100100011011011011011101111100011011011010100110110111 source: ; set pin BM2 to clear pin BB1 and TAPE BUS 3 OUTPUT source: 1 0 1 changed: 1 0 1 step 81 100001100110100100011011011011011111101110011011011010100110110111 source: 0 1 0 changed: 0 1 0 step 82 100001100110100100011011011011011101111100011011011010100110110111 source: ; no change source: 100000000000000000000000000000000001111100011011011010100110110111 changed: 00 00 0 0 00 00 00 00 000 step 83 100000000000000000000000000000000001111100011011011010100110110111 source: source: ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; source: ; test shifting the RWB source: ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; source: source: ; shift in 0, expect 10 source: 0 changed: 0 step 84 100000000000000000000000000000000001111100011011011010100110100111 source: 110 changed: 1 0 step 85 100000000000000000000000000000000001111100011011011010100110101101 source: 0 changed: 0 step 86 100000000000000000000000000000000001111100011011011010100110100101 source: ; toggle phase should toggle RWB 2 source: 0 0 changed: 0 0 step 87 100000000000000000000000000000000001111100011011011010100110000001 source: 1 1 changed: 1 1 step 88 100000000000000000000000000000000001111100011011011010100110100101 source: source: ; shift in 0, expect 00 source: 0 changed: step 89 100000000000000000000000000000000001111100011011011010100110100101 source: 100 changed: 10 step 90 100000000000000000000000000000000001111100011011011010100110101001 source: 0 changed: 0 step 91 100000000000000000000000000000000001111100011011011010100110100001 source: ; toggle phase should toggle RWB 2 source: 0 1 changed: 0 1 step 92 100000000000000000000000000000000001111100011011011010100110000101 source: 1 0 changed: 1 0 step 93 100000000000000000000000000000000001111100011011011010100110100001 source: source: ; shift in 0, expect 00 source: 0 changed: step 94 100000000000000000000000000000000001111100011011011010100110100001 source: 100 changed: 1 step 95 100000000000000000000000000000000001111100011011011010100110101001 source: 0 changed: 0 step 96 100000000000000000000000000000000001111100011011011010100110100001 source: ; shift in 1, expect 01 source: 1 changed: 1 step 97 100000000000000000000000000000000001111100011011011010100110110001 source: 101 changed: 1 1 step 98 100000000000000000000000000000000001111100011011011010100110111011 source: 0 changed: 0 step 99 100000000000000000000000000000000001111100011011011010100110110011 source: ; shift in 1, expect 11 source: 1 changed: step 100 100000000000000000000000000000000001111100011011011010100110110011 source: 111 changed: 11 step 101 100000000000000000000000000000000001111100011011011010100110111111 source: 0 changed: 0 step 102 100000000000000000000000000000000001111100011011011010100110110111 source: ; shift in 1, expect 11 source: 1 changed: step 103 100000000000000000000000000000000001111100011011011010100110110111 source: 111 changed: 1 step 104 100000000000000000000000000000000001111100011011011010100110111111 source: 0 changed: 0 step 105 100000000000000000000000000000000001111100011011011010100110110111 source: ; shift in 0, expect 10 source: 0 changed: 0 step 106 100000000000000000000000000000000001111100011011011010100110100111 source: 110 changed: 1 0 step 107 100000000000000000000000000000000001111100011011011010100110101101 source: 0 changed: 0 step 108 100000000000000000000000000000000001111100011011011010100110100101 source: ; shift in 1, expect 01 source: 1 changed: 1 step 109 100000000000000000000000000000000001111100011011011010100110110101 source: 101 changed: 101 step 110 100000000000000000000000000000000001111100011011011010100110111011 source: 0 changed: 0 step 111 100000000000000000000000000000000001111100011011011010100110110011 source: ; shift in 0, expect 10 source: 0 changed: 0 step 112 100000000000000000000000000000000001111100011011011010100110100011 source: 110 changed: 110 step 113 100000000000000000000000000000000001111100011011011010100110101101 source: 0 changed: 0 step 114 100000000000000000000000000000000001111100011011011010100110100101 source: ; shift in 1, expect 01 source: 0 changed: step 115 100000000000000000000000000000000001111100011011011010100110100101 SLOT BAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBAABBAAAAAAAAAAAAAABBBBBABBBB LETTER ALPSLFMDEEMCBFRSPKLEMFHRSCJLJKUHPNMBBNNVVRKRHUTDJUKANJHBTPDFSVEVDU SIDE 121212122121212121111111112212122222112222111221112112212112212122 DIRECTION IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIOOOOOOOIOOIOOIOOIOOOOIOOIIIIOOO source: 101 changed: 10 step 116 100000000000000000000000000000000001111100011011011010100110101001 fail ^ space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C toggle comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT BAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBAABBAAAAAAAAAAAAAABBBBBABBBB LETTER ALPSLFMDEEMCBFRSPKLEMFHRSCJLJKUHPNMBBNNVVRKRHUTDJUKANJHBTPDFSVEVDU SIDE 121212122121212121111111112212122222112222111221112112212112212122 DIRECTION IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIOOOOOOOIOOIOOIOOIOOOOIOOIIIIOOO all fails I I I O OO was lo 00000000000000000000000000000000000000 0000000000000000000000000 falling vvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvv vvvvvvvvvvvvvvvvvvvvvvvvv rising ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ ^^^^^^^^^^^^^^^^^^^^^^^^^ was hi 111111111111111111111111111111111111111111111111111111111111111111 total fails 34, total passes 0 Main menu Thu Aug 20 16:38:02 2015 test file is: tests\m222.new delay is: 0 trigger is: 1 1 read test file 2 set test delay 3 set test trigger 4 run test 5 output loading test 8 diags 9 exit Enter test file name? trying to open test file: tests\m222.new reading test file: tests\m222.new comment: M222 PCB REV B SCHEMATIC REV A LINC TAPE REGISTERS comment: comment: TERMINOLOGY- SIGNALS REFER TO VOL4 M222 SCHEMATIC. comment: comment: BUT... comment: comment: DEC USES AND-NOR GATES TO ROUTE THE ADDER A AND B INPUTS, SO... comment: DEC RENAMED THE ADDER TO NEGATIVE LOGIC TERMS (I.E. A-N + B-N + C-N -> SUM-N, C1-N). comment: (NOT THE 7482 DATASHEET NAMES OF A + B + C -> SUM, C1). comment: comment: SO, WITH ALL 'AND ENABLES' LOW, THE AND-NOR OUTPUTS = HIGH. comment: WITH C-L HIGH, THE ADDER OUTPUT IS SUM-N=1, C1-N=1; comment: THE INVERTED ADDER OUTPUT IS LOW (TAPE BUS). comment: AND THERE IS NO CARRY (C1-N IS HI). comment: comment: THE TWO ADDERS, TWO REGISTER BITS, ETC ARE LABELED BIT 2 (EVEN, MSB) AND BIT 3 (ODD, LSB). comment: THE ADDERS ARE REFERRED TO AS 'ADDER2' (MSB) AND 'ADDER3' (LSB). comment: comment: POWER PINS: comment: AA2 +5V comment: AT1 GROUND comment: AC2 GROUND comment: BA2 +5V comment: BT1 GROUND comment: BC2 GROUND comment: comment: (ALL PINS ARE USED). comment: comment: pins: PINS pins: 1 I BA1 CARRY IN-N, (TO E9-5 7482 C0) C-N TO ADDER2 pins: 2 I AL2 AND-NOR ENABLE: TAC TAC3 TO PIN BB2 (TO ADDER3) TAC2 TO PIN AN2 (TO ADDER2) pins: 3 I AP1 AND-NOR ENABLE: TMA SETUP (TMAS)3 TO PIN BB2 (TO ADDER3), (TMAS)3 TO PIN AN2 (TO ADDER2) pins: 4 I AS2 AND-NOR ENABLE: TMA TMA3 TO PIN BB2 (TO ADDER3), TMA2 TO PIN AN2 (TO ADDER2) pins: 5 I AL1 AND-NOR ENABLE: PIN AF2 TO PIN BB2 (TO ADDER3), PIN AM1 TO PIN AN2 (TO ADDER2) pins: 6 I AF2 AND-NOR INPUT (AL1 ENABLES) TO PIN BB2 (TO ADDER3). pins: 7 I AM1 AND-NOR INPUT (AL1 ENABLES) TO PIN AN2 (TO ADDER2) pins: 8 I AD2 AND-NOR ENABLE: RWB RWB3 TO PIN BB2 (TO ADDER3), RWB2 TO PIN AN2 (TO ADDER2) pins: 9 I AE2 AND-NOR ENABLE: PIN AE1 TO PIN BB2 (TO ADDER3), PIN AM2 TO PIN AN2 (TO ADDER2) pins: 10 I AE1 AND-NOR INPUT (AE2 ENABLES) TO PIN BB2 (TO ADDER3). pins: 11 I AM2 AND-NOR INPUT (AE2 ENABLES) TO PIN AN2 (TO ADDER2) pins: 12 I AC1 AND-NOR INPUT, AND WITH PIN AB2 TO PIN BB2 (TO ADDER3) pins: 13 I AB2 AND-NOR INPUT, AND WITH PIN AC1 TO PIN BB2 (TO ADDER3) pins: 14 I AF1 AND-NOR INPUT (AND WITH ITSELF) TO PIN BB2 (TO ADDER3) pins: 15 I AR2 AND-NOR INPUT, AND WITH PIN AS1 TO PIN AN2 (TO ADDER2) pins: 16 I AS1 AND-NOR INPUT, AND WITH PIN AR2 TO PIN AN2 (TO ADDER2) pins: 17 I AP2 AND-NOR INPUT (AND WITH ITSELF) TO PIN AN2 (TO ADDER2) pins: 18 I BK1 AND-NOR ENABLE: TB3 TO PIN BB1 (TO ADDER3), TB2 TO PIN BN1 (TO ADDER2) pins: 19 I BL1 AND-NOR ENABLE: PIN BE1 TO PIN BB1 (TO ADDER3), PIN BM1 TO PIN BN1 (TO ADDER2) pins: 20 I BE1 AND-NOR INPUT (BL1 ENABLES) TO PIN BB1 (TO ADDER3). pins: 21 I BM1 AND-NOR INPUT (BL1 ENABLES) TO PIN BN1 (TO ADDER2) pins: 22 I BF1 AND-NOR ENABLE: PIN BH1 TO PIN BB1 (TO ADDER3), PIN BR1 TO PIN BN1 (TO ADDER2) pins: 23 I BH1 AND-NOR INPUT (BF1 ENABLES): TO PIN BB1 (TO ADDER3), pins: 24 I BR1 AND-NOR INPUT (BF1 ENABLES): TO PIN BN1 (TO ADDER2) pins: 25 I BS1 AND-NOR ENABLE: PIN BC1 TO PIN BB1 (TO ADDER3), PIN BJ2 TO PIN BN1 (TO ADDER2) pins: 26 I BC1 AND-NOR INPUT (BS1 ENABLES): TO PIN BB1 (TO ADDER3), pins: 27 I BJ2 AND-NOR INPUT (BS1 ENABLES): TO PIN BN1 (TO ADDER2) pins: 28 I BL2 AND-NOR ENABLE: PIN BJ1 TO PIN BB1 (TO ADDER3), PIN BK2 TO PIN BN1 (TO ADDER2) pins: 29 I BJ1 AND-NOR INPUT (BL2 ENABLES): TO PIN BB1 (TO ADDER3), pins: 30 I BK2 AND-NOR INPUT (BL2 ENABLES): TO PIN BN1 (TO ADDER2) pins: 31 I BU1 AND-NOR ENABLE: PIN BH2 TO PIN BB1 (TO ADDER3), PIN BP2 TO PIN BN1 (TO ADDER2) pins: 32 I BH2 AND-NOR INPUT (BU1 ENABLES): TO PIN BB1 (TO ADDER3), pins: 33 I BP2 AND-NOR INPUT (BU1 ENABLES): TO PIN BN1 (TO ADDER2) pins: 34 I BN2 AND-NOR INPUT (AND WITH BM2): TO PIN BN1 (TO ADDER2) pins: 35 I BM2 AND-NOR INPUT (AND WITH BM2): TO PIN BN1 (TO ADDER2) pins: 36 O BB2 AND-NOR OUTPUT, (DRIVES E9-2 7482 A1) TO ADDER3 INPUT pins: 37 O BB1 AND-NOR OUTPUT, (DRIVES E9-3 7482 B1) TO ADDER3 INPUT pins: 38 O BN1 AND-NOR OUTPUT, (DRIVES E9-14 7482 A2) TO ADDER2 INPUT pins: 39 O AN2 AND-NOR OUTPUT, (DRIVES E9-13 7482 B2) TO ADDER2 INPUT pins: 40 O AV2 CARRY OUT-N (E9-10 7482 C2) pins: 41 O BV2 TAPE BUS 2 OUTPUT (INVERTED ADDER2 SUM-N (E9-12 7482 SUM2) pins: 42 O BR2 TAPE BUS 3 OUTPUT (INVERTED ADDER3 SUM-N (E9-1 7482 SUM1) pins: 43 I AK1 LOAD TMA SETUP (FROM TAPE BUS) (RISING EDGE CLOCK) pins: 44 O AR1 TMA SETUP 2 pins: 45 O AH1 TMA SETUP 3 pins: 46 I AU2 LOAD TMA (FROM TAPE BUS) (RISING EDGE CLOCK) pins: 47 O AT2 TMA 2 pins: 48 O AD1 TMA 3 pins: 49 I AJ1 LOAD TBN (FROM TAPE BUS) (RISING EDGE CLOCK) pins: 50 O AU1 TBN 2 pins: 51 O AK2 TBN 3 pins: 52 I AA1 LOAD TAC (FROM TAPE BUS) (RISING EDGE CLOCK) pins: 53 O AN1 TAC 2 pins: 54 O AJ2 TAC 2-N pins: 55 O AH2 TAC 3 pins: 56 O AB1 TAC 3-N pins: 57 I BT2 LOAD TB (FROM TAPE BUS) (RISING EDGE CLOCK) pins: 58 O BP1 TB 2 pins: 59 O BD1 TB 3 pins: 60 I BF2 LOAD RWB (FROM TB) (JAMS CLEAR,SET) pins: 61 I BS2 PHASE (SELECTS POLARITY OF RWB OUT, 0 -> INVERTED) pins: 62 I AV1 RWB IN (SHIFTED INTO RWB 3) pins: 63 I BE2 SHIFT RWB (SHIFTS PIN AV1 INTO RWB 3, SHIFTS RWB3 TO RWB2) (RISING CLOCK) pins: 64 O BV1 RWB OUT (IF PHASE=1, =RWB 2; IF PHASE=0; =RWB 2-N) pins: 65 O BD2 RWB 3 pins: 66 O BU2 +3.5V pins: direction: IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIOOOOOOOIOOIOOIOOIOOOOIOOIIIIOOO comment: ; all registers are unknown comment: ; turn on C0, PHASE comment: ; with no ENABLES, BUS2,BUS3 is 11, C2 is 1 test 1: 1000000000000000000000000000000000011111000XX0XX0XX0XXXX0XX0110XX1 comment: comment: ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; comment: ; comment: ; set all registers LOW comment: ; comment: ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; comment: comment: ; load TMA SETUP from tape bus (00) test 2: 100 test 3: 0 comment: ; load TMA from tape bus (00) test 4: 100 test 5: 0 comment: ; load TBN from tape bus (00) test 6: 100 test 7: 0 comment: ; load TAC from tape bus (00) test 8: 10101 test 9: 0 comment: ; load TB from tape bus (00) test 10: 100 test 11: 0 comment: ; load RWB from TB (JAMS CLEAR AND PRESET) test 12: 1 00 test 13: 0 comment: ; (no change) test 14: 100000000000000000000000000000000001111100000000000001010000110001 comment: comment: comment: ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; comment: ; comment: ; set all registers HIGH comment: ; comment: ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; comment: comment: ; set pin AF1 (AND with itself) to clear pin BB2 (AND-NOR output) and set pin BR2 TAPE BUS 3 OUTPUT test 15: 1 0 1 comment: ; set pin AP2 (AND with itself) to clear pin AN2 (AND-NOR output) and set pin BV2 TAPE BUS 2 OUTPUT test 16: 1 0 1 comment: comment: comment: ; load TMA SETUP from tape bus (11) test 17: 111 test 18: 0 comment: ; load TMA from tape bus (11) test 19: 111 test 20: 0 comment: ; load TBN from tape bus (11) test 21: 111 test 22: 0 comment: ; load TAC from tape bus (11) test 23: 11010 test 24: 0 comment: ; load TB from tape bus (11) test 25: 111 test 26: 0 comment: ; load RWB from TB (JAMS CLEAR AND PRESET) test 27: 1 11 test 28: 0 comment: ; clear pin AF1 (AND with itself) to set pin BB2 (AND-NOR output) and clear pin BR2 TAPE BUS 3 OUTPUT test 29: 0 1 0 comment: ; clear pin AP2 (AND with itself) to set pin AN2 (AND-NOR output) and clear pin BV2 TAPE BUS 2 OUTPUT test 30: 0 1 0 comment: ; (no change) test 31: 100000000000000000000000000000000001111100011011011010100110110111 comment: comment: comment: ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; comment: ; comment: ; test AND-NOR logic comment: ; comment: ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; comment: comment: ; (all registers are HIGH) comment: ; set all pins HIGH except ENABLES comment: comment: ; set pin AF2 HIGH test 32: 1 comment: ; set pin AM1 HIGH test 33: 1 comment: ; set pin AE1 HIGH test 34: 1 comment: ; set pin AM2 HIGH test 35: 1 comment: ; set pin AB2 HIGH test 36: 1 comment: ; set pin AS1 HIGH test 37: 1 comment: ; set pin BE1 HIGH test 38: 1 comment: ; set pin BM1 HIGH test 39: 1 comment: ; set pin BH1 HIGH test 40: 1 comment: ; set pin BR1 HIGH test 41: 1 comment: ; set pin BC1 HIGH test 42: 1 comment: ; set pin BJ2 HIGH test 43: 1 comment: ; set pin BJ1 HIGH test 44: 1 comment: ; set pin BK2 HIGH test 45: 1 comment: ; set pin BH2 HIGH test 46: 1 comment: ; set pin BP2 HIGH test 47: 1 comment: ; set pin BN2 HIGH test 48: 1 comment: ; toggle each ENABLE comment: comment: ; set pin AL2 to clear pin BB2 and pin AN2 AND-NOR OUTPUTS and set TAPE BUS 2 OUTPUT and TAPE BUS 3 OUTPUT test 49: 1 0 0 11 test 50: 0 1 1 00 comment: ; set pin AP1 to clear pin BB2 and pin AN2 AND-NOR OUTPUTS and set TAPE BUS 2 OUTPUT and TAPE BUS 3 OUTPUT test 51: 1 0 0 11 test 52: 0 1 1 00 comment: ; set pin AS2 to clear pin BB2 and pin AN2 AND-NOR OUTPUTS and set TAPE BUS 2 OUTPUT and TAPE BUS 3 OUTPUT test 53: 1 0 0 11 test 54: 0 1 1 00 comment: ; set pin AL1 to clear pin BB2 and pin AN2 AND-NOR OUTPUTS and set TAPE BUS 2 OUTPUT and TAPE BUS 3 OUTPUT test 55: 1 0 0 11 test 56: 0 1 1 00 comment: ; set pin AL1 to clear pin BB2 and pin AN2 AND-NOR OUTPUTS and set TAPE BUS 2 OUTPUT and TAPE BUS 3 OUTPUT test 57: 1 0 0 11 test 58: 0 1 1 00 comment: ; set pin AE2 to clear pin BB2 and pin AN2 AND-NOR OUTPUTS and set TAPE BUS 2 OUTPUT and TAPE BUS 3 OUTPUT test 59: 1 0 0 11 test 60: 0 1 1 00 comment: ; set pin AC1 to clear pin BB2 and set TAPE BUS 3 OUTPUT test 61: 1 0 1 test 62: 0 1 0 comment: ; set pin AF1 to clear pin BB2 and set TAPE BUS 3 OUTPUT test 63: 1 0 1 test 64: 0 1 0 comment: ; set pin AR2 to clear pin AN2 AND-NOR OUTPUTS and set TAPE BUS 2 OUTPUT test 65: 1 0 1 test 66: 0 1 0 comment: ; set pin AP2 to clear pin AN2 AND-NOR OUTPUTS and set TAPE BUS 2 OUTPUT test 67: 1 0 1 test 68: 0 1 0 comment: comment: ; set pin BK1 to clear pin BB1 and pin BN1 AND-NOR OUTPUTS and set TAPE BUS 2 OUTPUT and TAPE BUS 3 OUTPUT test 69: 1 00 11 test 70: 0 11 00 comment: ; set pin BL1 to clear pin BB1 and pin BN1 AND-NOR OUTPUTS and set TAPE BUS 2 OUTPUT and TAPE BUS 3 OUTPUT test 71: 1 00 11 test 72: 0 11 00 comment: ; set pin BF1 to clear pin BB1 and pin BN1 AND-NOR OUTPUTS and set TAPE BUS 2 OUTPUT and TAPE BUS 3 OUTPUT test 73: 1 00 11 test 74: 0 11 00 comment: ; set pin BS1 to clear pin BB1 and pin BN1 AND-NOR OUTPUTS and set TAPE BUS 2 OUTPUT and TAPE BUS 3 OUTPUT test 75: 1 00 11 test 76: 0 11 00 comment: ; set pin BL2 to clear pin BB1 and pin BN1 AND-NOR OUTPUTS and set TAPE BUS 2 OUTPUT and TAPE BUS 3 OUTPUT test 77: 1 00 11 test 78: 0 11 00 comment: ; set pin BU1 to clear pin BB1 and pin BN1 AND-NOR OUTPUTS and set TAPE BUS 2 OUTPUT and TAPE BUS 3 OUTPUT test 79: 1 00 11 test 80: 0 11 00 comment: ; set pin BM2 to clear pin BB1 and TAPE BUS 3 OUTPUT test 81: 1 0 1 test 82: 0 1 0 comment: ; no change test 83: 100000000000000000000000000000000001111100011011011010100110110111 comment: comment: ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; comment: ; test shifting the RWB comment: ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; comment: comment: ; shift in 0, expect 10 test 84: 0 test 85: 110 test 86: 0 comment: ; toggle phase should toggle RWB 2 test 87: 0 0 test 88: 1 1 comment: comment: ; shift in 0, expect 00 test 89: 0 test 90: 100 test 91: 0 comment: ; toggle phase should toggle RWB 2 test 92: 0 1 test 93: 1 0 comment: comment: ; shift in 0, expect 00 test 94: 0 test 95: 100 test 96: 0 comment: ; shift in 1, expect 01 test 97: 1 test 98: 101 test 99: 0 comment: ; shift in 1, expect 11 test 100: 1 test 101: 111 test 102: 0 comment: ; shift in 1, expect 11 test 103: 1 test 104: 111 test 105: 0 comment: ; shift in 0, expect 10 test 106: 0 test 107: 110 test 108: 0 comment: ; shift in 1, expect 01 test 109: 1 test 110: 101 test 111: 0 comment: ; shift in 0, expect 10 test 112: 0 test 113: 110 test 114: 0 comment: ; shift in 1, expect 01 test 115: 1 test 116: 101 test 117: 0 comment: ; shift in 1, expect 10 test 118: 1 test 119: 110 test 120: 0 comment: ; shift in 1, expect 11 test 121: 1 test 122: 111 test 123: 0 comment: ; no change test 124: 100000000000000000000000000000000001111100011011011010100110110111 comment: comment: ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; comment: ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; comment: ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; comment: ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; comment: ; needs work (more adder tests, more register tests) comment: ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; comment: ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; comment: ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; comment: ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; end: END summary column 1: offset 2, mask 0x2000 column 2: offset 1, mask 0x0002 column 3: offset 1, mask 0x0800 column 4: offset 1, mask 0x0040 column 5: offset 1, mask 0x4000 column 6: offset 0, mask 0x0004 column 7: offset 1, mask 0x2000 column 8: offset 0, mask 0x0010 column 9: offset 0, mask 0x0008 column 10: offset 0, mask 0x0800 column 11: offset 1, mask 0x0004 column 12: offset 0, mask 0x2000 column 13: offset 0, mask 0x0040 column 14: offset 0, mask 0x0400 column 15: offset 1, mask 0x0020 column 16: offset 1, mask 0x0200 column 17: offset 1, mask 0x0010 column 18: offset 3, mask 0x2000 column 19: offset 3, mask 0x1000 column 20: offset 2, mask 0x0200 column 21: offset 3, mask 0x0800 column 22: offset 2, mask 0x0100 column 23: offset 3, mask 0x8000 column 24: offset 3, mask 0x0100 column 25: offset 4, mask 0x8000 column 26: offset 2, mask 0x0800 column 27: offset 3, mask 0x0002 column 28: offset 3, mask 0x0008 column 29: offset 3, mask 0x4000 column 30: offset 3, mask 0x0004 column 31: offset 4, mask 0x2000 column 32: offset 3, mask 0x0001 column 33: offset 3, mask 0x0040 column 34: offset 3, mask 0x0020 column 35: offset 3, mask 0x0010 column 36: offset 2, mask 0x0008 column 37: offset 2, mask 0x1000 column 38: offset 3, mask 0x0400 column 39: offset 1, mask 0x0008 column 40: offset 2, mask 0x0002 column 41: offset 4, mask 0x0008 column 42: offset 3, mask 0x0080 column 43: offset 1, mask 0x8000 column 44: offset 1, mask 0x0400 column 45: offset 0, mask 0x0200 column 46: offset 2, mask 0x0001 column 47: offset 1, mask 0x0080 column 48: offset 0, mask 0x1000 column 49: offset 0, mask 0x0100 column 50: offset 2, mask 0x8000 column 51: offset 1, mask 0x0001 column 52: offset 0, mask 0x8000 column 53: offset 1, mask 0x1000 column 54: offset 0, mask 0x0001 column 55: offset 0, mask 0x0002 column 56: offset 0, mask 0x4000 column 57: offset 4, mask 0x0002 column 58: offset 3, mask 0x0200 column 59: offset 2, mask 0x0400 column 60: offset 2, mask 0x0080 column 61: offset 4, mask 0x0001 column 62: offset 2, mask 0x4000 column 63: offset 2, mask 0x0040 column 64: offset 4, mask 0x1000 column 65: offset 2, mask 0x0020 column 66: offset 4, mask 0x0004 direction bits (1=input) 0x52A3 0x1589 0x943A 0x0680 0x50FC pullup bits (1=pullup) 0x0000 0x0000 0x0000 0x0000 0x0000 test step out_data dont care 1: 0x0000 0x0008 0x700A 0x0400 0x0005 0x5203 0x1481 0x8420 0x0200 0x1000 2: 0x0000 0x8008 0x700A 0x0400 0x0005 0x5003 0x1081 0x8420 0x0200 0x1000 3: 0x0000 0x0008 0x700A 0x0400 0x0005 0x5003 0x1081 0x8420 0x0200 0x1000 4: 0x0000 0x0008 0x700B 0x0400 0x0005 0x4003 0x1001 0x8420 0x0200 0x1000 5: 0x0000 0x0008 0x700A 0x0400 0x0005 0x4003 0x1001 0x8420 0x0200 0x1000 6: 0x0100 0x0008 0x700A 0x0400 0x0005 0x4003 0x1000 0x0420 0x0200 0x1000 7: 0x0000 0x0008 0x700A 0x0400 0x0005 0x4003 0x1000 0x0420 0x0200 0x1000 8: 0xC001 0x0008 0x700A 0x0400 0x0005 0x0000 0x0000 0x0420 0x0200 0x1000 9: 0x4001 0x0008 0x700A 0x0400 0x0005 0x0000 0x0000 0x0420 0x0200 0x1000 10: 0x4001 0x0008 0x700A 0x0400 0x0007 0x0000 0x0000 0x0020 0x0000 0x1000 11: 0x4001 0x0008 0x700A 0x0400 0x0005 0x0000 0x0000 0x0020 0x0000 0x1000 12: 0x4001 0x0008 0x708A 0x0400 0x0005 13: 0x4001 0x0008 0x700A 0x0400 0x0005 14: 0x4001 0x0008 0x700A 0x0400 0x0005 15: 0x4401 0x0008 0x7002 0x0480 0x0005 16: 0x4401 0x0010 0x7002 0x0480 0x000D 17: 0x4601 0x8410 0x7002 0x0480 0x000D 18: 0x4601 0x0410 0x7002 0x0480 0x000D 19: 0x5601 0x0490 0x7003 0x0480 0x000D 20: 0x5601 0x0490 0x7002 0x0480 0x000D 21: 0x5701 0x0491 0xF002 0x0480 0x000D 22: 0x5601 0x0491 0xF002 0x0480 0x000D 23: 0x9602 0x1491 0xF002 0x0480 0x000D 24: 0x1602 0x1491 0xF002 0x0480 0x000D 25: 0x1602 0x1491 0xF402 0x0680 0x000F 26: 0x1602 0x1491 0xF402 0x0680 0x000D 27: 0x1602 0x1491 0xF4A2 0x0680 0x100D 28: 0x1602 0x1491 0xF422 0x0680 0x100D 29: 0x1202 0x1491 0xF42A 0x0600 0x100D 30: 0x1202 0x1489 0xF42A 0x0600 0x1005 31: 0x1202 0x1489 0xF42A 0x0600 0x1005 32: 0x1206 0x1489 0xF42A 0x0600 0x1005 33: 0x1206 0x3489 0xF42A 0x0600 0x1005 34: 0x1A06 0x3489 0xF42A 0x0600 0x1005 35: 0x1A06 0x348D 0xF42A 0x0600 0x1005 36: 0x1A46 0x348D 0xF42A 0x0600 0x1005 37: 0x1A46 0x368D 0xF42A 0x0600 0x1005 38: 0x1A46 0x368D 0xF62A 0x0600 0x1005 39: 0x1A46 0x368D 0xF62A 0x0E00 0x1005 40: 0x1A46 0x368D 0xF62A 0x8E00 0x1005 41: 0x1A46 0x368D 0xF62A 0x8F00 0x1005 42: 0x1A46 0x368D 0xFE2A 0x8F00 0x1005 43: 0x1A46 0x368D 0xFE2A 0x8F02 0x1005 44: 0x1A46 0x368D 0xFE2A 0xCF02 0x1005 45: 0x1A46 0x368D 0xFE2A 0xCF06 0x1005 46: 0x1A46 0x368D 0xFE2A 0xCF07 0x1005 47: 0x1A46 0x368D 0xFE2A 0xCF47 0x1005 48: 0x1A46 0x368D 0xFE2A 0xCF67 0x1005 49: 0x1A46 0x3687 0xFE22 0xCFE7 0x100D 50: 0x1A46 0x368D 0xFE2A 0xCF67 0x1005 51: 0x1A46 0x3E85 0xFE22 0xCFE7 0x100D 52: 0x1A46 0x368D 0xFE2A 0xCF67 0x1005 53: 0x1A46 0x36C5 0xFE22 0xCFE7 0x100D 54: 0x1A46 0x368D 0xFE2A 0xCF67 0x1005 55: 0x1A46 0x7685 0xFE22 0xCFE7 0x100D 56: 0x1A46 0x368D 0xFE2A 0xCF67 0x1005 57: 0x1A56 0x3685 0xFE22 0xCFE7 0x100D 58: 0x1A46 0x368D 0xFE2A 0xCF67 0x1005 59: 0x1A4E 0x3685 0xFE22 0xCFE7 0x100D 60: 0x1A46 0x368D 0xFE2A 0xCF67 0x1005 61: 0x3A46 0x368D 0xFE22 0xCFE7 0x1005 62: 0x1A46 0x368D 0xFE2A 0xCF67 0x1005 63: 0x1E46 0x368D 0xFE22 0xCFE7 0x1005 64: 0x1A46 0x368D 0xFE2A 0xCF67 0x1005 65: 0x1A46 0x36A5 0xFE2A 0xCF67 0x100D 66: 0x1A46 0x368D 0xFE2A 0xCF67 0x1005 67: 0x1A46 0x3695 0xFE2A 0xCF67 0x100D 68: 0x1A46 0x368D 0xFE2A 0xCF67 0x1005 69: 0x1A46 0x368D 0xEE2A 0xEBE7 0x100D 70: 0x1A46 0x368D 0xFE2A 0xCF67 0x1005 71: 0x1A46 0x368D 0xEE2A 0xDBE7 0x100D 72: 0x1A46 0x368D 0xFE2A 0xCF67 0x1005 73: 0x1A46 0x368D 0xEF2A 0xCBE7 0x100D 74: 0x1A46 0x368D 0xFE2A 0xCF67 0x1005 75: 0x1A46 0x368D 0xEE2A 0xCBE7 0x900D 76: 0x1A46 0x368D 0xFE2A 0xCF67 0x1005 77: 0x1A46 0x368D 0xEE2A 0xCBEF 0x100D 78: 0x1A46 0x368D 0xFE2A 0xCF67 0x1005 79: 0x1A46 0x368D 0xEE2A 0xCBE7 0x300D 80: 0x1A46 0x368D 0xFE2A 0xCF67 0x1005 81: 0x1A46 0x368D 0xFE2A 0xCB77 0x100D 82: 0x1A46 0x368D 0xFE2A 0xCF67 0x1005 83: 0x1202 0x1489 0xF42A 0x0600 0x1005 84: 0x1202 0x1489 0xB42A 0x0600 0x1005 85: 0x1202 0x1489 0xB44A 0x0600 0x1005 86: 0x1202 0x1489 0xB40A 0x0600 0x1005 87: 0x1202 0x1489 0xB40A 0x0600 0x0004 88: 0x1202 0x1489 0xB40A 0x0600 0x1005 89: 0x1202 0x1489 0xB40A 0x0600 0x1005 90: 0x1202 0x1489 0xB44A 0x0600 0x0005 91: 0x1202 0x1489 0xB40A 0x0600 0x0005 92: 0x1202 0x1489 0xB40A 0x0600 0x1004 93: 0x1202 0x1489 0xB40A 0x0600 0x0005 94: 0x1202 0x1489 0xB40A 0x0600 0x0005 95: 0x1202 0x1489 0xB44A 0x0600 0x0005 96: 0x1202 0x1489 0xB40A 0x0600 0x0005 97: 0x1202 0x1489 0xF40A 0x0600 0x0005 98: 0x1202 0x1489 0xF46A 0x0600 0x0005 99: 0x1202 0x1489 0xF42A 0x0600 0x0005 100: 0x1202 0x1489 0xF42A 0x0600 0x0005 101: 0x1202 0x1489 0xF46A 0x0600 0x1005 102: 0x1202 0x1489 0xF42A 0x0600 0x1005 103: 0x1202 0x1489 0xF42A 0x0600 0x1005 104: 0x1202 0x1489 0xF46A 0x0600 0x1005 105: 0x1202 0x1489 0xF42A 0x0600 0x1005 106: 0x1202 0x1489 0xB42A 0x0600 0x1005 107: 0x1202 0x1489 0xB44A 0x0600 0x1005 108: 0x1202 0x1489 0xB40A 0x0600 0x1005 109: 0x1202 0x1489 0xF40A 0x0600 0x1005 110: 0x1202 0x1489 0xF46A 0x0600 0x0005 111: 0x1202 0x1489 0xF42A 0x0600 0x0005 112: 0x1202 0x1489 0xB42A 0x0600 0x0005 113: 0x1202 0x1489 0xB44A 0x0600 0x1005 114: 0x1202 0x1489 0xB40A 0x0600 0x1005 115: 0x1202 0x1489 0xF40A 0x0600 0x1005 116: 0x1202 0x1489 0xF46A 0x0600 0x0005 117: 0x1202 0x1489 0xF42A 0x0600 0x0005 118: 0x1202 0x1489 0xF42A 0x0600 0x0005 119: 0x1202 0x1489 0xF44A 0x0600 0x1005 120: 0x1202 0x1489 0xF40A 0x0600 0x1005 121: 0x1202 0x1489 0xF40A 0x0600 0x1005 122: 0x1202 0x1489 0xF46A 0x0600 0x1005 123: 0x1202 0x1489 0xF42A 0x0600 0x1005 124: 0x1202 0x1489 0xF42A 0x0600 0x1005 PINs used (in edge connector order) (G=ground,P=power) SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBB LETTER ABCDEFHJKLMNPRSTUVABCDEFHJKLMNPRSTUVABCDEFHJKLMNPRSTUVABCDEFHJKLMNPRSTUV SIDE 111111111111111111222222222222222222111111111111111111222222222222222222 USAGE IOIOIIOIIIIOIOIGOIPIGIIIOOOIIOIIIOIOIOIOIIIIIIIOOIIGIOPOGOIIIIIIIIIOIIOO UUT has 44 inputs UUT has 22 outputs contains 66 pins/columns 0 pins are not used contains 124 'test steps' M222 PCB REV B SCHEMATIC REV A LINC TAPE REGISTERS TERMINOLOGY- SIGNALS REFER TO VOL4 M222 SCHEMATIC. BUT... DEC USES AND-NOR GATES TO ROUTE THE ADDER A AND B INPUTS, SO... DEC RENAMED THE ADDER TO NEGATIVE LOGIC TERMS (I.E. A-N + B-N + C-N -> SUM-N, C1-N). (NOT THE 7482 DATASHEET NAMES OF A + B + C -> SUM, C1). SO, WITH ALL 'AND ENABLES' LOW, THE AND-NOR OUTPUTS = HIGH. WITH C-L HIGH, THE ADDER OUTPUT IS SUM-N=1, C1-N=1; THE INVERTED ADDER OUTPUT IS LOW (TAPE BUS). AND THERE IS NO CARRY (C1-N IS HI). THE TWO ADDERS, TWO REGISTER BITS, ETC ARE LABELED BIT 2 (EVEN, MSB) AND BIT 3 (ODD, LSB). THE ADDERS ARE REFERRED TO AS 'ADDER2' (MSB) AND 'ADDER3' (LSB). POWER PINS: AA2 +5V AT1 GROUND AC2 GROUND BA2 +5V BT1 GROUND BC2 GROUND (ALL PINS ARE USED). PINS Main menu Thu Aug 20 16:38:09 2015 test file is: tests\m222.new delay is: 0 trigger is: 1 1 read test file 2 set test delay 3 set test trigger 4 run test 5 output loading test 8 diags 9 exit UUT power is okay Thu Aug 20 16:38:12 2015 space single step O run once (one test, all steps) F run, stop on fail G go (run tests N run, stop on fail, no print S scope (run, no print) C toggle comment printout + increase speed (less delay) - decrease speed (more delay)(slower) Q quit test scope (run, no print) FFFFFFFFFFFFFFFFFFFF space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C toggle comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit step 51 101001100110100100011011011011011100110111011011011010100110110111 step 52 100001100110100100011011011011011101111100011011011010100110110111 step 53 100101100110100100011011011011011100110111011011011010100110110111 step 54 100001100110100100011011011011011101111100011011011010100110110111 step 55 100011100110100100011011011011011100110111011011011010100110110111 step 56 100001100110100100011011011011011101111100011011011010100110110111 step 57 100001110110100100011011011011011100110111011011011010100110110111 step 58 100001100110100100011011011011011101111100011011011010100110110111 step 59 100001101110100100011011011011011100110111011011011010100110110111 step 60 100001100110100100011011011011011101111100011011011010100110110111 step 61 100001100111100100011011011011011100111101011011011010100110110111 step 62 100001100110100100011011011011011101111100011011011010100110110111 step 63 100001100110110100011011011011011100111101011011011010100110110111 step 64 100001100110100100011011011011011101111100011011011010100110110111 step 65 100001100110101100011011011011011101110110011011011010100110110111 step 66 100001100110100100011011011011011101111100011011011010100110110111 step 67 100001100110100110011011011011011101110110011011011010100110110111 step 68 100001100110100100011011011011011101111100011011011010100110110111 step 69 100001100110100101011011011011011101001111011011011010100110110111 step 70 100001100110100100011011011011011101111100011011011010100110110111 step 71 100001100110100100111011011011011101001111011011011010100110110111 step 72 100001100110100100011011011011011101111100011011011010100110110111 step 73 100001100110100100011111011011011101001111011011011010100110110111 step 74 100001100110100100011011011011011101111100011011011010100110110111 step 75 100001100110100100011011111011011101001111011011011010100110110111 step 76 100001100110100100011011011011011101111100011011011010100110110111 step 77 100001100110100100011011011111011101001111011011011010100110110111 step 78 100001100110100100011011011011011101111100011011011010100110110111 step 79 100001100110100100011011011011111101001111011011011010100110110111 step 80 100001100110100100011011011011011101111100011011011010100110110111 step 81 100001100110100100011011011011011111101110011011011010100110110111 step 82 100001100110100100011011011011011101111100011011011010100110110111 step 83 100000000000000000000000000000000001111100011011011010100110110111 step 84 100000000000000000000000000000000001111100011011011010100110100111 step 85 100000000000000000000000000000000001111100011011011010100110101101 step 86 100000000000000000000000000000000001111100011011011010100110100101 step 87 100000000000000000000000000000000001111100011011011010100110000001 step 88 100000000000000000000000000000000001111100011011011010100110100101 step 89 100000000000000000000000000000000001111100011011011010100110100101 step 90 100000000000000000000000000000000001111100011011011010100110101001 step 91 100000000000000000000000000000000001111100011011011010100110100001 step 92 100000000000000000000000000000000001111100011011011010100110000101 step 93 100000000000000000000000000000000001111100011011011010100110100001 step 94 100000000000000000000000000000000001111100011011011010100110100001 step 95 100000000000000000000000000000000001111100011011011010100110101001 step 96 100000000000000000000000000000000001111100011011011010100110100001 step 97 100000000000000000000000000000000001111100011011011010100110110001 step 98 100000000000000000000000000000000001111100011011011010100110111011 step 99 100000000000000000000000000000000001111100011011011010100110110011 step 100 100000000000000000000000000000000001111100011011011010100110110011 step 101 100000000000000000000000000000000001111100011011011010100110111111 step 102 100000000000000000000000000000000001111100011011011010100110110111 step 103 100000000000000000000000000000000001111100011011011010100110110111 step 104 100000000000000000000000000000000001111100011011011010100110111111 step 105 100000000000000000000000000000000001111100011011011010100110110111 step 106 100000000000000000000000000000000001111100011011011010100110100111 step 107 100000000000000000000000000000000001111100011011011010100110101101 step 108 100000000000000000000000000000000001111100011011011010100110100101 step 109 100000000000000000000000000000000001111100011011011010100110110101 step 110 100000000000000000000000000000000001111100011011011010100110111011 step 111 100000000000000000000000000000000001111100011011011010100110110011 step 112 100000000000000000000000000000000001111100011011011010100110100011 step 113 100000000000000000000000000000000001111100011011011010100110101101 step 114 100000000000000000000000000000000001111100011011011010100110100101 step 115 100000000000000000000000000000000001111100011011011010100110110101 step 116 100000000000000000000000000000000001111100011011011010100110111011 step 117 100000000000000000000000000000000001111100011011011010100110110011 step 118 100000000000000000000000000000000001111100011011011010100110110011 SLOT BAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBAABBAAAAAAAAAAAAAABBBBBABBBB LETTER ALPSLFMDEEMCBFRSPKLEMFHRSCJLJKUHPNMBBNNVVRKRHUTDJUKANJHBTPDFSVEVDU SIDE 121212122121212121111111112212122222112222111221112112212112212122 DIRECTION IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIOOOOOOOIOOIOOIOOIOOOOIOOIIIIOOO changed: 11 step 119 100000000000000000000000000000000001111100011011011010100110111111 fail ^ SLOT BAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBAABBAAAAAAAAAAAAAABBBBBABBBB LETTER ALPSLFMDEEMCBFRSPKLEMFHRSCJLJKUHPNMBBNNVVRKRHUTDJUKANJHBTPDFSVEVDU SIDE 121212122121212121111111112212122222112222111221112112212112212122 DIRECTION IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIOOOOOOOIOOIOOIOOIOOOOIOOIIIIOOO changed: 0 step 120 100000000000000000000000000000000001111100011011011010100110110111 fail ^ SLOT BAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBAABBAAAAAAAAAAAAAABBBBBABBBB LETTER ALPSLFMDEEMCBFRSPKLEMFHRSCJLJKUHPNMBBNNVVRKRHUTDJUKANJHBTPDFSVEVDU SIDE 121212122121212121111111112212122222112222111221112112212112212122 DIRECTION IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIOOOOOOOIOOIOOIOOIOOOOIOOIIIIOOO changed: step 121 100000000000000000000000000000000001111100011011011010100110110111 fail ^ step 122 100000000000000000000000000000000001111100011011011010100110111111 step 123 100000000000000000000000000000000001111100011011011010100110110111 step 124 100000000000000000000000000000000001111100011011011010100110110111 test 21: *** FAIL *************************** 3 steps failed SLOT BAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBAABBAAAAAAAAAAAAAABBBBBABBBB LETTER ALPSLFMDEEMCBFRSPKLEMFHRSCJLJKUHPNMBBNNVVRKRHUTDJUKANJHBTPDFSVEVDU SIDE 121212122121212121111111112212122222112222111221112112212112212122 DIRECTION IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIOOOOOOOIOOIOOIOOIOOOOIOOIIIIOOO this fail O all fails O was hi 111111111111111111111111111111111111111111111111111111111111111111 rising ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ ^^^^^^^^^^^^^^^^^^^^^^^^^ falling vvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvv vvvvvvvvvvvvvvvvvvvvvvvvv was lo 00000000000000000000000000000000000000 0000000000000000000000000 total fails 21, total passes 0 space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C toggle comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit comment_flag is 1 space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C toggle comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit source: ; all registers are unknown source: ; turn on C0, PHASE source: ; with no ENABLES, BUS2,BUS3 is 11, C2 is 1 source: 1000000000000000000000000000000000011111000XX0XX0XX0XXXX0XX0110XX1 changed: step 1 100000000000000000000000000000000001111100011011011010100110110111 source: source: ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; source: ; source: ; set all registers LOW source: ; source: ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; source: source: ; load TMA SETUP from tape bus (00) source: 100 changed: 100 step 2 100000000000000000000000000000000001111100100011011010100110110111 source: 0 changed: 0 step 3 100000000000000000000000000000000001111100000011011010100110110111 source: ; load TMA from tape bus (00) source: 100 changed: 100 step 4 100000000000000000000000000000000001111100000100011010100110110111 source: 0 changed: 0 step 5 100000000000000000000000000000000001111100000000011010100110110111 source: ; load TBN from tape bus (00) source: 100 changed: 100 step 6 100000000000000000000000000000000001111100000000100010100110110111 source: 0 changed: 0 step 7 100000000000000000000000000000000001111100000000000010100110110111 source: ; load TAC from tape bus (00) source: 10101 changed: 10101 step 8 100000000000000000000000000000000001111100000000000101010110110111 source: 0 changed: 0 step 9 100000000000000000000000000000000001111100000000000001010110110111 source: ; load TB from tape bus (00) source: 100 changed: 100 step 10 100000000000000000000000000000000001111100000000000001011000110111 source: 0 changed: 0 step 11 100000000000000000000000000000000001111100000000000001010000110111 source: ; load RWB from TB (JAMS CLEAR AND PRESET) source: 1 00 changed: 1 00 step 12 100000000000000000000000000000000001111100000000000001010001110001 source: 0 changed: 0 step 13 100000000000000000000000000000000001111100000000000001010000110001 source: ; (no change) source: 100000000000000000000000000000000001111100000000000001010000110001 changed: step 14 100000000000000000000000000000000001111100000000000001010000110001 source: source: source: ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; source: ; source: ; set all registers HIGH source: ; source: ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; source: source: ; set pin AF1 (AND with itself) to clear pin BB2 (AND-NOR output) and set pin BR2 TAPE BUS 3 OUTPUT source: 1 0 1 changed: 1 0 1 step 15 100000000000010000000000000000000000111101000000000001010000110001 source: ; set pin AP2 (AND with itself) to clear pin AN2 (AND-NOR output) and set pin BV2 TAPE BUS 2 OUTPUT source: 1 0 1 changed: 1 0 1 step 16 100000000000010010000000000000000000110111000000000001010000110001 source: source: source: ; load TMA SETUP from tape bus (11) source: 111 changed: 111 step 17 100000000000010010000000000000000000110111111000000001010000110001 source: 0 changed: 0 step 18 100000000000010010000000000000000000110111011000000001010000110001 source: ; load TMA from tape bus (11) source: 111 changed: 111 step 19 100000000000010010000000000000000000110111011111000001010000110001 source: 0 changed: 0 step 20 100000000000010010000000000000000000110111011011000001010000110001 source: ; load TBN from tape bus (11) source: 111 changed: 111 step 21 100000000000010010000000000000000000110111011011111001010000110001 source: 0 changed: 0 step 22 100000000000010010000000000000000000110111011011011001010000110001 source: ; load TAC from tape bus (11) source: 11010 changed: 11010 step 23 100000000000010010000000000000000000110111011011011110100000110001 source: 0 changed: 0 step 24 100000000000010010000000000000000000110111011011011010100000110001 source: ; load TB from tape bus (11) source: 111 changed: 111 step 25 100000000000010010000000000000000000110111011011011010101110110001 source: 0 changed: 0 step 26 100000000000010010000000000000000000110111011011011010100110110001 source: ; load RWB from TB (JAMS CLEAR AND PRESET) source: 1 11 changed: 1 11 step 27 100000000000010010000000000000000000110111011011011010100111110111 source: 0 changed: 0 step 28 100000000000010010000000000000000000110111011011011010100110110111 source: ; clear pin AF1 (AND with itself) to set pin BB2 (AND-NOR output) and clear pin BR2 TAPE BUS 3 OUTPUT source: 0 1 0 changed: 0 1 0 step 29 100000000000000010000000000000000001110110011011011010100110110111 source: ; clear pin AP2 (AND with itself) to set pin AN2 (AND-NOR output) and clear pin BV2 TAPE BUS 2 OUTPUT source: 0 1 0 changed: 0 1 0 step 30 100000000000000000000000000000000001111100011011011010100110110111 source: ; (no change) source: 100000000000000000000000000000000001111100011011011010100110110111 changed: step 31 100000000000000000000000000000000001111100011011011010100110110111 source: source: source: ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; source: ; source: ; test AND-NOR logic source: ; source: ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; source: source: ; (all registers are HIGH) source: ; set all pins HIGH except ENABLES source: source: ; set pin AF2 HIGH source: 1 changed: 1 step 32 100001000000000000000000000000000001111100011011011010100110110111 source: ; set pin AM1 HIGH source: 1 changed: 1 step 33 100001100000000000000000000000000001111100011011011010100110110111 source: ; set pin AE1 HIGH source: 1 changed: 1 step 34 100001100100000000000000000000000001111100011011011010100110110111 source: ; set pin AM2 HIGH source: 1 changed: 1 step 35 100001100110000000000000000000000001111100011011011010100110110111 source: ; set pin AB2 HIGH source: 1 changed: 1 step 36 100001100110100000000000000000000001111100011011011010100110110111 source: ; set pin AS1 HIGH source: 1 changed: 1 step 37 100001100110100100000000000000000001111100011011011010100110110111 source: ; set pin BE1 HIGH source: 1 changed: 1 step 38 100001100110100100010000000000000001111100011011011010100110110111 source: ; set pin BM1 HIGH source: 1 changed: 1 step 39 100001100110100100011000000000000001111100011011011010100110110111 source: ; set pin BH1 HIGH source: 1 changed: 1 step 40 100001100110100100011010000000000001111100011011011010100110110111 source: ; set pin BR1 HIGH source: 1 changed: 1 step 41 100001100110100100011011000000000001111100011011011010100110110111 source: ; set pin BC1 HIGH source: 1 changed: 1 step 42 100001100110100100011011010000000001111100011011011010100110110111 source: ; set pin BJ2 HIGH source: 1 changed: 1 step 43 100001100110100100011011011000000001111100011011011010100110110111 source: ; set pin BJ1 HIGH source: 1 changed: 1 step 44 100001100110100100011011011010000001111100011011011010100110110111 source: ; set pin BK2 HIGH source: 1 changed: 1 step 45 100001100110100100011011011011000001111100011011011010100110110111 source: ; set pin BH2 HIGH source: 1 changed: 1 step 46 100001100110100100011011011011010001111100011011011010100110110111 source: ; set pin BP2 HIGH source: 1 changed: 1 step 47 100001100110100100011011011011011001111100011011011010100110110111 source: ; set pin BN2 HIGH source: 1 changed: 1 step 48 100001100110100100011011011011011101111100011011011010100110110111 source: ; toggle each ENABLE source: source: ; set pin AL2 to clear pin BB2 and pin AN2 AND-NOR OUTPUTS and set TAPE BUS 2 OUTPUT and TAPE BUS 3 OUTPUT source: 1 0 0 11 changed: 1 0 0 11 step 49 110001100110100100011011011011011100110111011011011010100110110111 source: 0 1 1 00 changed: 0 1 1 00 step 50 100001100110100100011011011011011101111100011011011010100110110111 source: ; set pin AP1 to clear pin BB2 and pin AN2 AND-NOR OUTPUTS and set TAPE BUS 2 OUTPUT and TAPE BUS 3 OUTPUT source: 1 0 0 11 changed: 1 0 0 11 step 51 101001100110100100011011011011011100110111011011011010100110110111 source: 0 1 1 00 changed: 0 1 1 00 step 52 100001100110100100011011011011011101111100011011011010100110110111 source: ; set pin AS2 to clear pin BB2 and pin AN2 AND-NOR OUTPUTS and set TAPE BUS 2 OUTPUT and TAPE BUS 3 OUTPUT source: 1 0 0 11 changed: 1 0 0 11 step 53 100101100110100100011011011011011100110111011011011010100110110111 source: 0 1 1 00 changed: 0 1 1 00 step 54 100001100110100100011011011011011101111100011011011010100110110111 source: ; set pin AL1 to clear pin BB2 and pin AN2 AND-NOR OUTPUTS and set TAPE BUS 2 OUTPUT and TAPE BUS 3 OUTPUT source: 1 0 0 11 changed: 1 0 0 11 step 55 100011100110100100011011011011011100110111011011011010100110110111 source: 0 1 1 00 changed: 0 1 1 00 step 56 100001100110100100011011011011011101111100011011011010100110110111 source: ; set pin AL1 to clear pin BB2 and pin AN2 AND-NOR OUTPUTS and set TAPE BUS 2 OUTPUT and TAPE BUS 3 OUTPUT source: 1 0 0 11 changed: 1 0 0 11 step 57 100001110110100100011011011011011100110111011011011010100110110111 source: 0 1 1 00 changed: 0 1 1 00 step 58 100001100110100100011011011011011101111100011011011010100110110111 source: ; set pin AE2 to clear pin BB2 and pin AN2 AND-NOR OUTPUTS and set TAPE BUS 2 OUTPUT and TAPE BUS 3 OUTPUT source: 1 0 0 11 changed: 1 0 0 11 step 59 100001101110100100011011011011011100110111011011011010100110110111 source: 0 1 1 00 changed: 0 1 1 00 step 60 100001100110100100011011011011011101111100011011011010100110110111 source: ; set pin AC1 to clear pin BB2 and set TAPE BUS 3 OUTPUT source: 1 0 1 changed: 1 0 1 step 61 100001100111100100011011011011011100111101011011011010100110110111 source: 0 1 0 changed: 0 1 0 step 62 100001100110100100011011011011011101111100011011011010100110110111 source: ; set pin AF1 to clear pin BB2 and set TAPE BUS 3 OUTPUT source: 1 0 1 changed: 1 0 1 step 63 100001100110110100011011011011011100111101011011011010100110110111 source: 0 1 0 changed: 0 1 0 step 64 100001100110100100011011011011011101111100011011011010100110110111 source: ; set pin AR2 to clear pin AN2 AND-NOR OUTPUTS and set TAPE BUS 2 OUTPUT source: 1 0 1 changed: 1 0 1 step 65 100001100110101100011011011011011101110110011011011010100110110111 source: 0 1 0 changed: 0 1 0 step 66 100001100110100100011011011011011101111100011011011010100110110111 source: ; set pin AP2 to clear pin AN2 AND-NOR OUTPUTS and set TAPE BUS 2 OUTPUT source: 1 0 1 changed: 1 0 1 step 67 100001100110100110011011011011011101110110011011011010100110110111 source: 0 1 0 changed: 0 1 0 step 68 100001100110100100011011011011011101111100011011011010100110110111 source: source: ; set pin BK1 to clear pin BB1 and pin BN1 AND-NOR OUTPUTS and set TAPE BUS 2 OUTPUT and TAPE BUS 3 OUTPUT source: 1 00 11 changed: 1 00 11 step 69 100001100110100101011011011011011101001111011011011010100110110111 source: 0 11 00 changed: 0 11 00 step 70 100001100110100100011011011011011101111100011011011010100110110111 source: ; set pin BL1 to clear pin BB1 and pin BN1 AND-NOR OUTPUTS and set TAPE BUS 2 OUTPUT and TAPE BUS 3 OUTPUT source: 1 00 11 changed: 1 00 11 step 71 100001100110100100111011011011011101001111011011011010100110110111 source: 0 11 00 changed: 0 11 00 step 72 100001100110100100011011011011011101111100011011011010100110110111 source: ; set pin BF1 to clear pin BB1 and pin BN1 AND-NOR OUTPUTS and set TAPE BUS 2 OUTPUT and TAPE BUS 3 OUTPUT source: 1 00 11 changed: 1 00 11 step 73 100001100110100100011111011011011101001111011011011010100110110111 source: 0 11 00 changed: 0 11 00 step 74 100001100110100100011011011011011101111100011011011010100110110111 source: ; set pin BS1 to clear pin BB1 and pin BN1 AND-NOR OUTPUTS and set TAPE BUS 2 OUTPUT and TAPE BUS 3 OUTPUT source: 1 00 11 changed: 1 00 11 step 75 100001100110100100011011111011011101001111011011011010100110110111 source: 0 11 00 changed: 0 11 00 step 76 100001100110100100011011011011011101111100011011011010100110110111 source: ; set pin BL2 to clear pin BB1 and pin BN1 AND-NOR OUTPUTS and set TAPE BUS 2 OUTPUT and TAPE BUS 3 OUTPUT source: 1 00 11 changed: 1 00 11 step 77 100001100110100100011011011111011101001111011011011010100110110111 source: 0 11 00 changed: 0 11 00 step 78 100001100110100100011011011011011101111100011011011010100110110111 source: ; set pin BU1 to clear pin BB1 and pin BN1 AND-NOR OUTPUTS and set TAPE BUS 2 OUTPUT and TAPE BUS 3 OUTPUT source: 1 00 11 changed: 1 00 11 step 79 100001100110100100011011011011111101001111011011011010100110110111 source: 0 11 00 changed: 0 11 00 step 80 100001100110100100011011011011011101111100011011011010100110110111 source: ; set pin BM2 to clear pin BB1 and TAPE BUS 3 OUTPUT source: 1 0 1 changed: 1 0 1 step 81 100001100110100100011011011011011111101110011011011010100110110111 source: 0 1 0 changed: 0 1 0 step 82 100001100110100100011011011011011101111100011011011010100110110111 source: ; no change source: 100000000000000000000000000000000001111100011011011010100110110111 changed: 00 00 0 0 00 00 00 00 000 step 83 100000000000000000000000000000000001111100011011011010100110110111 source: source: ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; source: ; test shifting the RWB source: ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; source: source: ; shift in 0, expect 10 source: 0 changed: 0 step 84 100000000000000000000000000000000001111100011011011010100110100111 source: 110 changed: 1 0 step 85 100000000000000000000000000000000001111100011011011010100110101101 source: 0 changed: 0 step 86 100000000000000000000000000000000001111100011011011010100110100101 source: ; toggle phase should toggle RWB 2 source: 0 0 changed: 0 0 step 87 100000000000000000000000000000000001111100011011011010100110000001 source: 1 1 changed: 1 1 step 88 100000000000000000000000000000000001111100011011011010100110100101 source: source: ; shift in 0, expect 00 source: 0 changed: step 89 100000000000000000000000000000000001111100011011011010100110100101 source: 100 changed: 10 step 90 100000000000000000000000000000000001111100011011011010100110101001 source: 0 changed: 0 step 91 100000000000000000000000000000000001111100011011011010100110100001 source: ; toggle phase should toggle RWB 2 source: 0 1 changed: 0 1 step 92 100000000000000000000000000000000001111100011011011010100110000101 source: 1 0 changed: 1 0 step 93 100000000000000000000000000000000001111100011011011010100110100001 source: source: ; shift in 0, expect 00 source: 0 changed: step 94 100000000000000000000000000000000001111100011011011010100110100001 source: 100 changed: 1 step 95 100000000000000000000000000000000001111100011011011010100110101001 source: 0 changed: 0 step 96 100000000000000000000000000000000001111100011011011010100110100001 source: ; shift in 1, expect 01 source: 1 changed: 1 step 97 100000000000000000000000000000000001111100011011011010100110110001 source: 101 changed: 1 1 step 98 100000000000000000000000000000000001111100011011011010100110111011 source: 0 changed: 0 step 99 100000000000000000000000000000000001111100011011011010100110110011 source: ; shift in 1, expect 11 source: 1 changed: step 100 100000000000000000000000000000000001111100011011011010100110110011 source: 111 changed: 11 step 101 100000000000000000000000000000000001111100011011011010100110111111 source: 0 changed: 0 step 102 100000000000000000000000000000000001111100011011011010100110110111 source: ; shift in 1, expect 11 source: 1 changed: step 103 100000000000000000000000000000000001111100011011011010100110110111 source: 111 changed: 1 step 104 100000000000000000000000000000000001111100011011011010100110111111 source: 0 changed: 0 step 105 100000000000000000000000000000000001111100011011011010100110110111 source: ; shift in 0, expect 10 source: 0 changed: 0 step 106 100000000000000000000000000000000001111100011011011010100110100111 source: 110 changed: 1 0 step 107 100000000000000000000000000000000001111100011011011010100110101101 source: 0 changed: 0 step 108 100000000000000000000000000000000001111100011011011010100110100101 source: ; shift in 1, expect 01 source: 1 changed: 1 step 109 100000000000000000000000000000000001111100011011011010100110110101 source: 101 changed: 101 step 110 100000000000000000000000000000000001111100011011011010100110111011 source: 0 changed: 0 step 111 100000000000000000000000000000000001111100011011011010100110110011 source: ; shift in 0, expect 10 source: 0 changed: 0 step 112 100000000000000000000000000000000001111100011011011010100110100011 source: 110 changed: 110 step 113 100000000000000000000000000000000001111100011011011010100110101101 source: 0 changed: 0 step 114 100000000000000000000000000000000001111100011011011010100110100101 source: ; shift in 1, expect 01 source: 1 changed: 1 step 115 100000000000000000000000000000000001111100011011011010100110110101 source: 101 changed: 101 step 116 100000000000000000000000000000000001111100011011011010100110111011 source: 0 changed: 0 step 117 100000000000000000000000000000000001111100011011011010100110110011 source: ; shift in 1, expect 10 source: 1 changed: step 118 100000000000000000000000000000000001111100011011011010100110110011 SLOT BAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBAABBAAAAAAAAAAAAAABBBBBABBBB LETTER ALPSLFMDEEMCBFRSPKLEMFHRSCJLJKUHPNMBBNNVVRKRHUTDJUKANJHBTPDFSVEVDU SIDE 121212122121212121111111112212122222112222111221112112212112212122 DIRECTION IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIOOOOOOOIOOIOOIOOIOOOOIOOIIIIOOO source: 110 changed: 11 step 119 100000000000000000000000000000000001111100011011011010100110111111 fail ^ space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C toggle comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT BAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBAABBAAAAAAAAAAAAAABBBBBABBBB LETTER ALPSLFMDEEMCBFRSPKLEMFHRSCJLJKUHPNMBBNNVVRKRHUTDJUKANJHBTPDFSVEVDU SIDE 121212122121212121111111112212122222112222111221112112212112212122 DIRECTION IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIOOOOOOOIOOIOOIOOIOOOOIOOIIIIOOO source: 0 changed: 0 step 120 100000000000000000000000000000000001111100011011011010100110110111 fail ^ SLOT BAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBAABBAAAAAAAAAAAAAABBBBBABBBB LETTER ALPSLFMDEEMCBFRSPKLEMFHRSCJLJKUHPNMBBNNVVRKRHUTDJUKANJHBTPDFSVEVDU SIDE 121212122121212121111111112212122222112222111221112112212112212122 DIRECTION IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIOOOOOOOIOOIOOIOOIOOOOIOOIIIIOOO source: ; shift in 1, expect 11 source: 1 changed: step 121 100000000000000000000000000000000001111100011011011010100110110111 fail ^ source: 111 changed: 1 step 122 100000000000000000000000000000000001111100011011011010100110111111 source: 0 changed: 0 step 123 100000000000000000000000000000000001111100011011011010100110110111 source: ; no change source: 100000000000000000000000000000000001111100011011011010100110110111 changed: step 124 100000000000000000000000000000000001111100011011011010100110110111 test 22: *** FAIL *************************** 3 steps failed SLOT BAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBAABBAAAAAAAAAAAAAABBBBBABBBB LETTER ALPSLFMDEEMCBFRSPKLEMFHRSCJLJKUHPNMBBNNVVRKRHUTDJUKANJHBTPDFSVEVDU SIDE 121212122121212121111111112212122222112222111221112112212112212122 DIRECTION IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIOOOOOOOIOOIOOIOOIOOOOIOOIIIIOOO this fail O all fails O was hi 111111111111111111111111111111111111111111111111111111111111111111 rising ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ ^^^^^^^^^^^^^^^^^^^^^^^^^ falling vvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvv vvvvvvvvvvvvvvvvvvvvvvvvv was lo 00000000000000000000000000000000000000 0000000000000000000000000 total fails 22, total passes 0 space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C toggle comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit source: ; all registers are unknown source: ; turn on C0, PHASE source: ; with no ENABLES, BUS2,BUS3 is 11, C2 is 1 source: 1000000000000000000000000000000000011111000XX0XX0XX0XXXX0XX0110XX1 changed: step 1 100000000000000000000000000000000001111100011011011010100110110111 source: source: ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; source: ; source: ; set all registers LOW source: ; source: ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; source: source: ; load TMA SETUP from tape bus (00) source: 100 changed: 100 step 2 100000000000000000000000000000000001111100100011011010100110110111 source: 0 changed: 0 step 3 100000000000000000000000000000000001111100000011011010100110110111 source: ; load TMA from tape bus (00) source: 100 changed: 100 step 4 100000000000000000000000000000000001111100000100011010100110110111 source: 0 changed: 0 step 5 100000000000000000000000000000000001111100000000011010100110110111 source: ; load TBN from tape bus (00) source: 100 changed: 100 step 6 100000000000000000000000000000000001111100000000100010100110110111 source: 0 changed: 0 step 7 100000000000000000000000000000000001111100000000000010100110110111 source: ; load TAC from tape bus (00) source: 10101 changed: 10101 step 8 100000000000000000000000000000000001111100000000000101010110110111 source: 0 changed: 0 step 9 100000000000000000000000000000000001111100000000000001010110110111 source: ; load TB from tape bus (00) source: 100 changed: 100 step 10 100000000000000000000000000000000001111100000000000001011000110111 source: 0 changed: 0 step 11 100000000000000000000000000000000001111100000000000001010000110111 source: ; load RWB from TB (JAMS CLEAR AND PRESET) source: 1 00 changed: 1 00 step 12 100000000000000000000000000000000001111100000000000001010001110001 source: 0 changed: 0 step 13 100000000000000000000000000000000001111100000000000001010000110001 source: ; (no change) source: 100000000000000000000000000000000001111100000000000001010000110001 changed: step 14 100000000000000000000000000000000001111100000000000001010000110001 source: source: source: ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; source: ; source: ; set all registers HIGH source: ; source: ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; source: source: ; set pin AF1 (AND with itself) to clear pin BB2 (AND-NOR output) and set pin BR2 TAPE BUS 3 OUTPUT source: 1 0 1 changed: 1 0 1 step 15 100000000000010000000000000000000000111101000000000001010000110001 source: ; set pin AP2 (AND with itself) to clear pin AN2 (AND-NOR output) and set pin BV2 TAPE BUS 2 OUTPUT source: 1 0 1 changed: 1 0 1 step 16 100000000000010010000000000000000000110111000000000001010000110001 source: source: source: ; load TMA SETUP from tape bus (11) source: 111 changed: 111 step 17 100000000000010010000000000000000000110111111000000001010000110001 source: 0 changed: 0 step 18 100000000000010010000000000000000000110111011000000001010000110001 source: ; load TMA from tape bus (11) source: 111 changed: 111 step 19 100000000000010010000000000000000000110111011111000001010000110001 source: 0 changed: 0 step 20 100000000000010010000000000000000000110111011011000001010000110001 source: ; load TBN from tape bus (11) source: 111 changed: 111 step 21 100000000000010010000000000000000000110111011011111001010000110001 source: 0 changed: 0 step 22 100000000000010010000000000000000000110111011011011001010000110001 source: ; load TAC from tape bus (11) source: 11010 changed: 11010 step 23 100000000000010010000000000000000000110111011011011110100000110001 source: 0 changed: 0 step 24 100000000000010010000000000000000000110111011011011010100000110001 source: ; load TB from tape bus (11) source: 111 changed: 111 step 25 100000000000010010000000000000000000110111011011011010101110110001 source: 0 changed: 0 step 26 100000000000010010000000000000000000110111011011011010100110110001 source: ; load RWB from TB (JAMS CLEAR AND PRESET) source: 1 11 changed: 1 11 step 27 100000000000010010000000000000000000110111011011011010100111110111 source: 0 changed: 0 step 28 100000000000010010000000000000000000110111011011011010100110110111 source: ; clear pin AF1 (AND with itself) to set pin BB2 (AND-NOR output) and clear pin BR2 TAPE BUS 3 OUTPUT source: 0 1 0 changed: 0 1 0 step 29 100000000000000010000000000000000001110110011011011010100110110111 source: ; clear pin AP2 (AND with itself) to set pin AN2 (AND-NOR output) and clear pin BV2 TAPE BUS 2 OUTPUT source: 0 1 0 changed: 0 1 0 step 30 100000000000000000000000000000000001111100011011011010100110110111 source: ; (no change) source: 100000000000000000000000000000000001111100011011011010100110110111 changed: step 31 100000000000000000000000000000000001111100011011011010100110110111 source: source: source: ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; source: ; source: ; test AND-NOR logic source: ; source: ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; source: source: ; (all registers are HIGH) source: ; set all pins HIGH except ENABLES source: source: ; set pin AF2 HIGH source: 1 changed: 1 step 32 100001000000000000000000000000000001111100011011011010100110110111 source: ; set pin AM1 HIGH source: 1 changed: 1 step 33 100001100000000000000000000000000001111100011011011010100110110111 source: ; set pin AE1 HIGH source: 1 changed: 1 step 34 100001100100000000000000000000000001111100011011011010100110110111 source: ; set pin AM2 HIGH source: 1 changed: 1 step 35 100001100110000000000000000000000001111100011011011010100110110111 source: ; set pin AB2 HIGH source: 1 changed: 1 step 36 100001100110100000000000000000000001111100011011011010100110110111 source: ; set pin AS1 HIGH source: 1 changed: 1 step 37 100001100110100100000000000000000001111100011011011010100110110111 source: ; set pin BE1 HIGH source: 1 changed: 1 step 38 100001100110100100010000000000000001111100011011011010100110110111 source: ; set pin BM1 HIGH source: 1 changed: 1 step 39 100001100110100100011000000000000001111100011011011010100110110111 source: ; set pin BH1 HIGH source: 1 changed: 1 step 40 100001100110100100011010000000000001111100011011011010100110110111 source: ; set pin BR1 HIGH source: 1 changed: 1 step 41 100001100110100100011011000000000001111100011011011010100110110111 source: ; set pin BC1 HIGH source: 1 changed: 1 step 42 100001100110100100011011010000000001111100011011011010100110110111 source: ; set pin BJ2 HIGH source: 1 changed: 1 step 43 100001100110100100011011011000000001111100011011011010100110110111 source: ; set pin BJ1 HIGH source: 1 changed: 1 step 44 100001100110100100011011011010000001111100011011011010100110110111 source: ; set pin BK2 HIGH source: 1 changed: 1 step 45 100001100110100100011011011011000001111100011011011010100110110111 source: ; set pin BH2 HIGH source: 1 changed: 1 step 46 100001100110100100011011011011010001111100011011011010100110110111 source: ; set pin BP2 HIGH source: 1 changed: 1 step 47 100001100110100100011011011011011001111100011011011010100110110111 source: ; set pin BN2 HIGH source: 1 changed: 1 step 48 100001100110100100011011011011011101111100011011011010100110110111 source: ; toggle each ENABLE source: source: ; set pin AL2 to clear pin BB2 and pin AN2 AND-NOR OUTPUTS and set TAPE BUS 2 OUTPUT and TAPE BUS 3 OUTPUT source: 1 0 0 11 changed: 1 0 0 11 step 49 110001100110100100011011011011011100110111011011011010100110110111 source: 0 1 1 00 changed: 0 1 1 00 step 50 100001100110100100011011011011011101111100011011011010100110110111 source: ; set pin AP1 to clear pin BB2 and pin AN2 AND-NOR OUTPUTS and set TAPE BUS 2 OUTPUT and TAPE BUS 3 OUTPUT source: 1 0 0 11 changed: 1 0 0 11 step 51 101001100110100100011011011011011100110111011011011010100110110111 source: 0 1 1 00 changed: 0 1 1 00 step 52 100001100110100100011011011011011101111100011011011010100110110111 source: ; set pin AS2 to clear pin BB2 and pin AN2 AND-NOR OUTPUTS and set TAPE BUS 2 OUTPUT and TAPE BUS 3 OUTPUT source: 1 0 0 11 changed: 1 0 0 11 step 53 100101100110100100011011011011011100110111011011011010100110110111 source: 0 1 1 00 changed: 0 1 1 00 step 54 100001100110100100011011011011011101111100011011011010100110110111 source: ; set pin AL1 to clear pin BB2 and pin AN2 AND-NOR OUTPUTS and set TAPE BUS 2 OUTPUT and TAPE BUS 3 OUTPUT source: 1 0 0 11 changed: 1 0 0 11 step 55 100011100110100100011011011011011100110111011011011010100110110111 source: 0 1 1 00 changed: 0 1 1 00 step 56 100001100110100100011011011011011101111100011011011010100110110111 source: ; set pin AL1 to clear pin BB2 and pin AN2 AND-NOR OUTPUTS and set TAPE BUS 2 OUTPUT and TAPE BUS 3 OUTPUT source: 1 0 0 11 changed: 1 0 0 11 step 57 100001110110100100011011011011011100110111011011011010100110110111 source: 0 1 1 00 changed: 0 1 1 00 step 58 100001100110100100011011011011011101111100011011011010100110110111 source: ; set pin AE2 to clear pin BB2 and pin AN2 AND-NOR OUTPUTS and set TAPE BUS 2 OUTPUT and TAPE BUS 3 OUTPUT source: 1 0 0 11 changed: 1 0 0 11 step 59 100001101110100100011011011011011100110111011011011010100110110111 source: 0 1 1 00 changed: 0 1 1 00 step 60 100001100110100100011011011011011101111100011011011010100110110111 source: ; set pin AC1 to clear pin BB2 and set TAPE BUS 3 OUTPUT source: 1 0 1 changed: 1 0 1 step 61 100001100111100100011011011011011100111101011011011010100110110111 source: 0 1 0 changed: 0 1 0 step 62 100001100110100100011011011011011101111100011011011010100110110111 source: ; set pin AF1 to clear pin BB2 and set TAPE BUS 3 OUTPUT source: 1 0 1 changed: 1 0 1 step 63 100001100110110100011011011011011100111101011011011010100110110111 source: 0 1 0 changed: 0 1 0 step 64 100001100110100100011011011011011101111100011011011010100110110111 source: ; set pin AR2 to clear pin AN2 AND-NOR OUTPUTS and set TAPE BUS 2 OUTPUT source: 1 0 1 changed: 1 0 1 step 65 100001100110101100011011011011011101110110011011011010100110110111 source: 0 1 0 changed: 0 1 0 step 66 100001100110100100011011011011011101111100011011011010100110110111 source: ; set pin AP2 to clear pin AN2 AND-NOR OUTPUTS and set TAPE BUS 2 OUTPUT source: 1 0 1 changed: 1 0 1 step 67 100001100110100110011011011011011101110110011011011010100110110111 source: 0 1 0 changed: 0 1 0 step 68 100001100110100100011011011011011101111100011011011010100110110111 source: source: ; set pin BK1 to clear pin BB1 and pin BN1 AND-NOR OUTPUTS and set TAPE BUS 2 OUTPUT and TAPE BUS 3 OUTPUT source: 1 00 11 changed: 1 00 11 step 69 100001100110100101011011011011011101001111011011011010100110110111 source: 0 11 00 changed: 0 11 00 step 70 100001100110100100011011011011011101111100011011011010100110110111 source: ; set pin BL1 to clear pin BB1 and pin BN1 AND-NOR OUTPUTS and set TAPE BUS 2 OUTPUT and TAPE BUS 3 OUTPUT source: 1 00 11 changed: 1 00 11 step 71 100001100110100100111011011011011101001111011011011010100110110111 source: 0 11 00 changed: 0 11 00 step 72 100001100110100100011011011011011101111100011011011010100110110111 source: ; set pin BF1 to clear pin BB1 and pin BN1 AND-NOR OUTPUTS and set TAPE BUS 2 OUTPUT and TAPE BUS 3 OUTPUT source: 1 00 11 changed: 1 00 11 step 73 100001100110100100011111011011011101001111011011011010100110110111 source: 0 11 00 changed: 0 11 00 step 74 100001100110100100011011011011011101111100011011011010100110110111 source: ; set pin BS1 to clear pin BB1 and pin BN1 AND-NOR OUTPUTS and set TAPE BUS 2 OUTPUT and TAPE BUS 3 OUTPUT source: 1 00 11 changed: 1 00 11 step 75 100001100110100100011011111011011101001111011011011010100110110111 source: 0 11 00 changed: 0 11 00 step 76 100001100110100100011011011011011101111100011011011010100110110111 source: ; set pin BL2 to clear pin BB1 and pin BN1 AND-NOR OUTPUTS and set TAPE BUS 2 OUTPUT and TAPE BUS 3 OUTPUT source: 1 00 11 changed: 1 00 11 step 77 100001100110100100011011011111011101001111011011011010100110110111 source: 0 11 00 changed: 0 11 00 step 78 100001100110100100011011011011011101111100011011011010100110110111 source: ; set pin BU1 to clear pin BB1 and pin BN1 AND-NOR OUTPUTS and set TAPE BUS 2 OUTPUT and TAPE BUS 3 OUTPUT source: 1 00 11 changed: 1 00 11 step 79 100001100110100100011011011011111101001111011011011010100110110111 source: 0 11 00 changed: 0 11 00 step 80 100001100110100100011011011011011101111100011011011010100110110111 source: ; set pin BM2 to clear pin BB1 and TAPE BUS 3 OUTPUT source: 1 0 1 changed: 1 0 1 step 81 100001100110100100011011011011011111101110011011011010100110110111 source: 0 1 0 changed: 0 1 0 step 82 100001100110100100011011011011011101111100011011011010100110110111 source: ; no change source: 100000000000000000000000000000000001111100011011011010100110110111 changed: 00 00 0 0 00 00 00 00 000 step 83 100000000000000000000000000000000001111100011011011010100110110111 source: source: ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; source: ; test shifting the RWB source: ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; source: source: ; shift in 0, expect 10 source: 0 changed: 0 step 84 100000000000000000000000000000000001111100011011011010100110100111 source: 110 changed: 1 0 step 85 100000000000000000000000000000000001111100011011011010100110101101 source: 0 changed: 0 step 86 100000000000000000000000000000000001111100011011011010100110100101 source: ; toggle phase should toggle RWB 2 source: 0 0 changed: 0 0 step 87 100000000000000000000000000000000001111100011011011010100110000001 source: 1 1 changed: 1 1 step 88 100000000000000000000000000000000001111100011011011010100110100101 source: source: ; shift in 0, expect 00 source: 0 changed: step 89 100000000000000000000000000000000001111100011011011010100110100101 source: 100 changed: 10 step 90 100000000000000000000000000000000001111100011011011010100110101001 source: 0 changed: 0 step 91 100000000000000000000000000000000001111100011011011010100110100001 source: ; toggle phase should toggle RWB 2 source: 0 1 changed: 0 1 step 92 100000000000000000000000000000000001111100011011011010100110000101 source: 1 0 changed: 1 0 step 93 100000000000000000000000000000000001111100011011011010100110100001 source: source: ; shift in 0, expect 00 source: 0 changed: step 94 100000000000000000000000000000000001111100011011011010100110100001 source: 100 changed: 1 step 95 100000000000000000000000000000000001111100011011011010100110101001 source: 0 changed: 0 step 96 100000000000000000000000000000000001111100011011011010100110100001 source: ; shift in 1, expect 01 source: 1 changed: 1 step 97 100000000000000000000000000000000001111100011011011010100110110001 source: 101 changed: 1 1 step 98 100000000000000000000000000000000001111100011011011010100110111011 source: 0 changed: 0 step 99 100000000000000000000000000000000001111100011011011010100110110011 source: ; shift in 1, expect 11 source: 1 changed: step 100 100000000000000000000000000000000001111100011011011010100110110011 source: 111 changed: 11 step 101 100000000000000000000000000000000001111100011011011010100110111111 source: 0 changed: 0 step 102 100000000000000000000000000000000001111100011011011010100110110111 source: ; shift in 1, expect 11 source: 1 changed: step 103 100000000000000000000000000000000001111100011011011010100110110111 source: 111 changed: 1 step 104 100000000000000000000000000000000001111100011011011010100110111111 source: 0 changed: 0 step 105 100000000000000000000000000000000001111100011011011010100110110111 source: ; shift in 0, expect 10 source: 0 changed: 0 step 106 100000000000000000000000000000000001111100011011011010100110100111 source: 110 changed: 1 0 step 107 100000000000000000000000000000000001111100011011011010100110101101 source: 0 changed: 0 step 108 100000000000000000000000000000000001111100011011011010100110100101 source: ; shift in 1, expect 01 source: 1 changed: 1 step 109 100000000000000000000000000000000001111100011011011010100110110101 source: 101 changed: 101 step 110 100000000000000000000000000000000001111100011011011010100110111011 source: 0 changed: 0 step 111 100000000000000000000000000000000001111100011011011010100110110011 source: ; shift in 0, expect 10 source: 0 changed: 0 step 112 100000000000000000000000000000000001111100011011011010100110100011 source: 110 changed: 110 step 113 100000000000000000000000000000000001111100011011011010100110101101 source: 0 changed: 0 step 114 100000000000000000000000000000000001111100011011011010100110100101 source: ; shift in 1, expect 01 source: 1 changed: 1 step 115 100000000000000000000000000000000001111100011011011010100110110101 source: 101 changed: 101 step 116 100000000000000000000000000000000001111100011011011010100110111011 source: 0 changed: 0 step 117 100000000000000000000000000000000001111100011011011010100110110011 source: ; shift in 1, expect 10 source: 1 changed: step 118 100000000000000000000000000000000001111100011011011010100110110011 SLOT BAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBAABBAAAAAAAAAAAAAABBBBBABBBB LETTER ALPSLFMDEEMCBFRSPKLEMFHRSCJLJKUHPNMBBNNVVRKRHUTDJUKANJHBTPDFSVEVDU SIDE 121212122121212121111111112212122222112222111221112112212112212122 DIRECTION IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIOOOOOOOIOOIOOIOOIOOOOIOOIIIIOOO source: 110 changed: 11 step 119 100000000000000000000000000000000001111100011011011010100110111111 fail ^ SLOT BAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBAABBAAAAAAAAAAAAAABBBBBABBBB LETTER ALPSLFMDEEMCBFRSPKLEMFHRSCJLJKUHPNMBBNNVVRKRHUTDJUKANJHBTPDFSVEVDU SIDE 121212122121212121111111112212122222112222111221112112212112212122 DIRECTION IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIOOOOOOOIOOIOOIOOIOOOOIOOIIIIOOO source: 0 changed: 0 step 120 100000000000000000000000000000000001111100011011011010100110110111 fail ^ SLOT BAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBAABBAAAAAAAAAAAAAABBBBBABBBB LETTER ALPSLFMDEEMCBFRSPKLEMFHRSCJLJKUHPNMBBNNVVRKRHUTDJUKANJHBTPDFSVEVDU SIDE 121212122121212121111111112212122222112222111221112112212112212122 DIRECTION IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIOOOOOOOIOOIOOIOOIOOOOIOOIIIIOOO source: ; shift in 1, expect 11 source: 1 changed: step 121 100000000000000000000000000000000001111100011011011010100110110111 fail ^ source: 111 changed: 1 step 122 100000000000000000000000000000000001111100011011011010100110111111 source: 0 changed: 0 step 123 100000000000000000000000000000000001111100011011011010100110110111 source: ; no change source: 100000000000000000000000000000000001111100011011011010100110110111 changed: step 124 100000000000000000000000000000000001111100011011011010100110110111 test 23: *** FAIL *************************** 3 steps failed SLOT BAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBAABBAAAAAAAAAAAAAABBBBBABBBB LETTER ALPSLFMDEEMCBFRSPKLEMFHRSCJLJKUHPNMBBNNVVRKRHUTDJUKANJHBTPDFSVEVDU SIDE 121212122121212121111111112212122222112222111221112112212112212122 DIRECTION IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIOOOOOOOIOOIOOIOOIOOOOIOOIIIIOOO this fail O all fails O was hi 111111111111111111111111111111111111111111111111111111111111111111 rising ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ ^^^^^^^^^^^^^^^^^^^^^^^^^ falling vvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvv vvvvvvvvvvvvvvvvvvvvvvvvv was lo 00000000000000000000000000000000000000 0000000000000000000000000 total fails 23, total passes 0 space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C toggle comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT BAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBAABBAAAAAAAAAAAAAABBBBBABBBB LETTER ALPSLFMDEEMCBFRSPKLEMFHRSCJLJKUHPNMBBNNVVRKRHUTDJUKANJHBTPDFSVEVDU SIDE 121212122121212121111111112212122222112222111221112112212112212122 DIRECTION IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIOOOOOOOIOOIOOIOOIOOOOIOOIIIIOOO all fails O was lo 00000000000000000000000000000000000000 0000000000000000000000000 falling vvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvv vvvvvvvvvvvvvvvvvvvvvvvvv rising ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ ^^^^^^^^^^^^^^^^^^^^^^^^^ was hi 111111111111111111111111111111111111111111111111111111111111111111 total fails 23, total passes 0 Main menu Thu Aug 20 16:39:08 2015 test file is: tests\m222.new delay is: 0 trigger is: 1 1 read test file 2 set test delay 3 set test trigger 4 run test 5 output loading test 8 diags 9 exit Enter test file name? trying to open test file: tests\m222.new reading test file: tests\m222.new comment: M222 PCB REV B SCHEMATIC REV A LINC TAPE REGISTERS comment: comment: TERMINOLOGY- SIGNALS REFER TO VOL4 M222 SCHEMATIC. comment: comment: BUT... comment: comment: DEC USES AND-NOR GATES TO ROUTE THE ADDER A AND B INPUTS, SO... comment: DEC RENAMED THE ADDER TO NEGATIVE LOGIC TERMS (I.E. A-N + B-N + C-N -> SUM-N, C1-N). comment: (NOT THE 7482 DATASHEET NAMES OF A + B + C -> SUM, C1). comment: comment: SO, WITH ALL 'AND ENABLES' LOW, THE AND-NOR OUTPUTS = HIGH. comment: WITH C-L HIGH, THE ADDER OUTPUT IS SUM-N=1, C1-N=1; comment: THE INVERTED ADDER OUTPUT IS LOW (TAPE BUS). comment: AND THERE IS NO CARRY (C1-N IS HI). comment: comment: THE TWO ADDERS, TWO REGISTER BITS, ETC ARE LABELED BIT 2 (EVEN, MSB) AND BIT 3 (ODD, LSB). comment: THE ADDERS ARE REFERRED TO AS 'ADDER2' (MSB) AND 'ADDER3' (LSB). comment: comment: POWER PINS: comment: AA2 +5V comment: AT1 GROUND comment: AC2 GROUND comment: BA2 +5V comment: BT1 GROUND comment: BC2 GROUND comment: comment: (ALL PINS ARE USED). comment: comment: pins: PINS pins: 1 I BA1 CARRY IN-N, (TO E9-5 7482 C0) C-N TO ADDER2 pins: 2 I AL2 AND-NOR ENABLE: TAC TAC3 TO PIN BB2 (TO ADDER3) TAC2 TO PIN AN2 (TO ADDER2) pins: 3 I AP1 AND-NOR ENABLE: TMA SETUP (TMAS)3 TO PIN BB2 (TO ADDER3), (TMAS)3 TO PIN AN2 (TO ADDER2) pins: 4 I AS2 AND-NOR ENABLE: TMA TMA3 TO PIN BB2 (TO ADDER3), TMA2 TO PIN AN2 (TO ADDER2) pins: 5 I AL1 AND-NOR ENABLE: PIN AF2 TO PIN BB2 (TO ADDER3), PIN AM1 TO PIN AN2 (TO ADDER2) pins: 6 I AF2 AND-NOR INPUT (AL1 ENABLES) TO PIN BB2 (TO ADDER3). pins: 7 I AM1 AND-NOR INPUT (AL1 ENABLES) TO PIN AN2 (TO ADDER2) pins: 8 I AD2 AND-NOR ENABLE: RWB RWB3 TO PIN BB2 (TO ADDER3), RWB2 TO PIN AN2 (TO ADDER2) pins: 9 I AE2 AND-NOR ENABLE: PIN AE1 TO PIN BB2 (TO ADDER3), PIN AM2 TO PIN AN2 (TO ADDER2) pins: 10 I AE1 AND-NOR INPUT (AE2 ENABLES) TO PIN BB2 (TO ADDER3). pins: 11 I AM2 AND-NOR INPUT (AE2 ENABLES) TO PIN AN2 (TO ADDER2) pins: 12 I AC1 AND-NOR INPUT, AND WITH PIN AB2 TO PIN BB2 (TO ADDER3) pins: 13 I AB2 AND-NOR INPUT, AND WITH PIN AC1 TO PIN BB2 (TO ADDER3) pins: 14 I AF1 AND-NOR INPUT (AND WITH ITSELF) TO PIN BB2 (TO ADDER3) pins: 15 I AR2 AND-NOR INPUT, AND WITH PIN AS1 TO PIN AN2 (TO ADDER2) pins: 16 I AS1 AND-NOR INPUT, AND WITH PIN AR2 TO PIN AN2 (TO ADDER2) pins: 17 I AP2 AND-NOR INPUT (AND WITH ITSELF) TO PIN AN2 (TO ADDER2) pins: 18 I BK1 AND-NOR ENABLE: TB3 TO PIN BB1 (TO ADDER3), TB2 TO PIN BN1 (TO ADDER2) pins: 19 I BL1 AND-NOR ENABLE: PIN BE1 TO PIN BB1 (TO ADDER3), PIN BM1 TO PIN BN1 (TO ADDER2) pins: 20 I BE1 AND-NOR INPUT (BL1 ENABLES) TO PIN BB1 (TO ADDER3). pins: 21 I BM1 AND-NOR INPUT (BL1 ENABLES) TO PIN BN1 (TO ADDER2) pins: 22 I BF1 AND-NOR ENABLE: PIN BH1 TO PIN BB1 (TO ADDER3), PIN BR1 TO PIN BN1 (TO ADDER2) pins: 23 I BH1 AND-NOR INPUT (BF1 ENABLES): TO PIN BB1 (TO ADDER3), pins: 24 I BR1 AND-NOR INPUT (BF1 ENABLES): TO PIN BN1 (TO ADDER2) pins: 25 I BS1 AND-NOR ENABLE: PIN BC1 TO PIN BB1 (TO ADDER3), PIN BJ2 TO PIN BN1 (TO ADDER2) pins: 26 I BC1 AND-NOR INPUT (BS1 ENABLES): TO PIN BB1 (TO ADDER3), pins: 27 I BJ2 AND-NOR INPUT (BS1 ENABLES): TO PIN BN1 (TO ADDER2) pins: 28 I BL2 AND-NOR ENABLE: PIN BJ1 TO PIN BB1 (TO ADDER3), PIN BK2 TO PIN BN1 (TO ADDER2) pins: 29 I BJ1 AND-NOR INPUT (BL2 ENABLES): TO PIN BB1 (TO ADDER3), pins: 30 I BK2 AND-NOR INPUT (BL2 ENABLES): TO PIN BN1 (TO ADDER2) pins: 31 I BU1 AND-NOR ENABLE: PIN BH2 TO PIN BB1 (TO ADDER3), PIN BP2 TO PIN BN1 (TO ADDER2) pins: 32 I BH2 AND-NOR INPUT (BU1 ENABLES): TO PIN BB1 (TO ADDER3), pins: 33 I BP2 AND-NOR INPUT (BU1 ENABLES): TO PIN BN1 (TO ADDER2) pins: 34 I BN2 AND-NOR INPUT (AND WITH BM2): TO PIN BN1 (TO ADDER2) pins: 35 I BM2 AND-NOR INPUT (AND WITH BM2): TO PIN BN1 (TO ADDER2) pins: 36 O BB2 AND-NOR OUTPUT, (DRIVES E9-2 7482 A1) TO ADDER3 INPUT pins: 37 O BB1 AND-NOR OUTPUT, (DRIVES E9-3 7482 B1) TO ADDER3 INPUT pins: 38 O BN1 AND-NOR OUTPUT, (DRIVES E9-14 7482 A2) TO ADDER2 INPUT pins: 39 O AN2 AND-NOR OUTPUT, (DRIVES E9-13 7482 B2) TO ADDER2 INPUT pins: 40 O AV2 CARRY OUT-N (E9-10 7482 C2) pins: 41 O BV2 TAPE BUS 2 OUTPUT (INVERTED ADDER2 SUM-N (E9-12 7482 SUM2) pins: 42 O BR2 TAPE BUS 3 OUTPUT (INVERTED ADDER3 SUM-N (E9-1 7482 SUM1) pins: 43 I AK1 LOAD TMA SETUP (FROM TAPE BUS) (RISING EDGE CLOCK) pins: 44 O AR1 TMA SETUP 2 pins: 45 O AH1 TMA SETUP 3 pins: 46 I AU2 LOAD TMA (FROM TAPE BUS) (RISING EDGE CLOCK) pins: 47 O AT2 TMA 2 pins: 48 O AD1 TMA 3 pins: 49 I AJ1 LOAD TBN (FROM TAPE BUS) (RISING EDGE CLOCK) pins: 50 O AU1 TBN 2 pins: 51 O AK2 TBN 3 pins: 52 I AA1 LOAD TAC (FROM TAPE BUS) (RISING EDGE CLOCK) pins: 53 O AN1 TAC 2 pins: 54 O AJ2 TAC 2-N pins: 55 O AH2 TAC 3 pins: 56 O AB1 TAC 3-N pins: 57 I BT2 LOAD TB (FROM TAPE BUS) (RISING EDGE CLOCK) pins: 58 O BP1 TB 2 pins: 59 O BD1 TB 3 pins: 60 I BF2 LOAD RWB (FROM TB) (JAMS CLEAR,SET) pins: 61 I BS2 PHASE (SELECTS POLARITY OF RWB OUT, 0 -> INVERTED) pins: 62 I AV1 RWB IN (SHIFTED INTO RWB 3) pins: 63 I BE2 SHIFT RWB (SHIFTS PIN AV1 INTO RWB 3, SHIFTS RWB3 TO RWB2) (RISING CLOCK) pins: 64 O BV1 RWB OUT (IF PHASE=1, =RWB 2; IF PHASE=0; =RWB 2-N) pins: 65 O BD2 RWB 3 pins: 66 O BU2 +3.5V pins: direction: IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIOOOOOOOIOOIOOIOOIOOOOIOOIIIIOOO comment: ; all registers are unknown comment: ; turn on C0, PHASE comment: ; with no ENABLES, BUS2,BUS3 is 11, C2 is 1 test 1: 1000000000000000000000000000000000011111000XX0XX0XX0XXXX0XX0110XX1 comment: comment: ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; comment: ; comment: ; set all registers LOW comment: ; comment: ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; comment: comment: ; load TMA SETUP from tape bus (00) test 2: 100 test 3: 0 comment: ; load TMA from tape bus (00) test 4: 100 test 5: 0 comment: ; load TBN from tape bus (00) test 6: 100 test 7: 0 comment: ; load TAC from tape bus (00) test 8: 10101 test 9: 0 comment: ; load TB from tape bus (00) test 10: 100 test 11: 0 comment: ; load RWB from TB (JAMS CLEAR AND PRESET) test 12: 1 00 test 13: 0 comment: ; (no change) test 14: 100000000000000000000000000000000001111100000000000001010000110001 comment: comment: comment: ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; comment: ; comment: ; set all registers HIGH comment: ; comment: ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; comment: comment: ; set pin AF1 (AND with itself) to clear pin BB2 (AND-NOR output) and set pin BR2 TAPE BUS 3 OUTPUT test 15: 1 0 1 comment: ; set pin AP2 (AND with itself) to clear pin AN2 (AND-NOR output) and set pin BV2 TAPE BUS 2 OUTPUT test 16: 1 0 1 comment: comment: comment: ; load TMA SETUP from tape bus (11) test 17: 111 test 18: 0 comment: ; load TMA from tape bus (11) test 19: 111 test 20: 0 comment: ; load TBN from tape bus (11) test 21: 111 test 22: 0 comment: ; load TAC from tape bus (11) test 23: 11010 test 24: 0 comment: ; load TB from tape bus (11) test 25: 111 test 26: 0 comment: ; load RWB from TB (JAMS CLEAR AND PRESET) test 27: 1 11 test 28: 0 comment: ; clear pin AF1 (AND with itself) to set pin BB2 (AND-NOR output) and clear pin BR2 TAPE BUS 3 OUTPUT test 29: 0 1 0 comment: ; clear pin AP2 (AND with itself) to set pin AN2 (AND-NOR output) and clear pin BV2 TAPE BUS 2 OUTPUT test 30: 0 1 0 comment: ; (no change) test 31: 100000000000000000000000000000000001111100011011011010100110110111 comment: comment: comment: ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; comment: ; comment: ; test AND-NOR logic comment: ; comment: ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; comment: comment: ; (all registers are HIGH) comment: ; set all pins HIGH except ENABLES comment: comment: ; set pin AF2 HIGH test 32: 1 comment: ; set pin AM1 HIGH test 33: 1 comment: ; set pin AE1 HIGH test 34: 1 comment: ; set pin AM2 HIGH test 35: 1 comment: ; set pin AB2 HIGH test 36: 1 comment: ; set pin AS1 HIGH test 37: 1 comment: ; set pin BE1 HIGH test 38: 1 comment: ; set pin BM1 HIGH test 39: 1 comment: ; set pin BH1 HIGH test 40: 1 comment: ; set pin BR1 HIGH test 41: 1 comment: ; set pin BC1 HIGH test 42: 1 comment: ; set pin BJ2 HIGH test 43: 1 comment: ; set pin BJ1 HIGH test 44: 1 comment: ; set pin BK2 HIGH test 45: 1 comment: ; set pin BH2 HIGH test 46: 1 comment: ; set pin BP2 HIGH test 47: 1 comment: ; set pin BN2 HIGH test 48: 1 comment: ; toggle each ENABLE comment: comment: ; set pin AL2 to clear pin BB2 and pin AN2 AND-NOR OUTPUTS and set TAPE BUS 2 OUTPUT and TAPE BUS 3 OUTPUT test 49: 1 0 0 11 test 50: 0 1 1 00 comment: ; set pin AP1 to clear pin BB2 and pin AN2 AND-NOR OUTPUTS and set TAPE BUS 2 OUTPUT and TAPE BUS 3 OUTPUT test 51: 1 0 0 11 test 52: 0 1 1 00 comment: ; set pin AS2 to clear pin BB2 and pin AN2 AND-NOR OUTPUTS and set TAPE BUS 2 OUTPUT and TAPE BUS 3 OUTPUT test 53: 1 0 0 11 test 54: 0 1 1 00 comment: ; set pin AL1 to clear pin BB2 and pin AN2 AND-NOR OUTPUTS and set TAPE BUS 2 OUTPUT and TAPE BUS 3 OUTPUT test 55: 1 0 0 11 test 56: 0 1 1 00 comment: ; set pin AL1 to clear pin BB2 and pin AN2 AND-NOR OUTPUTS and set TAPE BUS 2 OUTPUT and TAPE BUS 3 OUTPUT test 57: 1 0 0 11 test 58: 0 1 1 00 comment: ; set pin AE2 to clear pin BB2 and pin AN2 AND-NOR OUTPUTS and set TAPE BUS 2 OUTPUT and TAPE BUS 3 OUTPUT test 59: 1 0 0 11 test 60: 0 1 1 00 comment: ; set pin AC1 to clear pin BB2 and set TAPE BUS 3 OUTPUT test 61: 1 0 1 test 62: 0 1 0 comment: ; set pin AF1 to clear pin BB2 and set TAPE BUS 3 OUTPUT test 63: 1 0 1 test 64: 0 1 0 comment: ; set pin AR2 to clear pin AN2 AND-NOR OUTPUTS and set TAPE BUS 2 OUTPUT test 65: 1 0 1 test 66: 0 1 0 comment: ; set pin AP2 to clear pin AN2 AND-NOR OUTPUTS and set TAPE BUS 2 OUTPUT test 67: 1 0 1 test 68: 0 1 0 comment: comment: ; set pin BK1 to clear pin BB1 and pin BN1 AND-NOR OUTPUTS and set TAPE BUS 2 OUTPUT and TAPE BUS 3 OUTPUT test 69: 1 00 11 test 70: 0 11 00 comment: ; set pin BL1 to clear pin BB1 and pin BN1 AND-NOR OUTPUTS and set TAPE BUS 2 OUTPUT and TAPE BUS 3 OUTPUT test 71: 1 00 11 test 72: 0 11 00 comment: ; set pin BF1 to clear pin BB1 and pin BN1 AND-NOR OUTPUTS and set TAPE BUS 2 OUTPUT and TAPE BUS 3 OUTPUT test 73: 1 00 11 test 74: 0 11 00 comment: ; set pin BS1 to clear pin BB1 and pin BN1 AND-NOR OUTPUTS and set TAPE BUS 2 OUTPUT and TAPE BUS 3 OUTPUT test 75: 1 00 11 test 76: 0 11 00 comment: ; set pin BL2 to clear pin BB1 and pin BN1 AND-NOR OUTPUTS and set TAPE BUS 2 OUTPUT and TAPE BUS 3 OUTPUT test 77: 1 00 11 test 78: 0 11 00 comment: ; set pin BU1 to clear pin BB1 and pin BN1 AND-NOR OUTPUTS and set TAPE BUS 2 OUTPUT and TAPE BUS 3 OUTPUT test 79: 1 00 11 test 80: 0 11 00 comment: ; set pin BM2 to clear pin BB1 and TAPE BUS 3 OUTPUT test 81: 1 0 1 test 82: 0 1 0 comment: ; no change test 83: 100000000000000000000000000000000001111100011011011010100110110111 comment: comment: ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; comment: ; test shifting the RWB comment: ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; comment: comment: ; shift in 0, expect 10 test 84: 0 test 85: 110 test 86: 0 comment: ; toggle phase should toggle RWB 2 test 87: 0 0 test 88: 1 1 comment: comment: ; shift in 0, expect 00 test 89: 0 test 90: 100 test 91: 0 comment: ; toggle phase should toggle RWB 2 test 92: 0 1 test 93: 1 0 comment: comment: ; shift in 0, expect 00 test 94: 0 test 95: 100 test 96: 0 comment: ; shift in 1, expect 01 test 97: 1 test 98: 101 test 99: 0 comment: ; shift in 1, expect 11 test 100: 1 test 101: 111 test 102: 0 comment: ; shift in 1, expect 11 test 103: 1 test 104: 111 test 105: 0 comment: ; shift in 0, expect 10 test 106: 0 test 107: 110 test 108: 0 comment: ; shift in 1, expect 01 test 109: 1 test 110: 101 test 111: 0 comment: ; shift in 0, expect 10 test 112: 0 test 113: 110 test 114: 0 comment: ; shift in 1, expect 01 test 115: 1 test 116: 101 test 117: 0 comment: ; shift in 1, expect 11 test 118: 1 test 119: 111 test 120: 0 comment: ; no change test 121: 100000000000000000000000000000000001111100011011011010100110110111 comment: comment: ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; comment: ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; comment: ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; comment: ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; comment: ; needs work (more adder tests, more register tests) comment: ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; comment: ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; comment: ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; comment: ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; end: END summary column 1: offset 2, mask 0x2000 column 2: offset 1, mask 0x0002 column 3: offset 1, mask 0x0800 column 4: offset 1, mask 0x0040 column 5: offset 1, mask 0x4000 column 6: offset 0, mask 0x0004 column 7: offset 1, mask 0x2000 column 8: offset 0, mask 0x0010 column 9: offset 0, mask 0x0008 column 10: offset 0, mask 0x0800 column 11: offset 1, mask 0x0004 column 12: offset 0, mask 0x2000 column 13: offset 0, mask 0x0040 column 14: offset 0, mask 0x0400 column 15: offset 1, mask 0x0020 column 16: offset 1, mask 0x0200 column 17: offset 1, mask 0x0010 column 18: offset 3, mask 0x2000 column 19: offset 3, mask 0x1000 column 20: offset 2, mask 0x0200 column 21: offset 3, mask 0x0800 column 22: offset 2, mask 0x0100 column 23: offset 3, mask 0x8000 column 24: offset 3, mask 0x0100 column 25: offset 4, mask 0x8000 column 26: offset 2, mask 0x0800 column 27: offset 3, mask 0x0002 column 28: offset 3, mask 0x0008 column 29: offset 3, mask 0x4000 column 30: offset 3, mask 0x0004 column 31: offset 4, mask 0x2000 column 32: offset 3, mask 0x0001 column 33: offset 3, mask 0x0040 column 34: offset 3, mask 0x0020 column 35: offset 3, mask 0x0010 column 36: offset 2, mask 0x0008 column 37: offset 2, mask 0x1000 column 38: offset 3, mask 0x0400 column 39: offset 1, mask 0x0008 column 40: offset 2, mask 0x0002 column 41: offset 4, mask 0x0008 column 42: offset 3, mask 0x0080 column 43: offset 1, mask 0x8000 column 44: offset 1, mask 0x0400 column 45: offset 0, mask 0x0200 column 46: offset 2, mask 0x0001 column 47: offset 1, mask 0x0080 column 48: offset 0, mask 0x1000 column 49: offset 0, mask 0x0100 column 50: offset 2, mask 0x8000 column 51: offset 1, mask 0x0001 column 52: offset 0, mask 0x8000 column 53: offset 1, mask 0x1000 column 54: offset 0, mask 0x0001 column 55: offset 0, mask 0x0002 column 56: offset 0, mask 0x4000 column 57: offset 4, mask 0x0002 column 58: offset 3, mask 0x0200 column 59: offset 2, mask 0x0400 column 60: offset 2, mask 0x0080 column 61: offset 4, mask 0x0001 column 62: offset 2, mask 0x4000 column 63: offset 2, mask 0x0040 column 64: offset 4, mask 0x1000 column 65: offset 2, mask 0x0020 column 66: offset 4, mask 0x0004 direction bits (1=input) 0x52A3 0x1589 0x943A 0x0680 0x50FC pullup bits (1=pullup) 0x0000 0x0000 0x0000 0x0000 0x0000 test step out_data dont care 1: 0x0000 0x0008 0x700A 0x0400 0x0005 0x5203 0x1481 0x8420 0x0200 0x1000 2: 0x0000 0x8008 0x700A 0x0400 0x0005 0x5003 0x1081 0x8420 0x0200 0x1000 3: 0x0000 0x0008 0x700A 0x0400 0x0005 0x5003 0x1081 0x8420 0x0200 0x1000 4: 0x0000 0x0008 0x700B 0x0400 0x0005 0x4003 0x1001 0x8420 0x0200 0x1000 5: 0x0000 0x0008 0x700A 0x0400 0x0005 0x4003 0x1001 0x8420 0x0200 0x1000 6: 0x0100 0x0008 0x700A 0x0400 0x0005 0x4003 0x1000 0x0420 0x0200 0x1000 7: 0x0000 0x0008 0x700A 0x0400 0x0005 0x4003 0x1000 0x0420 0x0200 0x1000 8: 0xC001 0x0008 0x700A 0x0400 0x0005 0x0000 0x0000 0x0420 0x0200 0x1000 9: 0x4001 0x0008 0x700A 0x0400 0x0005 0x0000 0x0000 0x0420 0x0200 0x1000 10: 0x4001 0x0008 0x700A 0x0400 0x0007 0x0000 0x0000 0x0020 0x0000 0x1000 11: 0x4001 0x0008 0x700A 0x0400 0x0005 0x0000 0x0000 0x0020 0x0000 0x1000 12: 0x4001 0x0008 0x708A 0x0400 0x0005 13: 0x4001 0x0008 0x700A 0x0400 0x0005 14: 0x4001 0x0008 0x700A 0x0400 0x0005 15: 0x4401 0x0008 0x7002 0x0480 0x0005 16: 0x4401 0x0010 0x7002 0x0480 0x000D 17: 0x4601 0x8410 0x7002 0x0480 0x000D 18: 0x4601 0x0410 0x7002 0x0480 0x000D 19: 0x5601 0x0490 0x7003 0x0480 0x000D 20: 0x5601 0x0490 0x7002 0x0480 0x000D 21: 0x5701 0x0491 0xF002 0x0480 0x000D 22: 0x5601 0x0491 0xF002 0x0480 0x000D 23: 0x9602 0x1491 0xF002 0x0480 0x000D 24: 0x1602 0x1491 0xF002 0x0480 0x000D 25: 0x1602 0x1491 0xF402 0x0680 0x000F 26: 0x1602 0x1491 0xF402 0x0680 0x000D 27: 0x1602 0x1491 0xF4A2 0x0680 0x100D 28: 0x1602 0x1491 0xF422 0x0680 0x100D 29: 0x1202 0x1491 0xF42A 0x0600 0x100D 30: 0x1202 0x1489 0xF42A 0x0600 0x1005 31: 0x1202 0x1489 0xF42A 0x0600 0x1005 32: 0x1206 0x1489 0xF42A 0x0600 0x1005 33: 0x1206 0x3489 0xF42A 0x0600 0x1005 34: 0x1A06 0x3489 0xF42A 0x0600 0x1005 35: 0x1A06 0x348D 0xF42A 0x0600 0x1005 36: 0x1A46 0x348D 0xF42A 0x0600 0x1005 37: 0x1A46 0x368D 0xF42A 0x0600 0x1005 38: 0x1A46 0x368D 0xF62A 0x0600 0x1005 39: 0x1A46 0x368D 0xF62A 0x0E00 0x1005 40: 0x1A46 0x368D 0xF62A 0x8E00 0x1005 41: 0x1A46 0x368D 0xF62A 0x8F00 0x1005 42: 0x1A46 0x368D 0xFE2A 0x8F00 0x1005 43: 0x1A46 0x368D 0xFE2A 0x8F02 0x1005 44: 0x1A46 0x368D 0xFE2A 0xCF02 0x1005 45: 0x1A46 0x368D 0xFE2A 0xCF06 0x1005 46: 0x1A46 0x368D 0xFE2A 0xCF07 0x1005 47: 0x1A46 0x368D 0xFE2A 0xCF47 0x1005 48: 0x1A46 0x368D 0xFE2A 0xCF67 0x1005 49: 0x1A46 0x3687 0xFE22 0xCFE7 0x100D 50: 0x1A46 0x368D 0xFE2A 0xCF67 0x1005 51: 0x1A46 0x3E85 0xFE22 0xCFE7 0x100D 52: 0x1A46 0x368D 0xFE2A 0xCF67 0x1005 53: 0x1A46 0x36C5 0xFE22 0xCFE7 0x100D 54: 0x1A46 0x368D 0xFE2A 0xCF67 0x1005 55: 0x1A46 0x7685 0xFE22 0xCFE7 0x100D 56: 0x1A46 0x368D 0xFE2A 0xCF67 0x1005 57: 0x1A56 0x3685 0xFE22 0xCFE7 0x100D 58: 0x1A46 0x368D 0xFE2A 0xCF67 0x1005 59: 0x1A4E 0x3685 0xFE22 0xCFE7 0x100D 60: 0x1A46 0x368D 0xFE2A 0xCF67 0x1005 61: 0x3A46 0x368D 0xFE22 0xCFE7 0x1005 62: 0x1A46 0x368D 0xFE2A 0xCF67 0x1005 63: 0x1E46 0x368D 0xFE22 0xCFE7 0x1005 64: 0x1A46 0x368D 0xFE2A 0xCF67 0x1005 65: 0x1A46 0x36A5 0xFE2A 0xCF67 0x100D 66: 0x1A46 0x368D 0xFE2A 0xCF67 0x1005 67: 0x1A46 0x3695 0xFE2A 0xCF67 0x100D 68: 0x1A46 0x368D 0xFE2A 0xCF67 0x1005 69: 0x1A46 0x368D 0xEE2A 0xEBE7 0x100D 70: 0x1A46 0x368D 0xFE2A 0xCF67 0x1005 71: 0x1A46 0x368D 0xEE2A 0xDBE7 0x100D 72: 0x1A46 0x368D 0xFE2A 0xCF67 0x1005 73: 0x1A46 0x368D 0xEF2A 0xCBE7 0x100D 74: 0x1A46 0x368D 0xFE2A 0xCF67 0x1005 75: 0x1A46 0x368D 0xEE2A 0xCBE7 0x900D 76: 0x1A46 0x368D 0xFE2A 0xCF67 0x1005 77: 0x1A46 0x368D 0xEE2A 0xCBEF 0x100D 78: 0x1A46 0x368D 0xFE2A 0xCF67 0x1005 79: 0x1A46 0x368D 0xEE2A 0xCBE7 0x300D 80: 0x1A46 0x368D 0xFE2A 0xCF67 0x1005 81: 0x1A46 0x368D 0xFE2A 0xCB77 0x100D 82: 0x1A46 0x368D 0xFE2A 0xCF67 0x1005 83: 0x1202 0x1489 0xF42A 0x0600 0x1005 84: 0x1202 0x1489 0xB42A 0x0600 0x1005 85: 0x1202 0x1489 0xB44A 0x0600 0x1005 86: 0x1202 0x1489 0xB40A 0x0600 0x1005 87: 0x1202 0x1489 0xB40A 0x0600 0x0004 88: 0x1202 0x1489 0xB40A 0x0600 0x1005 89: 0x1202 0x1489 0xB40A 0x0600 0x1005 90: 0x1202 0x1489 0xB44A 0x0600 0x0005 91: 0x1202 0x1489 0xB40A 0x0600 0x0005 92: 0x1202 0x1489 0xB40A 0x0600 0x1004 93: 0x1202 0x1489 0xB40A 0x0600 0x0005 94: 0x1202 0x1489 0xB40A 0x0600 0x0005 95: 0x1202 0x1489 0xB44A 0x0600 0x0005 96: 0x1202 0x1489 0xB40A 0x0600 0x0005 97: 0x1202 0x1489 0xF40A 0x0600 0x0005 98: 0x1202 0x1489 0xF46A 0x0600 0x0005 99: 0x1202 0x1489 0xF42A 0x0600 0x0005 100: 0x1202 0x1489 0xF42A 0x0600 0x0005 101: 0x1202 0x1489 0xF46A 0x0600 0x1005 102: 0x1202 0x1489 0xF42A 0x0600 0x1005 103: 0x1202 0x1489 0xF42A 0x0600 0x1005 104: 0x1202 0x1489 0xF46A 0x0600 0x1005 105: 0x1202 0x1489 0xF42A 0x0600 0x1005 106: 0x1202 0x1489 0xB42A 0x0600 0x1005 107: 0x1202 0x1489 0xB44A 0x0600 0x1005 108: 0x1202 0x1489 0xB40A 0x0600 0x1005 109: 0x1202 0x1489 0xF40A 0x0600 0x1005 110: 0x1202 0x1489 0xF46A 0x0600 0x0005 111: 0x1202 0x1489 0xF42A 0x0600 0x0005 112: 0x1202 0x1489 0xB42A 0x0600 0x0005 113: 0x1202 0x1489 0xB44A 0x0600 0x1005 114: 0x1202 0x1489 0xB40A 0x0600 0x1005 115: 0x1202 0x1489 0xF40A 0x0600 0x1005 116: 0x1202 0x1489 0xF46A 0x0600 0x0005 117: 0x1202 0x1489 0xF42A 0x0600 0x0005 118: 0x1202 0x1489 0xF42A 0x0600 0x0005 119: 0x1202 0x1489 0xF46A 0x0600 0x1005 120: 0x1202 0x1489 0xF42A 0x0600 0x1005 121: 0x1202 0x1489 0xF42A 0x0600 0x1005 PINs used (in edge connector order) (G=ground,P=power) SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBB LETTER ABCDEFHJKLMNPRSTUVABCDEFHJKLMNPRSTUVABCDEFHJKLMNPRSTUVABCDEFHJKLMNPRSTUV SIDE 111111111111111111222222222222222222111111111111111111222222222222222222 USAGE IOIOIIOIIIIOIOIGOIPIGIIIOOOIIOIIIOIOIOIOIIIIIIIOOIIGIOPOGOIIIIIIIIIOIIOO UUT has 44 inputs UUT has 22 outputs contains 66 pins/columns 0 pins are not used contains 121 'test steps' M222 PCB REV B SCHEMATIC REV A LINC TAPE REGISTERS TERMINOLOGY- SIGNALS REFER TO VOL4 M222 SCHEMATIC. BUT... DEC USES AND-NOR GATES TO ROUTE THE ADDER A AND B INPUTS, SO... DEC RENAMED THE ADDER TO NEGATIVE LOGIC TERMS (I.E. A-N + B-N + C-N -> SUM-N, C1-N). (NOT THE 7482 DATASHEET NAMES OF A + B + C -> SUM, C1). SO, WITH ALL 'AND ENABLES' LOW, THE AND-NOR OUTPUTS = HIGH. WITH C-L HIGH, THE ADDER OUTPUT IS SUM-N=1, C1-N=1; THE INVERTED ADDER OUTPUT IS LOW (TAPE BUS). AND THERE IS NO CARRY (C1-N IS HI). THE TWO ADDERS, TWO REGISTER BITS, ETC ARE LABELED BIT 2 (EVEN, MSB) AND BIT 3 (ODD, LSB). THE ADDERS ARE REFERRED TO AS 'ADDER2' (MSB) AND 'ADDER3' (LSB). POWER PINS: AA2 +5V AT1 GROUND AC2 GROUND BA2 +5V BT1 GROUND BC2 GROUND (ALL PINS ARE USED). PINS Main menu Thu Aug 20 16:39:13 2015 test file is: tests\m222.new delay is: 0 trigger is: 1 1 read test file 2 set test delay 3 set test trigger 4 run test 5 output loading test 8 diags 9 exit UUT power is okay Thu Aug 20 16:39:14 2015 space single step O run once (one test, all steps) F run, stop on fail G go (run tests N run, stop on fail, no print S scope (run, no print) C toggle comment printout + increase speed (less delay) - decrease speed (more delay)(slower) Q quit test scope (run, no print) ppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppFpppppppppppppp ppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppp ppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppp ppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppp ppppppppppppppppppppppppppppppppppppppppp space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C toggle comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT BAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBAABBAAAAAAAAAAAAAABBBBBABBBB LETTER ALPSLFMDEEMCBFRSPKLEMFHRSCJLJKUHPNMBBNNVVRKRHUTDJUKANJHBTPDFSVEVDU SIDE 121212122121212121111111112212122222112222111221112112212112212122 DIRECTION IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIOOOOOOOIOOIOOIOOIOOOOIOOIIIIOOO all fails I was lo 00000000000000000000000000000000000000 0000000000000000000000000 falling vvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvv vvvvvvvvvvvvvvvvvvvvvvvvv rising ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ ^^^^^^^^^^^^^^^^^^^^^^^^^ was hi 111111111111111111111111111111111111111111111111111111111111111111 total fails 1, total passes 356 Main menu Thu Aug 20 16:39:40 2015 test file is: tests\m222.new delay is: 0 trigger is: 1 1 read test file 2 set test delay 3 set test trigger 4 run test 5 output loading test 8 diags 9 exit UUT power is okay Thu Aug 20 16:40:05 2015 space single step O run once (one test, all steps) F run, stop on fail G go (run tests N run, stop on fail, no print S scope (run, no print) C toggle comment printout + increase speed (less delay) - decrease speed (more delay)(slower) Q quit test scope (run, no print) ppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppp pppppppppppppppppppppppppppppppppppppppppppppppppppppppFppppppppppppppppppppppp pppppppppppppp space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C toggle comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT BAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBAABBAAAAAAAAAAAAAABBBBBABBBB LETTER ALPSLFMDEEMCBFRSPKLEMFHRSCJLJKUHPNMBBNNVVRKRHUTDJUKANJHBTPDFSVEVDU SIDE 121212122121212121111111112212122222112222111221112112212112212122 DIRECTION IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIOOOOOOOIOOIOOIOOIOOOOIOOIIIIOOO all fails I OO was lo 00000000000000000000000000000000000000 0000000000000000000000000 falling vvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvv vvvvvvvvvvvvvvvvvvvvvvvvv rising ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ ^^^^^^^^^^^^^^^^^^^^^^^^^ was hi 111111111111111111111111111111111111111111111111111111111111111111 total fails 1, total passes 171 Main menu Thu Aug 20 16:40:19 2015 test file is: tests\m222.new delay is: 0 trigger is: 1 1 read test file 2 set test delay 3 set test trigger 4 run test 5 output loading test 8 diags 9 exit UUT power is okay Thu Aug 20 16:40:34 2015 space single step O run once (one test, all steps) F run, stop on fail G go (run tests N run, stop on fail, no print S scope (run, no print) C toggle comment printout + increase speed (less delay) - decrease speed (more delay)(slower) Q quit test scope (run, no print) ppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppp ppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppp pppppppppppppppppppp space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C toggle comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C toggle comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit scope (run, no print) Fpppppppppppppppppppppppppppppppppppppppppppppppppppppppppp ppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppp pppppppppppppppppppp space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C toggle comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT BAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBAABBAAAAAAAAAAAAAABBBBBABBBB LETTER ALPSLFMDEEMCBFRSPKLEMFHRSCJLJKUHPNMBBNNVVRKRHUTDJUKANJHBTPDFSVEVDU SIDE 121212122121212121111111112212122222112222111221112112212112212122 DIRECTION IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIOOOOOOOIOOIOOIOOIOOOOIOOIIIIOOO all fails O O OOOO O was lo 00000000000000000000000000000000000000 0000000000000000000000000 falling vvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvv vvvvvvvvvvvvvvvvvvvvvvvvv rising ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ ^^^^^^^^^^^^^^^^^^^^^^^^^ was hi 111111111111111111111111111111111111111111111111111111111111111111 total fails 1, total passes 335 Main menu Thu Aug 20 16:41:31 2015 test file is: tests\m222.new delay is: 0 trigger is: 1 1 read test file 2 set test delay 3 set test trigger 4 run test 5 output loading test 8 diags 9 exit UUT power is okay Thu Aug 20 17:11:47 2015 space single step O run once (one test, all steps) F run, stop on fail G go (run tests N run, stop on fail, no print S scope (run, no print) C toggle comment printout + increase speed (less delay) - decrease speed (more delay)(slower) Q quit test step 1 100000000000000000000000000000000001111100010010000001010100110101 step 2 100000000000000000000000000000000001111100100010000001010100110101 step 3 100000000000000000000000000000000001111100000010000001010100110101 step 4 100000000000000000000000000000000001111100000100000001010100110101 step 5 100000000000000000000000000000000001111100000000000001010100110101 step 6 100000000000000000000000000000000001111100000000100001010100110101 step 7 100000000000000000000000000000000001111100000000000001010100110101 step 8 100000000000000000000000000000000001111100000000000101010100110101 step 9 100000000000000000000000000000000001111100000000000001010100110101 step 10 100000000000000000000000000000000001111100000000000001011000110101 step 11 100000000000000000000000000000000001111100000000000001010000110101 step 12 100000000000000000000000000000000001111100000000000001010001110001 step 13 100000000000000000000000000000000001111100000000000001010000110001 step 14 100000000000000000000000000000000001111100000000000001010000110001 step 15 100000000000010000000000000000000000111101000000000001010000110001 step 16 100000000000010010000000000000000000110111000000000001010000110001 step 17 100000000000010010000000000000000000110111111000000001010000110001 step 18 100000000000010010000000000000000000110111011000000001010000110001 step 19 100000000000010010000000000000000000110111011111000001010000110001 step 20 100000000000010010000000000000000000110111011011000001010000110001 step 21 100000000000010010000000000000000000110111011011111001010000110001 step 22 100000000000010010000000000000000000110111011011011001010000110001 step 23 100000000000010010000000000000000000110111011011011110100000110001 step 24 100000000000010010000000000000000000110111011011011010100000110001 step 25 100000000000010010000000000000000000110111011011011010101110110001 step 26 100000000000010010000000000000000000110111011011011010100110110001 step 27 100000000000010010000000000000000000110111011011011010100111110111 step 28 100000000000010010000000000000000000110111011011011010100110110111 step 29 100000000000000010000000000000000001110110011011011010100110110111 step 30 100000000000000000000000000000000001111100011011011010100110110111 step 31 100000000000000000000000000000000001111100011011011010100110110111 step 32 100001000000000000000000000000000001111100011011011010100110110111 step 33 100001100000000000000000000000000001111100011011011010100110110111 step 34 100001100100000000000000000000000001111100011011011010100110110111 step 35 100001100110000000000000000000000001111100011011011010100110110111 step 36 100001100110100000000000000000000001111100011011011010100110110111 step 37 100001100110100100000000000000000001111100011011011010100110110111 step 38 100001100110100100010000000000000001111100011011011010100110110111 step 39 100001100110100100011000000000000001111100011011011010100110110111 step 40 100001100110100100011010000000000001111100011011011010100110110111 step 41 100001100110100100011011000000000001111100011011011010100110110111 step 42 100001100110100100011011010000000001111100011011011010100110110111 step 43 100001100110100100011011011000000001111100011011011010100110110111 step 44 100001100110100100011011011010000001111100011011011010100110110111 step 45 100001100110100100011011011011000001111100011011011010100110110111 step 46 100001100110100100011011011011010001111100011011011010100110110111 step 47 100001100110100100011011011011011001111100011011011010100110110111 step 48 100001100110100100011011011011011101111100011011011010100110110111 step 49 110001100110100100011011011011011100110111011011011010100110110111 step 50 100001100110100100011011011011011101111100011011011010100110110111 step 51 101001100110100100011011011011011100110111011011011010100110110111 step 52 100001100110100100011011011011011101111100011011011010100110110111 step 53 100101100110100100011011011011011100110111011011011010100110110111 step 54 100001100110100100011011011011011101111100011011011010100110110111 step 55 100011100110100100011011011011011100110111011011011010100110110111 step 56 100001100110100100011011011011011101111100011011011010100110110111 step 57 100001110110100100011011011011011100110111011011011010100110110111 step 58 100001100110100100011011011011011101111100011011011010100110110111 step 59 100001101110100100011011011011011100110111011011011010100110110111 step 60 100001100110100100011011011011011101111100011011011010100110110111 step 61 100001100111100100011011011011011100111101011011011010100110110111 step 62 100001100110100100011011011011011101111100011011011010100110110111 step 63 100001100110110100011011011011011100111101011011011010100110110111 step 64 100001100110100100011011011011011101111100011011011010100110110111 step 65 100001100110101100011011011011011101110110011011011010100110110111 step 66 100001100110100100011011011011011101111100011011011010100110110111 step 67 100001100110100110011011011011011101110110011011011010100110110111 step 68 100001100110100100011011011011011101111100011011011010100110110111 step 69 100001100110100101011011011011011101001111011011011010100110110111 step 70 100001100110100100011011011011011101111100011011011010100110110111 step 71 100001100110100100111011011011011101001111011011011010100110110111 step 72 100001100110100100011011011011011101111100011011011010100110110111 step 73 100001100110100100011111011011011101001111011011011010100110110111 step 74 100001100110100100011011011011011101111100011011011010100110110111 step 75 100001100110100100011011111011011101001111011011011010100110110111 step 76 100001100110100100011011011011011101111100011011011010100110110111 step 77 100001100110100100011011011111011101001111011011011010100110110111 step 78 100001100110100100011011011011011101111100011011011010100110110111 step 79 100001100110100100011011011011111101001111011011011010100110110111 step 80 100001100110100100011011011011011101111100011011011010100110110111 step 81 100001100110100100011011011011011111101110011011011010100110110111 step 82 100001100110100100011011011011011101111100011011011010100110110111 step 83 100000000000000000000000000000000001111100011011011010100110110111 step 84 100000000000000000000000000000000001111100011011011010100110100111 step 85 100000000000000000000000000000000001111100011011011010100110101101 step 86 100000000000000000000000000000000001111100011011011010100110100101 step 87 100000000000000000000000000000000001111100011011011010100110000001 step 88 100000000000000000000000000000000001111100011011011010100110100101 step 89 100000000000000000000000000000000001111100011011011010100110100101 step 90 100000000000000000000000000000000001111100011011011010100110101001 step 91 100000000000000000000000000000000001111100011011011010100110100001 step 92 100000000000000000000000000000000001111100011011011010100110000101 step 93 100000000000000000000000000000000001111100011011011010100110100001 step 94 100000000000000000000000000000000001111100011011011010100110100001 step 95 100000000000000000000000000000000001111100011011011010100110101001 step 96 100000000000000000000000000000000001111100011011011010100110100001 step 97 100000000000000000000000000000000001111100011011011010100110110001 step 98 100000000000000000000000000000000001111100011011011010100110111011 step 99 100000000000000000000000000000000001111100011011011010100110110011 step 100 100000000000000000000000000000000001111100011011011010100110110011 step 101 100000000000000000000000000000000001111100011011011010100110111111 step 102 100000000000000000000000000000000001111100011011011010100110110111 step 103 100000000000000000000000000000000001111100011011011010100110110111 step 104 100000000000000000000000000000000001111100011011011010100110111111 step 105 100000000000000000000000000000000001111100011011011010100110110111 step 106 100000000000000000000000000000000001111100011011011010100110100111 step 107 100000000000000000000000000000000001111100011011011010100110101101 step 108 100000000000000000000000000000000001111100011011011010100110100101 step 109 100000000000000000000000000000000001111100011011011010100110110101 step 110 100000000000000000000000000000000001111100011011011010100110111011 step 111 100000000000000000000000000000000001111100011011011010100110110011 step 112 100000000000000000000000000000000001111100011011011010100110100011 step 113 100000000000000000000000000000000001111100011011011010100110101101 step 114 100000000000000000000000000000000001111100011011011010100110100101 step 115 100000000000000000000000000000000001111100011011011010100110110101 step 116 100000000000000000000000000000000001111100011011011010100110111011 step 117 100000000000000000000000000000000001111100011011011010100110110011 step 118 100000000000000000000000000000000001111100011011011010100110110011 step 119 100000000000000000000000000000000001111100011011011010100110111111 step 120 100000000000000000000000000000000001111100011011011010100110110111 step 121 100000000000000000000000000000000001111100011011011010100110110111 test 1: pass SLOT BAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBAABBAAAAAAAAAAAAAABBBBBABBBB LETTER ALPSLFMDEEMCBFRSPKLEMFHRSCJLJKUHPNMBBNNVVRKRHUTDJUKANJHBTPDFSVEVDU SIDE 121212122121212121111111112212122222112222111221112112212112212122 DIRECTION IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIOOOOOOOIOOIOOIOOIOOOOIOOIIIIOOO this fail all fails was hi 111111111111111111111111111111111111111111111111111111111111111111 rising ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ ^^^^^^^^^^^^^ ^ ^^^^^^^^^ falling vvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvv vvvv vv v v v vvv vvvvvv was lo 00000000000000000000000000000000000000 0000000000000000000000000 total fails 0, total passes 1 space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C toggle comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit failure mode analysis: space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C toggle comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit up to this point: PINS that are always low PINS that are always high 1 I BA1 CARRY IN-N, (TO E9-5 7482 C0) C-N TO ADDER2 40 O AV2 CARRY OUT-N (E9-10 7482 C2) 66 O BU2 +3.5V space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C toggle comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT BAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBAABBAAAAAAAAAAAAAABBBBBABBBB LETTER ALPSLFMDEEMCBFRSPKLEMFHRSCJLJKUHPNMBBNNVVRKRHUTDJUKANJHBTPDFSVEVDU SIDE 121212122121212121111111112212122222112222111221112112212112212122 DIRECTION IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIOOOOOOOIOOIOOIOOIOOOOIOOIIIIOOO all fails was lo 00000000000000000000000000000000000000 0000000000000000000000000 falling vvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvv vvvv vv v v v vvv vvvvvv rising ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ ^^^^^^^^^^^^^ ^ ^^^^^^^^^ was hi 111111111111111111111111111111111111111111111111111111111111111111 total fails 0, total passes 1 Main menu Thu Aug 20 17:12:11 2015 test file is: tests\m222.new delay is: 0 trigger is: 1 1 read test file 2 set test delay 3 set test trigger 4 run test 5 output loading test 8 diags 9 exit Enter test file name? trying to open test file: tests\m222.new reading test file: tests\m222.new comment: M222 PCB REV B SCHEMATIC REV A LINC TAPE REGISTERS comment: comment: TERMINOLOGY- SIGNALS REFER TO PDP12 MAINT VOL4 M222 SCHEMATIC. comment: comment: BUT... comment: comment: DEC USES AND-NOR GATES TO ROUTE THE ADDER A AND B INPUTS, SO... comment: DEC RENAMED THE ADDER TO NEGATIVE LOGIC TERMS (I.E. A-N + B-N + C-N -> SUM-N, C1-N). comment: (NOT THE 7482 DATASHEET NAMES OF A + B + C -> SUM, C1). comment: comment: SO, WITH ALL 'AND ENABLES' LOW, THE AND-NOR OUTPUTS = HIGH. comment: WITH C-L HIGH, THE ADDER OUTPUT IS SUM-N=1, C1-N=1; comment: THE INVERTED ADDER OUTPUT IS LOW (TAPE BUS). comment: AND THERE IS NO CARRY (C1-N IS HI). comment: comment: THE TWO ADDERS, TWO REGISTER BITS, ETC ARE LABELED BIT 2 (EVEN, MSB) AND BIT 3 (ODD, LSB). comment: THE ADDERS ARE REFERRED TO AS 'ADDER2' (MSB) AND 'ADDER3' (LSB). comment: comment: POWER PINS: comment: AA2 +5V comment: AT1 GROUND comment: AC2 GROUND comment: BA2 +5V comment: BT1 GROUND comment: BC2 GROUND comment: comment: (ALL PINS ARE USED). comment: comment: pins: PINS pins: 1 I BA1 CARRY IN-N, (TO E9-5 7482 C0) C-N TO ADDER2 pins: 2 I AL2 AND-NOR ENABLE: TAC TAC3 TO PIN BB2 (TO ADDER3) TAC2 TO PIN AN2 (TO ADDER2) pins: 3 I AP1 AND-NOR ENABLE: TMA SETUP (TMAS)3 TO PIN BB2 (TO ADDER3), (TMAS)3 TO PIN AN2 (TO ADDER2) pins: 4 I AS2 AND-NOR ENABLE: TMA TMA3 TO PIN BB2 (TO ADDER3), TMA2 TO PIN AN2 (TO ADDER2) pins: 5 I AL1 AND-NOR ENABLE: PIN AF2 TO PIN BB2 (TO ADDER3), PIN AM1 TO PIN AN2 (TO ADDER2) pins: 6 I AF2 AND-NOR INPUT (AL1 ENABLES) TO PIN BB2 (TO ADDER3). pins: 7 I AM1 AND-NOR INPUT (AL1 ENABLES) TO PIN AN2 (TO ADDER2) pins: 8 I AD2 AND-NOR ENABLE: RWB RWB3 TO PIN BB2 (TO ADDER3), RWB2 TO PIN AN2 (TO ADDER2) pins: 9 I AE2 AND-NOR ENABLE: PIN AE1 TO PIN BB2 (TO ADDER3), PIN AM2 TO PIN AN2 (TO ADDER2) pins: 10 I AE1 AND-NOR INPUT (AE2 ENABLES) TO PIN BB2 (TO ADDER3). pins: 11 I AM2 AND-NOR INPUT (AE2 ENABLES) TO PIN AN2 (TO ADDER2) pins: 12 I AC1 AND-NOR INPUT, AND WITH PIN AB2 TO PIN BB2 (TO ADDER3) pins: 13 I AB2 AND-NOR INPUT, AND WITH PIN AC1 TO PIN BB2 (TO ADDER3) pins: 14 I AF1 AND-NOR INPUT (AND WITH ITSELF) TO PIN BB2 (TO ADDER3) pins: 15 I AR2 AND-NOR INPUT, AND WITH PIN AS1 TO PIN AN2 (TO ADDER2) pins: 16 I AS1 AND-NOR INPUT, AND WITH PIN AR2 TO PIN AN2 (TO ADDER2) pins: 17 I AP2 AND-NOR INPUT (AND WITH ITSELF) TO PIN AN2 (TO ADDER2) pins: 18 I BK1 AND-NOR ENABLE: TB3 TO PIN BB1 (TO ADDER3), TB2 TO PIN BN1 (TO ADDER2) pins: 19 I BL1 AND-NOR ENABLE: PIN BE1 TO PIN BB1 (TO ADDER3), PIN BM1 TO PIN BN1 (TO ADDER2) pins: 20 I BE1 AND-NOR INPUT (BL1 ENABLES) TO PIN BB1 (TO ADDER3). pins: 21 I BM1 AND-NOR INPUT (BL1 ENABLES) TO PIN BN1 (TO ADDER2) pins: 22 I BF1 AND-NOR ENABLE: PIN BH1 TO PIN BB1 (TO ADDER3), PIN BR1 TO PIN BN1 (TO ADDER2) pins: 23 I BH1 AND-NOR INPUT (BF1 ENABLES): TO PIN BB1 (TO ADDER3), pins: 24 I BR1 AND-NOR INPUT (BF1 ENABLES): TO PIN BN1 (TO ADDER2) pins: 25 I BS1 AND-NOR ENABLE: PIN BC1 TO PIN BB1 (TO ADDER3), PIN BJ2 TO PIN BN1 (TO ADDER2) pins: 26 I BC1 AND-NOR INPUT (BS1 ENABLES): TO PIN BB1 (TO ADDER3), pins: 27 I BJ2 AND-NOR INPUT (BS1 ENABLES): TO PIN BN1 (TO ADDER2) pins: 28 I BL2 AND-NOR ENABLE: PIN BJ1 TO PIN BB1 (TO ADDER3), PIN BK2 TO PIN BN1 (TO ADDER2) pins: 29 I BJ1 AND-NOR INPUT (BL2 ENABLES): TO PIN BB1 (TO ADDER3), pins: 30 I BK2 AND-NOR INPUT (BL2 ENABLES): TO PIN BN1 (TO ADDER2) pins: 31 I BU1 AND-NOR ENABLE: PIN BH2 TO PIN BB1 (TO ADDER3), PIN BP2 TO PIN BN1 (TO ADDER2) pins: 32 I BH2 AND-NOR INPUT (BU1 ENABLES): TO PIN BB1 (TO ADDER3), pins: 33 I BP2 AND-NOR INPUT (BU1 ENABLES): TO PIN BN1 (TO ADDER2) pins: 34 I BN2 AND-NOR INPUT (AND WITH BM2): TO PIN BN1 (TO ADDER2) pins: 35 I BM2 AND-NOR INPUT (AND WITH BM2): TO PIN BN1 (TO ADDER2) pins: 36 O BB2 AND-NOR OUTPUT, (DRIVES E9-2 7482 A1) TO ADDER3 INPUT pins: 37 O BB1 AND-NOR OUTPUT, (DRIVES E9-3 7482 B1) TO ADDER3 INPUT pins: 38 O BN1 AND-NOR OUTPUT, (DRIVES E9-14 7482 A2) TO ADDER2 INPUT pins: 39 O AN2 AND-NOR OUTPUT, (DRIVES E9-13 7482 B2) TO ADDER2 INPUT pins: 40 O AV2 CARRY OUT-N (E9-10 7482 C2) pins: 41 O BV2 TAPE BUS 2 OUTPUT (INVERTED ADDER2 SUM-N (E9-12 7482 SUM2) pins: 42 O BR2 TAPE BUS 3 OUTPUT (INVERTED ADDER3 SUM-N (E9-1 7482 SUM1) pins: 43 I AK1 LOAD TMA SETUP (FROM TAPE BUS) (RISING EDGE CLOCK) pins: 44 O AR1 TMA SETUP 2 pins: 45 O AH1 TMA SETUP 3 pins: 46 I AU2 LOAD TMA (FROM TAPE BUS) (RISING EDGE CLOCK) pins: 47 O AT2 TMA 2 pins: 48 O AD1 TMA 3 pins: 49 I AJ1 LOAD TBN (FROM TAPE BUS) (RISING EDGE CLOCK) pins: 50 O AU1 TBN 2 pins: 51 O AK2 TBN 3 pins: 52 I AA1 LOAD TAC (FROM TAPE BUS) (RISING EDGE CLOCK) pins: 53 O AN1 TAC 2 pins: 54 O AJ2 TAC 2-N pins: 55 O AH2 TAC 3 pins: 56 O AB1 TAC 3-N pins: 57 I BT2 LOAD TB (FROM TAPE BUS) (RISING EDGE CLOCK) pins: 58 O BP1 TB 2 pins: 59 O BD1 TB 3 pins: 60 I BF2 LOAD RWB (FROM TB) (JAMS CLEAR,SET) pins: 61 I BS2 PHASE (SELECTS POLARITY OF RWB OUT, 0 -> INVERTED) pins: 62 I AV1 RWB IN (SHIFTED INTO RWB 3) pins: 63 I BE2 SHIFT RWB (SHIFTS PIN AV1 INTO RWB 3, SHIFTS RWB3 TO RWB2) (RISING CLOCK) pins: 64 O BV1 RWB OUT (IF PHASE=1, =RWB 2; IF PHASE=0; =RWB 2-N) pins: 65 O BD2 RWB 3 pins: 66 O BU2 +3.5V pins: direction: IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIOOOOOOOIOOIOOIOOIOOOOIOOIIIIOOO comment: ; all registers are unknown comment: ; turn on C0, PHASE comment: ; with no ENABLES, BUS2,BUS3 is 11, C2 is 1 test 1: 1000000000000000000000000000000000011111000XX0XX0XX0XXXX0XX0110XX1 comment: comment: ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; comment: ; comment: ; set all registers LOW comment: ; comment: ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; comment: comment: ; load TMA SETUP from tape bus (00) test 2: 100 test 3: 0 comment: ; load TMA from tape bus (00) test 4: 100 test 5: 0 comment: ; load TBN from tape bus (00) test 6: 100 test 7: 0 comment: ; load TAC from tape bus (00) test 8: 10101 test 9: 0 comment: ; load TB from tape bus (00) test 10: 100 test 11: 0 comment: ; load RWB from TB (JAMS CLEAR AND PRESET) test 12: 1 00 test 13: 0 comment: ; (no change) test 14: 100000000000000000000000000000000001111100000000000001010000110001 comment: comment: comment: ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; comment: ; comment: ; set all registers HIGH comment: ; comment: ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; comment: comment: ; set pin AF1 which clears pin BB2 and sets pin BR2 TAPE BUS 3 OUTPUT test 15: 1 0 1 comment: ; set pin AP2 which clears pin AN2 and sets pin BV2 TAPE BUS 2 OUTPUT test 16: 1 0 1 comment: comment: comment: ; load TMA SETUP from tape bus (11) test 17: 111 test 18: 0 comment: ; load TMA from tape bus (11) test 19: 111 test 20: 0 comment: ; load TBN from tape bus (11) test 21: 111 test 22: 0 comment: ; load TAC from tape bus (11) test 23: 11010 test 24: 0 comment: ; load TB from tape bus (11) test 25: 111 test 26: 0 comment: ; load RWB from TB (JAMS CLEAR AND PRESET) test 27: 1 11 test 28: 0 comment: ; clear pin AF1 (AND with itself) to set pin BB2 (AND-NOR output) and clear pin BR2 TAPE BUS 3 OUTPUT test 29: 0 1 0 comment: ; clear pin AP2 (AND with itself) to set pin AN2 (AND-NOR output) and clear pin BV2 TAPE BUS 2 OUTPUT test 30: 0 1 0 comment: ; (no change) test 31: 100000000000000000000000000000000001111100011011011010100110110111 comment: comment: ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; comment: ; comment: ; will all registers high, walk a 0 comment: ; comment: ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; comment: comment: comment: ; walk a 0, TMA SETUP 2 comment: comment: comment: ; clear pin AP2 which sets pin AN2 and clears pin BV2 TAPE BUS 2 OUTPUT test 32: 1 0 1 comment: ; set pin AF1 which clears pin BB2 and sets pin BR2 TAPE BUS 3 OUTPUT test 33: 1 0 1 comment: ; load TMA SETUP from tape bus (01) test 34: 101 test 35: 0 comment: ; restore TMA SETUP 2 comment: ; set pin AP2 which clears pin AN2 and sets pin BV2 TAPE BUS 2 OUTPUT test 36: 1 0 1 comment: ; load TMA SETUP from tape bus (11) test 37: 111 test 38: 0 comment: comment: comment: ; walk a 0, TMA SETUP 3 comment: comment: comment: ; set pin AP2 which clears pin AN2 and sets pin BV2 TAPE BUS 2 OUTPUT test 39: 1 0 1 comment: ; clear pin AF1 which sets pin BB2 and clears pin BR2 TAPE BUS 3 OUTPUT test 40: 0 0 1 comment: ; load TMA SETUP from tape bus (10) test 41: 110 test 42: 0 comment: ; restore TMA SETUP 3 comment: ; set pin AF1 which clears pin BB2 and sets pin BR2 TAPE BUS 3 OUTPUT test 43: 1 0 1 comment: ; load TMA SETUP from tape bus (11) test 44: 111 test 45: 0 comment: comment: comment: ; walk a 0, TMA 2 comment: comment: comment: ; clear pin AP2 which sets pin AN2 and clears pin BV2 TAPE BUS 2 OUTPUT test 46: 1 0 1 comment: ; set pin AF1 which clears pin BB2 and sets pin BR2 TAPE BUS 3 OUTPUT test 47: 1 0 1 comment: ; load TMA from tape bus (01) test 48: 101 test 49: 0 comment: ; restore TMA 2 comment: ; set pin AP2 which clears pin AN2 and sets pin BV2 TAPE BUS 2 OUTPUT test 50: 1 0 1 comment: ; load TMA from tape bus (11) test 51: 111 test 52: 0 comment: comment: comment: ; walk a 0, TMA 3 comment: comment: comment: ; set pin AP2 which clears pin AN2 and sets pin BV2 TAPE BUS 2 OUTPUT test 53: 1 0 1 comment: ; clear pin AF1 which sets pin BB2 and clears pin BR2 TAPE BUS 3 OUTPUT test 54: 0 0 1 comment: ; load TMA from tape bus (10) test 55: 110 test 56: 0 comment: ; restore TMA 3 comment: ; set pin AF1 which clears pin BB2 and sets pin BR2 TAPE BUS 3 OUTPUT test 57: 1 0 1 comment: ; load TMA from tape bus (11) test 58: 111 test 59: 0 comment: comment: comment: comment: comment: comment: comment: comment: comment: comment: comment: comment: ; load TBN from tape bus (00) test 60: 100 test 61: 0 comment: ; load TAC from tape bus (00) test 62: 10101 test 63: 0 comment: ; load TB from tape bus (00) test 64: 100 test 65: 0 comment: ; load RWB from TB (JAMS CLEAR AND PRESET) test 66: 1 00 test 67: 0 comment: comment: comment: comment: comment: comment: comment: comment: comment: comment: comment: comment: comment: comment: comment: ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; comment: ; comment: ; test AND-NOR logic comment: ; comment: ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; comment: comment: ; (all registers are HIGH) comment: ; set all pins HIGH except ENABLES comment: comment: ; set pin AF2 HIGH test 68: 1 comment: ; set pin AM1 HIGH test 69: 1 comment: ; set pin AE1 HIGH test 70: 1 comment: ; set pin AM2 HIGH test 71: 1 comment: ; set pin AB2 HIGH test 72: 1 comment: ; set pin AS1 HIGH test 73: 1 comment: ; set pin BE1 HIGH test 74: 1 comment: ; set pin BM1 HIGH test 75: 1 comment: ; set pin BH1 HIGH test 76: 1 comment: ; set pin BR1 HIGH test 77: 1 comment: ; set pin BC1 HIGH test 78: 1 comment: ; set pin BJ2 HIGH test 79: 1 comment: ; set pin BJ1 HIGH test 80: 1 comment: ; set pin BK2 HIGH test 81: 1 comment: ; set pin BH2 HIGH test 82: 1 comment: ; set pin BP2 HIGH test 83: 1 comment: ; set pin BN2 HIGH test 84: 1 comment: ; toggle each ENABLE comment: comment: ; set pin AL2 to clear pin BB2 and pin AN2 AND-NOR OUTPUTS and set TAPE BUS 2 OUTPUT and TAPE BUS 3 OUTPUT test 85: 1 0 0 11 test 86: 0 1 1 00 comment: ; set pin AP1 to clear pin BB2 and pin AN2 AND-NOR OUTPUTS and set TAPE BUS 2 OUTPUT and TAPE BUS 3 OUTPUT test 87: 1 0 0 11 test 88: 0 1 1 00 comment: ; set pin AS2 to clear pin BB2 and pin AN2 AND-NOR OUTPUTS and set TAPE BUS 2 OUTPUT and TAPE BUS 3 OUTPUT test 89: 1 0 0 11 test 90: 0 1 1 00 comment: ; set pin AL1 to clear pin BB2 and pin AN2 AND-NOR OUTPUTS and set TAPE BUS 2 OUTPUT and TAPE BUS 3 OUTPUT test 91: 1 0 0 11 test 92: 0 1 1 00 comment: ; set pin AL1 to clear pin BB2 and pin AN2 AND-NOR OUTPUTS and set TAPE BUS 2 OUTPUT and TAPE BUS 3 OUTPUT test 93: 1 0 0 11 test 94: 0 1 1 00 comment: ; set pin AE2 to clear pin BB2 and pin AN2 AND-NOR OUTPUTS and set TAPE BUS 2 OUTPUT and TAPE BUS 3 OUTPUT test 95: 1 0 0 11 test 96: 0 1 1 00 comment: ; set pin AC1 to clear pin BB2 and set TAPE BUS 3 OUTPUT test 97: 1 0 1 test 98: 0 1 0 comment: ; set pin AF1 to clear pin BB2 and set TAPE BUS 3 OUTPUT test 99: 1 0 1 test 100: 0 1 0 comment: ; set pin AR2 to clear pin AN2 AND-NOR OUTPUTS and set TAPE BUS 2 OUTPUT test 101: 1 0 1 test 102: 0 1 0 comment: ; set pin AP2 to clear pin AN2 AND-NOR OUTPUTS and set TAPE BUS 2 OUTPUT test 103: 1 0 1 test 104: 0 1 0 comment: comment: ; set pin BK1 to clear pin BB1 and pin BN1 AND-NOR OUTPUTS and set TAPE BUS 2 OUTPUT and TAPE BUS 3 OUTPUT test 105: 1 00 11 test 106: 0 11 00 comment: ; set pin BL1 to clear pin BB1 and pin BN1 AND-NOR OUTPUTS and set TAPE BUS 2 OUTPUT and TAPE BUS 3 OUTPUT test 107: 1 00 11 test 108: 0 11 00 comment: ; set pin BF1 to clear pin BB1 and pin BN1 AND-NOR OUTPUTS and set TAPE BUS 2 OUTPUT and TAPE BUS 3 OUTPUT test 109: 1 00 11 test 110: 0 11 00 comment: ; set pin BS1 to clear pin BB1 and pin BN1 AND-NOR OUTPUTS and set TAPE BUS 2 OUTPUT and TAPE BUS 3 OUTPUT test 111: 1 00 11 test 112: 0 11 00 comment: ; set pin BL2 to clear pin BB1 and pin BN1 AND-NOR OUTPUTS and set TAPE BUS 2 OUTPUT and TAPE BUS 3 OUTPUT test 113: 1 00 11 test 114: 0 11 00 comment: ; set pin BU1 to clear pin BB1 and pin BN1 AND-NOR OUTPUTS and set TAPE BUS 2 OUTPUT and TAPE BUS 3 OUTPUT test 115: 1 00 11 test 116: 0 11 00 comment: ; set pin BM2 to clear pin BB1 and TAPE BUS 3 OUTPUT test 117: 1 0 1 test 118: 0 1 0 comment: ; no change test 119: 100000000000000000000000000000000001111100011011011010100110110111 comment: comment: ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; comment: ; test shifting the RWB comment: ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; comment: comment: ; shift in 0, expect 10 test 120: 0 test 121: 110 test 122: 0 comment: ; toggle phase should toggle RWB 2 test 123: 0 0 test 124: 1 1 comment: comment: ; shift in 0, expect 00 test 125: 0 test 126: 100 test 127: 0 comment: ; toggle phase should toggle RWB 2 test 128: 0 1 test 129: 1 0 comment: comment: ; shift in 0, expect 00 test 130: 0 test 131: 100 test 132: 0 comment: ; shift in 1, expect 01 test 133: 1 test 134: 101 test 135: 0 comment: ; shift in 1, expect 11 test 136: 1 test 137: 111 test 138: 0 comment: ; shift in 1, expect 11 test 139: 1 test 140: 111 test 141: 0 comment: ; shift in 0, expect 10 test 142: 0 test 143: 110 test 144: 0 comment: ; shift in 1, expect 01 test 145: 1 test 146: 101 test 147: 0 comment: ; shift in 0, expect 10 test 148: 0 test 149: 110 test 150: 0 comment: ; shift in 1, expect 01 test 151: 1 test 152: 101 test 153: 0 comment: ; shift in 1, expect 11 test 154: 1 test 155: 111 test 156: 0 comment: ; no change test 157: 100000000000000000000000000000000001111100011011011010100110110111 comment: comment: ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; comment: ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; comment: ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; comment: ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; comment: ; needs work (more adder tests, more register tests) comment: ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; comment: ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; comment: ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; comment: ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; end: END summary column 1: offset 2, mask 0x2000 column 2: offset 1, mask 0x0002 column 3: offset 1, mask 0x0800 column 4: offset 1, mask 0x0040 column 5: offset 1, mask 0x4000 column 6: offset 0, mask 0x0004 column 7: offset 1, mask 0x2000 column 8: offset 0, mask 0x0010 column 9: offset 0, mask 0x0008 column 10: offset 0, mask 0x0800 column 11: offset 1, mask 0x0004 column 12: offset 0, mask 0x2000 column 13: offset 0, mask 0x0040 column 14: offset 0, mask 0x0400 column 15: offset 1, mask 0x0020 column 16: offset 1, mask 0x0200 column 17: offset 1, mask 0x0010 column 18: offset 3, mask 0x2000 column 19: offset 3, mask 0x1000 column 20: offset 2, mask 0x0200 column 21: offset 3, mask 0x0800 column 22: offset 2, mask 0x0100 column 23: offset 3, mask 0x8000 column 24: offset 3, mask 0x0100 column 25: offset 4, mask 0x8000 column 26: offset 2, mask 0x0800 column 27: offset 3, mask 0x0002 column 28: offset 3, mask 0x0008 column 29: offset 3, mask 0x4000 column 30: offset 3, mask 0x0004 column 31: offset 4, mask 0x2000 column 32: offset 3, mask 0x0001 column 33: offset 3, mask 0x0040 column 34: offset 3, mask 0x0020 column 35: offset 3, mask 0x0010 column 36: offset 2, mask 0x0008 column 37: offset 2, mask 0x1000 column 38: offset 3, mask 0x0400 column 39: offset 1, mask 0x0008 column 40: offset 2, mask 0x0002 column 41: offset 4, mask 0x0008 column 42: offset 3, mask 0x0080 column 43: offset 1, mask 0x8000 column 44: offset 1, mask 0x0400 column 45: offset 0, mask 0x0200 column 46: offset 2, mask 0x0001 column 47: offset 1, mask 0x0080 column 48: offset 0, mask 0x1000 column 49: offset 0, mask 0x0100 column 50: offset 2, mask 0x8000 column 51: offset 1, mask 0x0001 column 52: offset 0, mask 0x8000 column 53: offset 1, mask 0x1000 column 54: offset 0, mask 0x0001 column 55: offset 0, mask 0x0002 column 56: offset 0, mask 0x4000 column 57: offset 4, mask 0x0002 column 58: offset 3, mask 0x0200 column 59: offset 2, mask 0x0400 column 60: offset 2, mask 0x0080 column 61: offset 4, mask 0x0001 column 62: offset 2, mask 0x4000 column 63: offset 2, mask 0x0040 column 64: offset 4, mask 0x1000 column 65: offset 2, mask 0x0020 column 66: offset 4, mask 0x0004 direction bits (1=input) 0x52A3 0x1589 0x943A 0x0680 0x50FC pullup bits (1=pullup) 0x0000 0x0000 0x0000 0x0000 0x0000 test step out_data dont care 1: 0x0000 0x0008 0x700A 0x0400 0x0005 0x5203 0x1481 0x8420 0x0200 0x1000 2: 0x0000 0x8008 0x700A 0x0400 0x0005 0x5003 0x1081 0x8420 0x0200 0x1000 3: 0x0000 0x0008 0x700A 0x0400 0x0005 0x5003 0x1081 0x8420 0x0200 0x1000 4: 0x0000 0x0008 0x700B 0x0400 0x0005 0x4003 0x1001 0x8420 0x0200 0x1000 5: 0x0000 0x0008 0x700A 0x0400 0x0005 0x4003 0x1001 0x8420 0x0200 0x1000 6: 0x0100 0x0008 0x700A 0x0400 0x0005 0x4003 0x1000 0x0420 0x0200 0x1000 7: 0x0000 0x0008 0x700A 0x0400 0x0005 0x4003 0x1000 0x0420 0x0200 0x1000 8: 0xC001 0x0008 0x700A 0x0400 0x0005 0x0000 0x0000 0x0420 0x0200 0x1000 9: 0x4001 0x0008 0x700A 0x0400 0x0005 0x0000 0x0000 0x0420 0x0200 0x1000 10: 0x4001 0x0008 0x700A 0x0400 0x0007 0x0000 0x0000 0x0020 0x0000 0x1000 11: 0x4001 0x0008 0x700A 0x0400 0x0005 0x0000 0x0000 0x0020 0x0000 0x1000 12: 0x4001 0x0008 0x708A 0x0400 0x0005 13: 0x4001 0x0008 0x700A 0x0400 0x0005 14: 0x4001 0x0008 0x700A 0x0400 0x0005 15: 0x4401 0x0008 0x7002 0x0480 0x0005 16: 0x4401 0x0010 0x7002 0x0480 0x000D 17: 0x4601 0x8410 0x7002 0x0480 0x000D 18: 0x4601 0x0410 0x7002 0x0480 0x000D 19: 0x5601 0x0490 0x7003 0x0480 0x000D 20: 0x5601 0x0490 0x7002 0x0480 0x000D 21: 0x5701 0x0491 0xF002 0x0480 0x000D 22: 0x5601 0x0491 0xF002 0x0480 0x000D 23: 0x9602 0x1491 0xF002 0x0480 0x000D 24: 0x1602 0x1491 0xF002 0x0480 0x000D 25: 0x1602 0x1491 0xF402 0x0680 0x000F 26: 0x1602 0x1491 0xF402 0x0680 0x000D 27: 0x1602 0x1491 0xF4A2 0x0680 0x100D 28: 0x1602 0x1491 0xF422 0x0680 0x100D 29: 0x1202 0x1491 0xF42A 0x0600 0x100D 30: 0x1202 0x1489 0xF42A 0x0600 0x1005 31: 0x1202 0x1489 0xF42A 0x0600 0x1005 32: 0x1202 0x1491 0xF42A 0x0600 0x100D 33: 0x1602 0x1491 0xF422 0x0680 0x100D 34: 0x1602 0x9091 0xF422 0x0680 0x100D 35: 0x1602 0x1091 0xF422 0x0680 0x100D 36: 0x1602 0x1091 0xF422 0x0680 0x100D 37: 0x1602 0x9491 0xF422 0x0680 0x100D 38: 0x1602 0x1491 0xF422 0x0680 0x100D 39: 0x1602 0x1491 0xF422 0x0680 0x100D 40: 0x1202 0x1491 0xF422 0x0680 0x100D 41: 0x1002 0x9491 0xF422 0x0680 0x100D 42: 0x1002 0x1491 0xF422 0x0680 0x100D 43: 0x1402 0x1491 0xF422 0x0680 0x100D 44: 0x1602 0x9491 0xF422 0x0680 0x100D 45: 0x1602 0x1491 0xF422 0x0680 0x100D 46: 0x1602 0x1491 0xF422 0x0680 0x100D 47: 0x1602 0x1491 0xF422 0x0680 0x100D 48: 0x1602 0x1411 0xF423 0x0680 0x100D 49: 0x1602 0x1411 0xF422 0x0680 0x100D 50: 0x1602 0x1411 0xF422 0x0680 0x100D 51: 0x1602 0x1491 0xF423 0x0680 0x100D 52: 0x1602 0x1491 0xF422 0x0680 0x100D 53: 0x1602 0x1491 0xF422 0x0680 0x100D 54: 0x1202 0x1491 0xF422 0x0680 0x100D 55: 0x0202 0x1491 0xF423 0x0680 0x100D 56: 0x0202 0x1491 0xF422 0x0680 0x100D 57: 0x0602 0x1491 0xF422 0x0680 0x100D 58: 0x1602 0x1491 0xF423 0x0680 0x100D 59: 0x1602 0x1491 0xF422 0x0680 0x100D 60: 0x1702 0x1490 0x7422 0x0680 0x100D 61: 0x1602 0x1490 0x7422 0x0680 0x100D 62: 0xD601 0x0490 0x7422 0x0680 0x100D 63: 0x5601 0x0490 0x7422 0x0680 0x100D 64: 0x5601 0x0490 0x7022 0x0480 0x100F 65: 0x5601 0x0490 0x7022 0x0480 0x100D 66: 0x5601 0x0490 0x7082 0x0480 0x000D 67: 0x5601 0x0490 0x7002 0x0480 0x000D 68: 0x5605 0x0490 0x7002 0x0480 0x000D 69: 0x5605 0x2490 0x7002 0x0480 0x000D 70: 0x5E05 0x2490 0x7002 0x0480 0x000D 71: 0x5E05 0x2494 0x7002 0x0480 0x000D 72: 0x5E45 0x2494 0x7002 0x0480 0x000D 73: 0x5E45 0x2694 0x7002 0x0480 0x000D 74: 0x5E45 0x2694 0x7202 0x0480 0x000D 75: 0x5E45 0x2694 0x7202 0x0C80 0x000D 76: 0x5E45 0x2694 0x7202 0x8C80 0x000D 77: 0x5E45 0x2694 0x7202 0x8D80 0x000D 78: 0x5E45 0x2694 0x7A02 0x8D80 0x000D 79: 0x5E45 0x2694 0x7A02 0x8D82 0x000D 80: 0x5E45 0x2694 0x7A02 0xCD82 0x000D 81: 0x5E45 0x2694 0x7A02 0xCD86 0x000D 82: 0x5E45 0x2694 0x7A02 0xCD87 0x000D 83: 0x5E45 0x2694 0x7A02 0xCDC7 0x000D 84: 0x5E45 0x2694 0x7A02 0xCDE7 0x000D 85: 0x5E45 0x2696 0x7A02 0xCDE7 0x000D 86: 0x5E45 0x269C 0x7A0A 0xCD67 0x0005 87: 0x5E45 0x2E94 0x7A02 0xCDE7 0x000D 88: 0x5E45 0x269C 0x7A0A 0xCD67 0x0005 89: 0x5E45 0x26D4 0x7A02 0xCDE7 0x000D 90: 0x5E45 0x269C 0x7A0A 0xCD67 0x0005 91: 0x5E45 0x6694 0x7A02 0xCDE7 0x000D 92: 0x5E45 0x269C 0x7A0A 0xCD67 0x0005 93: 0x5E55 0x2694 0x7A02 0xCDE7 0x000D 94: 0x5E45 0x269C 0x7A0A 0xCD67 0x0005 95: 0x5E4D 0x2694 0x7A02 0xCDE7 0x000D 96: 0x5E45 0x269C 0x7A0A 0xCD67 0x0005 97: 0x7E45 0x269C 0x7A02 0xCDE7 0x0005 98: 0x5E45 0x269C 0x7A0A 0xCD67 0x0005 99: 0x5E45 0x269C 0x7A02 0xCDE7 0x0005 100: 0x5A45 0x269C 0x7A0A 0xCD67 0x0005 101: 0x5A45 0x26B4 0x7A0A 0xCD67 0x000D 102: 0x5A45 0x269C 0x7A0A 0xCD67 0x0005 103: 0x5A45 0x2694 0x7A0A 0xCD67 0x000D 104: 0x5A45 0x268C 0x7A0A 0xCD67 0x0005 105: 0x5A45 0x268C 0x6A0A 0xE9E7 0x000D 106: 0x5A45 0x268C 0x7A0A 0xCD67 0x0005 107: 0x5A45 0x268C 0x6A0A 0xD9E7 0x000D 108: 0x5A45 0x268C 0x7A0A 0xCD67 0x0005 109: 0x5A45 0x268C 0x6B0A 0xC9E7 0x000D 110: 0x5A45 0x268C 0x7A0A 0xCD67 0x0005 111: 0x5A45 0x268C 0x6A0A 0xC9E7 0x800D 112: 0x5A45 0x268C 0x7A0A 0xCD67 0x0005 113: 0x5A45 0x268C 0x6A0A 0xC9EF 0x000D 114: 0x5A45 0x268C 0x7A0A 0xCD67 0x0005 115: 0x5A45 0x268C 0x6A0A 0xC9E7 0x200D 116: 0x5A45 0x268C 0x7A0A 0xCD67 0x0005 117: 0x5A45 0x268C 0x7A0A 0xC977 0x000D 118: 0x5A45 0x268C 0x7A0A 0xCD67 0x0005 119: 0x1202 0x1489 0xF42A 0x0600 0x1005 120: 0x1202 0x1489 0xB42A 0x0600 0x1005 121: 0x1202 0x1489 0xB44A 0x0600 0x1005 122: 0x1202 0x1489 0xB40A 0x0600 0x1005 123: 0x1202 0x1489 0xB40A 0x0600 0x0004 124: 0x1202 0x1489 0xB40A 0x0600 0x1005 125: 0x1202 0x1489 0xB40A 0x0600 0x1005 126: 0x1202 0x1489 0xB44A 0x0600 0x0005 127: 0x1202 0x1489 0xB40A 0x0600 0x0005 128: 0x1202 0x1489 0xB40A 0x0600 0x1004 129: 0x1202 0x1489 0xB40A 0x0600 0x0005 130: 0x1202 0x1489 0xB40A 0x0600 0x0005 131: 0x1202 0x1489 0xB44A 0x0600 0x0005 132: 0x1202 0x1489 0xB40A 0x0600 0x0005 133: 0x1202 0x1489 0xF40A 0x0600 0x0005 134: 0x1202 0x1489 0xF46A 0x0600 0x0005 135: 0x1202 0x1489 0xF42A 0x0600 0x0005 136: 0x1202 0x1489 0xF42A 0x0600 0x0005 137: 0x1202 0x1489 0xF46A 0x0600 0x1005 138: 0x1202 0x1489 0xF42A 0x0600 0x1005 139: 0x1202 0x1489 0xF42A 0x0600 0x1005 140: 0x1202 0x1489 0xF46A 0x0600 0x1005 141: 0x1202 0x1489 0xF42A 0x0600 0x1005 142: 0x1202 0x1489 0xB42A 0x0600 0x1005 143: 0x1202 0x1489 0xB44A 0x0600 0x1005 144: 0x1202 0x1489 0xB40A 0x0600 0x1005 145: 0x1202 0x1489 0xF40A 0x0600 0x1005 146: 0x1202 0x1489 0xF46A 0x0600 0x0005 147: 0x1202 0x1489 0xF42A 0x0600 0x0005 148: 0x1202 0x1489 0xB42A 0x0600 0x0005 149: 0x1202 0x1489 0xB44A 0x0600 0x1005 150: 0x1202 0x1489 0xB40A 0x0600 0x1005 151: 0x1202 0x1489 0xF40A 0x0600 0x1005 152: 0x1202 0x1489 0xF46A 0x0600 0x0005 153: 0x1202 0x1489 0xF42A 0x0600 0x0005 154: 0x1202 0x1489 0xF42A 0x0600 0x0005 155: 0x1202 0x1489 0xF46A 0x0600 0x1005 156: 0x1202 0x1489 0xF42A 0x0600 0x1005 157: 0x1202 0x1489 0xF42A 0x0600 0x1005 PINs used (in edge connector order) (G=ground,P=power) SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBB LETTER ABCDEFHJKLMNPRSTUVABCDEFHJKLMNPRSTUVABCDEFHJKLMNPRSTUVABCDEFHJKLMNPRSTUV SIDE 111111111111111111222222222222222222111111111111111111222222222222222222 USAGE IOIOIIOIIIIOIOIGOIPIGIIIOOOIIOIIIOIOIOIOIIIIIIIOOIIGIOPOGOIIIIIIIIIOIIOO UUT has 44 inputs UUT has 22 outputs contains 66 pins/columns 0 pins are not used contains 157 'test steps' M222 PCB REV B SCHEMATIC REV A LINC TAPE REGISTERS TERMINOLOGY- SIGNALS REFER TO PDP12 MAINT VOL4 M222 SCHEMATIC. BUT... DEC USES AND-NOR GATES TO ROUTE THE ADDER A AND B INPUTS, SO... DEC RENAMED THE ADDER TO NEGATIVE LOGIC TERMS (I.E. A-N + B-N + C-N -> SUM-N, C1-N). (NOT THE 7482 DATASHEET NAMES OF A + B + C -> SUM, C1). SO, WITH ALL 'AND ENABLES' LOW, THE AND-NOR OUTPUTS = HIGH. WITH C-L HIGH, THE ADDER OUTPUT IS SUM-N=1, C1-N=1; THE INVERTED ADDER OUTPUT IS LOW (TAPE BUS). AND THERE IS NO CARRY (C1-N IS HI). THE TWO ADDERS, TWO REGISTER BITS, ETC ARE LABELED BIT 2 (EVEN, MSB) AND BIT 3 (ODD, LSB). THE ADDERS ARE REFERRED TO AS 'ADDER2' (MSB) AND 'ADDER3' (LSB). POWER PINS: AA2 +5V AT1 GROUND AC2 GROUND BA2 +5V BT1 GROUND BC2 GROUND (ALL PINS ARE USED). PINS Main menu Thu Aug 20 17:51:45 2015 test file is: tests\m222.new delay is: 0 trigger is: 1 1 read test file 2 set test delay 3 set test trigger 4 run test 5 output loading test 8 diags 9 exit UUT power is okay Thu Aug 20 17:51:49 2015 space single step O run once (one test, all steps) F run, stop on fail G go (run tests N run, stop on fail, no print S scope (run, no print) C toggle comment printout + increase speed (less delay) - decrease speed (more delay)(slower) Q quit test space single step O run once (one test, all steps) F run, stop on fail G go (run tests N run, stop on fail, no print S scope (run, no print) C toggle comment printout + increase speed (less delay) - decrease speed (more delay)(slower) Q quit test space single step O run once (one test, all steps) F run, stop on fail G go (run tests N run, stop on fail, no print S scope (run, no print) C toggle comment printout + increase speed (less delay) - decrease speed (more delay)(slower) Q quit test SLOT BAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBAABBAAAAAAAAAAAAAABBBBBABBBB LETTER ALPSLFMDEEMCBFRSPKLEMFHRSCJLJKUHPNMBBNNVVRKRHUTDJUKANJHBTPDFSVEVDU SIDE 121212122121212121111111112212122222112222111221112112212112212122 DIRECTION IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIOOOOOOOIOOIOOIOOIOOOOIOOIIIIOOO all fails was lo falling rising was hi total fails 0, total passes 0 Main menu Thu Aug 20 17:51:58 2015 test file is: tests\m222.new delay is: 0 trigger is: 1 1 read test file 2 set test delay 3 set test trigger 4 run test 5 output loading test 8 diags 9 exit UUT power is okay Thu Aug 20 17:52:03 2015 space single step O run once (one test, all steps) F run, stop on fail G go (run tests N run, stop on fail, no print S scope (run, no print) C toggle comment printout + increase speed (less delay) - decrease speed (more delay)(slower) Q quit test step 1 100000000000000000000000000000000001111100010010000001010110110111 step 2 100000000000000000000000000000000001111100100010000001010110110111 step 3 100000000000000000000000000000000001111100000010000001010110110111 step 4 100000000000000000000000000000000001111100000100000001010110110111 step 5 100000000000000000000000000000000001111100000000000001010110110111 step 6 100000000000000000000000000000000001111100000000100001010110110111 step 7 100000000000000000000000000000000001111100000000000001010110110111 step 8 100000000000000000000000000000000001111100000000000101010110110111 step 9 100000000000000000000000000000000001111100000000000001010110110111 step 10 100000000000000000000000000000000001111100000000000001011000110111 step 11 100000000000000000000000000000000001111100000000000001010000110111 step 12 100000000000000000000000000000000001111100000000000001010001110001 step 13 100000000000000000000000000000000001111100000000000001010000110001 step 14 100000000000000000000000000000000001111100000000000001010000110001 step 15 100000000000010000000000000000000000111101000000000001010000110001 step 16 100000000000010010000000000000000000110111000000000001010000110001 step 17 100000000000010010000000000000000000110111111000000001010000110001 step 18 100000000000010010000000000000000000110111011000000001010000110001 step 19 100000000000010010000000000000000000110111011111000001010000110001 step 20 100000000000010010000000000000000000110111011011000001010000110001 step 21 100000000000010010000000000000000000110111011011111001010000110001 step 22 100000000000010010000000000000000000110111011011011001010000110001 step 23 100000000000010010000000000000000000110111011011011110100000110001 step 24 100000000000010010000000000000000000110111011011011010100000110001 step 25 100000000000010010000000000000000000110111011011011010101110110001 step 26 100000000000010010000000000000000000110111011011011010100110110001 step 27 100000000000010010000000000000000000110111011011011010100111110111 step 28 100000000000010010000000000000000000110111011011011010100110110111 step 29 100000000000000010000000000000000001110110011011011010100110110111 step 30 100000000000000000000000000000000001111100011011011010100110110111 step 31 100000000000000000000000000000000001111100011011011010100110110111 step 32 100000000000000010000000000000000001110110011011011010100110110111 step 33 100000000000010010000000000000000000110111011011011010100110110111 SLOT BAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBAABBAAAAAAAAAAAAAABBBBBABBBB LETTER ALPSLFMDEEMCBFRSPKLEMFHRSCJLJKUHPNMBBNNVVRKRHUTDJUKANJHBTPDFSVEVDU SIDE 121212122121212121111111112212122222112222111221112112212112212122 DIRECTION IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIOOOOOOOIOOIOOIOOIOOOOIOOIIIIOOO changed: 1 step 34 100000000000010010000000000000000000110111111011011010100110110111 fail ^ SLOT BAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBAABBAAAAAAAAAAAAAABBBBBABBBB LETTER ALPSLFMDEEMCBFRSPKLEMFHRSCJLJKUHPNMBBNNVVRKRHUTDJUKANJHBTPDFSVEVDU SIDE 121212122121212121111111112212122222112222111221112112212112212122 DIRECTION IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIOOOOOOOIOOIOOIOOIOOOOIOOIIIIOOO changed: 0 step 35 100000000000010010000000000000000000110111011011011010100110110111 fail ^ SLOT BAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBAABBAAAAAAAAAAAAAABBBBBABBBB LETTER ALPSLFMDEEMCBFRSPKLEMFHRSCJLJKUHPNMBBNNVVRKRHUTDJUKANJHBTPDFSVEVDU SIDE 121212122121212121111111112212122222112222111221112112212112212122 DIRECTION IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIOOOOOOOIOOIOOIOOIOOOOIOOIIIIOOO changed: step 36 100000000000010010000000000000000000110111011011011010100110110111 fail ^ step 37 100000000000010010000000000000000000110111111011011010100110110111 step 38 100000000000010010000000000000000000110111011011011010100110110111 step 39 100000000000010010000000000000000000110111011011011010100110110111 SLOT BAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBAABBAAAAAAAAAAAAAABBBBBABBBB LETTER ALPSLFMDEEMCBFRSPKLEMFHRSCJLJKUHPNMBBNNVVRKRHUTDJUKANJHBTPDFSVEVDU SIDE 121212122121212121111111112212122222112222111221112112212112212122 DIRECTION IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIOOOOOOOIOOIOOIOOIOOOOIOOIIIIOOO changed: 0 1 0 step 40 100000000000000010000000000000000001110110011011011010100110110111 fail ^ ^ SLOT BAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBAABBAAAAAAAAAAAAAABBBBBABBBB LETTER ALPSLFMDEEMCBFRSPKLEMFHRSCJLJKUHPNMBBNNVVRKRHUTDJUKANJHBTPDFSVEVDU SIDE 121212122121212121111111112212122222112222111221112112212112212122 DIRECTION IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIOOOOOOOIOOIOOIOOIOOOOIOOIIIIOOO changed: 1 0 step 41 100000000000000010000000000000000001110110110011011010100110110111 fail ^ ^ SLOT BAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBAABBAAAAAAAAAAAAAABBBBBABBBB LETTER ALPSLFMDEEMCBFRSPKLEMFHRSCJLJKUHPNMBBNNVVRKRHUTDJUKANJHBTPDFSVEVDU SIDE 121212122121212121111111112212122222112222111221112112212112212122 DIRECTION IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIOOOOOOOIOOIOOIOOIOOOOIOOIIIIOOO changed: 0 step 42 100000000000000010000000000000000001110110010011011010100110110111 fail ^ ^ step 43 100000000000010010000000000000000000110111010011011010100110110111 step 44 100000000000010010000000000000000000110111111011011010100110110111 step 45 100000000000010010000000000000000000110111011011011010100110110111 step 46 100000000000010010000000000000000000110111011011011010100110110111 step 47 100000000000010010000000000000000000110111011011011010100110110111 SLOT BAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBAABBAAAAAAAAAAAAAABBBBBABBBB LETTER ALPSLFMDEEMCBFRSPKLEMFHRSCJLJKUHPNMBBNNVVRKRHUTDJUKANJHBTPDFSVEVDU SIDE 121212122121212121111111112212122222112222111221112112212112212122 DIRECTION IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIOOOOOOOIOOIOOIOOIOOOOIOOIIIIOOO changed: 1 step 48 100000000000010010000000000000000000110111011111011010100110110111 fail ^ SLOT BAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBAABBAAAAAAAAAAAAAABBBBBABBBB LETTER ALPSLFMDEEMCBFRSPKLEMFHRSCJLJKUHPNMBBNNVVRKRHUTDJUKANJHBTPDFSVEVDU SIDE 121212122121212121111111112212122222112222111221112112212112212122 DIRECTION IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIOOOOOOOIOOIOOIOOIOOOOIOOIIIIOOO changed: 0 step 49 100000000000010010000000000000000000110111011011011010100110110111 fail ^ SLOT BAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBAABBAAAAAAAAAAAAAABBBBBABBBB LETTER ALPSLFMDEEMCBFRSPKLEMFHRSCJLJKUHPNMBBNNVVRKRHUTDJUKANJHBTPDFSVEVDU SIDE 121212122121212121111111112212122222112222111221112112212112212122 DIRECTION IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIOOOOOOOIOOIOOIOOIOOOOIOOIIIIOOO changed: step 50 100000000000010010000000000000000000110111011011011010100110110111 fail ^ step 51 100000000000010010000000000000000000110111011111011010100110110111 step 52 100000000000010010000000000000000000110111011011011010100110110111 step 53 100000000000010010000000000000000000110111011011011010100110110111 SLOT BAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBAABBAAAAAAAAAAAAAABBBBBABBBB LETTER ALPSLFMDEEMCBFRSPKLEMFHRSCJLJKUHPNMBBNNVVRKRHUTDJUKANJHBTPDFSVEVDU SIDE 121212122121212121111111112212122222112222111221112112212112212122 DIRECTION IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIOOOOOOOIOOIOOIOOIOOOOIOOIIIIOOO changed: 0 1 0 step 54 100000000000000010000000000000000001110110011011011010100110110111 fail ^ ^ SLOT BAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBAABBAAAAAAAAAAAAAABBBBBABBBB LETTER ALPSLFMDEEMCBFRSPKLEMFHRSCJLJKUHPNMBBNNVVRKRHUTDJUKANJHBTPDFSVEVDU SIDE 121212122121212121111111112212122222112222111221112112212112212122 DIRECTION IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIOOOOOOOIOOIOOIOOIOOOOIOOIIIIOOO changed: 1 0 step 55 100000000000000010000000000000000001110110011110011010100110110111 fail ^ ^ SLOT BAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBAABBAAAAAAAAAAAAAABBBBBABBBB LETTER ALPSLFMDEEMCBFRSPKLEMFHRSCJLJKUHPNMBBNNVVRKRHUTDJUKANJHBTPDFSVEVDU SIDE 121212122121212121111111112212122222112222111221112112212112212122 DIRECTION IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIOOOOOOOIOOIOOIOOIOOOOIOOIIIIOOO changed: 0 step 56 100000000000000010000000000000000001110110011010011010100110110111 fail ^ ^ step 57 100000000000010010000000000000000000110111011010011010100110110111 step 58 100000000000010010000000000000000000110111011111011010100110110111 step 59 100000000000010010000000000000000000110111011011011010100110110111 SLOT BAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBAABBAAAAAAAAAAAAAABBBBBABBBB LETTER ALPSLFMDEEMCBFRSPKLEMFHRSCJLJKUHPNMBBNNVVRKRHUTDJUKANJHBTPDFSVEVDU SIDE 121212122121212121111111112212122222112222111221112112212112212122 DIRECTION IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIOOOOOOOIOOIOOIOOIOOOOIOOIIIIOOO changed: 1 step 60 100000000000010010000000000000000000110111011011111010100110110111 fail ^^ SLOT BAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBAABBAAAAAAAAAAAAAABBBBBABBBB LETTER ALPSLFMDEEMCBFRSPKLEMFHRSCJLJKUHPNMBBNNVVRKRHUTDJUKANJHBTPDFSVEVDU SIDE 121212122121212121111111112212122222112222111221112112212112212122 DIRECTION IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIOOOOOOOIOOIOOIOOIOOOOIOOIIIIOOO changed: 0 step 61 100000000000010010000000000000000000110111011011011010100110110111 fail ^^ SLOT BAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBAABBAAAAAAAAAAAAAABBBBBABBBB LETTER ALPSLFMDEEMCBFRSPKLEMFHRSCJLJKUHPNMBBNNVVRKRHUTDJUKANJHBTPDFSVEVDU SIDE 121212122121212121111111112212122222112222111221112112212112212122 DIRECTION IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIOOOOOOOIOOIOOIOOIOOOOIOOIIIIOOO changed: 1 step 62 100000000000010010000000000000000000110111011011011110100110110111 fail ^^ ^^^^ SLOT BAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBAABBAAAAAAAAAAAAAABBBBBABBBB LETTER ALPSLFMDEEMCBFRSPKLEMFHRSCJLJKUHPNMBBNNVVRKRHUTDJUKANJHBTPDFSVEVDU SIDE 121212122121212121111111112212122222112222111221112112212112212122 DIRECTION IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIOOOOOOOIOOIOOIOOIOOOOIOOIIIIOOO changed: 0 step 63 100000000000010010000000000000000000110111011011011010100110110111 fail ^^ ^^^^ SLOT BAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBAABBAAAAAAAAAAAAAABBBBBABBBB LETTER ALPSLFMDEEMCBFRSPKLEMFHRSCJLJKUHPNMBBNNVVRKRHUTDJUKANJHBTPDFSVEVDU SIDE 121212122121212121111111112212122222112222111221112112212112212122 DIRECTION IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIOOOOOOOIOOIOOIOOIOOOOIOOIIIIOOO changed: 1 step 64 100000000000010010000000000000000000110111011011011010101110110111 fail ^^ ^^^^ ^^ SLOT BAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBAABBAAAAAAAAAAAAAABBBBBABBBB LETTER ALPSLFMDEEMCBFRSPKLEMFHRSCJLJKUHPNMBBNNVVRKRHUTDJUKANJHBTPDFSVEVDU SIDE 121212122121212121111111112212122222112222111221112112212112212122 DIRECTION IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIOOOOOOOIOOIOOIOOIOOOOIOOIIIIOOO changed: 0 step 65 100000000000010010000000000000000000110111011011011010100110110111 fail ^^ ^^^^ ^^ SLOT BAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBAABBAAAAAAAAAAAAAABBBBBABBBB LETTER ALPSLFMDEEMCBFRSPKLEMFHRSCJLJKUHPNMBBNNVVRKRHUTDJUKANJHBTPDFSVEVDU SIDE 121212122121212121111111112212122222112222111221112112212112212122 DIRECTION IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIOOOOOOOIOOIOOIOOIOOOOIOOIIIIOOO changed: 1 step 66 100000000000010010000000000000000000110111011011011010100111110111 fail ^^ ^^^^ ^^ ^^ SLOT BAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBAABBAAAAAAAAAAAAAABBBBBABBBB LETTER ALPSLFMDEEMCBFRSPKLEMFHRSCJLJKUHPNMBBNNVVRKRHUTDJUKANJHBTPDFSVEVDU SIDE 121212122121212121111111112212122222112222111221112112212112212122 DIRECTION IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIOOOOOOOIOOIOOIOOIOOOOIOOIIIIOOO changed: 0 step 67 100000000000010010000000000000000000110111011011011010100110110111 fail ^^ ^^^^ ^^ ^^ SLOT BAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBAABBAAAAAAAAAAAAAABBBBBABBBB LETTER ALPSLFMDEEMCBFRSPKLEMFHRSCJLJKUHPNMBBNNVVRKRHUTDJUKANJHBTPDFSVEVDU SIDE 121212122121212121111111112212122222112222111221112112212112212122 DIRECTION IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIOOOOOOOIOOIOOIOOIOOOOIOOIIIIOOO changed: 1 step 68 100001000000010010000000000000000000110111011011011010100110110111 fail ^^ ^^^^ ^^ ^^ SLOT BAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBAABBAAAAAAAAAAAAAABBBBBABBBB LETTER ALPSLFMDEEMCBFRSPKLEMFHRSCJLJKUHPNMBBNNVVRKRHUTDJUKANJHBTPDFSVEVDU SIDE 121212122121212121111111112212122222112222111221112112212112212122 DIRECTION IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIOOOOOOOIOOIOOIOOIOOOOIOOIIIIOOO changed: 1 step 69 100001100000010010000000000000000000110111011011011010100110110111 fail ^^ ^^^^ ^^ ^^ SLOT BAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBAABBAAAAAAAAAAAAAABBBBBABBBB LETTER ALPSLFMDEEMCBFRSPKLEMFHRSCJLJKUHPNMBBNNVVRKRHUTDJUKANJHBTPDFSVEVDU SIDE 121212122121212121111111112212122222112222111221112112212112212122 DIRECTION IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIOOOOOOOIOOIOOIOOIOOOOIOOIIIIOOO changed: 1 step 70 100001100100010010000000000000000000110111011011011010100110110111 fail ^^ ^^^^ ^^ ^^ SLOT BAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBAABBAAAAAAAAAAAAAABBBBBABBBB LETTER ALPSLFMDEEMCBFRSPKLEMFHRSCJLJKUHPNMBBNNVVRKRHUTDJUKANJHBTPDFSVEVDU SIDE 121212122121212121111111112212122222112222111221112112212112212122 DIRECTION IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIOOOOOOOIOOIOOIOOIOOOOIOOIIIIOOO changed: 1 step 71 100001100110010010000000000000000000110111011011011010100110110111 fail ^^ ^^^^ ^^ ^^ SLOT BAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBAABBAAAAAAAAAAAAAABBBBBABBBB LETTER ALPSLFMDEEMCBFRSPKLEMFHRSCJLJKUHPNMBBNNVVRKRHUTDJUKANJHBTPDFSVEVDU SIDE 121212122121212121111111112212122222112222111221112112212112212122 DIRECTION IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIOOOOOOOIOOIOOIOOIOOOOIOOIIIIOOO changed: 1 step 72 100001100110110010000000000000000000110111011011011010100110110111 fail ^^ ^^^^ ^^ ^^ SLOT BAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBAABBAAAAAAAAAAAAAABBBBBABBBB LETTER ALPSLFMDEEMCBFRSPKLEMFHRSCJLJKUHPNMBBNNVVRKRHUTDJUKANJHBTPDFSVEVDU SIDE 121212122121212121111111112212122222112222111221112112212112212122 DIRECTION IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIOOOOOOOIOOIOOIOOIOOOOIOOIIIIOOO changed: 1 step 73 100001100110110110000000000000000000110111011011011010100110110111 fail ^^ ^^^^ ^^ ^^ SLOT BAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBAABBAAAAAAAAAAAAAABBBBBABBBB LETTER ALPSLFMDEEMCBFRSPKLEMFHRSCJLJKUHPNMBBNNVVRKRHUTDJUKANJHBTPDFSVEVDU SIDE 121212122121212121111111112212122222112222111221112112212112212122 DIRECTION IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIOOOOOOOIOOIOOIOOIOOOOIOOIIIIOOO changed: 1 step 74 100001100110110110010000000000000000110111011011011010100110110111 fail ^^ ^^^^ ^^ ^^ SLOT BAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBAABBAAAAAAAAAAAAAABBBBBABBBB LETTER ALPSLFMDEEMCBFRSPKLEMFHRSCJLJKUHPNMBBNNVVRKRHUTDJUKANJHBTPDFSVEVDU SIDE 121212122121212121111111112212122222112222111221112112212112212122 DIRECTION IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIOOOOOOOIOOIOOIOOIOOOOIOOIIIIOOO changed: 1 step 75 100001100110110110011000000000000000110111011011011010100110110111 fail ^^ ^^^^ ^^ ^^ SLOT BAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBAABBAAAAAAAAAAAAAABBBBBABBBB LETTER ALPSLFMDEEMCBFRSPKLEMFHRSCJLJKUHPNMBBNNVVRKRHUTDJUKANJHBTPDFSVEVDU SIDE 121212122121212121111111112212122222112222111221112112212112212122 DIRECTION IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIOOOOOOOIOOIOOIOOIOOOOIOOIIIIOOO changed: 1 step 76 100001100110110110011010000000000000110111011011011010100110110111 fail ^^ ^^^^ ^^ ^^ SLOT BAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBAABBAAAAAAAAAAAAAABBBBBABBBB LETTER ALPSLFMDEEMCBFRSPKLEMFHRSCJLJKUHPNMBBNNVVRKRHUTDJUKANJHBTPDFSVEVDU SIDE 121212122121212121111111112212122222112222111221112112212112212122 DIRECTION IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIOOOOOOOIOOIOOIOOIOOOOIOOIIIIOOO changed: 1 step 77 100001100110110110011011000000000000110111011011011010100110110111 fail ^^ ^^^^ ^^ ^^ SLOT BAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBAABBAAAAAAAAAAAAAABBBBBABBBB LETTER ALPSLFMDEEMCBFRSPKLEMFHRSCJLJKUHPNMBBNNVVRKRHUTDJUKANJHBTPDFSVEVDU SIDE 121212122121212121111111112212122222112222111221112112212112212122 DIRECTION IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIOOOOOOOIOOIOOIOOIOOOOIOOIIIIOOO changed: 1 step 78 100001100110110110011011010000000000110111011011011010100110110111 fail ^^ ^^^^ ^^ ^^ SLOT BAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBAABBAAAAAAAAAAAAAABBBBBABBBB LETTER ALPSLFMDEEMCBFRSPKLEMFHRSCJLJKUHPNMBBNNVVRKRHUTDJUKANJHBTPDFSVEVDU SIDE 121212122121212121111111112212122222112222111221112112212112212122 DIRECTION IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIOOOOOOOIOOIOOIOOIOOOOIOOIIIIOOO changed: 1 step 79 100001100110110110011011011000000000110111011011011010100110110111 fail ^^ ^^^^ ^^ ^^ SLOT BAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBAABBAAAAAAAAAAAAAABBBBBABBBB LETTER ALPSLFMDEEMCBFRSPKLEMFHRSCJLJKUHPNMBBNNVVRKRHUTDJUKANJHBTPDFSVEVDU SIDE 121212122121212121111111112212122222112222111221112112212112212122 DIRECTION IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIOOOOOOOIOOIOOIOOIOOOOIOOIIIIOOO changed: 1 step 80 100001100110110110011011011010000000110111011011011010100110110111 fail ^^ ^^^^ ^^ ^^ SLOT BAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBAABBAAAAAAAAAAAAAABBBBBABBBB LETTER ALPSLFMDEEMCBFRSPKLEMFHRSCJLJKUHPNMBBNNVVRKRHUTDJUKANJHBTPDFSVEVDU SIDE 121212122121212121111111112212122222112222111221112112212112212122 DIRECTION IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIOOOOOOOIOOIOOIOOIOOOOIOOIIIIOOO changed: 1 step 81 100001100110110110011011011011000000110111011011011010100110110111 fail ^^ ^^^^ ^^ ^^ SLOT BAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBAABBAAAAAAAAAAAAAABBBBBABBBB LETTER ALPSLFMDEEMCBFRSPKLEMFHRSCJLJKUHPNMBBNNVVRKRHUTDJUKANJHBTPDFSVEVDU SIDE 121212122121212121111111112212122222112222111221112112212112212122 DIRECTION IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIOOOOOOOIOOIOOIOOIOOOOIOOIIIIOOO changed: 1 step 82 100001100110110110011011011011010000110111011011011010100110110111 fail ^^ ^^^^ ^^ ^^ SLOT BAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBAABBAAAAAAAAAAAAAABBBBBABBBB LETTER ALPSLFMDEEMCBFRSPKLEMFHRSCJLJKUHPNMBBNNVVRKRHUTDJUKANJHBTPDFSVEVDU SIDE 121212122121212121111111112212122222112222111221112112212112212122 DIRECTION IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIOOOOOOOIOOIOOIOOIOOOOIOOIIIIOOO changed: 1 step 83 100001100110110110011011011011011000110111011011011010100110110111 fail ^^ ^^^^ ^^ ^^ SLOT BAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBAABBAAAAAAAAAAAAAABBBBBABBBB LETTER ALPSLFMDEEMCBFRSPKLEMFHRSCJLJKUHPNMBBNNVVRKRHUTDJUKANJHBTPDFSVEVDU SIDE 121212122121212121111111112212122222112222111221112112212112212122 DIRECTION IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIOOOOOOOIOOIOOIOOIOOOOIOOIIIIOOO changed: 1 step 84 100001100110110110011011011011011100110111011011011010100110110111 fail ^^ ^^^^ ^^ ^^ SLOT BAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBAABBAAAAAAAAAAAAAABBBBBABBBB LETTER ALPSLFMDEEMCBFRSPKLEMFHRSCJLJKUHPNMBBNNVVRKRHUTDJUKANJHBTPDFSVEVDU SIDE 121212122121212121111111112212122222112222111221112112212112212122 DIRECTION IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIOOOOOOOIOOIOOIOOIOOOOIOOIIIIOOO changed: 1 step 85 110001100110110110011011011011011100110111011011011010100110110111 fail ^^ ^^^^ ^^ ^^ SLOT BAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBAABBAAAAAAAAAAAAAABBBBBABBBB LETTER ALPSLFMDEEMCBFRSPKLEMFHRSCJLJKUHPNMBBNNVVRKRHUTDJUKANJHBTPDFSVEVDU SIDE 121212122121212121111111112212122222112222111221112112212112212122 DIRECTION IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIOOOOOOOIOOIOOIOOIOOOOIOOIIIIOOO changed: 0 step 86 100001100110110110011011011011011100110111011011011010100110110111 fail ^ ^ ^^ ^^ ^^^^ ^^ ^^ SLOT BAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBAABBAAAAAAAAAAAAAABBBBBABBBB LETTER ALPSLFMDEEMCBFRSPKLEMFHRSCJLJKUHPNMBBNNVVRKRHUTDJUKANJHBTPDFSVEVDU SIDE 121212122121212121111111112212122222112222111221112112212112212122 DIRECTION IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIOOOOOOOIOOIOOIOOIOOOOIOOIIIIOOO changed: 1 step 87 101001100110110110011011011011011100110111011011011010100110110111 fail ^^ ^^^^ ^^ ^^ SLOT BAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBAABBAAAAAAAAAAAAAABBBBBABBBB LETTER ALPSLFMDEEMCBFRSPKLEMFHRSCJLJKUHPNMBBNNVVRKRHUTDJUKANJHBTPDFSVEVDU SIDE 121212122121212121111111112212122222112222111221112112212112212122 DIRECTION IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIOOOOOOOIOOIOOIOOIOOOOIOOIIIIOOO changed: 0 step 88 100001100110110110011011011011011100110111011011011010100110110111 fail ^ ^ ^^ ^^ ^^^^ ^^ ^^ SLOT BAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBAABBAAAAAAAAAAAAAABBBBBABBBB LETTER ALPSLFMDEEMCBFRSPKLEMFHRSCJLJKUHPNMBBNNVVRKRHUTDJUKANJHBTPDFSVEVDU SIDE 121212122121212121111111112212122222112222111221112112212112212122 DIRECTION IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIOOOOOOOIOOIOOIOOIOOOOIOOIIIIOOO changed: 1 step 89 100101100110110110011011011011011100110111011011011010100110110111 fail ^^ ^^^^ ^^ ^^ SLOT BAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBAABBAAAAAAAAAAAAAABBBBBABBBB LETTER ALPSLFMDEEMCBFRSPKLEMFHRSCJLJKUHPNMBBNNVVRKRHUTDJUKANJHBTPDFSVEVDU SIDE 121212122121212121111111112212122222112222111221112112212112212122 DIRECTION IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIOOOOOOOIOOIOOIOOIOOOOIOOIIIIOOO changed: 0 step 90 100001100110110110011011011011011100110111011011011010100110110111 fail ^ ^ ^^ ^^ ^^^^ ^^ ^^ SLOT BAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBAABBAAAAAAAAAAAAAABBBBBABBBB LETTER ALPSLFMDEEMCBFRSPKLEMFHRSCJLJKUHPNMBBNNVVRKRHUTDJUKANJHBTPDFSVEVDU SIDE 121212122121212121111111112212122222112222111221112112212112212122 DIRECTION IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIOOOOOOOIOOIOOIOOIOOOOIOOIIIIOOO changed: 1 step 91 100011100110110110011011011011011100110111011011011010100110110111 fail ^^ ^^^^ ^^ ^^ SLOT BAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBAABBAAAAAAAAAAAAAABBBBBABBBB LETTER ALPSLFMDEEMCBFRSPKLEMFHRSCJLJKUHPNMBBNNVVRKRHUTDJUKANJHBTPDFSVEVDU SIDE 121212122121212121111111112212122222112222111221112112212112212122 DIRECTION IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIOOOOOOOIOOIOOIOOIOOOOIOOIIIIOOO changed: 0 step 92 100001100110110110011011011011011100110111011011011010100110110111 fail ^ ^ ^^ ^^ ^^^^ ^^ ^^ SLOT BAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBAABBAAAAAAAAAAAAAABBBBBABBBB LETTER ALPSLFMDEEMCBFRSPKLEMFHRSCJLJKUHPNMBBNNVVRKRHUTDJUKANJHBTPDFSVEVDU SIDE 121212122121212121111111112212122222112222111221112112212112212122 DIRECTION IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIOOOOOOOIOOIOOIOOIOOOOIOOIIIIOOO changed: 1 step 93 100001110110110110011011011011011100110111011011011010100110110111 fail ^^ ^^^^ ^^ ^^ SLOT BAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBAABBAAAAAAAAAAAAAABBBBBABBBB LETTER ALPSLFMDEEMCBFRSPKLEMFHRSCJLJKUHPNMBBNNVVRKRHUTDJUKANJHBTPDFSVEVDU SIDE 121212122121212121111111112212122222112222111221112112212112212122 DIRECTION IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIOOOOOOOIOOIOOIOOIOOOOIOOIIIIOOO changed: 0 step 94 100001100110110110011011011011011100110111011011011010100110110111 fail ^ ^ ^^ ^^ ^^^^ ^^ ^^ SLOT BAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBAABBAAAAAAAAAAAAAABBBBBABBBB LETTER ALPSLFMDEEMCBFRSPKLEMFHRSCJLJKUHPNMBBNNVVRKRHUTDJUKANJHBTPDFSVEVDU SIDE 121212122121212121111111112212122222112222111221112112212112212122 DIRECTION IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIOOOOOOOIOOIOOIOOIOOOOIOOIIIIOOO changed: 1 step 95 100001101110110110011011011011011100110111011011011010100110110111 fail ^^ ^^^^ ^^ ^^ SLOT BAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBAABBAAAAAAAAAAAAAABBBBBABBBB LETTER ALPSLFMDEEMCBFRSPKLEMFHRSCJLJKUHPNMBBNNVVRKRHUTDJUKANJHBTPDFSVEVDU SIDE 121212122121212121111111112212122222112222111221112112212112212122 DIRECTION IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIOOOOOOOIOOIOOIOOIOOOOIOOIIIIOOO changed: 0 step 96 100001100110110110011011011011011100110111011011011010100110110111 fail ^ ^ ^^ ^^ ^^^^ ^^ ^^ SLOT BAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBAABBAAAAAAAAAAAAAABBBBBABBBB LETTER ALPSLFMDEEMCBFRSPKLEMFHRSCJLJKUHPNMBBNNVVRKRHUTDJUKANJHBTPDFSVEVDU SIDE 121212122121212121111111112212122222112222111221112112212112212122 DIRECTION IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIOOOOOOOIOOIOOIOOIOOOOIOOIIIIOOO changed: 1 step 97 100001100111110110011011011011011100110111011011011010100110110111 fail ^ ^ ^^ ^^^^ ^^ ^^ SLOT BAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBAABBAAAAAAAAAAAAAABBBBBABBBB LETTER ALPSLFMDEEMCBFRSPKLEMFHRSCJLJKUHPNMBBNNVVRKRHUTDJUKANJHBTPDFSVEVDU SIDE 121212122121212121111111112212122222112222111221112112212112212122 DIRECTION IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIOOOOOOOIOOIOOIOOIOOOOIOOIIIIOOO changed: 0 step 98 100001100110110110011011011011011100110111011011011010100110110111 fail ^ ^ ^^ ^^ ^^^^ ^^ ^^ SLOT BAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBAABBAAAAAAAAAAAAAABBBBBABBBB LETTER ALPSLFMDEEMCBFRSPKLEMFHRSCJLJKUHPNMBBNNVVRKRHUTDJUKANJHBTPDFSVEVDU SIDE 121212122121212121111111112212122222112222111221112112212112212122 DIRECTION IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIOOOOOOOIOOIOOIOOIOOOOIOOIIIIOOO changed: step 99 100001100110110110011011011011011100110111011011011010100110110111 fail ^ ^ ^^ ^^^^ ^^ ^^ SLOT BAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBAABBAAAAAAAAAAAAAABBBBBABBBB LETTER ALPSLFMDEEMCBFRSPKLEMFHRSCJLJKUHPNMBBNNVVRKRHUTDJUKANJHBTPDFSVEVDU SIDE 121212122121212121111111112212122222112222111221112112212112212122 DIRECTION IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIOOOOOOOIOOIOOIOOIOOOOIOOIIIIOOO changed: 0 1 0 step 100 100001100110100110011011011011011101110110011011011010100110110111 fail ^ ^ ^^ ^^^^ ^^ ^^ SLOT BAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBAABBAAAAAAAAAAAAAABBBBBABBBB LETTER ALPSLFMDEEMCBFRSPKLEMFHRSCJLJKUHPNMBBNNVVRKRHUTDJUKANJHBTPDFSVEVDU SIDE 121212122121212121111111112212122222112222111221112112212112212122 DIRECTION IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIOOOOOOOIOOIOOIOOIOOOOIOOIIIIOOO changed: 1 step 101 100001100110101110011011011011011101110110011011011010100110110111 fail ^^ ^^^^ ^^ ^^ SLOT BAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBAABBAAAAAAAAAAAAAABBBBBABBBB LETTER ALPSLFMDEEMCBFRSPKLEMFHRSCJLJKUHPNMBBNNVVRKRHUTDJUKANJHBTPDFSVEVDU SIDE 121212122121212121111111112212122222112222111221112112212112212122 DIRECTION IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIOOOOOOOIOOIOOIOOIOOOOIOOIIIIOOO changed: 0 step 102 100001100110100110011011011011011101110110011011011010100110110111 fail ^ ^ ^^ ^^^^ ^^ ^^ SLOT BAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBAABBAAAAAAAAAAAAAABBBBBABBBB LETTER ALPSLFMDEEMCBFRSPKLEMFHRSCJLJKUHPNMBBNNVVRKRHUTDJUKANJHBTPDFSVEVDU SIDE 121212122121212121111111112212122222112222111221112112212112212122 DIRECTION IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIOOOOOOOIOOIOOIOOIOOOOIOOIIIIOOO changed: step 103 100001100110100110011011011011011101110110011011011010100110110111 fail ^^ ^^^^ ^^ ^^ SLOT BAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBAABBAAAAAAAAAAAAAABBBBBABBBB LETTER ALPSLFMDEEMCBFRSPKLEMFHRSCJLJKUHPNMBBNNVVRKRHUTDJUKANJHBTPDFSVEVDU SIDE 121212122121212121111111112212122222112222111221112112212112212122 DIRECTION IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIOOOOOOOIOOIOOIOOIOOOOIOOIIIIOOO changed: 0 1 0 step 104 100001100110100100011011011011011101111100011011011010100110110111 fail ^^ ^^^^ ^^ ^^ SLOT BAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBAABBAAAAAAAAAAAAAABBBBBABBBB LETTER ALPSLFMDEEMCBFRSPKLEMFHRSCJLJKUHPNMBBNNVVRKRHUTDJUKANJHBTPDFSVEVDU SIDE 121212122121212121111111112212122222112222111221112112212112212122 DIRECTION IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIOOOOOOOIOOIOOIOOIOOOOIOOIIIIOOO changed: 1 00 11 step 105 100001100110100101011011011011011101001111011011011010100110110111 fail ^^ ^^^^ ^^ ^^ SLOT BAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBAABBAAAAAAAAAAAAAABBBBBABBBB LETTER ALPSLFMDEEMCBFRSPKLEMFHRSCJLJKUHPNMBBNNVVRKRHUTDJUKANJHBTPDFSVEVDU SIDE 121212122121212121111111112212122222112222111221112112212112212122 DIRECTION IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIOOOOOOOIOOIOOIOOIOOOOIOOIIIIOOO changed: 0 11 00 step 106 100001100110100100011011011011011101111100011011011010100110110111 fail ^^ ^^^^ ^^ ^^ SLOT BAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBAABBAAAAAAAAAAAAAABBBBBABBBB LETTER ALPSLFMDEEMCBFRSPKLEMFHRSCJLJKUHPNMBBNNVVRKRHUTDJUKANJHBTPDFSVEVDU SIDE 121212122121212121111111112212122222112222111221112112212112212122 DIRECTION IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIOOOOOOOIOOIOOIOOIOOOOIOOIIIIOOO changed: 1 00 11 step 107 100001100110100100111011011011011101001111011011011010100110110111 fail ^^ ^^^^ ^^ ^^ SLOT BAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBAABBAAAAAAAAAAAAAABBBBBABBBB LETTER ALPSLFMDEEMCBFRSPKLEMFHRSCJLJKUHPNMBBNNVVRKRHUTDJUKANJHBTPDFSVEVDU SIDE 121212122121212121111111112212122222112222111221112112212112212122 DIRECTION IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIOOOOOOOIOOIOOIOOIOOOOIOOIIIIOOO changed: 0 11 00 step 108 100001100110100100011011011011011101111100011011011010100110110111 fail ^^ ^^^^ ^^ ^^ SLOT BAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBAABBAAAAAAAAAAAAAABBBBBABBBB LETTER ALPSLFMDEEMCBFRSPKLEMFHRSCJLJKUHPNMBBNNVVRKRHUTDJUKANJHBTPDFSVEVDU SIDE 121212122121212121111111112212122222112222111221112112212112212122 DIRECTION IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIOOOOOOOIOOIOOIOOIOOOOIOOIIIIOOO changed: 1 00 11 step 109 100001100110100100011111011011011101001111011011011010100110110111 fail ^^ ^^^^ ^^ ^^ SLOT BAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBAABBAAAAAAAAAAAAAABBBBBABBBB LETTER ALPSLFMDEEMCBFRSPKLEMFHRSCJLJKUHPNMBBNNVVRKRHUTDJUKANJHBTPDFSVEVDU SIDE 121212122121212121111111112212122222112222111221112112212112212122 DIRECTION IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIOOOOOOOIOOIOOIOOIOOOOIOOIIIIOOO changed: 0 11 00 step 110 100001100110100100011011011011011101111100011011011010100110110111 fail ^^ ^^^^ ^^ ^^ SLOT BAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBAABBAAAAAAAAAAAAAABBBBBABBBB LETTER ALPSLFMDEEMCBFRSPKLEMFHRSCJLJKUHPNMBBNNVVRKRHUTDJUKANJHBTPDFSVEVDU SIDE 121212122121212121111111112212122222112222111221112112212112212122 DIRECTION IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIOOOOOOOIOOIOOIOOIOOOOIOOIIIIOOO changed: 1 00 11 step 111 100001100110100100011011111011011101001111011011011010100110110111 fail ^^ ^^^^ ^^ ^^ SLOT BAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBAABBAAAAAAAAAAAAAABBBBBABBBB LETTER ALPSLFMDEEMCBFRSPKLEMFHRSCJLJKUHPNMBBNNVVRKRHUTDJUKANJHBTPDFSVEVDU SIDE 121212122121212121111111112212122222112222111221112112212112212122 DIRECTION IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIOOOOOOOIOOIOOIOOIOOOOIOOIIIIOOO changed: 0 11 00 step 112 100001100110100100011011011011011101111100011011011010100110110111 fail ^^ ^^^^ ^^ ^^ SLOT BAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBAABBAAAAAAAAAAAAAABBBBBABBBB LETTER ALPSLFMDEEMCBFRSPKLEMFHRSCJLJKUHPNMBBNNVVRKRHUTDJUKANJHBTPDFSVEVDU SIDE 121212122121212121111111112212122222112222111221112112212112212122 DIRECTION IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIOOOOOOOIOOIOOIOOIOOOOIOOIIIIOOO changed: 1 00 11 step 113 100001100110100100011011011111011101001111011011011010100110110111 fail ^^ ^^^^ ^^ ^^ SLOT BAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBAABBAAAAAAAAAAAAAABBBBBABBBB LETTER ALPSLFMDEEMCBFRSPKLEMFHRSCJLJKUHPNMBBNNVVRKRHUTDJUKANJHBTPDFSVEVDU SIDE 121212122121212121111111112212122222112222111221112112212112212122 DIRECTION IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIOOOOOOOIOOIOOIOOIOOOOIOOIIIIOOO changed: 0 11 00 step 114 100001100110100100011011011011011101111100011011011010100110110111 fail ^^ ^^^^ ^^ ^^ SLOT BAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBAABBAAAAAAAAAAAAAABBBBBABBBB LETTER ALPSLFMDEEMCBFRSPKLEMFHRSCJLJKUHPNMBBNNVVRKRHUTDJUKANJHBTPDFSVEVDU SIDE 121212122121212121111111112212122222112222111221112112212112212122 DIRECTION IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIOOOOOOOIOOIOOIOOIOOOOIOOIIIIOOO changed: 1 00 11 step 115 100001100110100100011011011011111101001111011011011010100110110111 fail ^^ ^^^^ ^^ ^^ SLOT BAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBAABBAAAAAAAAAAAAAABBBBBABBBB LETTER ALPSLFMDEEMCBFRSPKLEMFHRSCJLJKUHPNMBBNNVVRKRHUTDJUKANJHBTPDFSVEVDU SIDE 121212122121212121111111112212122222112222111221112112212112212122 DIRECTION IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIOOOOOOOIOOIOOIOOIOOOOIOOIIIIOOO changed: 0 11 00 step 116 100001100110100100011011011011011101111100011011011010100110110111 fail ^^ ^^^^ ^^ ^^ SLOT BAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBAABBAAAAAAAAAAAAAABBBBBABBBB LETTER ALPSLFMDEEMCBFRSPKLEMFHRSCJLJKUHPNMBBNNVVRKRHUTDJUKANJHBTPDFSVEVDU SIDE 121212122121212121111111112212122222112222111221112112212112212122 DIRECTION IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIOOOOOOOIOOIOOIOOIOOOOIOOIIIIOOO changed: 1 0 1 step 117 100001100110100100011011011011011111101110011011011010100110110111 fail ^^ ^^^^ ^^ ^^ SLOT BAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBAABBAAAAAAAAAAAAAABBBBBABBBB LETTER ALPSLFMDEEMCBFRSPKLEMFHRSCJLJKUHPNMBBNNVVRKRHUTDJUKANJHBTPDFSVEVDU SIDE 121212122121212121111111112212122222112222111221112112212112212122 DIRECTION IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIOOOOOOOIOOIOOIOOIOOOOIOOIIIIOOO changed: 0 1 0 step 118 100001100110100100011011011011011101111100011011011010100110110111 fail ^^ ^^^^ ^^ ^^ step 119 100000000000000000000000000000000001111100011011011010100110110111 step 120 100000000000000000000000000000000001111100011011011010100110100111 step 121 100000000000000000000000000000000001111100011011011010100110101101 step 122 100000000000000000000000000000000001111100011011011010100110100101 step 123 100000000000000000000000000000000001111100011011011010100110000001 step 124 100000000000000000000000000000000001111100011011011010100110100101 step 125 100000000000000000000000000000000001111100011011011010100110100101 step 126 100000000000000000000000000000000001111100011011011010100110101001 step 127 100000000000000000000000000000000001111100011011011010100110100001 step 128 100000000000000000000000000000000001111100011011011010100110000101 step 129 100000000000000000000000000000000001111100011011011010100110100001 step 130 100000000000000000000000000000000001111100011011011010100110100001 step 131 100000000000000000000000000000000001111100011011011010100110101001 step 132 100000000000000000000000000000000001111100011011011010100110100001 step 133 100000000000000000000000000000000001111100011011011010100110110001 step 134 100000000000000000000000000000000001111100011011011010100110111011 step 135 100000000000000000000000000000000001111100011011011010100110110011 step 136 100000000000000000000000000000000001111100011011011010100110110011 step 137 100000000000000000000000000000000001111100011011011010100110111111 step 138 100000000000000000000000000000000001111100011011011010100110110111 step 139 100000000000000000000000000000000001111100011011011010100110110111 step 140 100000000000000000000000000000000001111100011011011010100110111111 step 141 100000000000000000000000000000000001111100011011011010100110110111 step 142 100000000000000000000000000000000001111100011011011010100110100111 step 143 100000000000000000000000000000000001111100011011011010100110101101 step 144 100000000000000000000000000000000001111100011011011010100110100101 step 145 100000000000000000000000000000000001111100011011011010100110110101 step 146 100000000000000000000000000000000001111100011011011010100110111011 step 147 100000000000000000000000000000000001111100011011011010100110110011 step 148 100000000000000000000000000000000001111100011011011010100110100011 step 149 100000000000000000000000000000000001111100011011011010100110101101 step 150 100000000000000000000000000000000001111100011011011010100110100101 step 151 100000000000000000000000000000000001111100011011011010100110110101 step 152 100000000000000000000000000000000001111100011011011010100110111011 step 153 100000000000000000000000000000000001111100011011011010100110110011 step 154 100000000000000000000000000000000001111100011011011010100110110011 step 155 100000000000000000000000000000000001111100011011011010100110111111 step 156 100000000000000000000000000000000001111100011011011010100110110111 step 157 100000000000000000000000000000000001111100011011011010100110110111 test 1: *** FAIL *************************** 71 steps failed SLOT BAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBAABBAAAAAAAAAAAAAABBBBBABBBB LETTER ALPSLFMDEEMCBFRSPKLEMFHRSCJLJKUHPNMBBNNVVRKRHUTDJUKANJHBTPDFSVEVDU SIDE 121212122121212121111111112212122222112222111221112112212112212122 DIRECTION IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIOOOOOOOIOOIOOIOOIOOOOIOOIIIIOOO this fail O O OO O O OO OOOO OO OO all fails O O OO O O OO OOOO OO OO was hi 111111111111111111111111111111111111111111111111111111111111111111 rising ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ ^^^^^^^^^^^^^ ^ ^^^^^^^^^ falling vvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvv vvvvvvvvv v v vvvvvvvvvv was lo 00000000000000000000000000000000000000 0000000000000000000000000 total fails 1, total passes 0 space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C toggle comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit comment_flag is 1 space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C toggle comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit source: ; all registers are unknown source: ; turn on C0, PHASE source: ; with no ENABLES, BUS2,BUS3 is 11, C2 is 1 source: 1000000000000000000000000000000000011111000XX0XX0XX0XXXX0XX0110XX1 changed: step 1 100000000000000000000000000000000001111100011011011010100110110111 source: source: ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; source: ; source: ; set all registers LOW source: ; source: ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; source: source: ; load TMA SETUP from tape bus (00) source: 100 changed: 100 step 2 100000000000000000000000000000000001111100100011011010100110110111 source: 0 changed: 0 step 3 100000000000000000000000000000000001111100000011011010100110110111 source: ; load TMA from tape bus (00) source: 100 changed: 100 step 4 100000000000000000000000000000000001111100000100011010100110110111 source: 0 changed: 0 step 5 100000000000000000000000000000000001111100000000011010100110110111 source: ; load TBN from tape bus (00) source: 100 changed: 100 step 6 100000000000000000000000000000000001111100000000100010100110110111 source: 0 changed: 0 step 7 100000000000000000000000000000000001111100000000000010100110110111 source: ; load TAC from tape bus (00) source: 10101 changed: 10101 step 8 100000000000000000000000000000000001111100000000000101010110110111 source: 0 changed: 0 step 9 100000000000000000000000000000000001111100000000000001010110110111 source: ; load TB from tape bus (00) source: 100 changed: 100 step 10 100000000000000000000000000000000001111100000000000001011000110111 source: 0 changed: 0 step 11 100000000000000000000000000000000001111100000000000001010000110111 source: ; load RWB from TB (JAMS CLEAR AND PRESET) source: 1 00 changed: 1 00 step 12 100000000000000000000000000000000001111100000000000001010001110001 source: 0 changed: 0 step 13 100000000000000000000000000000000001111100000000000001010000110001 source: ; (no change) source: 100000000000000000000000000000000001111100000000000001010000110001 changed: step 14 100000000000000000000000000000000001111100000000000001010000110001 source: source: source: ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; source: ; source: ; set all registers HIGH source: ; source: ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; source: source: ; set pin AF1 which clears pin BB2 and sets pin BR2 TAPE BUS 3 OUTPUT source: 1 0 1 changed: 1 0 1 step 15 100000000000010000000000000000000000111101000000000001010000110001 source: ; set pin AP2 which clears pin AN2 and sets pin BV2 TAPE BUS 2 OUTPUT source: 1 0 1 changed: 1 0 1 step 16 100000000000010010000000000000000000110111000000000001010000110001 source: source: source: ; load TMA SETUP from tape bus (11) source: 111 changed: 111 step 17 100000000000010010000000000000000000110111111000000001010000110001 source: 0 changed: 0 step 18 100000000000010010000000000000000000110111011000000001010000110001 source: ; load TMA from tape bus (11) source: 111 changed: 111 step 19 100000000000010010000000000000000000110111011111000001010000110001 source: 0 changed: 0 step 20 100000000000010010000000000000000000110111011011000001010000110001 source: ; load TBN from tape bus (11) source: 111 changed: 111 step 21 100000000000010010000000000000000000110111011011111001010000110001 source: 0 changed: 0 step 22 100000000000010010000000000000000000110111011011011001010000110001 source: ; load TAC from tape bus (11) source: 11010 changed: 11010 step 23 100000000000010010000000000000000000110111011011011110100000110001 source: 0 changed: 0 step 24 100000000000010010000000000000000000110111011011011010100000110001 source: ; load TB from tape bus (11) source: 111 changed: 111 step 25 100000000000010010000000000000000000110111011011011010101110110001 source: 0 changed: 0 step 26 100000000000010010000000000000000000110111011011011010100110110001 source: ; load RWB from TB (JAMS CLEAR AND PRESET) source: 1 11 changed: 1 11 step 27 100000000000010010000000000000000000110111011011011010100111110111 source: 0 changed: 0 step 28 100000000000010010000000000000000000110111011011011010100110110111 source: ; clear pin AF1 (AND with itself) to set pin BB2 (AND-NOR output) and clear pin BR2 TAPE BUS 3 OUTPUT source: 0 1 0 changed: 0 1 0 step 29 100000000000000010000000000000000001110110011011011010100110110111 source: ; clear pin AP2 (AND with itself) to set pin AN2 (AND-NOR output) and clear pin BV2 TAPE BUS 2 OUTPUT source: 0 1 0 changed: 0 1 0 step 30 100000000000000000000000000000000001111100011011011010100110110111 source: ; (no change) source: 100000000000000000000000000000000001111100011011011010100110110111 changed: step 31 100000000000000000000000000000000001111100011011011010100110110111 source: source: ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; source: ; source: ; will all registers high, walk a 0 source: ; source: ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; source: source: source: ; walk a 0, TMA SETUP 2 source: source: source: ; clear pin AP2 which sets pin AN2 and clears pin BV2 TAPE BUS 2 OUTPUT source: 1 0 1 changed: 1 0 1 step 32 100000000000000010000000000000000001110110011011011010100110110111 source: ; set pin AF1 which clears pin BB2 and sets pin BR2 TAPE BUS 3 OUTPUT source: 1 0 1 changed: 1 0 1 step 33 100000000000010010000000000000000000110111011011011010100110110111 SLOT BAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBAABBAAAAAAAAAAAAAABBBBBABBBB LETTER ALPSLFMDEEMCBFRSPKLEMFHRSCJLJKUHPNMBBNNVVRKRHUTDJUKANJHBTPDFSVEVDU SIDE 121212122121212121111111112212122222112222111221112112212112212122 DIRECTION IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIOOOOOOOIOOIOOIOOIOOOOIOOIIIIOOO source: ; load TMA SETUP from tape bus (01) source: 101 changed: 1 step 34 100000000000010010000000000000000000110111111011011010100110110111 fail ^ SLOT BAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBAABBAAAAAAAAAAAAAABBBBBABBBB LETTER ALPSLFMDEEMCBFRSPKLEMFHRSCJLJKUHPNMBBNNVVRKRHUTDJUKANJHBTPDFSVEVDU SIDE 121212122121212121111111112212122222112222111221112112212112212122 DIRECTION IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIOOOOOOOIOOIOOIOOIOOOOIOOIIIIOOO source: 0 changed: 0 step 35 100000000000010010000000000000000000110111011011011010100110110111 fail ^ SLOT BAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBAABBAAAAAAAAAAAAAABBBBBABBBB LETTER ALPSLFMDEEMCBFRSPKLEMFHRSCJLJKUHPNMBBNNVVRKRHUTDJUKANJHBTPDFSVEVDU SIDE 121212122121212121111111112212122222112222111221112112212112212122 DIRECTION IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIOOOOOOOIOOIOOIOOIOOOOIOOIIIIOOO source: ; restore TMA SETUP 2 source: ; set pin AP2 which clears pin AN2 and sets pin BV2 TAPE BUS 2 OUTPUT source: 1 0 1 changed: step 36 100000000000010010000000000000000000110111011011011010100110110111 fail ^ source: ; load TMA SETUP from tape bus (11) source: 111 changed: 1 step 37 100000000000010010000000000000000000110111111011011010100110110111 source: 0 changed: 0 step 38 100000000000010010000000000000000000110111011011011010100110110111 source: source: source: ; walk a 0, TMA SETUP 3 source: source: source: ; set pin AP2 which clears pin AN2 and sets pin BV2 TAPE BUS 2 OUTPUT source: 1 0 1 changed: step 39 100000000000010010000000000000000000110111011011011010100110110111 SLOT BAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBAABBAAAAAAAAAAAAAABBBBBABBBB LETTER ALPSLFMDEEMCBFRSPKLEMFHRSCJLJKUHPNMBBNNVVRKRHUTDJUKANJHBTPDFSVEVDU SIDE 121212122121212121111111112212122222112222111221112112212112212122 DIRECTION IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIOOOOOOOIOOIOOIOOIOOOOIOOIIIIOOO source: ; clear pin AF1 which sets pin BB2 and clears pin BR2 TAPE BUS 3 OUTPUT source: 0 0 1 changed: 0 1 0 step 40 100000000000000010000000000000000001110110011011011010100110110111 fail ^ ^ SLOT BAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBAABBAAAAAAAAAAAAAABBBBBABBBB LETTER ALPSLFMDEEMCBFRSPKLEMFHRSCJLJKUHPNMBBNNVVRKRHUTDJUKANJHBTPDFSVEVDU SIDE 121212122121212121111111112212122222112222111221112112212112212122 DIRECTION IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIOOOOOOOIOOIOOIOOIOOOOIOOIIIIOOO source: ; load TMA SETUP from tape bus (10) source: 110 changed: 1 0 step 41 100000000000000010000000000000000001110110110011011010100110110111 fail ^ ^ SLOT BAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBAABBAAAAAAAAAAAAAABBBBBABBBB LETTER ALPSLFMDEEMCBFRSPKLEMFHRSCJLJKUHPNMBBNNVVRKRHUTDJUKANJHBTPDFSVEVDU SIDE 121212122121212121111111112212122222112222111221112112212112212122 DIRECTION IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIOOOOOOOIOOIOOIOOIOOOOIOOIIIIOOO source: 0 changed: 0 step 42 100000000000000010000000000000000001110110010011011010100110110111 fail ^ ^ source: ; restore TMA SETUP 3 source: ; set pin AF1 which clears pin BB2 and sets pin BR2 TAPE BUS 3 OUTPUT source: 1 0 1 changed: 1 0 1 step 43 100000000000010010000000000000000000110111010011011010100110110111 source: ; load TMA SETUP from tape bus (11) source: 111 changed: 1 1 step 44 100000000000010010000000000000000000110111111011011010100110110111 source: 0 changed: 0 step 45 100000000000010010000000000000000000110111011011011010100110110111 source: source: source: ; walk a 0, TMA 2 source: source: source: ; clear pin AP2 which sets pin AN2 and clears pin BV2 TAPE BUS 2 OUTPUT source: 1 0 1 changed: step 46 100000000000010010000000000000000000110111011011011010100110110111 source: ; set pin AF1 which clears pin BB2 and sets pin BR2 TAPE BUS 3 OUTPUT source: 1 0 1 changed: step 47 100000000000010010000000000000000000110111011011011010100110110111 SLOT BAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBAABBAAAAAAAAAAAAAABBBBBABBBB LETTER ALPSLFMDEEMCBFRSPKLEMFHRSCJLJKUHPNMBBNNVVRKRHUTDJUKANJHBTPDFSVEVDU SIDE 121212122121212121111111112212122222112222111221112112212112212122 DIRECTION IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIOOOOOOOIOOIOOIOOIOOOOIOOIIIIOOO source: ; load TMA from tape bus (01) source: 101 changed: 1 step 48 100000000000010010000000000000000000110111011111011010100110110111 fail ^ SLOT BAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBAABBAAAAAAAAAAAAAABBBBBABBBB LETTER ALPSLFMDEEMCBFRSPKLEMFHRSCJLJKUHPNMBBNNVVRKRHUTDJUKANJHBTPDFSVEVDU SIDE 121212122121212121111111112212122222112222111221112112212112212122 DIRECTION IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIOOOOOOOIOOIOOIOOIOOOOIOOIIIIOOO source: 0 changed: 0 step 49 100000000000010010000000000000000000110111011011011010100110110111 fail ^ SLOT BAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBAABBAAAAAAAAAAAAAABBBBBABBBB LETTER ALPSLFMDEEMCBFRSPKLEMFHRSCJLJKUHPNMBBNNVVRKRHUTDJUKANJHBTPDFSVEVDU SIDE 121212122121212121111111112212122222112222111221112112212112212122 DIRECTION IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIOOOOOOOIOOIOOIOOIOOOOIOOIIIIOOO source: ; restore TMA 2 source: ; set pin AP2 which clears pin AN2 and sets pin BV2 TAPE BUS 2 OUTPUT source: 1 0 1 changed: step 50 100000000000010010000000000000000000110111011011011010100110110111 fail ^ source: ; load TMA from tape bus (11) source: 111 changed: 1 step 51 100000000000010010000000000000000000110111011111011010100110110111 source: 0 changed: 0 step 52 100000000000010010000000000000000000110111011011011010100110110111 source: source: source: ; walk a 0, TMA 3 source: source: source: ; set pin AP2 which clears pin AN2 and sets pin BV2 TAPE BUS 2 OUTPUT source: 1 0 1 changed: step 53 100000000000010010000000000000000000110111011011011010100110110111 SLOT BAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBAABBAAAAAAAAAAAAAABBBBBABBBB LETTER ALPSLFMDEEMCBFRSPKLEMFHRSCJLJKUHPNMBBNNVVRKRHUTDJUKANJHBTPDFSVEVDU SIDE 121212122121212121111111112212122222112222111221112112212112212122 DIRECTION IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIOOOOOOOIOOIOOIOOIOOOOIOOIIIIOOO source: ; clear pin AF1 which sets pin BB2 and clears pin BR2 TAPE BUS 3 OUTPUT source: 0 0 1 changed: 0 1 0 step 54 100000000000000010000000000000000001110110011011011010100110110111 fail ^ ^ SLOT BAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBAABBAAAAAAAAAAAAAABBBBBABBBB LETTER ALPSLFMDEEMCBFRSPKLEMFHRSCJLJKUHPNMBBNNVVRKRHUTDJUKANJHBTPDFSVEVDU SIDE 121212122121212121111111112212122222112222111221112112212112212122 DIRECTION IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIOOOOOOOIOOIOOIOOIOOOOIOOIIIIOOO source: ; load TMA from tape bus (10) source: 110 changed: 1 0 step 55 100000000000000010000000000000000001110110011110011010100110110111 fail ^ ^ SLOT BAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBAABBAAAAAAAAAAAAAABBBBBABBBB LETTER ALPSLFMDEEMCBFRSPKLEMFHRSCJLJKUHPNMBBNNVVRKRHUTDJUKANJHBTPDFSVEVDU SIDE 121212122121212121111111112212122222112222111221112112212112212122 DIRECTION IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIOOOOOOOIOOIOOIOOIOOOOIOOIIIIOOO source: 0 changed: 0 step 56 100000000000000010000000000000000001110110011010011010100110110111 fail ^ ^ source: ; restore TMA 3 source: ; set pin AF1 which clears pin BB2 and sets pin BR2 TAPE BUS 3 OUTPUT source: 1 0 1 changed: 1 0 1 step 57 100000000000010010000000000000000000110111011010011010100110110111 source: ; load TMA from tape bus (11) source: 111 changed: 1 1 step 58 100000000000010010000000000000000000110111011111011010100110110111 source: 0 changed: 0 step 59 100000000000010010000000000000000000110111011011011010100110110111 SLOT BAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBAABBAAAAAAAAAAAAAABBBBBABBBB LETTER ALPSLFMDEEMCBFRSPKLEMFHRSCJLJKUHPNMBBNNVVRKRHUTDJUKANJHBTPDFSVEVDU SIDE 121212122121212121111111112212122222112222111221112112212112212122 DIRECTION IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIOOOOOOOIOOIOOIOOIOOOOIOOIIIIOOO source: source: source: source: source: source: source: source: source: source: source: source: ; load TBN from tape bus (00) source: 100 changed: 1 step 60 100000000000010010000000000000000000110111011011111010100110110111 fail ^^ SLOT BAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBAABBAAAAAAAAAAAAAABBBBBABBBB LETTER ALPSLFMDEEMCBFRSPKLEMFHRSCJLJKUHPNMBBNNVVRKRHUTDJUKANJHBTPDFSVEVDU SIDE 121212122121212121111111112212122222112222111221112112212112212122 DIRECTION IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIOOOOOOOIOOIOOIOOIOOOOIOOIIIIOOO source: 0 changed: 0 step 61 100000000000010010000000000000000000110111011011011010100110110111 fail ^^ SLOT BAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBAABBAAAAAAAAAAAAAABBBBBABBBB LETTER ALPSLFMDEEMCBFRSPKLEMFHRSCJLJKUHPNMBBNNVVRKRHUTDJUKANJHBTPDFSVEVDU SIDE 121212122121212121111111112212122222112222111221112112212112212122 DIRECTION IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIOOOOOOOIOOIOOIOOIOOOOIOOIIIIOOO source: ; load TAC from tape bus (00) source: 10101 changed: 1 step 62 100000000000010010000000000000000000110111011011011110100110110111 fail ^^ ^^^^ SLOT BAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBAABBAAAAAAAAAAAAAABBBBBABBBB LETTER ALPSLFMDEEMCBFRSPKLEMFHRSCJLJKUHPNMBBNNVVRKRHUTDJUKANJHBTPDFSVEVDU SIDE 121212122121212121111111112212122222112222111221112112212112212122 DIRECTION IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIOOOOOOOIOOIOOIOOIOOOOIOOIIIIOOO source: 0 changed: 0 step 63 100000000000010010000000000000000000110111011011011010100110110111 fail ^^ ^^^^ SLOT BAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBAABBAAAAAAAAAAAAAABBBBBABBBB LETTER ALPSLFMDEEMCBFRSPKLEMFHRSCJLJKUHPNMBBNNVVRKRHUTDJUKANJHBTPDFSVEVDU SIDE 121212122121212121111111112212122222112222111221112112212112212122 DIRECTION IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIOOOOOOOIOOIOOIOOIOOOOIOOIIIIOOO source: ; load TB from tape bus (00) source: 100 changed: 1 step 64 100000000000010010000000000000000000110111011011011010101110110111 fail ^^ ^^^^ ^^ SLOT BAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBAABBAAAAAAAAAAAAAABBBBBABBBB LETTER ALPSLFMDEEMCBFRSPKLEMFHRSCJLJKUHPNMBBNNVVRKRHUTDJUKANJHBTPDFSVEVDU SIDE 121212122121212121111111112212122222112222111221112112212112212122 DIRECTION IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIOOOOOOOIOOIOOIOOIOOOOIOOIIIIOOO source: 0 changed: 0 step 65 100000000000010010000000000000000000110111011011011010100110110111 fail ^^ ^^^^ ^^ SLOT BAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBAABBAAAAAAAAAAAAAABBBBBABBBB LETTER ALPSLFMDEEMCBFRSPKLEMFHRSCJLJKUHPNMBBNNVVRKRHUTDJUKANJHBTPDFSVEVDU SIDE 121212122121212121111111112212122222112222111221112112212112212122 DIRECTION IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIOOOOOOOIOOIOOIOOIOOOOIOOIIIIOOO source: ; load RWB from TB (JAMS CLEAR AND PRESET) source: 1 00 changed: 1 step 66 100000000000010010000000000000000000110111011011011010100111110111 fail ^^ ^^^^ ^^ ^^ SLOT BAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBAABBAAAAAAAAAAAAAABBBBBABBBB LETTER ALPSLFMDEEMCBFRSPKLEMFHRSCJLJKUHPNMBBNNVVRKRHUTDJUKANJHBTPDFSVEVDU SIDE 121212122121212121111111112212122222112222111221112112212112212122 DIRECTION IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIOOOOOOOIOOIOOIOOIOOOOIOOIIIIOOO source: 0 changed: 0 step 67 100000000000010010000000000000000000110111011011011010100110110111 fail ^^ ^^^^ ^^ ^^ SLOT BAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBAABBAAAAAAAAAAAAAABBBBBABBBB LETTER ALPSLFMDEEMCBFRSPKLEMFHRSCJLJKUHPNMBBNNVVRKRHUTDJUKANJHBTPDFSVEVDU SIDE 121212122121212121111111112212122222112222111221112112212112212122 DIRECTION IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIOOOOOOOIOOIOOIOOIOOOOIOOIIIIOOO source: source: source: source: source: source: source: source: source: source: source: source: source: source: source: ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; source: ; source: ; test AND-NOR logic source: ; source: ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; source: source: ; (all registers are HIGH) source: ; set all pins HIGH except ENABLES source: source: ; set pin AF2 HIGH source: 1 changed: 1 step 68 100001000000010010000000000000000000110111011011011010100110110111 fail ^^ ^^^^ ^^ ^^ SLOT BAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBAABBAAAAAAAAAAAAAABBBBBABBBB LETTER ALPSLFMDEEMCBFRSPKLEMFHRSCJLJKUHPNMBBNNVVRKRHUTDJUKANJHBTPDFSVEVDU SIDE 121212122121212121111111112212122222112222111221112112212112212122 DIRECTION IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIOOOOOOOIOOIOOIOOIOOOOIOOIIIIOOO source: ; set pin AM1 HIGH source: 1 changed: 1 step 69 100001100000010010000000000000000000110111011011011010100110110111 fail ^^ ^^^^ ^^ ^^ SLOT BAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBAABBAAAAAAAAAAAAAABBBBBABBBB LETTER ALPSLFMDEEMCBFRSPKLEMFHRSCJLJKUHPNMBBNNVVRKRHUTDJUKANJHBTPDFSVEVDU SIDE 121212122121212121111111112212122222112222111221112112212112212122 DIRECTION IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIOOOOOOOIOOIOOIOOIOOOOIOOIIIIOOO source: ; set pin AE1 HIGH source: 1 changed: 1 step 70 100001100100010010000000000000000000110111011011011010100110110111 fail ^^ ^^^^ ^^ ^^ SLOT BAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBAABBAAAAAAAAAAAAAABBBBBABBBB LETTER ALPSLFMDEEMCBFRSPKLEMFHRSCJLJKUHPNMBBNNVVRKRHUTDJUKANJHBTPDFSVEVDU SIDE 121212122121212121111111112212122222112222111221112112212112212122 DIRECTION IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIOOOOOOOIOOIOOIOOIOOOOIOOIIIIOOO source: ; set pin AM2 HIGH source: 1 changed: 1 step 71 100001100110010010000000000000000000110111011011011010100110110111 fail ^^ ^^^^ ^^ ^^ SLOT BAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBAABBAAAAAAAAAAAAAABBBBBABBBB LETTER ALPSLFMDEEMCBFRSPKLEMFHRSCJLJKUHPNMBBNNVVRKRHUTDJUKANJHBTPDFSVEVDU SIDE 121212122121212121111111112212122222112222111221112112212112212122 DIRECTION IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIOOOOOOOIOOIOOIOOIOOOOIOOIIIIOOO source: ; set pin AB2 HIGH source: 1 changed: 1 step 72 100001100110110010000000000000000000110111011011011010100110110111 fail ^^ ^^^^ ^^ ^^ SLOT BAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBAABBAAAAAAAAAAAAAABBBBBABBBB LETTER ALPSLFMDEEMCBFRSPKLEMFHRSCJLJKUHPNMBBNNVVRKRHUTDJUKANJHBTPDFSVEVDU SIDE 121212122121212121111111112212122222112222111221112112212112212122 DIRECTION IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIOOOOOOOIOOIOOIOOIOOOOIOOIIIIOOO source: ; set pin AS1 HIGH source: 1 changed: 1 step 73 100001100110110110000000000000000000110111011011011010100110110111 fail ^^ ^^^^ ^^ ^^ SLOT BAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBAABBAAAAAAAAAAAAAABBBBBABBBB LETTER ALPSLFMDEEMCBFRSPKLEMFHRSCJLJKUHPNMBBNNVVRKRHUTDJUKANJHBTPDFSVEVDU SIDE 121212122121212121111111112212122222112222111221112112212112212122 DIRECTION IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIOOOOOOOIOOIOOIOOIOOOOIOOIIIIOOO source: ; set pin BE1 HIGH source: 1 changed: 1 step 74 100001100110110110010000000000000000110111011011011010100110110111 fail ^^ ^^^^ ^^ ^^ SLOT BAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBAABBAAAAAAAAAAAAAABBBBBABBBB LETTER ALPSLFMDEEMCBFRSPKLEMFHRSCJLJKUHPNMBBNNVVRKRHUTDJUKANJHBTPDFSVEVDU SIDE 121212122121212121111111112212122222112222111221112112212112212122 DIRECTION IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIOOOOOOOIOOIOOIOOIOOOOIOOIIIIOOO source: ; set pin BM1 HIGH source: 1 changed: 1 step 75 100001100110110110011000000000000000110111011011011010100110110111 fail ^^ ^^^^ ^^ ^^ SLOT BAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBAABBAAAAAAAAAAAAAABBBBBABBBB LETTER ALPSLFMDEEMCBFRSPKLEMFHRSCJLJKUHPNMBBNNVVRKRHUTDJUKANJHBTPDFSVEVDU SIDE 121212122121212121111111112212122222112222111221112112212112212122 DIRECTION IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIOOOOOOOIOOIOOIOOIOOOOIOOIIIIOOO source: ; set pin BH1 HIGH source: 1 changed: 1 step 76 100001100110110110011010000000000000110111011011011010100110110111 fail ^^ ^^^^ ^^ ^^ SLOT BAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBAABBAAAAAAAAAAAAAABBBBBABBBB LETTER ALPSLFMDEEMCBFRSPKLEMFHRSCJLJKUHPNMBBNNVVRKRHUTDJUKANJHBTPDFSVEVDU SIDE 121212122121212121111111112212122222112222111221112112212112212122 DIRECTION IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIOOOOOOOIOOIOOIOOIOOOOIOOIIIIOOO source: ; set pin BR1 HIGH source: 1 changed: 1 step 77 100001100110110110011011000000000000110111011011011010100110110111 fail ^^ ^^^^ ^^ ^^ SLOT BAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBAABBAAAAAAAAAAAAAABBBBBABBBB LETTER ALPSLFMDEEMCBFRSPKLEMFHRSCJLJKUHPNMBBNNVVRKRHUTDJUKANJHBTPDFSVEVDU SIDE 121212122121212121111111112212122222112222111221112112212112212122 DIRECTION IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIOOOOOOOIOOIOOIOOIOOOOIOOIIIIOOO source: ; set pin BC1 HIGH source: 1 changed: 1 step 78 100001100110110110011011010000000000110111011011011010100110110111 fail ^^ ^^^^ ^^ ^^ SLOT BAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBAABBAAAAAAAAAAAAAABBBBBABBBB LETTER ALPSLFMDEEMCBFRSPKLEMFHRSCJLJKUHPNMBBNNVVRKRHUTDJUKANJHBTPDFSVEVDU SIDE 121212122121212121111111112212122222112222111221112112212112212122 DIRECTION IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIOOOOOOOIOOIOOIOOIOOOOIOOIIIIOOO source: ; set pin BJ2 HIGH source: 1 changed: 1 step 79 100001100110110110011011011000000000110111011011011010100110110111 fail ^^ ^^^^ ^^ ^^ SLOT BAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBAABBAAAAAAAAAAAAAABBBBBABBBB LETTER ALPSLFMDEEMCBFRSPKLEMFHRSCJLJKUHPNMBBNNVVRKRHUTDJUKANJHBTPDFSVEVDU SIDE 121212122121212121111111112212122222112222111221112112212112212122 DIRECTION IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIOOOOOOOIOOIOOIOOIOOOOIOOIIIIOOO source: ; set pin BJ1 HIGH source: 1 changed: 1 step 80 100001100110110110011011011010000000110111011011011010100110110111 fail ^^ ^^^^ ^^ ^^ SLOT BAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBAABBAAAAAAAAAAAAAABBBBBABBBB LETTER ALPSLFMDEEMCBFRSPKLEMFHRSCJLJKUHPNMBBNNVVRKRHUTDJUKANJHBTPDFSVEVDU SIDE 121212122121212121111111112212122222112222111221112112212112212122 DIRECTION IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIOOOOOOOIOOIOOIOOIOOOOIOOIIIIOOO source: ; set pin BK2 HIGH source: 1 changed: 1 step 81 100001100110110110011011011011000000110111011011011010100110110111 fail ^^ ^^^^ ^^ ^^ SLOT BAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBAABBAAAAAAAAAAAAAABBBBBABBBB LETTER ALPSLFMDEEMCBFRSPKLEMFHRSCJLJKUHPNMBBNNVVRKRHUTDJUKANJHBTPDFSVEVDU SIDE 121212122121212121111111112212122222112222111221112112212112212122 DIRECTION IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIOOOOOOOIOOIOOIOOIOOOOIOOIIIIOOO source: ; set pin BH2 HIGH source: 1 changed: 1 step 82 100001100110110110011011011011010000110111011011011010100110110111 fail ^^ ^^^^ ^^ ^^ SLOT BAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBAABBAAAAAAAAAAAAAABBBBBABBBB LETTER ALPSLFMDEEMCBFRSPKLEMFHRSCJLJKUHPNMBBNNVVRKRHUTDJUKANJHBTPDFSVEVDU SIDE 121212122121212121111111112212122222112222111221112112212112212122 DIRECTION IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIOOOOOOOIOOIOOIOOIOOOOIOOIIIIOOO source: ; set pin BP2 HIGH source: 1 changed: 1 step 83 100001100110110110011011011011011000110111011011011010100110110111 fail ^^ ^^^^ ^^ ^^ SLOT BAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBAABBAAAAAAAAAAAAAABBBBBABBBB LETTER ALPSLFMDEEMCBFRSPKLEMFHRSCJLJKUHPNMBBNNVVRKRHUTDJUKANJHBTPDFSVEVDU SIDE 121212122121212121111111112212122222112222111221112112212112212122 DIRECTION IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIOOOOOOOIOOIOOIOOIOOOOIOOIIIIOOO source: ; set pin BN2 HIGH source: 1 changed: 1 step 84 100001100110110110011011011011011100110111011011011010100110110111 fail ^^ ^^^^ ^^ ^^ SLOT BAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBAABBAAAAAAAAAAAAAABBBBBABBBB LETTER ALPSLFMDEEMCBFRSPKLEMFHRSCJLJKUHPNMBBNNVVRKRHUTDJUKANJHBTPDFSVEVDU SIDE 121212122121212121111111112212122222112222111221112112212112212122 DIRECTION IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIOOOOOOOIOOIOOIOOIOOOOIOOIIIIOOO source: ; toggle each ENABLE source: source: ; set pin AL2 to clear pin BB2 and pin AN2 AND-NOR OUTPUTS and set TAPE BUS 2 OUTPUT and TAPE BUS 3 OUTPUT source: 1 0 0 11 changed: 1 step 85 110001100110110110011011011011011100110111011011011010100110110111 fail ^^ ^^^^ ^^ ^^ SLOT BAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBAABBAAAAAAAAAAAAAABBBBBABBBB LETTER ALPSLFMDEEMCBFRSPKLEMFHRSCJLJKUHPNMBBNNVVRKRHUTDJUKANJHBTPDFSVEVDU SIDE 121212122121212121111111112212122222112222111221112112212112212122 DIRECTION IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIOOOOOOOIOOIOOIOOIOOOOIOOIIIIOOO source: 0 1 1 00 changed: 0 step 86 100001100110110110011011011011011100110111011011011010100110110111 fail ^ ^ ^^ ^^ ^^^^ ^^ ^^ SLOT BAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBAABBAAAAAAAAAAAAAABBBBBABBBB LETTER ALPSLFMDEEMCBFRSPKLEMFHRSCJLJKUHPNMBBNNVVRKRHUTDJUKANJHBTPDFSVEVDU SIDE 121212122121212121111111112212122222112222111221112112212112212122 DIRECTION IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIOOOOOOOIOOIOOIOOIOOOOIOOIIIIOOO source: ; set pin AP1 to clear pin BB2 and pin AN2 AND-NOR OUTPUTS and set TAPE BUS 2 OUTPUT and TAPE BUS 3 OUTPUT source: 1 0 0 11 changed: 1 step 87 101001100110110110011011011011011100110111011011011010100110110111 fail ^^ ^^^^ ^^ ^^ SLOT BAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBAABBAAAAAAAAAAAAAABBBBBABBBB LETTER ALPSLFMDEEMCBFRSPKLEMFHRSCJLJKUHPNMBBNNVVRKRHUTDJUKANJHBTPDFSVEVDU SIDE 121212122121212121111111112212122222112222111221112112212112212122 DIRECTION IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIOOOOOOOIOOIOOIOOIOOOOIOOIIIIOOO source: 0 1 1 00 changed: 0 step 88 100001100110110110011011011011011100110111011011011010100110110111 fail ^ ^ ^^ ^^ ^^^^ ^^ ^^ SLOT BAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBAABBAAAAAAAAAAAAAABBBBBABBBB LETTER ALPSLFMDEEMCBFRSPKLEMFHRSCJLJKUHPNMBBNNVVRKRHUTDJUKANJHBTPDFSVEVDU SIDE 121212122121212121111111112212122222112222111221112112212112212122 DIRECTION IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIOOOOOOOIOOIOOIOOIOOOOIOOIIIIOOO source: ; set pin AS2 to clear pin BB2 and pin AN2 AND-NOR OUTPUTS and set TAPE BUS 2 OUTPUT and TAPE BUS 3 OUTPUT source: 1 0 0 11 changed: 1 step 89 100101100110110110011011011011011100110111011011011010100110110111 fail ^^ ^^^^ ^^ ^^ SLOT BAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBAABBAAAAAAAAAAAAAABBBBBABBBB LETTER ALPSLFMDEEMCBFRSPKLEMFHRSCJLJKUHPNMBBNNVVRKRHUTDJUKANJHBTPDFSVEVDU SIDE 121212122121212121111111112212122222112222111221112112212112212122 DIRECTION IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIOOOOOOOIOOIOOIOOIOOOOIOOIIIIOOO source: 0 1 1 00 changed: 0 step 90 100001100110110110011011011011011100110111011011011010100110110111 fail ^ ^ ^^ ^^ ^^^^ ^^ ^^ SLOT BAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBAABBAAAAAAAAAAAAAABBBBBABBBB LETTER ALPSLFMDEEMCBFRSPKLEMFHRSCJLJKUHPNMBBNNVVRKRHUTDJUKANJHBTPDFSVEVDU SIDE 121212122121212121111111112212122222112222111221112112212112212122 DIRECTION IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIOOOOOOOIOOIOOIOOIOOOOIOOIIIIOOO source: ; set pin AL1 to clear pin BB2 and pin AN2 AND-NOR OUTPUTS and set TAPE BUS 2 OUTPUT and TAPE BUS 3 OUTPUT source: 1 0 0 11 changed: 1 step 91 100011100110110110011011011011011100110111011011011010100110110111 fail ^^ ^^^^ ^^ ^^ SLOT BAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBAABBAAAAAAAAAAAAAABBBBBABBBB LETTER ALPSLFMDEEMCBFRSPKLEMFHRSCJLJKUHPNMBBNNVVRKRHUTDJUKANJHBTPDFSVEVDU SIDE 121212122121212121111111112212122222112222111221112112212112212122 DIRECTION IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIOOOOOOOIOOIOOIOOIOOOOIOOIIIIOOO source: 0 1 1 00 changed: 0 step 92 100001100110110110011011011011011100110111011011011010100110110111 fail ^ ^ ^^ ^^ ^^^^ ^^ ^^ SLOT BAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBAABBAAAAAAAAAAAAAABBBBBABBBB LETTER ALPSLFMDEEMCBFRSPKLEMFHRSCJLJKUHPNMBBNNVVRKRHUTDJUKANJHBTPDFSVEVDU SIDE 121212122121212121111111112212122222112222111221112112212112212122 DIRECTION IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIOOOOOOOIOOIOOIOOIOOOOIOOIIIIOOO source: ; set pin AL1 to clear pin BB2 and pin AN2 AND-NOR OUTPUTS and set TAPE BUS 2 OUTPUT and TAPE BUS 3 OUTPUT source: 1 0 0 11 changed: 1 step 93 100001110110110110011011011011011100110111011011011010100110110111 fail ^^ ^^^^ ^^ ^^ SLOT BAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBAABBAAAAAAAAAAAAAABBBBBABBBB LETTER ALPSLFMDEEMCBFRSPKLEMFHRSCJLJKUHPNMBBNNVVRKRHUTDJUKANJHBTPDFSVEVDU SIDE 121212122121212121111111112212122222112222111221112112212112212122 DIRECTION IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIOOOOOOOIOOIOOIOOIOOOOIOOIIIIOOO source: 0 1 1 00 changed: 0 step 94 100001100110110110011011011011011100110111011011011010100110110111 fail ^ ^ ^^ ^^ ^^^^ ^^ ^^ SLOT BAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBAABBAAAAAAAAAAAAAABBBBBABBBB LETTER ALPSLFMDEEMCBFRSPKLEMFHRSCJLJKUHPNMBBNNVVRKRHUTDJUKANJHBTPDFSVEVDU SIDE 121212122121212121111111112212122222112222111221112112212112212122 DIRECTION IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIOOOOOOOIOOIOOIOOIOOOOIOOIIIIOOO source: ; set pin AE2 to clear pin BB2 and pin AN2 AND-NOR OUTPUTS and set TAPE BUS 2 OUTPUT and TAPE BUS 3 OUTPUT source: 1 0 0 11 changed: 1 step 95 100001101110110110011011011011011100110111011011011010100110110111 fail ^^ ^^^^ ^^ ^^ SLOT BAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBAABBAAAAAAAAAAAAAABBBBBABBBB LETTER ALPSLFMDEEMCBFRSPKLEMFHRSCJLJKUHPNMBBNNVVRKRHUTDJUKANJHBTPDFSVEVDU SIDE 121212122121212121111111112212122222112222111221112112212112212122 DIRECTION IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIOOOOOOOIOOIOOIOOIOOOOIOOIIIIOOO source: 0 1 1 00 changed: 0 step 96 100001100110110110011011011011011100110111011011011010100110110111 fail ^ ^ ^^ ^^ ^^^^ ^^ ^^ SLOT BAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBAABBAAAAAAAAAAAAAABBBBBABBBB LETTER ALPSLFMDEEMCBFRSPKLEMFHRSCJLJKUHPNMBBNNVVRKRHUTDJUKANJHBTPDFSVEVDU SIDE 121212122121212121111111112212122222112222111221112112212112212122 DIRECTION IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIOOOOOOOIOOIOOIOOIOOOOIOOIIIIOOO source: ; set pin AC1 to clear pin BB2 and set TAPE BUS 3 OUTPUT source: 1 0 1 changed: 1 step 97 100001100111110110011011011011011100110111011011011010100110110111 fail ^ ^ ^^ ^^^^ ^^ ^^ SLOT BAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBAABBAAAAAAAAAAAAAABBBBBABBBB LETTER ALPSLFMDEEMCBFRSPKLEMFHRSCJLJKUHPNMBBNNVVRKRHUTDJUKANJHBTPDFSVEVDU SIDE 121212122121212121111111112212122222112222111221112112212112212122 DIRECTION IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIOOOOOOOIOOIOOIOOIOOOOIOOIIIIOOO source: 0 1 0 changed: 0 step 98 100001100110110110011011011011011100110111011011011010100110110111 fail ^ ^ ^^ ^^ ^^^^ ^^ ^^ SLOT BAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBAABBAAAAAAAAAAAAAABBBBBABBBB LETTER ALPSLFMDEEMCBFRSPKLEMFHRSCJLJKUHPNMBBNNVVRKRHUTDJUKANJHBTPDFSVEVDU SIDE 121212122121212121111111112212122222112222111221112112212112212122 DIRECTION IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIOOOOOOOIOOIOOIOOIOOOOIOOIIIIOOO source: ; set pin AF1 to clear pin BB2 and set TAPE BUS 3 OUTPUT source: 1 0 1 changed: step 99 100001100110110110011011011011011100110111011011011010100110110111 fail ^ ^ ^^ ^^^^ ^^ ^^ SLOT BAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBAABBAAAAAAAAAAAAAABBBBBABBBB LETTER ALPSLFMDEEMCBFRSPKLEMFHRSCJLJKUHPNMBBNNVVRKRHUTDJUKANJHBTPDFSVEVDU SIDE 121212122121212121111111112212122222112222111221112112212112212122 DIRECTION IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIOOOOOOOIOOIOOIOOIOOOOIOOIIIIOOO source: 0 1 0 changed: 0 1 0 step 100 100001100110100110011011011011011101110110011011011010100110110111 fail ^ ^ ^^ ^^^^ ^^ ^^ SLOT BAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBAABBAAAAAAAAAAAAAABBBBBABBBB LETTER ALPSLFMDEEMCBFRSPKLEMFHRSCJLJKUHPNMBBNNVVRKRHUTDJUKANJHBTPDFSVEVDU SIDE 121212122121212121111111112212122222112222111221112112212112212122 DIRECTION IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIOOOOOOOIOOIOOIOOIOOOOIOOIIIIOOO source: ; set pin AR2 to clear pin AN2 AND-NOR OUTPUTS and set TAPE BUS 2 OUTPUT source: 1 0 1 changed: 1 step 101 100001100110101110011011011011011101110110011011011010100110110111 fail ^^ ^^^^ ^^ ^^ SLOT BAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBAABBAAAAAAAAAAAAAABBBBBABBBB LETTER ALPSLFMDEEMCBFRSPKLEMFHRSCJLJKUHPNMBBNNVVRKRHUTDJUKANJHBTPDFSVEVDU SIDE 121212122121212121111111112212122222112222111221112112212112212122 DIRECTION IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIOOOOOOOIOOIOOIOOIOOOOIOOIIIIOOO source: 0 1 0 changed: 0 step 102 100001100110100110011011011011011101110110011011011010100110110111 fail ^ ^ ^^ ^^^^ ^^ ^^ SLOT BAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBAABBAAAAAAAAAAAAAABBBBBABBBB LETTER ALPSLFMDEEMCBFRSPKLEMFHRSCJLJKUHPNMBBNNVVRKRHUTDJUKANJHBTPDFSVEVDU SIDE 121212122121212121111111112212122222112222111221112112212112212122 DIRECTION IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIOOOOOOOIOOIOOIOOIOOOOIOOIIIIOOO source: ; set pin AP2 to clear pin AN2 AND-NOR OUTPUTS and set TAPE BUS 2 OUTPUT source: 1 0 1 changed: step 103 100001100110100110011011011011011101110110011011011010100110110111 fail ^^ ^^^^ ^^ ^^ SLOT BAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBAABBAAAAAAAAAAAAAABBBBBABBBB LETTER ALPSLFMDEEMCBFRSPKLEMFHRSCJLJKUHPNMBBNNVVRKRHUTDJUKANJHBTPDFSVEVDU SIDE 121212122121212121111111112212122222112222111221112112212112212122 DIRECTION IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIOOOOOOOIOOIOOIOOIOOOOIOOIIIIOOO source: 0 1 0 changed: 0 1 0 step 104 100001100110100100011011011011011101111100011011011010100110110111 fail ^^ ^^^^ ^^ ^^ SLOT BAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBAABBAAAAAAAAAAAAAABBBBBABBBB LETTER ALPSLFMDEEMCBFRSPKLEMFHRSCJLJKUHPNMBBNNVVRKRHUTDJUKANJHBTPDFSVEVDU SIDE 121212122121212121111111112212122222112222111221112112212112212122 DIRECTION IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIOOOOOOOIOOIOOIOOIOOOOIOOIIIIOOO source: source: ; set pin BK1 to clear pin BB1 and pin BN1 AND-NOR OUTPUTS and set TAPE BUS 2 OUTPUT and TAPE BUS 3 OUTPUT source: 1 00 11 changed: 1 00 11 step 105 100001100110100101011011011011011101001111011011011010100110110111 fail ^^ ^^^^ ^^ ^^ SLOT BAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBAABBAAAAAAAAAAAAAABBBBBABBBB LETTER ALPSLFMDEEMCBFRSPKLEMFHRSCJLJKUHPNMBBNNVVRKRHUTDJUKANJHBTPDFSVEVDU SIDE 121212122121212121111111112212122222112222111221112112212112212122 DIRECTION IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIOOOOOOOIOOIOOIOOIOOOOIOOIIIIOOO source: 0 11 00 changed: 0 11 00 step 106 100001100110100100011011011011011101111100011011011010100110110111 fail ^^ ^^^^ ^^ ^^ SLOT BAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBAABBAAAAAAAAAAAAAABBBBBABBBB LETTER ALPSLFMDEEMCBFRSPKLEMFHRSCJLJKUHPNMBBNNVVRKRHUTDJUKANJHBTPDFSVEVDU SIDE 121212122121212121111111112212122222112222111221112112212112212122 DIRECTION IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIOOOOOOOIOOIOOIOOIOOOOIOOIIIIOOO source: ; set pin BL1 to clear pin BB1 and pin BN1 AND-NOR OUTPUTS and set TAPE BUS 2 OUTPUT and TAPE BUS 3 OUTPUT source: 1 00 11 changed: 1 00 11 step 107 100001100110100100111011011011011101001111011011011010100110110111 fail ^^ ^^^^ ^^ ^^ SLOT BAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBAABBAAAAAAAAAAAAAABBBBBABBBB LETTER ALPSLFMDEEMCBFRSPKLEMFHRSCJLJKUHPNMBBNNVVRKRHUTDJUKANJHBTPDFSVEVDU SIDE 121212122121212121111111112212122222112222111221112112212112212122 DIRECTION IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIOOOOOOOIOOIOOIOOIOOOOIOOIIIIOOO source: 0 11 00 changed: 0 11 00 step 108 100001100110100100011011011011011101111100011011011010100110110111 fail ^^ ^^^^ ^^ ^^ SLOT BAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBAABBAAAAAAAAAAAAAABBBBBABBBB LETTER ALPSLFMDEEMCBFRSPKLEMFHRSCJLJKUHPNMBBNNVVRKRHUTDJUKANJHBTPDFSVEVDU SIDE 121212122121212121111111112212122222112222111221112112212112212122 DIRECTION IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIOOOOOOOIOOIOOIOOIOOOOIOOIIIIOOO source: ; set pin BF1 to clear pin BB1 and pin BN1 AND-NOR OUTPUTS and set TAPE BUS 2 OUTPUT and TAPE BUS 3 OUTPUT source: 1 00 11 changed: 1 00 11 step 109 100001100110100100011111011011011101001111011011011010100110110111 fail ^^ ^^^^ ^^ ^^ SLOT BAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBAABBAAAAAAAAAAAAAABBBBBABBBB LETTER ALPSLFMDEEMCBFRSPKLEMFHRSCJLJKUHPNMBBNNVVRKRHUTDJUKANJHBTPDFSVEVDU SIDE 121212122121212121111111112212122222112222111221112112212112212122 DIRECTION IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIOOOOOOOIOOIOOIOOIOOOOIOOIIIIOOO source: 0 11 00 changed: 0 11 00 step 110 100001100110100100011011011011011101111100011011011010100110110111 fail ^^ ^^^^ ^^ ^^ SLOT BAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBAABBAAAAAAAAAAAAAABBBBBABBBB LETTER ALPSLFMDEEMCBFRSPKLEMFHRSCJLJKUHPNMBBNNVVRKRHUTDJUKANJHBTPDFSVEVDU SIDE 121212122121212121111111112212122222112222111221112112212112212122 DIRECTION IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIOOOOOOOIOOIOOIOOIOOOOIOOIIIIOOO source: ; set pin BS1 to clear pin BB1 and pin BN1 AND-NOR OUTPUTS and set TAPE BUS 2 OUTPUT and TAPE BUS 3 OUTPUT source: 1 00 11 changed: 1 00 11 step 111 100001100110100100011011111011011101001111011011011010100110110111 fail ^^ ^^^^ ^^ ^^ SLOT BAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBAABBAAAAAAAAAAAAAABBBBBABBBB LETTER ALPSLFMDEEMCBFRSPKLEMFHRSCJLJKUHPNMBBNNVVRKRHUTDJUKANJHBTPDFSVEVDU SIDE 121212122121212121111111112212122222112222111221112112212112212122 DIRECTION IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIOOOOOOOIOOIOOIOOIOOOOIOOIIIIOOO source: 0 11 00 changed: 0 11 00 step 112 100001100110100100011011011011011101111100011011011010100110110111 fail ^^ ^^^^ ^^ ^^ SLOT BAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBAABBAAAAAAAAAAAAAABBBBBABBBB LETTER ALPSLFMDEEMCBFRSPKLEMFHRSCJLJKUHPNMBBNNVVRKRHUTDJUKANJHBTPDFSVEVDU SIDE 121212122121212121111111112212122222112222111221112112212112212122 DIRECTION IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIOOOOOOOIOOIOOIOOIOOOOIOOIIIIOOO source: ; set pin BL2 to clear pin BB1 and pin BN1 AND-NOR OUTPUTS and set TAPE BUS 2 OUTPUT and TAPE BUS 3 OUTPUT source: 1 00 11 changed: 1 00 11 step 113 100001100110100100011011011111011101001111011011011010100110110111 fail ^^ ^^^^ ^^ ^^ SLOT BAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBAABBAAAAAAAAAAAAAABBBBBABBBB LETTER ALPSLFMDEEMCBFRSPKLEMFHRSCJLJKUHPNMBBNNVVRKRHUTDJUKANJHBTPDFSVEVDU SIDE 121212122121212121111111112212122222112222111221112112212112212122 DIRECTION IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIOOOOOOOIOOIOOIOOIOOOOIOOIIIIOOO source: 0 11 00 changed: 0 11 00 step 114 100001100110100100011011011011011101111100011011011010100110110111 fail ^^ ^^^^ ^^ ^^ SLOT BAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBAABBAAAAAAAAAAAAAABBBBBABBBB LETTER ALPSLFMDEEMCBFRSPKLEMFHRSCJLJKUHPNMBBNNVVRKRHUTDJUKANJHBTPDFSVEVDU SIDE 121212122121212121111111112212122222112222111221112112212112212122 DIRECTION IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIOOOOOOOIOOIOOIOOIOOOOIOOIIIIOOO source: ; set pin BU1 to clear pin BB1 and pin BN1 AND-NOR OUTPUTS and set TAPE BUS 2 OUTPUT and TAPE BUS 3 OUTPUT source: 1 00 11 changed: 1 00 11 step 115 100001100110100100011011011011111101001111011011011010100110110111 fail ^^ ^^^^ ^^ ^^ SLOT BAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBAABBAAAAAAAAAAAAAABBBBBABBBB LETTER ALPSLFMDEEMCBFRSPKLEMFHRSCJLJKUHPNMBBNNVVRKRHUTDJUKANJHBTPDFSVEVDU SIDE 121212122121212121111111112212122222112222111221112112212112212122 DIRECTION IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIOOOOOOOIOOIOOIOOIOOOOIOOIIIIOOO source: 0 11 00 changed: 0 11 00 step 116 100001100110100100011011011011011101111100011011011010100110110111 fail ^^ ^^^^ ^^ ^^ SLOT BAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBAABBAAAAAAAAAAAAAABBBBBABBBB LETTER ALPSLFMDEEMCBFRSPKLEMFHRSCJLJKUHPNMBBNNVVRKRHUTDJUKANJHBTPDFSVEVDU SIDE 121212122121212121111111112212122222112222111221112112212112212122 DIRECTION IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIOOOOOOOIOOIOOIOOIOOOOIOOIIIIOOO source: ; set pin BM2 to clear pin BB1 and TAPE BUS 3 OUTPUT source: 1 0 1 changed: 1 0 1 step 117 100001100110100100011011011011011111101110011011011010100110110111 fail ^^ ^^^^ ^^ ^^ SLOT BAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBAABBAAAAAAAAAAAAAABBBBBABBBB LETTER ALPSLFMDEEMCBFRSPKLEMFHRSCJLJKUHPNMBBNNVVRKRHUTDJUKANJHBTPDFSVEVDU SIDE 121212122121212121111111112212122222112222111221112112212112212122 DIRECTION IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIOOOOOOOIOOIOOIOOIOOOOIOOIIIIOOO source: 0 1 0 changed: 0 1 0 step 118 100001100110100100011011011011011101111100011011011010100110110111 fail ^^ ^^^^ ^^ ^^ source: ; no change source: 100000000000000000000000000000000001111100011011011010100110110111 changed: 00 00 0 0 00 00 00 00 000 step 119 100000000000000000000000000000000001111100011011011010100110110111 source: source: ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; source: ; test shifting the RWB source: ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; source: source: ; shift in 0, expect 10 source: 0 changed: 0 step 120 100000000000000000000000000000000001111100011011011010100110100111 source: 110 changed: 1 0 step 121 100000000000000000000000000000000001111100011011011010100110101101 source: 0 changed: 0 step 122 100000000000000000000000000000000001111100011011011010100110100101 source: ; toggle phase should toggle RWB 2 source: 0 0 changed: 0 0 step 123 100000000000000000000000000000000001111100011011011010100110000001 source: 1 1 changed: 1 1 step 124 100000000000000000000000000000000001111100011011011010100110100101 source: source: ; shift in 0, expect 00 source: 0 changed: step 125 100000000000000000000000000000000001111100011011011010100110100101 source: 100 changed: 10 step 126 100000000000000000000000000000000001111100011011011010100110101001 source: 0 changed: 0 step 127 100000000000000000000000000000000001111100011011011010100110100001 source: ; toggle phase should toggle RWB 2 source: 0 1 changed: 0 1 step 128 100000000000000000000000000000000001111100011011011010100110000101 source: 1 0 changed: 1 0 step 129 100000000000000000000000000000000001111100011011011010100110100001 source: source: ; shift in 0, expect 00 source: 0 changed: step 130 100000000000000000000000000000000001111100011011011010100110100001 source: 100 changed: 1 step 131 100000000000000000000000000000000001111100011011011010100110101001 source: 0 changed: 0 step 132 100000000000000000000000000000000001111100011011011010100110100001 source: ; shift in 1, expect 01 source: 1 changed: 1 step 133 100000000000000000000000000000000001111100011011011010100110110001 source: 101 changed: 1 1 step 134 100000000000000000000000000000000001111100011011011010100110111011 source: 0 changed: 0 step 135 100000000000000000000000000000000001111100011011011010100110110011 source: ; shift in 1, expect 11 source: 1 changed: step 136 100000000000000000000000000000000001111100011011011010100110110011 source: 111 changed: 11 step 137 100000000000000000000000000000000001111100011011011010100110111111 source: 0 changed: 0 step 138 100000000000000000000000000000000001111100011011011010100110110111 source: ; shift in 1, expect 11 source: 1 changed: step 139 100000000000000000000000000000000001111100011011011010100110110111 source: 111 changed: 1 step 140 100000000000000000000000000000000001111100011011011010100110111111 source: 0 changed: 0 step 141 100000000000000000000000000000000001111100011011011010100110110111 source: ; shift in 0, expect 10 source: 0 changed: 0 step 142 100000000000000000000000000000000001111100011011011010100110100111 source: 110 changed: 1 0 step 143 100000000000000000000000000000000001111100011011011010100110101101 source: 0 changed: 0 step 144 100000000000000000000000000000000001111100011011011010100110100101 source: ; shift in 1, expect 01 source: 1 changed: 1 step 145 100000000000000000000000000000000001111100011011011010100110110101 source: 101 changed: 101 step 146 100000000000000000000000000000000001111100011011011010100110111011 source: 0 changed: 0 step 147 100000000000000000000000000000000001111100011011011010100110110011 source: ; shift in 0, expect 10 source: 0 changed: 0 step 148 100000000000000000000000000000000001111100011011011010100110100011 source: 110 changed: 110 step 149 100000000000000000000000000000000001111100011011011010100110101101 source: 0 changed: 0 step 150 100000000000000000000000000000000001111100011011011010100110100101 source: ; shift in 1, expect 01 source: 1 changed: 1 step 151 100000000000000000000000000000000001111100011011011010100110110101 source: 101 changed: 101 step 152 100000000000000000000000000000000001111100011011011010100110111011 source: 0 changed: 0 step 153 100000000000000000000000000000000001111100011011011010100110110011 source: ; shift in 1, expect 11 source: 1 changed: step 154 100000000000000000000000000000000001111100011011011010100110110011 source: 111 changed: 11 step 155 100000000000000000000000000000000001111100011011011010100110111111 source: 0 changed: 0 step 156 100000000000000000000000000000000001111100011011011010100110110111 source: ; no change source: 100000000000000000000000000000000001111100011011011010100110110111 changed: step 157 100000000000000000000000000000000001111100011011011010100110110111 test 2: *** FAIL *************************** 71 steps failed SLOT BAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBAABBAAAAAAAAAAAAAABBBBBABBBB LETTER ALPSLFMDEEMCBFRSPKLEMFHRSCJLJKUHPNMBBNNVVRKRHUTDJUKANJHBTPDFSVEVDU SIDE 121212122121212121111111112212122222112222111221112112212112212122 DIRECTION IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIOOOOOOOIOOIOOIOOIOOOOIOOIIIIOOO this fail O O OO O O OO OOOO OO OO all fails O O OO O O OO OOOO OO OO was hi 111111111111111111111111111111111111111111111111111111111111111111 rising ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ ^^^^^^^^^^^^^^^^^^^^^^^^^ falling vvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvv vvvvvvvvvvvvvvvvvvvvvvvvv was lo 00000000000000000000000000000000000000 0000000000000000000000000 total fails 2, total passes 0 space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C toggle comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit source: ; all registers are unknown source: ; turn on C0, PHASE source: ; with no ENABLES, BUS2,BUS3 is 11, C2 is 1 source: 1000000000000000000000000000000000011111000XX0XX0XX0XXXX0XX0110XX1 changed: step 1 100000000000000000000000000000000001111100011011011010100110110111 source: source: ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; source: ; source: ; set all registers LOW source: ; source: ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; source: source: ; load TMA SETUP from tape bus (00) source: 100 changed: 100 step 2 100000000000000000000000000000000001111100100011011010100110110111 source: 0 changed: 0 step 3 100000000000000000000000000000000001111100000011011010100110110111 source: ; load TMA from tape bus (00) source: 100 changed: 100 step 4 100000000000000000000000000000000001111100000100011010100110110111 source: 0 changed: 0 step 5 100000000000000000000000000000000001111100000000011010100110110111 source: ; load TBN from tape bus (00) source: 100 changed: 100 step 6 100000000000000000000000000000000001111100000000100010100110110111 source: 0 changed: 0 step 7 100000000000000000000000000000000001111100000000000010100110110111 source: ; load TAC from tape bus (00) source: 10101 changed: 10101 step 8 100000000000000000000000000000000001111100000000000101010110110111 source: 0 changed: 0 step 9 100000000000000000000000000000000001111100000000000001010110110111 source: ; load TB from tape bus (00) source: 100 changed: 100 step 10 100000000000000000000000000000000001111100000000000001011000110111 source: 0 changed: 0 step 11 100000000000000000000000000000000001111100000000000001010000110111 source: ; load RWB from TB (JAMS CLEAR AND PRESET) source: 1 00 changed: 1 00 step 12 100000000000000000000000000000000001111100000000000001010001110001 source: 0 changed: 0 step 13 100000000000000000000000000000000001111100000000000001010000110001 source: ; (no change) source: 100000000000000000000000000000000001111100000000000001010000110001 changed: step 14 100000000000000000000000000000000001111100000000000001010000110001 source: source: source: ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; source: ; source: ; set all registers HIGH source: ; source: ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; source: source: ; set pin AF1 which clears pin BB2 and sets pin BR2 TAPE BUS 3 OUTPUT source: 1 0 1 changed: 1 0 1 step 15 100000000000010000000000000000000000111101000000000001010000110001 source: ; set pin AP2 which clears pin AN2 and sets pin BV2 TAPE BUS 2 OUTPUT source: 1 0 1 changed: 1 0 1 step 16 100000000000010010000000000000000000110111000000000001010000110001 source: source: source: ; load TMA SETUP from tape bus (11) source: 111 changed: 111 step 17 100000000000010010000000000000000000110111111000000001010000110001 source: 0 changed: 0 step 18 100000000000010010000000000000000000110111011000000001010000110001 source: ; load TMA from tape bus (11) source: 111 changed: 111 step 19 100000000000010010000000000000000000110111011111000001010000110001 source: 0 changed: 0 step 20 100000000000010010000000000000000000110111011011000001010000110001 source: ; load TBN from tape bus (11) source: 111 changed: 111 step 21 100000000000010010000000000000000000110111011011111001010000110001 source: 0 changed: 0 step 22 100000000000010010000000000000000000110111011011011001010000110001 source: ; load TAC from tape bus (11) source: 11010 changed: 11010 step 23 100000000000010010000000000000000000110111011011011110100000110001 source: 0 changed: 0 step 24 100000000000010010000000000000000000110111011011011010100000110001 source: ; load TB from tape bus (11) source: 111 changed: 111 step 25 100000000000010010000000000000000000110111011011011010101110110001 source: 0 changed: 0 step 26 100000000000010010000000000000000000110111011011011010100110110001 source: ; load RWB from TB (JAMS CLEAR AND PRESET) source: 1 11 changed: 1 11 step 27 100000000000010010000000000000000000110111011011011010100111110111 source: 0 changed: 0 step 28 100000000000010010000000000000000000110111011011011010100110110111 source: ; clear pin AF1 (AND with itself) to set pin BB2 (AND-NOR output) and clear pin BR2 TAPE BUS 3 OUTPUT source: 0 1 0 changed: 0 1 0 step 29 100000000000000010000000000000000001110110011011011010100110110111 source: ; clear pin AP2 (AND with itself) to set pin AN2 (AND-NOR output) and clear pin BV2 TAPE BUS 2 OUTPUT source: 0 1 0 changed: 0 1 0 step 30 100000000000000000000000000000000001111100011011011010100110110111 source: ; (no change) source: 100000000000000000000000000000000001111100011011011010100110110111 changed: step 31 100000000000000000000000000000000001111100011011011010100110110111 source: source: ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; source: ; source: ; will all registers high, walk a 0 source: ; source: ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; source: source: source: ; walk a 0, TMA SETUP 2 source: source: source: ; clear pin AP2 which sets pin AN2 and clears pin BV2 TAPE BUS 2 OUTPUT source: 1 0 1 changed: 1 0 1 step 32 100000000000000010000000000000000001110110011011011010100110110111 source: ; set pin AF1 which clears pin BB2 and sets pin BR2 TAPE BUS 3 OUTPUT source: 1 0 1 changed: 1 0 1 step 33 100000000000010010000000000000000000110111011011011010100110110111 SLOT BAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBAABBAAAAAAAAAAAAAABBBBBABBBB LETTER ALPSLFMDEEMCBFRSPKLEMFHRSCJLJKUHPNMBBNNVVRKRHUTDJUKANJHBTPDFSVEVDU SIDE 121212122121212121111111112212122222112222111221112112212112212122 DIRECTION IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIOOOOOOOIOOIOOIOOIOOOOIOOIIIIOOO source: ; load TMA SETUP from tape bus (01) source: 101 changed: 1 step 34 100000000000010010000000000000000000110111111011011010100110110111 fail ^ space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C toggle comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT BAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBAABBAAAAAAAAAAAAAABBBBBABBBB LETTER ALPSLFMDEEMCBFRSPKLEMFHRSCJLJKUHPNMBBNNVVRKRHUTDJUKANJHBTPDFSVEVDU SIDE 121212122121212121111111112212122222112222111221112112212112212122 DIRECTION IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIOOOOOOOIOOIOOIOOIOOOOIOOIIIIOOO all fails O O OO O O OO OOOO OO OO was lo 00000000000000000000000000000000000000 0000000000000000000000000 falling vvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvv vvvvvvvvvvvvvvvvvvvvvvvvv rising ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ ^^^^^^^^^^^^^^^^^^^^^^^^^ was hi 111111111111111111111111111111111111111111111111111111111111111111 total fails 2, total passes 0 Main menu Thu Aug 20 17:53:05 2015 test file is: tests\m222.new delay is: 0 trigger is: 1 1 read test file 2 set test delay 3 set test trigger 4 run test 5 output loading test 8 diags 9 exit Enter test file name? trying to open test file: tests\m222.new reading test file: tests\m222.new comment: M222 PCB REV B SCHEMATIC REV A LINC TAPE REGISTERS comment: comment: TERMINOLOGY- SIGNALS REFER TO PDP12 MAINT VOL4 M222 SCHEMATIC. comment: comment: BUT... comment: comment: DEC USES AND-NOR GATES TO ROUTE THE ADDER A AND B INPUTS, SO... comment: DEC RENAMED THE ADDER TO NEGATIVE LOGIC TERMS (I.E. A-N + B-N + C-N -> SUM-N, C1-N). comment: (NOT THE 7482 DATASHEET NAMES OF A + B + C -> SUM, C1). comment: comment: SO, WITH ALL 'AND ENABLES' LOW, THE AND-NOR OUTPUTS = HIGH. comment: WITH C-L HIGH, THE ADDER OUTPUT IS SUM-N=1, C1-N=1; comment: THE INVERTED ADDER OUTPUT IS LOW (TAPE BUS). comment: AND THERE IS NO CARRY (C1-N IS HI). comment: comment: THE TWO ADDERS, TWO REGISTER BITS, ETC ARE LABELED BIT 2 (EVEN, MSB) AND BIT 3 (ODD, LSB). comment: THE ADDERS ARE REFERRED TO AS 'ADDER2' (MSB) AND 'ADDER3' (LSB). comment: comment: POWER PINS: comment: AA2 +5V comment: AT1 GROUND comment: AC2 GROUND comment: BA2 +5V comment: BT1 GROUND comment: BC2 GROUND comment: comment: (ALL PINS ARE USED). comment: comment: pins: PINS pins: 1 I BA1 CARRY IN-N, (TO E9-5 7482 C0) C-N TO ADDER2 pins: 2 I AL2 AND-NOR ENABLE: TAC TAC3 TO PIN BB2 (TO ADDER3) TAC2 TO PIN AN2 (TO ADDER2) pins: 3 I AP1 AND-NOR ENABLE: TMA SETUP (TMAS)3 TO PIN BB2 (TO ADDER3), (TMAS)3 TO PIN AN2 (TO ADDER2) pins: 4 I AS2 AND-NOR ENABLE: TMA TMA3 TO PIN BB2 (TO ADDER3), TMA2 TO PIN AN2 (TO ADDER2) pins: 5 I AL1 AND-NOR ENABLE: PIN AF2 TO PIN BB2 (TO ADDER3), PIN AM1 TO PIN AN2 (TO ADDER2) pins: 6 I AF2 AND-NOR INPUT (AL1 ENABLES) TO PIN BB2 (TO ADDER3). pins: 7 I AM1 AND-NOR INPUT (AL1 ENABLES) TO PIN AN2 (TO ADDER2) pins: 8 I AD2 AND-NOR ENABLE: RWB RWB3 TO PIN BB2 (TO ADDER3), RWB2 TO PIN AN2 (TO ADDER2) pins: 9 I AE2 AND-NOR ENABLE: PIN AE1 TO PIN BB2 (TO ADDER3), PIN AM2 TO PIN AN2 (TO ADDER2) pins: 10 I AE1 AND-NOR INPUT (AE2 ENABLES) TO PIN BB2 (TO ADDER3). pins: 11 I AM2 AND-NOR INPUT (AE2 ENABLES) TO PIN AN2 (TO ADDER2) pins: 12 I AC1 AND-NOR INPUT, AND WITH PIN AB2 TO PIN BB2 (TO ADDER3) pins: 13 I AB2 AND-NOR INPUT, AND WITH PIN AC1 TO PIN BB2 (TO ADDER3) pins: 14 I AF1 AND-NOR INPUT (AND WITH ITSELF) TO PIN BB2 (TO ADDER3) pins: 15 I AR2 AND-NOR INPUT, AND WITH PIN AS1 TO PIN AN2 (TO ADDER2) pins: 16 I AS1 AND-NOR INPUT, AND WITH PIN AR2 TO PIN AN2 (TO ADDER2) pins: 17 I AP2 AND-NOR INPUT (AND WITH ITSELF) TO PIN AN2 (TO ADDER2) pins: 18 I BK1 AND-NOR ENABLE: TB3 TO PIN BB1 (TO ADDER3), TB2 TO PIN BN1 (TO ADDER2) pins: 19 I BL1 AND-NOR ENABLE: PIN BE1 TO PIN BB1 (TO ADDER3), PIN BM1 TO PIN BN1 (TO ADDER2) pins: 20 I BE1 AND-NOR INPUT (BL1 ENABLES) TO PIN BB1 (TO ADDER3). pins: 21 I BM1 AND-NOR INPUT (BL1 ENABLES) TO PIN BN1 (TO ADDER2) pins: 22 I BF1 AND-NOR ENABLE: PIN BH1 TO PIN BB1 (TO ADDER3), PIN BR1 TO PIN BN1 (TO ADDER2) pins: 23 I BH1 AND-NOR INPUT (BF1 ENABLES): TO PIN BB1 (TO ADDER3), pins: 24 I BR1 AND-NOR INPUT (BF1 ENABLES): TO PIN BN1 (TO ADDER2) pins: 25 I BS1 AND-NOR ENABLE: PIN BC1 TO PIN BB1 (TO ADDER3), PIN BJ2 TO PIN BN1 (TO ADDER2) pins: 26 I BC1 AND-NOR INPUT (BS1 ENABLES): TO PIN BB1 (TO ADDER3), pins: 27 I BJ2 AND-NOR INPUT (BS1 ENABLES): TO PIN BN1 (TO ADDER2) pins: 28 I BL2 AND-NOR ENABLE: PIN BJ1 TO PIN BB1 (TO ADDER3), PIN BK2 TO PIN BN1 (TO ADDER2) pins: 29 I BJ1 AND-NOR INPUT (BL2 ENABLES): TO PIN BB1 (TO ADDER3), pins: 30 I BK2 AND-NOR INPUT (BL2 ENABLES): TO PIN BN1 (TO ADDER2) pins: 31 I BU1 AND-NOR ENABLE: PIN BH2 TO PIN BB1 (TO ADDER3), PIN BP2 TO PIN BN1 (TO ADDER2) pins: 32 I BH2 AND-NOR INPUT (BU1 ENABLES): TO PIN BB1 (TO ADDER3), pins: 33 I BP2 AND-NOR INPUT (BU1 ENABLES): TO PIN BN1 (TO ADDER2) pins: 34 I BN2 AND-NOR INPUT (AND WITH BM2): TO PIN BN1 (TO ADDER2) pins: 35 I BM2 AND-NOR INPUT (AND WITH BM2): TO PIN BN1 (TO ADDER2) pins: 36 O BB2 AND-NOR OUTPUT, (DRIVES E9-2 7482 A1) TO ADDER3 INPUT pins: 37 O BB1 AND-NOR OUTPUT, (DRIVES E9-3 7482 B1) TO ADDER3 INPUT pins: 38 O BN1 AND-NOR OUTPUT, (DRIVES E9-14 7482 A2) TO ADDER2 INPUT pins: 39 O AN2 AND-NOR OUTPUT, (DRIVES E9-13 7482 B2) TO ADDER2 INPUT pins: 40 O AV2 CARRY OUT-N (E9-10 7482 C2) pins: 41 O BV2 TAPE BUS 2 OUTPUT (INVERTED ADDER2 SUM-N (E9-12 7482 SUM2) pins: 42 O BR2 TAPE BUS 3 OUTPUT (INVERTED ADDER3 SUM-N (E9-1 7482 SUM1) pins: 43 I AK1 LOAD TMA SETUP (FROM TAPE BUS) (RISING EDGE CLOCK) pins: 44 O AR1 TMA SETUP 2 pins: 45 O AH1 TMA SETUP 3 pins: 46 I AU2 LOAD TMA (FROM TAPE BUS) (RISING EDGE CLOCK) pins: 47 O AT2 TMA 2 pins: 48 O AD1 TMA 3 pins: 49 I AJ1 LOAD TBN (FROM TAPE BUS) (RISING EDGE CLOCK) pins: 50 O AU1 TBN 2 pins: 51 O AK2 TBN 3 pins: 52 I AA1 LOAD TAC (FROM TAPE BUS) (RISING EDGE CLOCK) pins: 53 O AN1 TAC 2 pins: 54 O AJ2 TAC 2-N pins: 55 O AH2 TAC 3 pins: 56 O AB1 TAC 3-N pins: 57 I BT2 LOAD TB (FROM TAPE BUS) (RISING EDGE CLOCK) pins: 58 O BP1 TB 2 pins: 59 O BD1 TB 3 pins: 60 I BF2 LOAD RWB (FROM TB) (JAMS CLEAR,SET) pins: 61 I BS2 PHASE (SELECTS POLARITY OF RWB OUT, 0 -> INVERTED) pins: 62 I AV1 RWB IN (SHIFTED INTO RWB 3) pins: 63 I BE2 SHIFT RWB (SHIFTS PIN AV1 INTO RWB 3, SHIFTS RWB3 TO RWB2) (RISING CLOCK) pins: 64 O BV1 RWB OUT (IF PHASE=1, =RWB 2; IF PHASE=0; =RWB 2-N) pins: 65 O BD2 RWB 3 pins: 66 O BU2 +3.5V pins: direction: IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIOOOOOOOIOOIOOIOOIOOOOIOOIIIIOOO comment: ; all registers are unknown comment: ; turn on C0, PHASE comment: ; with no ENABLES, BUS2,BUS3 is 11, C2 is 1 test 1: 1000000000000000000000000000000000011111000XX0XX0XX0XXXX0XX0110XX1 comment: comment: ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; comment: ; comment: ; set all registers LOW comment: ; comment: ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; comment: comment: ; load TMA SETUP from tape bus (00) test 2: 100 test 3: 0 comment: ; load TMA from tape bus (00) test 4: 100 test 5: 0 comment: ; load TBN from tape bus (00) test 6: 100 test 7: 0 comment: ; load TAC from tape bus (00) test 8: 10101 test 9: 0 comment: ; load TB from tape bus (00) test 10: 100 test 11: 0 comment: ; load RWB from TB (JAMS CLEAR AND PRESET) test 12: 1 00 test 13: 0 comment: ; (no change) test 14: 100000000000000000000000000000000001111100000000000001010000110001 comment: comment: comment: ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; comment: ; comment: ; set all registers HIGH comment: ; comment: ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; comment: comment: ; set pin AF1 which clears pin BB2 and sets pin BR2 TAPE BUS 3 OUTPUT test 15: 1 0 1 comment: ; set pin AP2 which clears pin AN2 and sets pin BV2 TAPE BUS 2 OUTPUT test 16: 1 0 1 comment: comment: comment: ; load TMA SETUP from tape bus (11) test 17: 111 test 18: 0 comment: ; load TMA from tape bus (11) test 19: 111 test 20: 0 comment: ; load TBN from tape bus (11) test 21: 111 test 22: 0 comment: ; load TAC from tape bus (11) test 23: 11010 test 24: 0 comment: ; load TB from tape bus (11) test 25: 111 test 26: 0 comment: ; load RWB from TB (JAMS CLEAR AND PRESET) test 27: 1 11 test 28: 0 comment: ; clear pin AF1 (AND with itself) to set pin BB2 (AND-NOR output) and clear pin BR2 TAPE BUS 3 OUTPUT test 29: 0 1 0 comment: ; clear pin AP2 (AND with itself) to set pin AN2 (AND-NOR output) and clear pin BV2 TAPE BUS 2 OUTPUT test 30: 0 1 0 comment: ; (no change) test 31: 100000000000000000000000000000000001111100011011011010100110110111 comment: comment: ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; comment: ; comment: ; will all registers high, walk a 0 comment: ; comment: ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; comment: comment: comment: ; walk a 0, TMA SETUP 2 comment: comment: comment: ; clear pin AP2 which sets pin AN2 and clears pin BV2 TAPE BUS 2 OUTPUT test 32: 0 1 0 comment: ; set pin AF1 which clears pin BB2 and sets pin BR2 TAPE BUS 3 OUTPUT test 33: 1 0 1 comment: ; load TMA SETUP from tape bus (01) test 34: 101 test 35: 0 comment: ; restore TMA SETUP 2 comment: ; set pin AP2 which clears pin AN2 and sets pin BV2 TAPE BUS 2 OUTPUT test 36: 1 0 1 comment: ; load TMA SETUP from tape bus (11) test 37: 111 test 38: 0 comment: comment: comment: ; walk a 0, TMA SETUP 3 comment: comment: comment: ; set pin AP2 which clears pin AN2 and sets pin BV2 TAPE BUS 2 OUTPUT test 39: 1 0 1 comment: ; clear pin AF1 which sets pin BB2 and clears pin BR2 TAPE BUS 3 OUTPUT test 40: 0 0 1 comment: ; load TMA SETUP from tape bus (10) test 41: 110 test 42: 0 comment: ; restore TMA SETUP 3 comment: ; set pin AF1 which clears pin BB2 and sets pin BR2 TAPE BUS 3 OUTPUT test 43: 1 0 1 comment: ; load TMA SETUP from tape bus (11) test 44: 111 test 45: 0 comment: comment: comment: ; walk a 0, TMA 2 comment: comment: comment: ; clear pin AP2 which sets pin AN2 and clears pin BV2 TAPE BUS 2 OUTPUT test 46: 0 1 0 comment: ; set pin AF1 which clears pin BB2 and sets pin BR2 TAPE BUS 3 OUTPUT test 47: 1 0 1 comment: ; load TMA from tape bus (01) test 48: 101 test 49: 0 comment: ; restore TMA 2 comment: ; set pin AP2 which clears pin AN2 and sets pin BV2 TAPE BUS 2 OUTPUT test 50: 1 0 1 comment: ; load TMA from tape bus (11) test 51: 111 test 52: 0 comment: comment: comment: ; walk a 0, TMA 3 comment: comment: comment: ; set pin AP2 which clears pin AN2 and sets pin BV2 TAPE BUS 2 OUTPUT test 53: 1 0 1 comment: ; clear pin AF1 which sets pin BB2 and clears pin BR2 TAPE BUS 3 OUTPUT test 54: 0 0 1 comment: ; load TMA from tape bus (10) test 55: 110 test 56: 0 comment: ; restore TMA 3 comment: ; set pin AF1 which clears pin BB2 and sets pin BR2 TAPE BUS 3 OUTPUT test 57: 1 0 1 comment: ; load TMA from tape bus (11) test 58: 111 test 59: 0 comment: comment: comment: comment: comment: comment: comment: comment: comment: comment: comment: comment: ; load TBN from tape bus (00) test 60: 100 test 61: 0 comment: ; load TAC from tape bus (00) test 62: 10101 test 63: 0 comment: ; load TB from tape bus (00) test 64: 100 test 65: 0 comment: ; load RWB from TB (JAMS CLEAR AND PRESET) test 66: 1 00 test 67: 0 comment: comment: comment: comment: comment: comment: comment: comment: comment: comment: comment: comment: comment: comment: comment: ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; comment: ; comment: ; test AND-NOR logic comment: ; comment: ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; comment: comment: ; (all registers are HIGH) comment: ; set all pins HIGH except ENABLES comment: comment: ; set pin AF2 HIGH test 68: 1 comment: ; set pin AM1 HIGH test 69: 1 comment: ; set pin AE1 HIGH test 70: 1 comment: ; set pin AM2 HIGH test 71: 1 comment: ; set pin AB2 HIGH test 72: 1 comment: ; set pin AS1 HIGH test 73: 1 comment: ; set pin BE1 HIGH test 74: 1 comment: ; set pin BM1 HIGH test 75: 1 comment: ; set pin BH1 HIGH test 76: 1 comment: ; set pin BR1 HIGH test 77: 1 comment: ; set pin BC1 HIGH test 78: 1 comment: ; set pin BJ2 HIGH test 79: 1 comment: ; set pin BJ1 HIGH test 80: 1 comment: ; set pin BK2 HIGH test 81: 1 comment: ; set pin BH2 HIGH test 82: 1 comment: ; set pin BP2 HIGH test 83: 1 comment: ; set pin BN2 HIGH test 84: 1 comment: ; toggle each ENABLE comment: comment: ; set pin AL2 to clear pin BB2 and pin AN2 AND-NOR OUTPUTS and set TAPE BUS 2 OUTPUT and TAPE BUS 3 OUTPUT test 85: 1 0 0 11 test 86: 0 1 1 00 comment: ; set pin AP1 to clear pin BB2 and pin AN2 AND-NOR OUTPUTS and set TAPE BUS 2 OUTPUT and TAPE BUS 3 OUTPUT test 87: 1 0 0 11 test 88: 0 1 1 00 comment: ; set pin AS2 to clear pin BB2 and pin AN2 AND-NOR OUTPUTS and set TAPE BUS 2 OUTPUT and TAPE BUS 3 OUTPUT test 89: 1 0 0 11 test 90: 0 1 1 00 comment: ; set pin AL1 to clear pin BB2 and pin AN2 AND-NOR OUTPUTS and set TAPE BUS 2 OUTPUT and TAPE BUS 3 OUTPUT test 91: 1 0 0 11 test 92: 0 1 1 00 comment: ; set pin AL1 to clear pin BB2 and pin AN2 AND-NOR OUTPUTS and set TAPE BUS 2 OUTPUT and TAPE BUS 3 OUTPUT test 93: 1 0 0 11 test 94: 0 1 1 00 comment: ; set pin AE2 to clear pin BB2 and pin AN2 AND-NOR OUTPUTS and set TAPE BUS 2 OUTPUT and TAPE BUS 3 OUTPUT test 95: 1 0 0 11 test 96: 0 1 1 00 comment: ; set pin AC1 to clear pin BB2 and set TAPE BUS 3 OUTPUT test 97: 1 0 1 test 98: 0 1 0 comment: ; set pin AF1 to clear pin BB2 and set TAPE BUS 3 OUTPUT test 99: 1 0 1 test 100: 0 1 0 comment: ; set pin AR2 to clear pin AN2 AND-NOR OUTPUTS and set TAPE BUS 2 OUTPUT test 101: 1 0 1 test 102: 0 1 0 comment: ; set pin AP2 to clear pin AN2 AND-NOR OUTPUTS and set TAPE BUS 2 OUTPUT test 103: 1 0 1 test 104: 0 1 0 comment: comment: ; set pin BK1 to clear pin BB1 and pin BN1 AND-NOR OUTPUTS and set TAPE BUS 2 OUTPUT and TAPE BUS 3 OUTPUT test 105: 1 00 11 test 106: 0 11 00 comment: ; set pin BL1 to clear pin BB1 and pin BN1 AND-NOR OUTPUTS and set TAPE BUS 2 OUTPUT and TAPE BUS 3 OUTPUT test 107: 1 00 11 test 108: 0 11 00 comment: ; set pin BF1 to clear pin BB1 and pin BN1 AND-NOR OUTPUTS and set TAPE BUS 2 OUTPUT and TAPE BUS 3 OUTPUT test 109: 1 00 11 test 110: 0 11 00 comment: ; set pin BS1 to clear pin BB1 and pin BN1 AND-NOR OUTPUTS and set TAPE BUS 2 OUTPUT and TAPE BUS 3 OUTPUT test 111: 1 00 11 test 112: 0 11 00 comment: ; set pin BL2 to clear pin BB1 and pin BN1 AND-NOR OUTPUTS and set TAPE BUS 2 OUTPUT and TAPE BUS 3 OUTPUT test 113: 1 00 11 test 114: 0 11 00 comment: ; set pin BU1 to clear pin BB1 and pin BN1 AND-NOR OUTPUTS and set TAPE BUS 2 OUTPUT and TAPE BUS 3 OUTPUT test 115: 1 00 11 test 116: 0 11 00 comment: ; set pin BM2 to clear pin BB1 and TAPE BUS 3 OUTPUT test 117: 1 0 1 test 118: 0 1 0 comment: ; no change test 119: 100000000000000000000000000000000001111100011011011010100110110111 comment: comment: ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; comment: ; test shifting the RWB comment: ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; comment: comment: ; shift in 0, expect 10 test 120: 0 test 121: 110 test 122: 0 comment: ; toggle phase should toggle RWB 2 test 123: 0 0 test 124: 1 1 comment: comment: ; shift in 0, expect 00 test 125: 0 test 126: 100 test 127: 0 comment: ; toggle phase should toggle RWB 2 test 128: 0 1 test 129: 1 0 comment: comment: ; shift in 0, expect 00 test 130: 0 test 131: 100 test 132: 0 comment: ; shift in 1, expect 01 test 133: 1 test 134: 101 test 135: 0 comment: ; shift in 1, expect 11 test 136: 1 test 137: 111 test 138: 0 comment: ; shift in 1, expect 11 test 139: 1 test 140: 111 test 141: 0 comment: ; shift in 0, expect 10 test 142: 0 test 143: 110 test 144: 0 comment: ; shift in 1, expect 01 test 145: 1 test 146: 101 test 147: 0 comment: ; shift in 0, expect 10 test 148: 0 test 149: 110 test 150: 0 comment: ; shift in 1, expect 01 test 151: 1 test 152: 101 test 153: 0 comment: ; shift in 1, expect 11 test 154: 1 test 155: 111 test 156: 0 comment: ; no change test 157: 100000000000000000000000000000000001111100011011011010100110110111 comment: comment: ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; comment: ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; comment: ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; comment: ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; comment: ; needs work (more adder tests, more register tests) comment: ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; comment: ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; comment: ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; comment: ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; end: END summary column 1: offset 2, mask 0x2000 column 2: offset 1, mask 0x0002 column 3: offset 1, mask 0x0800 column 4: offset 1, mask 0x0040 column 5: offset 1, mask 0x4000 column 6: offset 0, mask 0x0004 column 7: offset 1, mask 0x2000 column 8: offset 0, mask 0x0010 column 9: offset 0, mask 0x0008 column 10: offset 0, mask 0x0800 column 11: offset 1, mask 0x0004 column 12: offset 0, mask 0x2000 column 13: offset 0, mask 0x0040 column 14: offset 0, mask 0x0400 column 15: offset 1, mask 0x0020 column 16: offset 1, mask 0x0200 column 17: offset 1, mask 0x0010 column 18: offset 3, mask 0x2000 column 19: offset 3, mask 0x1000 column 20: offset 2, mask 0x0200 column 21: offset 3, mask 0x0800 column 22: offset 2, mask 0x0100 column 23: offset 3, mask 0x8000 column 24: offset 3, mask 0x0100 column 25: offset 4, mask 0x8000 column 26: offset 2, mask 0x0800 column 27: offset 3, mask 0x0002 column 28: offset 3, mask 0x0008 column 29: offset 3, mask 0x4000 column 30: offset 3, mask 0x0004 column 31: offset 4, mask 0x2000 column 32: offset 3, mask 0x0001 column 33: offset 3, mask 0x0040 column 34: offset 3, mask 0x0020 column 35: offset 3, mask 0x0010 column 36: offset 2, mask 0x0008 column 37: offset 2, mask 0x1000 column 38: offset 3, mask 0x0400 column 39: offset 1, mask 0x0008 column 40: offset 2, mask 0x0002 column 41: offset 4, mask 0x0008 column 42: offset 3, mask 0x0080 column 43: offset 1, mask 0x8000 column 44: offset 1, mask 0x0400 column 45: offset 0, mask 0x0200 column 46: offset 2, mask 0x0001 column 47: offset 1, mask 0x0080 column 48: offset 0, mask 0x1000 column 49: offset 0, mask 0x0100 column 50: offset 2, mask 0x8000 column 51: offset 1, mask 0x0001 column 52: offset 0, mask 0x8000 column 53: offset 1, mask 0x1000 column 54: offset 0, mask 0x0001 column 55: offset 0, mask 0x0002 column 56: offset 0, mask 0x4000 column 57: offset 4, mask 0x0002 column 58: offset 3, mask 0x0200 column 59: offset 2, mask 0x0400 column 60: offset 2, mask 0x0080 column 61: offset 4, mask 0x0001 column 62: offset 2, mask 0x4000 column 63: offset 2, mask 0x0040 column 64: offset 4, mask 0x1000 column 65: offset 2, mask 0x0020 column 66: offset 4, mask 0x0004 direction bits (1=input) 0x52A3 0x1589 0x943A 0x0680 0x50FC pullup bits (1=pullup) 0x0000 0x0000 0x0000 0x0000 0x0000 test step out_data dont care 1: 0x0000 0x0008 0x700A 0x0400 0x0005 0x5203 0x1481 0x8420 0x0200 0x1000 2: 0x0000 0x8008 0x700A 0x0400 0x0005 0x5003 0x1081 0x8420 0x0200 0x1000 3: 0x0000 0x0008 0x700A 0x0400 0x0005 0x5003 0x1081 0x8420 0x0200 0x1000 4: 0x0000 0x0008 0x700B 0x0400 0x0005 0x4003 0x1001 0x8420 0x0200 0x1000 5: 0x0000 0x0008 0x700A 0x0400 0x0005 0x4003 0x1001 0x8420 0x0200 0x1000 6: 0x0100 0x0008 0x700A 0x0400 0x0005 0x4003 0x1000 0x0420 0x0200 0x1000 7: 0x0000 0x0008 0x700A 0x0400 0x0005 0x4003 0x1000 0x0420 0x0200 0x1000 8: 0xC001 0x0008 0x700A 0x0400 0x0005 0x0000 0x0000 0x0420 0x0200 0x1000 9: 0x4001 0x0008 0x700A 0x0400 0x0005 0x0000 0x0000 0x0420 0x0200 0x1000 10: 0x4001 0x0008 0x700A 0x0400 0x0007 0x0000 0x0000 0x0020 0x0000 0x1000 11: 0x4001 0x0008 0x700A 0x0400 0x0005 0x0000 0x0000 0x0020 0x0000 0x1000 12: 0x4001 0x0008 0x708A 0x0400 0x0005 13: 0x4001 0x0008 0x700A 0x0400 0x0005 14: 0x4001 0x0008 0x700A 0x0400 0x0005 15: 0x4401 0x0008 0x7002 0x0480 0x0005 16: 0x4401 0x0010 0x7002 0x0480 0x000D 17: 0x4601 0x8410 0x7002 0x0480 0x000D 18: 0x4601 0x0410 0x7002 0x0480 0x000D 19: 0x5601 0x0490 0x7003 0x0480 0x000D 20: 0x5601 0x0490 0x7002 0x0480 0x000D 21: 0x5701 0x0491 0xF002 0x0480 0x000D 22: 0x5601 0x0491 0xF002 0x0480 0x000D 23: 0x9602 0x1491 0xF002 0x0480 0x000D 24: 0x1602 0x1491 0xF002 0x0480 0x000D 25: 0x1602 0x1491 0xF402 0x0680 0x000F 26: 0x1602 0x1491 0xF402 0x0680 0x000D 27: 0x1602 0x1491 0xF4A2 0x0680 0x100D 28: 0x1602 0x1491 0xF422 0x0680 0x100D 29: 0x1202 0x1491 0xF42A 0x0600 0x100D 30: 0x1202 0x1489 0xF42A 0x0600 0x1005 31: 0x1202 0x1489 0xF42A 0x0600 0x1005 32: 0x1202 0x1489 0xF42A 0x0600 0x1005 33: 0x1602 0x1489 0xF422 0x0680 0x1005 34: 0x1602 0x9089 0xF422 0x0680 0x1005 35: 0x1602 0x1089 0xF422 0x0680 0x1005 36: 0x1602 0x1091 0xF422 0x0680 0x100D 37: 0x1602 0x9491 0xF422 0x0680 0x100D 38: 0x1602 0x1491 0xF422 0x0680 0x100D 39: 0x1602 0x1491 0xF422 0x0680 0x100D 40: 0x1202 0x1491 0xF422 0x0680 0x100D 41: 0x1002 0x9491 0xF422 0x0680 0x100D 42: 0x1002 0x1491 0xF422 0x0680 0x100D 43: 0x1402 0x1491 0xF422 0x0680 0x100D 44: 0x1602 0x9491 0xF422 0x0680 0x100D 45: 0x1602 0x1491 0xF422 0x0680 0x100D 46: 0x1602 0x1489 0xF422 0x0680 0x1005 47: 0x1602 0x1489 0xF422 0x0680 0x1005 48: 0x1602 0x1409 0xF423 0x0680 0x1005 49: 0x1602 0x1409 0xF422 0x0680 0x1005 50: 0x1602 0x1411 0xF422 0x0680 0x100D 51: 0x1602 0x1491 0xF423 0x0680 0x100D 52: 0x1602 0x1491 0xF422 0x0680 0x100D 53: 0x1602 0x1491 0xF422 0x0680 0x100D 54: 0x1202 0x1491 0xF422 0x0680 0x100D 55: 0x0202 0x1491 0xF423 0x0680 0x100D 56: 0x0202 0x1491 0xF422 0x0680 0x100D 57: 0x0602 0x1491 0xF422 0x0680 0x100D 58: 0x1602 0x1491 0xF423 0x0680 0x100D 59: 0x1602 0x1491 0xF422 0x0680 0x100D 60: 0x1702 0x1490 0x7422 0x0680 0x100D 61: 0x1602 0x1490 0x7422 0x0680 0x100D 62: 0xD601 0x0490 0x7422 0x0680 0x100D 63: 0x5601 0x0490 0x7422 0x0680 0x100D 64: 0x5601 0x0490 0x7022 0x0480 0x100F 65: 0x5601 0x0490 0x7022 0x0480 0x100D 66: 0x5601 0x0490 0x7082 0x0480 0x000D 67: 0x5601 0x0490 0x7002 0x0480 0x000D 68: 0x5605 0x0490 0x7002 0x0480 0x000D 69: 0x5605 0x2490 0x7002 0x0480 0x000D 70: 0x5E05 0x2490 0x7002 0x0480 0x000D 71: 0x5E05 0x2494 0x7002 0x0480 0x000D 72: 0x5E45 0x2494 0x7002 0x0480 0x000D 73: 0x5E45 0x2694 0x7002 0x0480 0x000D 74: 0x5E45 0x2694 0x7202 0x0480 0x000D 75: 0x5E45 0x2694 0x7202 0x0C80 0x000D 76: 0x5E45 0x2694 0x7202 0x8C80 0x000D 77: 0x5E45 0x2694 0x7202 0x8D80 0x000D 78: 0x5E45 0x2694 0x7A02 0x8D80 0x000D 79: 0x5E45 0x2694 0x7A02 0x8D82 0x000D 80: 0x5E45 0x2694 0x7A02 0xCD82 0x000D 81: 0x5E45 0x2694 0x7A02 0xCD86 0x000D 82: 0x5E45 0x2694 0x7A02 0xCD87 0x000D 83: 0x5E45 0x2694 0x7A02 0xCDC7 0x000D 84: 0x5E45 0x2694 0x7A02 0xCDE7 0x000D 85: 0x5E45 0x2696 0x7A02 0xCDE7 0x000D 86: 0x5E45 0x269C 0x7A0A 0xCD67 0x0005 87: 0x5E45 0x2E94 0x7A02 0xCDE7 0x000D 88: 0x5E45 0x269C 0x7A0A 0xCD67 0x0005 89: 0x5E45 0x26D4 0x7A02 0xCDE7 0x000D 90: 0x5E45 0x269C 0x7A0A 0xCD67 0x0005 91: 0x5E45 0x6694 0x7A02 0xCDE7 0x000D 92: 0x5E45 0x269C 0x7A0A 0xCD67 0x0005 93: 0x5E55 0x2694 0x7A02 0xCDE7 0x000D 94: 0x5E45 0x269C 0x7A0A 0xCD67 0x0005 95: 0x5E4D 0x2694 0x7A02 0xCDE7 0x000D 96: 0x5E45 0x269C 0x7A0A 0xCD67 0x0005 97: 0x7E45 0x269C 0x7A02 0xCDE7 0x0005 98: 0x5E45 0x269C 0x7A0A 0xCD67 0x0005 99: 0x5E45 0x269C 0x7A02 0xCDE7 0x0005 100: 0x5A45 0x269C 0x7A0A 0xCD67 0x0005 101: 0x5A45 0x26B4 0x7A0A 0xCD67 0x000D 102: 0x5A45 0x269C 0x7A0A 0xCD67 0x0005 103: 0x5A45 0x2694 0x7A0A 0xCD67 0x000D 104: 0x5A45 0x268C 0x7A0A 0xCD67 0x0005 105: 0x5A45 0x268C 0x6A0A 0xE9E7 0x000D 106: 0x5A45 0x268C 0x7A0A 0xCD67 0x0005 107: 0x5A45 0x268C 0x6A0A 0xD9E7 0x000D 108: 0x5A45 0x268C 0x7A0A 0xCD67 0x0005 109: 0x5A45 0x268C 0x6B0A 0xC9E7 0x000D 110: 0x5A45 0x268C 0x7A0A 0xCD67 0x0005 111: 0x5A45 0x268C 0x6A0A 0xC9E7 0x800D 112: 0x5A45 0x268C 0x7A0A 0xCD67 0x0005 113: 0x5A45 0x268C 0x6A0A 0xC9EF 0x000D 114: 0x5A45 0x268C 0x7A0A 0xCD67 0x0005 115: 0x5A45 0x268C 0x6A0A 0xC9E7 0x200D 116: 0x5A45 0x268C 0x7A0A 0xCD67 0x0005 117: 0x5A45 0x268C 0x7A0A 0xC977 0x000D 118: 0x5A45 0x268C 0x7A0A 0xCD67 0x0005 119: 0x1202 0x1489 0xF42A 0x0600 0x1005 120: 0x1202 0x1489 0xB42A 0x0600 0x1005 121: 0x1202 0x1489 0xB44A 0x0600 0x1005 122: 0x1202 0x1489 0xB40A 0x0600 0x1005 123: 0x1202 0x1489 0xB40A 0x0600 0x0004 124: 0x1202 0x1489 0xB40A 0x0600 0x1005 125: 0x1202 0x1489 0xB40A 0x0600 0x1005 126: 0x1202 0x1489 0xB44A 0x0600 0x0005 127: 0x1202 0x1489 0xB40A 0x0600 0x0005 128: 0x1202 0x1489 0xB40A 0x0600 0x1004 129: 0x1202 0x1489 0xB40A 0x0600 0x0005 130: 0x1202 0x1489 0xB40A 0x0600 0x0005 131: 0x1202 0x1489 0xB44A 0x0600 0x0005 132: 0x1202 0x1489 0xB40A 0x0600 0x0005 133: 0x1202 0x1489 0xF40A 0x0600 0x0005 134: 0x1202 0x1489 0xF46A 0x0600 0x0005 135: 0x1202 0x1489 0xF42A 0x0600 0x0005 136: 0x1202 0x1489 0xF42A 0x0600 0x0005 137: 0x1202 0x1489 0xF46A 0x0600 0x1005 138: 0x1202 0x1489 0xF42A 0x0600 0x1005 139: 0x1202 0x1489 0xF42A 0x0600 0x1005 140: 0x1202 0x1489 0xF46A 0x0600 0x1005 141: 0x1202 0x1489 0xF42A 0x0600 0x1005 142: 0x1202 0x1489 0xB42A 0x0600 0x1005 143: 0x1202 0x1489 0xB44A 0x0600 0x1005 144: 0x1202 0x1489 0xB40A 0x0600 0x1005 145: 0x1202 0x1489 0xF40A 0x0600 0x1005 146: 0x1202 0x1489 0xF46A 0x0600 0x0005 147: 0x1202 0x1489 0xF42A 0x0600 0x0005 148: 0x1202 0x1489 0xB42A 0x0600 0x0005 149: 0x1202 0x1489 0xB44A 0x0600 0x1005 150: 0x1202 0x1489 0xB40A 0x0600 0x1005 151: 0x1202 0x1489 0xF40A 0x0600 0x1005 152: 0x1202 0x1489 0xF46A 0x0600 0x0005 153: 0x1202 0x1489 0xF42A 0x0600 0x0005 154: 0x1202 0x1489 0xF42A 0x0600 0x0005 155: 0x1202 0x1489 0xF46A 0x0600 0x1005 156: 0x1202 0x1489 0xF42A 0x0600 0x1005 157: 0x1202 0x1489 0xF42A 0x0600 0x1005 PINs used (in edge connector order) (G=ground,P=power) SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBB LETTER ABCDEFHJKLMNPRSTUVABCDEFHJKLMNPRSTUVABCDEFHJKLMNPRSTUVABCDEFHJKLMNPRSTUV SIDE 111111111111111111222222222222222222111111111111111111222222222222222222 USAGE IOIOIIOIIIIOIOIGOIPIGIIIOOOIIOIIIOIOIOIOIIIIIIIOOIIGIOPOGOIIIIIIIIIOIIOO UUT has 44 inputs UUT has 22 outputs contains 66 pins/columns 0 pins are not used contains 157 'test steps' M222 PCB REV B SCHEMATIC REV A LINC TAPE REGISTERS TERMINOLOGY- SIGNALS REFER TO PDP12 MAINT VOL4 M222 SCHEMATIC. BUT... DEC USES AND-NOR GATES TO ROUTE THE ADDER A AND B INPUTS, SO... DEC RENAMED THE ADDER TO NEGATIVE LOGIC TERMS (I.E. A-N + B-N + C-N -> SUM-N, C1-N). (NOT THE 7482 DATASHEET NAMES OF A + B + C -> SUM, C1). SO, WITH ALL 'AND ENABLES' LOW, THE AND-NOR OUTPUTS = HIGH. WITH C-L HIGH, THE ADDER OUTPUT IS SUM-N=1, C1-N=1; THE INVERTED ADDER OUTPUT IS LOW (TAPE BUS). AND THERE IS NO CARRY (C1-N IS HI). THE TWO ADDERS, TWO REGISTER BITS, ETC ARE LABELED BIT 2 (EVEN, MSB) AND BIT 3 (ODD, LSB). THE ADDERS ARE REFERRED TO AS 'ADDER2' (MSB) AND 'ADDER3' (LSB). POWER PINS: AA2 +5V AT1 GROUND AC2 GROUND BA2 +5V BT1 GROUND BC2 GROUND (ALL PINS ARE USED). PINS Main menu Thu Aug 20 17:54:42 2015 test file is: tests\m222.new delay is: 0 trigger is: 1 1 read test file 2 set test delay 3 set test trigger 4 run test 5 output loading test 8 diags 9 exit UUT power is okay Thu Aug 20 17:54:44 2015 space single step O run once (one test, all steps) F run, stop on fail G go (run tests N run, stop on fail, no print S scope (run, no print) C toggle comment printout + increase speed (less delay) - decrease speed (more delay)(slower) Q quit test step 1 100000000000000000000000000000000001111100011010010010010100110101 step 2 100000000000000000000000000000000001111100100010010010010100110101 step 3 100000000000000000000000000000000001111100000010010010010100110101 step 4 100000000000000000000000000000000001111100000100010010010100110101 step 5 100000000000000000000000000000000001111100000000010010010100110101 step 6 100000000000000000000000000000000001111100000000100010010100110101 step 7 100000000000000000000000000000000001111100000000000010010100110101 step 8 100000000000000000000000000000000001111100000000000101010100110101 step 9 100000000000000000000000000000000001111100000000000001010100110101 step 10 100000000000000000000000000000000001111100000000000001011000110101 step 11 100000000000000000000000000000000001111100000000000001010000110101 step 12 100000000000000000000000000000000001111100000000000001010001110001 step 13 100000000000000000000000000000000001111100000000000001010000110001 step 14 100000000000000000000000000000000001111100000000000001010000110001 step 15 100000000000010000000000000000000000111101000000000001010000110001 step 16 100000000000010010000000000000000000110111000000000001010000110001 step 17 100000000000010010000000000000000000110111111000000001010000110001 step 18 100000000000010010000000000000000000110111011000000001010000110001 step 19 100000000000010010000000000000000000110111011111000001010000110001 step 20 100000000000010010000000000000000000110111011011000001010000110001 step 21 100000000000010010000000000000000000110111011011111001010000110001 step 22 100000000000010010000000000000000000110111011011011001010000110001 step 23 100000000000010010000000000000000000110111011011011110100000110001 step 24 100000000000010010000000000000000000110111011011011010100000110001 step 25 100000000000010010000000000000000000110111011011011010101110110001 step 26 100000000000010010000000000000000000110111011011011010100110110001 step 27 100000000000010010000000000000000000110111011011011010100111110111 step 28 100000000000010010000000000000000000110111011011011010100110110111 step 29 100000000000000010000000000000000001110110011011011010100110110111 step 30 100000000000000000000000000000000001111100011011011010100110110111 step 31 100000000000000000000000000000000001111100011011011010100110110111 step 32 100000000000000000000000000000000001111100011011011010100110110111 step 33 100000000000010000000000000000000000111101011011011010100110110111 step 34 100000000000010000000000000000000000111101101011011010100110110111 step 35 100000000000010000000000000000000000111101001011011010100110110111 step 36 100000000000010010000000000000000000110111001011011010100110110111 step 37 100000000000010010000000000000000000110111111011011010100110110111 step 38 100000000000010010000000000000000000110111011011011010100110110111 step 39 100000000000010010000000000000000000110111011011011010100110110111 SLOT BAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBAABBAAAAAAAAAAAAAABBBBBABBBB LETTER ALPSLFMDEEMCBFRSPKLEMFHRSCJLJKUHPNMBBNNVVRKRHUTDJUKANJHBTPDFSVEVDU SIDE 121212122121212121111111112212122222112222111221112112212112212122 DIRECTION IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIOOOOOOOIOOIOOIOOIOOOOIOOIIIIOOO changed: 0 1 0 step 40 100000000000000010000000000000000001110110011011011010100110110111 fail ^ ^ SLOT BAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBAABBAAAAAAAAAAAAAABBBBBABBBB LETTER ALPSLFMDEEMCBFRSPKLEMFHRSCJLJKUHPNMBBNNVVRKRHUTDJUKANJHBTPDFSVEVDU SIDE 121212122121212121111111112212122222112222111221112112212112212122 DIRECTION IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIOOOOOOOIOOIOOIOOIOOOOIOOIIIIOOO changed: 1 0 step 41 100000000000000010000000000000000001110110110011011010100110110111 fail ^ ^ SLOT BAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBAABBAAAAAAAAAAAAAABBBBBABBBB LETTER ALPSLFMDEEMCBFRSPKLEMFHRSCJLJKUHPNMBBNNVVRKRHUTDJUKANJHBTPDFSVEVDU SIDE 121212122121212121111111112212122222112222111221112112212112212122 DIRECTION IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIOOOOOOOIOOIOOIOOIOOOOIOOIIIIOOO changed: 0 step 42 100000000000000010000000000000000001110110010011011010100110110111 fail ^ ^ step 43 100000000000010010000000000000000000110111010011011010100110110111 step 44 100000000000010010000000000000000000110111111011011010100110110111 step 45 100000000000010010000000000000000000110111011011011010100110110111 step 46 100000000000010000000000000000000000111101011011011010100110110111 step 47 100000000000010000000000000000000000111101011011011010100110110111 step 48 100000000000010000000000000000000000111101011101011010100110110111 step 49 100000000000010000000000000000000000111101011001011010100110110111 step 50 100000000000010010000000000000000000110111011001011010100110110111 step 51 100000000000010010000000000000000000110111011111011010100110110111 step 52 100000000000010010000000000000000000110111011011011010100110110111 step 53 100000000000010010000000000000000000110111011011011010100110110111 SLOT BAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBAABBAAAAAAAAAAAAAABBBBBABBBB LETTER ALPSLFMDEEMCBFRSPKLEMFHRSCJLJKUHPNMBBNNVVRKRHUTDJUKANJHBTPDFSVEVDU SIDE 121212122121212121111111112212122222112222111221112112212112212122 DIRECTION IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIOOOOOOOIOOIOOIOOIOOOOIOOIIIIOOO changed: 0 1 0 step 54 100000000000000010000000000000000001110110011011011010100110110111 fail ^ ^ SLOT BAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBAABBAAAAAAAAAAAAAABBBBBABBBB LETTER ALPSLFMDEEMCBFRSPKLEMFHRSCJLJKUHPNMBBNNVVRKRHUTDJUKANJHBTPDFSVEVDU SIDE 121212122121212121111111112212122222112222111221112112212112212122 DIRECTION IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIOOOOOOOIOOIOOIOOIOOOOIOOIIIIOOO changed: 1 0 step 55 100000000000000010000000000000000001110110011110011010100110110111 fail ^ ^ SLOT BAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBAABBAAAAAAAAAAAAAABBBBBABBBB LETTER ALPSLFMDEEMCBFRSPKLEMFHRSCJLJKUHPNMBBNNVVRKRHUTDJUKANJHBTPDFSVEVDU SIDE 121212122121212121111111112212122222112222111221112112212112212122 DIRECTION IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIOOOOOOOIOOIOOIOOIOOOOIOOIIIIOOO changed: 0 step 56 100000000000000010000000000000000001110110011010011010100110110111 fail ^ ^ step 57 100000000000010010000000000000000000110111011010011010100110110111 step 58 100000000000010010000000000000000000110111011111011010100110110111 step 59 100000000000010010000000000000000000110111011011011010100110110111 SLOT BAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBAABBAAAAAAAAAAAAAABBBBBABBBB LETTER ALPSLFMDEEMCBFRSPKLEMFHRSCJLJKUHPNMBBNNVVRKRHUTDJUKANJHBTPDFSVEVDU SIDE 121212122121212121111111112212122222112222111221112112212112212122 DIRECTION IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIOOOOOOOIOOIOOIOOIOOOOIOOIIIIOOO changed: 1 step 60 100000000000010010000000000000000000110111011011111010100110110111 fail ^^ SLOT BAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBAABBAAAAAAAAAAAAAABBBBBABBBB LETTER ALPSLFMDEEMCBFRSPKLEMFHRSCJLJKUHPNMBBNNVVRKRHUTDJUKANJHBTPDFSVEVDU SIDE 121212122121212121111111112212122222112222111221112112212112212122 DIRECTION IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIOOOOOOOIOOIOOIOOIOOOOIOOIIIIOOO changed: 0 step 61 100000000000010010000000000000000000110111011011011010100110110111 fail ^^ SLOT BAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBAABBAAAAAAAAAAAAAABBBBBABBBB LETTER ALPSLFMDEEMCBFRSPKLEMFHRSCJLJKUHPNMBBNNVVRKRHUTDJUKANJHBTPDFSVEVDU SIDE 121212122121212121111111112212122222112222111221112112212112212122 DIRECTION IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIOOOOOOOIOOIOOIOOIOOOOIOOIIIIOOO changed: 1 step 62 100000000000010010000000000000000000110111011011011110100110110111 fail ^^ ^^^^ SLOT BAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBAABBAAAAAAAAAAAAAABBBBBABBBB LETTER ALPSLFMDEEMCBFRSPKLEMFHRSCJLJKUHPNMBBNNVVRKRHUTDJUKANJHBTPDFSVEVDU SIDE 121212122121212121111111112212122222112222111221112112212112212122 DIRECTION IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIOOOOOOOIOOIOOIOOIOOOOIOOIIIIOOO changed: 0 step 63 100000000000010010000000000000000000110111011011011010100110110111 fail ^^ ^^^^ SLOT BAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBAABBAAAAAAAAAAAAAABBBBBABBBB LETTER ALPSLFMDEEMCBFRSPKLEMFHRSCJLJKUHPNMBBNNVVRKRHUTDJUKANJHBTPDFSVEVDU SIDE 121212122121212121111111112212122222112222111221112112212112212122 DIRECTION IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIOOOOOOOIOOIOOIOOIOOOOIOOIIIIOOO changed: 1 step 64 100000000000010010000000000000000000110111011011011010101110110111 fail ^^ ^^^^ ^^ SLOT BAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBAABBAAAAAAAAAAAAAABBBBBABBBB LETTER ALPSLFMDEEMCBFRSPKLEMFHRSCJLJKUHPNMBBNNVVRKRHUTDJUKANJHBTPDFSVEVDU SIDE 121212122121212121111111112212122222112222111221112112212112212122 DIRECTION IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIOOOOOOOIOOIOOIOOIOOOOIOOIIIIOOO changed: 0 step 65 100000000000010010000000000000000000110111011011011010100110110111 fail ^^ ^^^^ ^^ SLOT BAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBAABBAAAAAAAAAAAAAABBBBBABBBB LETTER ALPSLFMDEEMCBFRSPKLEMFHRSCJLJKUHPNMBBNNVVRKRHUTDJUKANJHBTPDFSVEVDU SIDE 121212122121212121111111112212122222112222111221112112212112212122 DIRECTION IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIOOOOOOOIOOIOOIOOIOOOOIOOIIIIOOO changed: 1 step 66 100000000000010010000000000000000000110111011011011010100111110111 fail ^^ ^^^^ ^^ ^^ SLOT BAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBAABBAAAAAAAAAAAAAABBBBBABBBB LETTER ALPSLFMDEEMCBFRSPKLEMFHRSCJLJKUHPNMBBNNVVRKRHUTDJUKANJHBTPDFSVEVDU SIDE 121212122121212121111111112212122222112222111221112112212112212122 DIRECTION IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIOOOOOOOIOOIOOIOOIOOOOIOOIIIIOOO changed: 0 step 67 100000000000010010000000000000000000110111011011011010100110110111 fail ^^ ^^^^ ^^ ^^ SLOT BAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBAABBAAAAAAAAAAAAAABBBBBABBBB LETTER ALPSLFMDEEMCBFRSPKLEMFHRSCJLJKUHPNMBBNNVVRKRHUTDJUKANJHBTPDFSVEVDU SIDE 121212122121212121111111112212122222112222111221112112212112212122 DIRECTION IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIOOOOOOOIOOIOOIOOIOOOOIOOIIIIOOO changed: 1 step 68 100001000000010010000000000000000000110111011011011010100110110111 fail ^^ ^^^^ ^^ ^^ SLOT BAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBAABBAAAAAAAAAAAAAABBBBBABBBB LETTER ALPSLFMDEEMCBFRSPKLEMFHRSCJLJKUHPNMBBNNVVRKRHUTDJUKANJHBTPDFSVEVDU SIDE 121212122121212121111111112212122222112222111221112112212112212122 DIRECTION IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIOOOOOOOIOOIOOIOOIOOOOIOOIIIIOOO changed: 1 step 69 100001100000010010000000000000000000110111011011011010100110110111 fail ^^ ^^^^ ^^ ^^ SLOT BAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBAABBAAAAAAAAAAAAAABBBBBABBBB LETTER ALPSLFMDEEMCBFRSPKLEMFHRSCJLJKUHPNMBBNNVVRKRHUTDJUKANJHBTPDFSVEVDU SIDE 121212122121212121111111112212122222112222111221112112212112212122 DIRECTION IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIOOOOOOOIOOIOOIOOIOOOOIOOIIIIOOO changed: 1 step 70 100001100100010010000000000000000000110111011011011010100110110111 fail ^^ ^^^^ ^^ ^^ SLOT BAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBAABBAAAAAAAAAAAAAABBBBBABBBB LETTER ALPSLFMDEEMCBFRSPKLEMFHRSCJLJKUHPNMBBNNVVRKRHUTDJUKANJHBTPDFSVEVDU SIDE 121212122121212121111111112212122222112222111221112112212112212122 DIRECTION IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIOOOOOOOIOOIOOIOOIOOOOIOOIIIIOOO changed: 1 step 71 100001100110010010000000000000000000110111011011011010100110110111 fail ^^ ^^^^ ^^ ^^ SLOT BAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBAABBAAAAAAAAAAAAAABBBBBABBBB LETTER ALPSLFMDEEMCBFRSPKLEMFHRSCJLJKUHPNMBBNNVVRKRHUTDJUKANJHBTPDFSVEVDU SIDE 121212122121212121111111112212122222112222111221112112212112212122 DIRECTION IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIOOOOOOOIOOIOOIOOIOOOOIOOIIIIOOO changed: 1 step 72 100001100110110010000000000000000000110111011011011010100110110111 fail ^^ ^^^^ ^^ ^^ SLOT BAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBAABBAAAAAAAAAAAAAABBBBBABBBB LETTER ALPSLFMDEEMCBFRSPKLEMFHRSCJLJKUHPNMBBNNVVRKRHUTDJUKANJHBTPDFSVEVDU SIDE 121212122121212121111111112212122222112222111221112112212112212122 DIRECTION IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIOOOOOOOIOOIOOIOOIOOOOIOOIIIIOOO changed: 1 step 73 100001100110110110000000000000000000110111011011011010100110110111 fail ^^ ^^^^ ^^ ^^ SLOT BAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBAABBAAAAAAAAAAAAAABBBBBABBBB LETTER ALPSLFMDEEMCBFRSPKLEMFHRSCJLJKUHPNMBBNNVVRKRHUTDJUKANJHBTPDFSVEVDU SIDE 121212122121212121111111112212122222112222111221112112212112212122 DIRECTION IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIOOOOOOOIOOIOOIOOIOOOOIOOIIIIOOO changed: 1 step 74 100001100110110110010000000000000000110111011011011010100110110111 fail ^^ ^^^^ ^^ ^^ SLOT BAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBAABBAAAAAAAAAAAAAABBBBBABBBB LETTER ALPSLFMDEEMCBFRSPKLEMFHRSCJLJKUHPNMBBNNVVRKRHUTDJUKANJHBTPDFSVEVDU SIDE 121212122121212121111111112212122222112222111221112112212112212122 DIRECTION IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIOOOOOOOIOOIOOIOOIOOOOIOOIIIIOOO changed: 1 step 75 100001100110110110011000000000000000110111011011011010100110110111 fail ^^ ^^^^ ^^ ^^ SLOT BAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBAABBAAAAAAAAAAAAAABBBBBABBBB LETTER ALPSLFMDEEMCBFRSPKLEMFHRSCJLJKUHPNMBBNNVVRKRHUTDJUKANJHBTPDFSVEVDU SIDE 121212122121212121111111112212122222112222111221112112212112212122 DIRECTION IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIOOOOOOOIOOIOOIOOIOOOOIOOIIIIOOO changed: 1 step 76 100001100110110110011010000000000000110111011011011010100110110111 fail ^^ ^^^^ ^^ ^^ SLOT BAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBAABBAAAAAAAAAAAAAABBBBBABBBB LETTER ALPSLFMDEEMCBFRSPKLEMFHRSCJLJKUHPNMBBNNVVRKRHUTDJUKANJHBTPDFSVEVDU SIDE 121212122121212121111111112212122222112222111221112112212112212122 DIRECTION IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIOOOOOOOIOOIOOIOOIOOOOIOOIIIIOOO changed: 1 step 77 100001100110110110011011000000000000110111011011011010100110110111 fail ^^ ^^^^ ^^ ^^ SLOT BAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBAABBAAAAAAAAAAAAAABBBBBABBBB LETTER ALPSLFMDEEMCBFRSPKLEMFHRSCJLJKUHPNMBBNNVVRKRHUTDJUKANJHBTPDFSVEVDU SIDE 121212122121212121111111112212122222112222111221112112212112212122 DIRECTION IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIOOOOOOOIOOIOOIOOIOOOOIOOIIIIOOO changed: 1 step 78 100001100110110110011011010000000000110111011011011010100110110111 fail ^^ ^^^^ ^^ ^^ SLOT BAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBAABBAAAAAAAAAAAAAABBBBBABBBB LETTER ALPSLFMDEEMCBFRSPKLEMFHRSCJLJKUHPNMBBNNVVRKRHUTDJUKANJHBTPDFSVEVDU SIDE 121212122121212121111111112212122222112222111221112112212112212122 DIRECTION IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIOOOOOOOIOOIOOIOOIOOOOIOOIIIIOOO changed: 1 step 79 100001100110110110011011011000000000110111011011011010100110110111 fail ^^ ^^^^ ^^ ^^ SLOT BAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBAABBAAAAAAAAAAAAAABBBBBABBBB LETTER ALPSLFMDEEMCBFRSPKLEMFHRSCJLJKUHPNMBBNNVVRKRHUTDJUKANJHBTPDFSVEVDU SIDE 121212122121212121111111112212122222112222111221112112212112212122 DIRECTION IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIOOOOOOOIOOIOOIOOIOOOOIOOIIIIOOO changed: 1 step 80 100001100110110110011011011010000000110111011011011010100110110111 fail ^^ ^^^^ ^^ ^^ SLOT BAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBAABBAAAAAAAAAAAAAABBBBBABBBB LETTER ALPSLFMDEEMCBFRSPKLEMFHRSCJLJKUHPNMBBNNVVRKRHUTDJUKANJHBTPDFSVEVDU SIDE 121212122121212121111111112212122222112222111221112112212112212122 DIRECTION IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIOOOOOOOIOOIOOIOOIOOOOIOOIIIIOOO changed: 1 step 81 100001100110110110011011011011000000110111011011011010100110110111 fail ^^ ^^^^ ^^ ^^ SLOT BAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBAABBAAAAAAAAAAAAAABBBBBABBBB LETTER ALPSLFMDEEMCBFRSPKLEMFHRSCJLJKUHPNMBBNNVVRKRHUTDJUKANJHBTPDFSVEVDU SIDE 121212122121212121111111112212122222112222111221112112212112212122 DIRECTION IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIOOOOOOOIOOIOOIOOIOOOOIOOIIIIOOO changed: 1 step 82 100001100110110110011011011011010000110111011011011010100110110111 fail ^^ ^^^^ ^^ ^^ SLOT BAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBAABBAAAAAAAAAAAAAABBBBBABBBB LETTER ALPSLFMDEEMCBFRSPKLEMFHRSCJLJKUHPNMBBNNVVRKRHUTDJUKANJHBTPDFSVEVDU SIDE 121212122121212121111111112212122222112222111221112112212112212122 DIRECTION IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIOOOOOOOIOOIOOIOOIOOOOIOOIIIIOOO changed: 1 step 83 100001100110110110011011011011011000110111011011011010100110110111 fail ^^ ^^^^ ^^ ^^ SLOT BAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBAABBAAAAAAAAAAAAAABBBBBABBBB LETTER ALPSLFMDEEMCBFRSPKLEMFHRSCJLJKUHPNMBBNNVVRKRHUTDJUKANJHBTPDFSVEVDU SIDE 121212122121212121111111112212122222112222111221112112212112212122 DIRECTION IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIOOOOOOOIOOIOOIOOIOOOOIOOIIIIOOO changed: 1 step 84 100001100110110110011011011011011100110111011011011010100110110111 fail ^^ ^^^^ ^^ ^^ SLOT BAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBAABBAAAAAAAAAAAAAABBBBBABBBB LETTER ALPSLFMDEEMCBFRSPKLEMFHRSCJLJKUHPNMBBNNVVRKRHUTDJUKANJHBTPDFSVEVDU SIDE 121212122121212121111111112212122222112222111221112112212112212122 DIRECTION IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIOOOOOOOIOOIOOIOOIOOOOIOOIIIIOOO changed: 1 step 85 110001100110110110011011011011011100110111011011011010100110110111 fail ^^ ^^^^ ^^ ^^ SLOT BAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBAABBAAAAAAAAAAAAAABBBBBABBBB LETTER ALPSLFMDEEMCBFRSPKLEMFHRSCJLJKUHPNMBBNNVVRKRHUTDJUKANJHBTPDFSVEVDU SIDE 121212122121212121111111112212122222112222111221112112212112212122 DIRECTION IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIOOOOOOOIOOIOOIOOIOOOOIOOIIIIOOO changed: 0 step 86 100001100110110110011011011011011100110111011011011010100110110111 fail ^ ^ ^^ ^^ ^^^^ ^^ ^^ SLOT BAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBAABBAAAAAAAAAAAAAABBBBBABBBB LETTER ALPSLFMDEEMCBFRSPKLEMFHRSCJLJKUHPNMBBNNVVRKRHUTDJUKANJHBTPDFSVEVDU SIDE 121212122121212121111111112212122222112222111221112112212112212122 DIRECTION IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIOOOOOOOIOOIOOIOOIOOOOIOOIIIIOOO changed: 1 step 87 101001100110110110011011011011011100110111011011011010100110110111 fail ^^ ^^^^ ^^ ^^ SLOT BAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBAABBAAAAAAAAAAAAAABBBBBABBBB LETTER ALPSLFMDEEMCBFRSPKLEMFHRSCJLJKUHPNMBBNNVVRKRHUTDJUKANJHBTPDFSVEVDU SIDE 121212122121212121111111112212122222112222111221112112212112212122 DIRECTION IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIOOOOOOOIOOIOOIOOIOOOOIOOIIIIOOO changed: 0 step 88 100001100110110110011011011011011100110111011011011010100110110111 fail ^ ^ ^^ ^^ ^^^^ ^^ ^^ SLOT BAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBAABBAAAAAAAAAAAAAABBBBBABBBB LETTER ALPSLFMDEEMCBFRSPKLEMFHRSCJLJKUHPNMBBNNVVRKRHUTDJUKANJHBTPDFSVEVDU SIDE 121212122121212121111111112212122222112222111221112112212112212122 DIRECTION IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIOOOOOOOIOOIOOIOOIOOOOIOOIIIIOOO changed: 1 step 89 100101100110110110011011011011011100110111011011011010100110110111 fail ^^ ^^^^ ^^ ^^ SLOT BAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBAABBAAAAAAAAAAAAAABBBBBABBBB LETTER ALPSLFMDEEMCBFRSPKLEMFHRSCJLJKUHPNMBBNNVVRKRHUTDJUKANJHBTPDFSVEVDU SIDE 121212122121212121111111112212122222112222111221112112212112212122 DIRECTION IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIOOOOOOOIOOIOOIOOIOOOOIOOIIIIOOO changed: 0 step 90 100001100110110110011011011011011100110111011011011010100110110111 fail ^ ^ ^^ ^^ ^^^^ ^^ ^^ SLOT BAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBAABBAAAAAAAAAAAAAABBBBBABBBB LETTER ALPSLFMDEEMCBFRSPKLEMFHRSCJLJKUHPNMBBNNVVRKRHUTDJUKANJHBTPDFSVEVDU SIDE 121212122121212121111111112212122222112222111221112112212112212122 DIRECTION IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIOOOOOOOIOOIOOIOOIOOOOIOOIIIIOOO changed: 1 step 91 100011100110110110011011011011011100110111011011011010100110110111 fail ^^ ^^^^ ^^ ^^ SLOT BAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBAABBAAAAAAAAAAAAAABBBBBABBBB LETTER ALPSLFMDEEMCBFRSPKLEMFHRSCJLJKUHPNMBBNNVVRKRHUTDJUKANJHBTPDFSVEVDU SIDE 121212122121212121111111112212122222112222111221112112212112212122 DIRECTION IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIOOOOOOOIOOIOOIOOIOOOOIOOIIIIOOO changed: 0 step 92 100001100110110110011011011011011100110111011011011010100110110111 fail ^ ^ ^^ ^^ ^^^^ ^^ ^^ SLOT BAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBAABBAAAAAAAAAAAAAABBBBBABBBB LETTER ALPSLFMDEEMCBFRSPKLEMFHRSCJLJKUHPNMBBNNVVRKRHUTDJUKANJHBTPDFSVEVDU SIDE 121212122121212121111111112212122222112222111221112112212112212122 DIRECTION IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIOOOOOOOIOOIOOIOOIOOOOIOOIIIIOOO changed: 1 step 93 100001110110110110011011011011011100110111011011011010100110110111 fail ^^ ^^^^ ^^ ^^ SLOT BAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBAABBAAAAAAAAAAAAAABBBBBABBBB LETTER ALPSLFMDEEMCBFRSPKLEMFHRSCJLJKUHPNMBBNNVVRKRHUTDJUKANJHBTPDFSVEVDU SIDE 121212122121212121111111112212122222112222111221112112212112212122 DIRECTION IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIOOOOOOOIOOIOOIOOIOOOOIOOIIIIOOO changed: 0 step 94 100001100110110110011011011011011100110111011011011010100110110111 fail ^ ^ ^^ ^^ ^^^^ ^^ ^^ SLOT BAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBAABBAAAAAAAAAAAAAABBBBBABBBB LETTER ALPSLFMDEEMCBFRSPKLEMFHRSCJLJKUHPNMBBNNVVRKRHUTDJUKANJHBTPDFSVEVDU SIDE 121212122121212121111111112212122222112222111221112112212112212122 DIRECTION IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIOOOOOOOIOOIOOIOOIOOOOIOOIIIIOOO changed: 1 step 95 100001101110110110011011011011011100110111011011011010100110110111 fail ^^ ^^^^ ^^ ^^ SLOT BAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBAABBAAAAAAAAAAAAAABBBBBABBBB LETTER ALPSLFMDEEMCBFRSPKLEMFHRSCJLJKUHPNMBBNNVVRKRHUTDJUKANJHBTPDFSVEVDU SIDE 121212122121212121111111112212122222112222111221112112212112212122 DIRECTION IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIOOOOOOOIOOIOOIOOIOOOOIOOIIIIOOO changed: 0 step 96 100001100110110110011011011011011100110111011011011010100110110111 fail ^ ^ ^^ ^^ ^^^^ ^^ ^^ SLOT BAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBAABBAAAAAAAAAAAAAABBBBBABBBB LETTER ALPSLFMDEEMCBFRSPKLEMFHRSCJLJKUHPNMBBNNVVRKRHUTDJUKANJHBTPDFSVEVDU SIDE 121212122121212121111111112212122222112222111221112112212112212122 DIRECTION IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIOOOOOOOIOOIOOIOOIOOOOIOOIIIIOOO changed: 1 step 97 100001100111110110011011011011011100110111011011011010100110110111 fail ^ ^ ^^ ^^^^ ^^ ^^ SLOT BAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBAABBAAAAAAAAAAAAAABBBBBABBBB LETTER ALPSLFMDEEMCBFRSPKLEMFHRSCJLJKUHPNMBBNNVVRKRHUTDJUKANJHBTPDFSVEVDU SIDE 121212122121212121111111112212122222112222111221112112212112212122 DIRECTION IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIOOOOOOOIOOIOOIOOIOOOOIOOIIIIOOO changed: 0 step 98 100001100110110110011011011011011100110111011011011010100110110111 fail ^ ^ ^^ ^^ ^^^^ ^^ ^^ SLOT BAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBAABBAAAAAAAAAAAAAABBBBBABBBB LETTER ALPSLFMDEEMCBFRSPKLEMFHRSCJLJKUHPNMBBNNVVRKRHUTDJUKANJHBTPDFSVEVDU SIDE 121212122121212121111111112212122222112222111221112112212112212122 DIRECTION IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIOOOOOOOIOOIOOIOOIOOOOIOOIIIIOOO changed: step 99 100001100110110110011011011011011100110111011011011010100110110111 fail ^ ^ ^^ ^^^^ ^^ ^^ SLOT BAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBAABBAAAAAAAAAAAAAABBBBBABBBB LETTER ALPSLFMDEEMCBFRSPKLEMFHRSCJLJKUHPNMBBNNVVRKRHUTDJUKANJHBTPDFSVEVDU SIDE 121212122121212121111111112212122222112222111221112112212112212122 DIRECTION IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIOOOOOOOIOOIOOIOOIOOOOIOOIIIIOOO changed: 0 1 0 step 100 100001100110100110011011011011011101110110011011011010100110110111 fail ^ ^ ^^ ^^^^ ^^ ^^ SLOT BAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBAABBAAAAAAAAAAAAAABBBBBABBBB LETTER ALPSLFMDEEMCBFRSPKLEMFHRSCJLJKUHPNMBBNNVVRKRHUTDJUKANJHBTPDFSVEVDU SIDE 121212122121212121111111112212122222112222111221112112212112212122 DIRECTION IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIOOOOOOOIOOIOOIOOIOOOOIOOIIIIOOO changed: 1 step 101 100001100110101110011011011011011101110110011011011010100110110111 fail ^^ ^^^^ ^^ ^^ SLOT BAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBAABBAAAAAAAAAAAAAABBBBBABBBB LETTER ALPSLFMDEEMCBFRSPKLEMFHRSCJLJKUHPNMBBNNVVRKRHUTDJUKANJHBTPDFSVEVDU SIDE 121212122121212121111111112212122222112222111221112112212112212122 DIRECTION IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIOOOOOOOIOOIOOIOOIOOOOIOOIIIIOOO changed: 0 step 102 100001100110100110011011011011011101110110011011011010100110110111 fail ^ ^ ^^ ^^^^ ^^ ^^ SLOT BAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBAABBAAAAAAAAAAAAAABBBBBABBBB LETTER ALPSLFMDEEMCBFRSPKLEMFHRSCJLJKUHPNMBBNNVVRKRHUTDJUKANJHBTPDFSVEVDU SIDE 121212122121212121111111112212122222112222111221112112212112212122 DIRECTION IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIOOOOOOOIOOIOOIOOIOOOOIOOIIIIOOO changed: step 103 100001100110100110011011011011011101110110011011011010100110110111 fail ^^ ^^^^ ^^ ^^ SLOT BAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBAABBAAAAAAAAAAAAAABBBBBABBBB LETTER ALPSLFMDEEMCBFRSPKLEMFHRSCJLJKUHPNMBBNNVVRKRHUTDJUKANJHBTPDFSVEVDU SIDE 121212122121212121111111112212122222112222111221112112212112212122 DIRECTION IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIOOOOOOOIOOIOOIOOIOOOOIOOIIIIOOO changed: 0 1 0 step 104 100001100110100100011011011011011101111100011011011010100110110111 fail ^^ ^^^^ ^^ ^^ SLOT BAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBAABBAAAAAAAAAAAAAABBBBBABBBB LETTER ALPSLFMDEEMCBFRSPKLEMFHRSCJLJKUHPNMBBNNVVRKRHUTDJUKANJHBTPDFSVEVDU SIDE 121212122121212121111111112212122222112222111221112112212112212122 DIRECTION IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIOOOOOOOIOOIOOIOOIOOOOIOOIIIIOOO changed: 1 00 11 step 105 100001100110100101011011011011011101001111011011011010100110110111 fail ^^ ^^^^ ^^ ^^ SLOT BAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBAABBAAAAAAAAAAAAAABBBBBABBBB LETTER ALPSLFMDEEMCBFRSPKLEMFHRSCJLJKUHPNMBBNNVVRKRHUTDJUKANJHBTPDFSVEVDU SIDE 121212122121212121111111112212122222112222111221112112212112212122 DIRECTION IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIOOOOOOOIOOIOOIOOIOOOOIOOIIIIOOO changed: 0 11 00 step 106 100001100110100100011011011011011101111100011011011010100110110111 fail ^^ ^^^^ ^^ ^^ SLOT BAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBAABBAAAAAAAAAAAAAABBBBBABBBB LETTER ALPSLFMDEEMCBFRSPKLEMFHRSCJLJKUHPNMBBNNVVRKRHUTDJUKANJHBTPDFSVEVDU SIDE 121212122121212121111111112212122222112222111221112112212112212122 DIRECTION IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIOOOOOOOIOOIOOIOOIOOOOIOOIIIIOOO changed: 1 00 11 step 107 100001100110100100111011011011011101001111011011011010100110110111 fail ^^ ^^^^ ^^ ^^ SLOT BAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBAABBAAAAAAAAAAAAAABBBBBABBBB LETTER ALPSLFMDEEMCBFRSPKLEMFHRSCJLJKUHPNMBBNNVVRKRHUTDJUKANJHBTPDFSVEVDU SIDE 121212122121212121111111112212122222112222111221112112212112212122 DIRECTION IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIOOOOOOOIOOIOOIOOIOOOOIOOIIIIOOO changed: 0 11 00 step 108 100001100110100100011011011011011101111100011011011010100110110111 fail ^^ ^^^^ ^^ ^^ SLOT BAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBAABBAAAAAAAAAAAAAABBBBBABBBB LETTER ALPSLFMDEEMCBFRSPKLEMFHRSCJLJKUHPNMBBNNVVRKRHUTDJUKANJHBTPDFSVEVDU SIDE 121212122121212121111111112212122222112222111221112112212112212122 DIRECTION IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIOOOOOOOIOOIOOIOOIOOOOIOOIIIIOOO changed: 1 00 11 step 109 100001100110100100011111011011011101001111011011011010100110110111 fail ^^ ^^^^ ^^ ^^ SLOT BAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBAABBAAAAAAAAAAAAAABBBBBABBBB LETTER ALPSLFMDEEMCBFRSPKLEMFHRSCJLJKUHPNMBBNNVVRKRHUTDJUKANJHBTPDFSVEVDU SIDE 121212122121212121111111112212122222112222111221112112212112212122 DIRECTION IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIOOOOOOOIOOIOOIOOIOOOOIOOIIIIOOO changed: 0 11 00 step 110 100001100110100100011011011011011101111100011011011010100110110111 fail ^^ ^^^^ ^^ ^^ SLOT BAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBAABBAAAAAAAAAAAAAABBBBBABBBB LETTER ALPSLFMDEEMCBFRSPKLEMFHRSCJLJKUHPNMBBNNVVRKRHUTDJUKANJHBTPDFSVEVDU SIDE 121212122121212121111111112212122222112222111221112112212112212122 DIRECTION IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIOOOOOOOIOOIOOIOOIOOOOIOOIIIIOOO changed: 1 00 11 step 111 100001100110100100011011111011011101001111011011011010100110110111 fail ^^ ^^^^ ^^ ^^ SLOT BAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBAABBAAAAAAAAAAAAAABBBBBABBBB LETTER ALPSLFMDEEMCBFRSPKLEMFHRSCJLJKUHPNMBBNNVVRKRHUTDJUKANJHBTPDFSVEVDU SIDE 121212122121212121111111112212122222112222111221112112212112212122 DIRECTION IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIOOOOOOOIOOIOOIOOIOOOOIOOIIIIOOO changed: 0 11 00 step 112 100001100110100100011011011011011101111100011011011010100110110111 fail ^^ ^^^^ ^^ ^^ SLOT BAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBAABBAAAAAAAAAAAAAABBBBBABBBB LETTER ALPSLFMDEEMCBFRSPKLEMFHRSCJLJKUHPNMBBNNVVRKRHUTDJUKANJHBTPDFSVEVDU SIDE 121212122121212121111111112212122222112222111221112112212112212122 DIRECTION IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIOOOOOOOIOOIOOIOOIOOOOIOOIIIIOOO changed: 1 00 11 step 113 100001100110100100011011011111011101001111011011011010100110110111 fail ^^ ^^^^ ^^ ^^ SLOT BAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBAABBAAAAAAAAAAAAAABBBBBABBBB LETTER ALPSLFMDEEMCBFRSPKLEMFHRSCJLJKUHPNMBBNNVVRKRHUTDJUKANJHBTPDFSVEVDU SIDE 121212122121212121111111112212122222112222111221112112212112212122 DIRECTION IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIOOOOOOOIOOIOOIOOIOOOOIOOIIIIOOO changed: 0 11 00 step 114 100001100110100100011011011011011101111100011011011010100110110111 fail ^^ ^^^^ ^^ ^^ SLOT BAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBAABBAAAAAAAAAAAAAABBBBBABBBB LETTER ALPSLFMDEEMCBFRSPKLEMFHRSCJLJKUHPNMBBNNVVRKRHUTDJUKANJHBTPDFSVEVDU SIDE 121212122121212121111111112212122222112222111221112112212112212122 DIRECTION IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIOOOOOOOIOOIOOIOOIOOOOIOOIIIIOOO changed: 1 00 11 step 115 100001100110100100011011011011111101001111011011011010100110110111 fail ^^ ^^^^ ^^ ^^ SLOT BAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBAABBAAAAAAAAAAAAAABBBBBABBBB LETTER ALPSLFMDEEMCBFRSPKLEMFHRSCJLJKUHPNMBBNNVVRKRHUTDJUKANJHBTPDFSVEVDU SIDE 121212122121212121111111112212122222112222111221112112212112212122 DIRECTION IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIOOOOOOOIOOIOOIOOIOOOOIOOIIIIOOO changed: 0 11 00 step 116 100001100110100100011011011011011101111100011011011010100110110111 fail ^^ ^^^^ ^^ ^^ SLOT BAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBAABBAAAAAAAAAAAAAABBBBBABBBB LETTER ALPSLFMDEEMCBFRSPKLEMFHRSCJLJKUHPNMBBNNVVRKRHUTDJUKANJHBTPDFSVEVDU SIDE 121212122121212121111111112212122222112222111221112112212112212122 DIRECTION IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIOOOOOOOIOOIOOIOOIOOOOIOOIIIIOOO changed: 1 0 1 step 117 100001100110100100011011011011011111101110011011011010100110110111 fail ^^ ^^^^ ^^ ^^ SLOT BAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBAABBAAAAAAAAAAAAAABBBBBABBBB LETTER ALPSLFMDEEMCBFRSPKLEMFHRSCJLJKUHPNMBBNNVVRKRHUTDJUKANJHBTPDFSVEVDU SIDE 121212122121212121111111112212122222112222111221112112212112212122 DIRECTION IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIOOOOOOOIOOIOOIOOIOOOOIOOIIIIOOO changed: 0 1 0 step 118 100001100110100100011011011011011101111100011011011010100110110111 fail ^^ ^^^^ ^^ ^^ step 119 100000000000000000000000000000000001111100011011011010100110110111 step 120 100000000000000000000000000000000001111100011011011010100110100111 step 121 100000000000000000000000000000000001111100011011011010100110101101 step 122 100000000000000000000000000000000001111100011011011010100110100101 step 123 100000000000000000000000000000000001111100011011011010100110000001 step 124 100000000000000000000000000000000001111100011011011010100110100101 step 125 100000000000000000000000000000000001111100011011011010100110100101 step 126 100000000000000000000000000000000001111100011011011010100110101001 step 127 100000000000000000000000000000000001111100011011011010100110100001 step 128 100000000000000000000000000000000001111100011011011010100110000101 step 129 100000000000000000000000000000000001111100011011011010100110100001 step 130 100000000000000000000000000000000001111100011011011010100110100001 step 131 100000000000000000000000000000000001111100011011011010100110101001 step 132 100000000000000000000000000000000001111100011011011010100110100001 step 133 100000000000000000000000000000000001111100011011011010100110110001 step 134 100000000000000000000000000000000001111100011011011010100110111011 step 135 100000000000000000000000000000000001111100011011011010100110110011 step 136 100000000000000000000000000000000001111100011011011010100110110011 step 137 100000000000000000000000000000000001111100011011011010100110111111 step 138 100000000000000000000000000000000001111100011011011010100110110111 step 139 100000000000000000000000000000000001111100011011011010100110110111 step 140 100000000000000000000000000000000001111100011011011010100110111111 step 141 100000000000000000000000000000000001111100011011011010100110110111 step 142 100000000000000000000000000000000001111100011011011010100110100111 step 143 100000000000000000000000000000000001111100011011011010100110101101 step 144 100000000000000000000000000000000001111100011011011010100110100101 step 145 100000000000000000000000000000000001111100011011011010100110110101 step 146 100000000000000000000000000000000001111100011011011010100110111011 step 147 100000000000000000000000000000000001111100011011011010100110110011 step 148 100000000000000000000000000000000001111100011011011010100110100011 step 149 100000000000000000000000000000000001111100011011011010100110101101 step 150 100000000000000000000000000000000001111100011011011010100110100101 step 151 100000000000000000000000000000000001111100011011011010100110110101 step 152 100000000000000000000000000000000001111100011011011010100110111011 step 153 100000000000000000000000000000000001111100011011011010100110110011 step 154 100000000000000000000000000000000001111100011011011010100110110011 step 155 100000000000000000000000000000000001111100011011011010100110111111 step 156 100000000000000000000000000000000001111100011011011010100110110111 step 157 100000000000000000000000000000000001111100011011011010100110110111 test 1: *** FAIL *************************** 65 steps failed SLOT BAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBAABBAAAAAAAAAAAAAABBBBBABBBB LETTER ALPSLFMDEEMCBFRSPKLEMFHRSCJLJKUHPNMBBNNVVRKRHUTDJUKANJHBTPDFSVEVDU SIDE 121212122121212121111111112212122222112222111221112112212112212122 DIRECTION IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIOOOOOOOIOOIOOIOOIOOOOIOOIIIIOOO this fail O O OO OO OOOO OO OO all fails O O OO OO OOOO OO OO was hi 111111111111111111111111111111111111111111111111111111111111111111 rising ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ ^^^^^^^^^^^^^^^ ^^^^^^^^^ falling vvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvv vvvvvvvvvv vvv vvv vvvvvv was lo 00000000000000000000000000000000000000 0000000000000000000000000 total fails 1, total passes 0 space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C toggle comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit step 1 100000000000000000000000000000000001111100011011011010100110110111 step 2 100000000000000000000000000000000001111100100011011010100110110111 step 3 100000000000000000000000000000000001111100000011011010100110110111 step 4 100000000000000000000000000000000001111100000100011010100110110111 step 5 100000000000000000000000000000000001111100000000011010100110110111 step 6 100000000000000000000000000000000001111100000000100010100110110111 step 7 100000000000000000000000000000000001111100000000000010100110110111 step 8 100000000000000000000000000000000001111100000000000101010110110111 step 9 100000000000000000000000000000000001111100000000000001010110110111 step 10 100000000000000000000000000000000001111100000000000001011000110111 step 11 100000000000000000000000000000000001111100000000000001010000110111 step 12 100000000000000000000000000000000001111100000000000001010001110001 step 13 100000000000000000000000000000000001111100000000000001010000110001 step 14 100000000000000000000000000000000001111100000000000001010000110001 step 15 100000000000010000000000000000000000111101000000000001010000110001 step 16 100000000000010010000000000000000000110111000000000001010000110001 step 17 100000000000010010000000000000000000110111111000000001010000110001 step 18 100000000000010010000000000000000000110111011000000001010000110001 step 19 100000000000010010000000000000000000110111011111000001010000110001 step 20 100000000000010010000000000000000000110111011011000001010000110001 step 21 100000000000010010000000000000000000110111011011111001010000110001 step 22 100000000000010010000000000000000000110111011011011001010000110001 step 23 100000000000010010000000000000000000110111011011011110100000110001 step 24 100000000000010010000000000000000000110111011011011010100000110001 step 25 100000000000010010000000000000000000110111011011011010101110110001 step 26 100000000000010010000000000000000000110111011011011010100110110001 step 27 100000000000010010000000000000000000110111011011011010100111110111 step 28 100000000000010010000000000000000000110111011011011010100110110111 step 29 100000000000000010000000000000000001110110011011011010100110110111 step 30 100000000000000000000000000000000001111100011011011010100110110111 step 31 100000000000000000000000000000000001111100011011011010100110110111 step 32 100000000000000000000000000000000001111100011011011010100110110111 step 33 100000000000010000000000000000000000111101011011011010100110110111 step 34 100000000000010000000000000000000000111101101011011010100110110111 step 35 100000000000010000000000000000000000111101001011011010100110110111 step 36 100000000000010010000000000000000000110111001011011010100110110111 step 37 100000000000010010000000000000000000110111111011011010100110110111 step 38 100000000000010010000000000000000000110111011011011010100110110111 step 39 100000000000010010000000000000000000110111011011011010100110110111 SLOT BAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBAABBAAAAAAAAAAAAAABBBBBABBBB LETTER ALPSLFMDEEMCBFRSPKLEMFHRSCJLJKUHPNMBBNNVVRKRHUTDJUKANJHBTPDFSVEVDU SIDE 121212122121212121111111112212122222112222111221112112212112212122 DIRECTION IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIOOOOOOOIOOIOOIOOIOOOOIOOIIIIOOO changed: 0 1 0 step 40 100000000000000010000000000000000001110110011011011010100110110111 fail ^ ^ space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C toggle comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit comment_flag is 1 space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C toggle comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT BAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBAABBAAAAAAAAAAAAAABBBBBABBBB LETTER ALPSLFMDEEMCBFRSPKLEMFHRSCJLJKUHPNMBBNNVVRKRHUTDJUKANJHBTPDFSVEVDU SIDE 121212122121212121111111112212122222112222111221112112212112212122 DIRECTION IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIOOOOOOOIOOIOOIOOIOOOOIOOIIIIOOO source: ; load TMA SETUP from tape bus (10) source: 110 changed: 1 0 step 41 100000000000000010000000000000000001110110110011011010100110110111 fail ^ ^ SLOT BAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBAABBAAAAAAAAAAAAAABBBBBABBBB LETTER ALPSLFMDEEMCBFRSPKLEMFHRSCJLJKUHPNMBBNNVVRKRHUTDJUKANJHBTPDFSVEVDU SIDE 121212122121212121111111112212122222112222111221112112212112212122 DIRECTION IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIOOOOOOOIOOIOOIOOIOOOOIOOIIIIOOO source: 0 changed: 0 step 42 100000000000000010000000000000000001110110010011011010100110110111 fail ^ ^ source: ; restore TMA SETUP 3 source: ; set pin AF1 which clears pin BB2 and sets pin BR2 TAPE BUS 3 OUTPUT source: 1 0 1 changed: 1 0 1 step 43 100000000000010010000000000000000000110111010011011010100110110111 source: ; load TMA SETUP from tape bus (11) source: 111 changed: 1 1 step 44 100000000000010010000000000000000000110111111011011010100110110111 source: 0 changed: 0 step 45 100000000000010010000000000000000000110111011011011010100110110111 source: source: source: ; walk a 0, TMA 2 source: source: source: ; clear pin AP2 which sets pin AN2 and clears pin BV2 TAPE BUS 2 OUTPUT source: 0 1 0 changed: 0 1 0 step 46 100000000000010000000000000000000000111101011011011010100110110111 source: ; set pin AF1 which clears pin BB2 and sets pin BR2 TAPE BUS 3 OUTPUT source: 1 0 1 changed: step 47 100000000000010000000000000000000000111101011011011010100110110111 source: ; load TMA from tape bus (01) source: 101 changed: 10 step 48 100000000000010000000000000000000000111101011101011010100110110111 source: 0 changed: 0 step 49 100000000000010000000000000000000000111101011001011010100110110111 source: ; restore TMA 2 source: ; set pin AP2 which clears pin AN2 and sets pin BV2 TAPE BUS 2 OUTPUT source: 1 0 1 changed: 1 0 1 step 50 100000000000010010000000000000000000110111011001011010100110110111 source: ; load TMA from tape bus (11) source: 111 changed: 11 step 51 100000000000010010000000000000000000110111011111011010100110110111 source: 0 changed: 0 step 52 100000000000010010000000000000000000110111011011011010100110110111 source: source: source: ; walk a 0, TMA 3 source: source: source: ; set pin AP2 which clears pin AN2 and sets pin BV2 TAPE BUS 2 OUTPUT source: 1 0 1 changed: step 53 100000000000010010000000000000000000110111011011011010100110110111 SLOT BAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBAABBAAAAAAAAAAAAAABBBBBABBBB LETTER ALPSLFMDEEMCBFRSPKLEMFHRSCJLJKUHPNMBBNNVVRKRHUTDJUKANJHBTPDFSVEVDU SIDE 121212122121212121111111112212122222112222111221112112212112212122 DIRECTION IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIOOOOOOOIOOIOOIOOIOOOOIOOIIIIOOO source: ; clear pin AF1 which sets pin BB2 and clears pin BR2 TAPE BUS 3 OUTPUT source: 0 0 1 changed: 0 1 0 step 54 100000000000000010000000000000000001110110011011011010100110110111 fail ^ ^ SLOT BAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBAABBAAAAAAAAAAAAAABBBBBABBBB LETTER ALPSLFMDEEMCBFRSPKLEMFHRSCJLJKUHPNMBBNNVVRKRHUTDJUKANJHBTPDFSVEVDU SIDE 121212122121212121111111112212122222112222111221112112212112212122 DIRECTION IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIOOOOOOOIOOIOOIOOIOOOOIOOIIIIOOO source: ; load TMA from tape bus (10) source: 110 changed: 1 0 step 55 100000000000000010000000000000000001110110011110011010100110110111 fail ^ ^ SLOT BAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBAABBAAAAAAAAAAAAAABBBBBABBBB LETTER ALPSLFMDEEMCBFRSPKLEMFHRSCJLJKUHPNMBBNNVVRKRHUTDJUKANJHBTPDFSVEVDU SIDE 121212122121212121111111112212122222112222111221112112212112212122 DIRECTION IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIOOOOOOOIOOIOOIOOIOOOOIOOIIIIOOO source: 0 changed: 0 step 56 100000000000000010000000000000000001110110011010011010100110110111 fail ^ ^ source: ; restore TMA 3 source: ; set pin AF1 which clears pin BB2 and sets pin BR2 TAPE BUS 3 OUTPUT source: 1 0 1 changed: 1 0 1 step 57 100000000000010010000000000000000000110111011010011010100110110111 source: ; load TMA from tape bus (11) source: 111 changed: 1 1 step 58 100000000000010010000000000000000000110111011111011010100110110111 source: 0 changed: 0 step 59 100000000000010010000000000000000000110111011011011010100110110111 SLOT BAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBAABBAAAAAAAAAAAAAABBBBBABBBB LETTER ALPSLFMDEEMCBFRSPKLEMFHRSCJLJKUHPNMBBNNVVRKRHUTDJUKANJHBTPDFSVEVDU SIDE 121212122121212121111111112212122222112222111221112112212112212122 DIRECTION IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIOOOOOOOIOOIOOIOOIOOOOIOOIIIIOOO source: source: source: source: source: source: source: source: source: source: source: source: ; load TBN from tape bus (00) source: 100 changed: 1 step 60 100000000000010010000000000000000000110111011011111010100110110111 fail ^^ SLOT BAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBAABBAAAAAAAAAAAAAABBBBBABBBB LETTER ALPSLFMDEEMCBFRSPKLEMFHRSCJLJKUHPNMBBNNVVRKRHUTDJUKANJHBTPDFSVEVDU SIDE 121212122121212121111111112212122222112222111221112112212112212122 DIRECTION IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIOOOOOOOIOOIOOIOOIOOOOIOOIIIIOOO source: 0 changed: 0 step 61 100000000000010010000000000000000000110111011011011010100110110111 fail ^^ SLOT BAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBAABBAAAAAAAAAAAAAABBBBBABBBB LETTER ALPSLFMDEEMCBFRSPKLEMFHRSCJLJKUHPNMBBNNVVRKRHUTDJUKANJHBTPDFSVEVDU SIDE 121212122121212121111111112212122222112222111221112112212112212122 DIRECTION IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIOOOOOOOIOOIOOIOOIOOOOIOOIIIIOOO source: ; load TAC from tape bus (00) source: 10101 changed: 1 step 62 100000000000010010000000000000000000110111011011011110100110110111 fail ^^ ^^^^ SLOT BAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBAABBAAAAAAAAAAAAAABBBBBABBBB LETTER ALPSLFMDEEMCBFRSPKLEMFHRSCJLJKUHPNMBBNNVVRKRHUTDJUKANJHBTPDFSVEVDU SIDE 121212122121212121111111112212122222112222111221112112212112212122 DIRECTION IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIOOOOOOOIOOIOOIOOIOOOOIOOIIIIOOO source: 0 changed: 0 step 63 100000000000010010000000000000000000110111011011011010100110110111 fail ^^ ^^^^ SLOT BAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBAABBAAAAAAAAAAAAAABBBBBABBBB LETTER ALPSLFMDEEMCBFRSPKLEMFHRSCJLJKUHPNMBBNNVVRKRHUTDJUKANJHBTPDFSVEVDU SIDE 121212122121212121111111112212122222112222111221112112212112212122 DIRECTION IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIOOOOOOOIOOIOOIOOIOOOOIOOIIIIOOO source: ; load TB from tape bus (00) source: 100 changed: 1 step 64 100000000000010010000000000000000000110111011011011010101110110111 fail ^^ ^^^^ ^^ SLOT BAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBAABBAAAAAAAAAAAAAABBBBBABBBB LETTER ALPSLFMDEEMCBFRSPKLEMFHRSCJLJKUHPNMBBNNVVRKRHUTDJUKANJHBTPDFSVEVDU SIDE 121212122121212121111111112212122222112222111221112112212112212122 DIRECTION IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIOOOOOOOIOOIOOIOOIOOOOIOOIIIIOOO source: 0 changed: 0 step 65 100000000000010010000000000000000000110111011011011010100110110111 fail ^^ ^^^^ ^^ SLOT BAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBAABBAAAAAAAAAAAAAABBBBBABBBB LETTER ALPSLFMDEEMCBFRSPKLEMFHRSCJLJKUHPNMBBNNVVRKRHUTDJUKANJHBTPDFSVEVDU SIDE 121212122121212121111111112212122222112222111221112112212112212122 DIRECTION IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIOOOOOOOIOOIOOIOOIOOOOIOOIIIIOOO source: ; load RWB from TB (JAMS CLEAR AND PRESET) source: 1 00 changed: 1 step 66 100000000000010010000000000000000000110111011011011010100111110111 fail ^^ ^^^^ ^^ ^^ SLOT BAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBAABBAAAAAAAAAAAAAABBBBBABBBB LETTER ALPSLFMDEEMCBFRSPKLEMFHRSCJLJKUHPNMBBNNVVRKRHUTDJUKANJHBTPDFSVEVDU SIDE 121212122121212121111111112212122222112222111221112112212112212122 DIRECTION IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIOOOOOOOIOOIOOIOOIOOOOIOOIIIIOOO source: 0 changed: 0 step 67 100000000000010010000000000000000000110111011011011010100110110111 fail ^^ ^^^^ ^^ ^^ SLOT BAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBAABBAAAAAAAAAAAAAABBBBBABBBB LETTER ALPSLFMDEEMCBFRSPKLEMFHRSCJLJKUHPNMBBNNVVRKRHUTDJUKANJHBTPDFSVEVDU SIDE 121212122121212121111111112212122222112222111221112112212112212122 DIRECTION IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIOOOOOOOIOOIOOIOOIOOOOIOOIIIIOOO source: source: source: source: source: source: source: source: source: source: source: source: source: source: source: ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; source: ; source: ; test AND-NOR logic source: ; source: ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; source: source: ; (all registers are HIGH) source: ; set all pins HIGH except ENABLES source: source: ; set pin AF2 HIGH source: 1 changed: 1 step 68 100001000000010010000000000000000000110111011011011010100110110111 fail ^^ ^^^^ ^^ ^^ SLOT BAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBAABBAAAAAAAAAAAAAABBBBBABBBB LETTER ALPSLFMDEEMCBFRSPKLEMFHRSCJLJKUHPNMBBNNVVRKRHUTDJUKANJHBTPDFSVEVDU SIDE 121212122121212121111111112212122222112222111221112112212112212122 DIRECTION IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIOOOOOOOIOOIOOIOOIOOOOIOOIIIIOOO source: ; set pin AM1 HIGH source: 1 changed: 1 step 69 100001100000010010000000000000000000110111011011011010100110110111 fail ^^ ^^^^ ^^ ^^ SLOT BAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBAABBAAAAAAAAAAAAAABBBBBABBBB LETTER ALPSLFMDEEMCBFRSPKLEMFHRSCJLJKUHPNMBBNNVVRKRHUTDJUKANJHBTPDFSVEVDU SIDE 121212122121212121111111112212122222112222111221112112212112212122 DIRECTION IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIOOOOOOOIOOIOOIOOIOOOOIOOIIIIOOO source: ; set pin AE1 HIGH source: 1 changed: 1 step 70 100001100100010010000000000000000000110111011011011010100110110111 fail ^^ ^^^^ ^^ ^^ SLOT BAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBAABBAAAAAAAAAAAAAABBBBBABBBB LETTER ALPSLFMDEEMCBFRSPKLEMFHRSCJLJKUHPNMBBNNVVRKRHUTDJUKANJHBTPDFSVEVDU SIDE 121212122121212121111111112212122222112222111221112112212112212122 DIRECTION IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIOOOOOOOIOOIOOIOOIOOOOIOOIIIIOOO source: ; set pin AM2 HIGH source: 1 changed: 1 step 71 100001100110010010000000000000000000110111011011011010100110110111 fail ^^ ^^^^ ^^ ^^ SLOT BAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBAABBAAAAAAAAAAAAAABBBBBABBBB LETTER ALPSLFMDEEMCBFRSPKLEMFHRSCJLJKUHPNMBBNNVVRKRHUTDJUKANJHBTPDFSVEVDU SIDE 121212122121212121111111112212122222112222111221112112212112212122 DIRECTION IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIOOOOOOOIOOIOOIOOIOOOOIOOIIIIOOO source: ; set pin AB2 HIGH source: 1 changed: 1 step 72 100001100110110010000000000000000000110111011011011010100110110111 fail ^^ ^^^^ ^^ ^^ SLOT BAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBAABBAAAAAAAAAAAAAABBBBBABBBB LETTER ALPSLFMDEEMCBFRSPKLEMFHRSCJLJKUHPNMBBNNVVRKRHUTDJUKANJHBTPDFSVEVDU SIDE 121212122121212121111111112212122222112222111221112112212112212122 DIRECTION IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIOOOOOOOIOOIOOIOOIOOOOIOOIIIIOOO source: ; set pin AS1 HIGH source: 1 changed: 1 step 73 100001100110110110000000000000000000110111011011011010100110110111 fail ^^ ^^^^ ^^ ^^ SLOT BAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBAABBAAAAAAAAAAAAAABBBBBABBBB LETTER ALPSLFMDEEMCBFRSPKLEMFHRSCJLJKUHPNMBBNNVVRKRHUTDJUKANJHBTPDFSVEVDU SIDE 121212122121212121111111112212122222112222111221112112212112212122 DIRECTION IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIOOOOOOOIOOIOOIOOIOOOOIOOIIIIOOO source: ; set pin BE1 HIGH source: 1 changed: 1 step 74 100001100110110110010000000000000000110111011011011010100110110111 fail ^^ ^^^^ ^^ ^^ SLOT BAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBAABBAAAAAAAAAAAAAABBBBBABBBB LETTER ALPSLFMDEEMCBFRSPKLEMFHRSCJLJKUHPNMBBNNVVRKRHUTDJUKANJHBTPDFSVEVDU SIDE 121212122121212121111111112212122222112222111221112112212112212122 DIRECTION IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIOOOOOOOIOOIOOIOOIOOOOIOOIIIIOOO source: ; set pin BM1 HIGH source: 1 changed: 1 step 75 100001100110110110011000000000000000110111011011011010100110110111 fail ^^ ^^^^ ^^ ^^ SLOT BAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBAABBAAAAAAAAAAAAAABBBBBABBBB LETTER ALPSLFMDEEMCBFRSPKLEMFHRSCJLJKUHPNMBBNNVVRKRHUTDJUKANJHBTPDFSVEVDU SIDE 121212122121212121111111112212122222112222111221112112212112212122 DIRECTION IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIOOOOOOOIOOIOOIOOIOOOOIOOIIIIOOO source: ; set pin BH1 HIGH source: 1 changed: 1 step 76 100001100110110110011010000000000000110111011011011010100110110111 fail ^^ ^^^^ ^^ ^^ SLOT BAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBAABBAAAAAAAAAAAAAABBBBBABBBB LETTER ALPSLFMDEEMCBFRSPKLEMFHRSCJLJKUHPNMBBNNVVRKRHUTDJUKANJHBTPDFSVEVDU SIDE 121212122121212121111111112212122222112222111221112112212112212122 DIRECTION IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIOOOOOOOIOOIOOIOOIOOOOIOOIIIIOOO source: ; set pin BR1 HIGH source: 1 changed: 1 step 77 100001100110110110011011000000000000110111011011011010100110110111 fail ^^ ^^^^ ^^ ^^ SLOT BAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBAABBAAAAAAAAAAAAAABBBBBABBBB LETTER ALPSLFMDEEMCBFRSPKLEMFHRSCJLJKUHPNMBBNNVVRKRHUTDJUKANJHBTPDFSVEVDU SIDE 121212122121212121111111112212122222112222111221112112212112212122 DIRECTION IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIOOOOOOOIOOIOOIOOIOOOOIOOIIIIOOO source: ; set pin BC1 HIGH source: 1 changed: 1 step 78 100001100110110110011011010000000000110111011011011010100110110111 fail ^^ ^^^^ ^^ ^^ SLOT BAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBAABBAAAAAAAAAAAAAABBBBBABBBB LETTER ALPSLFMDEEMCBFRSPKLEMFHRSCJLJKUHPNMBBNNVVRKRHUTDJUKANJHBTPDFSVEVDU SIDE 121212122121212121111111112212122222112222111221112112212112212122 DIRECTION IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIOOOOOOOIOOIOOIOOIOOOOIOOIIIIOOO source: ; set pin BJ2 HIGH source: 1 changed: 1 step 79 100001100110110110011011011000000000110111011011011010100110110111 fail ^^ ^^^^ ^^ ^^ SLOT BAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBAABBAAAAAAAAAAAAAABBBBBABBBB LETTER ALPSLFMDEEMCBFRSPKLEMFHRSCJLJKUHPNMBBNNVVRKRHUTDJUKANJHBTPDFSVEVDU SIDE 121212122121212121111111112212122222112222111221112112212112212122 DIRECTION IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIOOOOOOOIOOIOOIOOIOOOOIOOIIIIOOO source: ; set pin BJ1 HIGH source: 1 changed: 1 step 80 100001100110110110011011011010000000110111011011011010100110110111 fail ^^ ^^^^ ^^ ^^ SLOT BAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBAABBAAAAAAAAAAAAAABBBBBABBBB LETTER ALPSLFMDEEMCBFRSPKLEMFHRSCJLJKUHPNMBBNNVVRKRHUTDJUKANJHBTPDFSVEVDU SIDE 121212122121212121111111112212122222112222111221112112212112212122 DIRECTION IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIOOOOOOOIOOIOOIOOIOOOOIOOIIIIOOO source: ; set pin BK2 HIGH source: 1 changed: 1 step 81 100001100110110110011011011011000000110111011011011010100110110111 fail ^^ ^^^^ ^^ ^^ SLOT BAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBAABBAAAAAAAAAAAAAABBBBBABBBB LETTER ALPSLFMDEEMCBFRSPKLEMFHRSCJLJKUHPNMBBNNVVRKRHUTDJUKANJHBTPDFSVEVDU SIDE 121212122121212121111111112212122222112222111221112112212112212122 DIRECTION IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIOOOOOOOIOOIOOIOOIOOOOIOOIIIIOOO source: ; set pin BH2 HIGH source: 1 changed: 1 step 82 100001100110110110011011011011010000110111011011011010100110110111 fail ^^ ^^^^ ^^ ^^ SLOT BAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBAABBAAAAAAAAAAAAAABBBBBABBBB LETTER ALPSLFMDEEMCBFRSPKLEMFHRSCJLJKUHPNMBBNNVVRKRHUTDJUKANJHBTPDFSVEVDU SIDE 121212122121212121111111112212122222112222111221112112212112212122 DIRECTION IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIOOOOOOOIOOIOOIOOIOOOOIOOIIIIOOO source: ; set pin BP2 HIGH source: 1 changed: 1 step 83 100001100110110110011011011011011000110111011011011010100110110111 fail ^^ ^^^^ ^^ ^^ SLOT BAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBAABBAAAAAAAAAAAAAABBBBBABBBB LETTER ALPSLFMDEEMCBFRSPKLEMFHRSCJLJKUHPNMBBNNVVRKRHUTDJUKANJHBTPDFSVEVDU SIDE 121212122121212121111111112212122222112222111221112112212112212122 DIRECTION IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIOOOOOOOIOOIOOIOOIOOOOIOOIIIIOOO source: ; set pin BN2 HIGH source: 1 changed: 1 step 84 100001100110110110011011011011011100110111011011011010100110110111 fail ^^ ^^^^ ^^ ^^ SLOT BAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBAABBAAAAAAAAAAAAAABBBBBABBBB LETTER ALPSLFMDEEMCBFRSPKLEMFHRSCJLJKUHPNMBBNNVVRKRHUTDJUKANJHBTPDFSVEVDU SIDE 121212122121212121111111112212122222112222111221112112212112212122 DIRECTION IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIOOOOOOOIOOIOOIOOIOOOOIOOIIIIOOO source: ; toggle each ENABLE source: source: ; set pin AL2 to clear pin BB2 and pin AN2 AND-NOR OUTPUTS and set TAPE BUS 2 OUTPUT and TAPE BUS 3 OUTPUT source: 1 0 0 11 changed: 1 step 85 110001100110110110011011011011011100110111011011011010100110110111 fail ^^ ^^^^ ^^ ^^ SLOT BAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBAABBAAAAAAAAAAAAAABBBBBABBBB LETTER ALPSLFMDEEMCBFRSPKLEMFHRSCJLJKUHPNMBBNNVVRKRHUTDJUKANJHBTPDFSVEVDU SIDE 121212122121212121111111112212122222112222111221112112212112212122 DIRECTION IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIOOOOOOOIOOIOOIOOIOOOOIOOIIIIOOO source: 0 1 1 00 changed: 0 step 86 100001100110110110011011011011011100110111011011011010100110110111 fail ^ ^ ^^ ^^ ^^^^ ^^ ^^ SLOT BAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBAABBAAAAAAAAAAAAAABBBBBABBBB LETTER ALPSLFMDEEMCBFRSPKLEMFHRSCJLJKUHPNMBBNNVVRKRHUTDJUKANJHBTPDFSVEVDU SIDE 121212122121212121111111112212122222112222111221112112212112212122 DIRECTION IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIOOOOOOOIOOIOOIOOIOOOOIOOIIIIOOO source: ; set pin AP1 to clear pin BB2 and pin AN2 AND-NOR OUTPUTS and set TAPE BUS 2 OUTPUT and TAPE BUS 3 OUTPUT source: 1 0 0 11 changed: 1 step 87 101001100110110110011011011011011100110111011011011010100110110111 fail ^^ ^^^^ ^^ ^^ SLOT BAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBAABBAAAAAAAAAAAAAABBBBBABBBB LETTER ALPSLFMDEEMCBFRSPKLEMFHRSCJLJKUHPNMBBNNVVRKRHUTDJUKANJHBTPDFSVEVDU SIDE 121212122121212121111111112212122222112222111221112112212112212122 DIRECTION IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIOOOOOOOIOOIOOIOOIOOOOIOOIIIIOOO source: 0 1 1 00 changed: 0 step 88 100001100110110110011011011011011100110111011011011010100110110111 fail ^ ^ ^^ ^^ ^^^^ ^^ ^^ SLOT BAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBAABBAAAAAAAAAAAAAABBBBBABBBB LETTER ALPSLFMDEEMCBFRSPKLEMFHRSCJLJKUHPNMBBNNVVRKRHUTDJUKANJHBTPDFSVEVDU SIDE 121212122121212121111111112212122222112222111221112112212112212122 DIRECTION IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIOOOOOOOIOOIOOIOOIOOOOIOOIIIIOOO source: ; set pin AS2 to clear pin BB2 and pin AN2 AND-NOR OUTPUTS and set TAPE BUS 2 OUTPUT and TAPE BUS 3 OUTPUT source: 1 0 0 11 changed: 1 step 89 100101100110110110011011011011011100110111011011011010100110110111 fail ^^ ^^^^ ^^ ^^ SLOT BAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBAABBAAAAAAAAAAAAAABBBBBABBBB LETTER ALPSLFMDEEMCBFRSPKLEMFHRSCJLJKUHPNMBBNNVVRKRHUTDJUKANJHBTPDFSVEVDU SIDE 121212122121212121111111112212122222112222111221112112212112212122 DIRECTION IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIOOOOOOOIOOIOOIOOIOOOOIOOIIIIOOO source: 0 1 1 00 changed: 0 step 90 100001100110110110011011011011011100110111011011011010100110110111 fail ^ ^ ^^ ^^ ^^^^ ^^ ^^ SLOT BAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBAABBAAAAAAAAAAAAAABBBBBABBBB LETTER ALPSLFMDEEMCBFRSPKLEMFHRSCJLJKUHPNMBBNNVVRKRHUTDJUKANJHBTPDFSVEVDU SIDE 121212122121212121111111112212122222112222111221112112212112212122 DIRECTION IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIOOOOOOOIOOIOOIOOIOOOOIOOIIIIOOO source: ; set pin AL1 to clear pin BB2 and pin AN2 AND-NOR OUTPUTS and set TAPE BUS 2 OUTPUT and TAPE BUS 3 OUTPUT source: 1 0 0 11 changed: 1 step 91 100011100110110110011011011011011100110111011011011010100110110111 fail ^^ ^^^^ ^^ ^^ SLOT BAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBAABBAAAAAAAAAAAAAABBBBBABBBB LETTER ALPSLFMDEEMCBFRSPKLEMFHRSCJLJKUHPNMBBNNVVRKRHUTDJUKANJHBTPDFSVEVDU SIDE 121212122121212121111111112212122222112222111221112112212112212122 DIRECTION IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIOOOOOOOIOOIOOIOOIOOOOIOOIIIIOOO source: 0 1 1 00 changed: 0 step 92 100001100110110110011011011011011100110111011011011010100110110111 fail ^ ^ ^^ ^^ ^^^^ ^^ ^^ SLOT BAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBAABBAAAAAAAAAAAAAABBBBBABBBB LETTER ALPSLFMDEEMCBFRSPKLEMFHRSCJLJKUHPNMBBNNVVRKRHUTDJUKANJHBTPDFSVEVDU SIDE 121212122121212121111111112212122222112222111221112112212112212122 DIRECTION IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIOOOOOOOIOOIOOIOOIOOOOIOOIIIIOOO source: ; set pin AL1 to clear pin BB2 and pin AN2 AND-NOR OUTPUTS and set TAPE BUS 2 OUTPUT and TAPE BUS 3 OUTPUT source: 1 0 0 11 changed: 1 step 93 100001110110110110011011011011011100110111011011011010100110110111 fail ^^ ^^^^ ^^ ^^ SLOT BAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBAABBAAAAAAAAAAAAAABBBBBABBBB LETTER ALPSLFMDEEMCBFRSPKLEMFHRSCJLJKUHPNMBBNNVVRKRHUTDJUKANJHBTPDFSVEVDU SIDE 121212122121212121111111112212122222112222111221112112212112212122 DIRECTION IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIOOOOOOOIOOIOOIOOIOOOOIOOIIIIOOO source: 0 1 1 00 changed: 0 step 94 100001100110110110011011011011011100110111011011011010100110110111 fail ^ ^ ^^ ^^ ^^^^ ^^ ^^ SLOT BAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBAABBAAAAAAAAAAAAAABBBBBABBBB LETTER ALPSLFMDEEMCBFRSPKLEMFHRSCJLJKUHPNMBBNNVVRKRHUTDJUKANJHBTPDFSVEVDU SIDE 121212122121212121111111112212122222112222111221112112212112212122 DIRECTION IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIOOOOOOOIOOIOOIOOIOOOOIOOIIIIOOO source: ; set pin AE2 to clear pin BB2 and pin AN2 AND-NOR OUTPUTS and set TAPE BUS 2 OUTPUT and TAPE BUS 3 OUTPUT source: 1 0 0 11 changed: 1 step 95 100001101110110110011011011011011100110111011011011010100110110111 fail ^^ ^^^^ ^^ ^^ SLOT BAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBAABBAAAAAAAAAAAAAABBBBBABBBB LETTER ALPSLFMDEEMCBFRSPKLEMFHRSCJLJKUHPNMBBNNVVRKRHUTDJUKANJHBTPDFSVEVDU SIDE 121212122121212121111111112212122222112222111221112112212112212122 DIRECTION IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIOOOOOOOIOOIOOIOOIOOOOIOOIIIIOOO source: 0 1 1 00 changed: 0 step 96 100001100110110110011011011011011100110111011011011010100110110111 fail ^ ^ ^^ ^^ ^^^^ ^^ ^^ SLOT BAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBAABBAAAAAAAAAAAAAABBBBBABBBB LETTER ALPSLFMDEEMCBFRSPKLEMFHRSCJLJKUHPNMBBNNVVRKRHUTDJUKANJHBTPDFSVEVDU SIDE 121212122121212121111111112212122222112222111221112112212112212122 DIRECTION IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIOOOOOOOIOOIOOIOOIOOOOIOOIIIIOOO source: ; set pin AC1 to clear pin BB2 and set TAPE BUS 3 OUTPUT source: 1 0 1 changed: 1 step 97 100001100111110110011011011011011100110111011011011010100110110111 fail ^ ^ ^^ ^^^^ ^^ ^^ SLOT BAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBAABBAAAAAAAAAAAAAABBBBBABBBB LETTER ALPSLFMDEEMCBFRSPKLEMFHRSCJLJKUHPNMBBNNVVRKRHUTDJUKANJHBTPDFSVEVDU SIDE 121212122121212121111111112212122222112222111221112112212112212122 DIRECTION IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIOOOOOOOIOOIOOIOOIOOOOIOOIIIIOOO source: 0 1 0 changed: 0 step 98 100001100110110110011011011011011100110111011011011010100110110111 fail ^ ^ ^^ ^^ ^^^^ ^^ ^^ SLOT BAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBAABBAAAAAAAAAAAAAABBBBBABBBB LETTER ALPSLFMDEEMCBFRSPKLEMFHRSCJLJKUHPNMBBNNVVRKRHUTDJUKANJHBTPDFSVEVDU SIDE 121212122121212121111111112212122222112222111221112112212112212122 DIRECTION IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIOOOOOOOIOOIOOIOOIOOOOIOOIIIIOOO source: ; set pin AF1 to clear pin BB2 and set TAPE BUS 3 OUTPUT source: 1 0 1 changed: step 99 100001100110110110011011011011011100110111011011011010100110110111 fail ^ ^ ^^ ^^^^ ^^ ^^ SLOT BAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBAABBAAAAAAAAAAAAAABBBBBABBBB LETTER ALPSLFMDEEMCBFRSPKLEMFHRSCJLJKUHPNMBBNNVVRKRHUTDJUKANJHBTPDFSVEVDU SIDE 121212122121212121111111112212122222112222111221112112212112212122 DIRECTION IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIOOOOOOOIOOIOOIOOIOOOOIOOIIIIOOO source: 0 1 0 changed: 0 1 0 step 100 100001100110100110011011011011011101110110011011011010100110110111 fail ^ ^ ^^ ^^^^ ^^ ^^ SLOT BAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBAABBAAAAAAAAAAAAAABBBBBABBBB LETTER ALPSLFMDEEMCBFRSPKLEMFHRSCJLJKUHPNMBBNNVVRKRHUTDJUKANJHBTPDFSVEVDU SIDE 121212122121212121111111112212122222112222111221112112212112212122 DIRECTION IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIOOOOOOOIOOIOOIOOIOOOOIOOIIIIOOO source: ; set pin AR2 to clear pin AN2 AND-NOR OUTPUTS and set TAPE BUS 2 OUTPUT source: 1 0 1 changed: 1 step 101 100001100110101110011011011011011101110110011011011010100110110111 fail ^^ ^^^^ ^^ ^^ SLOT BAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBAABBAAAAAAAAAAAAAABBBBBABBBB LETTER ALPSLFMDEEMCBFRSPKLEMFHRSCJLJKUHPNMBBNNVVRKRHUTDJUKANJHBTPDFSVEVDU SIDE 121212122121212121111111112212122222112222111221112112212112212122 DIRECTION IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIOOOOOOOIOOIOOIOOIOOOOIOOIIIIOOO source: 0 1 0 changed: 0 step 102 100001100110100110011011011011011101110110011011011010100110110111 fail ^ ^ ^^ ^^^^ ^^ ^^ SLOT BAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBAABBAAAAAAAAAAAAAABBBBBABBBB LETTER ALPSLFMDEEMCBFRSPKLEMFHRSCJLJKUHPNMBBNNVVRKRHUTDJUKANJHBTPDFSVEVDU SIDE 121212122121212121111111112212122222112222111221112112212112212122 DIRECTION IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIOOOOOOOIOOIOOIOOIOOOOIOOIIIIOOO source: ; set pin AP2 to clear pin AN2 AND-NOR OUTPUTS and set TAPE BUS 2 OUTPUT source: 1 0 1 changed: step 103 100001100110100110011011011011011101110110011011011010100110110111 fail ^^ ^^^^ ^^ ^^ SLOT BAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBAABBAAAAAAAAAAAAAABBBBBABBBB LETTER ALPSLFMDEEMCBFRSPKLEMFHRSCJLJKUHPNMBBNNVVRKRHUTDJUKANJHBTPDFSVEVDU SIDE 121212122121212121111111112212122222112222111221112112212112212122 DIRECTION IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIOOOOOOOIOOIOOIOOIOOOOIOOIIIIOOO source: 0 1 0 changed: 0 1 0 step 104 100001100110100100011011011011011101111100011011011010100110110111 fail ^^ ^^^^ ^^ ^^ SLOT BAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBAABBAAAAAAAAAAAAAABBBBBABBBB LETTER ALPSLFMDEEMCBFRSPKLEMFHRSCJLJKUHPNMBBNNVVRKRHUTDJUKANJHBTPDFSVEVDU SIDE 121212122121212121111111112212122222112222111221112112212112212122 DIRECTION IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIOOOOOOOIOOIOOIOOIOOOOIOOIIIIOOO source: source: ; set pin BK1 to clear pin BB1 and pin BN1 AND-NOR OUTPUTS and set TAPE BUS 2 OUTPUT and TAPE BUS 3 OUTPUT source: 1 00 11 changed: 1 00 11 step 105 100001100110100101011011011011011101001111011011011010100110110111 fail ^^ ^^^^ ^^ ^^ SLOT BAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBAABBAAAAAAAAAAAAAABBBBBABBBB LETTER ALPSLFMDEEMCBFRSPKLEMFHRSCJLJKUHPNMBBNNVVRKRHUTDJUKANJHBTPDFSVEVDU SIDE 121212122121212121111111112212122222112222111221112112212112212122 DIRECTION IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIOOOOOOOIOOIOOIOOIOOOOIOOIIIIOOO source: 0 11 00 changed: 0 11 00 step 106 100001100110100100011011011011011101111100011011011010100110110111 fail ^^ ^^^^ ^^ ^^ SLOT BAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBAABBAAAAAAAAAAAAAABBBBBABBBB LETTER ALPSLFMDEEMCBFRSPKLEMFHRSCJLJKUHPNMBBNNVVRKRHUTDJUKANJHBTPDFSVEVDU SIDE 121212122121212121111111112212122222112222111221112112212112212122 DIRECTION IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIOOOOOOOIOOIOOIOOIOOOOIOOIIIIOOO source: ; set pin BL1 to clear pin BB1 and pin BN1 AND-NOR OUTPUTS and set TAPE BUS 2 OUTPUT and TAPE BUS 3 OUTPUT source: 1 00 11 changed: 1 00 11 step 107 100001100110100100111011011011011101001111011011011010100110110111 fail ^^ ^^^^ ^^ ^^ SLOT BAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBAABBAAAAAAAAAAAAAABBBBBABBBB LETTER ALPSLFMDEEMCBFRSPKLEMFHRSCJLJKUHPNMBBNNVVRKRHUTDJUKANJHBTPDFSVEVDU SIDE 121212122121212121111111112212122222112222111221112112212112212122 DIRECTION IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIOOOOOOOIOOIOOIOOIOOOOIOOIIIIOOO source: 0 11 00 changed: 0 11 00 step 108 100001100110100100011011011011011101111100011011011010100110110111 fail ^^ ^^^^ ^^ ^^ SLOT BAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBAABBAAAAAAAAAAAAAABBBBBABBBB LETTER ALPSLFMDEEMCBFRSPKLEMFHRSCJLJKUHPNMBBNNVVRKRHUTDJUKANJHBTPDFSVEVDU SIDE 121212122121212121111111112212122222112222111221112112212112212122 DIRECTION IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIOOOOOOOIOOIOOIOOIOOOOIOOIIIIOOO source: ; set pin BF1 to clear pin BB1 and pin BN1 AND-NOR OUTPUTS and set TAPE BUS 2 OUTPUT and TAPE BUS 3 OUTPUT source: 1 00 11 changed: 1 00 11 step 109 100001100110100100011111011011011101001111011011011010100110110111 fail ^^ ^^^^ ^^ ^^ SLOT BAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBAABBAAAAAAAAAAAAAABBBBBABBBB LETTER ALPSLFMDEEMCBFRSPKLEMFHRSCJLJKUHPNMBBNNVVRKRHUTDJUKANJHBTPDFSVEVDU SIDE 121212122121212121111111112212122222112222111221112112212112212122 DIRECTION IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIOOOOOOOIOOIOOIOOIOOOOIOOIIIIOOO source: 0 11 00 changed: 0 11 00 step 110 100001100110100100011011011011011101111100011011011010100110110111 fail ^^ ^^^^ ^^ ^^ SLOT BAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBAABBAAAAAAAAAAAAAABBBBBABBBB LETTER ALPSLFMDEEMCBFRSPKLEMFHRSCJLJKUHPNMBBNNVVRKRHUTDJUKANJHBTPDFSVEVDU SIDE 121212122121212121111111112212122222112222111221112112212112212122 DIRECTION IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIOOOOOOOIOOIOOIOOIOOOOIOOIIIIOOO source: ; set pin BS1 to clear pin BB1 and pin BN1 AND-NOR OUTPUTS and set TAPE BUS 2 OUTPUT and TAPE BUS 3 OUTPUT source: 1 00 11 changed: 1 00 11 step 111 100001100110100100011011111011011101001111011011011010100110110111 fail ^^ ^^^^ ^^ ^^ SLOT BAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBAABBAAAAAAAAAAAAAABBBBBABBBB LETTER ALPSLFMDEEMCBFRSPKLEMFHRSCJLJKUHPNMBBNNVVRKRHUTDJUKANJHBTPDFSVEVDU SIDE 121212122121212121111111112212122222112222111221112112212112212122 DIRECTION IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIOOOOOOOIOOIOOIOOIOOOOIOOIIIIOOO source: 0 11 00 changed: 0 11 00 step 112 100001100110100100011011011011011101111100011011011010100110110111 fail ^^ ^^^^ ^^ ^^ SLOT BAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBAABBAAAAAAAAAAAAAABBBBBABBBB LETTER ALPSLFMDEEMCBFRSPKLEMFHRSCJLJKUHPNMBBNNVVRKRHUTDJUKANJHBTPDFSVEVDU SIDE 121212122121212121111111112212122222112222111221112112212112212122 DIRECTION IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIOOOOOOOIOOIOOIOOIOOOOIOOIIIIOOO source: ; set pin BL2 to clear pin BB1 and pin BN1 AND-NOR OUTPUTS and set TAPE BUS 2 OUTPUT and TAPE BUS 3 OUTPUT source: 1 00 11 changed: 1 00 11 step 113 100001100110100100011011011111011101001111011011011010100110110111 fail ^^ ^^^^ ^^ ^^ SLOT BAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBAABBAAAAAAAAAAAAAABBBBBABBBB LETTER ALPSLFMDEEMCBFRSPKLEMFHRSCJLJKUHPNMBBNNVVRKRHUTDJUKANJHBTPDFSVEVDU SIDE 121212122121212121111111112212122222112222111221112112212112212122 DIRECTION IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIOOOOOOOIOOIOOIOOIOOOOIOOIIIIOOO source: 0 11 00 changed: 0 11 00 step 114 100001100110100100011011011011011101111100011011011010100110110111 fail ^^ ^^^^ ^^ ^^ SLOT BAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBAABBAAAAAAAAAAAAAABBBBBABBBB LETTER ALPSLFMDEEMCBFRSPKLEMFHRSCJLJKUHPNMBBNNVVRKRHUTDJUKANJHBTPDFSVEVDU SIDE 121212122121212121111111112212122222112222111221112112212112212122 DIRECTION IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIOOOOOOOIOOIOOIOOIOOOOIOOIIIIOOO source: ; set pin BU1 to clear pin BB1 and pin BN1 AND-NOR OUTPUTS and set TAPE BUS 2 OUTPUT and TAPE BUS 3 OUTPUT source: 1 00 11 changed: 1 00 11 step 115 100001100110100100011011011011111101001111011011011010100110110111 fail ^^ ^^^^ ^^ ^^ SLOT BAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBAABBAAAAAAAAAAAAAABBBBBABBBB LETTER ALPSLFMDEEMCBFRSPKLEMFHRSCJLJKUHPNMBBNNVVRKRHUTDJUKANJHBTPDFSVEVDU SIDE 121212122121212121111111112212122222112222111221112112212112212122 DIRECTION IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIOOOOOOOIOOIOOIOOIOOOOIOOIIIIOOO source: 0 11 00 changed: 0 11 00 step 116 100001100110100100011011011011011101111100011011011010100110110111 fail ^^ ^^^^ ^^ ^^ SLOT BAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBAABBAAAAAAAAAAAAAABBBBBABBBB LETTER ALPSLFMDEEMCBFRSPKLEMFHRSCJLJKUHPNMBBNNVVRKRHUTDJUKANJHBTPDFSVEVDU SIDE 121212122121212121111111112212122222112222111221112112212112212122 DIRECTION IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIOOOOOOOIOOIOOIOOIOOOOIOOIIIIOOO source: ; set pin BM2 to clear pin BB1 and TAPE BUS 3 OUTPUT source: 1 0 1 changed: 1 0 1 step 117 100001100110100100011011011011011111101110011011011010100110110111 fail ^^ ^^^^ ^^ ^^ SLOT BAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBAABBAAAAAAAAAAAAAABBBBBABBBB LETTER ALPSLFMDEEMCBFRSPKLEMFHRSCJLJKUHPNMBBNNVVRKRHUTDJUKANJHBTPDFSVEVDU SIDE 121212122121212121111111112212122222112222111221112112212112212122 DIRECTION IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIOOOOOOOIOOIOOIOOIOOOOIOOIIIIOOO source: 0 1 0 changed: 0 1 0 step 118 100001100110100100011011011011011101111100011011011010100110110111 fail ^^ ^^^^ ^^ ^^ source: ; no change source: 100000000000000000000000000000000001111100011011011010100110110111 changed: 00 00 0 0 00 00 00 00 000 step 119 100000000000000000000000000000000001111100011011011010100110110111 source: source: ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; source: ; test shifting the RWB source: ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; source: source: ; shift in 0, expect 10 source: 0 changed: 0 step 120 100000000000000000000000000000000001111100011011011010100110100111 source: 110 changed: 1 0 step 121 100000000000000000000000000000000001111100011011011010100110101101 source: 0 changed: 0 step 122 100000000000000000000000000000000001111100011011011010100110100101 source: ; toggle phase should toggle RWB 2 source: 0 0 changed: 0 0 step 123 100000000000000000000000000000000001111100011011011010100110000001 source: 1 1 changed: 1 1 step 124 100000000000000000000000000000000001111100011011011010100110100101 source: source: ; shift in 0, expect 00 source: 0 changed: step 125 100000000000000000000000000000000001111100011011011010100110100101 source: 100 changed: 10 step 126 100000000000000000000000000000000001111100011011011010100110101001 source: 0 changed: 0 step 127 100000000000000000000000000000000001111100011011011010100110100001 source: ; toggle phase should toggle RWB 2 source: 0 1 changed: 0 1 step 128 100000000000000000000000000000000001111100011011011010100110000101 source: 1 0 changed: 1 0 step 129 100000000000000000000000000000000001111100011011011010100110100001 source: source: ; shift in 0, expect 00 source: 0 changed: step 130 100000000000000000000000000000000001111100011011011010100110100001 source: 100 changed: 1 step 131 100000000000000000000000000000000001111100011011011010100110101001 source: 0 changed: 0 step 132 100000000000000000000000000000000001111100011011011010100110100001 source: ; shift in 1, expect 01 source: 1 changed: 1 step 133 100000000000000000000000000000000001111100011011011010100110110001 source: 101 changed: 1 1 step 134 100000000000000000000000000000000001111100011011011010100110111011 source: 0 changed: 0 step 135 100000000000000000000000000000000001111100011011011010100110110011 source: ; shift in 1, expect 11 source: 1 changed: step 136 100000000000000000000000000000000001111100011011011010100110110011 source: 111 changed: 11 step 137 100000000000000000000000000000000001111100011011011010100110111111 source: 0 changed: 0 step 138 100000000000000000000000000000000001111100011011011010100110110111 source: ; shift in 1, expect 11 source: 1 changed: step 139 100000000000000000000000000000000001111100011011011010100110110111 source: 111 changed: 1 step 140 100000000000000000000000000000000001111100011011011010100110111111 source: 0 changed: 0 step 141 100000000000000000000000000000000001111100011011011010100110110111 source: ; shift in 0, expect 10 source: 0 changed: 0 step 142 100000000000000000000000000000000001111100011011011010100110100111 source: 110 changed: 1 0 step 143 100000000000000000000000000000000001111100011011011010100110101101 source: 0 changed: 0 step 144 100000000000000000000000000000000001111100011011011010100110100101 source: ; shift in 1, expect 01 source: 1 changed: 1 step 145 100000000000000000000000000000000001111100011011011010100110110101 source: 101 changed: 101 step 146 100000000000000000000000000000000001111100011011011010100110111011 source: 0 changed: 0 step 147 100000000000000000000000000000000001111100011011011010100110110011 source: ; shift in 0, expect 10 source: 0 changed: 0 step 148 100000000000000000000000000000000001111100011011011010100110100011 source: 110 changed: 110 step 149 100000000000000000000000000000000001111100011011011010100110101101 source: 0 changed: 0 step 150 100000000000000000000000000000000001111100011011011010100110100101 source: ; shift in 1, expect 01 source: 1 changed: 1 step 151 100000000000000000000000000000000001111100011011011010100110110101 source: 101 changed: 101 step 152 100000000000000000000000000000000001111100011011011010100110111011 source: 0 changed: 0 step 153 100000000000000000000000000000000001111100011011011010100110110011 source: ; shift in 1, expect 11 source: 1 changed: step 154 100000000000000000000000000000000001111100011011011010100110110011 source: 111 changed: 11 step 155 100000000000000000000000000000000001111100011011011010100110111111 source: 0 changed: 0 step 156 100000000000000000000000000000000001111100011011011010100110110111 source: ; no change source: 100000000000000000000000000000000001111100011011011010100110110111 changed: step 157 100000000000000000000000000000000001111100011011011010100110110111 test 2: *** FAIL *************************** 65 steps failed SLOT BAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBAABBAAAAAAAAAAAAAABBBBBABBBB LETTER ALPSLFMDEEMCBFRSPKLEMFHRSCJLJKUHPNMBBNNVVRKRHUTDJUKANJHBTPDFSVEVDU SIDE 121212122121212121111111112212122222112222111221112112212112212122 DIRECTION IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIOOOOOOOIOOIOOIOOIOOOOIOOIIIIOOO this fail O O OO OO OOOO OO OO all fails O O OO OO OOOO OO OO was hi 111111111111111111111111111111111111111111111111111111111111111111 rising ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ ^^^^^^^^^^^^^^^^^^^^^^^^^ falling vvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvv vvvvvvvvvvvvvvvvvvvvvvvvv was lo 00000000000000000000000000000000000000 0000000000000000000000000 total fails 2, total passes 0 space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C toggle comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit source: ; all registers are unknown source: ; turn on C0, PHASE source: ; with no ENABLES, BUS2,BUS3 is 11, C2 is 1 source: 1000000000000000000000000000000000011111000XX0XX0XX0XXXX0XX0110XX1 changed: step 1 100000000000000000000000000000000001111100011011011010100110110111 source: source: ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; source: ; source: ; set all registers LOW source: ; source: ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; source: source: ; load TMA SETUP from tape bus (00) source: 100 changed: 100 step 2 100000000000000000000000000000000001111100100011011010100110110111 source: 0 changed: 0 step 3 100000000000000000000000000000000001111100000011011010100110110111 source: ; load TMA from tape bus (00) source: 100 changed: 100 step 4 100000000000000000000000000000000001111100000100011010100110110111 source: 0 changed: 0 step 5 100000000000000000000000000000000001111100000000011010100110110111 source: ; load TBN from tape bus (00) source: 100 changed: 100 step 6 100000000000000000000000000000000001111100000000100010100110110111 source: 0 changed: 0 step 7 100000000000000000000000000000000001111100000000000010100110110111 source: ; load TAC from tape bus (00) source: 10101 changed: 10101 step 8 100000000000000000000000000000000001111100000000000101010110110111 source: 0 changed: 0 step 9 100000000000000000000000000000000001111100000000000001010110110111 source: ; load TB from tape bus (00) source: 100 changed: 100 step 10 100000000000000000000000000000000001111100000000000001011000110111 source: 0 changed: 0 step 11 100000000000000000000000000000000001111100000000000001010000110111 source: ; load RWB from TB (JAMS CLEAR AND PRESET) source: 1 00 changed: 1 00 step 12 100000000000000000000000000000000001111100000000000001010001110001 source: 0 changed: 0 step 13 100000000000000000000000000000000001111100000000000001010000110001 source: ; (no change) source: 100000000000000000000000000000000001111100000000000001010000110001 changed: step 14 100000000000000000000000000000000001111100000000000001010000110001 source: source: source: ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; source: ; source: ; set all registers HIGH source: ; source: ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; source: source: ; set pin AF1 which clears pin BB2 and sets pin BR2 TAPE BUS 3 OUTPUT source: 1 0 1 changed: 1 0 1 step 15 100000000000010000000000000000000000111101000000000001010000110001 source: ; set pin AP2 which clears pin AN2 and sets pin BV2 TAPE BUS 2 OUTPUT source: 1 0 1 changed: 1 0 1 step 16 100000000000010010000000000000000000110111000000000001010000110001 source: source: source: ; load TMA SETUP from tape bus (11) source: 111 changed: 111 step 17 100000000000010010000000000000000000110111111000000001010000110001 source: 0 changed: 0 step 18 100000000000010010000000000000000000110111011000000001010000110001 source: ; load TMA from tape bus (11) source: 111 changed: 111 step 19 100000000000010010000000000000000000110111011111000001010000110001 source: 0 changed: 0 step 20 100000000000010010000000000000000000110111011011000001010000110001 source: ; load TBN from tape bus (11) source: 111 changed: 111 step 21 100000000000010010000000000000000000110111011011111001010000110001 source: 0 changed: 0 step 22 100000000000010010000000000000000000110111011011011001010000110001 source: ; load TAC from tape bus (11) source: 11010 changed: 11010 step 23 100000000000010010000000000000000000110111011011011110100000110001 source: 0 changed: 0 step 24 100000000000010010000000000000000000110111011011011010100000110001 source: ; load TB from tape bus (11) source: 111 changed: 111 step 25 100000000000010010000000000000000000110111011011011010101110110001 source: 0 changed: 0 step 26 100000000000010010000000000000000000110111011011011010100110110001 source: ; load RWB from TB (JAMS CLEAR AND PRESET) source: 1 11 changed: 1 11 step 27 100000000000010010000000000000000000110111011011011010100111110111 source: 0 changed: 0 step 28 100000000000010010000000000000000000110111011011011010100110110111 source: ; clear pin AF1 (AND with itself) to set pin BB2 (AND-NOR output) and clear pin BR2 TAPE BUS 3 OUTPUT source: 0 1 0 changed: 0 1 0 step 29 100000000000000010000000000000000001110110011011011010100110110111 source: ; clear pin AP2 (AND with itself) to set pin AN2 (AND-NOR output) and clear pin BV2 TAPE BUS 2 OUTPUT source: 0 1 0 changed: 0 1 0 step 30 100000000000000000000000000000000001111100011011011010100110110111 source: ; (no change) source: 100000000000000000000000000000000001111100011011011010100110110111 changed: step 31 100000000000000000000000000000000001111100011011011010100110110111 source: source: ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; source: ; source: ; will all registers high, walk a 0 source: ; source: ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; source: source: source: ; walk a 0, TMA SETUP 2 source: source: source: ; clear pin AP2 which sets pin AN2 and clears pin BV2 TAPE BUS 2 OUTPUT source: 0 1 0 changed: step 32 100000000000000000000000000000000001111100011011011010100110110111 source: ; set pin AF1 which clears pin BB2 and sets pin BR2 TAPE BUS 3 OUTPUT source: 1 0 1 changed: 1 0 1 step 33 100000000000010000000000000000000000111101011011011010100110110111 source: ; load TMA SETUP from tape bus (01) source: 101 changed: 10 step 34 100000000000010000000000000000000000111101101011011010100110110111 source: 0 changed: 0 step 35 100000000000010000000000000000000000111101001011011010100110110111 source: ; restore TMA SETUP 2 source: ; set pin AP2 which clears pin AN2 and sets pin BV2 TAPE BUS 2 OUTPUT source: 1 0 1 changed: 1 0 1 step 36 100000000000010010000000000000000000110111001011011010100110110111 source: ; load TMA SETUP from tape bus (11) source: 111 changed: 11 step 37 100000000000010010000000000000000000110111111011011010100110110111 source: 0 changed: 0 step 38 100000000000010010000000000000000000110111011011011010100110110111 source: source: source: ; walk a 0, TMA SETUP 3 source: source: source: ; set pin AP2 which clears pin AN2 and sets pin BV2 TAPE BUS 2 OUTPUT source: 1 0 1 changed: step 39 100000000000010010000000000000000000110111011011011010100110110111 SLOT BAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBAABBAAAAAAAAAAAAAABBBBBABBBB LETTER ALPSLFMDEEMCBFRSPKLEMFHRSCJLJKUHPNMBBNNVVRKRHUTDJUKANJHBTPDFSVEVDU SIDE 121212122121212121111111112212122222112222111221112112212112212122 DIRECTION IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIOOOOOOOIOOIOOIOOIOOOOIOOIIIIOOO source: ; clear pin AF1 which sets pin BB2 and clears pin BR2 TAPE BUS 3 OUTPUT source: 0 0 1 changed: 0 1 0 step 40 100000000000000010000000000000000001110110011011011010100110110111 fail ^ ^ space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C toggle comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT BAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBAABBAAAAAAAAAAAAAABBBBBABBBB LETTER ALPSLFMDEEMCBFRSPKLEMFHRSCJLJKUHPNMBBNNVVRKRHUTDJUKANJHBTPDFSVEVDU SIDE 121212122121212121111111112212122222112222111221112112212112212122 DIRECTION IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIOOOOOOOIOOIOOIOOIOOOOIOOIIIIOOO all fails O O OO OO OOOO OO OO was lo 00000000000000000000000000000000000000 0000000000000000000000000 falling vvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvv vvvvvvvvvvvvvvvvvvvvvvvvv rising ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ ^^^^^^^^^^^^^^^^^^^^^^^^^ was hi 111111111111111111111111111111111111111111111111111111111111111111 total fails 2, total passes 0 Main menu Thu Aug 20 17:56:16 2015 test file is: tests\m222.new delay is: 0 trigger is: 1 1 read test file 2 set test delay 3 set test trigger 4 run test 5 output loading test 8 diags 9 exit Enter test file name? trying to open test file: tests\m222.new reading test file: tests\m222.new comment: M222 PCB REV B SCHEMATIC REV A LINC TAPE REGISTERS comment: comment: TERMINOLOGY- SIGNALS REFER TO PDP12 MAINT VOL4 M222 SCHEMATIC. comment: comment: BUT... comment: comment: DEC USES AND-NOR GATES TO ROUTE THE ADDER A AND B INPUTS, SO... comment: DEC RENAMED THE ADDER TO NEGATIVE LOGIC TERMS (I.E. A-N + B-N + C-N -> SUM-N, C1-N). comment: (NOT THE 7482 DATASHEET NAMES OF A + B + C -> SUM, C1). comment: comment: SO, WITH ALL 'AND ENABLES' LOW, THE AND-NOR OUTPUTS = HIGH. comment: WITH C-L HIGH, THE ADDER OUTPUT IS SUM-N=1, C1-N=1; comment: THE INVERTED ADDER OUTPUT IS LOW (TAPE BUS). comment: AND THERE IS NO CARRY (C1-N IS HI). comment: comment: THE TWO ADDERS, TWO REGISTER BITS, ETC ARE LABELED BIT 2 (EVEN, MSB) AND BIT 3 (ODD, LSB). comment: THE ADDERS ARE REFERRED TO AS 'ADDER2' (MSB) AND 'ADDER3' (LSB). comment: comment: POWER PINS: comment: AA2 +5V comment: AT1 GROUND comment: AC2 GROUND comment: BA2 +5V comment: BT1 GROUND comment: BC2 GROUND comment: comment: (ALL PINS ARE USED). comment: comment: pins: PINS pins: 1 I BA1 CARRY IN-N, (TO E9-5 7482 C0) C-N TO ADDER2 pins: 2 I AL2 AND-NOR ENABLE: TAC TAC3 TO PIN BB2 (TO ADDER3) TAC2 TO PIN AN2 (TO ADDER2) pins: 3 I AP1 AND-NOR ENABLE: TMA SETUP (TMAS)3 TO PIN BB2 (TO ADDER3), (TMAS)3 TO PIN AN2 (TO ADDER2) pins: 4 I AS2 AND-NOR ENABLE: TMA TMA3 TO PIN BB2 (TO ADDER3), TMA2 TO PIN AN2 (TO ADDER2) pins: 5 I AL1 AND-NOR ENABLE: PIN AF2 TO PIN BB2 (TO ADDER3), PIN AM1 TO PIN AN2 (TO ADDER2) pins: 6 I AF2 AND-NOR INPUT (AL1 ENABLES) TO PIN BB2 (TO ADDER3). pins: 7 I AM1 AND-NOR INPUT (AL1 ENABLES) TO PIN AN2 (TO ADDER2) pins: 8 I AD2 AND-NOR ENABLE: RWB RWB3 TO PIN BB2 (TO ADDER3), RWB2 TO PIN AN2 (TO ADDER2) pins: 9 I AE2 AND-NOR ENABLE: PIN AE1 TO PIN BB2 (TO ADDER3), PIN AM2 TO PIN AN2 (TO ADDER2) pins: 10 I AE1 AND-NOR INPUT (AE2 ENABLES) TO PIN BB2 (TO ADDER3). pins: 11 I AM2 AND-NOR INPUT (AE2 ENABLES) TO PIN AN2 (TO ADDER2) pins: 12 I AC1 AND-NOR INPUT, AND WITH PIN AB2 TO PIN BB2 (TO ADDER3) pins: 13 I AB2 AND-NOR INPUT, AND WITH PIN AC1 TO PIN BB2 (TO ADDER3) pins: 14 I AF1 AND-NOR INPUT (AND WITH ITSELF) TO PIN BB2 (TO ADDER3) pins: 15 I AR2 AND-NOR INPUT, AND WITH PIN AS1 TO PIN AN2 (TO ADDER2) pins: 16 I AS1 AND-NOR INPUT, AND WITH PIN AR2 TO PIN AN2 (TO ADDER2) pins: 17 I AP2 AND-NOR INPUT (AND WITH ITSELF) TO PIN AN2 (TO ADDER2) pins: 18 I BK1 AND-NOR ENABLE: TB3 TO PIN BB1 (TO ADDER3), TB2 TO PIN BN1 (TO ADDER2) pins: 19 I BL1 AND-NOR ENABLE: PIN BE1 TO PIN BB1 (TO ADDER3), PIN BM1 TO PIN BN1 (TO ADDER2) pins: 20 I BE1 AND-NOR INPUT (BL1 ENABLES) TO PIN BB1 (TO ADDER3). pins: 21 I BM1 AND-NOR INPUT (BL1 ENABLES) TO PIN BN1 (TO ADDER2) pins: 22 I BF1 AND-NOR ENABLE: PIN BH1 TO PIN BB1 (TO ADDER3), PIN BR1 TO PIN BN1 (TO ADDER2) pins: 23 I BH1 AND-NOR INPUT (BF1 ENABLES): TO PIN BB1 (TO ADDER3), pins: 24 I BR1 AND-NOR INPUT (BF1 ENABLES): TO PIN BN1 (TO ADDER2) pins: 25 I BS1 AND-NOR ENABLE: PIN BC1 TO PIN BB1 (TO ADDER3), PIN BJ2 TO PIN BN1 (TO ADDER2) pins: 26 I BC1 AND-NOR INPUT (BS1 ENABLES): TO PIN BB1 (TO ADDER3), pins: 27 I BJ2 AND-NOR INPUT (BS1 ENABLES): TO PIN BN1 (TO ADDER2) pins: 28 I BL2 AND-NOR ENABLE: PIN BJ1 TO PIN BB1 (TO ADDER3), PIN BK2 TO PIN BN1 (TO ADDER2) pins: 29 I BJ1 AND-NOR INPUT (BL2 ENABLES): TO PIN BB1 (TO ADDER3), pins: 30 I BK2 AND-NOR INPUT (BL2 ENABLES): TO PIN BN1 (TO ADDER2) pins: 31 I BU1 AND-NOR ENABLE: PIN BH2 TO PIN BB1 (TO ADDER3), PIN BP2 TO PIN BN1 (TO ADDER2) pins: 32 I BH2 AND-NOR INPUT (BU1 ENABLES): TO PIN BB1 (TO ADDER3), pins: 33 I BP2 AND-NOR INPUT (BU1 ENABLES): TO PIN BN1 (TO ADDER2) pins: 34 I BN2 AND-NOR INPUT (AND WITH BM2): TO PIN BN1 (TO ADDER2) pins: 35 I BM2 AND-NOR INPUT (AND WITH BM2): TO PIN BN1 (TO ADDER2) pins: 36 O BB2 AND-NOR OUTPUT, (DRIVES E9-2 7482 A1) TO ADDER3 INPUT pins: 37 O BB1 AND-NOR OUTPUT, (DRIVES E9-3 7482 B1) TO ADDER3 INPUT pins: 38 O BN1 AND-NOR OUTPUT, (DRIVES E9-14 7482 A2) TO ADDER2 INPUT pins: 39 O AN2 AND-NOR OUTPUT, (DRIVES E9-13 7482 B2) TO ADDER2 INPUT pins: 40 O AV2 CARRY OUT-N (E9-10 7482 C2) pins: 41 O BV2 TAPE BUS 2 OUTPUT (INVERTED ADDER2 SUM-N (E9-12 7482 SUM2) pins: 42 O BR2 TAPE BUS 3 OUTPUT (INVERTED ADDER3 SUM-N (E9-1 7482 SUM1) pins: 43 I AK1 LOAD TMA SETUP (FROM TAPE BUS) (RISING EDGE CLOCK) pins: 44 O AR1 TMA SETUP 2 pins: 45 O AH1 TMA SETUP 3 pins: 46 I AU2 LOAD TMA (FROM TAPE BUS) (RISING EDGE CLOCK) pins: 47 O AT2 TMA 2 pins: 48 O AD1 TMA 3 pins: 49 I AJ1 LOAD TBN (FROM TAPE BUS) (RISING EDGE CLOCK) pins: 50 O AU1 TBN 2 pins: 51 O AK2 TBN 3 pins: 52 I AA1 LOAD TAC (FROM TAPE BUS) (RISING EDGE CLOCK) pins: 53 O AN1 TAC 2 pins: 54 O AJ2 TAC 2-N pins: 55 O AH2 TAC 3 pins: 56 O AB1 TAC 3-N pins: 57 I BT2 LOAD TB (FROM TAPE BUS) (RISING EDGE CLOCK) pins: 58 O BP1 TB 2 pins: 59 O BD1 TB 3 pins: 60 I BF2 LOAD RWB (FROM TB) (JAMS CLEAR,SET) pins: 61 I BS2 PHASE (SELECTS POLARITY OF RWB OUT, 0 -> INVERTED) pins: 62 I AV1 RWB IN (SHIFTED INTO RWB 3) pins: 63 I BE2 SHIFT RWB (SHIFTS PIN AV1 INTO RWB 3, SHIFTS RWB3 TO RWB2) (RISING CLOCK) pins: 64 O BV1 RWB OUT (IF PHASE=1, =RWB 2; IF PHASE=0; =RWB 2-N) pins: 65 O BD2 RWB 3 pins: 66 O BU2 +3.5V pins: direction: IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIOOOOOOOIOOIOOIOOIOOOOIOOIIIIOOO comment: ; all registers are unknown comment: ; turn on C0, PHASE comment: ; with no ENABLES, BUS2,BUS3 is 11, C2 is 1 test 1: 1000000000000000000000000000000000011111000XX0XX0XX0XXXX0XX0110XX1 comment: comment: ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; comment: ; comment: ; set all registers LOW comment: ; comment: ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; comment: comment: ; load TMA SETUP from tape bus (00) test 2: 100 test 3: 0 comment: ; load TMA from tape bus (00) test 4: 100 test 5: 0 comment: ; load TBN from tape bus (00) test 6: 100 test 7: 0 comment: ; load TAC from tape bus (00) test 8: 10101 test 9: 0 comment: ; load TB from tape bus (00) test 10: 100 test 11: 0 comment: ; load RWB from TB (JAMS CLEAR AND PRESET) test 12: 1 00 test 13: 0 comment: ; (no change) test 14: 100000000000000000000000000000000001111100000000000001010000110001 comment: comment: comment: ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; comment: ; comment: ; set all registers HIGH comment: ; comment: ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; comment: comment: ; set pin AF1 which clears pin BB2 and sets pin BR2 TAPE BUS 3 OUTPUT test 15: 1 0 1 comment: ; set pin AP2 which clears pin AN2 and sets pin BV2 TAPE BUS 2 OUTPUT test 16: 1 0 1 comment: comment: comment: ; load TMA SETUP from tape bus (11) test 17: 111 test 18: 0 comment: ; load TMA from tape bus (11) test 19: 111 test 20: 0 comment: ; load TBN from tape bus (11) test 21: 111 test 22: 0 comment: ; load TAC from tape bus (11) test 23: 11010 test 24: 0 comment: ; load TB from tape bus (11) test 25: 111 test 26: 0 comment: ; load RWB from TB (JAMS CLEAR AND PRESET) test 27: 1 11 test 28: 0 comment: ; clear pin AF1 (AND with itself) to set pin BB2 (AND-NOR output) and clear pin BR2 TAPE BUS 3 OUTPUT test 29: 0 1 0 comment: ; clear pin AP2 (AND with itself) to set pin AN2 (AND-NOR output) and clear pin BV2 TAPE BUS 2 OUTPUT test 30: 0 1 0 comment: ; (no change) test 31: 100000000000000000000000000000000001111100011011011010100110110111 comment: comment: ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; comment: ; comment: ; will all registers high, walk a 0 comment: ; comment: ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; comment: comment: comment: ; walk a 0, TMA SETUP 2 comment: comment: comment: ; clear pin AP2 which sets pin AN2 and clears pin BV2 TAPE BUS 2 OUTPUT test 32: 0 1 0 comment: ; set pin AF1 which clears pin BB2 and sets pin BR2 TAPE BUS 3 OUTPUT test 33: 1 0 1 comment: ; load TMA SETUP from tape bus (01) test 34: 101 test 35: 0 comment: ; restore TMA SETUP 2 comment: ; set pin AP2 which clears pin AN2 and sets pin BV2 TAPE BUS 2 OUTPUT test 36: 1 0 1 comment: ; load TMA SETUP from tape bus (11) test 37: 111 test 38: 0 comment: comment: comment: ; walk a 0, TMA SETUP 3 comment: comment: comment: ; set pin AP2 which clears pin AN2 and sets pin BV2 TAPE BUS 2 OUTPUT test 39: 1 0 1 comment: ; clear pin AF1 which sets pin BB2 and clears pin BR2 TAPE BUS 3 OUTPUT test 40: 0 1 0 comment: ; load TMA SETUP from tape bus (10) test 41: 110 test 42: 0 comment: ; restore TMA SETUP 3 comment: ; set pin AF1 which clears pin BB2 and sets pin BR2 TAPE BUS 3 OUTPUT test 43: 1 0 1 comment: ; load TMA SETUP from tape bus (11) test 44: 111 test 45: 0 comment: comment: comment: ; walk a 0, TMA 2 comment: comment: comment: ; clear pin AP2 which sets pin AN2 and clears pin BV2 TAPE BUS 2 OUTPUT test 46: 0 1 0 comment: ; set pin AF1 which clears pin BB2 and sets pin BR2 TAPE BUS 3 OUTPUT test 47: 1 0 1 comment: ; load TMA from tape bus (01) test 48: 101 test 49: 0 comment: ; restore TMA 2 comment: ; set pin AP2 which clears pin AN2 and sets pin BV2 TAPE BUS 2 OUTPUT test 50: 1 0 1 comment: ; load TMA from tape bus (11) test 51: 111 test 52: 0 comment: comment: comment: ; walk a 0, TMA 3 comment: comment: comment: ; set pin AP2 which clears pin AN2 and sets pin BV2 TAPE BUS 2 OUTPUT test 53: 1 0 1 comment: ; clear pin AF1 which sets pin BB2 and clears pin BR2 TAPE BUS 3 OUTPUT test 54: 0 1 0 comment: ; load TMA from tape bus (10) test 55: 110 test 56: 0 comment: ; restore TMA 3 comment: ; set pin AF1 which clears pin BB2 and sets pin BR2 TAPE BUS 3 OUTPUT test 57: 1 0 1 comment: ; load TMA from tape bus (11) test 58: 111 test 59: 0 comment: comment: comment: comment: comment: comment: comment: comment: comment: comment: comment: comment: ; load TBN from tape bus (00) test 60: 100 test 61: 0 comment: ; load TAC from tape bus (00) test 62: 10101 test 63: 0 comment: ; load TB from tape bus (00) test 64: 100 test 65: 0 comment: ; load RWB from TB (JAMS CLEAR AND PRESET) test 66: 1 00 test 67: 0 comment: comment: comment: comment: comment: comment: comment: comment: comment: comment: comment: comment: comment: comment: comment: ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; comment: ; comment: ; test AND-NOR logic comment: ; comment: ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; comment: comment: ; (all registers are HIGH) comment: ; set all pins HIGH except ENABLES comment: comment: ; set pin AF2 HIGH test 68: 1 comment: ; set pin AM1 HIGH test 69: 1 comment: ; set pin AE1 HIGH test 70: 1 comment: ; set pin AM2 HIGH test 71: 1 comment: ; set pin AB2 HIGH test 72: 1 comment: ; set pin AS1 HIGH test 73: 1 comment: ; set pin BE1 HIGH test 74: 1 comment: ; set pin BM1 HIGH test 75: 1 comment: ; set pin BH1 HIGH test 76: 1 comment: ; set pin BR1 HIGH test 77: 1 comment: ; set pin BC1 HIGH test 78: 1 comment: ; set pin BJ2 HIGH test 79: 1 comment: ; set pin BJ1 HIGH test 80: 1 comment: ; set pin BK2 HIGH test 81: 1 comment: ; set pin BH2 HIGH test 82: 1 comment: ; set pin BP2 HIGH test 83: 1 comment: ; set pin BN2 HIGH test 84: 1 comment: ; toggle each ENABLE comment: comment: ; set pin AL2 to clear pin BB2 and pin AN2 AND-NOR OUTPUTS and set TAPE BUS 2 OUTPUT and TAPE BUS 3 OUTPUT test 85: 1 0 0 11 test 86: 0 1 1 00 comment: ; set pin AP1 to clear pin BB2 and pin AN2 AND-NOR OUTPUTS and set TAPE BUS 2 OUTPUT and TAPE BUS 3 OUTPUT test 87: 1 0 0 11 test 88: 0 1 1 00 comment: ; set pin AS2 to clear pin BB2 and pin AN2 AND-NOR OUTPUTS and set TAPE BUS 2 OUTPUT and TAPE BUS 3 OUTPUT test 89: 1 0 0 11 test 90: 0 1 1 00 comment: ; set pin AL1 to clear pin BB2 and pin AN2 AND-NOR OUTPUTS and set TAPE BUS 2 OUTPUT and TAPE BUS 3 OUTPUT test 91: 1 0 0 11 test 92: 0 1 1 00 comment: ; set pin AL1 to clear pin BB2 and pin AN2 AND-NOR OUTPUTS and set TAPE BUS 2 OUTPUT and TAPE BUS 3 OUTPUT test 93: 1 0 0 11 test 94: 0 1 1 00 comment: ; set pin AE2 to clear pin BB2 and pin AN2 AND-NOR OUTPUTS and set TAPE BUS 2 OUTPUT and TAPE BUS 3 OUTPUT test 95: 1 0 0 11 test 96: 0 1 1 00 comment: ; set pin AC1 to clear pin BB2 and set TAPE BUS 3 OUTPUT test 97: 1 0 1 test 98: 0 1 0 comment: ; set pin AF1 to clear pin BB2 and set TAPE BUS 3 OUTPUT test 99: 1 0 1 test 100: 0 1 0 comment: ; set pin AR2 to clear pin AN2 AND-NOR OUTPUTS and set TAPE BUS 2 OUTPUT test 101: 1 0 1 test 102: 0 1 0 comment: ; set pin AP2 to clear pin AN2 AND-NOR OUTPUTS and set TAPE BUS 2 OUTPUT test 103: 1 0 1 test 104: 0 1 0 comment: comment: ; set pin BK1 to clear pin BB1 and pin BN1 AND-NOR OUTPUTS and set TAPE BUS 2 OUTPUT and TAPE BUS 3 OUTPUT test 105: 1 00 11 test 106: 0 11 00 comment: ; set pin BL1 to clear pin BB1 and pin BN1 AND-NOR OUTPUTS and set TAPE BUS 2 OUTPUT and TAPE BUS 3 OUTPUT test 107: 1 00 11 test 108: 0 11 00 comment: ; set pin BF1 to clear pin BB1 and pin BN1 AND-NOR OUTPUTS and set TAPE BUS 2 OUTPUT and TAPE BUS 3 OUTPUT test 109: 1 00 11 test 110: 0 11 00 comment: ; set pin BS1 to clear pin BB1 and pin BN1 AND-NOR OUTPUTS and set TAPE BUS 2 OUTPUT and TAPE BUS 3 OUTPUT test 111: 1 00 11 test 112: 0 11 00 comment: ; set pin BL2 to clear pin BB1 and pin BN1 AND-NOR OUTPUTS and set TAPE BUS 2 OUTPUT and TAPE BUS 3 OUTPUT test 113: 1 00 11 test 114: 0 11 00 comment: ; set pin BU1 to clear pin BB1 and pin BN1 AND-NOR OUTPUTS and set TAPE BUS 2 OUTPUT and TAPE BUS 3 OUTPUT test 115: 1 00 11 test 116: 0 11 00 comment: ; set pin BM2 to clear pin BB1 and TAPE BUS 3 OUTPUT test 117: 1 0 1 test 118: 0 1 0 comment: ; no change test 119: 100000000000000000000000000000000001111100011011011010100110110111 comment: comment: ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; comment: ; test shifting the RWB comment: ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; comment: comment: ; shift in 0, expect 10 test 120: 0 test 121: 110 test 122: 0 comment: ; toggle phase should toggle RWB 2 test 123: 0 0 test 124: 1 1 comment: comment: ; shift in 0, expect 00 test 125: 0 test 126: 100 test 127: 0 comment: ; toggle phase should toggle RWB 2 test 128: 0 1 test 129: 1 0 comment: comment: ; shift in 0, expect 00 test 130: 0 test 131: 100 test 132: 0 comment: ; shift in 1, expect 01 test 133: 1 test 134: 101 test 135: 0 comment: ; shift in 1, expect 11 test 136: 1 test 137: 111 test 138: 0 comment: ; shift in 1, expect 11 test 139: 1 test 140: 111 test 141: 0 comment: ; shift in 0, expect 10 test 142: 0 test 143: 110 test 144: 0 comment: ; shift in 1, expect 01 test 145: 1 test 146: 101 test 147: 0 comment: ; shift in 0, expect 10 test 148: 0 test 149: 110 test 150: 0 comment: ; shift in 1, expect 01 test 151: 1 test 152: 101 test 153: 0 comment: ; shift in 1, expect 11 test 154: 1 test 155: 111 test 156: 0 comment: ; no change test 157: 100000000000000000000000000000000001111100011011011010100110110111 comment: comment: ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; comment: ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; comment: ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; comment: ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; comment: ; needs work (more adder tests, more register tests) comment: ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; comment: ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; comment: ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; comment: ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; end: END summary column 1: offset 2, mask 0x2000 column 2: offset 1, mask 0x0002 column 3: offset 1, mask 0x0800 column 4: offset 1, mask 0x0040 column 5: offset 1, mask 0x4000 column 6: offset 0, mask 0x0004 column 7: offset 1, mask 0x2000 column 8: offset 0, mask 0x0010 column 9: offset 0, mask 0x0008 column 10: offset 0, mask 0x0800 column 11: offset 1, mask 0x0004 column 12: offset 0, mask 0x2000 column 13: offset 0, mask 0x0040 column 14: offset 0, mask 0x0400 column 15: offset 1, mask 0x0020 column 16: offset 1, mask 0x0200 column 17: offset 1, mask 0x0010 column 18: offset 3, mask 0x2000 column 19: offset 3, mask 0x1000 column 20: offset 2, mask 0x0200 column 21: offset 3, mask 0x0800 column 22: offset 2, mask 0x0100 column 23: offset 3, mask 0x8000 column 24: offset 3, mask 0x0100 column 25: offset 4, mask 0x8000 column 26: offset 2, mask 0x0800 column 27: offset 3, mask 0x0002 column 28: offset 3, mask 0x0008 column 29: offset 3, mask 0x4000 column 30: offset 3, mask 0x0004 column 31: offset 4, mask 0x2000 column 32: offset 3, mask 0x0001 column 33: offset 3, mask 0x0040 column 34: offset 3, mask 0x0020 column 35: offset 3, mask 0x0010 column 36: offset 2, mask 0x0008 column 37: offset 2, mask 0x1000 column 38: offset 3, mask 0x0400 column 39: offset 1, mask 0x0008 column 40: offset 2, mask 0x0002 column 41: offset 4, mask 0x0008 column 42: offset 3, mask 0x0080 column 43: offset 1, mask 0x8000 column 44: offset 1, mask 0x0400 column 45: offset 0, mask 0x0200 column 46: offset 2, mask 0x0001 column 47: offset 1, mask 0x0080 column 48: offset 0, mask 0x1000 column 49: offset 0, mask 0x0100 column 50: offset 2, mask 0x8000 column 51: offset 1, mask 0x0001 column 52: offset 0, mask 0x8000 column 53: offset 1, mask 0x1000 column 54: offset 0, mask 0x0001 column 55: offset 0, mask 0x0002 column 56: offset 0, mask 0x4000 column 57: offset 4, mask 0x0002 column 58: offset 3, mask 0x0200 column 59: offset 2, mask 0x0400 column 60: offset 2, mask 0x0080 column 61: offset 4, mask 0x0001 column 62: offset 2, mask 0x4000 column 63: offset 2, mask 0x0040 column 64: offset 4, mask 0x1000 column 65: offset 2, mask 0x0020 column 66: offset 4, mask 0x0004 direction bits (1=input) 0x52A3 0x1589 0x943A 0x0680 0x50FC pullup bits (1=pullup) 0x0000 0x0000 0x0000 0x0000 0x0000 test step out_data dont care 1: 0x0000 0x0008 0x700A 0x0400 0x0005 0x5203 0x1481 0x8420 0x0200 0x1000 2: 0x0000 0x8008 0x700A 0x0400 0x0005 0x5003 0x1081 0x8420 0x0200 0x1000 3: 0x0000 0x0008 0x700A 0x0400 0x0005 0x5003 0x1081 0x8420 0x0200 0x1000 4: 0x0000 0x0008 0x700B 0x0400 0x0005 0x4003 0x1001 0x8420 0x0200 0x1000 5: 0x0000 0x0008 0x700A 0x0400 0x0005 0x4003 0x1001 0x8420 0x0200 0x1000 6: 0x0100 0x0008 0x700A 0x0400 0x0005 0x4003 0x1000 0x0420 0x0200 0x1000 7: 0x0000 0x0008 0x700A 0x0400 0x0005 0x4003 0x1000 0x0420 0x0200 0x1000 8: 0xC001 0x0008 0x700A 0x0400 0x0005 0x0000 0x0000 0x0420 0x0200 0x1000 9: 0x4001 0x0008 0x700A 0x0400 0x0005 0x0000 0x0000 0x0420 0x0200 0x1000 10: 0x4001 0x0008 0x700A 0x0400 0x0007 0x0000 0x0000 0x0020 0x0000 0x1000 11: 0x4001 0x0008 0x700A 0x0400 0x0005 0x0000 0x0000 0x0020 0x0000 0x1000 12: 0x4001 0x0008 0x708A 0x0400 0x0005 13: 0x4001 0x0008 0x700A 0x0400 0x0005 14: 0x4001 0x0008 0x700A 0x0400 0x0005 15: 0x4401 0x0008 0x7002 0x0480 0x0005 16: 0x4401 0x0010 0x7002 0x0480 0x000D 17: 0x4601 0x8410 0x7002 0x0480 0x000D 18: 0x4601 0x0410 0x7002 0x0480 0x000D 19: 0x5601 0x0490 0x7003 0x0480 0x000D 20: 0x5601 0x0490 0x7002 0x0480 0x000D 21: 0x5701 0x0491 0xF002 0x0480 0x000D 22: 0x5601 0x0491 0xF002 0x0480 0x000D 23: 0x9602 0x1491 0xF002 0x0480 0x000D 24: 0x1602 0x1491 0xF002 0x0480 0x000D 25: 0x1602 0x1491 0xF402 0x0680 0x000F 26: 0x1602 0x1491 0xF402 0x0680 0x000D 27: 0x1602 0x1491 0xF4A2 0x0680 0x100D 28: 0x1602 0x1491 0xF422 0x0680 0x100D 29: 0x1202 0x1491 0xF42A 0x0600 0x100D 30: 0x1202 0x1489 0xF42A 0x0600 0x1005 31: 0x1202 0x1489 0xF42A 0x0600 0x1005 32: 0x1202 0x1489 0xF42A 0x0600 0x1005 33: 0x1602 0x1489 0xF422 0x0680 0x1005 34: 0x1602 0x9089 0xF422 0x0680 0x1005 35: 0x1602 0x1089 0xF422 0x0680 0x1005 36: 0x1602 0x1091 0xF422 0x0680 0x100D 37: 0x1602 0x9491 0xF422 0x0680 0x100D 38: 0x1602 0x1491 0xF422 0x0680 0x100D 39: 0x1602 0x1491 0xF422 0x0680 0x100D 40: 0x1202 0x1491 0xF42A 0x0600 0x100D 41: 0x1002 0x9491 0xF42A 0x0600 0x100D 42: 0x1002 0x1491 0xF42A 0x0600 0x100D 43: 0x1402 0x1491 0xF422 0x0680 0x100D 44: 0x1602 0x9491 0xF422 0x0680 0x100D 45: 0x1602 0x1491 0xF422 0x0680 0x100D 46: 0x1602 0x1489 0xF422 0x0680 0x1005 47: 0x1602 0x1489 0xF422 0x0680 0x1005 48: 0x1602 0x1409 0xF423 0x0680 0x1005 49: 0x1602 0x1409 0xF422 0x0680 0x1005 50: 0x1602 0x1411 0xF422 0x0680 0x100D 51: 0x1602 0x1491 0xF423 0x0680 0x100D 52: 0x1602 0x1491 0xF422 0x0680 0x100D 53: 0x1602 0x1491 0xF422 0x0680 0x100D 54: 0x1202 0x1491 0xF42A 0x0600 0x100D 55: 0x0202 0x1491 0xF42B 0x0600 0x100D 56: 0x0202 0x1491 0xF42A 0x0600 0x100D 57: 0x0602 0x1491 0xF422 0x0680 0x100D 58: 0x1602 0x1491 0xF423 0x0680 0x100D 59: 0x1602 0x1491 0xF422 0x0680 0x100D 60: 0x1702 0x1490 0x7422 0x0680 0x100D 61: 0x1602 0x1490 0x7422 0x0680 0x100D 62: 0xD601 0x0490 0x7422 0x0680 0x100D 63: 0x5601 0x0490 0x7422 0x0680 0x100D 64: 0x5601 0x0490 0x7022 0x0480 0x100F 65: 0x5601 0x0490 0x7022 0x0480 0x100D 66: 0x5601 0x0490 0x7082 0x0480 0x000D 67: 0x5601 0x0490 0x7002 0x0480 0x000D 68: 0x5605 0x0490 0x7002 0x0480 0x000D 69: 0x5605 0x2490 0x7002 0x0480 0x000D 70: 0x5E05 0x2490 0x7002 0x0480 0x000D 71: 0x5E05 0x2494 0x7002 0x0480 0x000D 72: 0x5E45 0x2494 0x7002 0x0480 0x000D 73: 0x5E45 0x2694 0x7002 0x0480 0x000D 74: 0x5E45 0x2694 0x7202 0x0480 0x000D 75: 0x5E45 0x2694 0x7202 0x0C80 0x000D 76: 0x5E45 0x2694 0x7202 0x8C80 0x000D 77: 0x5E45 0x2694 0x7202 0x8D80 0x000D 78: 0x5E45 0x2694 0x7A02 0x8D80 0x000D 79: 0x5E45 0x2694 0x7A02 0x8D82 0x000D 80: 0x5E45 0x2694 0x7A02 0xCD82 0x000D 81: 0x5E45 0x2694 0x7A02 0xCD86 0x000D 82: 0x5E45 0x2694 0x7A02 0xCD87 0x000D 83: 0x5E45 0x2694 0x7A02 0xCDC7 0x000D 84: 0x5E45 0x2694 0x7A02 0xCDE7 0x000D 85: 0x5E45 0x2696 0x7A02 0xCDE7 0x000D 86: 0x5E45 0x269C 0x7A0A 0xCD67 0x0005 87: 0x5E45 0x2E94 0x7A02 0xCDE7 0x000D 88: 0x5E45 0x269C 0x7A0A 0xCD67 0x0005 89: 0x5E45 0x26D4 0x7A02 0xCDE7 0x000D 90: 0x5E45 0x269C 0x7A0A 0xCD67 0x0005 91: 0x5E45 0x6694 0x7A02 0xCDE7 0x000D 92: 0x5E45 0x269C 0x7A0A 0xCD67 0x0005 93: 0x5E55 0x2694 0x7A02 0xCDE7 0x000D 94: 0x5E45 0x269C 0x7A0A 0xCD67 0x0005 95: 0x5E4D 0x2694 0x7A02 0xCDE7 0x000D 96: 0x5E45 0x269C 0x7A0A 0xCD67 0x0005 97: 0x7E45 0x269C 0x7A02 0xCDE7 0x0005 98: 0x5E45 0x269C 0x7A0A 0xCD67 0x0005 99: 0x5E45 0x269C 0x7A02 0xCDE7 0x0005 100: 0x5A45 0x269C 0x7A0A 0xCD67 0x0005 101: 0x5A45 0x26B4 0x7A0A 0xCD67 0x000D 102: 0x5A45 0x269C 0x7A0A 0xCD67 0x0005 103: 0x5A45 0x2694 0x7A0A 0xCD67 0x000D 104: 0x5A45 0x268C 0x7A0A 0xCD67 0x0005 105: 0x5A45 0x268C 0x6A0A 0xE9E7 0x000D 106: 0x5A45 0x268C 0x7A0A 0xCD67 0x0005 107: 0x5A45 0x268C 0x6A0A 0xD9E7 0x000D 108: 0x5A45 0x268C 0x7A0A 0xCD67 0x0005 109: 0x5A45 0x268C 0x6B0A 0xC9E7 0x000D 110: 0x5A45 0x268C 0x7A0A 0xCD67 0x0005 111: 0x5A45 0x268C 0x6A0A 0xC9E7 0x800D 112: 0x5A45 0x268C 0x7A0A 0xCD67 0x0005 113: 0x5A45 0x268C 0x6A0A 0xC9EF 0x000D 114: 0x5A45 0x268C 0x7A0A 0xCD67 0x0005 115: 0x5A45 0x268C 0x6A0A 0xC9E7 0x200D 116: 0x5A45 0x268C 0x7A0A 0xCD67 0x0005 117: 0x5A45 0x268C 0x7A0A 0xC977 0x000D 118: 0x5A45 0x268C 0x7A0A 0xCD67 0x0005 119: 0x1202 0x1489 0xF42A 0x0600 0x1005 120: 0x1202 0x1489 0xB42A 0x0600 0x1005 121: 0x1202 0x1489 0xB44A 0x0600 0x1005 122: 0x1202 0x1489 0xB40A 0x0600 0x1005 123: 0x1202 0x1489 0xB40A 0x0600 0x0004 124: 0x1202 0x1489 0xB40A 0x0600 0x1005 125: 0x1202 0x1489 0xB40A 0x0600 0x1005 126: 0x1202 0x1489 0xB44A 0x0600 0x0005 127: 0x1202 0x1489 0xB40A 0x0600 0x0005 128: 0x1202 0x1489 0xB40A 0x0600 0x1004 129: 0x1202 0x1489 0xB40A 0x0600 0x0005 130: 0x1202 0x1489 0xB40A 0x0600 0x0005 131: 0x1202 0x1489 0xB44A 0x0600 0x0005 132: 0x1202 0x1489 0xB40A 0x0600 0x0005 133: 0x1202 0x1489 0xF40A 0x0600 0x0005 134: 0x1202 0x1489 0xF46A 0x0600 0x0005 135: 0x1202 0x1489 0xF42A 0x0600 0x0005 136: 0x1202 0x1489 0xF42A 0x0600 0x0005 137: 0x1202 0x1489 0xF46A 0x0600 0x1005 138: 0x1202 0x1489 0xF42A 0x0600 0x1005 139: 0x1202 0x1489 0xF42A 0x0600 0x1005 140: 0x1202 0x1489 0xF46A 0x0600 0x1005 141: 0x1202 0x1489 0xF42A 0x0600 0x1005 142: 0x1202 0x1489 0xB42A 0x0600 0x1005 143: 0x1202 0x1489 0xB44A 0x0600 0x1005 144: 0x1202 0x1489 0xB40A 0x0600 0x1005 145: 0x1202 0x1489 0xF40A 0x0600 0x1005 146: 0x1202 0x1489 0xF46A 0x0600 0x0005 147: 0x1202 0x1489 0xF42A 0x0600 0x0005 148: 0x1202 0x1489 0xB42A 0x0600 0x0005 149: 0x1202 0x1489 0xB44A 0x0600 0x1005 150: 0x1202 0x1489 0xB40A 0x0600 0x1005 151: 0x1202 0x1489 0xF40A 0x0600 0x1005 152: 0x1202 0x1489 0xF46A 0x0600 0x0005 153: 0x1202 0x1489 0xF42A 0x0600 0x0005 154: 0x1202 0x1489 0xF42A 0x0600 0x0005 155: 0x1202 0x1489 0xF46A 0x0600 0x1005 156: 0x1202 0x1489 0xF42A 0x0600 0x1005 157: 0x1202 0x1489 0xF42A 0x0600 0x1005 PINs used (in edge connector order) (G=ground,P=power) SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBB LETTER ABCDEFHJKLMNPRSTUVABCDEFHJKLMNPRSTUVABCDEFHJKLMNPRSTUVABCDEFHJKLMNPRSTUV SIDE 111111111111111111222222222222222222111111111111111111222222222222222222 USAGE IOIOIIOIIIIOIOIGOIPIGIIIOOOIIOIIIOIOIOIOIIIIIIIOOIIGIOPOGOIIIIIIIIIOIIOO UUT has 44 inputs UUT has 22 outputs contains 66 pins/columns 0 pins are not used contains 157 'test steps' M222 PCB REV B SCHEMATIC REV A LINC TAPE REGISTERS TERMINOLOGY- SIGNALS REFER TO PDP12 MAINT VOL4 M222 SCHEMATIC. BUT... DEC USES AND-NOR GATES TO ROUTE THE ADDER A AND B INPUTS, SO... DEC RENAMED THE ADDER TO NEGATIVE LOGIC TERMS (I.E. A-N + B-N + C-N -> SUM-N, C1-N). (NOT THE 7482 DATASHEET NAMES OF A + B + C -> SUM, C1). SO, WITH ALL 'AND ENABLES' LOW, THE AND-NOR OUTPUTS = HIGH. WITH C-L HIGH, THE ADDER OUTPUT IS SUM-N=1, C1-N=1; THE INVERTED ADDER OUTPUT IS LOW (TAPE BUS). AND THERE IS NO CARRY (C1-N IS HI). THE TWO ADDERS, TWO REGISTER BITS, ETC ARE LABELED BIT 2 (EVEN, MSB) AND BIT 3 (ODD, LSB). THE ADDERS ARE REFERRED TO AS 'ADDER2' (MSB) AND 'ADDER3' (LSB). POWER PINS: AA2 +5V AT1 GROUND AC2 GROUND BA2 +5V BT1 GROUND BC2 GROUND (ALL PINS ARE USED). PINS Main menu Thu Aug 20 17:56:22 2015 test file is: tests\m222.new delay is: 0 trigger is: 1 1 read test file 2 set test delay 3 set test trigger 4 run test 5 output loading test 8 diags 9 exit UUT power is okay Thu Aug 20 17:56:23 2015 space single step O run once (one test, all steps) F run, stop on fail G go (run tests N run, stop on fail, no print S scope (run, no print) C toggle comment printout + increase speed (less delay) - decrease speed (more delay)(slower) Q quit test comment_flag is 1 space single step O run once (one test, all steps) F run, stop on fail G go (run tests N run, stop on fail, no print S scope (run, no print) C toggle comment printout + increase speed (less delay) - decrease speed (more delay)(slower) Q quit test source: ; all registers are unknown source: ; turn on C0, PHASE source: ; with no ENABLES, BUS2,BUS3 is 11, C2 is 1 source: 1000000000000000000000000000000000011111000XX0XX0XX0XXXX0XX0110XX1 changed: step 1 100000000000000000000000000000000001111100010010010010010100110101 source: source: ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; source: ; source: ; set all registers LOW source: ; source: ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; source: source: ; load TMA SETUP from tape bus (00) source: 100 changed: 10 step 2 100000000000000000000000000000000001111100100010010010010100110101 source: 0 changed: 0 step 3 100000000000000000000000000000000001111100000010010010010100110101 source: ; load TMA from tape bus (00) source: 100 changed: 10 step 4 100000000000000000000000000000000001111100000100010010010100110101 source: 0 changed: 0 step 5 100000000000000000000000000000000001111100000000010010010100110101 source: ; load TBN from tape bus (00) source: 100 changed: 10 step 6 100000000000000000000000000000000001111100000000100010010100110101 source: 0 changed: 0 step 7 100000000000000000000000000000000001111100000000000010010100110101 source: ; load TAC from tape bus (00) source: 10101 changed: 101 step 8 100000000000000000000000000000000001111100000000000101010100110101 source: 0 changed: 0 step 9 100000000000000000000000000000000001111100000000000001010100110101 source: ; load TB from tape bus (00) source: 100 changed: 10 step 10 100000000000000000000000000000000001111100000000000001011000110101 source: 0 changed: 0 step 11 100000000000000000000000000000000001111100000000000001010000110101 source: ; load RWB from TB (JAMS CLEAR AND PRESET) source: 1 00 changed: 1 0 step 12 100000000000000000000000000000000001111100000000000001010001110001 source: 0 changed: 0 step 13 100000000000000000000000000000000001111100000000000001010000110001 source: ; (no change) source: 100000000000000000000000000000000001111100000000000001010000110001 changed: step 14 100000000000000000000000000000000001111100000000000001010000110001 source: source: source: ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; source: ; source: ; set all registers HIGH source: ; source: ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; source: source: ; set pin AF1 which clears pin BB2 and sets pin BR2 TAPE BUS 3 OUTPUT source: 1 0 1 changed: 1 0 1 step 15 100000000000010000000000000000000000111101000000000001010000110001 source: ; set pin AP2 which clears pin AN2 and sets pin BV2 TAPE BUS 2 OUTPUT source: 1 0 1 changed: 1 0 1 step 16 100000000000010010000000000000000000110111000000000001010000110001 source: source: source: ; load TMA SETUP from tape bus (11) source: 111 changed: 111 step 17 100000000000010010000000000000000000110111111000000001010000110001 source: 0 changed: 0 step 18 100000000000010010000000000000000000110111011000000001010000110001 source: ; load TMA from tape bus (11) source: 111 changed: 111 step 19 100000000000010010000000000000000000110111011111000001010000110001 source: 0 changed: 0 step 20 100000000000010010000000000000000000110111011011000001010000110001 source: ; load TBN from tape bus (11) source: 111 changed: 111 step 21 100000000000010010000000000000000000110111011011111001010000110001 source: 0 changed: 0 step 22 100000000000010010000000000000000000110111011011011001010000110001 source: ; load TAC from tape bus (11) source: 11010 changed: 11010 step 23 100000000000010010000000000000000000110111011011011110100000110001 source: 0 changed: 0 step 24 100000000000010010000000000000000000110111011011011010100000110001 source: ; load TB from tape bus (11) source: 111 changed: 111 step 25 100000000000010010000000000000000000110111011011011010101110110001 source: 0 changed: 0 step 26 100000000000010010000000000000000000110111011011011010100110110001 source: ; load RWB from TB (JAMS CLEAR AND PRESET) source: 1 11 changed: 1 11 step 27 100000000000010010000000000000000000110111011011011010100111110111 source: 0 changed: 0 step 28 100000000000010010000000000000000000110111011011011010100110110111 source: ; clear pin AF1 (AND with itself) to set pin BB2 (AND-NOR output) and clear pin BR2 TAPE BUS 3 OUTPUT source: 0 1 0 changed: 0 1 0 step 29 100000000000000010000000000000000001110110011011011010100110110111 source: ; clear pin AP2 (AND with itself) to set pin AN2 (AND-NOR output) and clear pin BV2 TAPE BUS 2 OUTPUT source: 0 1 0 changed: 0 1 0 step 30 100000000000000000000000000000000001111100011011011010100110110111 source: ; (no change) source: 100000000000000000000000000000000001111100011011011010100110110111 changed: step 31 100000000000000000000000000000000001111100011011011010100110110111 source: source: ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; source: ; source: ; will all registers high, walk a 0 source: ; source: ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; source: source: source: ; walk a 0, TMA SETUP 2 source: source: source: ; clear pin AP2 which sets pin AN2 and clears pin BV2 TAPE BUS 2 OUTPUT source: 0 1 0 changed: step 32 100000000000000000000000000000000001111100011011011010100110110111 source: ; set pin AF1 which clears pin BB2 and sets pin BR2 TAPE BUS 3 OUTPUT source: 1 0 1 changed: 1 0 1 step 33 100000000000010000000000000000000000111101011011011010100110110111 source: ; load TMA SETUP from tape bus (01) source: 101 changed: 10 step 34 100000000000010000000000000000000000111101101011011010100110110111 source: 0 changed: 0 step 35 100000000000010000000000000000000000111101001011011010100110110111 source: ; restore TMA SETUP 2 source: ; set pin AP2 which clears pin AN2 and sets pin BV2 TAPE BUS 2 OUTPUT source: 1 0 1 changed: 1 0 1 step 36 100000000000010010000000000000000000110111001011011010100110110111 source: ; load TMA SETUP from tape bus (11) source: 111 changed: 11 step 37 100000000000010010000000000000000000110111111011011010100110110111 source: 0 changed: 0 step 38 100000000000010010000000000000000000110111011011011010100110110111 source: source: source: ; walk a 0, TMA SETUP 3 source: source: source: ; set pin AP2 which clears pin AN2 and sets pin BV2 TAPE BUS 2 OUTPUT source: 1 0 1 changed: step 39 100000000000010010000000000000000000110111011011011010100110110111 source: ; clear pin AF1 which sets pin BB2 and clears pin BR2 TAPE BUS 3 OUTPUT source: 0 1 0 changed: 0 1 0 step 40 100000000000000010000000000000000001110110011011011010100110110111 source: ; load TMA SETUP from tape bus (10) source: 110 changed: 1 0 step 41 100000000000000010000000000000000001110110110011011010100110110111 source: 0 changed: 0 step 42 100000000000000010000000000000000001110110010011011010100110110111 source: ; restore TMA SETUP 3 source: ; set pin AF1 which clears pin BB2 and sets pin BR2 TAPE BUS 3 OUTPUT source: 1 0 1 changed: 1 0 1 step 43 100000000000010010000000000000000000110111010011011010100110110111 source: ; load TMA SETUP from tape bus (11) source: 111 changed: 1 1 step 44 100000000000010010000000000000000000110111111011011010100110110111 source: 0 changed: 0 step 45 100000000000010010000000000000000000110111011011011010100110110111 source: source: source: ; walk a 0, TMA 2 source: source: source: ; clear pin AP2 which sets pin AN2 and clears pin BV2 TAPE BUS 2 OUTPUT source: 0 1 0 changed: 0 1 0 step 46 100000000000010000000000000000000000111101011011011010100110110111 source: ; set pin AF1 which clears pin BB2 and sets pin BR2 TAPE BUS 3 OUTPUT source: 1 0 1 changed: step 47 100000000000010000000000000000000000111101011011011010100110110111 source: ; load TMA from tape bus (01) source: 101 changed: 10 step 48 100000000000010000000000000000000000111101011101011010100110110111 source: 0 changed: 0 step 49 100000000000010000000000000000000000111101011001011010100110110111 source: ; restore TMA 2 source: ; set pin AP2 which clears pin AN2 and sets pin BV2 TAPE BUS 2 OUTPUT source: 1 0 1 changed: 1 0 1 step 50 100000000000010010000000000000000000110111011001011010100110110111 source: ; load TMA from tape bus (11) source: 111 changed: 11 step 51 100000000000010010000000000000000000110111011111011010100110110111 source: 0 changed: 0 step 52 100000000000010010000000000000000000110111011011011010100110110111 source: source: source: ; walk a 0, TMA 3 source: source: source: ; set pin AP2 which clears pin AN2 and sets pin BV2 TAPE BUS 2 OUTPUT source: 1 0 1 changed: step 53 100000000000010010000000000000000000110111011011011010100110110111 source: ; clear pin AF1 which sets pin BB2 and clears pin BR2 TAPE BUS 3 OUTPUT source: 0 1 0 changed: 0 1 0 step 54 100000000000000010000000000000000001110110011011011010100110110111 source: ; load TMA from tape bus (10) source: 110 changed: 1 0 step 55 100000000000000010000000000000000001110110011110011010100110110111 source: 0 changed: 0 step 56 100000000000000010000000000000000001110110011010011010100110110111 source: ; restore TMA 3 source: ; set pin AF1 which clears pin BB2 and sets pin BR2 TAPE BUS 3 OUTPUT source: 1 0 1 changed: 1 0 1 step 57 100000000000010010000000000000000000110111011010011010100110110111 source: ; load TMA from tape bus (11) source: 111 changed: 1 1 step 58 100000000000010010000000000000000000110111011111011010100110110111 source: 0 changed: 0 step 59 100000000000010010000000000000000000110111011011011010100110110111 SLOT BAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBAABBAAAAAAAAAAAAAABBBBBABBBB LETTER ALPSLFMDEEMCBFRSPKLEMFHRSCJLJKUHPNMBBNNVVRKRHUTDJUKANJHBTPDFSVEVDU SIDE 121212122121212121111111112212122222112222111221112112212112212122 DIRECTION IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIOOOOOOOIOOIOOIOOIOOOOIOOIIIIOOO source: source: source: source: source: source: source: source: source: source: source: source: ; load TBN from tape bus (00) source: 100 changed: 1 step 60 100000000000010010000000000000000000110111011011111010100110110111 fail ^^ space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C toggle comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT BAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBAABBAAAAAAAAAAAAAABBBBBABBBB LETTER ALPSLFMDEEMCBFRSPKLEMFHRSCJLJKUHPNMBBNNVVRKRHUTDJUKANJHBTPDFSVEVDU SIDE 121212122121212121111111112212122222112222111221112112212112212122 DIRECTION IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIOOOOOOOIOOIOOIOOIOOOOIOOIIIIOOO all fails OO was lo 00000000000000000000000000000000000 0 00000000000000000000 000 falling v v v v vvvvvvvvvv vvv vvv v v rising ^ ^ ^ ^ ^^^^^^^^^^^^^^^ ^^^^ ^^ was hi 1 1 1 111111111111111111111111111 111 total fails 0, total passes 0 Main menu Thu Aug 20 17:56:34 2015 test file is: tests\m222.new delay is: 0 trigger is: 1 1 read test file 2 set test delay 3 set test trigger 4 run test 5 output loading test 8 diags 9 exit Enter test file name? trying to open test file: tests\m222.new reading test file: tests\m222.new comment: M222 PCB REV B SCHEMATIC REV A LINC TAPE REGISTERS comment: comment: TERMINOLOGY- SIGNALS REFER TO PDP12 MAINT VOL4 M222 SCHEMATIC. comment: comment: BUT... comment: comment: DEC USES AND-NOR GATES TO ROUTE THE ADDER A AND B INPUTS, SO... comment: DEC RENAMED THE ADDER TO NEGATIVE LOGIC TERMS (I.E. A-N + B-N + C-N -> SUM-N, C1-N). comment: (NOT THE 7482 DATASHEET NAMES OF A + B + C -> SUM, C1). comment: comment: SO, WITH ALL 'AND ENABLES' LOW, THE AND-NOR OUTPUTS = HIGH. comment: WITH C-L HIGH, THE ADDER OUTPUT IS SUM-N=1, C1-N=1; comment: THE INVERTED ADDER OUTPUT IS LOW (TAPE BUS). comment: AND THERE IS NO CARRY (C1-N IS HI). comment: comment: THE TWO ADDERS, TWO REGISTER BITS, ETC ARE LABELED BIT 2 (EVEN, MSB) AND BIT 3 (ODD, LSB). comment: THE ADDERS ARE REFERRED TO AS 'ADDER2' (MSB) AND 'ADDER3' (LSB). comment: comment: POWER PINS: comment: AA2 +5V comment: AT1 GROUND comment: AC2 GROUND comment: BA2 +5V comment: BT1 GROUND comment: BC2 GROUND comment: comment: (ALL PINS ARE USED). comment: comment: pins: PINS pins: 1 I BA1 CARRY IN-N, (TO E9-5 7482 C0) C-N TO ADDER2 pins: 2 I AL2 AND-NOR ENABLE: TAC TAC3 TO PIN BB2 (TO ADDER3) TAC2 TO PIN AN2 (TO ADDER2) pins: 3 I AP1 AND-NOR ENABLE: TMA SETUP (TMAS)3 TO PIN BB2 (TO ADDER3), (TMAS)3 TO PIN AN2 (TO ADDER2) pins: 4 I AS2 AND-NOR ENABLE: TMA TMA3 TO PIN BB2 (TO ADDER3), TMA2 TO PIN AN2 (TO ADDER2) pins: 5 I AL1 AND-NOR ENABLE: PIN AF2 TO PIN BB2 (TO ADDER3), PIN AM1 TO PIN AN2 (TO ADDER2) pins: 6 I AF2 AND-NOR INPUT (AL1 ENABLES) TO PIN BB2 (TO ADDER3). pins: 7 I AM1 AND-NOR INPUT (AL1 ENABLES) TO PIN AN2 (TO ADDER2) pins: 8 I AD2 AND-NOR ENABLE: RWB RWB3 TO PIN BB2 (TO ADDER3), RWB2 TO PIN AN2 (TO ADDER2) pins: 9 I AE2 AND-NOR ENABLE: PIN AE1 TO PIN BB2 (TO ADDER3), PIN AM2 TO PIN AN2 (TO ADDER2) pins: 10 I AE1 AND-NOR INPUT (AE2 ENABLES) TO PIN BB2 (TO ADDER3). pins: 11 I AM2 AND-NOR INPUT (AE2 ENABLES) TO PIN AN2 (TO ADDER2) pins: 12 I AC1 AND-NOR INPUT, AND WITH PIN AB2 TO PIN BB2 (TO ADDER3) pins: 13 I AB2 AND-NOR INPUT, AND WITH PIN AC1 TO PIN BB2 (TO ADDER3) pins: 14 I AF1 AND-NOR INPUT (AND WITH ITSELF) TO PIN BB2 (TO ADDER3) pins: 15 I AR2 AND-NOR INPUT, AND WITH PIN AS1 TO PIN AN2 (TO ADDER2) pins: 16 I AS1 AND-NOR INPUT, AND WITH PIN AR2 TO PIN AN2 (TO ADDER2) pins: 17 I AP2 AND-NOR INPUT (AND WITH ITSELF) TO PIN AN2 (TO ADDER2) pins: 18 I BK1 AND-NOR ENABLE: TB3 TO PIN BB1 (TO ADDER3), TB2 TO PIN BN1 (TO ADDER2) pins: 19 I BL1 AND-NOR ENABLE: PIN BE1 TO PIN BB1 (TO ADDER3), PIN BM1 TO PIN BN1 (TO ADDER2) pins: 20 I BE1 AND-NOR INPUT (BL1 ENABLES) TO PIN BB1 (TO ADDER3). pins: 21 I BM1 AND-NOR INPUT (BL1 ENABLES) TO PIN BN1 (TO ADDER2) pins: 22 I BF1 AND-NOR ENABLE: PIN BH1 TO PIN BB1 (TO ADDER3), PIN BR1 TO PIN BN1 (TO ADDER2) pins: 23 I BH1 AND-NOR INPUT (BF1 ENABLES): TO PIN BB1 (TO ADDER3), pins: 24 I BR1 AND-NOR INPUT (BF1 ENABLES): TO PIN BN1 (TO ADDER2) pins: 25 I BS1 AND-NOR ENABLE: PIN BC1 TO PIN BB1 (TO ADDER3), PIN BJ2 TO PIN BN1 (TO ADDER2) pins: 26 I BC1 AND-NOR INPUT (BS1 ENABLES): TO PIN BB1 (TO ADDER3), pins: 27 I BJ2 AND-NOR INPUT (BS1 ENABLES): TO PIN BN1 (TO ADDER2) pins: 28 I BL2 AND-NOR ENABLE: PIN BJ1 TO PIN BB1 (TO ADDER3), PIN BK2 TO PIN BN1 (TO ADDER2) pins: 29 I BJ1 AND-NOR INPUT (BL2 ENABLES): TO PIN BB1 (TO ADDER3), pins: 30 I BK2 AND-NOR INPUT (BL2 ENABLES): TO PIN BN1 (TO ADDER2) pins: 31 I BU1 AND-NOR ENABLE: PIN BH2 TO PIN BB1 (TO ADDER3), PIN BP2 TO PIN BN1 (TO ADDER2) pins: 32 I BH2 AND-NOR INPUT (BU1 ENABLES): TO PIN BB1 (TO ADDER3), pins: 33 I BP2 AND-NOR INPUT (BU1 ENABLES): TO PIN BN1 (TO ADDER2) pins: 34 I BN2 AND-NOR INPUT (AND WITH BM2): TO PIN BN1 (TO ADDER2) pins: 35 I BM2 AND-NOR INPUT (AND WITH BM2): TO PIN BN1 (TO ADDER2) pins: 36 O BB2 AND-NOR OUTPUT, (DRIVES E9-2 7482 A1) TO ADDER3 INPUT pins: 37 O BB1 AND-NOR OUTPUT, (DRIVES E9-3 7482 B1) TO ADDER3 INPUT pins: 38 O BN1 AND-NOR OUTPUT, (DRIVES E9-14 7482 A2) TO ADDER2 INPUT pins: 39 O AN2 AND-NOR OUTPUT, (DRIVES E9-13 7482 B2) TO ADDER2 INPUT pins: 40 O AV2 CARRY OUT-N (E9-10 7482 C2) pins: 41 O BV2 TAPE BUS 2 OUTPUT (INVERTED ADDER2 SUM-N (E9-12 7482 SUM2) pins: 42 O BR2 TAPE BUS 3 OUTPUT (INVERTED ADDER3 SUM-N (E9-1 7482 SUM1) pins: 43 I AK1 LOAD TMA SETUP (FROM TAPE BUS) (RISING EDGE CLOCK) pins: 44 O AR1 TMA SETUP 2 pins: 45 O AH1 TMA SETUP 3 pins: 46 I AU2 LOAD TMA (FROM TAPE BUS) (RISING EDGE CLOCK) pins: 47 O AT2 TMA 2 pins: 48 O AD1 TMA 3 pins: 49 I AJ1 LOAD TBN (FROM TAPE BUS) (RISING EDGE CLOCK) pins: 50 O AU1 TBN 2 pins: 51 O AK2 TBN 3 pins: 52 I AA1 LOAD TAC (FROM TAPE BUS) (RISING EDGE CLOCK) pins: 53 O AN1 TAC 2 pins: 54 O AJ2 TAC 2-N pins: 55 O AH2 TAC 3 pins: 56 O AB1 TAC 3-N pins: 57 I BT2 LOAD TB (FROM TAPE BUS) (RISING EDGE CLOCK) pins: 58 O BP1 TB 2 pins: 59 O BD1 TB 3 pins: 60 I BF2 LOAD RWB (FROM TB) (JAMS CLEAR,SET) pins: 61 I BS2 PHASE (SELECTS POLARITY OF RWB OUT, 0 -> INVERTED) pins: 62 I AV1 RWB IN (SHIFTED INTO RWB 3) pins: 63 I BE2 SHIFT RWB (SHIFTS PIN AV1 INTO RWB 3, SHIFTS RWB3 TO RWB2) (RISING CLOCK) pins: 64 O BV1 RWB OUT (IF PHASE=1, =RWB 2; IF PHASE=0; =RWB 2-N) pins: 65 O BD2 RWB 3 pins: 66 O BU2 +3.5V pins: direction: IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIOOOOOOOIOOIOOIOOIOOOOIOOIIIIOOO comment: ; all registers are unknown comment: ; turn on C0, PHASE comment: ; with no ENABLES, BUS2,BUS3 is 11, C2 is 1 test 1: 1000000000000000000000000000000000011111000XX0XX0XX0XXXX0XX0110XX1 comment: comment: ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; comment: ; comment: ; set all registers LOW comment: ; comment: ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; comment: comment: ; load TMA SETUP from tape bus (00) test 2: 100 test 3: 0 comment: ; load TMA from tape bus (00) test 4: 100 test 5: 0 comment: ; load TBN from tape bus (00) test 6: 100 test 7: 0 comment: ; load TAC from tape bus (00) test 8: 10101 test 9: 0 comment: ; load TB from tape bus (00) test 10: 100 test 11: 0 comment: ; load RWB from TB (JAMS CLEAR AND PRESET) test 12: 1 00 test 13: 0 comment: ; (no change) test 14: 100000000000000000000000000000000001111100000000000001010000110001 comment: comment: comment: ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; comment: ; comment: ; set all registers HIGH comment: ; comment: ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; comment: comment: ; set pin AF1 which clears pin BB2 and sets pin BR2 TAPE BUS 3 OUTPUT test 15: 1 0 1 comment: ; set pin AP2 which clears pin AN2 and sets pin BV2 TAPE BUS 2 OUTPUT test 16: 1 0 1 comment: comment: comment: ; load TMA SETUP from tape bus (11) test 17: 111 test 18: 0 comment: ; load TMA from tape bus (11) test 19: 111 test 20: 0 comment: ; load TBN from tape bus (11) test 21: 111 test 22: 0 comment: ; load TAC from tape bus (11) test 23: 11010 test 24: 0 comment: ; load TB from tape bus (11) test 25: 111 test 26: 0 comment: ; load RWB from TB (JAMS CLEAR AND PRESET) test 27: 1 11 test 28: 0 comment: ; clear pin AF1 (AND with itself) to set pin BB2 (AND-NOR output) and clear pin BR2 TAPE BUS 3 OUTPUT test 29: 0 1 0 comment: ; clear pin AP2 (AND with itself) to set pin AN2 (AND-NOR output) and clear pin BV2 TAPE BUS 2 OUTPUT test 30: 0 1 0 comment: ; (no change) test 31: 100000000000000000000000000000000001111100011011011010100110110111 comment: comment: ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; comment: ; comment: ; will all registers high, walk a 0 comment: ; comment: ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; comment: comment: comment: ; walk a 0, TMA SETUP 2 comment: comment: comment: ; clear pin AP2 which sets pin AN2 and clears pin BV2 TAPE BUS 2 OUTPUT test 32: 0 1 0 comment: ; set pin AF1 which clears pin BB2 and sets pin BR2 TAPE BUS 3 OUTPUT test 33: 1 0 1 comment: ; load TMA SETUP from tape bus (01) test 34: 101 test 35: 0 comment: ; restore TMA SETUP 2 comment: ; set pin AP2 which clears pin AN2 and sets pin BV2 TAPE BUS 2 OUTPUT test 36: 1 0 1 comment: ; load TMA SETUP from tape bus (11) test 37: 111 test 38: 0 comment: comment: comment: ; walk a 0, TMA SETUP 3 comment: comment: comment: ; set pin AP2 which clears pin AN2 and sets pin BV2 TAPE BUS 2 OUTPUT test 39: 1 0 1 comment: ; clear pin AF1 which sets pin BB2 and clears pin BR2 TAPE BUS 3 OUTPUT test 40: 0 1 0 comment: ; load TMA SETUP from tape bus (10) test 41: 110 test 42: 0 comment: ; restore TMA SETUP 3 comment: ; set pin AF1 which clears pin BB2 and sets pin BR2 TAPE BUS 3 OUTPUT test 43: 1 0 1 comment: ; load TMA SETUP from tape bus (11) test 44: 111 test 45: 0 comment: comment: comment: ; walk a 0, TMA 2 comment: comment: comment: ; clear pin AP2 which sets pin AN2 and clears pin BV2 TAPE BUS 2 OUTPUT test 46: 0 1 0 comment: ; set pin AF1 which clears pin BB2 and sets pin BR2 TAPE BUS 3 OUTPUT test 47: 1 0 1 comment: ; load TMA from tape bus (01) test 48: 101 test 49: 0 comment: ; restore TMA 2 comment: ; set pin AP2 which clears pin AN2 and sets pin BV2 TAPE BUS 2 OUTPUT test 50: 1 0 1 comment: ; load TMA from tape bus (11) test 51: 111 test 52: 0 comment: comment: comment: ; walk a 0, TMA 3 comment: comment: comment: ; set pin AP2 which clears pin AN2 and sets pin BV2 TAPE BUS 2 OUTPUT test 53: 1 0 1 comment: ; clear pin AF1 which sets pin BB2 and clears pin BR2 TAPE BUS 3 OUTPUT test 54: 0 1 0 comment: ; load TMA from tape bus (10) test 55: 110 test 56: 0 comment: ; restore TMA 3 comment: ; set pin AF1 which clears pin BB2 and sets pin BR2 TAPE BUS 3 OUTPUT test 57: 1 0 1 comment: ; load TMA from tape bus (11) test 58: 111 test 59: 0 comment: comment: comment: ; walk a 0, TBN 2 comment: comment: comment: ; clear pin AP2 which sets pin AN2 and clears pin BV2 TAPE BUS 2 OUTPUT test 60: 0 1 0 comment: ; set pin AF1 which clears pin BB2 and sets pin BR2 TAPE BUS 3 OUTPUT test 61: 1 0 1 comment: ; load TBN from tape bus (01) test 62: 101 test 63: 0 comment: ; restore TBN 2 comment: ; set pin AP2 which clears pin AN2 and sets pin BV2 TAPE BUS 2 OUTPUT test 64: 1 0 1 comment: ; load TBN from tape bus (11) test 65: 111 test 66: 0 comment: comment: comment: ; walk a 0, TBN 3 comment: comment: comment: ; set pin AP2 which clears pin AN2 and sets pin BV2 TAPE BUS 2 OUTPUT test 67: 1 0 1 comment: ; clear pin AF1 which sets pin BB2 and clears pin BR2 TAPE BUS 3 OUTPUT test 68: 0 1 0 comment: ; load TBN from tape bus (10) test 69: 110 test 70: 0 comment: ; restore TBN 3 comment: ; set pin AF1 which clears pin BB2 and sets pin BR2 TAPE BUS 3 OUTPUT test 71: 1 0 1 comment: ; load TBN from tape bus (11) test 72: 111 test 73: 0 comment: comment: comment: comment: comment: comment: comment: comment: comment: comment: comment: comment: comment: comment: comment: comment: comment: comment: comment: ; load TAC from tape bus (00) test 74: 10101 test 75: 0 comment: ; load TB from tape bus (00) test 76: 100 test 77: 0 comment: ; load RWB from TB (JAMS CLEAR AND PRESET) test 78: 1 00 test 79: 0 comment: comment: comment: comment: comment: comment: comment: comment: comment: comment: comment: comment: comment: comment: comment: ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; comment: ; comment: ; test AND-NOR logic comment: ; comment: ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; comment: comment: ; (all registers are HIGH) comment: ; set all pins HIGH except ENABLES comment: comment: ; set pin AF2 HIGH test 80: 1 comment: ; set pin AM1 HIGH test 81: 1 comment: ; set pin AE1 HIGH test 82: 1 comment: ; set pin AM2 HIGH test 83: 1 comment: ; set pin AB2 HIGH test 84: 1 comment: ; set pin AS1 HIGH test 85: 1 comment: ; set pin BE1 HIGH test 86: 1 comment: ; set pin BM1 HIGH test 87: 1 comment: ; set pin BH1 HIGH test 88: 1 comment: ; set pin BR1 HIGH test 89: 1 comment: ; set pin BC1 HIGH test 90: 1 comment: ; set pin BJ2 HIGH test 91: 1 comment: ; set pin BJ1 HIGH test 92: 1 comment: ; set pin BK2 HIGH test 93: 1 comment: ; set pin BH2 HIGH test 94: 1 comment: ; set pin BP2 HIGH test 95: 1 comment: ; set pin BN2 HIGH test 96: 1 comment: ; toggle each ENABLE comment: comment: ; set pin AL2 to clear pin BB2 and pin AN2 AND-NOR OUTPUTS and set TAPE BUS 2 OUTPUT and TAPE BUS 3 OUTPUT test 97: 1 0 0 11 test 98: 0 1 1 00 comment: ; set pin AP1 to clear pin BB2 and pin AN2 AND-NOR OUTPUTS and set TAPE BUS 2 OUTPUT and TAPE BUS 3 OUTPUT test 99: 1 0 0 11 test 100: 0 1 1 00 comment: ; set pin AS2 to clear pin BB2 and pin AN2 AND-NOR OUTPUTS and set TAPE BUS 2 OUTPUT and TAPE BUS 3 OUTPUT test 101: 1 0 0 11 test 102: 0 1 1 00 comment: ; set pin AL1 to clear pin BB2 and pin AN2 AND-NOR OUTPUTS and set TAPE BUS 2 OUTPUT and TAPE BUS 3 OUTPUT test 103: 1 0 0 11 test 104: 0 1 1 00 comment: ; set pin AL1 to clear pin BB2 and pin AN2 AND-NOR OUTPUTS and set TAPE BUS 2 OUTPUT and TAPE BUS 3 OUTPUT test 105: 1 0 0 11 test 106: 0 1 1 00 comment: ; set pin AE2 to clear pin BB2 and pin AN2 AND-NOR OUTPUTS and set TAPE BUS 2 OUTPUT and TAPE BUS 3 OUTPUT test 107: 1 0 0 11 test 108: 0 1 1 00 comment: ; set pin AC1 to clear pin BB2 and set TAPE BUS 3 OUTPUT test 109: 1 0 1 test 110: 0 1 0 comment: ; set pin AF1 to clear pin BB2 and set TAPE BUS 3 OUTPUT test 111: 1 0 1 test 112: 0 1 0 comment: ; set pin AR2 to clear pin AN2 AND-NOR OUTPUTS and set TAPE BUS 2 OUTPUT test 113: 1 0 1 test 114: 0 1 0 comment: ; set pin AP2 to clear pin AN2 AND-NOR OUTPUTS and set TAPE BUS 2 OUTPUT test 115: 1 0 1 test 116: 0 1 0 comment: comment: ; set pin BK1 to clear pin BB1 and pin BN1 AND-NOR OUTPUTS and set TAPE BUS 2 OUTPUT and TAPE BUS 3 OUTPUT test 117: 1 00 11 test 118: 0 11 00 comment: ; set pin BL1 to clear pin BB1 and pin BN1 AND-NOR OUTPUTS and set TAPE BUS 2 OUTPUT and TAPE BUS 3 OUTPUT test 119: 1 00 11 test 120: 0 11 00 comment: ; set pin BF1 to clear pin BB1 and pin BN1 AND-NOR OUTPUTS and set TAPE BUS 2 OUTPUT and TAPE BUS 3 OUTPUT test 121: 1 00 11 test 122: 0 11 00 comment: ; set pin BS1 to clear pin BB1 and pin BN1 AND-NOR OUTPUTS and set TAPE BUS 2 OUTPUT and TAPE BUS 3 OUTPUT test 123: 1 00 11 test 124: 0 11 00 comment: ; set pin BL2 to clear pin BB1 and pin BN1 AND-NOR OUTPUTS and set TAPE BUS 2 OUTPUT and TAPE BUS 3 OUTPUT test 125: 1 00 11 test 126: 0 11 00 comment: ; set pin BU1 to clear pin BB1 and pin BN1 AND-NOR OUTPUTS and set TAPE BUS 2 OUTPUT and TAPE BUS 3 OUTPUT test 127: 1 00 11 test 128: 0 11 00 comment: ; set pin BM2 to clear pin BB1 and TAPE BUS 3 OUTPUT test 129: 1 0 1 test 130: 0 1 0 comment: ; no change test 131: 100000000000000000000000000000000001111100011011011010100110110111 comment: comment: ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; comment: ; test shifting the RWB comment: ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; comment: comment: ; shift in 0, expect 10 test 132: 0 test 133: 110 test 134: 0 comment: ; toggle phase should toggle RWB 2 test 135: 0 0 test 136: 1 1 comment: comment: ; shift in 0, expect 00 test 137: 0 test 138: 100 test 139: 0 comment: ; toggle phase should toggle RWB 2 test 140: 0 1 test 141: 1 0 comment: comment: ; shift in 0, expect 00 test 142: 0 test 143: 100 test 144: 0 comment: ; shift in 1, expect 01 test 145: 1 test 146: 101 test 147: 0 comment: ; shift in 1, expect 11 test 148: 1 test 149: 111 test 150: 0 comment: ; shift in 1, expect 11 test 151: 1 test 152: 111 test 153: 0 comment: ; shift in 0, expect 10 test 154: 0 test 155: 110 test 156: 0 comment: ; shift in 1, expect 01 test 157: 1 test 158: 101 test 159: 0 comment: ; shift in 0, expect 10 test 160: 0 test 161: 110 test 162: 0 comment: ; shift in 1, expect 01 test 163: 1 test 164: 101 test 165: 0 comment: ; shift in 1, expect 11 test 166: 1 test 167: 111 test 168: 0 comment: ; no change test 169: 100000000000000000000000000000000001111100011011011010100110110111 comment: comment: ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; comment: ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; comment: ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; comment: ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; comment: ; needs work (more adder tests, more register tests) comment: ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; comment: ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; comment: ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; comment: ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; end: END summary column 1: offset 2, mask 0x2000 column 2: offset 1, mask 0x0002 column 3: offset 1, mask 0x0800 column 4: offset 1, mask 0x0040 column 5: offset 1, mask 0x4000 column 6: offset 0, mask 0x0004 column 7: offset 1, mask 0x2000 column 8: offset 0, mask 0x0010 column 9: offset 0, mask 0x0008 column 10: offset 0, mask 0x0800 column 11: offset 1, mask 0x0004 column 12: offset 0, mask 0x2000 column 13: offset 0, mask 0x0040 column 14: offset 0, mask 0x0400 column 15: offset 1, mask 0x0020 column 16: offset 1, mask 0x0200 column 17: offset 1, mask 0x0010 column 18: offset 3, mask 0x2000 column 19: offset 3, mask 0x1000 column 20: offset 2, mask 0x0200 column 21: offset 3, mask 0x0800 column 22: offset 2, mask 0x0100 column 23: offset 3, mask 0x8000 column 24: offset 3, mask 0x0100 column 25: offset 4, mask 0x8000 column 26: offset 2, mask 0x0800 column 27: offset 3, mask 0x0002 column 28: offset 3, mask 0x0008 column 29: offset 3, mask 0x4000 column 30: offset 3, mask 0x0004 column 31: offset 4, mask 0x2000 column 32: offset 3, mask 0x0001 column 33: offset 3, mask 0x0040 column 34: offset 3, mask 0x0020 column 35: offset 3, mask 0x0010 column 36: offset 2, mask 0x0008 column 37: offset 2, mask 0x1000 column 38: offset 3, mask 0x0400 column 39: offset 1, mask 0x0008 column 40: offset 2, mask 0x0002 column 41: offset 4, mask 0x0008 column 42: offset 3, mask 0x0080 column 43: offset 1, mask 0x8000 column 44: offset 1, mask 0x0400 column 45: offset 0, mask 0x0200 column 46: offset 2, mask 0x0001 column 47: offset 1, mask 0x0080 column 48: offset 0, mask 0x1000 column 49: offset 0, mask 0x0100 column 50: offset 2, mask 0x8000 column 51: offset 1, mask 0x0001 column 52: offset 0, mask 0x8000 column 53: offset 1, mask 0x1000 column 54: offset 0, mask 0x0001 column 55: offset 0, mask 0x0002 column 56: offset 0, mask 0x4000 column 57: offset 4, mask 0x0002 column 58: offset 3, mask 0x0200 column 59: offset 2, mask 0x0400 column 60: offset 2, mask 0x0080 column 61: offset 4, mask 0x0001 column 62: offset 2, mask 0x4000 column 63: offset 2, mask 0x0040 column 64: offset 4, mask 0x1000 column 65: offset 2, mask 0x0020 column 66: offset 4, mask 0x0004 direction bits (1=input) 0x52A3 0x1589 0x943A 0x0680 0x50FC pullup bits (1=pullup) 0x0000 0x0000 0x0000 0x0000 0x0000 test step out_data dont care 1: 0x0000 0x0008 0x700A 0x0400 0x0005 0x5203 0x1481 0x8420 0x0200 0x1000 2: 0x0000 0x8008 0x700A 0x0400 0x0005 0x5003 0x1081 0x8420 0x0200 0x1000 3: 0x0000 0x0008 0x700A 0x0400 0x0005 0x5003 0x1081 0x8420 0x0200 0x1000 4: 0x0000 0x0008 0x700B 0x0400 0x0005 0x4003 0x1001 0x8420 0x0200 0x1000 5: 0x0000 0x0008 0x700A 0x0400 0x0005 0x4003 0x1001 0x8420 0x0200 0x1000 6: 0x0100 0x0008 0x700A 0x0400 0x0005 0x4003 0x1000 0x0420 0x0200 0x1000 7: 0x0000 0x0008 0x700A 0x0400 0x0005 0x4003 0x1000 0x0420 0x0200 0x1000 8: 0xC001 0x0008 0x700A 0x0400 0x0005 0x0000 0x0000 0x0420 0x0200 0x1000 9: 0x4001 0x0008 0x700A 0x0400 0x0005 0x0000 0x0000 0x0420 0x0200 0x1000 10: 0x4001 0x0008 0x700A 0x0400 0x0007 0x0000 0x0000 0x0020 0x0000 0x1000 11: 0x4001 0x0008 0x700A 0x0400 0x0005 0x0000 0x0000 0x0020 0x0000 0x1000 12: 0x4001 0x0008 0x708A 0x0400 0x0005 13: 0x4001 0x0008 0x700A 0x0400 0x0005 14: 0x4001 0x0008 0x700A 0x0400 0x0005 15: 0x4401 0x0008 0x7002 0x0480 0x0005 16: 0x4401 0x0010 0x7002 0x0480 0x000D 17: 0x4601 0x8410 0x7002 0x0480 0x000D 18: 0x4601 0x0410 0x7002 0x0480 0x000D 19: 0x5601 0x0490 0x7003 0x0480 0x000D 20: 0x5601 0x0490 0x7002 0x0480 0x000D 21: 0x5701 0x0491 0xF002 0x0480 0x000D 22: 0x5601 0x0491 0xF002 0x0480 0x000D 23: 0x9602 0x1491 0xF002 0x0480 0x000D 24: 0x1602 0x1491 0xF002 0x0480 0x000D 25: 0x1602 0x1491 0xF402 0x0680 0x000F 26: 0x1602 0x1491 0xF402 0x0680 0x000D 27: 0x1602 0x1491 0xF4A2 0x0680 0x100D 28: 0x1602 0x1491 0xF422 0x0680 0x100D 29: 0x1202 0x1491 0xF42A 0x0600 0x100D 30: 0x1202 0x1489 0xF42A 0x0600 0x1005 31: 0x1202 0x1489 0xF42A 0x0600 0x1005 32: 0x1202 0x1489 0xF42A 0x0600 0x1005 33: 0x1602 0x1489 0xF422 0x0680 0x1005 34: 0x1602 0x9089 0xF422 0x0680 0x1005 35: 0x1602 0x1089 0xF422 0x0680 0x1005 36: 0x1602 0x1091 0xF422 0x0680 0x100D 37: 0x1602 0x9491 0xF422 0x0680 0x100D 38: 0x1602 0x1491 0xF422 0x0680 0x100D 39: 0x1602 0x1491 0xF422 0x0680 0x100D 40: 0x1202 0x1491 0xF42A 0x0600 0x100D 41: 0x1002 0x9491 0xF42A 0x0600 0x100D 42: 0x1002 0x1491 0xF42A 0x0600 0x100D 43: 0x1402 0x1491 0xF422 0x0680 0x100D 44: 0x1602 0x9491 0xF422 0x0680 0x100D 45: 0x1602 0x1491 0xF422 0x0680 0x100D 46: 0x1602 0x1489 0xF422 0x0680 0x1005 47: 0x1602 0x1489 0xF422 0x0680 0x1005 48: 0x1602 0x1409 0xF423 0x0680 0x1005 49: 0x1602 0x1409 0xF422 0x0680 0x1005 50: 0x1602 0x1411 0xF422 0x0680 0x100D 51: 0x1602 0x1491 0xF423 0x0680 0x100D 52: 0x1602 0x1491 0xF422 0x0680 0x100D 53: 0x1602 0x1491 0xF422 0x0680 0x100D 54: 0x1202 0x1491 0xF42A 0x0600 0x100D 55: 0x0202 0x1491 0xF42B 0x0600 0x100D 56: 0x0202 0x1491 0xF42A 0x0600 0x100D 57: 0x0602 0x1491 0xF422 0x0680 0x100D 58: 0x1602 0x1491 0xF423 0x0680 0x100D 59: 0x1602 0x1491 0xF422 0x0680 0x100D 60: 0x1602 0x1489 0xF422 0x0680 0x1005 61: 0x1602 0x1489 0xF422 0x0680 0x1005 62: 0x1702 0x1489 0x7422 0x0680 0x1005 63: 0x1602 0x1489 0x7422 0x0680 0x1005 64: 0x1602 0x1491 0x7422 0x0680 0x100D 65: 0x1702 0x1491 0xF422 0x0680 0x100D 66: 0x1602 0x1491 0xF422 0x0680 0x100D 67: 0x1602 0x1491 0xF422 0x0680 0x100D 68: 0x1202 0x1491 0xF42A 0x0600 0x100D 69: 0x1302 0x1490 0xF42A 0x0600 0x100D 70: 0x1202 0x1490 0xF42A 0x0600 0x100D 71: 0x1602 0x1490 0xF422 0x0680 0x100D 72: 0x1702 0x1491 0xF422 0x0680 0x100D 73: 0x1602 0x1491 0xF422 0x0680 0x100D 74: 0xD601 0x0491 0xF422 0x0680 0x100D 75: 0x5601 0x0491 0xF422 0x0680 0x100D 76: 0x5601 0x0491 0xF022 0x0480 0x100F 77: 0x5601 0x0491 0xF022 0x0480 0x100D 78: 0x5601 0x0491 0xF082 0x0480 0x000D 79: 0x5601 0x0491 0xF002 0x0480 0x000D 80: 0x5605 0x0491 0xF002 0x0480 0x000D 81: 0x5605 0x2491 0xF002 0x0480 0x000D 82: 0x5E05 0x2491 0xF002 0x0480 0x000D 83: 0x5E05 0x2495 0xF002 0x0480 0x000D 84: 0x5E45 0x2495 0xF002 0x0480 0x000D 85: 0x5E45 0x2695 0xF002 0x0480 0x000D 86: 0x5E45 0x2695 0xF202 0x0480 0x000D 87: 0x5E45 0x2695 0xF202 0x0C80 0x000D 88: 0x5E45 0x2695 0xF202 0x8C80 0x000D 89: 0x5E45 0x2695 0xF202 0x8D80 0x000D 90: 0x5E45 0x2695 0xFA02 0x8D80 0x000D 91: 0x5E45 0x2695 0xFA02 0x8D82 0x000D 92: 0x5E45 0x2695 0xFA02 0xCD82 0x000D 93: 0x5E45 0x2695 0xFA02 0xCD86 0x000D 94: 0x5E45 0x2695 0xFA02 0xCD87 0x000D 95: 0x5E45 0x2695 0xFA02 0xCDC7 0x000D 96: 0x5E45 0x2695 0xFA02 0xCDE7 0x000D 97: 0x5E45 0x2697 0xFA02 0xCDE7 0x000D 98: 0x5E45 0x269D 0xFA0A 0xCD67 0x0005 99: 0x5E45 0x2E95 0xFA02 0xCDE7 0x000D 100: 0x5E45 0x269D 0xFA0A 0xCD67 0x0005 101: 0x5E45 0x26D5 0xFA02 0xCDE7 0x000D 102: 0x5E45 0x269D 0xFA0A 0xCD67 0x0005 103: 0x5E45 0x6695 0xFA02 0xCDE7 0x000D 104: 0x5E45 0x269D 0xFA0A 0xCD67 0x0005 105: 0x5E55 0x2695 0xFA02 0xCDE7 0x000D 106: 0x5E45 0x269D 0xFA0A 0xCD67 0x0005 107: 0x5E4D 0x2695 0xFA02 0xCDE7 0x000D 108: 0x5E45 0x269D 0xFA0A 0xCD67 0x0005 109: 0x7E45 0x269D 0xFA02 0xCDE7 0x0005 110: 0x5E45 0x269D 0xFA0A 0xCD67 0x0005 111: 0x5E45 0x269D 0xFA02 0xCDE7 0x0005 112: 0x5A45 0x269D 0xFA0A 0xCD67 0x0005 113: 0x5A45 0x26B5 0xFA0A 0xCD67 0x000D 114: 0x5A45 0x269D 0xFA0A 0xCD67 0x0005 115: 0x5A45 0x2695 0xFA0A 0xCD67 0x000D 116: 0x5A45 0x268D 0xFA0A 0xCD67 0x0005 117: 0x5A45 0x268D 0xEA0A 0xE9E7 0x000D 118: 0x5A45 0x268D 0xFA0A 0xCD67 0x0005 119: 0x5A45 0x268D 0xEA0A 0xD9E7 0x000D 120: 0x5A45 0x268D 0xFA0A 0xCD67 0x0005 121: 0x5A45 0x268D 0xEB0A 0xC9E7 0x000D 122: 0x5A45 0x268D 0xFA0A 0xCD67 0x0005 123: 0x5A45 0x268D 0xEA0A 0xC9E7 0x800D 124: 0x5A45 0x268D 0xFA0A 0xCD67 0x0005 125: 0x5A45 0x268D 0xEA0A 0xC9EF 0x000D 126: 0x5A45 0x268D 0xFA0A 0xCD67 0x0005 127: 0x5A45 0x268D 0xEA0A 0xC9E7 0x200D 128: 0x5A45 0x268D 0xFA0A 0xCD67 0x0005 129: 0x5A45 0x268D 0xFA0A 0xC977 0x000D 130: 0x5A45 0x268D 0xFA0A 0xCD67 0x0005 131: 0x1202 0x1489 0xF42A 0x0600 0x1005 132: 0x1202 0x1489 0xB42A 0x0600 0x1005 133: 0x1202 0x1489 0xB44A 0x0600 0x1005 134: 0x1202 0x1489 0xB40A 0x0600 0x1005 135: 0x1202 0x1489 0xB40A 0x0600 0x0004 136: 0x1202 0x1489 0xB40A 0x0600 0x1005 137: 0x1202 0x1489 0xB40A 0x0600 0x1005 138: 0x1202 0x1489 0xB44A 0x0600 0x0005 139: 0x1202 0x1489 0xB40A 0x0600 0x0005 140: 0x1202 0x1489 0xB40A 0x0600 0x1004 141: 0x1202 0x1489 0xB40A 0x0600 0x0005 142: 0x1202 0x1489 0xB40A 0x0600 0x0005 143: 0x1202 0x1489 0xB44A 0x0600 0x0005 144: 0x1202 0x1489 0xB40A 0x0600 0x0005 145: 0x1202 0x1489 0xF40A 0x0600 0x0005 146: 0x1202 0x1489 0xF46A 0x0600 0x0005 147: 0x1202 0x1489 0xF42A 0x0600 0x0005 148: 0x1202 0x1489 0xF42A 0x0600 0x0005 149: 0x1202 0x1489 0xF46A 0x0600 0x1005 150: 0x1202 0x1489 0xF42A 0x0600 0x1005 151: 0x1202 0x1489 0xF42A 0x0600 0x1005 152: 0x1202 0x1489 0xF46A 0x0600 0x1005 153: 0x1202 0x1489 0xF42A 0x0600 0x1005 154: 0x1202 0x1489 0xB42A 0x0600 0x1005 155: 0x1202 0x1489 0xB44A 0x0600 0x1005 156: 0x1202 0x1489 0xB40A 0x0600 0x1005 157: 0x1202 0x1489 0xF40A 0x0600 0x1005 158: 0x1202 0x1489 0xF46A 0x0600 0x0005 159: 0x1202 0x1489 0xF42A 0x0600 0x0005 160: 0x1202 0x1489 0xB42A 0x0600 0x0005 161: 0x1202 0x1489 0xB44A 0x0600 0x1005 162: 0x1202 0x1489 0xB40A 0x0600 0x1005 163: 0x1202 0x1489 0xF40A 0x0600 0x1005 164: 0x1202 0x1489 0xF46A 0x0600 0x0005 165: 0x1202 0x1489 0xF42A 0x0600 0x0005 166: 0x1202 0x1489 0xF42A 0x0600 0x0005 167: 0x1202 0x1489 0xF46A 0x0600 0x1005 168: 0x1202 0x1489 0xF42A 0x0600 0x1005 169: 0x1202 0x1489 0xF42A 0x0600 0x1005 PINs used (in edge connector order) (G=ground,P=power) SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBB LETTER ABCDEFHJKLMNPRSTUVABCDEFHJKLMNPRSTUVABCDEFHJKLMNPRSTUVABCDEFHJKLMNPRSTUV SIDE 111111111111111111222222222222222222111111111111111111222222222222222222 USAGE IOIOIIOIIIIOIOIGOIPIGIIIOOOIIOIIIOIOIOIOIIIIIIIOOIIGIOPOGOIIIIIIIIIOIIOO UUT has 44 inputs UUT has 22 outputs contains 66 pins/columns 0 pins are not used contains 169 'test steps' M222 PCB REV B SCHEMATIC REV A LINC TAPE REGISTERS TERMINOLOGY- SIGNALS REFER TO PDP12 MAINT VOL4 M222 SCHEMATIC. BUT... DEC USES AND-NOR GATES TO ROUTE THE ADDER A AND B INPUTS, SO... DEC RENAMED THE ADDER TO NEGATIVE LOGIC TERMS (I.E. A-N + B-N + C-N -> SUM-N, C1-N). (NOT THE 7482 DATASHEET NAMES OF A + B + C -> SUM, C1). SO, WITH ALL 'AND ENABLES' LOW, THE AND-NOR OUTPUTS = HIGH. WITH C-L HIGH, THE ADDER OUTPUT IS SUM-N=1, C1-N=1; THE INVERTED ADDER OUTPUT IS LOW (TAPE BUS). AND THERE IS NO CARRY (C1-N IS HI). THE TWO ADDERS, TWO REGISTER BITS, ETC ARE LABELED BIT 2 (EVEN, MSB) AND BIT 3 (ODD, LSB). THE ADDERS ARE REFERRED TO AS 'ADDER2' (MSB) AND 'ADDER3' (LSB). POWER PINS: AA2 +5V AT1 GROUND AC2 GROUND BA2 +5V BT1 GROUND BC2 GROUND (ALL PINS ARE USED). PINS Main menu Thu Aug 20 18:00:12 2015 test file is: tests\m222.new delay is: 0 trigger is: 1 1 read test file 2 set test delay 3 set test trigger 4 run test 5 output loading test 8 diags 9 exit UUT power is okay Thu Aug 20 18:00:13 2015 space single step O run once (one test, all steps) F run, stop on fail G go (run tests N run, stop on fail, no print S scope (run, no print) C toggle comment printout + increase speed (less delay) - decrease speed (more delay)(slower) Q quit test comment_flag is 1 space single step O run once (one test, all steps) F run, stop on fail G go (run tests N run, stop on fail, no print S scope (run, no print) C toggle comment printout + increase speed (less delay) - decrease speed (more delay)(slower) Q quit test source: ; all registers are unknown source: ; turn on C0, PHASE source: ; with no ENABLES, BUS2,BUS3 is 11, C2 is 1 source: 1000000000000000000000000000000000011111000XX0XX0XX0XXXX0XX0110XX1 changed: step 1 100000000000000000000000000000000001111100010010011010010100110101 source: source: ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; source: ; source: ; set all registers LOW source: ; source: ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; source: source: ; load TMA SETUP from tape bus (00) source: 100 changed: 10 step 2 100000000000000000000000000000000001111100100010011010010100110101 source: 0 changed: 0 step 3 100000000000000000000000000000000001111100000010011010010100110101 source: ; load TMA from tape bus (00) source: 100 changed: 10 step 4 100000000000000000000000000000000001111100000100011010010100110101 source: 0 changed: 0 step 5 100000000000000000000000000000000001111100000000011010010100110101 source: ; load TBN from tape bus (00) source: 100 changed: 100 step 6 100000000000000000000000000000000001111100000000100010010100110101 source: 0 changed: 0 step 7 100000000000000000000000000000000001111100000000000010010100110101 source: ; load TAC from tape bus (00) source: 10101 changed: 101 step 8 100000000000000000000000000000000001111100000000000101010100110101 source: 0 changed: 0 step 9 100000000000000000000000000000000001111100000000000001010100110101 source: ; load TB from tape bus (00) source: 100 changed: 10 step 10 100000000000000000000000000000000001111100000000000001011000110101 source: 0 changed: 0 step 11 100000000000000000000000000000000001111100000000000001010000110101 source: ; load RWB from TB (JAMS CLEAR AND PRESET) source: 1 00 changed: 1 0 step 12 100000000000000000000000000000000001111100000000000001010001110001 source: 0 changed: 0 step 13 100000000000000000000000000000000001111100000000000001010000110001 source: ; (no change) source: 100000000000000000000000000000000001111100000000000001010000110001 changed: step 14 100000000000000000000000000000000001111100000000000001010000110001 source: source: source: ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; source: ; source: ; set all registers HIGH source: ; source: ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; source: source: ; set pin AF1 which clears pin BB2 and sets pin BR2 TAPE BUS 3 OUTPUT source: 1 0 1 changed: 1 0 1 step 15 100000000000010000000000000000000000111101000000000001010000110001 source: ; set pin AP2 which clears pin AN2 and sets pin BV2 TAPE BUS 2 OUTPUT source: 1 0 1 changed: 1 0 1 step 16 100000000000010010000000000000000000110111000000000001010000110001 source: source: source: ; load TMA SETUP from tape bus (11) source: 111 changed: 111 step 17 100000000000010010000000000000000000110111111000000001010000110001 source: 0 changed: 0 step 18 100000000000010010000000000000000000110111011000000001010000110001 source: ; load TMA from tape bus (11) source: 111 changed: 111 step 19 100000000000010010000000000000000000110111011111000001010000110001 source: 0 changed: 0 step 20 100000000000010010000000000000000000110111011011000001010000110001 source: ; load TBN from tape bus (11) source: 111 changed: 111 step 21 100000000000010010000000000000000000110111011011111001010000110001 source: 0 changed: 0 step 22 100000000000010010000000000000000000110111011011011001010000110001 source: ; load TAC from tape bus (11) source: 11010 changed: 11010 step 23 100000000000010010000000000000000000110111011011011110100000110001 source: 0 changed: 0 step 24 100000000000010010000000000000000000110111011011011010100000110001 source: ; load TB from tape bus (11) source: 111 changed: 111 step 25 100000000000010010000000000000000000110111011011011010101110110001 source: 0 changed: 0 step 26 100000000000010010000000000000000000110111011011011010100110110001 source: ; load RWB from TB (JAMS CLEAR AND PRESET) source: 1 11 changed: 1 11 step 27 100000000000010010000000000000000000110111011011011010100111110111 source: 0 changed: 0 step 28 100000000000010010000000000000000000110111011011011010100110110111 source: ; clear pin AF1 (AND with itself) to set pin BB2 (AND-NOR output) and clear pin BR2 TAPE BUS 3 OUTPUT source: 0 1 0 changed: 0 1 0 step 29 100000000000000010000000000000000001110110011011011010100110110111 source: ; clear pin AP2 (AND with itself) to set pin AN2 (AND-NOR output) and clear pin BV2 TAPE BUS 2 OUTPUT source: 0 1 0 changed: 0 1 0 step 30 100000000000000000000000000000000001111100011011011010100110110111 source: ; (no change) source: 100000000000000000000000000000000001111100011011011010100110110111 changed: step 31 100000000000000000000000000000000001111100011011011010100110110111 source: source: ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; source: ; source: ; will all registers high, walk a 0 source: ; source: ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; source: source: source: ; walk a 0, TMA SETUP 2 source: source: source: ; clear pin AP2 which sets pin AN2 and clears pin BV2 TAPE BUS 2 OUTPUT source: 0 1 0 changed: step 32 100000000000000000000000000000000001111100011011011010100110110111 source: ; set pin AF1 which clears pin BB2 and sets pin BR2 TAPE BUS 3 OUTPUT source: 1 0 1 changed: 1 0 1 step 33 100000000000010000000000000000000000111101011011011010100110110111 source: ; load TMA SETUP from tape bus (01) source: 101 changed: 10 step 34 100000000000010000000000000000000000111101101011011010100110110111 source: 0 changed: 0 step 35 100000000000010000000000000000000000111101001011011010100110110111 source: ; restore TMA SETUP 2 source: ; set pin AP2 which clears pin AN2 and sets pin BV2 TAPE BUS 2 OUTPUT source: 1 0 1 changed: 1 0 1 step 36 100000000000010010000000000000000000110111001011011010100110110111 source: ; load TMA SETUP from tape bus (11) source: 111 changed: 11 step 37 100000000000010010000000000000000000110111111011011010100110110111 source: 0 changed: 0 step 38 100000000000010010000000000000000000110111011011011010100110110111 source: source: source: ; walk a 0, TMA SETUP 3 source: source: source: ; set pin AP2 which clears pin AN2 and sets pin BV2 TAPE BUS 2 OUTPUT source: 1 0 1 changed: step 39 100000000000010010000000000000000000110111011011011010100110110111 source: ; clear pin AF1 which sets pin BB2 and clears pin BR2 TAPE BUS 3 OUTPUT source: 0 1 0 changed: 0 1 0 step 40 100000000000000010000000000000000001110110011011011010100110110111 source: ; load TMA SETUP from tape bus (10) source: 110 changed: 1 0 step 41 100000000000000010000000000000000001110110110011011010100110110111 source: 0 changed: 0 step 42 100000000000000010000000000000000001110110010011011010100110110111 source: ; restore TMA SETUP 3 source: ; set pin AF1 which clears pin BB2 and sets pin BR2 TAPE BUS 3 OUTPUT source: 1 0 1 changed: 1 0 1 step 43 100000000000010010000000000000000000110111010011011010100110110111 source: ; load TMA SETUP from tape bus (11) source: 111 changed: 1 1 step 44 100000000000010010000000000000000000110111111011011010100110110111 source: 0 changed: 0 step 45 100000000000010010000000000000000000110111011011011010100110110111 source: source: source: ; walk a 0, TMA 2 source: source: source: ; clear pin AP2 which sets pin AN2 and clears pin BV2 TAPE BUS 2 OUTPUT source: 0 1 0 changed: 0 1 0 step 46 100000000000010000000000000000000000111101011011011010100110110111 source: ; set pin AF1 which clears pin BB2 and sets pin BR2 TAPE BUS 3 OUTPUT source: 1 0 1 changed: step 47 100000000000010000000000000000000000111101011011011010100110110111 source: ; load TMA from tape bus (01) source: 101 changed: 10 step 48 100000000000010000000000000000000000111101011101011010100110110111 source: 0 changed: 0 step 49 100000000000010000000000000000000000111101011001011010100110110111 source: ; restore TMA 2 source: ; set pin AP2 which clears pin AN2 and sets pin BV2 TAPE BUS 2 OUTPUT source: 1 0 1 changed: 1 0 1 step 50 100000000000010010000000000000000000110111011001011010100110110111 source: ; load TMA from tape bus (11) source: 111 changed: 11 step 51 100000000000010010000000000000000000110111011111011010100110110111 source: 0 changed: 0 step 52 100000000000010010000000000000000000110111011011011010100110110111 source: source: source: ; walk a 0, TMA 3 source: source: source: ; set pin AP2 which clears pin AN2 and sets pin BV2 TAPE BUS 2 OUTPUT source: 1 0 1 changed: step 53 100000000000010010000000000000000000110111011011011010100110110111 source: ; clear pin AF1 which sets pin BB2 and clears pin BR2 TAPE BUS 3 OUTPUT source: 0 1 0 changed: 0 1 0 step 54 100000000000000010000000000000000001110110011011011010100110110111 source: ; load TMA from tape bus (10) source: 110 changed: 1 0 step 55 100000000000000010000000000000000001110110011110011010100110110111 source: 0 changed: 0 step 56 100000000000000010000000000000000001110110011010011010100110110111 source: ; restore TMA 3 source: ; set pin AF1 which clears pin BB2 and sets pin BR2 TAPE BUS 3 OUTPUT source: 1 0 1 changed: 1 0 1 step 57 100000000000010010000000000000000000110111011010011010100110110111 source: ; load TMA from tape bus (11) source: 111 changed: 1 1 step 58 100000000000010010000000000000000000110111011111011010100110110111 source: 0 changed: 0 step 59 100000000000010010000000000000000000110111011011011010100110110111 source: source: source: ; walk a 0, TBN 2 source: source: source: ; clear pin AP2 which sets pin AN2 and clears pin BV2 TAPE BUS 2 OUTPUT source: 0 1 0 changed: 0 1 0 step 60 100000000000010000000000000000000000111101011011011010100110110111 source: ; set pin AF1 which clears pin BB2 and sets pin BR2 TAPE BUS 3 OUTPUT source: 1 0 1 changed: step 61 100000000000010000000000000000000000111101011011011010100110110111 source: ; load TBN from tape bus (01) source: 101 changed: 10 step 62 100000000000010000000000000000000000111101011011101010100110110111 source: 0 changed: 0 step 63 100000000000010000000000000000000000111101011011001010100110110111 source: ; restore TBN 2 source: ; set pin AP2 which clears pin AN2 and sets pin BV2 TAPE BUS 2 OUTPUT source: 1 0 1 changed: 1 0 1 step 64 100000000000010010000000000000000000110111011011001010100110110111 source: ; load TBN from tape bus (11) source: 111 changed: 11 step 65 100000000000010010000000000000000000110111011011111010100110110111 source: 0 changed: 0 step 66 100000000000010010000000000000000000110111011011011010100110110111 source: source: source: ; walk a 0, TBN 3 source: source: source: ; set pin AP2 which clears pin AN2 and sets pin BV2 TAPE BUS 2 OUTPUT source: 1 0 1 changed: step 67 100000000000010010000000000000000000110111011011011010100110110111 source: ; clear pin AF1 which sets pin BB2 and clears pin BR2 TAPE BUS 3 OUTPUT source: 0 1 0 changed: 0 1 0 step 68 100000000000000010000000000000000001110110011011011010100110110111 source: ; load TBN from tape bus (10) source: 110 changed: 1 0 step 69 100000000000000010000000000000000001110110011011110010100110110111 source: 0 changed: 0 step 70 100000000000000010000000000000000001110110011011010010100110110111 source: ; restore TBN 3 source: ; set pin AF1 which clears pin BB2 and sets pin BR2 TAPE BUS 3 OUTPUT source: 1 0 1 changed: 1 0 1 step 71 100000000000010010000000000000000000110111011011010010100110110111 source: ; load TBN from tape bus (11) source: 111 changed: 1 1 step 72 100000000000010010000000000000000000110111011011111010100110110111 source: 0 changed: 0 step 73 100000000000010010000000000000000000110111011011011010100110110111 SLOT BAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBAABBAAAAAAAAAAAAAABBBBBABBBB LETTER ALPSLFMDEEMCBFRSPKLEMFHRSCJLJKUHPNMBBNNVVRKRHUTDJUKANJHBTPDFSVEVDU SIDE 121212122121212121111111112212122222112222111221112112212112212122 DIRECTION IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIOOOOOOOIOOIOOIOOIOOOOIOOIIIIOOO source: source: source: source: source: source: source: source: source: source: source: source: source: source: source: source: source: source: source: ; load TAC from tape bus (00) source: 10101 changed: 1 step 74 100000000000010010000000000000000000110111011011011110100110110111 fail ^^^^ space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C toggle comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT BAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBAABBAAAAAAAAAAAAAABBBBBABBBB LETTER ALPSLFMDEEMCBFRSPKLEMFHRSCJLJKUHPNMBBNNVVRKRHUTDJUKANJHBTPDFSVEVDU SIDE 121212122121212121111111112212122222112222111221112112212112212122 DIRECTION IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIOOOOOOOIOOIOOIOOIOOOOIOOIIIIOOO all fails OOOO was lo 00000000000000000000000000000000000 0 00000000000000000000 000 falling v v v v vvvvvvvvvvvvvv vvv v v rising ^ ^ ^ ^ ^^^^^^^^^^^^^^^ ^^^^ ^^ was hi 1 1 1 111111111111111111111111111 111 total fails 0, total passes 0 Main menu Thu Aug 20 18:00:24 2015 test file is: tests\m222.new delay is: 0 trigger is: 1 1 read test file 2 set test delay 3 set test trigger 4 run test 5 output loading test 8 diags 9 exit Enter test file name? trying to open test file: tests\m222.tst reading test file: tests\m222.tst comment: M222 PCB REV B SCHEMATIC REV A LINC TAPE REGISTERS comment: comment: TERMINOLOGY- SIGNALS REFER TO VOL4 M222 SCHEMATIC. comment: comment: BUT... comment: comment: DEC USES AND-NOR GATES TO ROUTE THE ADDER A AND B INPUTS, SO... comment: DEC RENAMED THE ADDER TO NEGATIVE LOGIC TERMS (I.E. A-N + B-N + C-N -> SUM-N, C1-N). comment: (NOT THE 7482 DATASHEET NAMES OF A + B + C -> SUM, C1). comment: comment: SO, WITH ALL 'AND ENABLES' LOW, THE AND-NOR OUTPUTS = HIGH. comment: WITH C-L HIGH, THE ADDER OUTPUT IS SUM-N=1, C1-N=1; comment: THE INVERTED ADDER OUTPUT IS LOW (TAPE BUS). comment: AND THERE IS NO CARRY (C1-N IS HI). comment: comment: THE TWO ADDERS, TWO REGISTER BITS, ETC ARE LABELED BIT 2 (EVEN, MSB) AND BIT 3 (ODD, LSB). comment: THE ADDERS ARE REFERRED TO AS 'ADDER2' (MSB) AND 'ADDER3' (LSB). comment: comment: POWER PINS: comment: AA2 +5V comment: AT1 GROUND comment: AC2 GROUND comment: BA2 +5V comment: BT1 GROUND comment: BC2 GROUND comment: comment: (ALL PINS ARE USED). comment: comment: pins: PINS pins: 1 I BA1 CARRY IN-N, (TO E9-5 7482 C0) C-N TO ADDER2 pins: 2 I AL2 AND-NOR ENABLE: TAC TAC3 TO PIN BB2 (TO ADDER3) TAC2 TO PIN AN2 (TO ADDER2) pins: 3 I AP1 AND-NOR ENABLE: TMA SETUP (TMAS)3 TO PIN BB2 (TO ADDER3), (TMAS)3 TO PIN AN2 (TO ADDER2) pins: 4 I AS2 AND-NOR ENABLE: TMA TMA3 TO PIN BB2 (TO ADDER3), TMA2 TO PIN AN2 (TO ADDER2) pins: 5 I AL1 AND-NOR ENABLE: PIN AF2 TO PIN BB2 (TO ADDER3), PIN AM1 TO PIN AN2 (TO ADDER2) pins: 6 I AF2 AND-NOR INPUT (AL1 ENABLES) TO PIN BB2 (TO ADDER3). pins: 7 I AM1 AND-NOR INPUT (AL1 ENABLES) TO PIN AN2 (TO ADDER2) pins: 8 I AD2 AND-NOR ENABLE: RWB RWB3 TO PIN BB2 (TO ADDER3), RWB2 TO PIN AN2 (TO ADDER2) pins: 9 I AE2 AND-NOR ENABLE: PIN AE1 TO PIN BB2 (TO ADDER3), PIN AM2 TO PIN AN2 (TO ADDER2) pins: 10 I AE1 AND-NOR INPUT (AE2 ENABLES) TO PIN BB2 (TO ADDER3). pins: 11 I AM2 AND-NOR INPUT (AE2 ENABLES) TO PIN AN2 (TO ADDER2) pins: 12 I AC1 AND-NOR INPUT, AND WITH PIN AB2 TO PIN BB2 (TO ADDER3) pins: 13 I AB2 AND-NOR INPUT, AND WITH PIN AC1 TO PIN BB2 (TO ADDER3) pins: 14 I AF1 AND-NOR INPUT (AND WITH ITSELF) TO PIN BB2 (TO ADDER3) pins: 15 I AR2 AND-NOR INPUT, AND WITH PIN AS1 TO PIN AN2 (TO ADDER2) pins: 16 I AS1 AND-NOR INPUT, AND WITH PIN AR2 TO PIN AN2 (TO ADDER2) pins: 17 I AP2 AND-NOR INPUT (AND WITH ITSELF) TO PIN AN2 (TO ADDER2) pins: 18 I BK1 AND-NOR ENABLE: TB3 TO PIN BB1 (TO ADDER3), TB2 TO PIN BN1 (TO ADDER2) pins: 19 I BL1 AND-NOR ENABLE: PIN BE1 TO PIN BB1 (TO ADDER3), PIN BM1 TO PIN BN1 (TO ADDER2) pins: 20 I BE1 AND-NOR INPUT (BL1 ENABLES) TO PIN BB1 (TO ADDER3). pins: 21 I BM1 AND-NOR INPUT (BL1 ENABLES) TO PIN BN1 (TO ADDER2) pins: 22 I BF1 AND-NOR ENABLE: PIN BH1 TO PIN BB1 (TO ADDER3), PIN BR1 TO PIN BN1 (TO ADDER2) pins: 23 I BH1 AND-NOR INPUT (BF1 ENABLES): TO PIN BB1 (TO ADDER3), pins: 24 I BR1 AND-NOR INPUT (BF1 ENABLES): TO PIN BN1 (TO ADDER2) pins: 25 I BS1 AND-NOR ENABLE: PIN BC1 TO PIN BB1 (TO ADDER3), PIN BJ2 TO PIN BN1 (TO ADDER2) pins: 26 I BC1 AND-NOR INPUT (BS1 ENABLES): TO PIN BB1 (TO ADDER3), pins: 27 I BJ2 AND-NOR INPUT (BS1 ENABLES): TO PIN BN1 (TO ADDER2) pins: 28 I BL2 AND-NOR ENABLE: PIN BJ1 TO PIN BB1 (TO ADDER3), PIN BK2 TO PIN BN1 (TO ADDER2) pins: 29 I BJ1 AND-NOR INPUT (BL2 ENABLES): TO PIN BB1 (TO ADDER3), pins: 30 I BK2 AND-NOR INPUT (BL2 ENABLES): TO PIN BN1 (TO ADDER2) pins: 31 I BU1 AND-NOR ENABLE: PIN BH2 TO PIN BB1 (TO ADDER3), PIN BP2 TO PIN BN1 (TO ADDER2) pins: 32 I BH2 AND-NOR INPUT (BU1 ENABLES): TO PIN BB1 (TO ADDER3), pins: 33 I BP2 AND-NOR INPUT (BU1 ENABLES): TO PIN BN1 (TO ADDER2) pins: 34 I BN2 AND-NOR INPUT (AND WITH BM2): TO PIN BN1 (TO ADDER2) pins: 35 I BM2 AND-NOR INPUT (AND WITH BM2): TO PIN BN1 (TO ADDER2) pins: 36 O BB2 AND-NOR OUTPUT, (DRIVES E9-2 7482 A1) TO ADDER3 INPUT pins: 37 O BB1 AND-NOR OUTPUT, (DRIVES E9-3 7482 B1) TO ADDER3 INPUT pins: 38 O BN1 AND-NOR OUTPUT, (DRIVES E9-14 7482 A2) TO ADDER2 INPUT pins: 39 O AN2 AND-NOR OUTPUT, (DRIVES E9-13 7482 B2) TO ADDER2 INPUT pins: 40 O AV2 CARRY OUT-N (E9-10 7482 C2) pins: 41 O BV2 TAPE BUS 2 OUTPUT (INVERTED ADDER2 SUM-N (E9-12 7482 SUM2) pins: 42 O BR2 TAPE BUS 3 OUTPUT (INVERTED ADDER3 SUM-N (E9-1 7482 SUM1) pins: 43 I AK1 LOAD TMA SETUP (FROM TAPE BUS) (RISING EDGE CLOCK) pins: 44 O AR1 TMA SETUP 2 pins: 45 O AH1 TMA SETUP 3 pins: 46 I AU2 LOAD TMA (FROM TAPE BUS) (RISING EDGE CLOCK) pins: 47 O AT2 TMA 2 pins: 48 O AD1 TMA 3 pins: 49 I AJ1 LOAD TBN (FROM TAPE BUS) (RISING EDGE CLOCK) pins: 50 O AU1 TBN 2 pins: 51 O AK2 TBN 3 pins: 52 I AA1 LOAD TAC (FROM TAPE BUS) (RISING EDGE CLOCK) pins: 53 O AN1 TAC 2 pins: 54 O AJ2 TAC 2-N pins: 55 O AH2 TAC 3 pins: 56 O AB1 TAC 3-N pins: 57 I BT2 LOAD TB (FROM TAPE BUS) (RISING EDGE CLOCK) pins: 58 O BP1 TB 2 pins: 59 O BD1 TB 3 pins: 60 I BF2 LOAD RWB (FROM TB) (JAMS CLEAR,SET) pins: 61 I BS2 PHASE (SELECTS POLARITY OF RWB OUT, 0 -> INVERTED) pins: 62 I AV1 RWB IN (SHIFTED INTO RWB 3) pins: 63 I BE2 SHIFT RWB (SHIFTS PIN AV1 INTO RWB 3, SHIFTS RWB3 TO RWB2) (RISING CLOCK) pins: 64 O BV1 RWB OUT (IF PHASE=1, =RWB 2; IF PHASE=0; =RWB 2-N) pins: 65 O BD2 RWB 3 pins: 66 O BU2 +3.5V pins: direction: IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIOOOOOOOIOOIOOIOOIOOOOIOOIIIIOOO comment: ; all registers are unknown comment: ; turn on C0, PHASE comment: ; with no ENABLES, BUS2,BUS3 is 11, C2 is 1 test 1: 1000000000000000000000000000000000011111000XX0XX0XX0XXXX0XX0110XX1 comment: comment: ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; comment: ; comment: ; set all registers LOW comment: ; comment: ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; comment: comment: ; load TMA SETUP from tape bus (00) test 2: 100 test 3: 0 comment: ; load TMA from tape bus (00) test 4: 100 test 5: 0 comment: ; load TBN from tape bus (00) test 6: 100 test 7: 0 comment: ; load TAC from tape bus (00) test 8: 10101 test 9: 0 comment: ; load TB from tape bus (00) test 10: 100 test 11: 0 comment: ; load RWB from TB (JAMS CLEAR AND PRESET) test 12: 1 00 test 13: 0 comment: ; (no change) test 14: 100000000000000000000000000000000001111100000000000001010000110001 comment: comment: comment: ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; comment: ; comment: ; set all registers HIGH comment: ; comment: ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; comment: comment: ; set pin AF1 (AND with itself) to clear pin BB2 (AND-NOR output) and set pin BR2 TAPE BUS 3 OUTPUT test 15: 1 0 1 comment: ; set pin AP2 (AND with itself) to clear pin AN2 (AND-NOR output) and set pin BV2 TAPE BUS 2 OUTPUT test 16: 1 0 1 comment: comment: comment: ; load TMA SETUP from tape bus (11) test 17: 111 test 18: 0 comment: ; load TMA from tape bus (11) test 19: 111 test 20: 0 comment: ; load TBN from tape bus (11) test 21: 111 test 22: 0 comment: ; load TAC from tape bus (11) test 23: 11010 test 24: 0 comment: ; load TB from tape bus (11) test 25: 111 test 26: 0 comment: ; load RWB from TB (JAMS CLEAR AND PRESET) test 27: 1 11 test 28: 0 comment: ; clear pin AF1 (AND with itself) to set pin BB2 (AND-NOR output) and clear pin BR2 TAPE BUS 3 OUTPUT test 29: 0 1 0 comment: ; clear pin AP2 (AND with itself) to set pin AN2 (AND-NOR output) and clear pin BV2 TAPE BUS 2 OUTPUT test 30: 0 1 0 comment: ; (no change) test 31: 100000000000000000000000000000000001111100011011011010100110110111 comment: comment: comment: ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; comment: ; comment: ; test AND-NOR logic comment: ; comment: ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; comment: comment: ; (all registers are HIGH) comment: ; set all pins HIGH except ENABLES comment: comment: ; set pin AF2 HIGH test 32: 1 comment: ; set pin AM1 HIGH test 33: 1 comment: ; set pin AE1 HIGH test 34: 1 comment: ; set pin AM2 HIGH test 35: 1 comment: ; set pin AB2 HIGH test 36: 1 comment: ; set pin AS1 HIGH test 37: 1 comment: ; set pin BE1 HIGH test 38: 1 comment: ; set pin BM1 HIGH test 39: 1 comment: ; set pin BH1 HIGH test 40: 1 comment: ; set pin BR1 HIGH test 41: 1 comment: ; set pin BC1 HIGH test 42: 1 comment: ; set pin BJ2 HIGH test 43: 1 comment: ; set pin BJ1 HIGH test 44: 1 comment: ; set pin BK2 HIGH test 45: 1 comment: ; set pin BH2 HIGH test 46: 1 comment: ; set pin BP2 HIGH test 47: 1 comment: ; set pin BN2 HIGH test 48: 1 comment: ; toggle each ENABLE comment: comment: ; set pin AL2 to clear pin BB2 and pin AN2 AND-NOR OUTPUTS and set TAPE BUS 2 OUTPUT and TAPE BUS 3 OUTPUT test 49: 1 0 0 11 test 50: 0 1 1 00 comment: ; set pin AP1 to clear pin BB2 and pin AN2 AND-NOR OUTPUTS and set TAPE BUS 2 OUTPUT and TAPE BUS 3 OUTPUT test 51: 1 0 0 11 test 52: 0 1 1 00 comment: ; set pin AS2 to clear pin BB2 and pin AN2 AND-NOR OUTPUTS and set TAPE BUS 2 OUTPUT and TAPE BUS 3 OUTPUT test 53: 1 0 0 11 test 54: 0 1 1 00 comment: ; set pin AL1 to clear pin BB2 and pin AN2 AND-NOR OUTPUTS and set TAPE BUS 2 OUTPUT and TAPE BUS 3 OUTPUT test 55: 1 0 0 11 test 56: 0 1 1 00 comment: ; set pin AL1 to clear pin BB2 and pin AN2 AND-NOR OUTPUTS and set TAPE BUS 2 OUTPUT and TAPE BUS 3 OUTPUT test 57: 1 0 0 11 test 58: 0 1 1 00 comment: ; set pin AE2 to clear pin BB2 and pin AN2 AND-NOR OUTPUTS and set TAPE BUS 2 OUTPUT and TAPE BUS 3 OUTPUT test 59: 1 0 0 11 test 60: 0 1 1 00 comment: ; set pin AC1 to clear pin BB2 and set TAPE BUS 3 OUTPUT test 61: 1 0 1 test 62: 0 1 0 comment: ; set pin AF1 to clear pin BB2 and set TAPE BUS 3 OUTPUT test 63: 1 0 1 test 64: 0 1 0 comment: ; set pin AR2 to clear pin AN2 AND-NOR OUTPUTS and set TAPE BUS 2 OUTPUT test 65: 1 0 1 test 66: 0 1 0 comment: ; set pin AP2 to clear pin AN2 AND-NOR OUTPUTS and set TAPE BUS 2 OUTPUT test 67: 1 0 1 test 68: 0 1 0 comment: comment: ; set pin BK1 to clear pin BB1 and pin BN1 AND-NOR OUTPUTS and set TAPE BUS 2 OUTPUT and TAPE BUS 3 OUTPUT test 69: 1 00 11 test 70: 0 11 00 comment: ; set pin BL1 to clear pin BB1 and pin BN1 AND-NOR OUTPUTS and set TAPE BUS 2 OUTPUT and TAPE BUS 3 OUTPUT test 71: 1 00 11 test 72: 0 11 00 comment: ; set pin BF1 to clear pin BB1 and pin BN1 AND-NOR OUTPUTS and set TAPE BUS 2 OUTPUT and TAPE BUS 3 OUTPUT test 73: 1 00 11 test 74: 0 11 00 comment: ; set pin BS1 to clear pin BB1 and pin BN1 AND-NOR OUTPUTS and set TAPE BUS 2 OUTPUT and TAPE BUS 3 OUTPUT test 75: 1 00 11 test 76: 0 11 00 comment: ; set pin BL2 to clear pin BB1 and pin BN1 AND-NOR OUTPUTS and set TAPE BUS 2 OUTPUT and TAPE BUS 3 OUTPUT test 77: 1 00 11 test 78: 0 11 00 comment: ; set pin BU1 to clear pin BB1 and pin BN1 AND-NOR OUTPUTS and set TAPE BUS 2 OUTPUT and TAPE BUS 3 OUTPUT test 79: 1 00 11 test 80: 0 11 00 comment: ; set pin BM2 to clear pin BB1 and TAPE BUS 3 OUTPUT test 81: 1 0 1 test 82: 0 1 0 comment: ; no change test 83: 100000000000000000000000000000000001111100011011011010100110110111 comment: comment: ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; comment: ; test shifting the RWB comment: ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; comment: comment: ; shift in 0, expect 10 test 84: 0 test 85: 110 test 86: 0 comment: ; toggle phase should toggle RWB 2 test 87: 0 0 test 88: 1 1 comment: comment: ; shift in 0, expect 00 test 89: 0 test 90: 100 test 91: 0 comment: ; toggle phase should toggle RWB 2 test 92: 0 1 test 93: 1 0 comment: comment: ; shift in 0, expect 00 test 94: 0 test 95: 100 test 96: 0 comment: ; shift in 1, expect 01 test 97: 1 test 98: 101 test 99: 0 comment: ; shift in 1, expect 11 test 100: 1 test 101: 111 test 102: 0 comment: ; shift in 1, expect 11 test 103: 1 test 104: 111 test 105: 0 comment: ; shift in 0, expect 10 test 106: 0 test 107: 110 test 108: 0 comment: ; shift in 1, expect 01 test 109: 1 test 110: 101 test 111: 0 comment: ; shift in 0, expect 10 test 112: 0 test 113: 110 test 114: 0 comment: ; shift in 1, expect 01 test 115: 1 test 116: 101 test 117: 0 comment: ; shift in 1, expect 11 test 118: 1 test 119: 111 test 120: 0 comment: ; no change test 121: 100000000000000000000000000000000001111100011011011010100110110111 comment: comment: ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; comment: ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; comment: ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; comment: ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; comment: ; needs work (more adder tests, more register tests) comment: ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; comment: ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; comment: ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; comment: ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; end: END summary column 1: offset 2, mask 0x2000 column 2: offset 1, mask 0x0002 column 3: offset 1, mask 0x0800 column 4: offset 1, mask 0x0040 column 5: offset 1, mask 0x4000 column 6: offset 0, mask 0x0004 column 7: offset 1, mask 0x2000 column 8: offset 0, mask 0x0010 column 9: offset 0, mask 0x0008 column 10: offset 0, mask 0x0800 column 11: offset 1, mask 0x0004 column 12: offset 0, mask 0x2000 column 13: offset 0, mask 0x0040 column 14: offset 0, mask 0x0400 column 15: offset 1, mask 0x0020 column 16: offset 1, mask 0x0200 column 17: offset 1, mask 0x0010 column 18: offset 3, mask 0x2000 column 19: offset 3, mask 0x1000 column 20: offset 2, mask 0x0200 column 21: offset 3, mask 0x0800 column 22: offset 2, mask 0x0100 column 23: offset 3, mask 0x8000 column 24: offset 3, mask 0x0100 column 25: offset 4, mask 0x8000 column 26: offset 2, mask 0x0800 column 27: offset 3, mask 0x0002 column 28: offset 3, mask 0x0008 column 29: offset 3, mask 0x4000 column 30: offset 3, mask 0x0004 column 31: offset 4, mask 0x2000 column 32: offset 3, mask 0x0001 column 33: offset 3, mask 0x0040 column 34: offset 3, mask 0x0020 column 35: offset 3, mask 0x0010 column 36: offset 2, mask 0x0008 column 37: offset 2, mask 0x1000 column 38: offset 3, mask 0x0400 column 39: offset 1, mask 0x0008 column 40: offset 2, mask 0x0002 column 41: offset 4, mask 0x0008 column 42: offset 3, mask 0x0080 column 43: offset 1, mask 0x8000 column 44: offset 1, mask 0x0400 column 45: offset 0, mask 0x0200 column 46: offset 2, mask 0x0001 column 47: offset 1, mask 0x0080 column 48: offset 0, mask 0x1000 column 49: offset 0, mask 0x0100 column 50: offset 2, mask 0x8000 column 51: offset 1, mask 0x0001 column 52: offset 0, mask 0x8000 column 53: offset 1, mask 0x1000 column 54: offset 0, mask 0x0001 column 55: offset 0, mask 0x0002 column 56: offset 0, mask 0x4000 column 57: offset 4, mask 0x0002 column 58: offset 3, mask 0x0200 column 59: offset 2, mask 0x0400 column 60: offset 2, mask 0x0080 column 61: offset 4, mask 0x0001 column 62: offset 2, mask 0x4000 column 63: offset 2, mask 0x0040 column 64: offset 4, mask 0x1000 column 65: offset 2, mask 0x0020 column 66: offset 4, mask 0x0004 direction bits (1=input) 0x52A3 0x1589 0x943A 0x0680 0x50FC pullup bits (1=pullup) 0x0000 0x0000 0x0000 0x0000 0x0000 test step out_data dont care 1: 0x0000 0x0008 0x700A 0x0400 0x0005 0x5203 0x1481 0x8420 0x0200 0x1000 2: 0x0000 0x8008 0x700A 0x0400 0x0005 0x5003 0x1081 0x8420 0x0200 0x1000 3: 0x0000 0x0008 0x700A 0x0400 0x0005 0x5003 0x1081 0x8420 0x0200 0x1000 4: 0x0000 0x0008 0x700B 0x0400 0x0005 0x4003 0x1001 0x8420 0x0200 0x1000 5: 0x0000 0x0008 0x700A 0x0400 0x0005 0x4003 0x1001 0x8420 0x0200 0x1000 6: 0x0100 0x0008 0x700A 0x0400 0x0005 0x4003 0x1000 0x0420 0x0200 0x1000 7: 0x0000 0x0008 0x700A 0x0400 0x0005 0x4003 0x1000 0x0420 0x0200 0x1000 8: 0xC001 0x0008 0x700A 0x0400 0x0005 0x0000 0x0000 0x0420 0x0200 0x1000 9: 0x4001 0x0008 0x700A 0x0400 0x0005 0x0000 0x0000 0x0420 0x0200 0x1000 10: 0x4001 0x0008 0x700A 0x0400 0x0007 0x0000 0x0000 0x0020 0x0000 0x1000 11: 0x4001 0x0008 0x700A 0x0400 0x0005 0x0000 0x0000 0x0020 0x0000 0x1000 12: 0x4001 0x0008 0x708A 0x0400 0x0005 13: 0x4001 0x0008 0x700A 0x0400 0x0005 14: 0x4001 0x0008 0x700A 0x0400 0x0005 15: 0x4401 0x0008 0x7002 0x0480 0x0005 16: 0x4401 0x0010 0x7002 0x0480 0x000D 17: 0x4601 0x8410 0x7002 0x0480 0x000D 18: 0x4601 0x0410 0x7002 0x0480 0x000D 19: 0x5601 0x0490 0x7003 0x0480 0x000D 20: 0x5601 0x0490 0x7002 0x0480 0x000D 21: 0x5701 0x0491 0xF002 0x0480 0x000D 22: 0x5601 0x0491 0xF002 0x0480 0x000D 23: 0x9602 0x1491 0xF002 0x0480 0x000D 24: 0x1602 0x1491 0xF002 0x0480 0x000D 25: 0x1602 0x1491 0xF402 0x0680 0x000F 26: 0x1602 0x1491 0xF402 0x0680 0x000D 27: 0x1602 0x1491 0xF4A2 0x0680 0x100D 28: 0x1602 0x1491 0xF422 0x0680 0x100D 29: 0x1202 0x1491 0xF42A 0x0600 0x100D 30: 0x1202 0x1489 0xF42A 0x0600 0x1005 31: 0x1202 0x1489 0xF42A 0x0600 0x1005 32: 0x1206 0x1489 0xF42A 0x0600 0x1005 33: 0x1206 0x3489 0xF42A 0x0600 0x1005 34: 0x1A06 0x3489 0xF42A 0x0600 0x1005 35: 0x1A06 0x348D 0xF42A 0x0600 0x1005 36: 0x1A46 0x348D 0xF42A 0x0600 0x1005 37: 0x1A46 0x368D 0xF42A 0x0600 0x1005 38: 0x1A46 0x368D 0xF62A 0x0600 0x1005 39: 0x1A46 0x368D 0xF62A 0x0E00 0x1005 40: 0x1A46 0x368D 0xF62A 0x8E00 0x1005 41: 0x1A46 0x368D 0xF62A 0x8F00 0x1005 42: 0x1A46 0x368D 0xFE2A 0x8F00 0x1005 43: 0x1A46 0x368D 0xFE2A 0x8F02 0x1005 44: 0x1A46 0x368D 0xFE2A 0xCF02 0x1005 45: 0x1A46 0x368D 0xFE2A 0xCF06 0x1005 46: 0x1A46 0x368D 0xFE2A 0xCF07 0x1005 47: 0x1A46 0x368D 0xFE2A 0xCF47 0x1005 48: 0x1A46 0x368D 0xFE2A 0xCF67 0x1005 49: 0x1A46 0x3687 0xFE22 0xCFE7 0x100D 50: 0x1A46 0x368D 0xFE2A 0xCF67 0x1005 51: 0x1A46 0x3E85 0xFE22 0xCFE7 0x100D 52: 0x1A46 0x368D 0xFE2A 0xCF67 0x1005 53: 0x1A46 0x36C5 0xFE22 0xCFE7 0x100D 54: 0x1A46 0x368D 0xFE2A 0xCF67 0x1005 55: 0x1A46 0x7685 0xFE22 0xCFE7 0x100D 56: 0x1A46 0x368D 0xFE2A 0xCF67 0x1005 57: 0x1A56 0x3685 0xFE22 0xCFE7 0x100D 58: 0x1A46 0x368D 0xFE2A 0xCF67 0x1005 59: 0x1A4E 0x3685 0xFE22 0xCFE7 0x100D 60: 0x1A46 0x368D 0xFE2A 0xCF67 0x1005 61: 0x3A46 0x368D 0xFE22 0xCFE7 0x1005 62: 0x1A46 0x368D 0xFE2A 0xCF67 0x1005 63: 0x1E46 0x368D 0xFE22 0xCFE7 0x1005 64: 0x1A46 0x368D 0xFE2A 0xCF67 0x1005 65: 0x1A46 0x36A5 0xFE2A 0xCF67 0x100D 66: 0x1A46 0x368D 0xFE2A 0xCF67 0x1005 67: 0x1A46 0x3695 0xFE2A 0xCF67 0x100D 68: 0x1A46 0x368D 0xFE2A 0xCF67 0x1005 69: 0x1A46 0x368D 0xEE2A 0xEBE7 0x100D 70: 0x1A46 0x368D 0xFE2A 0xCF67 0x1005 71: 0x1A46 0x368D 0xEE2A 0xDBE7 0x100D 72: 0x1A46 0x368D 0xFE2A 0xCF67 0x1005 73: 0x1A46 0x368D 0xEF2A 0xCBE7 0x100D 74: 0x1A46 0x368D 0xFE2A 0xCF67 0x1005 75: 0x1A46 0x368D 0xEE2A 0xCBE7 0x900D 76: 0x1A46 0x368D 0xFE2A 0xCF67 0x1005 77: 0x1A46 0x368D 0xEE2A 0xCBEF 0x100D 78: 0x1A46 0x368D 0xFE2A 0xCF67 0x1005 79: 0x1A46 0x368D 0xEE2A 0xCBE7 0x300D 80: 0x1A46 0x368D 0xFE2A 0xCF67 0x1005 81: 0x1A46 0x368D 0xFE2A 0xCB77 0x100D 82: 0x1A46 0x368D 0xFE2A 0xCF67 0x1005 83: 0x1202 0x1489 0xF42A 0x0600 0x1005 84: 0x1202 0x1489 0xB42A 0x0600 0x1005 85: 0x1202 0x1489 0xB44A 0x0600 0x1005 86: 0x1202 0x1489 0xB40A 0x0600 0x1005 87: 0x1202 0x1489 0xB40A 0x0600 0x0004 88: 0x1202 0x1489 0xB40A 0x0600 0x1005 89: 0x1202 0x1489 0xB40A 0x0600 0x1005 90: 0x1202 0x1489 0xB44A 0x0600 0x0005 91: 0x1202 0x1489 0xB40A 0x0600 0x0005 92: 0x1202 0x1489 0xB40A 0x0600 0x1004 93: 0x1202 0x1489 0xB40A 0x0600 0x0005 94: 0x1202 0x1489 0xB40A 0x0600 0x0005 95: 0x1202 0x1489 0xB44A 0x0600 0x0005 96: 0x1202 0x1489 0xB40A 0x0600 0x0005 97: 0x1202 0x1489 0xF40A 0x0600 0x0005 98: 0x1202 0x1489 0xF46A 0x0600 0x0005 99: 0x1202 0x1489 0xF42A 0x0600 0x0005 100: 0x1202 0x1489 0xF42A 0x0600 0x0005 101: 0x1202 0x1489 0xF46A 0x0600 0x1005 102: 0x1202 0x1489 0xF42A 0x0600 0x1005 103: 0x1202 0x1489 0xF42A 0x0600 0x1005 104: 0x1202 0x1489 0xF46A 0x0600 0x1005 105: 0x1202 0x1489 0xF42A 0x0600 0x1005 106: 0x1202 0x1489 0xB42A 0x0600 0x1005 107: 0x1202 0x1489 0xB44A 0x0600 0x1005 108: 0x1202 0x1489 0xB40A 0x0600 0x1005 109: 0x1202 0x1489 0xF40A 0x0600 0x1005 110: 0x1202 0x1489 0xF46A 0x0600 0x0005 111: 0x1202 0x1489 0xF42A 0x0600 0x0005 112: 0x1202 0x1489 0xB42A 0x0600 0x0005 113: 0x1202 0x1489 0xB44A 0x0600 0x1005 114: 0x1202 0x1489 0xB40A 0x0600 0x1005 115: 0x1202 0x1489 0xF40A 0x0600 0x1005 116: 0x1202 0x1489 0xF46A 0x0600 0x0005 117: 0x1202 0x1489 0xF42A 0x0600 0x0005 118: 0x1202 0x1489 0xF42A 0x0600 0x0005 119: 0x1202 0x1489 0xF46A 0x0600 0x1005 120: 0x1202 0x1489 0xF42A 0x0600 0x1005 121: 0x1202 0x1489 0xF42A 0x0600 0x1005 PINs used (in edge connector order) (G=ground,P=power) SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBB LETTER ABCDEFHJKLMNPRSTUVABCDEFHJKLMNPRSTUVABCDEFHJKLMNPRSTUVABCDEFHJKLMNPRSTUV SIDE 111111111111111111222222222222222222111111111111111111222222222222222222 USAGE IOIOIIOIIIIOIOIGOIPIGIIIOOOIIOIIIOIOIOIOIIIIIIIOOIIGIOPOGOIIIIIIIIIOIIOO UUT has 44 inputs UUT has 22 outputs contains 66 pins/columns 0 pins are not used contains 121 'test steps' M222 PCB REV B SCHEMATIC REV A LINC TAPE REGISTERS TERMINOLOGY- SIGNALS REFER TO VOL4 M222 SCHEMATIC. BUT... DEC USES AND-NOR GATES TO ROUTE THE ADDER A AND B INPUTS, SO... DEC RENAMED THE ADDER TO NEGATIVE LOGIC TERMS (I.E. A-N + B-N + C-N -> SUM-N, C1-N). (NOT THE 7482 DATASHEET NAMES OF A + B + C -> SUM, C1). SO, WITH ALL 'AND ENABLES' LOW, THE AND-NOR OUTPUTS = HIGH. WITH C-L HIGH, THE ADDER OUTPUT IS SUM-N=1, C1-N=1; THE INVERTED ADDER OUTPUT IS LOW (TAPE BUS). AND THERE IS NO CARRY (C1-N IS HI). THE TWO ADDERS, TWO REGISTER BITS, ETC ARE LABELED BIT 2 (EVEN, MSB) AND BIT 3 (ODD, LSB). THE ADDERS ARE REFERRED TO AS 'ADDER2' (MSB) AND 'ADDER3' (LSB). POWER PINS: AA2 +5V AT1 GROUND AC2 GROUND BA2 +5V BT1 GROUND BC2 GROUND (ALL PINS ARE USED). PINS Main menu Thu Aug 20 18:40:49 2015 test file is: tests\m222.tst delay is: 0 trigger is: 1 1 read test file 2 set test delay 3 set test trigger 4 run test 5 output loading test 8 diags 9 exit UUT power is okay Thu Aug 20 18:40:53 2015 space single step O run once (one test, all steps) F run, stop on fail G go (run tests N run, stop on fail, no print S scope (run, no print) C toggle comment printout + increase speed (less delay) - decrease speed (more delay)(slower) Q quit test comment_flag is 1 space single step O run once (one test, all steps) F run, stop on fail G go (run tests N run, stop on fail, no print S scope (run, no print) C toggle comment printout + increase speed (less delay) - decrease speed (more delay)(slower) Q quit test source: ; all registers are unknown source: ; turn on C0, PHASE source: ; with no ENABLES, BUS2,BUS3 is 11, C2 is 1 source: 1000000000000000000000000000000000011111000XX0XX0XX0XXXX0XX0110XX1 changed: step 1 100000000000000000000000000000000001111100010010010010100100110101 source: source: ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; source: ; source: ; set all registers LOW source: ; source: ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; source: source: ; load TMA SETUP from tape bus (00) source: 100 changed: 10 step 2 100000000000000000000000000000000001111100100010010010100100110101 source: 0 changed: 0 step 3 100000000000000000000000000000000001111100000010010010100100110101 source: ; load TMA from tape bus (00) source: 100 changed: 10 step 4 100000000000000000000000000000000001111100000100010010100100110101 source: 0 changed: 0 step 5 100000000000000000000000000000000001111100000000010010100100110101 source: ; load TBN from tape bus (00) source: 100 changed: 10 step 6 100000000000000000000000000000000001111100000000100010100100110101 source: 0 changed: 0 step 7 100000000000000000000000000000000001111100000000000010100100110101 source: ; load TAC from tape bus (00) source: 10101 changed: 10101 step 8 100000000000000000000000000000000001111100000000000101010100110101 source: 0 changed: 0 step 9 100000000000000000000000000000000001111100000000000001010100110101 source: ; load TB from tape bus (00) source: 100 changed: 10 step 10 100000000000000000000000000000000001111100000000000001011000110101 source: 0 changed: 0 step 11 100000000000000000000000000000000001111100000000000001010000110101 source: ; load RWB from TB (JAMS CLEAR AND PRESET) source: 1 00 changed: 1 0 step 12 100000000000000000000000000000000001111100000000000001010001110001 source: 0 changed: 0 step 13 100000000000000000000000000000000001111100000000000001010000110001 source: ; (no change) source: 100000000000000000000000000000000001111100000000000001010000110001 changed: step 14 100000000000000000000000000000000001111100000000000001010000110001 source: source: source: ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; source: ; source: ; set all registers HIGH source: ; source: ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; source: source: ; set pin AF1 (AND with itself) to clear pin BB2 (AND-NOR output) and set pin BR2 TAPE BUS 3 OUTPUT source: 1 0 1 changed: 1 0 1 step 15 100000000000010000000000000000000000111101000000000001010000110001 source: ; set pin AP2 (AND with itself) to clear pin AN2 (AND-NOR output) and set pin BV2 TAPE BUS 2 OUTPUT source: 1 0 1 changed: 1 0 1 step 16 100000000000010010000000000000000000110111000000000001010000110001 source: source: source: ; load TMA SETUP from tape bus (11) source: 111 changed: 111 step 17 100000000000010010000000000000000000110111111000000001010000110001 source: 0 changed: 0 step 18 100000000000010010000000000000000000110111011000000001010000110001 source: ; load TMA from tape bus (11) source: 111 changed: 111 step 19 100000000000010010000000000000000000110111011111000001010000110001 source: 0 changed: 0 step 20 100000000000010010000000000000000000110111011011000001010000110001 source: ; load TBN from tape bus (11) source: 111 changed: 111 step 21 100000000000010010000000000000000000110111011011111001010000110001 source: 0 changed: 0 step 22 100000000000010010000000000000000000110111011011011001010000110001 source: ; load TAC from tape bus (11) source: 11010 changed: 11010 step 23 100000000000010010000000000000000000110111011011011110100000110001 source: 0 changed: 0 step 24 100000000000010010000000000000000000110111011011011010100000110001 source: ; load TB from tape bus (11) source: 111 changed: 111 step 25 100000000000010010000000000000000000110111011011011010101110110001 source: 0 changed: 0 step 26 100000000000010010000000000000000000110111011011011010100110110001 source: ; load RWB from TB (JAMS CLEAR AND PRESET) source: 1 11 changed: 1 11 step 27 100000000000010010000000000000000000110111011011011010100111110111 source: 0 changed: 0 step 28 100000000000010010000000000000000000110111011011011010100110110111 source: ; clear pin AF1 (AND with itself) to set pin BB2 (AND-NOR output) and clear pin BR2 TAPE BUS 3 OUTPUT source: 0 1 0 changed: 0 1 0 step 29 100000000000000010000000000000000001110110011011011010100110110111 source: ; clear pin AP2 (AND with itself) to set pin AN2 (AND-NOR output) and clear pin BV2 TAPE BUS 2 OUTPUT source: 0 1 0 changed: 0 1 0 step 30 100000000000000000000000000000000001111100011011011010100110110111 source: ; (no change) source: 100000000000000000000000000000000001111100011011011010100110110111 changed: step 31 100000000000000000000000000000000001111100011011011010100110110111 source: source: source: ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; source: ; source: ; test AND-NOR logic source: ; source: ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; source: source: ; (all registers are HIGH) source: ; set all pins HIGH except ENABLES source: source: ; set pin AF2 HIGH source: 1 changed: 1 step 32 100001000000000000000000000000000001111100011011011010100110110111 source: ; set pin AM1 HIGH source: 1 changed: 1 step 33 100001100000000000000000000000000001111100011011011010100110110111 source: ; set pin AE1 HIGH source: 1 changed: 1 step 34 100001100100000000000000000000000001111100011011011010100110110111 source: ; set pin AM2 HIGH source: 1 changed: 1 step 35 100001100110000000000000000000000001111100011011011010100110110111 source: ; set pin AB2 HIGH source: 1 changed: 1 step 36 100001100110100000000000000000000001111100011011011010100110110111 source: ; set pin AS1 HIGH source: 1 changed: 1 step 37 100001100110100100000000000000000001111100011011011010100110110111 source: ; set pin BE1 HIGH source: 1 changed: 1 step 38 100001100110100100010000000000000001111100011011011010100110110111 source: ; set pin BM1 HIGH source: 1 changed: 1 step 39 100001100110100100011000000000000001111100011011011010100110110111 source: ; set pin BH1 HIGH source: 1 changed: 1 step 40 100001100110100100011010000000000001111100011011011010100110110111 source: ; set pin BR1 HIGH source: 1 changed: 1 step 41 100001100110100100011011000000000001111100011011011010100110110111 source: ; set pin BC1 HIGH source: 1 changed: 1 step 42 100001100110100100011011010000000001111100011011011010100110110111 source: ; set pin BJ2 HIGH source: 1 changed: 1 step 43 100001100110100100011011011000000001111100011011011010100110110111 source: ; set pin BJ1 HIGH source: 1 changed: 1 step 44 100001100110100100011011011010000001111100011011011010100110110111 source: ; set pin BK2 HIGH source: 1 changed: 1 step 45 100001100110100100011011011011000001111100011011011010100110110111 source: ; set pin BH2 HIGH source: 1 changed: 1 step 46 100001100110100100011011011011010001111100011011011010100110110111 source: ; set pin BP2 HIGH source: 1 changed: 1 step 47 100001100110100100011011011011011001111100011011011010100110110111 source: ; set pin BN2 HIGH source: 1 changed: 1 step 48 100001100110100100011011011011011101111100011011011010100110110111 source: ; toggle each ENABLE source: source: ; set pin AL2 to clear pin BB2 and pin AN2 AND-NOR OUTPUTS and set TAPE BUS 2 OUTPUT and TAPE BUS 3 OUTPUT source: 1 0 0 11 changed: 1 0 0 11 step 49 110001100110100100011011011011011100110111011011011010100110110111 source: 0 1 1 00 changed: 0 1 1 00 step 50 100001100110100100011011011011011101111100011011011010100110110111 source: ; set pin AP1 to clear pin BB2 and pin AN2 AND-NOR OUTPUTS and set TAPE BUS 2 OUTPUT and TAPE BUS 3 OUTPUT source: 1 0 0 11 changed: 1 0 0 11 step 51 101001100110100100011011011011011100110111011011011010100110110111 source: 0 1 1 00 changed: 0 1 1 00 step 52 100001100110100100011011011011011101111100011011011010100110110111 source: ; set pin AS2 to clear pin BB2 and pin AN2 AND-NOR OUTPUTS and set TAPE BUS 2 OUTPUT and TAPE BUS 3 OUTPUT source: 1 0 0 11 changed: 1 0 0 11 step 53 100101100110100100011011011011011100110111011011011010100110110111 source: 0 1 1 00 changed: 0 1 1 00 step 54 100001100110100100011011011011011101111100011011011010100110110111 source: ; set pin AL1 to clear pin BB2 and pin AN2 AND-NOR OUTPUTS and set TAPE BUS 2 OUTPUT and TAPE BUS 3 OUTPUT source: 1 0 0 11 changed: 1 0 0 11 step 55 100011100110100100011011011011011100110111011011011010100110110111 source: 0 1 1 00 changed: 0 1 1 00 step 56 100001100110100100011011011011011101111100011011011010100110110111 source: ; set pin AL1 to clear pin BB2 and pin AN2 AND-NOR OUTPUTS and set TAPE BUS 2 OUTPUT and TAPE BUS 3 OUTPUT source: 1 0 0 11 changed: 1 0 0 11 step 57 100001110110100100011011011011011100110111011011011010100110110111 source: 0 1 1 00 changed: 0 1 1 00 step 58 100001100110100100011011011011011101111100011011011010100110110111 source: ; set pin AE2 to clear pin BB2 and pin AN2 AND-NOR OUTPUTS and set TAPE BUS 2 OUTPUT and TAPE BUS 3 OUTPUT source: 1 0 0 11 changed: 1 0 0 11 step 59 100001101110100100011011011011011100110111011011011010100110110111 source: 0 1 1 00 changed: 0 1 1 00 step 60 100001100110100100011011011011011101111100011011011010100110110111 source: ; set pin AC1 to clear pin BB2 and set TAPE BUS 3 OUTPUT source: 1 0 1 changed: 1 0 1 step 61 100001100111100100011011011011011100111101011011011010100110110111 source: 0 1 0 changed: 0 1 0 step 62 100001100110100100011011011011011101111100011011011010100110110111 source: ; set pin AF1 to clear pin BB2 and set TAPE BUS 3 OUTPUT source: 1 0 1 changed: 1 0 1 step 63 100001100110110100011011011011011100111101011011011010100110110111 source: 0 1 0 changed: 0 1 0 step 64 100001100110100100011011011011011101111100011011011010100110110111 source: ; set pin AR2 to clear pin AN2 AND-NOR OUTPUTS and set TAPE BUS 2 OUTPUT source: 1 0 1 changed: 1 0 1 step 65 100001100110101100011011011011011101110110011011011010100110110111 source: 0 1 0 changed: 0 1 0 step 66 100001100110100100011011011011011101111100011011011010100110110111 source: ; set pin AP2 to clear pin AN2 AND-NOR OUTPUTS and set TAPE BUS 2 OUTPUT source: 1 0 1 changed: 1 0 1 step 67 100001100110100110011011011011011101110110011011011010100110110111 source: 0 1 0 changed: 0 1 0 step 68 100001100110100100011011011011011101111100011011011010100110110111 source: source: ; set pin BK1 to clear pin BB1 and pin BN1 AND-NOR OUTPUTS and set TAPE BUS 2 OUTPUT and TAPE BUS 3 OUTPUT source: 1 00 11 changed: 1 00 11 step 69 100001100110100101011011011011011101001111011011011010100110110111 source: 0 11 00 changed: 0 11 00 step 70 100001100110100100011011011011011101111100011011011010100110110111 source: ; set pin BL1 to clear pin BB1 and pin BN1 AND-NOR OUTPUTS and set TAPE BUS 2 OUTPUT and TAPE BUS 3 OUTPUT source: 1 00 11 changed: 1 00 11 step 71 100001100110100100111011011011011101001111011011011010100110110111 source: 0 11 00 changed: 0 11 00 step 72 100001100110100100011011011011011101111100011011011010100110110111 source: ; set pin BF1 to clear pin BB1 and pin BN1 AND-NOR OUTPUTS and set TAPE BUS 2 OUTPUT and TAPE BUS 3 OUTPUT source: 1 00 11 changed: 1 00 11 step 73 100001100110100100011111011011011101001111011011011010100110110111 source: 0 11 00 changed: 0 11 00 step 74 100001100110100100011011011011011101111100011011011010100110110111 source: ; set pin BS1 to clear pin BB1 and pin BN1 AND-NOR OUTPUTS and set TAPE BUS 2 OUTPUT and TAPE BUS 3 OUTPUT source: 1 00 11 changed: 1 00 11 step 75 100001100110100100011011111011011101001111011011011010100110110111 source: 0 11 00 changed: 0 11 00 step 76 100001100110100100011011011011011101111100011011011010100110110111 source: ; set pin BL2 to clear pin BB1 and pin BN1 AND-NOR OUTPUTS and set TAPE BUS 2 OUTPUT and TAPE BUS 3 OUTPUT source: 1 00 11 changed: 1 00 11 step 77 100001100110100100011011011111011101001111011011011010100110110111 source: 0 11 00 changed: 0 11 00 step 78 100001100110100100011011011011011101111100011011011010100110110111 source: ; set pin BU1 to clear pin BB1 and pin BN1 AND-NOR OUTPUTS and set TAPE BUS 2 OUTPUT and TAPE BUS 3 OUTPUT source: 1 00 11 changed: 1 00 11 step 79 100001100110100100011011011011111101001111011011011010100110110111 source: 0 11 00 changed: 0 11 00 step 80 100001100110100100011011011011011101111100011011011010100110110111 source: ; set pin BM2 to clear pin BB1 and TAPE BUS 3 OUTPUT source: 1 0 1 changed: 1 0 1 step 81 100001100110100100011011011011011111101110011011011010100110110111 source: 0 1 0 changed: 0 1 0 step 82 100001100110100100011011011011011101111100011011011010100110110111 source: ; no change source: 100000000000000000000000000000000001111100011011011010100110110111 changed: 00 00 0 0 00 00 00 00 000 step 83 100000000000000000000000000000000001111100011011011010100110110111 source: source: ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; source: ; test shifting the RWB source: ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; source: source: ; shift in 0, expect 10 source: 0 changed: 0 step 84 100000000000000000000000000000000001111100011011011010100110100111 source: 110 changed: 1 0 step 85 100000000000000000000000000000000001111100011011011010100110101101 source: 0 changed: 0 step 86 100000000000000000000000000000000001111100011011011010100110100101 source: ; toggle phase should toggle RWB 2 source: 0 0 changed: 0 0 step 87 100000000000000000000000000000000001111100011011011010100110000001 source: 1 1 changed: 1 1 step 88 100000000000000000000000000000000001111100011011011010100110100101 source: source: ; shift in 0, expect 00 source: 0 changed: step 89 100000000000000000000000000000000001111100011011011010100110100101 source: 100 changed: 10 step 90 100000000000000000000000000000000001111100011011011010100110101001 source: 0 changed: 0 step 91 100000000000000000000000000000000001111100011011011010100110100001 source: ; toggle phase should toggle RWB 2 source: 0 1 changed: 0 1 step 92 100000000000000000000000000000000001111100011011011010100110000101 source: 1 0 changed: 1 0 step 93 100000000000000000000000000000000001111100011011011010100110100001 source: source: ; shift in 0, expect 00 source: 0 changed: step 94 100000000000000000000000000000000001111100011011011010100110100001 source: 100 changed: 1 step 95 100000000000000000000000000000000001111100011011011010100110101001 source: 0 changed: 0 step 96 100000000000000000000000000000000001111100011011011010100110100001 source: ; shift in 1, expect 01 source: 1 changed: 1 step 97 100000000000000000000000000000000001111100011011011010100110110001 source: 101 changed: 1 1 step 98 100000000000000000000000000000000001111100011011011010100110111011 source: 0 changed: 0 step 99 100000000000000000000000000000000001111100011011011010100110110011 source: ; shift in 1, expect 11 source: 1 changed: step 100 100000000000000000000000000000000001111100011011011010100110110011 source: 111 changed: 11 step 101 100000000000000000000000000000000001111100011011011010100110111111 source: 0 changed: 0 step 102 100000000000000000000000000000000001111100011011011010100110110111 source: ; shift in 1, expect 11 source: 1 changed: step 103 100000000000000000000000000000000001111100011011011010100110110111 source: 111 changed: 1 step 104 100000000000000000000000000000000001111100011011011010100110111111 source: 0 changed: 0 step 105 100000000000000000000000000000000001111100011011011010100110110111 source: ; shift in 0, expect 10 source: 0 changed: 0 step 106 100000000000000000000000000000000001111100011011011010100110100111 source: 110 changed: 1 0 step 107 100000000000000000000000000000000001111100011011011010100110101101 source: 0 changed: 0 step 108 100000000000000000000000000000000001111100011011011010100110100101 source: ; shift in 1, expect 01 source: 1 changed: 1 step 109 100000000000000000000000000000000001111100011011011010100110110101 source: 101 changed: 101 step 110 100000000000000000000000000000000001111100011011011010100110111011 source: 0 changed: 0 step 111 100000000000000000000000000000000001111100011011011010100110110011 source: ; shift in 0, expect 10 source: 0 changed: 0 step 112 100000000000000000000000000000000001111100011011011010100110100011 source: 110 changed: 110 step 113 100000000000000000000000000000000001111100011011011010100110101101 source: 0 changed: 0 step 114 100000000000000000000000000000000001111100011011011010100110100101 source: ; shift in 1, expect 01 source: 1 changed: 1 step 115 100000000000000000000000000000000001111100011011011010100110110101 source: 101 changed: 101 step 116 100000000000000000000000000000000001111100011011011010100110111011 source: 0 changed: 0 step 117 100000000000000000000000000000000001111100011011011010100110110011 source: ; shift in 1, expect 11 source: 1 changed: step 118 100000000000000000000000000000000001111100011011011010100110110011 source: 111 changed: 11 step 119 100000000000000000000000000000000001111100011011011010100110111111 source: 0 changed: 0 step 120 100000000000000000000000000000000001111100011011011010100110110111 source: ; no change source: 100000000000000000000000000000000001111100011011011010100110110111 changed: step 121 100000000000000000000000000000000001111100011011011010100110110111 test 1: pass SLOT BAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBAABBAAAAAAAAAAAAAABBBBBABBBB LETTER ALPSLFMDEEMCBFRSPKLEMFHRSCJLJKUHPNMBBNNVVRKRHUTDJUKANJHBTPDFSVEVDU SIDE 121212122121212121111111112212122222112222111221112112212112212122 DIRECTION IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIOOOOOOOIOOIOOIOOIOOOOIOOIIIIOOO this fail all fails was hi 111111111111111111111111111111111111111111111111111111111111111111 rising ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ ^^^^^^^^^^^^^^^^^^^^^^^^^ falling vvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvv vvvv vv vv vvvvvvv vvvvvv was lo 00000000000000000000000000000000000000 0000000000000000000000000 total fails 0, total passes 1 source: ; all registers are unknown source: ; turn on C0, PHASE source: ; with no ENABLES, BUS2,BUS3 is 11, C2 is 1 source: 1000000000000000000000000000000000011111000XX0XX0XX0XXXX0XX0110XX1 changed: step 1 100000000000000000000000000000000001111100011011011010100110110111 source: source: ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; source: ; source: ; set all registers LOW source: ; source: ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; source: source: ; load TMA SETUP from tape bus (00) source: 100 changed: 100 step 2 100000000000000000000000000000000001111100100011011010100110110111 source: 0 changed: 0 step 3 100000000000000000000000000000000001111100000011011010100110110111 source: ; load TMA from tape bus (00) source: 100 changed: 100 step 4 100000000000000000000000000000000001111100000100011010100110110111 source: 0 changed: 0 step 5 100000000000000000000000000000000001111100000000011010100110110111 source: ; load TBN from tape bus (00) source: 100 changed: 100 step 6 100000000000000000000000000000000001111100000000100010100110110111 source: 0 changed: 0 step 7 100000000000000000000000000000000001111100000000000010100110110111 source: ; load TAC from tape bus (00) source: 10101 changed: 10101 step 8 100000000000000000000000000000000001111100000000000101010110110111 source: 0 changed: 0 step 9 100000000000000000000000000000000001111100000000000001010110110111 source: ; load TB from tape bus (00) source: 100 changed: 100 step 10 100000000000000000000000000000000001111100000000000001011000110111 source: 0 changed: 0 step 11 100000000000000000000000000000000001111100000000000001010000110111 source: ; load RWB from TB (JAMS CLEAR AND PRESET) source: 1 00 changed: 1 00 step 12 100000000000000000000000000000000001111100000000000001010001110001 source: 0 changed: 0 step 13 100000000000000000000000000000000001111100000000000001010000110001 source: ; (no change) source: 100000000000000000000000000000000001111100000000000001010000110001 changed: step 14 100000000000000000000000000000000001111100000000000001010000110001 source: source: source: ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; source: ; source: ; set all registers HIGH source: ; source: ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; source: source: ; set pin AF1 (AND with itself) to clear pin BB2 (AND-NOR output) and set pin BR2 TAPE BUS 3 OUTPUT source: 1 0 1 changed: 1 0 1 step 15 100000000000010000000000000000000000111101000000000001010000110001 source: ; set pin AP2 (AND with itself) to clear pin AN2 (AND-NOR output) and set pin BV2 TAPE BUS 2 OUTPUT source: 1 0 1 changed: 1 0 1 step 16 100000000000010010000000000000000000110111000000000001010000110001 source: source: source: ; load TMA SETUP from tape bus (11) source: 111 changed: 111 step 17 100000000000010010000000000000000000110111111000000001010000110001 source: 0 changed: 0 step 18 100000000000010010000000000000000000110111011000000001010000110001 source: ; load TMA from tape bus (11) source: 111 changed: 111 step 19 100000000000010010000000000000000000110111011111000001010000110001 source: 0 changed: 0 step 20 100000000000010010000000000000000000110111011011000001010000110001 source: ; load TBN from tape bus (11) source: 111 changed: 111 step 21 100000000000010010000000000000000000110111011011111001010000110001 source: 0 changed: 0 step 22 100000000000010010000000000000000000110111011011011001010000110001 source: ; load TAC from tape bus (11) source: 11010 changed: 11010 step 23 100000000000010010000000000000000000110111011011011110100000110001 source: 0 changed: 0 step 24 100000000000010010000000000000000000110111011011011010100000110001 source: ; load TB from tape bus (11) source: 111 changed: 111 step 25 100000000000010010000000000000000000110111011011011010101110110001 source: 0 changed: 0 step 26 100000000000010010000000000000000000110111011011011010100110110001 source: ; load RWB from TB (JAMS CLEAR AND PRESET) source: 1 11 changed: 1 11 step 27 100000000000010010000000000000000000110111011011011010100111110111 source: 0 changed: 0 step 28 100000000000010010000000000000000000110111011011011010100110110111 source: ; clear pin AF1 (AND with itself) to set pin BB2 (AND-NOR output) and clear pin BR2 TAPE BUS 3 OUTPUT source: 0 1 0 changed: 0 1 0 step 29 100000000000000010000000000000000001110110011011011010100110110111 source: ; clear pin AP2 (AND with itself) to set pin AN2 (AND-NOR output) and clear pin BV2 TAPE BUS 2 OUTPUT source: 0 1 0 changed: 0 1 0 step 30 100000000000000000000000000000000001111100011011011010100110110111 source: ; (no change) source: 100000000000000000000000000000000001111100011011011010100110110111 changed: step 31 100000000000000000000000000000000001111100011011011010100110110111 source: source: source: ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; source: ; source: ; test AND-NOR logic source: ; source: ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; source: source: ; (all registers are HIGH) source: ; set all pins HIGH except ENABLES source: source: ; set pin AF2 HIGH source: 1 changed: 1 step 32 100001000000000000000000000000000001111100011011011010100110110111 source: ; set pin AM1 HIGH source: 1 changed: 1 step 33 100001100000000000000000000000000001111100011011011010100110110111 source: ; set pin AE1 HIGH source: 1 changed: 1 step 34 100001100100000000000000000000000001111100011011011010100110110111 source: ; set pin AM2 HIGH source: 1 changed: 1 step 35 100001100110000000000000000000000001111100011011011010100110110111 source: ; set pin AB2 HIGH source: 1 changed: 1 step 36 100001100110100000000000000000000001111100011011011010100110110111 source: ; set pin AS1 HIGH source: 1 changed: 1 step 37 100001100110100100000000000000000001111100011011011010100110110111 source: ; set pin BE1 HIGH source: 1 changed: 1 step 38 100001100110100100010000000000000001111100011011011010100110110111 source: ; set pin BM1 HIGH source: 1 changed: 1 step 39 100001100110100100011000000000000001111100011011011010100110110111 source: ; set pin BH1 HIGH source: 1 changed: 1 step 40 100001100110100100011010000000000001111100011011011010100110110111 source: ; set pin BR1 HIGH source: 1 changed: 1 step 41 100001100110100100011011000000000001111100011011011010100110110111 source: ; set pin BC1 HIGH source: 1 changed: 1 step 42 100001100110100100011011010000000001111100011011011010100110110111 source: ; set pin BJ2 HIGH source: 1 changed: 1 step 43 100001100110100100011011011000000001111100011011011010100110110111 source: ; set pin BJ1 HIGH source: 1 changed: 1 step 44 100001100110100100011011011010000001111100011011011010100110110111 source: ; set pin BK2 HIGH source: 1 changed: 1 step 45 100001100110100100011011011011000001111100011011011010100110110111 source: ; set pin BH2 HIGH source: 1 changed: 1 step 46 100001100110100100011011011011010001111100011011011010100110110111 source: ; set pin BP2 HIGH source: 1 changed: 1 step 47 100001100110100100011011011011011001111100011011011010100110110111 source: ; set pin BN2 HIGH source: 1 changed: 1 step 48 100001100110100100011011011011011101111100011011011010100110110111 source: ; toggle each ENABLE source: source: ; set pin AL2 to clear pin BB2 and pin AN2 AND-NOR OUTPUTS and set TAPE BUS 2 OUTPUT and TAPE BUS 3 OUTPUT source: 1 0 0 11 changed: 1 0 0 11 step 49 110001100110100100011011011011011100110111011011011010100110110111 source: 0 1 1 00 changed: 0 1 1 00 step 50 100001100110100100011011011011011101111100011011011010100110110111 source: ; set pin AP1 to clear pin BB2 and pin AN2 AND-NOR OUTPUTS and set TAPE BUS 2 OUTPUT and TAPE BUS 3 OUTPUT source: 1 0 0 11 changed: 1 0 0 11 step 51 101001100110100100011011011011011100110111011011011010100110110111 source: 0 1 1 00 changed: 0 1 1 00 step 52 100001100110100100011011011011011101111100011011011010100110110111 source: ; set pin AS2 to clear pin BB2 and pin AN2 AND-NOR OUTPUTS and set TAPE BUS 2 OUTPUT and TAPE BUS 3 OUTPUT source: 1 0 0 11 changed: 1 0 0 11 step 53 100101100110100100011011011011011100110111011011011010100110110111 source: 0 1 1 00 changed: 0 1 1 00 step 54 100001100110100100011011011011011101111100011011011010100110110111 source: ; set pin AL1 to clear pin BB2 and pin AN2 AND-NOR OUTPUTS and set TAPE BUS 2 OUTPUT and TAPE BUS 3 OUTPUT source: 1 0 0 11 changed: 1 0 0 11 step 55 100011100110100100011011011011011100110111011011011010100110110111 source: 0 1 1 00 changed: 0 1 1 00 step 56 100001100110100100011011011011011101111100011011011010100110110111 source: ; set pin AL1 to clear pin BB2 and pin AN2 AND-NOR OUTPUTS and set TAPE BUS 2 OUTPUT and TAPE BUS 3 OUTPUT source: 1 0 0 11 changed: 1 0 0 11 step 57 100001110110100100011011011011011100110111011011011010100110110111 source: 0 1 1 00 changed: 0 1 1 00 step 58 100001100110100100011011011011011101111100011011011010100110110111 source: ; set pin AE2 to clear pin BB2 and pin AN2 AND-NOR OUTPUTS and set TAPE BUS 2 OUTPUT and TAPE BUS 3 OUTPUT source: 1 0 0 11 changed: 1 0 0 11 step 59 100001101110100100011011011011011100110111011011011010100110110111 source: 0 1 1 00 changed: 0 1 1 00 step 60 100001100110100100011011011011011101111100011011011010100110110111 source: ; set pin AC1 to clear pin BB2 and set TAPE BUS 3 OUTPUT source: 1 0 1 changed: 1 0 1 step 61 100001100111100100011011011011011100111101011011011010100110110111 source: 0 1 0 changed: 0 1 0 step 62 100001100110100100011011011011011101111100011011011010100110110111 source: ; set pin AF1 to clear pin BB2 and set TAPE BUS 3 OUTPUT source: 1 0 1 changed: 1 0 1 step 63 100001100110110100011011011011011100111101011011011010100110110111 source: 0 1 0 changed: 0 1 0 step 64 100001100110100100011011011011011101111100011011011010100110110111 source: ; set pin AR2 to clear pin AN2 AND-NOR OUTPUTS and set TAPE BUS 2 OUTPUT source: 1 0 1 changed: 1 0 1 step 65 100001100110101100011011011011011101110110011011011010100110110111 source: 0 1 0 changed: 0 1 0 step 66 100001100110100100011011011011011101111100011011011010100110110111 source: ; set pin AP2 to clear pin AN2 AND-NOR OUTPUTS and set TAPE BUS 2 OUTPUT source: 1 0 1 changed: 1 0 1 step 67 100001100110100110011011011011011101110110011011011010100110110111 source: 0 1 0 changed: 0 1 0 step 68 100001100110100100011011011011011101111100011011011010100110110111 source: source: ; set pin BK1 to clear pin BB1 and pin BN1 AND-NOR OUTPUTS and set TAPE BUS 2 OUTPUT and TAPE BUS 3 OUTPUT source: 1 00 11 changed: 1 00 11 step 69 100001100110100101011011011011011101001111011011011010100110110111 source: 0 11 00 changed: 0 11 00 step 70 100001100110100100011011011011011101111100011011011010100110110111 source: ; set pin BL1 to clear pin BB1 and pin BN1 AND-NOR OUTPUTS and set TAPE BUS 2 OUTPUT and TAPE BUS 3 OUTPUT source: 1 00 11 changed: 1 00 11 step 71 100001100110100100111011011011011101001111011011011010100110110111 source: 0 11 00 changed: 0 11 00 step 72 100001100110100100011011011011011101111100011011011010100110110111 source: ; set pin BF1 to clear pin BB1 and pin BN1 AND-NOR OUTPUTS and set TAPE BUS 2 OUTPUT and TAPE BUS 3 OUTPUT source: 1 00 11 changed: 1 00 11 step 73 100001100110100100011111011011011101001111011011011010100110110111 source: 0 11 00 changed: 0 11 00 step 74 100001100110100100011011011011011101111100011011011010100110110111 source: ; set pin BS1 to clear pin BB1 and pin BN1 AND-NOR OUTPUTS and set TAPE BUS 2 OUTPUT and TAPE BUS 3 OUTPUT source: 1 00 11 changed: 1 00 11 step 75 100001100110100100011011111011011101001111011011011010100110110111 source: 0 11 00 changed: 0 11 00 step 76 100001100110100100011011011011011101111100011011011010100110110111 source: ; set pin BL2 to clear pin BB1 and pin BN1 AND-NOR OUTPUTS and set TAPE BUS 2 OUTPUT and TAPE BUS 3 OUTPUT source: 1 00 11 changed: 1 00 11 step 77 100001100110100100011011011111011101001111011011011010100110110111 source: 0 11 00 changed: 0 11 00 step 78 100001100110100100011011011011011101111100011011011010100110110111 source: ; set pin BU1 to clear pin BB1 and pin BN1 AND-NOR OUTPUTS and set TAPE BUS 2 OUTPUT and TAPE BUS 3 OUTPUT source: 1 00 11 changed: 1 00 11 step 79 100001100110100100011011011011111101001111011011011010100110110111 source: 0 11 00 changed: 0 11 00 step 80 100001100110100100011011011011011101111100011011011010100110110111 source: ; set pin BM2 to clear pin BB1 and TAPE BUS 3 OUTPUT source: 1 0 1 changed: 1 0 1 step 81 100001100110100100011011011011011111101110011011011010100110110111 source: 0 1 0 changed: 0 1 0 step 82 100001100110100100011011011011011101111100011011011010100110110111 source: ; no change source: 100000000000000000000000000000000001111100011011011010100110110111 changed: 00 00 0 0 00 00 00 00 000 step 83 100000000000000000000000000000000001111100011011011010100110110111 source: source: ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; source: ; test shifting the RWB source: ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; source: source: ; shift in 0, expect 10 source: 0 changed: 0 step 84 100000000000000000000000000000000001111100011011011010100110100111 source: 110 changed: 1 0 step 85 100000000000000000000000000000000001111100011011011010100110101101 source: 0 changed: 0 step 86 100000000000000000000000000000000001111100011011011010100110100101 source: ; toggle phase should toggle RWB 2 source: 0 0 changed: 0 0 step 87 100000000000000000000000000000000001111100011011011010100110000001 source: 1 1 changed: 1 1 step 88 100000000000000000000000000000000001111100011011011010100110100101 source: source: ; shift in 0, expect 00 source: 0 changed: step 89 100000000000000000000000000000000001111100011011011010100110100101 source: 100 changed: 10 step 90 100000000000000000000000000000000001111100011011011010100110101001 source: 0 changed: 0 step 91 100000000000000000000000000000000001111100011011011010100110100001 source: ; toggle phase should toggle RWB 2 source: 0 1 changed: 0 1 step 92 100000000000000000000000000000000001111100011011011010100110000101 source: 1 0 changed: 1 0 step 93 100000000000000000000000000000000001111100011011011010100110100001 source: source: ; shift in 0, expect 00 source: 0 changed: step 94 100000000000000000000000000000000001111100011011011010100110100001 source: 100 changed: 1 step 95 100000000000000000000000000000000001111100011011011010100110101001 source: 0 changed: 0 step 96 100000000000000000000000000000000001111100011011011010100110100001 source: ; shift in 1, expect 01 source: 1 changed: 1 step 97 100000000000000000000000000000000001111100011011011010100110110001 source: 101 changed: 1 1 step 98 100000000000000000000000000000000001111100011011011010100110111011 source: 0 changed: 0 step 99 100000000000000000000000000000000001111100011011011010100110110011 source: ; shift in 1, expect 11 source: 1 changed: step 100 100000000000000000000000000000000001111100011011011010100110110011 source: 111 changed: 11 step 101 100000000000000000000000000000000001111100011011011010100110111111 source: 0 changed: 0 step 102 100000000000000000000000000000000001111100011011011010100110110111 source: ; shift in 1, expect 11 source: 1 changed: step 103 100000000000000000000000000000000001111100011011011010100110110111 source: 111 changed: 1 step 104 100000000000000000000000000000000001111100011011011010100110111111 source: 0 changed: 0 step 105 100000000000000000000000000000000001111100011011011010100110110111 source: ; shift in 0, expect 10 source: 0 changed: 0 step 106 100000000000000000000000000000000001111100011011011010100110100111 source: 110 changed: 1 0 step 107 100000000000000000000000000000000001111100011011011010100110101101 source: 0 changed: 0 step 108 100000000000000000000000000000000001111100011011011010100110100101 source: ; shift in 1, expect 01 source: 1 changed: 1 step 109 100000000000000000000000000000000001111100011011011010100110110101 source: 101 changed: 101 step 110 100000000000000000000000000000000001111100011011011010100110111011 source: 0 changed: 0 step 111 100000000000000000000000000000000001111100011011011010100110110011 source: ; shift in 0, expect 10 source: 0 changed: 0 step 112 100000000000000000000000000000000001111100011011011010100110100011 source: 110 changed: 110 step 113 100000000000000000000000000000000001111100011011011010100110101101 source: 0 changed: 0 step 114 100000000000000000000000000000000001111100011011011010100110100101 source: ; shift in 1, expect 01 source: 1 changed: 1 step 115 100000000000000000000000000000000001111100011011011010100110110101 source: 101 changed: 101 step 116 100000000000000000000000000000000001111100011011011010100110111011 source: 0 changed: 0 step 117 100000000000000000000000000000000001111100011011011010100110110011 source: ; shift in 1, expect 11 source: 1 changed: step 118 100000000000000000000000000000000001111100011011011010100110110011 source: 111 changed: 11 step 119 100000000000000000000000000000000001111100011011011010100110111111 source: 0 changed: 0 step 120 100000000000000000000000000000000001111100011011011010100110110111 source: ; no change source: 100000000000000000000000000000000001111100011011011010100110110111 changed: step 121 100000000000000000000000000000000001111100011011011010100110110111 test 2: pass SLOT BAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBAABBAAAAAAAAAAAAAABBBBBABBBB LETTER ALPSLFMDEEMCBFRSPKLEMFHRSCJLJKUHPNMBBNNVVRKRHUTDJUKANJHBTPDFSVEVDU SIDE 121212122121212121111111112212122222112222111221112112212112212122 DIRECTION IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIOOOOOOOIOOIOOIOOIOOOOIOOIIIIOOO this fail all fails was hi 111111111111111111111111111111111111111111111111111111111111111111 rising ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ ^^^^^^^^^^^^^^^^^^^^^^^^^ falling vvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvv vvvvvvvvvvvvvvvvvvvvvvvvv was lo 00000000000000000000000000000000000000 0000000000000000000000000 total fails 0, total passes 2 source: ; all registers are unknown source: ; turn on C0, PHASE source: ; with no ENABLES, BUS2,BUS3 is 11, C2 is 1 source: 1000000000000000000000000000000000011111000XX0XX0XX0XXXX0XX0110XX1 changed: step 1 100000000000000000000000000000000001111100011011011010100110110111 source: source: ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; source: ; source: ; set all registers LOW source: ; source: ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; source: source: ; load TMA SETUP from tape bus (00) source: 100 changed: 100 step 2 100000000000000000000000000000000001111100100011011010100110110111 source: 0 changed: 0 step 3 100000000000000000000000000000000001111100000011011010100110110111 source: ; load TMA from tape bus (00) source: 100 changed: 100 step 4 100000000000000000000000000000000001111100000100011010100110110111 source: 0 changed: 0 step 5 100000000000000000000000000000000001111100000000011010100110110111 source: ; load TBN from tape bus (00) source: 100 changed: 100 step 6 100000000000000000000000000000000001111100000000100010100110110111 source: 0 changed: 0 step 7 100000000000000000000000000000000001111100000000000010100110110111 source: ; load TAC from tape bus (00) source: 10101 changed: 10101 step 8 100000000000000000000000000000000001111100000000000101010110110111 source: 0 changed: 0 step 9 100000000000000000000000000000000001111100000000000001010110110111 source: ; load TB from tape bus (00) source: 100 changed: 100 step 10 100000000000000000000000000000000001111100000000000001011000110111 source: 0 changed: 0 step 11 100000000000000000000000000000000001111100000000000001010000110111 source: ; load RWB from TB (JAMS CLEAR AND PRESET) source: 1 00 changed: 1 00 step 12 100000000000000000000000000000000001111100000000000001010001110001 source: 0 changed: 0 step 13 100000000000000000000000000000000001111100000000000001010000110001 source: ; (no change) source: 100000000000000000000000000000000001111100000000000001010000110001 changed: step 14 100000000000000000000000000000000001111100000000000001010000110001 source: source: source: ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; source: ; source: ; set all registers HIGH source: ; source: ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; source: source: ; set pin AF1 (AND with itself) to clear pin BB2 (AND-NOR output) and set pin BR2 TAPE BUS 3 OUTPUT source: 1 0 1 changed: 1 0 1 step 15 100000000000010000000000000000000000111101000000000001010000110001 source: ; set pin AP2 (AND with itself) to clear pin AN2 (AND-NOR output) and set pin BV2 TAPE BUS 2 OUTPUT source: 1 0 1 changed: 1 0 1 step 16 100000000000010010000000000000000000110111000000000001010000110001 source: source: source: ; load TMA SETUP from tape bus (11) source: 111 changed: 111 step 17 100000000000010010000000000000000000110111111000000001010000110001 source: 0 changed: 0 step 18 100000000000010010000000000000000000110111011000000001010000110001 source: ; load TMA from tape bus (11) source: 111 changed: 111 step 19 100000000000010010000000000000000000110111011111000001010000110001 source: 0 changed: 0 step 20 100000000000010010000000000000000000110111011011000001010000110001 source: ; load TBN from tape bus (11) source: 111 changed: 111 step 21 100000000000010010000000000000000000110111011011111001010000110001 source: 0 changed: 0 step 22 100000000000010010000000000000000000110111011011011001010000110001 source: ; load TAC from tape bus (11) source: 11010 changed: 11010 step 23 100000000000010010000000000000000000110111011011011110100000110001 source: 0 changed: 0 step 24 100000000000010010000000000000000000110111011011011010100000110001 source: ; load TB from tape bus (11) source: 111 changed: 111 step 25 100000000000010010000000000000000000110111011011011010101110110001 source: 0 changed: 0 step 26 100000000000010010000000000000000000110111011011011010100110110001 source: ; load RWB from TB (JAMS CLEAR AND PRESET) source: 1 11 changed: 1 11 step 27 100000000000010010000000000000000000110111011011011010100111110111 source: 0 changed: 0 step 28 100000000000010010000000000000000000110111011011011010100110110111 source: ; clear pin AF1 (AND with itself) to set pin BB2 (AND-NOR output) and clear pin BR2 TAPE BUS 3 OUTPUT source: 0 1 0 changed: 0 1 0 step 29 100000000000000010000000000000000001110110011011011010100110110111 source: ; clear pin AP2 (AND with itself) to set pin AN2 (AND-NOR output) and clear pin BV2 TAPE BUS 2 OUTPUT source: 0 1 0 changed: 0 1 0 step 30 100000000000000000000000000000000001111100011011011010100110110111 source: ; (no change) source: 100000000000000000000000000000000001111100011011011010100110110111 changed: step 31 100000000000000000000000000000000001111100011011011010100110110111 source: source: source: ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; source: ; source: ; test AND-NOR logic source: ; source: ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; source: source: ; (all registers are HIGH) source: ; set all pins HIGH except ENABLES source: source: ; set pin AF2 HIGH source: 1 changed: 1 step 32 100001000000000000000000000000000001111100011011011010100110110111 source: ; set pin AM1 HIGH source: 1 changed: 1 step 33 100001100000000000000000000000000001111100011011011010100110110111 source: ; set pin AE1 HIGH source: 1 changed: 1 step 34 100001100100000000000000000000000001111100011011011010100110110111 source: ; set pin AM2 HIGH source: 1 changed: 1 step 35 100001100110000000000000000000000001111100011011011010100110110111 source: ; set pin AB2 HIGH source: 1 changed: 1 step 36 100001100110100000000000000000000001111100011011011010100110110111 source: ; set pin AS1 HIGH source: 1 changed: 1 step 37 100001100110100100000000000000000001111100011011011010100110110111 source: ; set pin BE1 HIGH source: 1 changed: 1 step 38 100001100110100100010000000000000001111100011011011010100110110111 source: ; set pin BM1 HIGH source: 1 changed: 1 step 39 100001100110100100011000000000000001111100011011011010100110110111 source: ; set pin BH1 HIGH source: 1 changed: 1 step 40 100001100110100100011010000000000001111100011011011010100110110111 source: ; set pin BR1 HIGH source: 1 changed: 1 step 41 100001100110100100011011000000000001111100011011011010100110110111 source: ; set pin BC1 HIGH source: 1 changed: 1 step 42 100001100110100100011011010000000001111100011011011010100110110111 source: ; set pin BJ2 HIGH source: 1 changed: 1 step 43 100001100110100100011011011000000001111100011011011010100110110111 source: ; set pin BJ1 HIGH source: 1 changed: 1 step 44 100001100110100100011011011010000001111100011011011010100110110111 source: ; set pin BK2 HIGH source: 1 changed: 1 step 45 100001100110100100011011011011000001111100011011011010100110110111 source: ; set pin BH2 HIGH source: 1 changed: 1 step 46 100001100110100100011011011011010001111100011011011010100110110111 source: ; set pin BP2 HIGH source: 1 changed: 1 step 47 100001100110100100011011011011011001111100011011011010100110110111 source: ; set pin BN2 HIGH source: 1 changed: 1 step 48 100001100110100100011011011011011101111100011011011010100110110111 source: ; toggle each ENABLE source: source: ; set pin AL2 to clear pin BB2 and pin AN2 AND-NOR OUTPUTS and set TAPE BUS 2 OUTPUT and TAPE BUS 3 OUTPUT source: 1 0 0 11 changed: 1 0 0 11 step 49 110001100110100100011011011011011100110111011011011010100110110111 source: 0 1 1 00 changed: 0 1 1 00 step 50 100001100110100100011011011011011101111100011011011010100110110111 source: ; set pin AP1 to clear pin BB2 and pin AN2 AND-NOR OUTPUTS and set TAPE BUS 2 OUTPUT and TAPE BUS 3 OUTPUT source: 1 0 0 11 changed: 1 0 0 11 step 51 101001100110100100011011011011011100110111011011011010100110110111 source: 0 1 1 00 changed: 0 1 1 00 step 52 100001100110100100011011011011011101111100011011011010100110110111 source: ; set pin AS2 to clear pin BB2 and pin AN2 AND-NOR OUTPUTS and set TAPE BUS 2 OUTPUT and TAPE BUS 3 OUTPUT source: 1 0 0 11 changed: 1 0 0 11 step 53 100101100110100100011011011011011100110111011011011010100110110111 source: 0 1 1 00 changed: 0 1 1 00 step 54 100001100110100100011011011011011101111100011011011010100110110111 source: ; set pin AL1 to clear pin BB2 and pin AN2 AND-NOR OUTPUTS and set TAPE BUS 2 OUTPUT and TAPE BUS 3 OUTPUT source: 1 0 0 11 changed: 1 0 0 11 step 55 100011100110100100011011011011011100110111011011011010100110110111 source: 0 1 1 00 changed: 0 1 1 00 step 56 100001100110100100011011011011011101111100011011011010100110110111 source: ; set pin AL1 to clear pin BB2 and pin AN2 AND-NOR OUTPUTS and set TAPE BUS 2 OUTPUT and TAPE BUS 3 OUTPUT source: 1 0 0 11 changed: 1 0 0 11 step 57 100001110110100100011011011011011100110111011011011010100110110111 source: 0 1 1 00 changed: 0 1 1 00 step 58 100001100110100100011011011011011101111100011011011010100110110111 source: ; set pin AE2 to clear pin BB2 and pin AN2 AND-NOR OUTPUTS and set TAPE BUS 2 OUTPUT and TAPE BUS 3 OUTPUT source: 1 0 0 11 changed: 1 0 0 11 step 59 100001101110100100011011011011011100110111011011011010100110110111 source: 0 1 1 00 changed: 0 1 1 00 step 60 100001100110100100011011011011011101111100011011011010100110110111 source: ; set pin AC1 to clear pin BB2 and set TAPE BUS 3 OUTPUT source: 1 0 1 changed: 1 0 1 step 61 100001100111100100011011011011011100111101011011011010100110110111 source: 0 1 0 changed: 0 1 0 step 62 100001100110100100011011011011011101111100011011011010100110110111 source: ; set pin AF1 to clear pin BB2 and set TAPE BUS 3 OUTPUT source: 1 0 1 changed: 1 0 1 step 63 100001100110110100011011011011011100111101011011011010100110110111 source: 0 1 0 changed: 0 1 0 step 64 100001100110100100011011011011011101111100011011011010100110110111 source: ; set pin AR2 to clear pin AN2 AND-NOR OUTPUTS and set TAPE BUS 2 OUTPUT source: 1 0 1 changed: 1 0 1 step 65 100001100110101100011011011011011101110110011011011010100110110111 source: 0 1 0 changed: 0 1 0 step 66 100001100110100100011011011011011101111100011011011010100110110111 source: ; set pin AP2 to clear pin AN2 AND-NOR OUTPUTS and set TAPE BUS 2 OUTPUT source: 1 0 1 changed: 1 0 1 step 67 100001100110100110011011011011011101110110011011011010100110110111 source: 0 1 0 changed: 0 1 0 step 68 100001100110100100011011011011011101111100011011011010100110110111 source: source: ; set pin BK1 to clear pin BB1 and pin BN1 AND-NOR OUTPUTS and set TAPE BUS 2 OUTPUT and TAPE BUS 3 OUTPUT source: 1 00 11 changed: 1 00 11 step 69 100001100110100101011011011011011101001111011011011010100110110111 source: 0 11 00 changed: 0 11 00 step 70 100001100110100100011011011011011101111100011011011010100110110111 source: ; set pin BL1 to clear pin BB1 and pin BN1 AND-NOR OUTPUTS and set TAPE BUS 2 OUTPUT and TAPE BUS 3 OUTPUT source: 1 00 11 changed: 1 00 11 step 71 100001100110100100111011011011011101001111011011011010100110110111 source: 0 11 00 changed: 0 11 00 step 72 100001100110100100011011011011011101111100011011011010100110110111 source: ; set pin BF1 to clear pin BB1 and pin BN1 AND-NOR OUTPUTS and set TAPE BUS 2 OUTPUT and TAPE BUS 3 OUTPUT source: 1 00 11 changed: 1 00 11 step 73 100001100110100100011111011011011101001111011011011010100110110111 source: 0 11 00 changed: 0 11 00 step 74 100001100110100100011011011011011101111100011011011010100110110111 source: ; set pin BS1 to clear pin BB1 and pin BN1 AND-NOR OUTPUTS and set TAPE BUS 2 OUTPUT and TAPE BUS 3 OUTPUT source: 1 00 11 changed: 1 00 11 step 75 100001100110100100011011111011011101001111011011011010100110110111 source: 0 11 00 changed: 0 11 00 step 76 100001100110100100011011011011011101111100011011011010100110110111 source: ; set pin BL2 to clear pin BB1 and pin BN1 AND-NOR OUTPUTS and set TAPE BUS 2 OUTPUT and TAPE BUS 3 OUTPUT source: 1 00 11 changed: 1 00 11 step 77 100001100110100100011011011111011101001111011011011010100110110111 source: 0 11 00 changed: 0 11 00 step 78 100001100110100100011011011011011101111100011011011010100110110111 source: ; set pin BU1 to clear pin BB1 and pin BN1 AND-NOR OUTPUTS and set TAPE BUS 2 OUTPUT and TAPE BUS 3 OUTPUT source: 1 00 11 changed: 1 00 11 step 79 100001100110100100011011011011111101001111011011011010100110110111 source: 0 11 00 changed: 0 11 00 step 80 100001100110100100011011011011011101111100011011011010100110110111 source: ; set pin BM2 to clear pin BB1 and TAPE BUS 3 OUTPUT source: 1 0 1 changed: 1 0 1 step 81 100001100110100100011011011011011111101110011011011010100110110111 source: 0 1 0 changed: 0 1 0 step 82 100001100110100100011011011011011101111100011011011010100110110111 source: ; no change source: 100000000000000000000000000000000001111100011011011010100110110111 changed: 00 00 0 0 00 00 00 00 000 step 83 100000000000000000000000000000000001111100011011011010100110110111 source: source: ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; source: ; test shifting the RWB source: ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; source: source: ; shift in 0, expect 10 source: 0 changed: 0 step 84 100000000000000000000000000000000001111100011011011010100110100111 source: 110 changed: 1 0 step 85 100000000000000000000000000000000001111100011011011010100110101101 source: 0 changed: 0 step 86 100000000000000000000000000000000001111100011011011010100110100101 source: ; toggle phase should toggle RWB 2 source: 0 0 changed: 0 0 step 87 100000000000000000000000000000000001111100011011011010100110000001 source: 1 1 changed: 1 1 step 88 100000000000000000000000000000000001111100011011011010100110100101 source: source: ; shift in 0, expect 00 source: 0 changed: step 89 100000000000000000000000000000000001111100011011011010100110100101 source: 100 changed: 10 step 90 100000000000000000000000000000000001111100011011011010100110101001 source: 0 changed: 0 step 91 100000000000000000000000000000000001111100011011011010100110100001 source: ; toggle phase should toggle RWB 2 source: 0 1 changed: 0 1 step 92 100000000000000000000000000000000001111100011011011010100110000101 source: 1 0 changed: 1 0 step 93 100000000000000000000000000000000001111100011011011010100110100001 source: source: ; shift in 0, expect 00 source: 0 changed: step 94 100000000000000000000000000000000001111100011011011010100110100001 source: 100 changed: 1 step 95 100000000000000000000000000000000001111100011011011010100110101001 source: 0 changed: 0 step 96 100000000000000000000000000000000001111100011011011010100110100001 source: ; shift in 1, expect 01 source: 1 changed: 1 step 97 100000000000000000000000000000000001111100011011011010100110110001 source: 101 changed: 1 1 step 98 100000000000000000000000000000000001111100011011011010100110111011 source: 0 changed: 0 step 99 100000000000000000000000000000000001111100011011011010100110110011 source: ; shift in 1, expect 11 source: 1 changed: step 100 100000000000000000000000000000000001111100011011011010100110110011 source: 111 changed: 11 step 101 100000000000000000000000000000000001111100011011011010100110111111 source: 0 changed: 0 step 102 100000000000000000000000000000000001111100011011011010100110110111 source: ; shift in 1, expect 11 source: 1 changed: step 103 100000000000000000000000000000000001111100011011011010100110110111 source: 111 changed: 1 step 104 100000000000000000000000000000000001111100011011011010100110111111 source: 0 changed: 0 step 105 100000000000000000000000000000000001111100011011011010100110110111 source: ; shift in 0, expect 10 source: 0 changed: 0 step 106 100000000000000000000000000000000001111100011011011010100110100111 source: 110 changed: 1 0 step 107 100000000000000000000000000000000001111100011011011010100110101101 source: 0 changed: 0 step 108 100000000000000000000000000000000001111100011011011010100110100101 source: ; shift in 1, expect 01 source: 1 changed: 1 step 109 100000000000000000000000000000000001111100011011011010100110110101 source: 101 changed: 101 step 110 100000000000000000000000000000000001111100011011011010100110111011 source: 0 changed: 0 step 111 100000000000000000000000000000000001111100011011011010100110110011 source: ; shift in 0, expect 10 source: 0 changed: 0 step 112 100000000000000000000000000000000001111100011011011010100110100011 source: 110 changed: 110 step 113 100000000000000000000000000000000001111100011011011010100110101101 source: 0 changed: 0 step 114 100000000000000000000000000000000001111100011011011010100110100101 source: ; shift in 1, expect 01 source: 1 changed: 1 step 115 100000000000000000000000000000000001111100011011011010100110110101 source: 101 changed: 101 step 116 100000000000000000000000000000000001111100011011011010100110111011 source: 0 changed: 0 step 117 100000000000000000000000000000000001111100011011011010100110110011 source: ; shift in 1, expect 11 source: 1 changed: step 118 100000000000000000000000000000000001111100011011011010100110110011 source: 111 changed: 11 step 119 100000000000000000000000000000000001111100011011011010100110111111 source: 0 changed: 0 step 120 100000000000000000000000000000000001111100011011011010100110110111 source: ; no change source: 100000000000000000000000000000000001111100011011011010100110110111 changed: step 121 100000000000000000000000000000000001111100011011011010100110110111 test 3: pass SLOT BAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBAABBAAAAAAAAAAAAAABBBBBABBBB LETTER ALPSLFMDEEMCBFRSPKLEMFHRSCJLJKUHPNMBBNNVVRKRHUTDJUKANJHBTPDFSVEVDU SIDE 121212122121212121111111112212122222112222111221112112212112212122 DIRECTION IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIOOOOOOOIOOIOOIOOIOOOOIOOIIIIOOO this fail all fails was hi 111111111111111111111111111111111111111111111111111111111111111111 rising ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ ^^^^^^^^^^^^^^^^^^^^^^^^^ falling vvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvv vvvvvvvvvvvvvvvvvvvvvvvvv was lo 00000000000000000000000000000000000000 0000000000000000000000000 total fails 0, total passes 3 source: ; all registers are unknown source: ; turn on C0, PHASE source: ; with no ENABLES, BUS2,BUS3 is 11, C2 is 1 source: 1000000000000000000000000000000000011111000XX0XX0XX0XXXX0XX0110XX1 changed: step 1 100000000000000000000000000000000001111100011011011010100110110111 source: source: ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; source: ; source: ; set all registers LOW source: ; source: ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; source: source: ; load TMA SETUP from tape bus (00) source: 100 changed: 100 step 2 100000000000000000000000000000000001111100100011011010100110110111 source: 0 changed: 0 step 3 100000000000000000000000000000000001111100000011011010100110110111 source: ; load TMA from tape bus (00) source: 100 changed: 100 step 4 100000000000000000000000000000000001111100000100011010100110110111 source: 0 changed: 0 step 5 100000000000000000000000000000000001111100000000011010100110110111 source: ; load TBN from tape bus (00) source: 100 changed: 100 step 6 100000000000000000000000000000000001111100000000100010100110110111 source: 0 changed: 0 step 7 100000000000000000000000000000000001111100000000000010100110110111 source: ; load TAC from tape bus (00) source: 10101 changed: 10101 step 8 100000000000000000000000000000000001111100000000000101010110110111 source: 0 changed: 0 step 9 100000000000000000000000000000000001111100000000000001010110110111 source: ; load TB from tape bus (00) source: 100 changed: 100 step 10 100000000000000000000000000000000001111100000000000001011000110111 source: 0 changed: 0 step 11 100000000000000000000000000000000001111100000000000001010000110111 source: ; load RWB from TB (JAMS CLEAR AND PRESET) source: 1 00 changed: 1 00 step 12 100000000000000000000000000000000001111100000000000001010001110001 source: 0 changed: 0 step 13 100000000000000000000000000000000001111100000000000001010000110001 source: ; (no change) source: 100000000000000000000000000000000001111100000000000001010000110001 changed: step 14 100000000000000000000000000000000001111100000000000001010000110001 source: source: source: ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; source: ; source: ; set all registers HIGH source: ; source: ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; source: source: ; set pin AF1 (AND with itself) to clear pin BB2 (AND-NOR output) and set pin BR2 TAPE BUS 3 OUTPUT source: 1 0 1 changed: 1 0 1 step 15 100000000000010000000000000000000000111101000000000001010000110001 source: ; set pin AP2 (AND with itself) to clear pin AN2 (AND-NOR output) and set pin BV2 TAPE BUS 2 OUTPUT source: 1 0 1 changed: 1 0 1 step 16 100000000000010010000000000000000000110111000000000001010000110001 source: source: source: ; load TMA SETUP from tape bus (11) source: 111 changed: 111 step 17 100000000000010010000000000000000000110111111000000001010000110001 source: 0 changed: 0 step 18 100000000000010010000000000000000000110111011000000001010000110001 source: ; load TMA from tape bus (11) source: 111 changed: 111 step 19 100000000000010010000000000000000000110111011111000001010000110001 source: 0 changed: 0 step 20 100000000000010010000000000000000000110111011011000001010000110001 source: ; load TBN from tape bus (11) source: 111 changed: 111 step 21 100000000000010010000000000000000000110111011011111001010000110001 source: 0 changed: 0 step 22 100000000000010010000000000000000000110111011011011001010000110001 source: ; load TAC from tape bus (11) source: 11010 changed: 11010 step 23 100000000000010010000000000000000000110111011011011110100000110001 source: 0 changed: 0 step 24 100000000000010010000000000000000000110111011011011010100000110001 source: ; load TB from tape bus (11) source: 111 changed: 111 step 25 100000000000010010000000000000000000110111011011011010101110110001 source: 0 changed: 0 step 26 100000000000010010000000000000000000110111011011011010100110110001 source: ; load RWB from TB (JAMS CLEAR AND PRESET) source: 1 11 changed: 1 11 step 27 100000000000010010000000000000000000110111011011011010100111110111 source: 0 changed: 0 step 28 100000000000010010000000000000000000110111011011011010100110110111 source: ; clear pin AF1 (AND with itself) to set pin BB2 (AND-NOR output) and clear pin BR2 TAPE BUS 3 OUTPUT source: 0 1 0 changed: 0 1 0 step 29 100000000000000010000000000000000001110110011011011010100110110111 source: ; clear pin AP2 (AND with itself) to set pin AN2 (AND-NOR output) and clear pin BV2 TAPE BUS 2 OUTPUT source: 0 1 0 changed: 0 1 0 step 30 100000000000000000000000000000000001111100011011011010100110110111 source: ; (no change) source: 100000000000000000000000000000000001111100011011011010100110110111 changed: step 31 100000000000000000000000000000000001111100011011011010100110110111 source: source: source: ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; source: ; source: ; test AND-NOR logic source: ; source: ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; source: source: ; (all registers are HIGH) source: ; set all pins HIGH except ENABLES source: source: ; set pin AF2 HIGH source: 1 changed: 1 step 32 100001000000000000000000000000000001111100011011011010100110110111 source: ; set pin AM1 HIGH source: 1 changed: 1 step 33 100001100000000000000000000000000001111100011011011010100110110111 source: ; set pin AE1 HIGH source: 1 changed: 1 step 34 100001100100000000000000000000000001111100011011011010100110110111 source: ; set pin AM2 HIGH source: 1 changed: 1 step 35 100001100110000000000000000000000001111100011011011010100110110111 source: ; set pin AB2 HIGH source: 1 changed: 1 step 36 100001100110100000000000000000000001111100011011011010100110110111 source: ; set pin AS1 HIGH source: 1 changed: 1 step 37 100001100110100100000000000000000001111100011011011010100110110111 source: ; set pin BE1 HIGH source: 1 changed: 1 step 38 100001100110100100010000000000000001111100011011011010100110110111 source: ; set pin BM1 HIGH source: 1 changed: 1 step 39 100001100110100100011000000000000001111100011011011010100110110111 source: ; set pin BH1 HIGH source: 1 changed: 1 step 40 100001100110100100011010000000000001111100011011011010100110110111 source: ; set pin BR1 HIGH source: 1 changed: 1 step 41 100001100110100100011011000000000001111100011011011010100110110111 source: ; set pin BC1 HIGH source: 1 changed: 1 step 42 100001100110100100011011010000000001111100011011011010100110110111 source: ; set pin BJ2 HIGH source: 1 changed: 1 step 43 100001100110100100011011011000000001111100011011011010100110110111 source: ; set pin BJ1 HIGH source: 1 changed: 1 step 44 100001100110100100011011011010000001111100011011011010100110110111 source: ; set pin BK2 HIGH source: 1 changed: 1 step 45 100001100110100100011011011011000001111100011011011010100110110111 source: ; set pin BH2 HIGH source: 1 changed: 1 step 46 100001100110100100011011011011010001111100011011011010100110110111 source: ; set pin BP2 HIGH source: 1 changed: 1 step 47 100001100110100100011011011011011001111100011011011010100110110111 source: ; set pin BN2 HIGH source: 1 changed: 1 step 48 100001100110100100011011011011011101111100011011011010100110110111 source: ; toggle each ENABLE source: source: ; set pin AL2 to clear pin BB2 and pin AN2 AND-NOR OUTPUTS and set TAPE BUS 2 OUTPUT and TAPE BUS 3 OUTPUT source: 1 0 0 11 changed: 1 0 0 11 step 49 110001100110100100011011011011011100110111011011011010100110110111 source: 0 1 1 00 changed: 0 1 1 00 step 50 100001100110100100011011011011011101111100011011011010100110110111 source: ; set pin AP1 to clear pin BB2 and pin AN2 AND-NOR OUTPUTS and set TAPE BUS 2 OUTPUT and TAPE BUS 3 OUTPUT source: 1 0 0 11 changed: 1 0 0 11 step 51 101001100110100100011011011011011100110111011011011010100110110111 source: 0 1 1 00 changed: 0 1 1 00 step 52 100001100110100100011011011011011101111100011011011010100110110111 source: ; set pin AS2 to clear pin BB2 and pin AN2 AND-NOR OUTPUTS and set TAPE BUS 2 OUTPUT and TAPE BUS 3 OUTPUT source: 1 0 0 11 changed: 1 0 0 11 step 53 100101100110100100011011011011011100110111011011011010100110110111 source: 0 1 1 00 changed: 0 1 1 00 step 54 100001100110100100011011011011011101111100011011011010100110110111 source: ; set pin AL1 to clear pin BB2 and pin AN2 AND-NOR OUTPUTS and set TAPE BUS 2 OUTPUT and TAPE BUS 3 OUTPUT source: 1 0 0 11 changed: 1 0 0 11 step 55 100011100110100100011011011011011100110111011011011010100110110111 source: 0 1 1 00 changed: 0 1 1 00 step 56 100001100110100100011011011011011101111100011011011010100110110111 source: ; set pin AL1 to clear pin BB2 and pin AN2 AND-NOR OUTPUTS and set TAPE BUS 2 OUTPUT and TAPE BUS 3 OUTPUT source: 1 0 0 11 changed: 1 0 0 11 step 57 100001110110100100011011011011011100110111011011011010100110110111 source: 0 1 1 00 changed: 0 1 1 00 step 58 100001100110100100011011011011011101111100011011011010100110110111 source: ; set pin AE2 to clear pin BB2 and pin AN2 AND-NOR OUTPUTS and set TAPE BUS 2 OUTPUT and TAPE BUS 3 OUTPUT source: 1 0 0 11 changed: 1 0 0 11 step 59 100001101110100100011011011011011100110111011011011010100110110111 source: 0 1 1 00 changed: 0 1 1 00 step 60 100001100110100100011011011011011101111100011011011010100110110111 source: ; set pin AC1 to clear pin BB2 and set TAPE BUS 3 OUTPUT source: 1 0 1 changed: 1 0 1 step 61 100001100111100100011011011011011100111101011011011010100110110111 source: 0 1 0 changed: 0 1 0 step 62 100001100110100100011011011011011101111100011011011010100110110111 source: ; set pin AF1 to clear pin BB2 and set TAPE BUS 3 OUTPUT source: 1 0 1 changed: 1 0 1 step 63 100001100110110100011011011011011100111101011011011010100110110111 source: 0 1 0 changed: 0 1 0 step 64 100001100110100100011011011011011101111100011011011010100110110111 source: ; set pin AR2 to clear pin AN2 AND-NOR OUTPUTS and set TAPE BUS 2 OUTPUT source: 1 0 1 changed: 1 0 1 step 65 100001100110101100011011011011011101110110011011011010100110110111 source: 0 1 0 changed: 0 1 0 step 66 100001100110100100011011011011011101111100011011011010100110110111 source: ; set pin AP2 to clear pin AN2 AND-NOR OUTPUTS and set TAPE BUS 2 OUTPUT source: 1 0 1 changed: 1 0 1 step 67 100001100110100110011011011011011101110110011011011010100110110111 source: 0 1 0 changed: 0 1 0 step 68 100001100110100100011011011011011101111100011011011010100110110111 source: source: ; set pin BK1 to clear pin BB1 and pin BN1 AND-NOR OUTPUTS and set TAPE BUS 2 OUTPUT and TAPE BUS 3 OUTPUT source: 1 00 11 changed: 1 00 11 step 69 100001100110100101011011011011011101001111011011011010100110110111 source: 0 11 00 changed: 0 11 00 step 70 100001100110100100011011011011011101111100011011011010100110110111 source: ; set pin BL1 to clear pin BB1 and pin BN1 AND-NOR OUTPUTS and set TAPE BUS 2 OUTPUT and TAPE BUS 3 OUTPUT source: 1 00 11 changed: 1 00 11 step 71 100001100110100100111011011011011101001111011011011010100110110111 source: 0 11 00 changed: 0 11 00 step 72 100001100110100100011011011011011101111100011011011010100110110111 source: ; set pin BF1 to clear pin BB1 and pin BN1 AND-NOR OUTPUTS and set TAPE BUS 2 OUTPUT and TAPE BUS 3 OUTPUT source: 1 00 11 changed: 1 00 11 step 73 100001100110100100011111011011011101001111011011011010100110110111 source: 0 11 00 changed: 0 11 00 step 74 100001100110100100011011011011011101111100011011011010100110110111 source: ; set pin BS1 to clear pin BB1 and pin BN1 AND-NOR OUTPUTS and set TAPE BUS 2 OUTPUT and TAPE BUS 3 OUTPUT source: 1 00 11 changed: 1 00 11 step 75 100001100110100100011011111011011101001111011011011010100110110111 source: 0 11 00 changed: 0 11 00 step 76 100001100110100100011011011011011101111100011011011010100110110111 source: ; set pin BL2 to clear pin BB1 and pin BN1 AND-NOR OUTPUTS and set TAPE BUS 2 OUTPUT and TAPE BUS 3 OUTPUT source: 1 00 11 changed: 1 00 11 step 77 100001100110100100011011011111011101001111011011011010100110110111 source: 0 11 00 changed: 0 11 00 step 78 100001100110100100011011011011011101111100011011011010100110110111 source: ; set pin BU1 to clear pin BB1 and pin BN1 AND-NOR OUTPUTS and set TAPE BUS 2 OUTPUT and TAPE BUS 3 OUTPUT source: 1 00 11 changed: 1 00 11 step 79 100001100110100100011011011011111101001111011011011010100110110111 source: 0 11 00 changed: 0 11 00 step 80 100001100110100100011011011011011101111100011011011010100110110111 source: ; set pin BM2 to clear pin BB1 and TAPE BUS 3 OUTPUT source: 1 0 1 changed: 1 0 1 step 81 100001100110100100011011011011011111101110011011011010100110110111 source: 0 1 0 changed: 0 1 0 step 82 100001100110100100011011011011011101111100011011011010100110110111 source: ; no change source: 100000000000000000000000000000000001111100011011011010100110110111 changed: 00 00 0 0 00 00 00 00 000 step 83 100000000000000000000000000000000001111100011011011010100110110111 source: source: ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; source: ; test shifting the RWB source: ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; source: source: ; shift in 0, expect 10 source: 0 changed: 0 step 84 100000000000000000000000000000000001111100011011011010100110100111 source: 110 changed: 1 0 step 85 100000000000000000000000000000000001111100011011011010100110101101 source: 0 changed: 0 step 86 100000000000000000000000000000000001111100011011011010100110100101 source: ; toggle phase should toggle RWB 2 source: 0 0 changed: 0 0 step 87 100000000000000000000000000000000001111100011011011010100110000001 source: 1 1 changed: 1 1 step 88 100000000000000000000000000000000001111100011011011010100110100101 source: source: ; shift in 0, expect 00 source: 0 changed: step 89 100000000000000000000000000000000001111100011011011010100110100101 source: 100 changed: 10 step 90 100000000000000000000000000000000001111100011011011010100110101001 source: 0 changed: 0 step 91 100000000000000000000000000000000001111100011011011010100110100001 source: ; toggle phase should toggle RWB 2 source: 0 1 changed: 0 1 step 92 100000000000000000000000000000000001111100011011011010100110000101 source: 1 0 changed: 1 0 step 93 100000000000000000000000000000000001111100011011011010100110100001 source: source: ; shift in 0, expect 00 source: 0 changed: step 94 100000000000000000000000000000000001111100011011011010100110100001 source: 100 changed: 1 step 95 100000000000000000000000000000000001111100011011011010100110101001 source: 0 changed: 0 step 96 100000000000000000000000000000000001111100011011011010100110100001 source: ; shift in 1, expect 01 source: 1 changed: 1 step 97 100000000000000000000000000000000001111100011011011010100110110001 source: 101 changed: 1 1 step 98 100000000000000000000000000000000001111100011011011010100110111011 source: 0 changed: 0 step 99 100000000000000000000000000000000001111100011011011010100110110011 source: ; shift in 1, expect 11 source: 1 changed: step 100 100000000000000000000000000000000001111100011011011010100110110011 source: 111 changed: 11 step 101 100000000000000000000000000000000001111100011011011010100110111111 source: 0 changed: 0 step 102 100000000000000000000000000000000001111100011011011010100110110111 source: ; shift in 1, expect 11 source: 1 changed: step 103 100000000000000000000000000000000001111100011011011010100110110111 source: 111 changed: 1 step 104 100000000000000000000000000000000001111100011011011010100110111111 source: 0 changed: 0 step 105 100000000000000000000000000000000001111100011011011010100110110111 source: ; shift in 0, expect 10 source: 0 changed: 0 step 106 100000000000000000000000000000000001111100011011011010100110100111 source: 110 changed: 1 0 step 107 100000000000000000000000000000000001111100011011011010100110101101 source: 0 changed: 0 step 108 100000000000000000000000000000000001111100011011011010100110100101 source: ; shift in 1, expect 01 source: 1 changed: 1 step 109 100000000000000000000000000000000001111100011011011010100110110101 source: 101 changed: 101 step 110 100000000000000000000000000000000001111100011011011010100110111011 source: 0 changed: 0 step 111 100000000000000000000000000000000001111100011011011010100110110011 source: ; shift in 0, expect 10 source: 0 changed: 0 step 112 100000000000000000000000000000000001111100011011011010100110100011 source: 110 changed: 110 step 113 100000000000000000000000000000000001111100011011011010100110101101 source: 0 changed: 0 step 114 100000000000000000000000000000000001111100011011011010100110100101 source: ; shift in 1, expect 01 source: 1 changed: 1 step 115 100000000000000000000000000000000001111100011011011010100110110101 source: 101 changed: 101 step 116 100000000000000000000000000000000001111100011011011010100110111011 source: 0 changed: 0 step 117 100000000000000000000000000000000001111100011011011010100110110011 source: ; shift in 1, expect 11 source: 1 changed: step 118 100000000000000000000000000000000001111100011011011010100110110011 source: 111 changed: 11 step 119 100000000000000000000000000000000001111100011011011010100110111111 source: 0 changed: 0 step 120 100000000000000000000000000000000001111100011011011010100110110111 source: ; no change source: 100000000000000000000000000000000001111100011011011010100110110111 changed: step 121 100000000000000000000000000000000001111100011011011010100110110111 test 4: pass SLOT BAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBAABBAAAAAAAAAAAAAABBBBBABBBB LETTER ALPSLFMDEEMCBFRSPKLEMFHRSCJLJKUHPNMBBNNVVRKRHUTDJUKANJHBTPDFSVEVDU SIDE 121212122121212121111111112212122222112222111221112112212112212122 DIRECTION IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIOOOOOOOIOOIOOIOOIOOOOIOOIIIIOOO this fail all fails was hi 111111111111111111111111111111111111111111111111111111111111111111 rising ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ ^^^^^^^^^^^^^^^^^^^^^^^^^ falling vvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvv vvvvvvvvvvvvvvvvvvvvvvvvv was lo 00000000000000000000000000000000000000 0000000000000000000000000 total fails 0, total passes 4 source: ; all registers are unknown source: ; turn on C0, PHASE source: ; with no ENABLES, BUS2,BUS3 is 11, C2 is 1 source: 1000000000000000000000000000000000011111000XX0XX0XX0XXXX0XX0110XX1 changed: step 1 100000000000000000000000000000000001111100011011011010100110110111 source: source: ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; source: ; source: ; set all registers LOW source: ; source: ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; source: source: ; load TMA SETUP from tape bus (00) source: 100 changed: 100 step 2 100000000000000000000000000000000001111100100011011010100110110111 source: 0 changed: 0 step 3 100000000000000000000000000000000001111100000011011010100110110111 source: ; load TMA from tape bus (00) source: 100 changed: 100 step 4 100000000000000000000000000000000001111100000100011010100110110111 source: 0 changed: 0 step 5 100000000000000000000000000000000001111100000000011010100110110111 source: ; load TBN from tape bus (00) source: 100 changed: 100 step 6 100000000000000000000000000000000001111100000000100010100110110111 source: 0 changed: 0 step 7 100000000000000000000000000000000001111100000000000010100110110111 source: ; load TAC from tape bus (00) source: 10101 changed: 10101 step 8 100000000000000000000000000000000001111100000000000101010110110111 source: 0 changed: 0 step 9 100000000000000000000000000000000001111100000000000001010110110111 source: ; load TB from tape bus (00) source: 100 changed: 100 step 10 100000000000000000000000000000000001111100000000000001011000110111 source: 0 changed: 0 step 11 100000000000000000000000000000000001111100000000000001010000110111 source: ; load RWB from TB (JAMS CLEAR AND PRESET) source: 1 00 changed: 1 00 step 12 100000000000000000000000000000000001111100000000000001010001110001 source: 0 changed: 0 step 13 100000000000000000000000000000000001111100000000000001010000110001 source: ; (no change) source: 100000000000000000000000000000000001111100000000000001010000110001 changed: step 14 100000000000000000000000000000000001111100000000000001010000110001 source: source: source: ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; source: ; source: ; set all registers HIGH source: ; source: ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; source: source: ; set pin AF1 (AND with itself) to clear pin BB2 (AND-NOR output) and set pin BR2 TAPE BUS 3 OUTPUT source: 1 0 1 changed: 1 0 1 step 15 100000000000010000000000000000000000111101000000000001010000110001 source: ; set pin AP2 (AND with itself) to clear pin AN2 (AND-NOR output) and set pin BV2 TAPE BUS 2 OUTPUT source: 1 0 1 changed: 1 0 1 step 16 100000000000010010000000000000000000110111000000000001010000110001 source: source: source: ; load TMA SETUP from tape bus (11) source: 111 changed: 111 step 17 100000000000010010000000000000000000110111111000000001010000110001 source: 0 changed: 0 step 18 100000000000010010000000000000000000110111011000000001010000110001 source: ; load TMA from tape bus (11) source: 111 changed: 111 step 19 100000000000010010000000000000000000110111011111000001010000110001 source: 0 changed: 0 step 20 100000000000010010000000000000000000110111011011000001010000110001 source: ; load TBN from tape bus (11) source: 111 changed: 111 step 21 100000000000010010000000000000000000110111011011111001010000110001 source: 0 changed: 0 step 22 100000000000010010000000000000000000110111011011011001010000110001 source: ; load TAC from tape bus (11) source: 11010 changed: 11010 step 23 100000000000010010000000000000000000110111011011011110100000110001 source: 0 changed: 0 step 24 100000000000010010000000000000000000110111011011011010100000110001 source: ; load TB from tape bus (11) source: 111 changed: 111 step 25 100000000000010010000000000000000000110111011011011010101110110001 source: 0 changed: 0 step 26 100000000000010010000000000000000000110111011011011010100110110001 source: ; load RWB from TB (JAMS CLEAR AND PRESET) source: 1 11 changed: 1 11 step 27 100000000000010010000000000000000000110111011011011010100111110111 source: 0 changed: 0 step 28 100000000000010010000000000000000000110111011011011010100110110111 source: ; clear pin AF1 (AND with itself) to set pin BB2 (AND-NOR output) and clear pin BR2 TAPE BUS 3 OUTPUT source: 0 1 0 changed: 0 1 0 step 29 100000000000000010000000000000000001110110011011011010100110110111 source: ; clear pin AP2 (AND with itself) to set pin AN2 (AND-NOR output) and clear pin BV2 TAPE BUS 2 OUTPUT source: 0 1 0 changed: 0 1 0 step 30 100000000000000000000000000000000001111100011011011010100110110111 source: ; (no change) source: 100000000000000000000000000000000001111100011011011010100110110111 changed: step 31 100000000000000000000000000000000001111100011011011010100110110111 source: source: source: ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; source: ; source: ; test AND-NOR logic source: ; source: ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; source: source: ; (all registers are HIGH) source: ; set all pins HIGH except ENABLES source: source: ; set pin AF2 HIGH source: 1 changed: 1 step 32 100001000000000000000000000000000001111100011011011010100110110111 source: ; set pin AM1 HIGH source: 1 changed: 1 step 33 100001100000000000000000000000000001111100011011011010100110110111 source: ; set pin AE1 HIGH source: 1 changed: 1 step 34 100001100100000000000000000000000001111100011011011010100110110111 source: ; set pin AM2 HIGH source: 1 changed: 1 step 35 100001100110000000000000000000000001111100011011011010100110110111 source: ; set pin AB2 HIGH source: 1 changed: 1 step 36 100001100110100000000000000000000001111100011011011010100110110111 source: ; set pin AS1 HIGH source: 1 changed: 1 step 37 100001100110100100000000000000000001111100011011011010100110110111 source: ; set pin BE1 HIGH source: 1 changed: 1 step 38 100001100110100100010000000000000001111100011011011010100110110111 source: ; set pin BM1 HIGH source: 1 changed: 1 step 39 100001100110100100011000000000000001111100011011011010100110110111 source: ; set pin BH1 HIGH source: 1 changed: 1 step 40 100001100110100100011010000000000001111100011011011010100110110111 source: ; set pin BR1 HIGH source: 1 changed: 1 step 41 100001100110100100011011000000000001111100011011011010100110110111 source: ; set pin BC1 HIGH source: 1 changed: 1 step 42 100001100110100100011011010000000001111100011011011010100110110111 source: ; set pin BJ2 HIGH source: 1 changed: 1 step 43 100001100110100100011011011000000001111100011011011010100110110111 source: ; set pin BJ1 HIGH source: 1 changed: 1 step 44 100001100110100100011011011010000001111100011011011010100110110111 source: ; set pin BK2 HIGH source: 1 changed: 1 step 45 100001100110100100011011011011000001111100011011011010100110110111 source: ; set pin BH2 HIGH source: 1 changed: 1 step 46 100001100110100100011011011011010001111100011011011010100110110111 source: ; set pin BP2 HIGH source: 1 changed: 1 step 47 100001100110100100011011011011011001111100011011011010100110110111 source: ; set pin BN2 HIGH source: 1 changed: 1 step 48 100001100110100100011011011011011101111100011011011010100110110111 source: ; toggle each ENABLE source: source: ; set pin AL2 to clear pin BB2 and pin AN2 AND-NOR OUTPUTS and set TAPE BUS 2 OUTPUT and TAPE BUS 3 OUTPUT source: 1 0 0 11 changed: 1 0 0 11 step 49 110001100110100100011011011011011100110111011011011010100110110111 source: 0 1 1 00 changed: 0 1 1 00 step 50 100001100110100100011011011011011101111100011011011010100110110111 source: ; set pin AP1 to clear pin BB2 and pin AN2 AND-NOR OUTPUTS and set TAPE BUS 2 OUTPUT and TAPE BUS 3 OUTPUT source: 1 0 0 11 changed: 1 0 0 11 step 51 101001100110100100011011011011011100110111011011011010100110110111 source: 0 1 1 00 changed: 0 1 1 00 step 52 100001100110100100011011011011011101111100011011011010100110110111 source: ; set pin AS2 to clear pin BB2 and pin AN2 AND-NOR OUTPUTS and set TAPE BUS 2 OUTPUT and TAPE BUS 3 OUTPUT source: 1 0 0 11 changed: 1 0 0 11 step 53 100101100110100100011011011011011100110111011011011010100110110111 source: 0 1 1 00 changed: 0 1 1 00 step 54 100001100110100100011011011011011101111100011011011010100110110111 source: ; set pin AL1 to clear pin BB2 and pin AN2 AND-NOR OUTPUTS and set TAPE BUS 2 OUTPUT and TAPE BUS 3 OUTPUT source: 1 0 0 11 changed: 1 0 0 11 step 55 100011100110100100011011011011011100110111011011011010100110110111 source: 0 1 1 00 changed: 0 1 1 00 step 56 100001100110100100011011011011011101111100011011011010100110110111 source: ; set pin AL1 to clear pin BB2 and pin AN2 AND-NOR OUTPUTS and set TAPE BUS 2 OUTPUT and TAPE BUS 3 OUTPUT source: 1 0 0 11 changed: 1 0 0 11 step 57 100001110110100100011011011011011100110111011011011010100110110111 source: 0 1 1 00 changed: 0 1 1 00 step 58 100001100110100100011011011011011101111100011011011010100110110111 source: ; set pin AE2 to clear pin BB2 and pin AN2 AND-NOR OUTPUTS and set TAPE BUS 2 OUTPUT and TAPE BUS 3 OUTPUT source: 1 0 0 11 changed: 1 0 0 11 step 59 100001101110100100011011011011011100110111011011011010100110110111 source: 0 1 1 00 changed: 0 1 1 00 step 60 100001100110100100011011011011011101111100011011011010100110110111 source: ; set pin AC1 to clear pin BB2 and set TAPE BUS 3 OUTPUT source: 1 0 1 changed: 1 0 1 step 61 100001100111100100011011011011011100111101011011011010100110110111 source: 0 1 0 changed: 0 1 0 step 62 100001100110100100011011011011011101111100011011011010100110110111 source: ; set pin AF1 to clear pin BB2 and set TAPE BUS 3 OUTPUT source: 1 0 1 changed: 1 0 1 step 63 100001100110110100011011011011011100111101011011011010100110110111 source: 0 1 0 changed: 0 1 0 step 64 100001100110100100011011011011011101111100011011011010100110110111 source: ; set pin AR2 to clear pin AN2 AND-NOR OUTPUTS and set TAPE BUS 2 OUTPUT source: 1 0 1 changed: 1 0 1 step 65 100001100110101100011011011011011101110110011011011010100110110111 source: 0 1 0 changed: 0 1 0 step 66 100001100110100100011011011011011101111100011011011010100110110111 source: ; set pin AP2 to clear pin AN2 AND-NOR OUTPUTS and set TAPE BUS 2 OUTPUT source: 1 0 1 changed: 1 0 1 step 67 100001100110100110011011011011011101110110011011011010100110110111 source: 0 1 0 changed: 0 1 0 step 68 100001100110100100011011011011011101111100011011011010100110110111 source: source: ; set pin BK1 to clear pin BB1 and pin BN1 AND-NOR OUTPUTS and set TAPE BUS 2 OUTPUT and TAPE BUS 3 OUTPUT source: 1 00 11 changed: 1 00 11 step 69 100001100110100101011011011011011101001111011011011010100110110111 source: 0 11 00 changed: 0 11 00 step 70 100001100110100100011011011011011101111100011011011010100110110111 source: ; set pin BL1 to clear pin BB1 and pin BN1 AND-NOR OUTPUTS and set TAPE BUS 2 OUTPUT and TAPE BUS 3 OUTPUT source: 1 00 11 changed: 1 00 11 step 71 100001100110100100111011011011011101001111011011011010100110110111 source: 0 11 00 changed: 0 11 00 step 72 100001100110100100011011011011011101111100011011011010100110110111 source: ; set pin BF1 to clear pin BB1 and pin BN1 AND-NOR OUTPUTS and set TAPE BUS 2 OUTPUT and TAPE BUS 3 OUTPUT source: 1 00 11 changed: 1 00 11 step 73 100001100110100100011111011011011101001111011011011010100110110111 source: 0 11 00 changed: 0 11 00 step 74 100001100110100100011011011011011101111100011011011010100110110111 source: ; set pin BS1 to clear pin BB1 and pin BN1 AND-NOR OUTPUTS and set TAPE BUS 2 OUTPUT and TAPE BUS 3 OUTPUT source: 1 00 11 changed: 1 00 11 step 75 100001100110100100011011111011011101001111011011011010100110110111 source: 0 11 00 changed: 0 11 00 step 76 100001100110100100011011011011011101111100011011011010100110110111 source: ; set pin BL2 to clear pin BB1 and pin BN1 AND-NOR OUTPUTS and set TAPE BUS 2 OUTPUT and TAPE BUS 3 OUTPUT source: 1 00 11 changed: 1 00 11 step 77 100001100110100100011011011111011101001111011011011010100110110111 source: 0 11 00 changed: 0 11 00 step 78 100001100110100100011011011011011101111100011011011010100110110111 source: ; set pin BU1 to clear pin BB1 and pin BN1 AND-NOR OUTPUTS and set TAPE BUS 2 OUTPUT and TAPE BUS 3 OUTPUT source: 1 00 11 changed: 1 00 11 step 79 100001100110100100011011011011111101001111011011011010100110110111 source: 0 11 00 changed: 0 11 00 step 80 100001100110100100011011011011011101111100011011011010100110110111 source: ; set pin BM2 to clear pin BB1 and TAPE BUS 3 OUTPUT source: 1 0 1 changed: 1 0 1 step 81 100001100110100100011011011011011111101110011011011010100110110111 source: 0 1 0 changed: 0 1 0 step 82 100001100110100100011011011011011101111100011011011010100110110111 source: ; no change source: 100000000000000000000000000000000001111100011011011010100110110111 changed: 00 00 0 0 00 00 00 00 000 step 83 100000000000000000000000000000000001111100011011011010100110110111 source: source: ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; source: ; test shifting the RWB source: ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; source: source: ; shift in 0, expect 10 source: 0 changed: 0 step 84 100000000000000000000000000000000001111100011011011010100110100111 source: 110 changed: 1 0 step 85 100000000000000000000000000000000001111100011011011010100110101101 source: 0 changed: 0 step 86 100000000000000000000000000000000001111100011011011010100110100101 source: ; toggle phase should toggle RWB 2 source: 0 0 changed: 0 0 step 87 100000000000000000000000000000000001111100011011011010100110000001 source: 1 1 changed: 1 1 step 88 100000000000000000000000000000000001111100011011011010100110100101 source: source: ; shift in 0, expect 00 source: 0 changed: step 89 100000000000000000000000000000000001111100011011011010100110100101 source: 100 changed: 10 step 90 100000000000000000000000000000000001111100011011011010100110101001 source: 0 changed: 0 step 91 100000000000000000000000000000000001111100011011011010100110100001 source: ; toggle phase should toggle RWB 2 source: 0 1 changed: 0 1 step 92 100000000000000000000000000000000001111100011011011010100110000101 source: 1 0 changed: 1 0 step 93 100000000000000000000000000000000001111100011011011010100110100001 source: source: ; shift in 0, expect 00 source: 0 changed: step 94 100000000000000000000000000000000001111100011011011010100110100001 source: 100 changed: 1 step 95 100000000000000000000000000000000001111100011011011010100110101001 source: 0 changed: 0 step 96 100000000000000000000000000000000001111100011011011010100110100001 source: ; shift in 1, expect 01 source: 1 changed: 1 step 97 100000000000000000000000000000000001111100011011011010100110110001 source: 101 changed: 1 1 step 98 100000000000000000000000000000000001111100011011011010100110111011 source: 0 changed: 0 step 99 100000000000000000000000000000000001111100011011011010100110110011 source: ; shift in 1, expect 11 source: 1 changed: step 100 100000000000000000000000000000000001111100011011011010100110110011 source: 111 changed: 11 step 101 100000000000000000000000000000000001111100011011011010100110111111 source: 0 changed: 0 step 102 100000000000000000000000000000000001111100011011011010100110110111 source: ; shift in 1, expect 11 source: 1 changed: step 103 100000000000000000000000000000000001111100011011011010100110110111 source: 111 changed: 1 step 104 100000000000000000000000000000000001111100011011011010100110111111 source: 0 changed: 0 step 105 100000000000000000000000000000000001111100011011011010100110110111 source: ; shift in 0, expect 10 source: 0 changed: 0 step 106 100000000000000000000000000000000001111100011011011010100110100111 source: 110 changed: 1 0 step 107 100000000000000000000000000000000001111100011011011010100110101101 source: 0 changed: 0 step 108 100000000000000000000000000000000001111100011011011010100110100101 source: ; shift in 1, expect 01 source: 1 changed: 1 step 109 100000000000000000000000000000000001111100011011011010100110110101 source: 101 changed: 101 step 110 100000000000000000000000000000000001111100011011011010100110111011 source: 0 changed: 0 step 111 100000000000000000000000000000000001111100011011011010100110110011 source: ; shift in 0, expect 10 source: 0 changed: 0 step 112 100000000000000000000000000000000001111100011011011010100110100011 source: 110 changed: 110 step 113 100000000000000000000000000000000001111100011011011010100110101101 source: 0 changed: 0 step 114 100000000000000000000000000000000001111100011011011010100110100101 source: ; shift in 1, expect 01 source: 1 changed: 1 step 115 100000000000000000000000000000000001111100011011011010100110110101 source: 101 changed: 101 step 116 100000000000000000000000000000000001111100011011011010100110111011 source: 0 changed: 0 step 117 100000000000000000000000000000000001111100011011011010100110110011 source: ; shift in 1, expect 11 source: 1 changed: step 118 100000000000000000000000000000000001111100011011011010100110110011 space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C toggle comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit scope (run, no print) pppppppppppppppppppppppppppppFppppppppppppppppppppppppppppppppppppppppppppppppp ppppppppppppppppppppppppppppppppppppppppppppppppppppppppppp space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C toggle comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT BAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBAABBAAAAAAAAAAAAAABBBBBABBBB LETTER ALPSLFMDEEMCBFRSPKLEMFHRSCJLJKUHPNMBBNNVVRKRHUTDJUKANJHBTPDFSVEVDU SIDE 121212122121212121111111112212122222112222111221112112212112212122 DIRECTION IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIOOOOOOOIOOIOOIOOIOOOOIOOIIIIOOO all fails I I I O O was lo 00000000000000000000000000000000000000 0000000000000000000000000 falling vvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvv vvvvvvvvvvvvvvvvvvvvvvvvv rising ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ ^^^^^^^^^^^^^^^^^^^^^^^^^ was hi 111111111111111111111111111111111111111111111111111111111111111111 total fails 1, total passes 141 Main menu Thu Aug 20 18:41:13 2015 test file is: tests\m222.tst delay is: 0 trigger is: 1 1 read test file 2 set test delay 3 set test trigger 4 run test 5 output loading test 8 diags 9 exit Enter test file name? trying to open test file: tests\m222.new reading test file: tests\m222.new comment: M222 PCB REV B SCHEMATIC REV A LINC TAPE REGISTERS comment: comment: TERMINOLOGY- SIGNALS REFER TO PDP12 MAINT VOL4 M222 SCHEMATIC. comment: comment: BUT... comment: comment: DEC USES AND-NOR GATES TO ROUTE THE ADDER A AND B INPUTS, SO... comment: DEC RENAMED THE ADDER TO NEGATIVE LOGIC TERMS (I.E. A-N + B-N + C-N -> SUM-N, C1-N). comment: (NOT THE 7482 DATASHEET NAMES OF A + B + C -> SUM, C1). comment: comment: SO, WITH ALL 'AND ENABLES' LOW, THE AND-NOR OUTPUTS = HIGH. comment: WITH C-L HIGH, THE ADDER OUTPUT IS SUM-N=1, C1-N=1; comment: THE INVERTED ADDER OUTPUT IS LOW (TAPE BUS). comment: AND THERE IS NO CARRY (C1-N IS HI). comment: comment: THE TWO ADDERS, TWO REGISTER BITS, ETC ARE LABELED BIT 2 (EVEN, MSB) AND BIT 3 (ODD, LSB). comment: THE ADDERS ARE REFERRED TO AS 'ADDER2' (MSB) AND 'ADDER3' (LSB). comment: comment: POWER PINS: comment: AA2 +5V comment: AT1 GROUND comment: AC2 GROUND comment: BA2 +5V comment: BT1 GROUND comment: BC2 GROUND comment: comment: (ALL PINS ARE USED). comment: comment: pins: PINS pins: 1 I BA1 CARRY IN-N, (TO E9-5 7482 C0) C-N TO ADDER2 pins: 2 I AL2 AND-NOR ENABLE: TAC TAC3 TO PIN BB2 (TO ADDER3) TAC2 TO PIN AN2 (TO ADDER2) pins: 3 I AP1 AND-NOR ENABLE: TMA SETUP (TMAS)3 TO PIN BB2 (TO ADDER3), (TMAS)3 TO PIN AN2 (TO ADDER2) pins: 4 I AS2 AND-NOR ENABLE: TMA TMA3 TO PIN BB2 (TO ADDER3), TMA2 TO PIN AN2 (TO ADDER2) pins: 5 I AL1 AND-NOR ENABLE: PIN AF2 TO PIN BB2 (TO ADDER3), PIN AM1 TO PIN AN2 (TO ADDER2) pins: 6 I AF2 AND-NOR INPUT (AL1 ENABLES) TO PIN BB2 (TO ADDER3). pins: 7 I AM1 AND-NOR INPUT (AL1 ENABLES) TO PIN AN2 (TO ADDER2) pins: 8 I AD2 AND-NOR ENABLE: RWB RWB3 TO PIN BB2 (TO ADDER3), RWB2 TO PIN AN2 (TO ADDER2) pins: 9 I AE2 AND-NOR ENABLE: PIN AE1 TO PIN BB2 (TO ADDER3), PIN AM2 TO PIN AN2 (TO ADDER2) pins: 10 I AE1 AND-NOR INPUT (AE2 ENABLES) TO PIN BB2 (TO ADDER3). pins: 11 I AM2 AND-NOR INPUT (AE2 ENABLES) TO PIN AN2 (TO ADDER2) pins: 12 I AC1 AND-NOR INPUT, AND WITH PIN AB2 TO PIN BB2 (TO ADDER3) pins: 13 I AB2 AND-NOR INPUT, AND WITH PIN AC1 TO PIN BB2 (TO ADDER3) pins: 14 I AF1 AND-NOR INPUT (AND WITH ITSELF) TO PIN BB2 (TO ADDER3) pins: 15 I AR2 AND-NOR INPUT, AND WITH PIN AS1 TO PIN AN2 (TO ADDER2) pins: 16 I AS1 AND-NOR INPUT, AND WITH PIN AR2 TO PIN AN2 (TO ADDER2) pins: 17 I AP2 AND-NOR INPUT (AND WITH ITSELF) TO PIN AN2 (TO ADDER2) pins: 18 I BK1 AND-NOR ENABLE: TB3 TO PIN BB1 (TO ADDER3), TB2 TO PIN BN1 (TO ADDER2) pins: 19 I BL1 AND-NOR ENABLE: PIN BE1 TO PIN BB1 (TO ADDER3), PIN BM1 TO PIN BN1 (TO ADDER2) pins: 20 I BE1 AND-NOR INPUT (BL1 ENABLES) TO PIN BB1 (TO ADDER3). pins: 21 I BM1 AND-NOR INPUT (BL1 ENABLES) TO PIN BN1 (TO ADDER2) pins: 22 I BF1 AND-NOR ENABLE: PIN BH1 TO PIN BB1 (TO ADDER3), PIN BR1 TO PIN BN1 (TO ADDER2) pins: 23 I BH1 AND-NOR INPUT (BF1 ENABLES): TO PIN BB1 (TO ADDER3), pins: 24 I BR1 AND-NOR INPUT (BF1 ENABLES): TO PIN BN1 (TO ADDER2) pins: 25 I BS1 AND-NOR ENABLE: PIN BC1 TO PIN BB1 (TO ADDER3), PIN BJ2 TO PIN BN1 (TO ADDER2) pins: 26 I BC1 AND-NOR INPUT (BS1 ENABLES): TO PIN BB1 (TO ADDER3), pins: 27 I BJ2 AND-NOR INPUT (BS1 ENABLES): TO PIN BN1 (TO ADDER2) pins: 28 I BL2 AND-NOR ENABLE: PIN BJ1 TO PIN BB1 (TO ADDER3), PIN BK2 TO PIN BN1 (TO ADDER2) pins: 29 I BJ1 AND-NOR INPUT (BL2 ENABLES): TO PIN BB1 (TO ADDER3), pins: 30 I BK2 AND-NOR INPUT (BL2 ENABLES): TO PIN BN1 (TO ADDER2) pins: 31 I BU1 AND-NOR ENABLE: PIN BH2 TO PIN BB1 (TO ADDER3), PIN BP2 TO PIN BN1 (TO ADDER2) pins: 32 I BH2 AND-NOR INPUT (BU1 ENABLES): TO PIN BB1 (TO ADDER3), pins: 33 I BP2 AND-NOR INPUT (BU1 ENABLES): TO PIN BN1 (TO ADDER2) pins: 34 I BN2 AND-NOR INPUT (AND WITH BM2): TO PIN BN1 (TO ADDER2) pins: 35 I BM2 AND-NOR INPUT (AND WITH BM2): TO PIN BN1 (TO ADDER2) pins: 36 O BB2 AND-NOR OUTPUT, (DRIVES E9-2 7482 A1) TO ADDER3 INPUT pins: 37 O BB1 AND-NOR OUTPUT, (DRIVES E9-3 7482 B1) TO ADDER3 INPUT pins: 38 O BN1 AND-NOR OUTPUT, (DRIVES E9-14 7482 A2) TO ADDER2 INPUT pins: 39 O AN2 AND-NOR OUTPUT, (DRIVES E9-13 7482 B2) TO ADDER2 INPUT pins: 40 O AV2 CARRY OUT-N (E9-10 7482 C2) pins: 41 O BV2 TAPE BUS 2 OUTPUT (INVERTED ADDER2 SUM-N (E9-12 7482 SUM2) pins: 42 O BR2 TAPE BUS 3 OUTPUT (INVERTED ADDER3 SUM-N (E9-1 7482 SUM1) pins: 43 I AK1 LOAD TMA SETUP (FROM TAPE BUS) (RISING EDGE CLOCK) pins: 44 O AR1 TMA SETUP 2 pins: 45 O AH1 TMA SETUP 3 pins: 46 I AU2 LOAD TMA (FROM TAPE BUS) (RISING EDGE CLOCK) pins: 47 O AT2 TMA 2 pins: 48 O AD1 TMA 3 pins: 49 I AJ1 LOAD TBN (FROM TAPE BUS) (RISING EDGE CLOCK) pins: 50 O AU1 TBN 2 pins: 51 O AK2 TBN 3 pins: 52 I AA1 LOAD TAC (FROM TAPE BUS) (RISING EDGE CLOCK) pins: 53 O AN1 TAC 2 pins: 54 O AJ2 TAC 2-N pins: 55 O AH2 TAC 3 pins: 56 O AB1 TAC 3-N pins: 57 I BT2 LOAD TB (FROM TAPE BUS) (RISING EDGE CLOCK) pins: 58 O BP1 TB 2 pins: 59 O BD1 TB 3 pins: 60 I BF2 LOAD RWB (FROM TB) (JAMS CLEAR,SET) pins: 61 I BS2 PHASE (SELECTS POLARITY OF RWB OUT, 0 -> INVERTED) pins: 62 I AV1 RWB IN (SHIFTED INTO RWB 3) pins: 63 I BE2 SHIFT RWB (SHIFTS PIN AV1 INTO RWB 3, SHIFTS RWB3 TO RWB2) (RISING CLOCK) pins: 64 O BV1 RWB OUT (IF PHASE=1, =RWB 2; IF PHASE=0; =RWB 2-N) pins: 65 O BD2 RWB 3 pins: 66 O BU2 +3.5V pins: direction: IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIOOOOOOOIOOIOOIOOIOOOOIOOIIIIOOO comment: ; all registers are unknown comment: ; turn on C0, PHASE comment: ; with no ENABLES, BUS2,BUS3 is 11, C2 is 1 test 1: 1000000000000000000000000000000000011111000XX0XX0XX0XXXX0XX0110XX1 comment: comment: ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; comment: ; comment: ; set all registers LOW comment: ; comment: ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; comment: comment: ; load TMA SETUP from tape bus (00) test 2: 100 test 3: 0 comment: ; load TMA from tape bus (00) test 4: 100 test 5: 0 comment: ; load TBN from tape bus (00) test 6: 100 test 7: 0 comment: ; load TAC from tape bus (00) test 8: 10101 test 9: 0 comment: ; load TB from tape bus (00) test 10: 100 test 11: 0 comment: ; load RWB from TB (JAMS CLEAR AND PRESET) test 12: 1 00 test 13: 0 comment: ; (no change) test 14: 100000000000000000000000000000000001111100000000000001010000110001 comment: comment: comment: ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; comment: ; comment: ; set all registers HIGH comment: ; comment: ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; comment: comment: ; set pin AF1 which clears pin BB2 and sets pin BR2 TAPE BUS 3 OUTPUT test 15: 1 0 1 comment: ; set pin AP2 which clears pin AN2 and sets pin BV2 TAPE BUS 2 OUTPUT test 16: 1 0 1 comment: comment: comment: ; load TMA SETUP from tape bus (11) test 17: 111 test 18: 0 comment: ; load TMA from tape bus (11) test 19: 111 test 20: 0 comment: ; load TBN from tape bus (11) test 21: 111 test 22: 0 comment: ; load TAC from tape bus (11) test 23: 11010 test 24: 0 comment: ; load TB from tape bus (11) test 25: 111 test 26: 0 comment: ; load RWB from TB (JAMS CLEAR AND PRESET) test 27: 1 11 test 28: 0 comment: ; clear pin AF1 (AND with itself) to set pin BB2 (AND-NOR output) and clear pin BR2 TAPE BUS 3 OUTPUT test 29: 0 1 0 comment: ; clear pin AP2 (AND with itself) to set pin AN2 (AND-NOR output) and clear pin BV2 TAPE BUS 2 OUTPUT test 30: 0 1 0 comment: ; (no change) test 31: 100000000000000000000000000000000001111100011011011010100110110111 comment: comment: ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; comment: ; comment: ; will all registers high, walk a 0 comment: ; comment: ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; comment: comment: comment: ; walk a 0, TMA SETUP 2 comment: comment: comment: ; clear pin AP2 which sets pin AN2 and clears pin BV2 TAPE BUS 2 OUTPUT test 32: 0 1 0 comment: ; set pin AF1 which clears pin BB2 and sets pin BR2 TAPE BUS 3 OUTPUT test 33: 1 0 1 comment: ; load TMA SETUP from tape bus (01) test 34: 101 test 35: 0 comment: ; restore TMA SETUP 2 comment: ; set pin AP2 which clears pin AN2 and sets pin BV2 TAPE BUS 2 OUTPUT test 36: 1 0 1 comment: ; load TMA SETUP from tape bus (11) test 37: 111 test 38: 0 comment: comment: comment: ; walk a 0, TMA SETUP 3 comment: comment: comment: ; set pin AP2 which clears pin AN2 and sets pin BV2 TAPE BUS 2 OUTPUT test 39: 1 0 1 comment: ; clear pin AF1 which sets pin BB2 and clears pin BR2 TAPE BUS 3 OUTPUT test 40: 0 1 0 comment: ; load TMA SETUP from tape bus (10) test 41: 110 test 42: 0 comment: ; restore TMA SETUP 3 comment: ; set pin AF1 which clears pin BB2 and sets pin BR2 TAPE BUS 3 OUTPUT test 43: 1 0 1 comment: ; load TMA SETUP from tape bus (11) test 44: 111 test 45: 0 comment: comment: comment: ; walk a 0, TMA 2 comment: comment: comment: ; clear pin AP2 which sets pin AN2 and clears pin BV2 TAPE BUS 2 OUTPUT test 46: 0 1 0 comment: ; set pin AF1 which clears pin BB2 and sets pin BR2 TAPE BUS 3 OUTPUT test 47: 1 0 1 comment: ; load TMA from tape bus (01) test 48: 101 test 49: 0 comment: ; restore TMA 2 comment: ; set pin AP2 which clears pin AN2 and sets pin BV2 TAPE BUS 2 OUTPUT test 50: 1 0 1 comment: ; load TMA from tape bus (11) test 51: 111 test 52: 0 comment: comment: comment: ; walk a 0, TMA 3 comment: comment: comment: ; set pin AP2 which clears pin AN2 and sets pin BV2 TAPE BUS 2 OUTPUT test 53: 1 0 1 comment: ; clear pin AF1 which sets pin BB2 and clears pin BR2 TAPE BUS 3 OUTPUT test 54: 0 1 0 comment: ; load TMA from tape bus (10) test 55: 110 test 56: 0 comment: ; restore TMA 3 comment: ; set pin AF1 which clears pin BB2 and sets pin BR2 TAPE BUS 3 OUTPUT test 57: 1 0 1 comment: ; load TMA from tape bus (11) test 58: 111 test 59: 0 comment: comment: comment: ; walk a 0, TBN 2 comment: comment: comment: ; clear pin AP2 which sets pin AN2 and clears pin BV2 TAPE BUS 2 OUTPUT test 60: 0 1 0 comment: ; set pin AF1 which clears pin BB2 and sets pin BR2 TAPE BUS 3 OUTPUT test 61: 1 0 1 comment: ; load TBN from tape bus (01) test 62: 101 test 63: 0 comment: ; restore TBN 2 comment: ; set pin AP2 which clears pin AN2 and sets pin BV2 TAPE BUS 2 OUTPUT test 64: 1 0 1 comment: ; load TBN from tape bus (11) test 65: 111 test 66: 0 comment: comment: comment: ; walk a 0, TBN 3 comment: comment: comment: ; set pin AP2 which clears pin AN2 and sets pin BV2 TAPE BUS 2 OUTPUT test 67: 1 0 1 comment: ; clear pin AF1 which sets pin BB2 and clears pin BR2 TAPE BUS 3 OUTPUT test 68: 0 1 0 comment: ; load TBN from tape bus (10) test 69: 110 test 70: 0 comment: ; restore TBN 3 comment: ; set pin AF1 which clears pin BB2 and sets pin BR2 TAPE BUS 3 OUTPUT test 71: 1 0 1 comment: ; load TBN from tape bus (11) test 72: 111 test 73: 0 comment: comment: comment: ; walk a 0, TAC 2 comment: comment: comment: ; clear pin AP2 which sets pin AN2 and clears pin BV2 TAPE BUS 2 OUTPUT test 74: 0 1 0 comment: ; set pin AF1 which clears pin BB2 and sets pin BR2 TAPE BUS 3 OUTPUT test 75: 1 0 1 comment: ; load TAC from tape bus (01) test 76: 10110 test 77: 0 comment: ; restore TAC 2 comment: ; set pin AP2 which clears pin AN2 and sets pin BV2 TAPE BUS 2 OUTPUT test 78: 1 0 1 comment: ; load TAC from tape bus (11) test 79: 11010 test 80: 0 comment: comment: comment: ; walk a 0, TAC 3 comment: comment: comment: ; set pin AP2 which clears pin AN2 and sets pin BV2 TAPE BUS 2 OUTPUT test 81: 1 0 1 comment: ; clear pin AF1 which sets pin BB2 and clears pin BR2 TAPE BUS 3 OUTPUT test 82: 0 1 0 comment: ; load TAC from tape bus (10) test 83: 11001 test 84: 0 comment: ; restore TAC 3 comment: ; set pin AF1 which clears pin BB2 and sets pin BR2 TAPE BUS 3 OUTPUT test 85: 1 0 1 comment: ; load TAC from tape bus (11) test 86: 11010 test 87: 0 comment: comment: comment: comment: comment: comment: comment: comment: comment: comment: comment: comment: comment: comment: comment: comment: comment: comment: comment: comment: ; load TB from tape bus (00) test 88: 100 test 89: 0 comment: ; load RWB from TB (JAMS CLEAR AND PRESET) test 90: 1 00 test 91: 0 comment: comment: comment: comment: comment: comment: comment: comment: comment: comment: comment: comment: comment: comment: comment: ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; comment: ; comment: ; test AND-NOR logic comment: ; comment: ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; comment: comment: ; (all registers are HIGH) comment: ; set all pins HIGH except ENABLES comment: comment: ; set pin AF2 HIGH test 92: 1 comment: ; set pin AM1 HIGH test 93: 1 comment: ; set pin AE1 HIGH test 94: 1 comment: ; set pin AM2 HIGH test 95: 1 comment: ; set pin AB2 HIGH test 96: 1 comment: ; set pin AS1 HIGH test 97: 1 comment: ; set pin BE1 HIGH test 98: 1 comment: ; set pin BM1 HIGH test 99: 1 comment: ; set pin BH1 HIGH test 100: 1 comment: ; set pin BR1 HIGH test 101: 1 comment: ; set pin BC1 HIGH test 102: 1 comment: ; set pin BJ2 HIGH test 103: 1 comment: ; set pin BJ1 HIGH test 104: 1 comment: ; set pin BK2 HIGH test 105: 1 comment: ; set pin BH2 HIGH test 106: 1 comment: ; set pin BP2 HIGH test 107: 1 comment: ; set pin BN2 HIGH test 108: 1 comment: ; toggle each ENABLE comment: comment: ; set pin AL2 to clear pin BB2 and pin AN2 AND-NOR OUTPUTS and set TAPE BUS 2 OUTPUT and TAPE BUS 3 OUTPUT test 109: 1 0 0 11 test 110: 0 1 1 00 comment: ; set pin AP1 to clear pin BB2 and pin AN2 AND-NOR OUTPUTS and set TAPE BUS 2 OUTPUT and TAPE BUS 3 OUTPUT test 111: 1 0 0 11 test 112: 0 1 1 00 comment: ; set pin AS2 to clear pin BB2 and pin AN2 AND-NOR OUTPUTS and set TAPE BUS 2 OUTPUT and TAPE BUS 3 OUTPUT test 113: 1 0 0 11 test 114: 0 1 1 00 comment: ; set pin AL1 to clear pin BB2 and pin AN2 AND-NOR OUTPUTS and set TAPE BUS 2 OUTPUT and TAPE BUS 3 OUTPUT test 115: 1 0 0 11 test 116: 0 1 1 00 comment: ; set pin AL1 to clear pin BB2 and pin AN2 AND-NOR OUTPUTS and set TAPE BUS 2 OUTPUT and TAPE BUS 3 OUTPUT test 117: 1 0 0 11 test 118: 0 1 1 00 comment: ; set pin AE2 to clear pin BB2 and pin AN2 AND-NOR OUTPUTS and set TAPE BUS 2 OUTPUT and TAPE BUS 3 OUTPUT test 119: 1 0 0 11 test 120: 0 1 1 00 comment: ; set pin AC1 to clear pin BB2 and set TAPE BUS 3 OUTPUT test 121: 1 0 1 test 122: 0 1 0 comment: ; set pin AF1 to clear pin BB2 and set TAPE BUS 3 OUTPUT test 123: 1 0 1 test 124: 0 1 0 comment: ; set pin AR2 to clear pin AN2 AND-NOR OUTPUTS and set TAPE BUS 2 OUTPUT test 125: 1 0 1 test 126: 0 1 0 comment: ; set pin AP2 to clear pin AN2 AND-NOR OUTPUTS and set TAPE BUS 2 OUTPUT test 127: 1 0 1 test 128: 0 1 0 comment: comment: ; set pin BK1 to clear pin BB1 and pin BN1 AND-NOR OUTPUTS and set TAPE BUS 2 OUTPUT and TAPE BUS 3 OUTPUT test 129: 1 00 11 test 130: 0 11 00 comment: ; set pin BL1 to clear pin BB1 and pin BN1 AND-NOR OUTPUTS and set TAPE BUS 2 OUTPUT and TAPE BUS 3 OUTPUT test 131: 1 00 11 test 132: 0 11 00 comment: ; set pin BF1 to clear pin BB1 and pin BN1 AND-NOR OUTPUTS and set TAPE BUS 2 OUTPUT and TAPE BUS 3 OUTPUT test 133: 1 00 11 test 134: 0 11 00 comment: ; set pin BS1 to clear pin BB1 and pin BN1 AND-NOR OUTPUTS and set TAPE BUS 2 OUTPUT and TAPE BUS 3 OUTPUT test 135: 1 00 11 test 136: 0 11 00 comment: ; set pin BL2 to clear pin BB1 and pin BN1 AND-NOR OUTPUTS and set TAPE BUS 2 OUTPUT and TAPE BUS 3 OUTPUT test 137: 1 00 11 test 138: 0 11 00 comment: ; set pin BU1 to clear pin BB1 and pin BN1 AND-NOR OUTPUTS and set TAPE BUS 2 OUTPUT and TAPE BUS 3 OUTPUT test 139: 1 00 11 test 140: 0 11 00 comment: ; set pin BM2 to clear pin BB1 and TAPE BUS 3 OUTPUT test 141: 1 0 1 test 142: 0 1 0 comment: ; no change test 143: 100000000000000000000000000000000001111100011011011010100110110111 comment: comment: ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; comment: ; test shifting the RWB comment: ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; comment: comment: ; shift in 0, expect 10 test 144: 0 test 145: 110 test 146: 0 comment: ; toggle phase should toggle RWB 2 test 147: 0 0 test 148: 1 1 comment: comment: ; shift in 0, expect 00 test 149: 0 test 150: 100 test 151: 0 comment: ; toggle phase should toggle RWB 2 test 152: 0 1 test 153: 1 0 comment: comment: ; shift in 0, expect 00 test 154: 0 test 155: 100 test 156: 0 comment: ; shift in 1, expect 01 test 157: 1 test 158: 101 test 159: 0 comment: ; shift in 1, expect 11 test 160: 1 test 161: 111 test 162: 0 comment: ; shift in 1, expect 11 test 163: 1 test 164: 111 test 165: 0 comment: ; shift in 0, expect 10 test 166: 0 test 167: 110 test 168: 0 comment: ; shift in 1, expect 01 test 169: 1 test 170: 101 test 171: 0 comment: ; shift in 0, expect 10 test 172: 0 test 173: 110 test 174: 0 comment: ; shift in 1, expect 01 test 175: 1 test 176: 101 test 177: 0 comment: ; shift in 1, expect 11 test 178: 1 test 179: 111 test 180: 0 comment: ; no change test 181: 100000000000000000000000000000000001111100011011011010100110110111 comment: comment: ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; comment: ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; comment: ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; comment: ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; comment: ; needs work (more adder tests, more register tests) comment: ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; comment: ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; comment: ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; comment: ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; end: END summary column 1: offset 2, mask 0x2000 column 2: offset 1, mask 0x0002 column 3: offset 1, mask 0x0800 column 4: offset 1, mask 0x0040 column 5: offset 1, mask 0x4000 column 6: offset 0, mask 0x0004 column 7: offset 1, mask 0x2000 column 8: offset 0, mask 0x0010 column 9: offset 0, mask 0x0008 column 10: offset 0, mask 0x0800 column 11: offset 1, mask 0x0004 column 12: offset 0, mask 0x2000 column 13: offset 0, mask 0x0040 column 14: offset 0, mask 0x0400 column 15: offset 1, mask 0x0020 column 16: offset 1, mask 0x0200 column 17: offset 1, mask 0x0010 column 18: offset 3, mask 0x2000 column 19: offset 3, mask 0x1000 column 20: offset 2, mask 0x0200 column 21: offset 3, mask 0x0800 column 22: offset 2, mask 0x0100 column 23: offset 3, mask 0x8000 column 24: offset 3, mask 0x0100 column 25: offset 4, mask 0x8000 column 26: offset 2, mask 0x0800 column 27: offset 3, mask 0x0002 column 28: offset 3, mask 0x0008 column 29: offset 3, mask 0x4000 column 30: offset 3, mask 0x0004 column 31: offset 4, mask 0x2000 column 32: offset 3, mask 0x0001 column 33: offset 3, mask 0x0040 column 34: offset 3, mask 0x0020 column 35: offset 3, mask 0x0010 column 36: offset 2, mask 0x0008 column 37: offset 2, mask 0x1000 column 38: offset 3, mask 0x0400 column 39: offset 1, mask 0x0008 column 40: offset 2, mask 0x0002 column 41: offset 4, mask 0x0008 column 42: offset 3, mask 0x0080 column 43: offset 1, mask 0x8000 column 44: offset 1, mask 0x0400 column 45: offset 0, mask 0x0200 column 46: offset 2, mask 0x0001 column 47: offset 1, mask 0x0080 column 48: offset 0, mask 0x1000 column 49: offset 0, mask 0x0100 column 50: offset 2, mask 0x8000 column 51: offset 1, mask 0x0001 column 52: offset 0, mask 0x8000 column 53: offset 1, mask 0x1000 column 54: offset 0, mask 0x0001 column 55: offset 0, mask 0x0002 column 56: offset 0, mask 0x4000 column 57: offset 4, mask 0x0002 column 58: offset 3, mask 0x0200 column 59: offset 2, mask 0x0400 column 60: offset 2, mask 0x0080 column 61: offset 4, mask 0x0001 column 62: offset 2, mask 0x4000 column 63: offset 2, mask 0x0040 column 64: offset 4, mask 0x1000 column 65: offset 2, mask 0x0020 column 66: offset 4, mask 0x0004 direction bits (1=input) 0x52A3 0x1589 0x943A 0x0680 0x50FC pullup bits (1=pullup) 0x0000 0x0000 0x0000 0x0000 0x0000 test step out_data dont care 1: 0x0000 0x0008 0x700A 0x0400 0x0005 0x5203 0x1481 0x8420 0x0200 0x1000 2: 0x0000 0x8008 0x700A 0x0400 0x0005 0x5003 0x1081 0x8420 0x0200 0x1000 3: 0x0000 0x0008 0x700A 0x0400 0x0005 0x5003 0x1081 0x8420 0x0200 0x1000 4: 0x0000 0x0008 0x700B 0x0400 0x0005 0x4003 0x1001 0x8420 0x0200 0x1000 5: 0x0000 0x0008 0x700A 0x0400 0x0005 0x4003 0x1001 0x8420 0x0200 0x1000 6: 0x0100 0x0008 0x700A 0x0400 0x0005 0x4003 0x1000 0x0420 0x0200 0x1000 7: 0x0000 0x0008 0x700A 0x0400 0x0005 0x4003 0x1000 0x0420 0x0200 0x1000 8: 0xC001 0x0008 0x700A 0x0400 0x0005 0x0000 0x0000 0x0420 0x0200 0x1000 9: 0x4001 0x0008 0x700A 0x0400 0x0005 0x0000 0x0000 0x0420 0x0200 0x1000 10: 0x4001 0x0008 0x700A 0x0400 0x0007 0x0000 0x0000 0x0020 0x0000 0x1000 11: 0x4001 0x0008 0x700A 0x0400 0x0005 0x0000 0x0000 0x0020 0x0000 0x1000 12: 0x4001 0x0008 0x708A 0x0400 0x0005 13: 0x4001 0x0008 0x700A 0x0400 0x0005 14: 0x4001 0x0008 0x700A 0x0400 0x0005 15: 0x4401 0x0008 0x7002 0x0480 0x0005 16: 0x4401 0x0010 0x7002 0x0480 0x000D 17: 0x4601 0x8410 0x7002 0x0480 0x000D 18: 0x4601 0x0410 0x7002 0x0480 0x000D 19: 0x5601 0x0490 0x7003 0x0480 0x000D 20: 0x5601 0x0490 0x7002 0x0480 0x000D 21: 0x5701 0x0491 0xF002 0x0480 0x000D 22: 0x5601 0x0491 0xF002 0x0480 0x000D 23: 0x9602 0x1491 0xF002 0x0480 0x000D 24: 0x1602 0x1491 0xF002 0x0480 0x000D 25: 0x1602 0x1491 0xF402 0x0680 0x000F 26: 0x1602 0x1491 0xF402 0x0680 0x000D 27: 0x1602 0x1491 0xF4A2 0x0680 0x100D 28: 0x1602 0x1491 0xF422 0x0680 0x100D 29: 0x1202 0x1491 0xF42A 0x0600 0x100D 30: 0x1202 0x1489 0xF42A 0x0600 0x1005 31: 0x1202 0x1489 0xF42A 0x0600 0x1005 32: 0x1202 0x1489 0xF42A 0x0600 0x1005 33: 0x1602 0x1489 0xF422 0x0680 0x1005 34: 0x1602 0x9089 0xF422 0x0680 0x1005 35: 0x1602 0x1089 0xF422 0x0680 0x1005 36: 0x1602 0x1091 0xF422 0x0680 0x100D 37: 0x1602 0x9491 0xF422 0x0680 0x100D 38: 0x1602 0x1491 0xF422 0x0680 0x100D 39: 0x1602 0x1491 0xF422 0x0680 0x100D 40: 0x1202 0x1491 0xF42A 0x0600 0x100D 41: 0x1002 0x9491 0xF42A 0x0600 0x100D 42: 0x1002 0x1491 0xF42A 0x0600 0x100D 43: 0x1402 0x1491 0xF422 0x0680 0x100D 44: 0x1602 0x9491 0xF422 0x0680 0x100D 45: 0x1602 0x1491 0xF422 0x0680 0x100D 46: 0x1602 0x1489 0xF422 0x0680 0x1005 47: 0x1602 0x1489 0xF422 0x0680 0x1005 48: 0x1602 0x1409 0xF423 0x0680 0x1005 49: 0x1602 0x1409 0xF422 0x0680 0x1005 50: 0x1602 0x1411 0xF422 0x0680 0x100D 51: 0x1602 0x1491 0xF423 0x0680 0x100D 52: 0x1602 0x1491 0xF422 0x0680 0x100D 53: 0x1602 0x1491 0xF422 0x0680 0x100D 54: 0x1202 0x1491 0xF42A 0x0600 0x100D 55: 0x0202 0x1491 0xF42B 0x0600 0x100D 56: 0x0202 0x1491 0xF42A 0x0600 0x100D 57: 0x0602 0x1491 0xF422 0x0680 0x100D 58: 0x1602 0x1491 0xF423 0x0680 0x100D 59: 0x1602 0x1491 0xF422 0x0680 0x100D 60: 0x1602 0x1489 0xF422 0x0680 0x1005 61: 0x1602 0x1489 0xF422 0x0680 0x1005 62: 0x1702 0x1489 0x7422 0x0680 0x1005 63: 0x1602 0x1489 0x7422 0x0680 0x1005 64: 0x1602 0x1491 0x7422 0x0680 0x100D 65: 0x1702 0x1491 0xF422 0x0680 0x100D 66: 0x1602 0x1491 0xF422 0x0680 0x100D 67: 0x1602 0x1491 0xF422 0x0680 0x100D 68: 0x1202 0x1491 0xF42A 0x0600 0x100D 69: 0x1302 0x1490 0xF42A 0x0600 0x100D 70: 0x1202 0x1490 0xF42A 0x0600 0x100D 71: 0x1602 0x1490 0xF422 0x0680 0x100D 72: 0x1702 0x1491 0xF422 0x0680 0x100D 73: 0x1602 0x1491 0xF422 0x0680 0x100D 74: 0x1602 0x1489 0xF422 0x0680 0x1005 75: 0x1602 0x1489 0xF422 0x0680 0x1005 76: 0x9603 0x0489 0xF422 0x0680 0x1005 77: 0x1603 0x0489 0xF422 0x0680 0x1005 78: 0x1603 0x0491 0xF422 0x0680 0x100D 79: 0x9602 0x1491 0xF422 0x0680 0x100D 80: 0x1602 0x1491 0xF422 0x0680 0x100D 81: 0x1602 0x1491 0xF422 0x0680 0x100D 82: 0x1202 0x1491 0xF42A 0x0600 0x100D 83: 0xD200 0x1491 0xF42A 0x0600 0x100D 84: 0x5200 0x1491 0xF42A 0x0600 0x100D 85: 0x5600 0x1491 0xF422 0x0680 0x100D 86: 0x9602 0x1491 0xF422 0x0680 0x100D 87: 0x1602 0x1491 0xF422 0x0680 0x100D 88: 0x1602 0x1491 0xF022 0x0480 0x100F 89: 0x1602 0x1491 0xF022 0x0480 0x100D 90: 0x1602 0x1491 0xF082 0x0480 0x000D 91: 0x1602 0x1491 0xF002 0x0480 0x000D 92: 0x1606 0x1491 0xF002 0x0480 0x000D 93: 0x1606 0x3491 0xF002 0x0480 0x000D 94: 0x1E06 0x3491 0xF002 0x0480 0x000D 95: 0x1E06 0x3495 0xF002 0x0480 0x000D 96: 0x1E46 0x3495 0xF002 0x0480 0x000D 97: 0x1E46 0x3695 0xF002 0x0480 0x000D 98: 0x1E46 0x3695 0xF202 0x0480 0x000D 99: 0x1E46 0x3695 0xF202 0x0C80 0x000D 100: 0x1E46 0x3695 0xF202 0x8C80 0x000D 101: 0x1E46 0x3695 0xF202 0x8D80 0x000D 102: 0x1E46 0x3695 0xFA02 0x8D80 0x000D 103: 0x1E46 0x3695 0xFA02 0x8D82 0x000D 104: 0x1E46 0x3695 0xFA02 0xCD82 0x000D 105: 0x1E46 0x3695 0xFA02 0xCD86 0x000D 106: 0x1E46 0x3695 0xFA02 0xCD87 0x000D 107: 0x1E46 0x3695 0xFA02 0xCDC7 0x000D 108: 0x1E46 0x3695 0xFA02 0xCDE7 0x000D 109: 0x1E46 0x3697 0xFA02 0xCDE7 0x000D 110: 0x1E46 0x369D 0xFA0A 0xCD67 0x0005 111: 0x1E46 0x3E95 0xFA02 0xCDE7 0x000D 112: 0x1E46 0x369D 0xFA0A 0xCD67 0x0005 113: 0x1E46 0x36D5 0xFA02 0xCDE7 0x000D 114: 0x1E46 0x369D 0xFA0A 0xCD67 0x0005 115: 0x1E46 0x7695 0xFA02 0xCDE7 0x000D 116: 0x1E46 0x369D 0xFA0A 0xCD67 0x0005 117: 0x1E56 0x3695 0xFA02 0xCDE7 0x000D 118: 0x1E46 0x369D 0xFA0A 0xCD67 0x0005 119: 0x1E4E 0x3695 0xFA02 0xCDE7 0x000D 120: 0x1E46 0x369D 0xFA0A 0xCD67 0x0005 121: 0x3E46 0x369D 0xFA02 0xCDE7 0x0005 122: 0x1E46 0x369D 0xFA0A 0xCD67 0x0005 123: 0x1E46 0x369D 0xFA02 0xCDE7 0x0005 124: 0x1A46 0x369D 0xFA0A 0xCD67 0x0005 125: 0x1A46 0x36B5 0xFA0A 0xCD67 0x000D 126: 0x1A46 0x369D 0xFA0A 0xCD67 0x0005 127: 0x1A46 0x3695 0xFA0A 0xCD67 0x000D 128: 0x1A46 0x368D 0xFA0A 0xCD67 0x0005 129: 0x1A46 0x368D 0xEA0A 0xE9E7 0x000D 130: 0x1A46 0x368D 0xFA0A 0xCD67 0x0005 131: 0x1A46 0x368D 0xEA0A 0xD9E7 0x000D 132: 0x1A46 0x368D 0xFA0A 0xCD67 0x0005 133: 0x1A46 0x368D 0xEB0A 0xC9E7 0x000D 134: 0x1A46 0x368D 0xFA0A 0xCD67 0x0005 135: 0x1A46 0x368D 0xEA0A 0xC9E7 0x800D 136: 0x1A46 0x368D 0xFA0A 0xCD67 0x0005 137: 0x1A46 0x368D 0xEA0A 0xC9EF 0x000D 138: 0x1A46 0x368D 0xFA0A 0xCD67 0x0005 139: 0x1A46 0x368D 0xEA0A 0xC9E7 0x200D 140: 0x1A46 0x368D 0xFA0A 0xCD67 0x0005 141: 0x1A46 0x368D 0xFA0A 0xC977 0x000D 142: 0x1A46 0x368D 0xFA0A 0xCD67 0x0005 143: 0x1202 0x1489 0xF42A 0x0600 0x1005 144: 0x1202 0x1489 0xB42A 0x0600 0x1005 145: 0x1202 0x1489 0xB44A 0x0600 0x1005 146: 0x1202 0x1489 0xB40A 0x0600 0x1005 147: 0x1202 0x1489 0xB40A 0x0600 0x0004 148: 0x1202 0x1489 0xB40A 0x0600 0x1005 149: 0x1202 0x1489 0xB40A 0x0600 0x1005 150: 0x1202 0x1489 0xB44A 0x0600 0x0005 151: 0x1202 0x1489 0xB40A 0x0600 0x0005 152: 0x1202 0x1489 0xB40A 0x0600 0x1004 153: 0x1202 0x1489 0xB40A 0x0600 0x0005 154: 0x1202 0x1489 0xB40A 0x0600 0x0005 155: 0x1202 0x1489 0xB44A 0x0600 0x0005 156: 0x1202 0x1489 0xB40A 0x0600 0x0005 157: 0x1202 0x1489 0xF40A 0x0600 0x0005 158: 0x1202 0x1489 0xF46A 0x0600 0x0005 159: 0x1202 0x1489 0xF42A 0x0600 0x0005 160: 0x1202 0x1489 0xF42A 0x0600 0x0005 161: 0x1202 0x1489 0xF46A 0x0600 0x1005 162: 0x1202 0x1489 0xF42A 0x0600 0x1005 163: 0x1202 0x1489 0xF42A 0x0600 0x1005 164: 0x1202 0x1489 0xF46A 0x0600 0x1005 165: 0x1202 0x1489 0xF42A 0x0600 0x1005 166: 0x1202 0x1489 0xB42A 0x0600 0x1005 167: 0x1202 0x1489 0xB44A 0x0600 0x1005 168: 0x1202 0x1489 0xB40A 0x0600 0x1005 169: 0x1202 0x1489 0xF40A 0x0600 0x1005 170: 0x1202 0x1489 0xF46A 0x0600 0x0005 171: 0x1202 0x1489 0xF42A 0x0600 0x0005 172: 0x1202 0x1489 0xB42A 0x0600 0x0005 173: 0x1202 0x1489 0xB44A 0x0600 0x1005 174: 0x1202 0x1489 0xB40A 0x0600 0x1005 175: 0x1202 0x1489 0xF40A 0x0600 0x1005 176: 0x1202 0x1489 0xF46A 0x0600 0x0005 177: 0x1202 0x1489 0xF42A 0x0600 0x0005 178: 0x1202 0x1489 0xF42A 0x0600 0x0005 179: 0x1202 0x1489 0xF46A 0x0600 0x1005 180: 0x1202 0x1489 0xF42A 0x0600 0x1005 181: 0x1202 0x1489 0xF42A 0x0600 0x1005 PINs used (in edge connector order) (G=ground,P=power) SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBB LETTER ABCDEFHJKLMNPRSTUVABCDEFHJKLMNPRSTUVABCDEFHJKLMNPRSTUVABCDEFHJKLMNPRSTUV SIDE 111111111111111111222222222222222222111111111111111111222222222222222222 USAGE IOIOIIOIIIIOIOIGOIPIGIIIOOOIIOIIIOIOIOIOIIIIIIIOOIIGIOPOGOIIIIIIIIIOIIOO UUT has 44 inputs UUT has 22 outputs contains 66 pins/columns 0 pins are not used contains 181 'test steps' M222 PCB REV B SCHEMATIC REV A LINC TAPE REGISTERS TERMINOLOGY- SIGNALS REFER TO PDP12 MAINT VOL4 M222 SCHEMATIC. BUT... DEC USES AND-NOR GATES TO ROUTE THE ADDER A AND B INPUTS, SO... DEC RENAMED THE ADDER TO NEGATIVE LOGIC TERMS (I.E. A-N + B-N + C-N -> SUM-N, C1-N). (NOT THE 7482 DATASHEET NAMES OF A + B + C -> SUM, C1). SO, WITH ALL 'AND ENABLES' LOW, THE AND-NOR OUTPUTS = HIGH. WITH C-L HIGH, THE ADDER OUTPUT IS SUM-N=1, C1-N=1; THE INVERTED ADDER OUTPUT IS LOW (TAPE BUS). AND THERE IS NO CARRY (C1-N IS HI). THE TWO ADDERS, TWO REGISTER BITS, ETC ARE LABELED BIT 2 (EVEN, MSB) AND BIT 3 (ODD, LSB). THE ADDERS ARE REFERRED TO AS 'ADDER2' (MSB) AND 'ADDER3' (LSB). POWER PINS: AA2 +5V AT1 GROUND AC2 GROUND BA2 +5V BT1 GROUND BC2 GROUND (ALL PINS ARE USED). PINS Main menu Thu Aug 20 18:41:20 2015 test file is: tests\m222.new delay is: 0 trigger is: 1 1 read test file 2 set test delay 3 set test trigger 4 run test 5 output loading test 8 diags 9 exit UUT power is okay Thu Aug 20 18:41:22 2015 space single step O run once (one test, all steps) F run, stop on fail G go (run tests N run, stop on fail, no print S scope (run, no print) C toggle comment printout + increase speed (less delay) - decrease speed (more delay)(slower) Q quit test step 1 100000000000000000000000000000000001111100010011011010100110110111 step 2 100000000000000000000000000000000001111100100011011010100110110111 step 3 100000000000000000000000000000000001111100000011011010100110110111 step 4 100000000000000000000000000000000001111100000100011010100110110111 step 5 100000000000000000000000000000000001111100000000011010100110110111 step 6 100000000000000000000000000000000001111100000000100010100110110111 step 7 100000000000000000000000000000000001111100000000000010100110110111 step 8 100000000000000000000000000000000001111100000000000101010110110111 step 9 100000000000000000000000000000000001111100000000000001010110110111 step 10 100000000000000000000000000000000001111100000000000001011000110111 step 11 100000000000000000000000000000000001111100000000000001010000110111 step 12 100000000000000000000000000000000001111100000000000001010001110001 step 13 100000000000000000000000000000000001111100000000000001010000110001 step 14 100000000000000000000000000000000001111100000000000001010000110001 step 15 100000000000010000000000000000000000111101000000000001010000110001 step 16 100000000000010010000000000000000000110111000000000001010000110001 step 17 100000000000010010000000000000000000110111111000000001010000110001 step 18 100000000000010010000000000000000000110111011000000001010000110001 step 19 100000000000010010000000000000000000110111011111000001010000110001 step 20 100000000000010010000000000000000000110111011011000001010000110001 step 21 100000000000010010000000000000000000110111011011111001010000110001 step 22 100000000000010010000000000000000000110111011011011001010000110001 step 23 100000000000010010000000000000000000110111011011011110100000110001 step 24 100000000000010010000000000000000000110111011011011010100000110001 step 25 100000000000010010000000000000000000110111011011011010101110110001 step 26 100000000000010010000000000000000000110111011011011010100110110001 step 27 100000000000010010000000000000000000110111011011011010100111110111 step 28 100000000000010010000000000000000000110111011011011010100110110111 step 29 100000000000000010000000000000000001110110011011011010100110110111 step 30 100000000000000000000000000000000001111100011011011010100110110111 step 31 100000000000000000000000000000000001111100011011011010100110110111 step 32 100000000000000000000000000000000001111100011011011010100110110111 step 33 100000000000010000000000000000000000111101011011011010100110110111 step 34 100000000000010000000000000000000000111101101011011010100110110111 step 35 100000000000010000000000000000000000111101001011011010100110110111 step 36 100000000000010010000000000000000000110111001011011010100110110111 step 37 100000000000010010000000000000000000110111111011011010100110110111 step 38 100000000000010010000000000000000000110111011011011010100110110111 step 39 100000000000010010000000000000000000110111011011011010100110110111 step 40 100000000000000010000000000000000001110110011011011010100110110111 step 41 100000000000000010000000000000000001110110110011011010100110110111 step 42 100000000000000010000000000000000001110110010011011010100110110111 step 43 100000000000010010000000000000000000110111010011011010100110110111 step 44 100000000000010010000000000000000000110111111011011010100110110111 step 45 100000000000010010000000000000000000110111011011011010100110110111 step 46 100000000000010000000000000000000000111101011011011010100110110111 step 47 100000000000010000000000000000000000111101011011011010100110110111 step 48 100000000000010000000000000000000000111101011101011010100110110111 step 49 100000000000010000000000000000000000111101011001011010100110110111 step 50 100000000000010010000000000000000000110111011001011010100110110111 step 51 100000000000010010000000000000000000110111011111011010100110110111 step 52 100000000000010010000000000000000000110111011011011010100110110111 step 53 100000000000010010000000000000000000110111011011011010100110110111 step 54 100000000000000010000000000000000001110110011011011010100110110111 step 55 100000000000000010000000000000000001110110011110011010100110110111 step 56 100000000000000010000000000000000001110110011010011010100110110111 step 57 100000000000010010000000000000000000110111011010011010100110110111 step 58 100000000000010010000000000000000000110111011111011010100110110111 step 59 100000000000010010000000000000000000110111011011011010100110110111 step 60 100000000000010000000000000000000000111101011011011010100110110111 step 61 100000000000010000000000000000000000111101011011011010100110110111 step 62 100000000000010000000000000000000000111101011011101010100110110111 step 63 100000000000010000000000000000000000111101011011001010100110110111 step 64 100000000000010010000000000000000000110111011011001010100110110111 step 65 100000000000010010000000000000000000110111011011111010100110110111 step 66 100000000000010010000000000000000000110111011011011010100110110111 step 67 100000000000010010000000000000000000110111011011011010100110110111 step 68 100000000000000010000000000000000001110110011011011010100110110111 step 69 100000000000000010000000000000000001110110011011110010100110110111 step 70 100000000000000010000000000000000001110110011011010010100110110111 step 71 100000000000010010000000000000000000110111011011010010100110110111 step 72 100000000000010010000000000000000000110111011011111010100110110111 step 73 100000000000010010000000000000000000110111011011011010100110110111 step 74 100000000000010000000000000000000000111101011011011010100110110111 step 75 100000000000010000000000000000000000111101011011011010100110110111 step 76 100000000000010000000000000000000000111101011011011101100110110111 step 77 100000000000010000000000000000000000111101011011011001100110110111 step 78 100000000000010010000000000000000000110111011011011001100110110111 step 79 100000000000010010000000000000000000110111011011011110100110110111 step 80 100000000000010010000000000000000000110111011011011010100110110111 step 81 100000000000010010000000000000000000110111011011011010100110110111 step 82 100000000000000010000000000000000001110110011011011010100110110111 step 83 100000000000000010000000000000000001110110011011011110010110110111 step 84 100000000000000010000000000000000001110110011011011010010110110111 step 85 100000000000010010000000000000000000110111011011011010010110110111 step 86 100000000000010010000000000000000000110111011011011110100110110111 step 87 100000000000010010000000000000000000110111011011011010100110110111 SLOT BAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBAABBAAAAAAAAAAAAAABBBBBABBBB LETTER ALPSLFMDEEMCBFRSPKLEMFHRSCJLJKUHPNMBBNNVVRKRHUTDJUKANJHBTPDFSVEVDU SIDE 121212122121212121111111112212122222112222111221112112212112212122 DIRECTION IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIOOOOOOOIOOIOOIOOIOOOOIOOIIIIOOO changed: 1 step 88 100000000000010010000000000000000000110111011011011010101110110111 fail ^^ space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C toggle comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit comment_flag is 1 space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C toggle comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT BAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBAABBAAAAAAAAAAAAAABBBBBABBBB LETTER ALPSLFMDEEMCBFRSPKLEMFHRSCJLJKUHPNMBBNNVVRKRHUTDJUKANJHBTPDFSVEVDU SIDE 121212122121212121111111112212122222112222111221112112212112212122 DIRECTION IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIOOOOOOOIOOIOOIOOIOOOOIOOIIIIOOO source: 0 changed: 0 step 89 100000000000010010000000000000000000110111011011011010100110110111 fail ^^ SLOT BAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBAABBAAAAAAAAAAAAAABBBBBABBBB LETTER ALPSLFMDEEMCBFRSPKLEMFHRSCJLJKUHPNMBBNNVVRKRHUTDJUKANJHBTPDFSVEVDU SIDE 121212122121212121111111112212122222112222111221112112212112212122 DIRECTION IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIOOOOOOOIOOIOOIOOIOOOOIOOIIIIOOO source: ; load RWB from TB (JAMS CLEAR AND PRESET) source: 1 00 changed: 1 step 90 100000000000010010000000000000000000110111011011011010100111110111 fail ^^ ^^ SLOT BAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBAABBAAAAAAAAAAAAAABBBBBABBBB LETTER ALPSLFMDEEMCBFRSPKLEMFHRSCJLJKUHPNMBBNNVVRKRHUTDJUKANJHBTPDFSVEVDU SIDE 121212122121212121111111112212122222112222111221112112212112212122 DIRECTION IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIOOOOOOOIOOIOOIOOIOOOOIOOIIIIOOO source: 0 changed: 0 step 91 100000000000010010000000000000000000110111011011011010100110110111 fail ^^ ^^ SLOT BAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBAABBAAAAAAAAAAAAAABBBBBABBBB LETTER ALPSLFMDEEMCBFRSPKLEMFHRSCJLJKUHPNMBBNNVVRKRHUTDJUKANJHBTPDFSVEVDU SIDE 121212122121212121111111112212122222112222111221112112212112212122 DIRECTION IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIOOOOOOOIOOIOOIOOIOOOOIOOIIIIOOO source: source: source: source: source: source: source: source: source: source: source: source: source: source: source: ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; source: ; source: ; test AND-NOR logic source: ; source: ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; source: source: ; (all registers are HIGH) source: ; set all pins HIGH except ENABLES source: source: ; set pin AF2 HIGH source: 1 changed: 1 step 92 100001000000010010000000000000000000110111011011011010100110110111 fail ^^ ^^ SLOT BAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBAABBAAAAAAAAAAAAAABBBBBABBBB LETTER ALPSLFMDEEMCBFRSPKLEMFHRSCJLJKUHPNMBBNNVVRKRHUTDJUKANJHBTPDFSVEVDU SIDE 121212122121212121111111112212122222112222111221112112212112212122 DIRECTION IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIOOOOOOOIOOIOOIOOIOOOOIOOIIIIOOO source: ; set pin AM1 HIGH source: 1 changed: 1 step 93 100001100000010010000000000000000000110111011011011010100110110111 fail ^^ ^^ SLOT BAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBAABBAAAAAAAAAAAAAABBBBBABBBB LETTER ALPSLFMDEEMCBFRSPKLEMFHRSCJLJKUHPNMBBNNVVRKRHUTDJUKANJHBTPDFSVEVDU SIDE 121212122121212121111111112212122222112222111221112112212112212122 DIRECTION IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIOOOOOOOIOOIOOIOOIOOOOIOOIIIIOOO source: ; set pin AE1 HIGH source: 1 changed: 1 step 94 100001100100010010000000000000000000110111011011011010100110110111 fail ^^ ^^ SLOT BAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBAABBAAAAAAAAAAAAAABBBBBABBBB LETTER ALPSLFMDEEMCBFRSPKLEMFHRSCJLJKUHPNMBBNNVVRKRHUTDJUKANJHBTPDFSVEVDU SIDE 121212122121212121111111112212122222112222111221112112212112212122 DIRECTION IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIOOOOOOOIOOIOOIOOIOOOOIOOIIIIOOO source: ; set pin AM2 HIGH source: 1 changed: 1 step 95 100001100110010010000000000000000000110111011011011010100110110111 fail ^^ ^^ SLOT BAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBAABBAAAAAAAAAAAAAABBBBBABBBB LETTER ALPSLFMDEEMCBFRSPKLEMFHRSCJLJKUHPNMBBNNVVRKRHUTDJUKANJHBTPDFSVEVDU SIDE 121212122121212121111111112212122222112222111221112112212112212122 DIRECTION IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIOOOOOOOIOOIOOIOOIOOOOIOOIIIIOOO source: ; set pin AB2 HIGH source: 1 changed: 1 step 96 100001100110110010000000000000000000110111011011011010100110110111 fail ^^ ^^ SLOT BAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBAABBAAAAAAAAAAAAAABBBBBABBBB LETTER ALPSLFMDEEMCBFRSPKLEMFHRSCJLJKUHPNMBBNNVVRKRHUTDJUKANJHBTPDFSVEVDU SIDE 121212122121212121111111112212122222112222111221112112212112212122 DIRECTION IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIOOOOOOOIOOIOOIOOIOOOOIOOIIIIOOO source: ; set pin AS1 HIGH source: 1 changed: 1 step 97 100001100110110110000000000000000000110111011011011010100110110111 fail ^^ ^^ SLOT BAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBAABBAAAAAAAAAAAAAABBBBBABBBB LETTER ALPSLFMDEEMCBFRSPKLEMFHRSCJLJKUHPNMBBNNVVRKRHUTDJUKANJHBTPDFSVEVDU SIDE 121212122121212121111111112212122222112222111221112112212112212122 DIRECTION IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIOOOOOOOIOOIOOIOOIOOOOIOOIIIIOOO source: ; set pin BE1 HIGH source: 1 changed: 1 step 98 100001100110110110010000000000000000110111011011011010100110110111 fail ^^ ^^ SLOT BAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBAABBAAAAAAAAAAAAAABBBBBABBBB LETTER ALPSLFMDEEMCBFRSPKLEMFHRSCJLJKUHPNMBBNNVVRKRHUTDJUKANJHBTPDFSVEVDU SIDE 121212122121212121111111112212122222112222111221112112212112212122 DIRECTION IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIOOOOOOOIOOIOOIOOIOOOOIOOIIIIOOO source: ; set pin BM1 HIGH source: 1 changed: 1 step 99 100001100110110110011000000000000000110111011011011010100110110111 fail ^^ ^^ SLOT BAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBAABBAAAAAAAAAAAAAABBBBBABBBB LETTER ALPSLFMDEEMCBFRSPKLEMFHRSCJLJKUHPNMBBNNVVRKRHUTDJUKANJHBTPDFSVEVDU SIDE 121212122121212121111111112212122222112222111221112112212112212122 DIRECTION IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIOOOOOOOIOOIOOIOOIOOOOIOOIIIIOOO source: ; set pin BH1 HIGH source: 1 changed: 1 step 100 100001100110110110011010000000000000110111011011011010100110110111 fail ^^ ^^ SLOT BAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBAABBAAAAAAAAAAAAAABBBBBABBBB LETTER ALPSLFMDEEMCBFRSPKLEMFHRSCJLJKUHPNMBBNNVVRKRHUTDJUKANJHBTPDFSVEVDU SIDE 121212122121212121111111112212122222112222111221112112212112212122 DIRECTION IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIOOOOOOOIOOIOOIOOIOOOOIOOIIIIOOO source: ; set pin BR1 HIGH source: 1 changed: 1 step 101 100001100110110110011011000000000000110111011011011010100110110111 fail ^^ ^^ SLOT BAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBAABBAAAAAAAAAAAAAABBBBBABBBB LETTER ALPSLFMDEEMCBFRSPKLEMFHRSCJLJKUHPNMBBNNVVRKRHUTDJUKANJHBTPDFSVEVDU SIDE 121212122121212121111111112212122222112222111221112112212112212122 DIRECTION IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIOOOOOOOIOOIOOIOOIOOOOIOOIIIIOOO source: ; set pin BC1 HIGH source: 1 changed: 1 step 102 100001100110110110011011010000000000110111011011011010100110110111 fail ^^ ^^ SLOT BAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBAABBAAAAAAAAAAAAAABBBBBABBBB LETTER ALPSLFMDEEMCBFRSPKLEMFHRSCJLJKUHPNMBBNNVVRKRHUTDJUKANJHBTPDFSVEVDU SIDE 121212122121212121111111112212122222112222111221112112212112212122 DIRECTION IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIOOOOOOOIOOIOOIOOIOOOOIOOIIIIOOO source: ; set pin BJ2 HIGH source: 1 changed: 1 step 103 100001100110110110011011011000000000110111011011011010100110110111 fail ^^ ^^ SLOT BAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBAABBAAAAAAAAAAAAAABBBBBABBBB LETTER ALPSLFMDEEMCBFRSPKLEMFHRSCJLJKUHPNMBBNNVVRKRHUTDJUKANJHBTPDFSVEVDU SIDE 121212122121212121111111112212122222112222111221112112212112212122 DIRECTION IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIOOOOOOOIOOIOOIOOIOOOOIOOIIIIOOO source: ; set pin BJ1 HIGH source: 1 changed: 1 step 104 100001100110110110011011011010000000110111011011011010100110110111 fail ^^ ^^ SLOT BAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBAABBAAAAAAAAAAAAAABBBBBABBBB LETTER ALPSLFMDEEMCBFRSPKLEMFHRSCJLJKUHPNMBBNNVVRKRHUTDJUKANJHBTPDFSVEVDU SIDE 121212122121212121111111112212122222112222111221112112212112212122 DIRECTION IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIOOOOOOOIOOIOOIOOIOOOOIOOIIIIOOO source: ; set pin BK2 HIGH source: 1 changed: 1 step 105 100001100110110110011011011011000000110111011011011010100110110111 fail ^^ ^^ SLOT BAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBAABBAAAAAAAAAAAAAABBBBBABBBB LETTER ALPSLFMDEEMCBFRSPKLEMFHRSCJLJKUHPNMBBNNVVRKRHUTDJUKANJHBTPDFSVEVDU SIDE 121212122121212121111111112212122222112222111221112112212112212122 DIRECTION IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIOOOOOOOIOOIOOIOOIOOOOIOOIIIIOOO source: ; set pin BH2 HIGH source: 1 changed: 1 step 106 100001100110110110011011011011010000110111011011011010100110110111 fail ^^ ^^ SLOT BAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBAABBAAAAAAAAAAAAAABBBBBABBBB LETTER ALPSLFMDEEMCBFRSPKLEMFHRSCJLJKUHPNMBBNNVVRKRHUTDJUKANJHBTPDFSVEVDU SIDE 121212122121212121111111112212122222112222111221112112212112212122 DIRECTION IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIOOOOOOOIOOIOOIOOIOOOOIOOIIIIOOO source: ; set pin BP2 HIGH source: 1 changed: 1 step 107 100001100110110110011011011011011000110111011011011010100110110111 fail ^^ ^^ SLOT BAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBAABBAAAAAAAAAAAAAABBBBBABBBB LETTER ALPSLFMDEEMCBFRSPKLEMFHRSCJLJKUHPNMBBNNVVRKRHUTDJUKANJHBTPDFSVEVDU SIDE 121212122121212121111111112212122222112222111221112112212112212122 DIRECTION IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIOOOOOOOIOOIOOIOOIOOOOIOOIIIIOOO source: ; set pin BN2 HIGH source: 1 changed: 1 step 108 100001100110110110011011011011011100110111011011011010100110110111 fail ^^ ^^ SLOT BAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBAABBAAAAAAAAAAAAAABBBBBABBBB LETTER ALPSLFMDEEMCBFRSPKLEMFHRSCJLJKUHPNMBBNNVVRKRHUTDJUKANJHBTPDFSVEVDU SIDE 121212122121212121111111112212122222112222111221112112212112212122 DIRECTION IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIOOOOOOOIOOIOOIOOIOOOOIOOIIIIOOO source: ; toggle each ENABLE source: source: ; set pin AL2 to clear pin BB2 and pin AN2 AND-NOR OUTPUTS and set TAPE BUS 2 OUTPUT and TAPE BUS 3 OUTPUT source: 1 0 0 11 changed: 1 step 109 110001100110110110011011011011011100110111011011011010100110110111 fail ^^ ^^ SLOT BAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBAABBAAAAAAAAAAAAAABBBBBABBBB LETTER ALPSLFMDEEMCBFRSPKLEMFHRSCJLJKUHPNMBBNNVVRKRHUTDJUKANJHBTPDFSVEVDU SIDE 121212122121212121111111112212122222112222111221112112212112212122 DIRECTION IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIOOOOOOOIOOIOOIOOIOOOOIOOIIIIOOO source: 0 1 1 00 changed: 0 step 110 100001100110110110011011011011011100110111011011011010100110110111 fail ^ ^ ^^ ^^ ^^ SLOT BAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBAABBAAAAAAAAAAAAAABBBBBABBBB LETTER ALPSLFMDEEMCBFRSPKLEMFHRSCJLJKUHPNMBBNNVVRKRHUTDJUKANJHBTPDFSVEVDU SIDE 121212122121212121111111112212122222112222111221112112212112212122 DIRECTION IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIOOOOOOOIOOIOOIOOIOOOOIOOIIIIOOO source: ; set pin AP1 to clear pin BB2 and pin AN2 AND-NOR OUTPUTS and set TAPE BUS 2 OUTPUT and TAPE BUS 3 OUTPUT source: 1 0 0 11 changed: 1 step 111 101001100110110110011011011011011100110111011011011010100110110111 fail ^^ ^^ SLOT BAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBAABBAAAAAAAAAAAAAABBBBBABBBB LETTER ALPSLFMDEEMCBFRSPKLEMFHRSCJLJKUHPNMBBNNVVRKRHUTDJUKANJHBTPDFSVEVDU SIDE 121212122121212121111111112212122222112222111221112112212112212122 DIRECTION IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIOOOOOOOIOOIOOIOOIOOOOIOOIIIIOOO source: 0 1 1 00 changed: 0 step 112 100001100110110110011011011011011100110111011011011010100110110111 fail ^ ^ ^^ ^^ ^^ SLOT BAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBAABBAAAAAAAAAAAAAABBBBBABBBB LETTER ALPSLFMDEEMCBFRSPKLEMFHRSCJLJKUHPNMBBNNVVRKRHUTDJUKANJHBTPDFSVEVDU SIDE 121212122121212121111111112212122222112222111221112112212112212122 DIRECTION IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIOOOOOOOIOOIOOIOOIOOOOIOOIIIIOOO source: ; set pin AS2 to clear pin BB2 and pin AN2 AND-NOR OUTPUTS and set TAPE BUS 2 OUTPUT and TAPE BUS 3 OUTPUT source: 1 0 0 11 changed: 1 step 113 100101100110110110011011011011011100110111011011011010100110110111 fail ^^ ^^ SLOT BAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBAABBAAAAAAAAAAAAAABBBBBABBBB LETTER ALPSLFMDEEMCBFRSPKLEMFHRSCJLJKUHPNMBBNNVVRKRHUTDJUKANJHBTPDFSVEVDU SIDE 121212122121212121111111112212122222112222111221112112212112212122 DIRECTION IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIOOOOOOOIOOIOOIOOIOOOOIOOIIIIOOO source: 0 1 1 00 changed: 0 step 114 100001100110110110011011011011011100110111011011011010100110110111 fail ^ ^ ^^ ^^ ^^ SLOT BAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBAABBAAAAAAAAAAAAAABBBBBABBBB LETTER ALPSLFMDEEMCBFRSPKLEMFHRSCJLJKUHPNMBBNNVVRKRHUTDJUKANJHBTPDFSVEVDU SIDE 121212122121212121111111112212122222112222111221112112212112212122 DIRECTION IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIOOOOOOOIOOIOOIOOIOOOOIOOIIIIOOO source: ; set pin AL1 to clear pin BB2 and pin AN2 AND-NOR OUTPUTS and set TAPE BUS 2 OUTPUT and TAPE BUS 3 OUTPUT source: 1 0 0 11 changed: 1 step 115 100011100110110110011011011011011100110111011011011010100110110111 fail ^^ ^^ SLOT BAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBAABBAAAAAAAAAAAAAABBBBBABBBB LETTER ALPSLFMDEEMCBFRSPKLEMFHRSCJLJKUHPNMBBNNVVRKRHUTDJUKANJHBTPDFSVEVDU SIDE 121212122121212121111111112212122222112222111221112112212112212122 DIRECTION IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIOOOOOOOIOOIOOIOOIOOOOIOOIIIIOOO source: 0 1 1 00 changed: 0 step 116 100001100110110110011011011011011100110111011011011010100110110111 fail ^ ^ ^^ ^^ ^^ SLOT BAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBAABBAAAAAAAAAAAAAABBBBBABBBB LETTER ALPSLFMDEEMCBFRSPKLEMFHRSCJLJKUHPNMBBNNVVRKRHUTDJUKANJHBTPDFSVEVDU SIDE 121212122121212121111111112212122222112222111221112112212112212122 DIRECTION IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIOOOOOOOIOOIOOIOOIOOOOIOOIIIIOOO source: ; set pin AL1 to clear pin BB2 and pin AN2 AND-NOR OUTPUTS and set TAPE BUS 2 OUTPUT and TAPE BUS 3 OUTPUT source: 1 0 0 11 changed: 1 step 117 100001110110110110011011011011011100110111011011011010100110110111 fail ^^ ^^ SLOT BAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBAABBAAAAAAAAAAAAAABBBBBABBBB LETTER ALPSLFMDEEMCBFRSPKLEMFHRSCJLJKUHPNMBBNNVVRKRHUTDJUKANJHBTPDFSVEVDU SIDE 121212122121212121111111112212122222112222111221112112212112212122 DIRECTION IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIOOOOOOOIOOIOOIOOIOOOOIOOIIIIOOO source: 0 1 1 00 changed: 0 step 118 100001100110110110011011011011011100110111011011011010100110110111 fail ^ ^ ^^ ^^ ^^ SLOT BAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBAABBAAAAAAAAAAAAAABBBBBABBBB LETTER ALPSLFMDEEMCBFRSPKLEMFHRSCJLJKUHPNMBBNNVVRKRHUTDJUKANJHBTPDFSVEVDU SIDE 121212122121212121111111112212122222112222111221112112212112212122 DIRECTION IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIOOOOOOOIOOIOOIOOIOOOOIOOIIIIOOO source: ; set pin AE2 to clear pin BB2 and pin AN2 AND-NOR OUTPUTS and set TAPE BUS 2 OUTPUT and TAPE BUS 3 OUTPUT source: 1 0 0 11 changed: 1 step 119 100001101110110110011011011011011100110111011011011010100110110111 fail ^^ ^^ SLOT BAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBAABBAAAAAAAAAAAAAABBBBBABBBB LETTER ALPSLFMDEEMCBFRSPKLEMFHRSCJLJKUHPNMBBNNVVRKRHUTDJUKANJHBTPDFSVEVDU SIDE 121212122121212121111111112212122222112222111221112112212112212122 DIRECTION IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIOOOOOOOIOOIOOIOOIOOOOIOOIIIIOOO source: 0 1 1 00 changed: 0 step 120 100001100110110110011011011011011100110111011011011010100110110111 fail ^ ^ ^^ ^^ ^^ SLOT BAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBAABBAAAAAAAAAAAAAABBBBBABBBB LETTER ALPSLFMDEEMCBFRSPKLEMFHRSCJLJKUHPNMBBNNVVRKRHUTDJUKANJHBTPDFSVEVDU SIDE 121212122121212121111111112212122222112222111221112112212112212122 DIRECTION IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIOOOOOOOIOOIOOIOOIOOOOIOOIIIIOOO source: ; set pin AC1 to clear pin BB2 and set TAPE BUS 3 OUTPUT source: 1 0 1 changed: 1 step 121 100001100111110110011011011011011100110111011011011010100110110111 fail ^ ^ ^^ ^^ SLOT BAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBAABBAAAAAAAAAAAAAABBBBBABBBB LETTER ALPSLFMDEEMCBFRSPKLEMFHRSCJLJKUHPNMBBNNVVRKRHUTDJUKANJHBTPDFSVEVDU SIDE 121212122121212121111111112212122222112222111221112112212112212122 DIRECTION IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIOOOOOOOIOOIOOIOOIOOOOIOOIIIIOOO source: 0 1 0 changed: 0 step 122 100001100110110110011011011011011100110111011011011010100110110111 fail ^ ^ ^^ ^^ ^^ SLOT BAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBAABBAAAAAAAAAAAAAABBBBBABBBB LETTER ALPSLFMDEEMCBFRSPKLEMFHRSCJLJKUHPNMBBNNVVRKRHUTDJUKANJHBTPDFSVEVDU SIDE 121212122121212121111111112212122222112222111221112112212112212122 DIRECTION IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIOOOOOOOIOOIOOIOOIOOOOIOOIIIIOOO source: ; set pin AF1 to clear pin BB2 and set TAPE BUS 3 OUTPUT source: 1 0 1 changed: step 123 100001100110110110011011011011011100110111011011011010100110110111 fail ^ ^ ^^ ^^ SLOT BAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBAABBAAAAAAAAAAAAAABBBBBABBBB LETTER ALPSLFMDEEMCBFRSPKLEMFHRSCJLJKUHPNMBBNNVVRKRHUTDJUKANJHBTPDFSVEVDU SIDE 121212122121212121111111112212122222112222111221112112212112212122 DIRECTION IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIOOOOOOOIOOIOOIOOIOOOOIOOIIIIOOO source: 0 1 0 changed: 0 1 0 step 124 100001100110100110011011011011011101110110011011011010100110110111 fail ^ ^ ^^ ^^ SLOT BAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBAABBAAAAAAAAAAAAAABBBBBABBBB LETTER ALPSLFMDEEMCBFRSPKLEMFHRSCJLJKUHPNMBBNNVVRKRHUTDJUKANJHBTPDFSVEVDU SIDE 121212122121212121111111112212122222112222111221112112212112212122 DIRECTION IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIOOOOOOOIOOIOOIOOIOOOOIOOIIIIOOO source: ; set pin AR2 to clear pin AN2 AND-NOR OUTPUTS and set TAPE BUS 2 OUTPUT source: 1 0 1 changed: 1 step 125 100001100110101110011011011011011101110110011011011010100110110111 fail ^^ ^^ SLOT BAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBAABBAAAAAAAAAAAAAABBBBBABBBB LETTER ALPSLFMDEEMCBFRSPKLEMFHRSCJLJKUHPNMBBNNVVRKRHUTDJUKANJHBTPDFSVEVDU SIDE 121212122121212121111111112212122222112222111221112112212112212122 DIRECTION IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIOOOOOOOIOOIOOIOOIOOOOIOOIIIIOOO source: 0 1 0 changed: 0 step 126 100001100110100110011011011011011101110110011011011010100110110111 fail ^ ^ ^^ ^^ SLOT BAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBAABBAAAAAAAAAAAAAABBBBBABBBB LETTER ALPSLFMDEEMCBFRSPKLEMFHRSCJLJKUHPNMBBNNVVRKRHUTDJUKANJHBTPDFSVEVDU SIDE 121212122121212121111111112212122222112222111221112112212112212122 DIRECTION IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIOOOOOOOIOOIOOIOOIOOOOIOOIIIIOOO source: ; set pin AP2 to clear pin AN2 AND-NOR OUTPUTS and set TAPE BUS 2 OUTPUT source: 1 0 1 changed: step 127 100001100110100110011011011011011101110110011011011010100110110111 fail ^^ ^^ SLOT BAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBAABBAAAAAAAAAAAAAABBBBBABBBB LETTER ALPSLFMDEEMCBFRSPKLEMFHRSCJLJKUHPNMBBNNVVRKRHUTDJUKANJHBTPDFSVEVDU SIDE 121212122121212121111111112212122222112222111221112112212112212122 DIRECTION IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIOOOOOOOIOOIOOIOOIOOOOIOOIIIIOOO source: 0 1 0 changed: 0 1 0 step 128 100001100110100100011011011011011101111100011011011010100110110111 fail ^^ ^^ SLOT BAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBAABBAAAAAAAAAAAAAABBBBBABBBB LETTER ALPSLFMDEEMCBFRSPKLEMFHRSCJLJKUHPNMBBNNVVRKRHUTDJUKANJHBTPDFSVEVDU SIDE 121212122121212121111111112212122222112222111221112112212112212122 DIRECTION IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIOOOOOOOIOOIOOIOOIOOOOIOOIIIIOOO source: source: ; set pin BK1 to clear pin BB1 and pin BN1 AND-NOR OUTPUTS and set TAPE BUS 2 OUTPUT and TAPE BUS 3 OUTPUT source: 1 00 11 changed: 1 00 11 step 129 100001100110100101011011011011011101001111011011011010100110110111 fail ^^ ^^ SLOT BAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBAABBAAAAAAAAAAAAAABBBBBABBBB LETTER ALPSLFMDEEMCBFRSPKLEMFHRSCJLJKUHPNMBBNNVVRKRHUTDJUKANJHBTPDFSVEVDU SIDE 121212122121212121111111112212122222112222111221112112212112212122 DIRECTION IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIOOOOOOOIOOIOOIOOIOOOOIOOIIIIOOO source: 0 11 00 changed: 0 11 00 step 130 100001100110100100011011011011011101111100011011011010100110110111 fail ^^ ^^ SLOT BAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBAABBAAAAAAAAAAAAAABBBBBABBBB LETTER ALPSLFMDEEMCBFRSPKLEMFHRSCJLJKUHPNMBBNNVVRKRHUTDJUKANJHBTPDFSVEVDU SIDE 121212122121212121111111112212122222112222111221112112212112212122 DIRECTION IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIOOOOOOOIOOIOOIOOIOOOOIOOIIIIOOO source: ; set pin BL1 to clear pin BB1 and pin BN1 AND-NOR OUTPUTS and set TAPE BUS 2 OUTPUT and TAPE BUS 3 OUTPUT source: 1 00 11 changed: 1 00 11 step 131 100001100110100100111011011011011101001111011011011010100110110111 fail ^^ ^^ SLOT BAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBAABBAAAAAAAAAAAAAABBBBBABBBB LETTER ALPSLFMDEEMCBFRSPKLEMFHRSCJLJKUHPNMBBNNVVRKRHUTDJUKANJHBTPDFSVEVDU SIDE 121212122121212121111111112212122222112222111221112112212112212122 DIRECTION IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIOOOOOOOIOOIOOIOOIOOOOIOOIIIIOOO source: 0 11 00 changed: 0 11 00 step 132 100001100110100100011011011011011101111100011011011010100110110111 fail ^^ ^^ SLOT BAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBAABBAAAAAAAAAAAAAABBBBBABBBB LETTER ALPSLFMDEEMCBFRSPKLEMFHRSCJLJKUHPNMBBNNVVRKRHUTDJUKANJHBTPDFSVEVDU SIDE 121212122121212121111111112212122222112222111221112112212112212122 DIRECTION IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIOOOOOOOIOOIOOIOOIOOOOIOOIIIIOOO source: ; set pin BF1 to clear pin BB1 and pin BN1 AND-NOR OUTPUTS and set TAPE BUS 2 OUTPUT and TAPE BUS 3 OUTPUT source: 1 00 11 changed: 1 00 11 step 133 100001100110100100011111011011011101001111011011011010100110110111 fail ^^ ^^ SLOT BAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBAABBAAAAAAAAAAAAAABBBBBABBBB LETTER ALPSLFMDEEMCBFRSPKLEMFHRSCJLJKUHPNMBBNNVVRKRHUTDJUKANJHBTPDFSVEVDU SIDE 121212122121212121111111112212122222112222111221112112212112212122 DIRECTION IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIOOOOOOOIOOIOOIOOIOOOOIOOIIIIOOO source: 0 11 00 changed: 0 11 00 step 134 100001100110100100011011011011011101111100011011011010100110110111 fail ^^ ^^ SLOT BAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBAABBAAAAAAAAAAAAAABBBBBABBBB LETTER ALPSLFMDEEMCBFRSPKLEMFHRSCJLJKUHPNMBBNNVVRKRHUTDJUKANJHBTPDFSVEVDU SIDE 121212122121212121111111112212122222112222111221112112212112212122 DIRECTION IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIOOOOOOOIOOIOOIOOIOOOOIOOIIIIOOO source: ; set pin BS1 to clear pin BB1 and pin BN1 AND-NOR OUTPUTS and set TAPE BUS 2 OUTPUT and TAPE BUS 3 OUTPUT source: 1 00 11 changed: 1 00 11 step 135 100001100110100100011011111011011101001111011011011010100110110111 fail ^^ ^^ SLOT BAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBAABBAAAAAAAAAAAAAABBBBBABBBB LETTER ALPSLFMDEEMCBFRSPKLEMFHRSCJLJKUHPNMBBNNVVRKRHUTDJUKANJHBTPDFSVEVDU SIDE 121212122121212121111111112212122222112222111221112112212112212122 DIRECTION IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIOOOOOOOIOOIOOIOOIOOOOIOOIIIIOOO source: 0 11 00 changed: 0 11 00 step 136 100001100110100100011011011011011101111100011011011010100110110111 fail ^^ ^^ SLOT BAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBAABBAAAAAAAAAAAAAABBBBBABBBB LETTER ALPSLFMDEEMCBFRSPKLEMFHRSCJLJKUHPNMBBNNVVRKRHUTDJUKANJHBTPDFSVEVDU SIDE 121212122121212121111111112212122222112222111221112112212112212122 DIRECTION IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIOOOOOOOIOOIOOIOOIOOOOIOOIIIIOOO source: ; set pin BL2 to clear pin BB1 and pin BN1 AND-NOR OUTPUTS and set TAPE BUS 2 OUTPUT and TAPE BUS 3 OUTPUT source: 1 00 11 changed: 1 00 11 step 137 100001100110100100011011011111011101001111011011011010100110110111 fail ^^ ^^ SLOT BAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBAABBAAAAAAAAAAAAAABBBBBABBBB LETTER ALPSLFMDEEMCBFRSPKLEMFHRSCJLJKUHPNMBBNNVVRKRHUTDJUKANJHBTPDFSVEVDU SIDE 121212122121212121111111112212122222112222111221112112212112212122 DIRECTION IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIOOOOOOOIOOIOOIOOIOOOOIOOIIIIOOO source: 0 11 00 changed: 0 11 00 step 138 100001100110100100011011011011011101111100011011011010100110110111 fail ^^ ^^ SLOT BAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBAABBAAAAAAAAAAAAAABBBBBABBBB LETTER ALPSLFMDEEMCBFRSPKLEMFHRSCJLJKUHPNMBBNNVVRKRHUTDJUKANJHBTPDFSVEVDU SIDE 121212122121212121111111112212122222112222111221112112212112212122 DIRECTION IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIOOOOOOOIOOIOOIOOIOOOOIOOIIIIOOO source: ; set pin BU1 to clear pin BB1 and pin BN1 AND-NOR OUTPUTS and set TAPE BUS 2 OUTPUT and TAPE BUS 3 OUTPUT source: 1 00 11 changed: 1 00 11 step 139 100001100110100100011011011011111101001111011011011010100110110111 fail ^^ ^^ SLOT BAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBAABBAAAAAAAAAAAAAABBBBBABBBB LETTER ALPSLFMDEEMCBFRSPKLEMFHRSCJLJKUHPNMBBNNVVRKRHUTDJUKANJHBTPDFSVEVDU SIDE 121212122121212121111111112212122222112222111221112112212112212122 DIRECTION IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIOOOOOOOIOOIOOIOOIOOOOIOOIIIIOOO source: 0 11 00 changed: 0 11 00 step 140 100001100110100100011011011011011101111100011011011010100110110111 fail ^^ ^^ SLOT BAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBAABBAAAAAAAAAAAAAABBBBBABBBB LETTER ALPSLFMDEEMCBFRSPKLEMFHRSCJLJKUHPNMBBNNVVRKRHUTDJUKANJHBTPDFSVEVDU SIDE 121212122121212121111111112212122222112222111221112112212112212122 DIRECTION IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIOOOOOOOIOOIOOIOOIOOOOIOOIIIIOOO source: ; set pin BM2 to clear pin BB1 and TAPE BUS 3 OUTPUT source: 1 0 1 changed: 1 0 1 step 141 100001100110100100011011011011011111101110011011011010100110110111 fail ^^ ^^ SLOT BAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBAABBAAAAAAAAAAAAAABBBBBABBBB LETTER ALPSLFMDEEMCBFRSPKLEMFHRSCJLJKUHPNMBBNNVVRKRHUTDJUKANJHBTPDFSVEVDU SIDE 121212122121212121111111112212122222112222111221112112212112212122 DIRECTION IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIOOOOOOOIOOIOOIOOIOOOOIOOIIIIOOO source: 0 1 0 changed: 0 1 0 step 142 100001100110100100011011011011011101111100011011011010100110110111 fail ^^ ^^ source: ; no change source: 100000000000000000000000000000000001111100011011011010100110110111 changed: 00 00 0 0 00 00 00 00 000 step 143 100000000000000000000000000000000001111100011011011010100110110111 source: source: ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; source: ; test shifting the RWB source: ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; source: source: ; shift in 0, expect 10 source: 0 changed: 0 step 144 100000000000000000000000000000000001111100011011011010100110100111 source: 110 changed: 1 0 step 145 100000000000000000000000000000000001111100011011011010100110101101 source: 0 changed: 0 step 146 100000000000000000000000000000000001111100011011011010100110100101 source: ; toggle phase should toggle RWB 2 source: 0 0 changed: 0 0 step 147 100000000000000000000000000000000001111100011011011010100110000001 source: 1 1 changed: 1 1 step 148 100000000000000000000000000000000001111100011011011010100110100101 source: source: ; shift in 0, expect 00 source: 0 changed: step 149 100000000000000000000000000000000001111100011011011010100110100101 source: 100 changed: 10 step 150 100000000000000000000000000000000001111100011011011010100110101001 source: 0 changed: 0 step 151 100000000000000000000000000000000001111100011011011010100110100001 source: ; toggle phase should toggle RWB 2 source: 0 1 changed: 0 1 step 152 100000000000000000000000000000000001111100011011011010100110000101 source: 1 0 changed: 1 0 step 153 100000000000000000000000000000000001111100011011011010100110100001 source: source: ; shift in 0, expect 00 source: 0 changed: step 154 100000000000000000000000000000000001111100011011011010100110100001 source: 100 changed: 1 step 155 100000000000000000000000000000000001111100011011011010100110101001 source: 0 changed: 0 step 156 100000000000000000000000000000000001111100011011011010100110100001 source: ; shift in 1, expect 01 source: 1 changed: 1 step 157 100000000000000000000000000000000001111100011011011010100110110001 source: 101 changed: 1 1 step 158 100000000000000000000000000000000001111100011011011010100110111011 source: 0 changed: 0 step 159 100000000000000000000000000000000001111100011011011010100110110011 source: ; shift in 1, expect 11 source: 1 changed: step 160 100000000000000000000000000000000001111100011011011010100110110011 source: 111 changed: 11 step 161 100000000000000000000000000000000001111100011011011010100110111111 source: 0 changed: 0 step 162 100000000000000000000000000000000001111100011011011010100110110111 source: ; shift in 1, expect 11 source: 1 changed: step 163 100000000000000000000000000000000001111100011011011010100110110111 source: 111 changed: 1 step 164 100000000000000000000000000000000001111100011011011010100110111111 source: 0 changed: 0 step 165 100000000000000000000000000000000001111100011011011010100110110111 source: ; shift in 0, expect 10 source: 0 changed: 0 step 166 100000000000000000000000000000000001111100011011011010100110100111 source: 110 changed: 1 0 step 167 100000000000000000000000000000000001111100011011011010100110101101 source: 0 changed: 0 step 168 100000000000000000000000000000000001111100011011011010100110100101 source: ; shift in 1, expect 01 source: 1 changed: 1 step 169 100000000000000000000000000000000001111100011011011010100110110101 source: 101 changed: 101 step 170 100000000000000000000000000000000001111100011011011010100110111011 source: 0 changed: 0 step 171 100000000000000000000000000000000001111100011011011010100110110011 source: ; shift in 0, expect 10 source: 0 changed: 0 step 172 100000000000000000000000000000000001111100011011011010100110100011 source: 110 changed: 110 step 173 100000000000000000000000000000000001111100011011011010100110101101 source: 0 changed: 0 step 174 100000000000000000000000000000000001111100011011011010100110100101 source: ; shift in 1, expect 01 source: 1 changed: 1 step 175 100000000000000000000000000000000001111100011011011010100110110101 source: 101 changed: 101 step 176 100000000000000000000000000000000001111100011011011010100110111011 source: 0 changed: 0 step 177 100000000000000000000000000000000001111100011011011010100110110011 source: ; shift in 1, expect 11 source: 1 changed: step 178 100000000000000000000000000000000001111100011011011010100110110011 source: 111 changed: 11 step 179 100000000000000000000000000000000001111100011011011010100110111111 source: 0 changed: 0 step 180 100000000000000000000000000000000001111100011011011010100110110111 source: ; no change source: 100000000000000000000000000000000001111100011011011010100110110111 changed: step 181 100000000000000000000000000000000001111100011011011010100110110111 test 1: *** FAIL *************************** 55 steps failed SLOT BAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBAABBAAAAAAAAAAAAAABBBBBABBBB LETTER ALPSLFMDEEMCBFRSPKLEMFHRSCJLJKUHPNMBBNNVVRKRHUTDJUKANJHBTPDFSVEVDU SIDE 121212122121212121111111112212122222112222111221112112212112212122 DIRECTION IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIOOOOOOOIOOIOOIOOIOOOOIOOIIIIOOO this fail O O OO OO OO all fails O O OO OO OO was hi 111111111111111111111111111111111111111111111111111111111111111111 rising ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ ^^^^^^^^^^^^^^^^^^^^^^^^^ falling vvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvv vvvvvvvvvvvvvvvvvvvvvvvvv was lo 00000000000000000000000000000000000000 0000000000000000000000000 total fails 1, total passes 0 space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C toggle comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit source: ; all registers are unknown source: ; turn on C0, PHASE source: ; with no ENABLES, BUS2,BUS3 is 11, C2 is 1 source: 1000000000000000000000000000000000011111000XX0XX0XX0XXXX0XX0110XX1 changed: step 1 100000000000000000000000000000000001111100011011011010100110110111 source: source: ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; source: ; source: ; set all registers LOW source: ; source: ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; source: source: ; load TMA SETUP from tape bus (00) source: 100 changed: 100 step 2 100000000000000000000000000000000001111100100011011010100110110111 source: 0 changed: 0 step 3 100000000000000000000000000000000001111100000011011010100110110111 source: ; load TMA from tape bus (00) source: 100 changed: 100 step 4 100000000000000000000000000000000001111100000100011010100110110111 source: 0 changed: 0 step 5 100000000000000000000000000000000001111100000000011010100110110111 source: ; load TBN from tape bus (00) source: 100 changed: 100 step 6 100000000000000000000000000000000001111100000000100010100110110111 source: 0 changed: 0 step 7 100000000000000000000000000000000001111100000000000010100110110111 source: ; load TAC from tape bus (00) source: 10101 changed: 10101 step 8 100000000000000000000000000000000001111100000000000101010110110111 source: 0 changed: 0 step 9 100000000000000000000000000000000001111100000000000001010110110111 source: ; load TB from tape bus (00) source: 100 changed: 100 step 10 100000000000000000000000000000000001111100000000000001011000110111 source: 0 changed: 0 step 11 100000000000000000000000000000000001111100000000000001010000110111 source: ; load RWB from TB (JAMS CLEAR AND PRESET) source: 1 00 changed: 1 00 step 12 100000000000000000000000000000000001111100000000000001010001110001 source: 0 changed: 0 step 13 100000000000000000000000000000000001111100000000000001010000110001 source: ; (no change) source: 100000000000000000000000000000000001111100000000000001010000110001 changed: step 14 100000000000000000000000000000000001111100000000000001010000110001 source: source: source: ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; source: ; source: ; set all registers HIGH source: ; source: ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; source: source: ; set pin AF1 which clears pin BB2 and sets pin BR2 TAPE BUS 3 OUTPUT source: 1 0 1 changed: 1 0 1 step 15 100000000000010000000000000000000000111101000000000001010000110001 source: ; set pin AP2 which clears pin AN2 and sets pin BV2 TAPE BUS 2 OUTPUT source: 1 0 1 changed: 1 0 1 step 16 100000000000010010000000000000000000110111000000000001010000110001 source: source: source: ; load TMA SETUP from tape bus (11) source: 111 changed: 111 step 17 100000000000010010000000000000000000110111111000000001010000110001 source: 0 changed: 0 step 18 100000000000010010000000000000000000110111011000000001010000110001 source: ; load TMA from tape bus (11) source: 111 changed: 111 step 19 100000000000010010000000000000000000110111011111000001010000110001 source: 0 changed: 0 step 20 100000000000010010000000000000000000110111011011000001010000110001 source: ; load TBN from tape bus (11) source: 111 changed: 111 step 21 100000000000010010000000000000000000110111011011111001010000110001 source: 0 changed: 0 step 22 100000000000010010000000000000000000110111011011011001010000110001 source: ; load TAC from tape bus (11) source: 11010 changed: 11010 step 23 100000000000010010000000000000000000110111011011011110100000110001 source: 0 changed: 0 step 24 100000000000010010000000000000000000110111011011011010100000110001 source: ; load TB from tape bus (11) source: 111 changed: 111 step 25 100000000000010010000000000000000000110111011011011010101110110001 source: 0 changed: 0 step 26 100000000000010010000000000000000000110111011011011010100110110001 source: ; load RWB from TB (JAMS CLEAR AND PRESET) source: 1 11 changed: 1 11 step 27 100000000000010010000000000000000000110111011011011010100111110111 source: 0 changed: 0 step 28 100000000000010010000000000000000000110111011011011010100110110111 source: ; clear pin AF1 (AND with itself) to set pin BB2 (AND-NOR output) and clear pin BR2 TAPE BUS 3 OUTPUT source: 0 1 0 changed: 0 1 0 step 29 100000000000000010000000000000000001110110011011011010100110110111 source: ; clear pin AP2 (AND with itself) to set pin AN2 (AND-NOR output) and clear pin BV2 TAPE BUS 2 OUTPUT source: 0 1 0 changed: 0 1 0 step 30 100000000000000000000000000000000001111100011011011010100110110111 source: ; (no change) source: 100000000000000000000000000000000001111100011011011010100110110111 changed: step 31 100000000000000000000000000000000001111100011011011010100110110111 source: source: ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; source: ; source: ; will all registers high, walk a 0 source: ; source: ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; source: source: source: ; walk a 0, TMA SETUP 2 source: source: source: ; clear pin AP2 which sets pin AN2 and clears pin BV2 TAPE BUS 2 OUTPUT source: 0 1 0 changed: step 32 100000000000000000000000000000000001111100011011011010100110110111 source: ; set pin AF1 which clears pin BB2 and sets pin BR2 TAPE BUS 3 OUTPUT source: 1 0 1 changed: 1 0 1 step 33 100000000000010000000000000000000000111101011011011010100110110111 source: ; load TMA SETUP from tape bus (01) source: 101 changed: 10 step 34 100000000000010000000000000000000000111101101011011010100110110111 source: 0 changed: 0 step 35 100000000000010000000000000000000000111101001011011010100110110111 source: ; restore TMA SETUP 2 source: ; set pin AP2 which clears pin AN2 and sets pin BV2 TAPE BUS 2 OUTPUT source: 1 0 1 changed: 1 0 1 step 36 100000000000010010000000000000000000110111001011011010100110110111 source: ; load TMA SETUP from tape bus (11) source: 111 changed: 11 step 37 100000000000010010000000000000000000110111111011011010100110110111 source: 0 changed: 0 step 38 100000000000010010000000000000000000110111011011011010100110110111 source: source: source: ; walk a 0, TMA SETUP 3 source: source: source: ; set pin AP2 which clears pin AN2 and sets pin BV2 TAPE BUS 2 OUTPUT source: 1 0 1 changed: step 39 100000000000010010000000000000000000110111011011011010100110110111 source: ; clear pin AF1 which sets pin BB2 and clears pin BR2 TAPE BUS 3 OUTPUT source: 0 1 0 changed: 0 1 0 step 40 100000000000000010000000000000000001110110011011011010100110110111 source: ; load TMA SETUP from tape bus (10) source: 110 changed: 1 0 step 41 100000000000000010000000000000000001110110110011011010100110110111 source: 0 changed: 0 step 42 100000000000000010000000000000000001110110010011011010100110110111 source: ; restore TMA SETUP 3 source: ; set pin AF1 which clears pin BB2 and sets pin BR2 TAPE BUS 3 OUTPUT source: 1 0 1 changed: 1 0 1 step 43 100000000000010010000000000000000000110111010011011010100110110111 source: ; load TMA SETUP from tape bus (11) source: 111 changed: 1 1 step 44 100000000000010010000000000000000000110111111011011010100110110111 source: 0 changed: 0 step 45 100000000000010010000000000000000000110111011011011010100110110111 source: source: source: ; walk a 0, TMA 2 source: source: source: ; clear pin AP2 which sets pin AN2 and clears pin BV2 TAPE BUS 2 OUTPUT source: 0 1 0 changed: 0 1 0 step 46 100000000000010000000000000000000000111101011011011010100110110111 source: ; set pin AF1 which clears pin BB2 and sets pin BR2 TAPE BUS 3 OUTPUT source: 1 0 1 changed: step 47 100000000000010000000000000000000000111101011011011010100110110111 source: ; load TMA from tape bus (01) source: 101 changed: 10 step 48 100000000000010000000000000000000000111101011101011010100110110111 source: 0 changed: 0 step 49 100000000000010000000000000000000000111101011001011010100110110111 source: ; restore TMA 2 source: ; set pin AP2 which clears pin AN2 and sets pin BV2 TAPE BUS 2 OUTPUT source: 1 0 1 changed: 1 0 1 step 50 100000000000010010000000000000000000110111011001011010100110110111 source: ; load TMA from tape bus (11) source: 111 changed: 11 step 51 100000000000010010000000000000000000110111011111011010100110110111 source: 0 changed: 0 step 52 100000000000010010000000000000000000110111011011011010100110110111 source: source: source: ; walk a 0, TMA 3 source: source: source: ; set pin AP2 which clears pin AN2 and sets pin BV2 TAPE BUS 2 OUTPUT source: 1 0 1 changed: step 53 100000000000010010000000000000000000110111011011011010100110110111 source: ; clear pin AF1 which sets pin BB2 and clears pin BR2 TAPE BUS 3 OUTPUT source: 0 1 0 changed: 0 1 0 step 54 100000000000000010000000000000000001110110011011011010100110110111 source: ; load TMA from tape bus (10) source: 110 changed: 1 0 step 55 100000000000000010000000000000000001110110011110011010100110110111 source: 0 changed: 0 step 56 100000000000000010000000000000000001110110011010011010100110110111 source: ; restore TMA 3 source: ; set pin AF1 which clears pin BB2 and sets pin BR2 TAPE BUS 3 OUTPUT source: 1 0 1 changed: 1 0 1 step 57 100000000000010010000000000000000000110111011010011010100110110111 source: ; load TMA from tape bus (11) source: 111 changed: 1 1 step 58 100000000000010010000000000000000000110111011111011010100110110111 source: 0 changed: 0 step 59 100000000000010010000000000000000000110111011011011010100110110111 source: source: source: ; walk a 0, TBN 2 source: source: source: ; clear pin AP2 which sets pin AN2 and clears pin BV2 TAPE BUS 2 OUTPUT source: 0 1 0 changed: 0 1 0 step 60 100000000000010000000000000000000000111101011011011010100110110111 source: ; set pin AF1 which clears pin BB2 and sets pin BR2 TAPE BUS 3 OUTPUT source: 1 0 1 changed: step 61 100000000000010000000000000000000000111101011011011010100110110111 source: ; load TBN from tape bus (01) source: 101 changed: 10 step 62 100000000000010000000000000000000000111101011011101010100110110111 source: 0 changed: 0 step 63 100000000000010000000000000000000000111101011011001010100110110111 source: ; restore TBN 2 source: ; set pin AP2 which clears pin AN2 and sets pin BV2 TAPE BUS 2 OUTPUT source: 1 0 1 changed: 1 0 1 step 64 100000000000010010000000000000000000110111011011001010100110110111 source: ; load TBN from tape bus (11) source: 111 changed: 11 step 65 100000000000010010000000000000000000110111011011111010100110110111 source: 0 changed: 0 step 66 100000000000010010000000000000000000110111011011011010100110110111 source: source: source: ; walk a 0, TBN 3 source: source: source: ; set pin AP2 which clears pin AN2 and sets pin BV2 TAPE BUS 2 OUTPUT source: 1 0 1 changed: step 67 100000000000010010000000000000000000110111011011011010100110110111 source: ; clear pin AF1 which sets pin BB2 and clears pin BR2 TAPE BUS 3 OUTPUT source: 0 1 0 changed: 0 1 0 step 68 100000000000000010000000000000000001110110011011011010100110110111 source: ; load TBN from tape bus (10) source: 110 changed: 1 0 step 69 100000000000000010000000000000000001110110011011110010100110110111 source: 0 changed: 0 step 70 100000000000000010000000000000000001110110011011010010100110110111 source: ; restore TBN 3 source: ; set pin AF1 which clears pin BB2 and sets pin BR2 TAPE BUS 3 OUTPUT source: 1 0 1 changed: 1 0 1 step 71 100000000000010010000000000000000000110111011011010010100110110111 source: ; load TBN from tape bus (11) source: 111 changed: 1 1 step 72 100000000000010010000000000000000000110111011011111010100110110111 source: 0 changed: 0 step 73 100000000000010010000000000000000000110111011011011010100110110111 source: source: source: ; walk a 0, TAC 2 source: source: source: ; clear pin AP2 which sets pin AN2 and clears pin BV2 TAPE BUS 2 OUTPUT source: 0 1 0 changed: 0 1 0 step 74 100000000000010000000000000000000000111101011011011010100110110111 source: ; set pin AF1 which clears pin BB2 and sets pin BR2 TAPE BUS 3 OUTPUT source: 1 0 1 changed: step 75 100000000000010000000000000000000000111101011011011010100110110111 source: ; load TAC from tape bus (01) source: 10110 changed: 101 step 76 100000000000010000000000000000000000111101011011011101100110110111 source: 0 changed: 0 step 77 100000000000010000000000000000000000111101011011011001100110110111 source: ; restore TAC 2 source: ; set pin AP2 which clears pin AN2 and sets pin BV2 TAPE BUS 2 OUTPUT source: 1 0 1 changed: 1 0 1 step 78 100000000000010010000000000000000000110111011011011001100110110111 source: ; load TAC from tape bus (11) source: 11010 changed: 110 step 79 100000000000010010000000000000000000110111011011011110100110110111 source: 0 changed: 0 step 80 100000000000010010000000000000000000110111011011011010100110110111 source: source: source: ; walk a 0, TAC 3 source: source: source: ; set pin AP2 which clears pin AN2 and sets pin BV2 TAPE BUS 2 OUTPUT source: 1 0 1 changed: step 81 100000000000010010000000000000000000110111011011011010100110110111 source: ; clear pin AF1 which sets pin BB2 and clears pin BR2 TAPE BUS 3 OUTPUT source: 0 1 0 changed: 0 1 0 step 82 100000000000000010000000000000000001110110011011011010100110110111 source: ; load TAC from tape bus (10) source: 11001 changed: 1 01 step 83 100000000000000010000000000000000001110110011011011110010110110111 source: 0 changed: 0 step 84 100000000000000010000000000000000001110110011011011010010110110111 source: ; restore TAC 3 source: ; set pin AF1 which clears pin BB2 and sets pin BR2 TAPE BUS 3 OUTPUT source: 1 0 1 changed: 1 0 1 step 85 100000000000010010000000000000000000110111011011011010010110110111 source: ; load TAC from tape bus (11) source: 11010 changed: 1 10 step 86 100000000000010010000000000000000000110111011011011110100110110111 source: 0 changed: 0 step 87 100000000000010010000000000000000000110111011011011010100110110111 SLOT BAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBAABBAAAAAAAAAAAAAABBBBBABBBB LETTER ALPSLFMDEEMCBFRSPKLEMFHRSCJLJKUHPNMBBNNVVRKRHUTDJUKANJHBTPDFSVEVDU SIDE 121212122121212121111111112212122222112222111221112112212112212122 DIRECTION IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIOOOOOOOIOOIOOIOOIOOOOIOOIIIIOOO source: source: source: source: source: source: source: source: source: source: source: source: source: source: source: source: source: source: source: source: ; load TB from tape bus (00) source: 100 changed: 1 step 88 100000000000010010000000000000000000110111011011011010101110110111 fail ^^ space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C toggle comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT BAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBAABBAAAAAAAAAAAAAABBBBBABBBB LETTER ALPSLFMDEEMCBFRSPKLEMFHRSCJLJKUHPNMBBNNVVRKRHUTDJUKANJHBTPDFSVEVDU SIDE 121212122121212121111111112212122222112222111221112112212112212122 DIRECTION IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIOOOOOOOIOOIOOIOOIOOOOIOOIIIIOOO all fails O O OO OO OO was lo 00000000000000000000000000000000000000 0000000000000000000000000 falling vvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvv vvvvvvvvvvvvvvvvvvvvvvvvv rising ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ ^^^^^^^^^^^^^^^^^^^^^^^^^ was hi 111111111111111111111111111111111111111111111111111111111111111111 total fails 1, total passes 0 Main menu Thu Aug 20 18:41:35 2015 test file is: tests\m222.new delay is: 0 trigger is: 1 1 read test file 2 set test delay 3 set test trigger 4 run test 5 output loading test 8 diags 9 exit exiting tester- PDP8 card tester via printer port version 0.85 June 4, 2015 mapping[] is verified Main menu Thu Aug 20 18:41:45 2015 test file is: delay is: 0 trigger is: 1 1 read test file 2 set test delay 3 set test trigger 4 run test 5 output loading test 8 diags 9 exit Enter test file name? trying to open test file: tests\m222.new reading test file: tests\m222.new comment: M222 PCB REV B SCHEMATIC REV A LINC TAPE REGISTERS comment: comment: TERMINOLOGY- SIGNALS REFER TO PDP12 MAINT VOL4 M222 SCHEMATIC. comment: comment: BUT... comment: comment: DEC USES AND-NOR GATES TO ROUTE THE ADDER A AND B INPUTS, SO... comment: DEC RENAMED THE ADDER TO NEGATIVE LOGIC TERMS (I.E. A-N + B-N + C-N -> SUM-N, C1-N). comment: (NOT THE 7482 DATASHEET NAMES OF A + B + C -> SUM, C1). comment: comment: SO, WITH ALL 'AND ENABLES' LOW, THE AND-NOR OUTPUTS = HIGH. comment: WITH C-L HIGH, THE ADDER OUTPUT IS SUM-N=1, C1-N=1; comment: THE INVERTED ADDER OUTPUT IS LOW (TAPE BUS). comment: AND THERE IS NO CARRY (C1-N IS HI). comment: comment: THE TWO ADDERS, TWO REGISTER BITS, ETC ARE LABELED BIT 2 (EVEN, MSB) AND BIT 3 (ODD, LSB). comment: THE ADDERS ARE REFERRED TO AS 'ADDER2' (MSB) AND 'ADDER3' (LSB). comment: comment: POWER PINS: comment: AA2 +5V comment: AT1 GROUND comment: AC2 GROUND comment: BA2 +5V comment: BT1 GROUND comment: BC2 GROUND comment: comment: (ALL PINS ARE USED). comment: comment: pins: PINS pins: 1 I BA1 CARRY IN-N, (TO E9-5 7482 C0) C-N TO ADDER2 pins: 2 I AL2 AND-NOR ENABLE: TAC TAC3 TO PIN BB2 (TO ADDER3) TAC2 TO PIN AN2 (TO ADDER2) pins: 3 I AP1 AND-NOR ENABLE: TMA SETUP (TMAS)3 TO PIN BB2 (TO ADDER3), (TMAS)3 TO PIN AN2 (TO ADDER2) pins: 4 I AS2 AND-NOR ENABLE: TMA TMA3 TO PIN BB2 (TO ADDER3), TMA2 TO PIN AN2 (TO ADDER2) pins: 5 I AL1 AND-NOR ENABLE: PIN AF2 TO PIN BB2 (TO ADDER3), PIN AM1 TO PIN AN2 (TO ADDER2) pins: 6 I AF2 AND-NOR INPUT (AL1 ENABLES) TO PIN BB2 (TO ADDER3). pins: 7 I AM1 AND-NOR INPUT (AL1 ENABLES) TO PIN AN2 (TO ADDER2) pins: 8 I AD2 AND-NOR ENABLE: RWB RWB3 TO PIN BB2 (TO ADDER3), RWB2 TO PIN AN2 (TO ADDER2) pins: 9 I AE2 AND-NOR ENABLE: PIN AE1 TO PIN BB2 (TO ADDER3), PIN AM2 TO PIN AN2 (TO ADDER2) pins: 10 I AE1 AND-NOR INPUT (AE2 ENABLES) TO PIN BB2 (TO ADDER3). pins: 11 I AM2 AND-NOR INPUT (AE2 ENABLES) TO PIN AN2 (TO ADDER2) pins: 12 I AC1 AND-NOR INPUT, AND WITH PIN AB2 TO PIN BB2 (TO ADDER3) pins: 13 I AB2 AND-NOR INPUT, AND WITH PIN AC1 TO PIN BB2 (TO ADDER3) pins: 14 I AF1 AND-NOR INPUT (AND WITH ITSELF) TO PIN BB2 (TO ADDER3) pins: 15 I AR2 AND-NOR INPUT, AND WITH PIN AS1 TO PIN AN2 (TO ADDER2) pins: 16 I AS1 AND-NOR INPUT, AND WITH PIN AR2 TO PIN AN2 (TO ADDER2) pins: 17 I AP2 AND-NOR INPUT (AND WITH ITSELF) TO PIN AN2 (TO ADDER2) pins: 18 I BK1 AND-NOR ENABLE: TB3 TO PIN BB1 (TO ADDER3), TB2 TO PIN BN1 (TO ADDER2) pins: 19 I BL1 AND-NOR ENABLE: PIN BE1 TO PIN BB1 (TO ADDER3), PIN BM1 TO PIN BN1 (TO ADDER2) pins: 20 I BE1 AND-NOR INPUT (BL1 ENABLES) TO PIN BB1 (TO ADDER3). pins: 21 I BM1 AND-NOR INPUT (BL1 ENABLES) TO PIN BN1 (TO ADDER2) pins: 22 I BF1 AND-NOR ENABLE: PIN BH1 TO PIN BB1 (TO ADDER3), PIN BR1 TO PIN BN1 (TO ADDER2) pins: 23 I BH1 AND-NOR INPUT (BF1 ENABLES): TO PIN BB1 (TO ADDER3), pins: 24 I BR1 AND-NOR INPUT (BF1 ENABLES): TO PIN BN1 (TO ADDER2) pins: 25 I BS1 AND-NOR ENABLE: PIN BC1 TO PIN BB1 (TO ADDER3), PIN BJ2 TO PIN BN1 (TO ADDER2) pins: 26 I BC1 AND-NOR INPUT (BS1 ENABLES): TO PIN BB1 (TO ADDER3), pins: 27 I BJ2 AND-NOR INPUT (BS1 ENABLES): TO PIN BN1 (TO ADDER2) pins: 28 I BL2 AND-NOR ENABLE: PIN BJ1 TO PIN BB1 (TO ADDER3), PIN BK2 TO PIN BN1 (TO ADDER2) pins: 29 I BJ1 AND-NOR INPUT (BL2 ENABLES): TO PIN BB1 (TO ADDER3), pins: 30 I BK2 AND-NOR INPUT (BL2 ENABLES): TO PIN BN1 (TO ADDER2) pins: 31 I BU1 AND-NOR ENABLE: PIN BH2 TO PIN BB1 (TO ADDER3), PIN BP2 TO PIN BN1 (TO ADDER2) pins: 32 I BH2 AND-NOR INPUT (BU1 ENABLES): TO PIN BB1 (TO ADDER3), pins: 33 I BP2 AND-NOR INPUT (BU1 ENABLES): TO PIN BN1 (TO ADDER2) pins: 34 I BN2 AND-NOR INPUT (AND WITH BM2): TO PIN BN1 (TO ADDER2) pins: 35 I BM2 AND-NOR INPUT (AND WITH BM2): TO PIN BN1 (TO ADDER2) pins: 36 O BB2 AND-NOR OUTPUT, (DRIVES E9-2 7482 A1) TO ADDER3 INPUT pins: 37 O BB1 AND-NOR OUTPUT, (DRIVES E9-3 7482 B1) TO ADDER3 INPUT pins: 38 O BN1 AND-NOR OUTPUT, (DRIVES E9-14 7482 A2) TO ADDER2 INPUT pins: 39 O AN2 AND-NOR OUTPUT, (DRIVES E9-13 7482 B2) TO ADDER2 INPUT pins: 40 O AV2 CARRY OUT-N (E9-10 7482 C2) pins: 41 O BV2 TAPE BUS 2 OUTPUT (INVERTED ADDER2 SUM-N (E9-12 7482 SUM2) pins: 42 O BR2 TAPE BUS 3 OUTPUT (INVERTED ADDER3 SUM-N (E9-1 7482 SUM1) pins: 43 I AK1 LOAD TMA SETUP (FROM TAPE BUS) (RISING EDGE CLOCK) pins: 44 O AR1 TMA SETUP 2 pins: 45 O AH1 TMA SETUP 3 pins: 46 I AU2 LOAD TMA (FROM TAPE BUS) (RISING EDGE CLOCK) pins: 47 O AT2 TMA 2 pins: 48 O AD1 TMA 3 pins: 49 I AJ1 LOAD TBN (FROM TAPE BUS) (RISING EDGE CLOCK) pins: 50 O AU1 TBN 2 pins: 51 O AK2 TBN 3 pins: 52 I AA1 LOAD TAC (FROM TAPE BUS) (RISING EDGE CLOCK) pins: 53 O AN1 TAC 2 pins: 54 O AJ2 TAC 2-N pins: 55 O AH2 TAC 3 pins: 56 O AB1 TAC 3-N pins: 57 I BT2 LOAD TB (FROM TAPE BUS) (RISING EDGE CLOCK) pins: 58 O BP1 TB 2 pins: 59 O BD1 TB 3 pins: 60 I BF2 LOAD RWB (FROM TB) (JAMS CLEAR,SET) pins: 61 I BS2 PHASE (SELECTS POLARITY OF RWB OUT, 0 -> INVERTED) pins: 62 I AV1 RWB IN (SHIFTED INTO RWB 3) pins: 63 I BE2 SHIFT RWB (SHIFTS PIN AV1 INTO RWB 3, SHIFTS RWB3 TO RWB2) (RISING CLOCK) pins: 64 O BV1 RWB OUT (IF PHASE=1, =RWB 2; IF PHASE=0; =RWB 2-N) pins: 65 O BD2 RWB 3 pins: 66 O BU2 +3.5V pins: direction: IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIOOOOOOOIOOIOOIOOIOOOOIOOIIIIOOO comment: ; all registers are unknown comment: ; turn on C0, PHASE comment: ; with no ENABLES, BUS2,BUS3 is 11, C2 is 1 test 1: 1000000000000000000000000000000000011111000XX0XX0XX0XXXX0XX0110XX1 comment: comment: ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; comment: ; comment: ; set all registers LOW comment: ; comment: ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; comment: comment: ; load TMA SETUP from tape bus (00) test 2: 100 test 3: 0 comment: ; load TMA from tape bus (00) test 4: 100 test 5: 0 comment: ; load TBN from tape bus (00) test 6: 100 test 7: 0 comment: ; load TAC from tape bus (00) test 8: 10101 test 9: 0 comment: ; load TB from tape bus (00) test 10: 100 test 11: 0 comment: ; load RWB from TB (JAMS CLEAR AND PRESET) test 12: 1 00 test 13: 0 comment: ; (no change) test 14: 100000000000000000000000000000000001111100000000000001010000110001 comment: comment: comment: ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; comment: ; comment: ; set all registers HIGH comment: ; comment: ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; comment: comment: ; set pin AF1 which clears pin BB2 and sets pin BR2 TAPE BUS 3 OUTPUT test 15: 1 0 1 comment: ; set pin AP2 which clears pin AN2 and sets pin BV2 TAPE BUS 2 OUTPUT test 16: 1 0 1 comment: comment: comment: ; load TMA SETUP from tape bus (11) test 17: 111 test 18: 0 comment: ; load TMA from tape bus (11) test 19: 111 test 20: 0 comment: ; load TBN from tape bus (11) test 21: 111 test 22: 0 comment: ; load TAC from tape bus (11) test 23: 11010 test 24: 0 comment: ; load TB from tape bus (11) test 25: 111 test 26: 0 comment: ; load RWB from TB (JAMS CLEAR AND PRESET) test 27: 1 11 test 28: 0 comment: ; clear pin AF1 (AND with itself) to set pin BB2 (AND-NOR output) and clear pin BR2 TAPE BUS 3 OUTPUT test 29: 0 1 0 comment: ; clear pin AP2 (AND with itself) to set pin AN2 (AND-NOR output) and clear pin BV2 TAPE BUS 2 OUTPUT test 30: 0 1 0 comment: ; (no change) test 31: 100000000000000000000000000000000001111100011011011010100110110111 comment: comment: ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; comment: ; comment: ; will all registers high, walk a 0 comment: ; comment: ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; comment: comment: comment: ; walk a 0, TMA SETUP 2 comment: comment: comment: ; clear pin AP2 which sets pin AN2 and clears pin BV2 TAPE BUS 2 OUTPUT test 32: 0 1 0 comment: ; set pin AF1 which clears pin BB2 and sets pin BR2 TAPE BUS 3 OUTPUT test 33: 1 0 1 comment: ; load TMA SETUP from tape bus (01) test 34: 101 test 35: 0 comment: ; restore TMA SETUP 2 comment: ; set pin AP2 which clears pin AN2 and sets pin BV2 TAPE BUS 2 OUTPUT test 36: 1 0 1 comment: ; load TMA SETUP from tape bus (11) test 37: 111 test 38: 0 comment: comment: comment: ; walk a 0, TMA SETUP 3 comment: comment: comment: ; set pin AP2 which clears pin AN2 and sets pin BV2 TAPE BUS 2 OUTPUT test 39: 1 0 1 comment: ; clear pin AF1 which sets pin BB2 and clears pin BR2 TAPE BUS 3 OUTPUT test 40: 0 1 0 comment: ; load TMA SETUP from tape bus (10) test 41: 110 test 42: 0 comment: ; restore TMA SETUP 3 comment: ; set pin AF1 which clears pin BB2 and sets pin BR2 TAPE BUS 3 OUTPUT test 43: 1 0 1 comment: ; load TMA SETUP from tape bus (11) test 44: 111 test 45: 0 comment: comment: comment: ; walk a 0, TMA 2 comment: comment: comment: ; clear pin AP2 which sets pin AN2 and clears pin BV2 TAPE BUS 2 OUTPUT test 46: 0 1 0 comment: ; set pin AF1 which clears pin BB2 and sets pin BR2 TAPE BUS 3 OUTPUT test 47: 1 0 1 comment: ; load TMA from tape bus (01) test 48: 101 test 49: 0 comment: ; restore TMA 2 comment: ; set pin AP2 which clears pin AN2 and sets pin BV2 TAPE BUS 2 OUTPUT test 50: 1 0 1 comment: ; load TMA from tape bus (11) test 51: 111 test 52: 0 comment: comment: comment: ; walk a 0, TMA 3 comment: comment: comment: ; set pin AP2 which clears pin AN2 and sets pin BV2 TAPE BUS 2 OUTPUT test 53: 1 0 1 comment: ; clear pin AF1 which sets pin BB2 and clears pin BR2 TAPE BUS 3 OUTPUT test 54: 0 1 0 comment: ; load TMA from tape bus (10) test 55: 110 test 56: 0 comment: ; restore TMA 3 comment: ; set pin AF1 which clears pin BB2 and sets pin BR2 TAPE BUS 3 OUTPUT test 57: 1 0 1 comment: ; load TMA from tape bus (11) test 58: 111 test 59: 0 comment: comment: comment: ; walk a 0, TBN 2 comment: comment: comment: ; clear pin AP2 which sets pin AN2 and clears pin BV2 TAPE BUS 2 OUTPUT test 60: 0 1 0 comment: ; set pin AF1 which clears pin BB2 and sets pin BR2 TAPE BUS 3 OUTPUT test 61: 1 0 1 comment: ; load TBN from tape bus (01) test 62: 101 test 63: 0 comment: ; restore TBN 2 comment: ; set pin AP2 which clears pin AN2 and sets pin BV2 TAPE BUS 2 OUTPUT test 64: 1 0 1 comment: ; load TBN from tape bus (11) test 65: 111 test 66: 0 comment: comment: comment: ; walk a 0, TBN 3 comment: comment: comment: ; set pin AP2 which clears pin AN2 and sets pin BV2 TAPE BUS 2 OUTPUT test 67: 1 0 1 comment: ; clear pin AF1 which sets pin BB2 and clears pin BR2 TAPE BUS 3 OUTPUT test 68: 0 1 0 comment: ; load TBN from tape bus (10) test 69: 110 test 70: 0 comment: ; restore TBN 3 comment: ; set pin AF1 which clears pin BB2 and sets pin BR2 TAPE BUS 3 OUTPUT test 71: 1 0 1 comment: ; load TBN from tape bus (11) test 72: 111 test 73: 0 comment: comment: comment: ; walk a 0, TAC 2 comment: comment: comment: ; clear pin AP2 which sets pin AN2 and clears pin BV2 TAPE BUS 2 OUTPUT test 74: 0 1 0 comment: ; set pin AF1 which clears pin BB2 and sets pin BR2 TAPE BUS 3 OUTPUT test 75: 1 0 1 comment: ; load TAC from tape bus (01) test 76: 10110 test 77: 0 comment: ; restore TAC 2 comment: ; set pin AP2 which clears pin AN2 and sets pin BV2 TAPE BUS 2 OUTPUT test 78: 1 0 1 comment: ; load TAC from tape bus (11) test 79: 11010 test 80: 0 comment: comment: comment: ; walk a 0, TAC 3 comment: comment: comment: ; set pin AP2 which clears pin AN2 and sets pin BV2 TAPE BUS 2 OUTPUT test 81: 1 0 1 comment: ; clear pin AF1 which sets pin BB2 and clears pin BR2 TAPE BUS 3 OUTPUT test 82: 0 1 0 comment: ; load TAC from tape bus (10) test 83: 11001 test 84: 0 comment: ; restore TAC 3 comment: ; set pin AF1 which clears pin BB2 and sets pin BR2 TAPE BUS 3 OUTPUT test 85: 1 0 1 comment: ; load TAC from tape bus (11) test 86: 11010 test 87: 0 comment: comment: comment: ; walk a 0, TB 2 comment: comment: comment: ; clear pin AP2 which sets pin AN2 and clears pin BV2 TAPE BUS 2 OUTPUT test 88: 0 1 0 comment: ; set pin AF1 which clears pin BB2 and sets pin BR2 TAPE BUS 3 OUTPUT test 89: 1 0 1 comment: ; load TB from tape bus (01) test 90: 101 test 91: 0 comment: ; restore TB 2 comment: ; set pin AP2 which clears pin AN2 and sets pin BV2 TAPE BUS 2 OUTPUT test 92: 1 0 1 comment: ; load TB from tape bus (11) test 93: 111 test 94: 0 comment: comment: comment: ; walk a 0, TB 3 comment: comment: comment: ; set pin AP2 which clears pin AN2 and sets pin BV2 TAPE BUS 2 OUTPUT test 95: 1 0 1 comment: ; clear pin AF1 which sets pin BB2 and clears pin BR2 TAPE BUS 3 OUTPUT test 96: 0 1 0 comment: ; load TB from tape bus (10) test 97: 110 test 98: 0 comment: ; restore TB 3 comment: ; set pin AF1 which clears pin BB2 and sets pin BR2 TAPE BUS 3 OUTPUT test 99: 1 0 1 comment: ; load TB from tape bus (11) test 100: 111 test 101: 0 comment: comment: comment: comment: comment: comment: comment: comment: comment: comment: comment: comment: comment: comment: comment: comment: comment: comment: comment: comment: comment: comment: ; load RWB from TB (JAMS CLEAR AND PRESET) test 102: 1 00 test 103: 0 comment: comment: comment: comment: comment: comment: comment: comment: comment: comment: comment: comment: comment: comment: comment: ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; comment: ; comment: ; test AND-NOR logic comment: ; comment: ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; comment: comment: ; (all registers are HIGH) comment: ; set all pins HIGH except ENABLES comment: comment: ; set pin AF2 HIGH test 104: 1 comment: ; set pin AM1 HIGH test 105: 1 comment: ; set pin AE1 HIGH test 106: 1 comment: ; set pin AM2 HIGH test 107: 1 comment: ; set pin AB2 HIGH test 108: 1 comment: ; set pin AS1 HIGH test 109: 1 comment: ; set pin BE1 HIGH test 110: 1 comment: ; set pin BM1 HIGH test 111: 1 comment: ; set pin BH1 HIGH test 112: 1 comment: ; set pin BR1 HIGH test 113: 1 comment: ; set pin BC1 HIGH test 114: 1 comment: ; set pin BJ2 HIGH test 115: 1 comment: ; set pin BJ1 HIGH test 116: 1 comment: ; set pin BK2 HIGH test 117: 1 comment: ; set pin BH2 HIGH test 118: 1 comment: ; set pin BP2 HIGH test 119: 1 comment: ; set pin BN2 HIGH test 120: 1 comment: ; toggle each ENABLE comment: comment: ; set pin AL2 to clear pin BB2 and pin AN2 AND-NOR OUTPUTS and set TAPE BUS 2 OUTPUT and TAPE BUS 3 OUTPUT test 121: 1 0 0 11 test 122: 0 1 1 00 comment: ; set pin AP1 to clear pin BB2 and pin AN2 AND-NOR OUTPUTS and set TAPE BUS 2 OUTPUT and TAPE BUS 3 OUTPUT test 123: 1 0 0 11 test 124: 0 1 1 00 comment: ; set pin AS2 to clear pin BB2 and pin AN2 AND-NOR OUTPUTS and set TAPE BUS 2 OUTPUT and TAPE BUS 3 OUTPUT test 125: 1 0 0 11 test 126: 0 1 1 00 comment: ; set pin AL1 to clear pin BB2 and pin AN2 AND-NOR OUTPUTS and set TAPE BUS 2 OUTPUT and TAPE BUS 3 OUTPUT test 127: 1 0 0 11 test 128: 0 1 1 00 comment: ; set pin AL1 to clear pin BB2 and pin AN2 AND-NOR OUTPUTS and set TAPE BUS 2 OUTPUT and TAPE BUS 3 OUTPUT test 129: 1 0 0 11 test 130: 0 1 1 00 comment: ; set pin AE2 to clear pin BB2 and pin AN2 AND-NOR OUTPUTS and set TAPE BUS 2 OUTPUT and TAPE BUS 3 OUTPUT test 131: 1 0 0 11 test 132: 0 1 1 00 comment: ; set pin AC1 to clear pin BB2 and set TAPE BUS 3 OUTPUT test 133: 1 0 1 test 134: 0 1 0 comment: ; set pin AF1 to clear pin BB2 and set TAPE BUS 3 OUTPUT test 135: 1 0 1 test 136: 0 1 0 comment: ; set pin AR2 to clear pin AN2 AND-NOR OUTPUTS and set TAPE BUS 2 OUTPUT test 137: 1 0 1 test 138: 0 1 0 comment: ; set pin AP2 to clear pin AN2 AND-NOR OUTPUTS and set TAPE BUS 2 OUTPUT test 139: 1 0 1 test 140: 0 1 0 comment: comment: ; set pin BK1 to clear pin BB1 and pin BN1 AND-NOR OUTPUTS and set TAPE BUS 2 OUTPUT and TAPE BUS 3 OUTPUT test 141: 1 00 11 test 142: 0 11 00 comment: ; set pin BL1 to clear pin BB1 and pin BN1 AND-NOR OUTPUTS and set TAPE BUS 2 OUTPUT and TAPE BUS 3 OUTPUT test 143: 1 00 11 test 144: 0 11 00 comment: ; set pin BF1 to clear pin BB1 and pin BN1 AND-NOR OUTPUTS and set TAPE BUS 2 OUTPUT and TAPE BUS 3 OUTPUT test 145: 1 00 11 test 146: 0 11 00 comment: ; set pin BS1 to clear pin BB1 and pin BN1 AND-NOR OUTPUTS and set TAPE BUS 2 OUTPUT and TAPE BUS 3 OUTPUT test 147: 1 00 11 test 148: 0 11 00 comment: ; set pin BL2 to clear pin BB1 and pin BN1 AND-NOR OUTPUTS and set TAPE BUS 2 OUTPUT and TAPE BUS 3 OUTPUT test 149: 1 00 11 test 150: 0 11 00 comment: ; set pin BU1 to clear pin BB1 and pin BN1 AND-NOR OUTPUTS and set TAPE BUS 2 OUTPUT and TAPE BUS 3 OUTPUT test 151: 1 00 11 test 152: 0 11 00 comment: ; set pin BM2 to clear pin BB1 and TAPE BUS 3 OUTPUT test 153: 1 0 1 test 154: 0 1 0 comment: ; no change test 155: 100000000000000000000000000000000001111100011011011010100110110111 comment: comment: ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; comment: ; test shifting the RWB comment: ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; comment: comment: ; shift in 0, expect 10 test 156: 0 test 157: 110 test 158: 0 comment: ; toggle phase should toggle RWB 2 test 159: 0 0 test 160: 1 1 comment: comment: ; shift in 0, expect 00 test 161: 0 test 162: 100 test 163: 0 comment: ; toggle phase should toggle RWB 2 test 164: 0 1 test 165: 1 0 comment: comment: ; shift in 0, expect 00 test 166: 0 test 167: 100 test 168: 0 comment: ; shift in 1, expect 01 test 169: 1 test 170: 101 test 171: 0 comment: ; shift in 1, expect 11 test 172: 1 test 173: 111 test 174: 0 comment: ; shift in 1, expect 11 test 175: 1 test 176: 111 test 177: 0 comment: ; shift in 0, expect 10 test 178: 0 test 179: 110 test 180: 0 comment: ; shift in 1, expect 01 test 181: 1 test 182: 101 test 183: 0 comment: ; shift in 0, expect 10 test 184: 0 test 185: 110 test 186: 0 comment: ; shift in 1, expect 01 test 187: 1 test 188: 101 test 189: 0 comment: ; shift in 1, expect 11 test 190: 1 test 191: 111 test 192: 0 comment: ; no change test 193: 100000000000000000000000000000000001111100011011011010100110110111 comment: comment: ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; comment: ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; comment: ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; comment: ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; comment: ; needs work (more adder tests, more register tests) comment: ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; comment: ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; comment: ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; comment: ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; end: END summary column 1: offset 2, mask 0x2000 column 2: offset 1, mask 0x0002 column 3: offset 1, mask 0x0800 column 4: offset 1, mask 0x0040 column 5: offset 1, mask 0x4000 column 6: offset 0, mask 0x0004 column 7: offset 1, mask 0x2000 column 8: offset 0, mask 0x0010 column 9: offset 0, mask 0x0008 column 10: offset 0, mask 0x0800 column 11: offset 1, mask 0x0004 column 12: offset 0, mask 0x2000 column 13: offset 0, mask 0x0040 column 14: offset 0, mask 0x0400 column 15: offset 1, mask 0x0020 column 16: offset 1, mask 0x0200 column 17: offset 1, mask 0x0010 column 18: offset 3, mask 0x2000 column 19: offset 3, mask 0x1000 column 20: offset 2, mask 0x0200 column 21: offset 3, mask 0x0800 column 22: offset 2, mask 0x0100 column 23: offset 3, mask 0x8000 column 24: offset 3, mask 0x0100 column 25: offset 4, mask 0x8000 column 26: offset 2, mask 0x0800 column 27: offset 3, mask 0x0002 column 28: offset 3, mask 0x0008 column 29: offset 3, mask 0x4000 column 30: offset 3, mask 0x0004 column 31: offset 4, mask 0x2000 column 32: offset 3, mask 0x0001 column 33: offset 3, mask 0x0040 column 34: offset 3, mask 0x0020 column 35: offset 3, mask 0x0010 column 36: offset 2, mask 0x0008 column 37: offset 2, mask 0x1000 column 38: offset 3, mask 0x0400 column 39: offset 1, mask 0x0008 column 40: offset 2, mask 0x0002 column 41: offset 4, mask 0x0008 column 42: offset 3, mask 0x0080 column 43: offset 1, mask 0x8000 column 44: offset 1, mask 0x0400 column 45: offset 0, mask 0x0200 column 46: offset 2, mask 0x0001 column 47: offset 1, mask 0x0080 column 48: offset 0, mask 0x1000 column 49: offset 0, mask 0x0100 column 50: offset 2, mask 0x8000 column 51: offset 1, mask 0x0001 column 52: offset 0, mask 0x8000 column 53: offset 1, mask 0x1000 column 54: offset 0, mask 0x0001 column 55: offset 0, mask 0x0002 column 56: offset 0, mask 0x4000 column 57: offset 4, mask 0x0002 column 58: offset 3, mask 0x0200 column 59: offset 2, mask 0x0400 column 60: offset 2, mask 0x0080 column 61: offset 4, mask 0x0001 column 62: offset 2, mask 0x4000 column 63: offset 2, mask 0x0040 column 64: offset 4, mask 0x1000 column 65: offset 2, mask 0x0020 column 66: offset 4, mask 0x0004 direction bits (1=input) 0x52A3 0x1589 0x943A 0x0680 0x50FC pullup bits (1=pullup) 0x0000 0x0000 0x0000 0x0000 0x0000 test step out_data dont care 1: 0x0000 0x0008 0x700A 0x0400 0x0005 0x5203 0x1481 0x8420 0x0200 0x1000 2: 0x0000 0x8008 0x700A 0x0400 0x0005 0x5003 0x1081 0x8420 0x0200 0x1000 3: 0x0000 0x0008 0x700A 0x0400 0x0005 0x5003 0x1081 0x8420 0x0200 0x1000 4: 0x0000 0x0008 0x700B 0x0400 0x0005 0x4003 0x1001 0x8420 0x0200 0x1000 5: 0x0000 0x0008 0x700A 0x0400 0x0005 0x4003 0x1001 0x8420 0x0200 0x1000 6: 0x0100 0x0008 0x700A 0x0400 0x0005 0x4003 0x1000 0x0420 0x0200 0x1000 7: 0x0000 0x0008 0x700A 0x0400 0x0005 0x4003 0x1000 0x0420 0x0200 0x1000 8: 0xC001 0x0008 0x700A 0x0400 0x0005 0x0000 0x0000 0x0420 0x0200 0x1000 9: 0x4001 0x0008 0x700A 0x0400 0x0005 0x0000 0x0000 0x0420 0x0200 0x1000 10: 0x4001 0x0008 0x700A 0x0400 0x0007 0x0000 0x0000 0x0020 0x0000 0x1000 11: 0x4001 0x0008 0x700A 0x0400 0x0005 0x0000 0x0000 0x0020 0x0000 0x1000 12: 0x4001 0x0008 0x708A 0x0400 0x0005 13: 0x4001 0x0008 0x700A 0x0400 0x0005 14: 0x4001 0x0008 0x700A 0x0400 0x0005 15: 0x4401 0x0008 0x7002 0x0480 0x0005 16: 0x4401 0x0010 0x7002 0x0480 0x000D 17: 0x4601 0x8410 0x7002 0x0480 0x000D 18: 0x4601 0x0410 0x7002 0x0480 0x000D 19: 0x5601 0x0490 0x7003 0x0480 0x000D 20: 0x5601 0x0490 0x7002 0x0480 0x000D 21: 0x5701 0x0491 0xF002 0x0480 0x000D 22: 0x5601 0x0491 0xF002 0x0480 0x000D 23: 0x9602 0x1491 0xF002 0x0480 0x000D 24: 0x1602 0x1491 0xF002 0x0480 0x000D 25: 0x1602 0x1491 0xF402 0x0680 0x000F 26: 0x1602 0x1491 0xF402 0x0680 0x000D 27: 0x1602 0x1491 0xF4A2 0x0680 0x100D 28: 0x1602 0x1491 0xF422 0x0680 0x100D 29: 0x1202 0x1491 0xF42A 0x0600 0x100D 30: 0x1202 0x1489 0xF42A 0x0600 0x1005 31: 0x1202 0x1489 0xF42A 0x0600 0x1005 32: 0x1202 0x1489 0xF42A 0x0600 0x1005 33: 0x1602 0x1489 0xF422 0x0680 0x1005 34: 0x1602 0x9089 0xF422 0x0680 0x1005 35: 0x1602 0x1089 0xF422 0x0680 0x1005 36: 0x1602 0x1091 0xF422 0x0680 0x100D 37: 0x1602 0x9491 0xF422 0x0680 0x100D 38: 0x1602 0x1491 0xF422 0x0680 0x100D 39: 0x1602 0x1491 0xF422 0x0680 0x100D 40: 0x1202 0x1491 0xF42A 0x0600 0x100D 41: 0x1002 0x9491 0xF42A 0x0600 0x100D 42: 0x1002 0x1491 0xF42A 0x0600 0x100D 43: 0x1402 0x1491 0xF422 0x0680 0x100D 44: 0x1602 0x9491 0xF422 0x0680 0x100D 45: 0x1602 0x1491 0xF422 0x0680 0x100D 46: 0x1602 0x1489 0xF422 0x0680 0x1005 47: 0x1602 0x1489 0xF422 0x0680 0x1005 48: 0x1602 0x1409 0xF423 0x0680 0x1005 49: 0x1602 0x1409 0xF422 0x0680 0x1005 50: 0x1602 0x1411 0xF422 0x0680 0x100D 51: 0x1602 0x1491 0xF423 0x0680 0x100D 52: 0x1602 0x1491 0xF422 0x0680 0x100D 53: 0x1602 0x1491 0xF422 0x0680 0x100D 54: 0x1202 0x1491 0xF42A 0x0600 0x100D 55: 0x0202 0x1491 0xF42B 0x0600 0x100D 56: 0x0202 0x1491 0xF42A 0x0600 0x100D 57: 0x0602 0x1491 0xF422 0x0680 0x100D 58: 0x1602 0x1491 0xF423 0x0680 0x100D 59: 0x1602 0x1491 0xF422 0x0680 0x100D 60: 0x1602 0x1489 0xF422 0x0680 0x1005 61: 0x1602 0x1489 0xF422 0x0680 0x1005 62: 0x1702 0x1489 0x7422 0x0680 0x1005 63: 0x1602 0x1489 0x7422 0x0680 0x1005 64: 0x1602 0x1491 0x7422 0x0680 0x100D 65: 0x1702 0x1491 0xF422 0x0680 0x100D 66: 0x1602 0x1491 0xF422 0x0680 0x100D 67: 0x1602 0x1491 0xF422 0x0680 0x100D 68: 0x1202 0x1491 0xF42A 0x0600 0x100D 69: 0x1302 0x1490 0xF42A 0x0600 0x100D 70: 0x1202 0x1490 0xF42A 0x0600 0x100D 71: 0x1602 0x1490 0xF422 0x0680 0x100D 72: 0x1702 0x1491 0xF422 0x0680 0x100D 73: 0x1602 0x1491 0xF422 0x0680 0x100D 74: 0x1602 0x1489 0xF422 0x0680 0x1005 75: 0x1602 0x1489 0xF422 0x0680 0x1005 76: 0x9603 0x0489 0xF422 0x0680 0x1005 77: 0x1603 0x0489 0xF422 0x0680 0x1005 78: 0x1603 0x0491 0xF422 0x0680 0x100D 79: 0x9602 0x1491 0xF422 0x0680 0x100D 80: 0x1602 0x1491 0xF422 0x0680 0x100D 81: 0x1602 0x1491 0xF422 0x0680 0x100D 82: 0x1202 0x1491 0xF42A 0x0600 0x100D 83: 0xD200 0x1491 0xF42A 0x0600 0x100D 84: 0x5200 0x1491 0xF42A 0x0600 0x100D 85: 0x5600 0x1491 0xF422 0x0680 0x100D 86: 0x9602 0x1491 0xF422 0x0680 0x100D 87: 0x1602 0x1491 0xF422 0x0680 0x100D 88: 0x1602 0x1489 0xF422 0x0680 0x1005 89: 0x1602 0x1489 0xF422 0x0680 0x1005 90: 0x1602 0x1489 0xF422 0x0480 0x1007 91: 0x1602 0x1489 0xF422 0x0480 0x1005 92: 0x1602 0x1491 0xF422 0x0480 0x100D 93: 0x1602 0x1491 0xF422 0x0680 0x100F 94: 0x1602 0x1491 0xF422 0x0680 0x100D 95: 0x1602 0x1491 0xF422 0x0680 0x100D 96: 0x1202 0x1491 0xF42A 0x0600 0x100D 97: 0x1202 0x1491 0xF02A 0x0600 0x100F 98: 0x1202 0x1491 0xF02A 0x0600 0x100D 99: 0x1602 0x1491 0xF022 0x0680 0x100D 100: 0x1602 0x1491 0xF422 0x0680 0x100F 101: 0x1602 0x1491 0xF422 0x0680 0x100D 102: 0x1602 0x1491 0xF482 0x0680 0x000D 103: 0x1602 0x1491 0xF402 0x0680 0x000D 104: 0x1606 0x1491 0xF402 0x0680 0x000D 105: 0x1606 0x3491 0xF402 0x0680 0x000D 106: 0x1E06 0x3491 0xF402 0x0680 0x000D 107: 0x1E06 0x3495 0xF402 0x0680 0x000D 108: 0x1E46 0x3495 0xF402 0x0680 0x000D 109: 0x1E46 0x3695 0xF402 0x0680 0x000D 110: 0x1E46 0x3695 0xF602 0x0680 0x000D 111: 0x1E46 0x3695 0xF602 0x0E80 0x000D 112: 0x1E46 0x3695 0xF602 0x8E80 0x000D 113: 0x1E46 0x3695 0xF602 0x8F80 0x000D 114: 0x1E46 0x3695 0xFE02 0x8F80 0x000D 115: 0x1E46 0x3695 0xFE02 0x8F82 0x000D 116: 0x1E46 0x3695 0xFE02 0xCF82 0x000D 117: 0x1E46 0x3695 0xFE02 0xCF86 0x000D 118: 0x1E46 0x3695 0xFE02 0xCF87 0x000D 119: 0x1E46 0x3695 0xFE02 0xCFC7 0x000D 120: 0x1E46 0x3695 0xFE02 0xCFE7 0x000D 121: 0x1E46 0x3697 0xFE02 0xCFE7 0x000D 122: 0x1E46 0x369D 0xFE0A 0xCF67 0x0005 123: 0x1E46 0x3E95 0xFE02 0xCFE7 0x000D 124: 0x1E46 0x369D 0xFE0A 0xCF67 0x0005 125: 0x1E46 0x36D5 0xFE02 0xCFE7 0x000D 126: 0x1E46 0x369D 0xFE0A 0xCF67 0x0005 127: 0x1E46 0x7695 0xFE02 0xCFE7 0x000D 128: 0x1E46 0x369D 0xFE0A 0xCF67 0x0005 129: 0x1E56 0x3695 0xFE02 0xCFE7 0x000D 130: 0x1E46 0x369D 0xFE0A 0xCF67 0x0005 131: 0x1E4E 0x3695 0xFE02 0xCFE7 0x000D 132: 0x1E46 0x369D 0xFE0A 0xCF67 0x0005 133: 0x3E46 0x369D 0xFE02 0xCFE7 0x0005 134: 0x1E46 0x369D 0xFE0A 0xCF67 0x0005 135: 0x1E46 0x369D 0xFE02 0xCFE7 0x0005 136: 0x1A46 0x369D 0xFE0A 0xCF67 0x0005 137: 0x1A46 0x36B5 0xFE0A 0xCF67 0x000D 138: 0x1A46 0x369D 0xFE0A 0xCF67 0x0005 139: 0x1A46 0x3695 0xFE0A 0xCF67 0x000D 140: 0x1A46 0x368D 0xFE0A 0xCF67 0x0005 141: 0x1A46 0x368D 0xEE0A 0xEBE7 0x000D 142: 0x1A46 0x368D 0xFE0A 0xCF67 0x0005 143: 0x1A46 0x368D 0xEE0A 0xDBE7 0x000D 144: 0x1A46 0x368D 0xFE0A 0xCF67 0x0005 145: 0x1A46 0x368D 0xEF0A 0xCBE7 0x000D 146: 0x1A46 0x368D 0xFE0A 0xCF67 0x0005 147: 0x1A46 0x368D 0xEE0A 0xCBE7 0x800D 148: 0x1A46 0x368D 0xFE0A 0xCF67 0x0005 149: 0x1A46 0x368D 0xEE0A 0xCBEF 0x000D 150: 0x1A46 0x368D 0xFE0A 0xCF67 0x0005 151: 0x1A46 0x368D 0xEE0A 0xCBE7 0x200D 152: 0x1A46 0x368D 0xFE0A 0xCF67 0x0005 153: 0x1A46 0x368D 0xFE0A 0xCB77 0x000D 154: 0x1A46 0x368D 0xFE0A 0xCF67 0x0005 155: 0x1202 0x1489 0xF42A 0x0600 0x1005 156: 0x1202 0x1489 0xB42A 0x0600 0x1005 157: 0x1202 0x1489 0xB44A 0x0600 0x1005 158: 0x1202 0x1489 0xB40A 0x0600 0x1005 159: 0x1202 0x1489 0xB40A 0x0600 0x0004 160: 0x1202 0x1489 0xB40A 0x0600 0x1005 161: 0x1202 0x1489 0xB40A 0x0600 0x1005 162: 0x1202 0x1489 0xB44A 0x0600 0x0005 163: 0x1202 0x1489 0xB40A 0x0600 0x0005 164: 0x1202 0x1489 0xB40A 0x0600 0x1004 165: 0x1202 0x1489 0xB40A 0x0600 0x0005 166: 0x1202 0x1489 0xB40A 0x0600 0x0005 167: 0x1202 0x1489 0xB44A 0x0600 0x0005 168: 0x1202 0x1489 0xB40A 0x0600 0x0005 169: 0x1202 0x1489 0xF40A 0x0600 0x0005 170: 0x1202 0x1489 0xF46A 0x0600 0x0005 171: 0x1202 0x1489 0xF42A 0x0600 0x0005 172: 0x1202 0x1489 0xF42A 0x0600 0x0005 173: 0x1202 0x1489 0xF46A 0x0600 0x1005 174: 0x1202 0x1489 0xF42A 0x0600 0x1005 175: 0x1202 0x1489 0xF42A 0x0600 0x1005 176: 0x1202 0x1489 0xF46A 0x0600 0x1005 177: 0x1202 0x1489 0xF42A 0x0600 0x1005 178: 0x1202 0x1489 0xB42A 0x0600 0x1005 179: 0x1202 0x1489 0xB44A 0x0600 0x1005 180: 0x1202 0x1489 0xB40A 0x0600 0x1005 181: 0x1202 0x1489 0xF40A 0x0600 0x1005 182: 0x1202 0x1489 0xF46A 0x0600 0x0005 183: 0x1202 0x1489 0xF42A 0x0600 0x0005 184: 0x1202 0x1489 0xB42A 0x0600 0x0005 185: 0x1202 0x1489 0xB44A 0x0600 0x1005 186: 0x1202 0x1489 0xB40A 0x0600 0x1005 187: 0x1202 0x1489 0xF40A 0x0600 0x1005 188: 0x1202 0x1489 0xF46A 0x0600 0x0005 189: 0x1202 0x1489 0xF42A 0x0600 0x0005 190: 0x1202 0x1489 0xF42A 0x0600 0x0005 191: 0x1202 0x1489 0xF46A 0x0600 0x1005 192: 0x1202 0x1489 0xF42A 0x0600 0x1005 193: 0x1202 0x1489 0xF42A 0x0600 0x1005 PINs used (in edge connector order) (G=ground,P=power) SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBB LETTER ABCDEFHJKLMNPRSTUVABCDEFHJKLMNPRSTUVABCDEFHJKLMNPRSTUVABCDEFHJKLMNPRSTUV SIDE 111111111111111111222222222222222222111111111111111111222222222222222222 USAGE IOIOIIOIIIIOIOIGOIPIGIIIOOOIIOIIIOIOIOIOIIIIIIIOOIIGIOPOGOIIIIIIIIIOIIOO UUT has 44 inputs UUT has 22 outputs contains 66 pins/columns 0 pins are not used contains 193 'test steps' M222 PCB REV B SCHEMATIC REV A LINC TAPE REGISTERS TERMINOLOGY- SIGNALS REFER TO PDP12 MAINT VOL4 M222 SCHEMATIC. BUT... DEC USES AND-NOR GATES TO ROUTE THE ADDER A AND B INPUTS, SO... DEC RENAMED THE ADDER TO NEGATIVE LOGIC TERMS (I.E. A-N + B-N + C-N -> SUM-N, C1-N). (NOT THE 7482 DATASHEET NAMES OF A + B + C -> SUM, C1). SO, WITH ALL 'AND ENABLES' LOW, THE AND-NOR OUTPUTS = HIGH. WITH C-L HIGH, THE ADDER OUTPUT IS SUM-N=1, C1-N=1; THE INVERTED ADDER OUTPUT IS LOW (TAPE BUS). AND THERE IS NO CARRY (C1-N IS HI). THE TWO ADDERS, TWO REGISTER BITS, ETC ARE LABELED BIT 2 (EVEN, MSB) AND BIT 3 (ODD, LSB). THE ADDERS ARE REFERRED TO AS 'ADDER2' (MSB) AND 'ADDER3' (LSB). POWER PINS: AA2 +5V AT1 GROUND AC2 GROUND BA2 +5V BT1 GROUND BC2 GROUND (ALL PINS ARE USED). PINS Main menu Thu Aug 20 18:44:53 2015 test file is: tests\m222.new delay is: 0 trigger is: 1 1 read test file 2 set test delay 3 set test trigger 4 run test 5 output loading test 8 diags 9 exit key is 0x0063 Main menu Thu Aug 20 18:44:54 2015 test file is: tests\m222.new delay is: 0 trigger is: 1 1 read test file 2 set test delay 3 set test trigger 4 run test 5 output loading test 8 diags 9 exit UUT power is okay Thu Aug 20 18:44:55 2015 space single step O run once (one test, all steps) F run, stop on fail G go (run tests N run, stop on fail, no print S scope (run, no print) C toggle comment printout + increase speed (less delay) - decrease speed (more delay)(slower) Q quit test comment_flag is 1 space single step O run once (one test, all steps) F run, stop on fail G go (run tests N run, stop on fail, no print S scope (run, no print) C toggle comment printout + increase speed (less delay) - decrease speed (more delay)(slower) Q quit test source: ; all registers are unknown source: ; turn on C0, PHASE source: ; with no ENABLES, BUS2,BUS3 is 11, C2 is 1 source: 1000000000000000000000000000000000011111000XX0XX0XX0XXXX0XX0110XX1 changed: step 1 100000000000000000000000000000000001111100011011011010100110110111 source: source: ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; source: ; source: ; set all registers LOW source: ; source: ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; source: source: ; load TMA SETUP from tape bus (00) source: 100 changed: 100 step 2 100000000000000000000000000000000001111100100011011010100110110111 source: 0 changed: 0 step 3 100000000000000000000000000000000001111100000011011010100110110111 source: ; load TMA from tape bus (00) source: 100 changed: 100 step 4 100000000000000000000000000000000001111100000100011010100110110111 source: 0 changed: 0 step 5 100000000000000000000000000000000001111100000000011010100110110111 source: ; load TBN from tape bus (00) source: 100 changed: 100 step 6 100000000000000000000000000000000001111100000000100010100110110111 source: 0 changed: 0 step 7 100000000000000000000000000000000001111100000000000010100110110111 source: ; load TAC from tape bus (00) source: 10101 changed: 10101 step 8 100000000000000000000000000000000001111100000000000101010110110111 source: 0 changed: 0 step 9 100000000000000000000000000000000001111100000000000001010110110111 source: ; load TB from tape bus (00) source: 100 changed: 100 step 10 100000000000000000000000000000000001111100000000000001011000110111 source: 0 changed: 0 step 11 100000000000000000000000000000000001111100000000000001010000110111 source: ; load RWB from TB (JAMS CLEAR AND PRESET) source: 1 00 changed: 1 00 step 12 100000000000000000000000000000000001111100000000000001010001110001 source: 0 changed: 0 step 13 100000000000000000000000000000000001111100000000000001010000110001 source: ; (no change) source: 100000000000000000000000000000000001111100000000000001010000110001 changed: step 14 100000000000000000000000000000000001111100000000000001010000110001 source: source: source: ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; source: ; source: ; set all registers HIGH source: ; source: ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; source: source: ; set pin AF1 which clears pin BB2 and sets pin BR2 TAPE BUS 3 OUTPUT source: 1 0 1 changed: 1 0 1 step 15 100000000000010000000000000000000000111101000000000001010000110001 source: ; set pin AP2 which clears pin AN2 and sets pin BV2 TAPE BUS 2 OUTPUT source: 1 0 1 changed: 1 0 1 step 16 100000000000010010000000000000000000110111000000000001010000110001 source: source: source: ; load TMA SETUP from tape bus (11) source: 111 changed: 111 step 17 100000000000010010000000000000000000110111111000000001010000110001 source: 0 changed: 0 step 18 100000000000010010000000000000000000110111011000000001010000110001 source: ; load TMA from tape bus (11) source: 111 changed: 111 step 19 100000000000010010000000000000000000110111011111000001010000110001 source: 0 changed: 0 step 20 100000000000010010000000000000000000110111011011000001010000110001 source: ; load TBN from tape bus (11) source: 111 changed: 111 step 21 100000000000010010000000000000000000110111011011111001010000110001 source: 0 changed: 0 step 22 100000000000010010000000000000000000110111011011011001010000110001 source: ; load TAC from tape bus (11) source: 11010 changed: 11010 step 23 100000000000010010000000000000000000110111011011011110100000110001 source: 0 changed: 0 step 24 100000000000010010000000000000000000110111011011011010100000110001 source: ; load TB from tape bus (11) source: 111 changed: 111 step 25 100000000000010010000000000000000000110111011011011010101110110001 source: 0 changed: 0 step 26 100000000000010010000000000000000000110111011011011010100110110001 source: ; load RWB from TB (JAMS CLEAR AND PRESET) source: 1 11 changed: 1 11 step 27 100000000000010010000000000000000000110111011011011010100111110111 source: 0 changed: 0 step 28 100000000000010010000000000000000000110111011011011010100110110111 source: ; clear pin AF1 (AND with itself) to set pin BB2 (AND-NOR output) and clear pin BR2 TAPE BUS 3 OUTPUT source: 0 1 0 changed: 0 1 0 step 29 100000000000000010000000000000000001110110011011011010100110110111 source: ; clear pin AP2 (AND with itself) to set pin AN2 (AND-NOR output) and clear pin BV2 TAPE BUS 2 OUTPUT source: 0 1 0 changed: 0 1 0 step 30 100000000000000000000000000000000001111100011011011010100110110111 source: ; (no change) source: 100000000000000000000000000000000001111100011011011010100110110111 changed: step 31 100000000000000000000000000000000001111100011011011010100110110111 source: source: ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; source: ; source: ; will all registers high, walk a 0 source: ; source: ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; source: source: source: ; walk a 0, TMA SETUP 2 source: source: source: ; clear pin AP2 which sets pin AN2 and clears pin BV2 TAPE BUS 2 OUTPUT source: 0 1 0 changed: step 32 100000000000000000000000000000000001111100011011011010100110110111 source: ; set pin AF1 which clears pin BB2 and sets pin BR2 TAPE BUS 3 OUTPUT source: 1 0 1 changed: 1 0 1 step 33 100000000000010000000000000000000000111101011011011010100110110111 source: ; load TMA SETUP from tape bus (01) source: 101 changed: 10 step 34 100000000000010000000000000000000000111101101011011010100110110111 source: 0 changed: 0 step 35 100000000000010000000000000000000000111101001011011010100110110111 source: ; restore TMA SETUP 2 source: ; set pin AP2 which clears pin AN2 and sets pin BV2 TAPE BUS 2 OUTPUT source: 1 0 1 changed: 1 0 1 step 36 100000000000010010000000000000000000110111001011011010100110110111 source: ; load TMA SETUP from tape bus (11) source: 111 changed: 11 step 37 100000000000010010000000000000000000110111111011011010100110110111 source: 0 changed: 0 step 38 100000000000010010000000000000000000110111011011011010100110110111 source: source: source: ; walk a 0, TMA SETUP 3 source: source: source: ; set pin AP2 which clears pin AN2 and sets pin BV2 TAPE BUS 2 OUTPUT source: 1 0 1 changed: step 39 100000000000010010000000000000000000110111011011011010100110110111 source: ; clear pin AF1 which sets pin BB2 and clears pin BR2 TAPE BUS 3 OUTPUT source: 0 1 0 changed: 0 1 0 step 40 100000000000000010000000000000000001110110011011011010100110110111 source: ; load TMA SETUP from tape bus (10) source: 110 changed: 1 0 step 41 100000000000000010000000000000000001110110110011011010100110110111 source: 0 changed: 0 step 42 100000000000000010000000000000000001110110010011011010100110110111 source: ; restore TMA SETUP 3 source: ; set pin AF1 which clears pin BB2 and sets pin BR2 TAPE BUS 3 OUTPUT source: 1 0 1 changed: 1 0 1 step 43 100000000000010010000000000000000000110111010011011010100110110111 source: ; load TMA SETUP from tape bus (11) source: 111 changed: 1 1 step 44 100000000000010010000000000000000000110111111011011010100110110111 source: 0 changed: 0 step 45 100000000000010010000000000000000000110111011011011010100110110111 source: source: source: ; walk a 0, TMA 2 source: source: source: ; clear pin AP2 which sets pin AN2 and clears pin BV2 TAPE BUS 2 OUTPUT source: 0 1 0 changed: 0 1 0 step 46 100000000000010000000000000000000000111101011011011010100110110111 source: ; set pin AF1 which clears pin BB2 and sets pin BR2 TAPE BUS 3 OUTPUT source: 1 0 1 changed: step 47 100000000000010000000000000000000000111101011011011010100110110111 source: ; load TMA from tape bus (01) source: 101 changed: 10 step 48 100000000000010000000000000000000000111101011101011010100110110111 source: 0 changed: 0 step 49 100000000000010000000000000000000000111101011001011010100110110111 source: ; restore TMA 2 source: ; set pin AP2 which clears pin AN2 and sets pin BV2 TAPE BUS 2 OUTPUT source: 1 0 1 changed: 1 0 1 step 50 100000000000010010000000000000000000110111011001011010100110110111 source: ; load TMA from tape bus (11) source: 111 changed: 11 step 51 100000000000010010000000000000000000110111011111011010100110110111 source: 0 changed: 0 step 52 100000000000010010000000000000000000110111011011011010100110110111 source: source: source: ; walk a 0, TMA 3 source: source: source: ; set pin AP2 which clears pin AN2 and sets pin BV2 TAPE BUS 2 OUTPUT source: 1 0 1 changed: step 53 100000000000010010000000000000000000110111011011011010100110110111 source: ; clear pin AF1 which sets pin BB2 and clears pin BR2 TAPE BUS 3 OUTPUT source: 0 1 0 changed: 0 1 0 step 54 100000000000000010000000000000000001110110011011011010100110110111 source: ; load TMA from tape bus (10) source: 110 changed: 1 0 step 55 100000000000000010000000000000000001110110011110011010100110110111 source: 0 changed: 0 step 56 100000000000000010000000000000000001110110011010011010100110110111 source: ; restore TMA 3 source: ; set pin AF1 which clears pin BB2 and sets pin BR2 TAPE BUS 3 OUTPUT source: 1 0 1 changed: 1 0 1 step 57 100000000000010010000000000000000000110111011010011010100110110111 source: ; load TMA from tape bus (11) source: 111 changed: 1 1 step 58 100000000000010010000000000000000000110111011111011010100110110111 source: 0 changed: 0 step 59 100000000000010010000000000000000000110111011011011010100110110111 source: source: source: ; walk a 0, TBN 2 source: source: source: ; clear pin AP2 which sets pin AN2 and clears pin BV2 TAPE BUS 2 OUTPUT source: 0 1 0 changed: 0 1 0 step 60 100000000000010000000000000000000000111101011011011010100110110111 source: ; set pin AF1 which clears pin BB2 and sets pin BR2 TAPE BUS 3 OUTPUT source: 1 0 1 changed: step 61 100000000000010000000000000000000000111101011011011010100110110111 source: ; load TBN from tape bus (01) source: 101 changed: 10 step 62 100000000000010000000000000000000000111101011011101010100110110111 source: 0 changed: 0 step 63 100000000000010000000000000000000000111101011011001010100110110111 source: ; restore TBN 2 source: ; set pin AP2 which clears pin AN2 and sets pin BV2 TAPE BUS 2 OUTPUT source: 1 0 1 changed: 1 0 1 step 64 100000000000010010000000000000000000110111011011001010100110110111 source: ; load TBN from tape bus (11) source: 111 changed: 11 step 65 100000000000010010000000000000000000110111011011111010100110110111 source: 0 changed: 0 step 66 100000000000010010000000000000000000110111011011011010100110110111 source: source: source: ; walk a 0, TBN 3 source: source: source: ; set pin AP2 which clears pin AN2 and sets pin BV2 TAPE BUS 2 OUTPUT source: 1 0 1 changed: step 67 100000000000010010000000000000000000110111011011011010100110110111 source: ; clear pin AF1 which sets pin BB2 and clears pin BR2 TAPE BUS 3 OUTPUT source: 0 1 0 changed: 0 1 0 step 68 100000000000000010000000000000000001110110011011011010100110110111 source: ; load TBN from tape bus (10) source: 110 changed: 1 0 step 69 100000000000000010000000000000000001110110011011110010100110110111 source: 0 changed: 0 step 70 100000000000000010000000000000000001110110011011010010100110110111 source: ; restore TBN 3 source: ; set pin AF1 which clears pin BB2 and sets pin BR2 TAPE BUS 3 OUTPUT source: 1 0 1 changed: 1 0 1 step 71 100000000000010010000000000000000000110111011011010010100110110111 source: ; load TBN from tape bus (11) source: 111 changed: 1 1 step 72 100000000000010010000000000000000000110111011011111010100110110111 source: 0 changed: 0 step 73 100000000000010010000000000000000000110111011011011010100110110111 source: source: source: ; walk a 0, TAC 2 source: source: source: ; clear pin AP2 which sets pin AN2 and clears pin BV2 TAPE BUS 2 OUTPUT source: 0 1 0 changed: 0 1 0 step 74 100000000000010000000000000000000000111101011011011010100110110111 source: ; set pin AF1 which clears pin BB2 and sets pin BR2 TAPE BUS 3 OUTPUT source: 1 0 1 changed: step 75 100000000000010000000000000000000000111101011011011010100110110111 source: ; load TAC from tape bus (01) source: 10110 changed: 101 step 76 100000000000010000000000000000000000111101011011011101100110110111 source: 0 changed: 0 step 77 100000000000010000000000000000000000111101011011011001100110110111 source: ; restore TAC 2 source: ; set pin AP2 which clears pin AN2 and sets pin BV2 TAPE BUS 2 OUTPUT source: 1 0 1 changed: 1 0 1 step 78 100000000000010010000000000000000000110111011011011001100110110111 source: ; load TAC from tape bus (11) source: 11010 changed: 110 step 79 100000000000010010000000000000000000110111011011011110100110110111 source: 0 changed: 0 step 80 100000000000010010000000000000000000110111011011011010100110110111 source: source: source: ; walk a 0, TAC 3 source: source: source: ; set pin AP2 which clears pin AN2 and sets pin BV2 TAPE BUS 2 OUTPUT source: 1 0 1 changed: step 81 100000000000010010000000000000000000110111011011011010100110110111 source: ; clear pin AF1 which sets pin BB2 and clears pin BR2 TAPE BUS 3 OUTPUT source: 0 1 0 changed: 0 1 0 step 82 100000000000000010000000000000000001110110011011011010100110110111 source: ; load TAC from tape bus (10) source: 11001 changed: 1 01 step 83 100000000000000010000000000000000001110110011011011110010110110111 source: 0 changed: 0 step 84 100000000000000010000000000000000001110110011011011010010110110111 source: ; restore TAC 3 source: ; set pin AF1 which clears pin BB2 and sets pin BR2 TAPE BUS 3 OUTPUT source: 1 0 1 changed: 1 0 1 step 85 100000000000010010000000000000000000110111011011011010010110110111 source: ; load TAC from tape bus (11) source: 11010 changed: 1 10 step 86 100000000000010010000000000000000000110111011011011110100110110111 source: 0 changed: 0 step 87 100000000000010010000000000000000000110111011011011010100110110111 source: source: source: ; walk a 0, TB 2 source: source: source: ; clear pin AP2 which sets pin AN2 and clears pin BV2 TAPE BUS 2 OUTPUT source: 0 1 0 changed: 0 1 0 step 88 100000000000010000000000000000000000111101011011011010100110110111 source: ; set pin AF1 which clears pin BB2 and sets pin BR2 TAPE BUS 3 OUTPUT source: 1 0 1 changed: step 89 100000000000010000000000000000000000111101011011011010100110110111 source: ; load TB from tape bus (01) source: 101 changed: 10 step 90 100000000000010000000000000000000000111101011011011010101010110111 source: 0 changed: 0 step 91 100000000000010000000000000000000000111101011011011010100010110111 source: ; restore TB 2 source: ; set pin AP2 which clears pin AN2 and sets pin BV2 TAPE BUS 2 OUTPUT source: 1 0 1 changed: 1 0 1 step 92 100000000000010010000000000000000000110111011011011010100010110111 source: ; load TB from tape bus (11) source: 111 changed: 11 step 93 100000000000010010000000000000000000110111011011011010101110110111 source: 0 changed: 0 step 94 100000000000010010000000000000000000110111011011011010100110110111 source: source: source: ; walk a 0, TB 3 source: source: source: ; set pin AP2 which clears pin AN2 and sets pin BV2 TAPE BUS 2 OUTPUT source: 1 0 1 changed: step 95 100000000000010010000000000000000000110111011011011010100110110111 source: ; clear pin AF1 which sets pin BB2 and clears pin BR2 TAPE BUS 3 OUTPUT source: 0 1 0 changed: 0 1 0 step 96 100000000000000010000000000000000001110110011011011010100110110111 source: ; load TB from tape bus (10) source: 110 changed: 1 0 step 97 100000000000000010000000000000000001110110011011011010101100110111 source: 0 changed: 0 step 98 100000000000000010000000000000000001110110011011011010100100110111 source: ; restore TB 3 source: ; set pin AF1 which clears pin BB2 and sets pin BR2 TAPE BUS 3 OUTPUT source: 1 0 1 changed: 1 0 1 step 99 100000000000010010000000000000000000110111011011011010100100110111 source: ; load TB from tape bus (11) source: 111 changed: 1 1 step 100 100000000000010010000000000000000000110111011011011010101110110111 source: 0 changed: 0 step 101 100000000000010010000000000000000000110111011011011010100110110111 SLOT BAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBAABBAAAAAAAAAAAAAABBBBBABBBB LETTER ALPSLFMDEEMCBFRSPKLEMFHRSCJLJKUHPNMBBNNVVRKRHUTDJUKANJHBTPDFSVEVDU SIDE 121212122121212121111111112212122222112222111221112112212112212122 DIRECTION IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIOOOOOOOIOOIOOIOOIOOOOIOOIIIIOOO source: source: source: source: source: source: source: source: source: source: source: source: source: source: source: source: source: source: source: source: source: source: ; load RWB from TB (JAMS CLEAR AND PRESET) source: 1 00 changed: 1 step 102 100000000000010010000000000000000000110111011011011010100111110111 fail ^^ space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C toggle comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT BAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBAABBAAAAAAAAAAAAAABBBBBABBBB LETTER ALPSLFMDEEMCBFRSPKLEMFHRSCJLJKUHPNMBBNNVVRKRHUTDJUKANJHBTPDFSVEVDU SIDE 121212122121212121111111112212122222112222111221112112212112212122 DIRECTION IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIOOOOOOOIOOIOOIOOIOOOOIOOIIIIOOO all fails OO was lo 00000000000000000000000000000000000 0 00000000000000000000 000 falling v v v v vvvvvvvvvvvvvvvvvvvv vv rising ^ ^ ^ ^ ^^^^^^^^^^^^^^^^^^^^ ^^ was hi 1 1 1 111111111111111111111111111 111 total fails 0, total passes 0 Main menu Thu Aug 20 18:51:51 2015 test file is: tests\m222.new delay is: 0 trigger is: 1 1 read test file 2 set test delay 3 set test trigger 4 run test 5 output loading test 8 diags 9 exit Enter test file name? trying to open test file: tests\m222.new reading test file: tests\m222.new comment: M222 PCB REV B SCHEMATIC REV A LINC TAPE REGISTERS comment: comment: TERMINOLOGY- SIGNALS REFER TO PDP12 MAINT VOL4 M222 SCHEMATIC. comment: comment: BUT... comment: comment: DEC USES AND-NOR GATES TO ROUTE THE ADDER A AND B INPUTS, SO... comment: DEC RENAMED THE ADDER TO NEGATIVE LOGIC TERMS (I.E. A-N + B-N + C-N -> SUM-N, C1-N). comment: (NOT THE 7482 DATASHEET NAMES OF A + B + C -> SUM, C1). comment: comment: SO, WITH ALL 'AND ENABLES' LOW, THE AND-NOR OUTPUTS = HIGH. comment: WITH C-L HIGH, THE ADDER OUTPUT IS SUM-N=1, C1-N=1; comment: THE INVERTED ADDER OUTPUT IS LOW (TAPE BUS). comment: AND THERE IS NO CARRY (C1-N IS HI). comment: comment: THE TWO ADDERS, TWO REGISTER BITS, ETC ARE LABELED BIT 2 (EVEN, MSB) AND BIT 3 (ODD, LSB). comment: THE ADDERS ARE REFERRED TO AS 'ADDER2' (MSB) AND 'ADDER3' (LSB). comment: comment: POWER PINS: comment: AA2 +5V comment: AT1 GROUND comment: AC2 GROUND comment: BA2 +5V comment: BT1 GROUND comment: BC2 GROUND comment: comment: (ALL PINS ARE USED). comment: comment: pins: PINS pins: 1 I BA1 CARRY IN-N, (TO E9-5 7482 C0) C-N TO ADDER2 pins: 2 I AL2 AND-NOR ENABLE: TAC TAC3 TO PIN BB2 (TO ADDER3) TAC2 TO PIN AN2 (TO ADDER2) pins: 3 I AP1 AND-NOR ENABLE: TMA SETUP (TMAS)3 TO PIN BB2 (TO ADDER3), (TMAS)3 TO PIN AN2 (TO ADDER2) pins: 4 I AS2 AND-NOR ENABLE: TMA TMA3 TO PIN BB2 (TO ADDER3), TMA2 TO PIN AN2 (TO ADDER2) pins: 5 I AL1 AND-NOR ENABLE: PIN AF2 TO PIN BB2 (TO ADDER3), PIN AM1 TO PIN AN2 (TO ADDER2) pins: 6 I AF2 AND-NOR INPUT (AL1 ENABLES) TO PIN BB2 (TO ADDER3). pins: 7 I AM1 AND-NOR INPUT (AL1 ENABLES) TO PIN AN2 (TO ADDER2) pins: 8 I AD2 AND-NOR ENABLE: RWB RWB3 TO PIN BB2 (TO ADDER3), RWB2 TO PIN AN2 (TO ADDER2) pins: 9 I AE2 AND-NOR ENABLE: PIN AE1 TO PIN BB2 (TO ADDER3), PIN AM2 TO PIN AN2 (TO ADDER2) pins: 10 I AE1 AND-NOR INPUT (AE2 ENABLES) TO PIN BB2 (TO ADDER3). pins: 11 I AM2 AND-NOR INPUT (AE2 ENABLES) TO PIN AN2 (TO ADDER2) pins: 12 I AC1 AND-NOR INPUT, AND WITH PIN AB2 TO PIN BB2 (TO ADDER3) pins: 13 I AB2 AND-NOR INPUT, AND WITH PIN AC1 TO PIN BB2 (TO ADDER3) pins: 14 I AF1 AND-NOR INPUT (AND WITH ITSELF) TO PIN BB2 (TO ADDER3) pins: 15 I AR2 AND-NOR INPUT, AND WITH PIN AS1 TO PIN AN2 (TO ADDER2) pins: 16 I AS1 AND-NOR INPUT, AND WITH PIN AR2 TO PIN AN2 (TO ADDER2) pins: 17 I AP2 AND-NOR INPUT (AND WITH ITSELF) TO PIN AN2 (TO ADDER2) pins: 18 I BK1 AND-NOR ENABLE: TB3 TO PIN BB1 (TO ADDER3), TB2 TO PIN BN1 (TO ADDER2) pins: 19 I BL1 AND-NOR ENABLE: PIN BE1 TO PIN BB1 (TO ADDER3), PIN BM1 TO PIN BN1 (TO ADDER2) pins: 20 I BE1 AND-NOR INPUT (BL1 ENABLES) TO PIN BB1 (TO ADDER3). pins: 21 I BM1 AND-NOR INPUT (BL1 ENABLES) TO PIN BN1 (TO ADDER2) pins: 22 I BF1 AND-NOR ENABLE: PIN BH1 TO PIN BB1 (TO ADDER3), PIN BR1 TO PIN BN1 (TO ADDER2) pins: 23 I BH1 AND-NOR INPUT (BF1 ENABLES): TO PIN BB1 (TO ADDER3), pins: 24 I BR1 AND-NOR INPUT (BF1 ENABLES): TO PIN BN1 (TO ADDER2) pins: 25 I BS1 AND-NOR ENABLE: PIN BC1 TO PIN BB1 (TO ADDER3), PIN BJ2 TO PIN BN1 (TO ADDER2) pins: 26 I BC1 AND-NOR INPUT (BS1 ENABLES): TO PIN BB1 (TO ADDER3), pins: 27 I BJ2 AND-NOR INPUT (BS1 ENABLES): TO PIN BN1 (TO ADDER2) pins: 28 I BL2 AND-NOR ENABLE: PIN BJ1 TO PIN BB1 (TO ADDER3), PIN BK2 TO PIN BN1 (TO ADDER2) pins: 29 I BJ1 AND-NOR INPUT (BL2 ENABLES): TO PIN BB1 (TO ADDER3), pins: 30 I BK2 AND-NOR INPUT (BL2 ENABLES): TO PIN BN1 (TO ADDER2) pins: 31 I BU1 AND-NOR ENABLE: PIN BH2 TO PIN BB1 (TO ADDER3), PIN BP2 TO PIN BN1 (TO ADDER2) pins: 32 I BH2 AND-NOR INPUT (BU1 ENABLES): TO PIN BB1 (TO ADDER3), pins: 33 I BP2 AND-NOR INPUT (BU1 ENABLES): TO PIN BN1 (TO ADDER2) pins: 34 I BN2 AND-NOR INPUT (AND WITH BM2): TO PIN BN1 (TO ADDER2) pins: 35 I BM2 AND-NOR INPUT (AND WITH BM2): TO PIN BN1 (TO ADDER2) pins: 36 O BB2 AND-NOR OUTPUT, (DRIVES E9-2 7482 A1) TO ADDER3 INPUT pins: 37 O BB1 AND-NOR OUTPUT, (DRIVES E9-3 7482 B1) TO ADDER3 INPUT pins: 38 O BN1 AND-NOR OUTPUT, (DRIVES E9-14 7482 A2) TO ADDER2 INPUT pins: 39 O AN2 AND-NOR OUTPUT, (DRIVES E9-13 7482 B2) TO ADDER2 INPUT pins: 40 O AV2 CARRY OUT-N (E9-10 7482 C2) pins: 41 O BV2 TAPE BUS 2 OUTPUT (INVERTED ADDER2 SUM-N (E9-12 7482 SUM2) pins: 42 O BR2 TAPE BUS 3 OUTPUT (INVERTED ADDER3 SUM-N (E9-1 7482 SUM1) pins: 43 I AK1 LOAD TMA SETUP (FROM TAPE BUS) (RISING EDGE CLOCK) pins: 44 O AR1 TMA SETUP 2 pins: 45 O AH1 TMA SETUP 3 pins: 46 I AU2 LOAD TMA (FROM TAPE BUS) (RISING EDGE CLOCK) pins: 47 O AT2 TMA 2 pins: 48 O AD1 TMA 3 pins: 49 I AJ1 LOAD TBN (FROM TAPE BUS) (RISING EDGE CLOCK) pins: 50 O AU1 TBN 2 pins: 51 O AK2 TBN 3 pins: 52 I AA1 LOAD TAC (FROM TAPE BUS) (RISING EDGE CLOCK) pins: 53 O AN1 TAC 2 pins: 54 O AJ2 TAC 2-N pins: 55 O AH2 TAC 3 pins: 56 O AB1 TAC 3-N pins: 57 I BT2 LOAD TB (FROM TAPE BUS) (RISING EDGE CLOCK) pins: 58 O BP1 TB 2 pins: 59 O BD1 TB 3 pins: 60 I BF2 LOAD RWB (FROM TB) (JAMS CLEAR,SET) pins: 61 I BS2 PHASE (SELECTS POLARITY OF RWB OUT, 0 -> INVERTED) pins: 62 I AV1 RWB IN (SHIFTED INTO RWB 3) pins: 63 I BE2 SHIFT RWB (SHIFTS PIN AV1 INTO RWB 3, SHIFTS RWB3 TO RWB2) (RISING CLOCK) pins: 64 O BV1 RWB OUT (IF PHASE=1, =RWB 2; IF PHASE=0; =RWB 2-N) pins: 65 O BD2 RWB 3 pins: 66 O BU2 +3.5V pins: direction: IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIOOOOOOOIOOIOOIOOIOOOOIOOIIIIOOO comment: ; all registers are unknown comment: ; turn on C0, PHASE comment: ; with no ENABLES, BUS2,BUS3 is 11, C2 is 1 test 1: 1000000000000000000000000000000000011111000XX0XX0XX0XXXX0XX0110XX1 comment: comment: ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; comment: ; comment: ; set all registers LOW comment: ; comment: ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; comment: comment: ; load TMA SETUP from tape bus (00) test 2: 100 test 3: 0 comment: ; load TMA from tape bus (00) test 4: 100 test 5: 0 comment: ; load TBN from tape bus (00) test 6: 100 test 7: 0 comment: ; load TAC from tape bus (00) test 8: 10101 test 9: 0 comment: ; load TB from tape bus (00) test 10: 100 test 11: 0 comment: ; load RWB from TB (JAMS CLEAR AND PRESET) test 12: 1 00 test 13: 0 comment: ; (no change) test 14: 100000000000000000000000000000000001111100000000000001010000110001 comment: comment: comment: ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; comment: ; comment: ; set all registers HIGH comment: ; comment: ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; comment: comment: ; set pin AF1 which clears pin BB2 and sets pin BR2 TAPE BUS 3 OUTPUT test 15: 1 0 1 comment: ; set pin AP2 which clears pin AN2 and sets pin BV2 TAPE BUS 2 OUTPUT test 16: 1 0 1 comment: comment: comment: ; load TMA SETUP from tape bus (11) test 17: 111 test 18: 0 comment: ; load TMA from tape bus (11) test 19: 111 test 20: 0 comment: ; load TBN from tape bus (11) test 21: 111 test 22: 0 comment: ; load TAC from tape bus (11) test 23: 11010 test 24: 0 comment: ; load TB from tape bus (11) test 25: 111 test 26: 0 comment: ; load RWB from TB (JAMS CLEAR AND PRESET) test 27: 1 11 test 28: 0 comment: ; clear pin AF1 (AND with itself) to set pin BB2 (AND-NOR output) and clear pin BR2 TAPE BUS 3 OUTPUT test 29: 0 1 0 comment: ; clear pin AP2 (AND with itself) to set pin AN2 (AND-NOR output) and clear pin BV2 TAPE BUS 2 OUTPUT test 30: 0 1 0 comment: ; (no change) test 31: 100000000000000000000000000000000001111100011011011010100110110111 comment: comment: ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; comment: ; comment: ; will all registers high, walk a 0 comment: ; comment: ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; comment: comment: comment: ; walk a 0, TMA SETUP 2 comment: comment: comment: ; clear pin AP2 which sets pin AN2 and clears pin BV2 TAPE BUS 2 OUTPUT test 32: 0 1 0 comment: ; set pin AF1 which clears pin BB2 and sets pin BR2 TAPE BUS 3 OUTPUT test 33: 1 0 1 comment: ; load TMA SETUP from tape bus (01) test 34: 101 test 35: 0 comment: ; restore TMA SETUP 2 comment: ; set pin AP2 which clears pin AN2 and sets pin BV2 TAPE BUS 2 OUTPUT test 36: 1 0 1 comment: ; load TMA SETUP from tape bus (11) test 37: 111 test 38: 0 comment: comment: comment: ; walk a 0, TMA SETUP 3 comment: comment: comment: ; set pin AP2 which clears pin AN2 and sets pin BV2 TAPE BUS 2 OUTPUT test 39: 1 0 1 comment: ; clear pin AF1 which sets pin BB2 and clears pin BR2 TAPE BUS 3 OUTPUT test 40: 0 1 0 comment: ; load TMA SETUP from tape bus (10) test 41: 110 test 42: 0 comment: ; restore TMA SETUP 3 comment: ; set pin AF1 which clears pin BB2 and sets pin BR2 TAPE BUS 3 OUTPUT test 43: 1 0 1 comment: ; load TMA SETUP from tape bus (11) test 44: 111 test 45: 0 comment: comment: comment: ; walk a 0, TMA 2 comment: comment: comment: ; clear pin AP2 which sets pin AN2 and clears pin BV2 TAPE BUS 2 OUTPUT test 46: 0 1 0 comment: ; set pin AF1 which clears pin BB2 and sets pin BR2 TAPE BUS 3 OUTPUT test 47: 1 0 1 comment: ; load TMA from tape bus (01) test 48: 101 test 49: 0 comment: ; restore TMA 2 comment: ; set pin AP2 which clears pin AN2 and sets pin BV2 TAPE BUS 2 OUTPUT test 50: 1 0 1 comment: ; load TMA from tape bus (11) test 51: 111 test 52: 0 comment: comment: comment: ; walk a 0, TMA 3 comment: comment: comment: ; set pin AP2 which clears pin AN2 and sets pin BV2 TAPE BUS 2 OUTPUT test 53: 1 0 1 comment: ; clear pin AF1 which sets pin BB2 and clears pin BR2 TAPE BUS 3 OUTPUT test 54: 0 1 0 comment: ; load TMA from tape bus (10) test 55: 110 test 56: 0 comment: ; restore TMA 3 comment: ; set pin AF1 which clears pin BB2 and sets pin BR2 TAPE BUS 3 OUTPUT test 57: 1 0 1 comment: ; load TMA from tape bus (11) test 58: 111 test 59: 0 comment: comment: comment: ; walk a 0, TBN 2 comment: comment: comment: ; clear pin AP2 which sets pin AN2 and clears pin BV2 TAPE BUS 2 OUTPUT test 60: 0 1 0 comment: ; set pin AF1 which clears pin BB2 and sets pin BR2 TAPE BUS 3 OUTPUT test 61: 1 0 1 comment: ; load TBN from tape bus (01) test 62: 101 test 63: 0 comment: ; restore TBN 2 comment: ; set pin AP2 which clears pin AN2 and sets pin BV2 TAPE BUS 2 OUTPUT test 64: 1 0 1 comment: ; load TBN from tape bus (11) test 65: 111 test 66: 0 comment: comment: comment: ; walk a 0, TBN 3 comment: comment: comment: ; set pin AP2 which clears pin AN2 and sets pin BV2 TAPE BUS 2 OUTPUT test 67: 1 0 1 comment: ; clear pin AF1 which sets pin BB2 and clears pin BR2 TAPE BUS 3 OUTPUT test 68: 0 1 0 comment: ; load TBN from tape bus (10) test 69: 110 test 70: 0 comment: ; restore TBN 3 comment: ; set pin AF1 which clears pin BB2 and sets pin BR2 TAPE BUS 3 OUTPUT test 71: 1 0 1 comment: ; load TBN from tape bus (11) test 72: 111 test 73: 0 comment: comment: comment: ; walk a 0, TAC 2 comment: comment: comment: ; clear pin AP2 which sets pin AN2 and clears pin BV2 TAPE BUS 2 OUTPUT test 74: 0 1 0 comment: ; set pin AF1 which clears pin BB2 and sets pin BR2 TAPE BUS 3 OUTPUT test 75: 1 0 1 comment: ; load TAC from tape bus (01) test 76: 10110 test 77: 0 comment: ; restore TAC 2 comment: ; set pin AP2 which clears pin AN2 and sets pin BV2 TAPE BUS 2 OUTPUT test 78: 1 0 1 comment: ; load TAC from tape bus (11) test 79: 11010 test 80: 0 comment: comment: comment: ; walk a 0, TAC 3 comment: comment: comment: ; set pin AP2 which clears pin AN2 and sets pin BV2 TAPE BUS 2 OUTPUT test 81: 1 0 1 comment: ; clear pin AF1 which sets pin BB2 and clears pin BR2 TAPE BUS 3 OUTPUT test 82: 0 1 0 comment: ; load TAC from tape bus (10) test 83: 11001 test 84: 0 comment: ; restore TAC 3 comment: ; set pin AF1 which clears pin BB2 and sets pin BR2 TAPE BUS 3 OUTPUT test 85: 1 0 1 comment: ; load TAC from tape bus (11) test 86: 11010 test 87: 0 comment: comment: comment: ; walk a 0, TB 2 comment: comment: comment: ; clear pin AP2 which sets pin AN2 and clears pin BV2 TAPE BUS 2 OUTPUT test 88: 0 1 0 comment: ; set pin AF1 which clears pin BB2 and sets pin BR2 TAPE BUS 3 OUTPUT test 89: 1 0 1 comment: ; load TB from tape bus (01) test 90: 101 test 91: 0 comment: ; restore TB 2 comment: ; set pin AP2 which clears pin AN2 and sets pin BV2 TAPE BUS 2 OUTPUT test 92: 1 0 1 comment: ; load TB from tape bus (11) test 93: 111 test 94: 0 comment: comment: comment: ; walk a 0, TB 3 comment: comment: comment: ; set pin AP2 which clears pin AN2 and sets pin BV2 TAPE BUS 2 OUTPUT test 95: 1 0 1 comment: ; clear pin AF1 which sets pin BB2 and clears pin BR2 TAPE BUS 3 OUTPUT test 96: 0 1 0 comment: ; load TB from tape bus (10) test 97: 110 test 98: 0 comment: ; restore TB 3 comment: ; set pin AF1 which clears pin BB2 and sets pin BR2 TAPE BUS 3 OUTPUT test 99: 1 0 1 comment: ; load TB from tape bus (11) test 100: 111 test 101: 0 comment: comment: comment: ; walk a 0, RWB 2 comment: comment: comment: ; clear pin AP2 which sets pin AN2 and clears pin BV2 TAPE BUS 2 OUTPUT test 102: 0 1 0 comment: ; set pin AF1 which clears pin BB2 and sets pin BR2 TAPE BUS 3 OUTPUT test 103: 1 0 1 comment: ; load TB from tape bus (01) test 104: 101 test 105: 0 comment: ; load RWB from TB (JAMS CLEAR AND PRESET) test 106: 1 01 test 107: 0 comment: ; restore TB 2 and RWB 2 comment: ; set pin AP2 which clears pin AN2 and sets pin BV2 TAPE BUS 2 OUTPUT test 108: 1 0 1 comment: ; load TB from tape bus (11) test 109: 111 test 110: 0 comment: ; load RWB from TB (JAMS CLEAR AND PRESET) test 111: 1 11 test 112: 0 comment: comment: comment: ; walk a 0, RWB 3 comment: comment: comment: ; set pin AP2 which clears pin AN2 and sets pin BV2 TAPE BUS 2 OUTPUT test 113: 1 0 1 comment: ; clear pin AF1 which sets pin BB2 and clears pin BR2 TAPE BUS 3 OUTPUT test 114: 0 1 0 comment: ; load TB from tape bus (10) test 115: 110 test 116: 0 comment: ; load RWB from TB (JAMS CLEAR AND PRESET) test 117: 1 10 test 118: 0 comment: ; restore TB 3 and RWB 3 comment: ; set pin AF1 which clears pin BB2 and sets pin BR2 TAPE BUS 3 OUTPUT test 119: 1 0 1 comment: ; load TB from tape bus (11) test 120: 111 test 121: 0 comment: ; load RWB from TB (JAMS CLEAR AND PRESET) test 122: 1 11 test 123: 0 comment: comment: comment: ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; comment: ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; comment: ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; comment: ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; comment: ;********************* need to walk a one ********************** comment: ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; comment: ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; comment: ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; comment: ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; comment: comment: ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; comment: ; comment: ; test AND-NOR logic comment: ; comment: ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; comment: comment: ; (all registers are HIGH) comment: ; set all pins HIGH except ENABLES comment: comment: ; set pin AF2 HIGH test 124: 1 comment: ; set pin AM1 HIGH test 125: 1 comment: ; set pin AE1 HIGH test 126: 1 comment: ; set pin AM2 HIGH test 127: 1 comment: ; set pin AB2 HIGH test 128: 1 comment: ; set pin AS1 HIGH test 129: 1 comment: ; set pin BE1 HIGH test 130: 1 comment: ; set pin BM1 HIGH test 131: 1 comment: ; set pin BH1 HIGH test 132: 1 comment: ; set pin BR1 HIGH test 133: 1 comment: ; set pin BC1 HIGH test 134: 1 comment: ; set pin BJ2 HIGH test 135: 1 comment: ; set pin BJ1 HIGH test 136: 1 comment: ; set pin BK2 HIGH test 137: 1 comment: ; set pin BH2 HIGH test 138: 1 comment: ; set pin BP2 HIGH test 139: 1 comment: ; set pin BN2 HIGH test 140: 1 comment: ; toggle each ENABLE comment: comment: ; set pin AL2 to clear pin BB2 and pin AN2 AND-NOR OUTPUTS and set TAPE BUS 2 OUTPUT and TAPE BUS 3 OUTPUT test 141: 1 0 0 11 test 142: 0 1 1 00 comment: ; set pin AP1 to clear pin BB2 and pin AN2 AND-NOR OUTPUTS and set TAPE BUS 2 OUTPUT and TAPE BUS 3 OUTPUT test 143: 1 0 0 11 test 144: 0 1 1 00 comment: ; set pin AS2 to clear pin BB2 and pin AN2 AND-NOR OUTPUTS and set TAPE BUS 2 OUTPUT and TAPE BUS 3 OUTPUT test 145: 1 0 0 11 test 146: 0 1 1 00 comment: ; set pin AL1 to clear pin BB2 and pin AN2 AND-NOR OUTPUTS and set TAPE BUS 2 OUTPUT and TAPE BUS 3 OUTPUT test 147: 1 0 0 11 test 148: 0 1 1 00 comment: ; set pin AL1 to clear pin BB2 and pin AN2 AND-NOR OUTPUTS and set TAPE BUS 2 OUTPUT and TAPE BUS 3 OUTPUT test 149: 1 0 0 11 test 150: 0 1 1 00 comment: ; set pin AE2 to clear pin BB2 and pin AN2 AND-NOR OUTPUTS and set TAPE BUS 2 OUTPUT and TAPE BUS 3 OUTPUT test 151: 1 0 0 11 test 152: 0 1 1 00 comment: ; set pin AC1 to clear pin BB2 and set TAPE BUS 3 OUTPUT test 153: 1 0 1 test 154: 0 1 0 comment: ; set pin AF1 to clear pin BB2 and set TAPE BUS 3 OUTPUT test 155: 1 0 1 test 156: 0 1 0 comment: ; set pin AR2 to clear pin AN2 AND-NOR OUTPUTS and set TAPE BUS 2 OUTPUT test 157: 1 0 1 test 158: 0 1 0 comment: ; set pin AP2 to clear pin AN2 AND-NOR OUTPUTS and set TAPE BUS 2 OUTPUT test 159: 1 0 1 test 160: 0 1 0 comment: comment: ; set pin BK1 to clear pin BB1 and pin BN1 AND-NOR OUTPUTS and set TAPE BUS 2 OUTPUT and TAPE BUS 3 OUTPUT test 161: 1 00 11 test 162: 0 11 00 comment: ; set pin BL1 to clear pin BB1 and pin BN1 AND-NOR OUTPUTS and set TAPE BUS 2 OUTPUT and TAPE BUS 3 OUTPUT test 163: 1 00 11 test 164: 0 11 00 comment: ; set pin BF1 to clear pin BB1 and pin BN1 AND-NOR OUTPUTS and set TAPE BUS 2 OUTPUT and TAPE BUS 3 OUTPUT test 165: 1 00 11 test 166: 0 11 00 comment: ; set pin BS1 to clear pin BB1 and pin BN1 AND-NOR OUTPUTS and set TAPE BUS 2 OUTPUT and TAPE BUS 3 OUTPUT test 167: 1 00 11 test 168: 0 11 00 comment: ; set pin BL2 to clear pin BB1 and pin BN1 AND-NOR OUTPUTS and set TAPE BUS 2 OUTPUT and TAPE BUS 3 OUTPUT test 169: 1 00 11 test 170: 0 11 00 comment: ; set pin BU1 to clear pin BB1 and pin BN1 AND-NOR OUTPUTS and set TAPE BUS 2 OUTPUT and TAPE BUS 3 OUTPUT test 171: 1 00 11 test 172: 0 11 00 comment: ; set pin BM2 to clear pin BB1 and TAPE BUS 3 OUTPUT test 173: 1 0 1 test 174: 0 1 0 comment: ; no change test 175: 100000000000000000000000000000000001111100011011011010100110110111 comment: comment: ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; comment: ; test shifting the RWB comment: ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; comment: comment: ; shift in 0, expect 10 test 176: 0 test 177: 110 test 178: 0 comment: ; toggle phase should toggle RWB 2 test 179: 0 0 test 180: 1 1 comment: comment: ; shift in 0, expect 00 test 181: 0 test 182: 100 test 183: 0 comment: ; toggle phase should toggle RWB 2 test 184: 0 1 test 185: 1 0 comment: comment: ; shift in 0, expect 00 test 186: 0 test 187: 100 test 188: 0 comment: ; shift in 1, expect 01 test 189: 1 test 190: 101 test 191: 0 comment: ; shift in 1, expect 11 test 192: 1 test 193: 111 test 194: 0 comment: ; shift in 1, expect 11 test 195: 1 test 196: 111 test 197: 0 comment: ; shift in 0, expect 10 test 198: 0 test 199: 110 test 200: 0 comment: ; shift in 1, expect 01 test 201: 1 test 202: 101 test 203: 0 comment: ; shift in 0, expect 10 test 204: 0 test 205: 110 test 206: 0 comment: ; shift in 1, expect 01 test 207: 1 test 208: 101 test 209: 0 comment: ; shift in 1, expect 11 test 210: 1 test 211: 111 test 212: 0 comment: ; no change test 213: 100000000000000000000000000000000001111100011011011010100110110111 comment: comment: ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; comment: ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; comment: ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; comment: ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; comment: ; needs work (more adder tests, more register tests) comment: ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; comment: ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; comment: ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; comment: ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; end: END summary column 1: offset 2, mask 0x2000 column 2: offset 1, mask 0x0002 column 3: offset 1, mask 0x0800 column 4: offset 1, mask 0x0040 column 5: offset 1, mask 0x4000 column 6: offset 0, mask 0x0004 column 7: offset 1, mask 0x2000 column 8: offset 0, mask 0x0010 column 9: offset 0, mask 0x0008 column 10: offset 0, mask 0x0800 column 11: offset 1, mask 0x0004 column 12: offset 0, mask 0x2000 column 13: offset 0, mask 0x0040 column 14: offset 0, mask 0x0400 column 15: offset 1, mask 0x0020 column 16: offset 1, mask 0x0200 column 17: offset 1, mask 0x0010 column 18: offset 3, mask 0x2000 column 19: offset 3, mask 0x1000 column 20: offset 2, mask 0x0200 column 21: offset 3, mask 0x0800 column 22: offset 2, mask 0x0100 column 23: offset 3, mask 0x8000 column 24: offset 3, mask 0x0100 column 25: offset 4, mask 0x8000 column 26: offset 2, mask 0x0800 column 27: offset 3, mask 0x0002 column 28: offset 3, mask 0x0008 column 29: offset 3, mask 0x4000 column 30: offset 3, mask 0x0004 column 31: offset 4, mask 0x2000 column 32: offset 3, mask 0x0001 column 33: offset 3, mask 0x0040 column 34: offset 3, mask 0x0020 column 35: offset 3, mask 0x0010 column 36: offset 2, mask 0x0008 column 37: offset 2, mask 0x1000 column 38: offset 3, mask 0x0400 column 39: offset 1, mask 0x0008 column 40: offset 2, mask 0x0002 column 41: offset 4, mask 0x0008 column 42: offset 3, mask 0x0080 column 43: offset 1, mask 0x8000 column 44: offset 1, mask 0x0400 column 45: offset 0, mask 0x0200 column 46: offset 2, mask 0x0001 column 47: offset 1, mask 0x0080 column 48: offset 0, mask 0x1000 column 49: offset 0, mask 0x0100 column 50: offset 2, mask 0x8000 column 51: offset 1, mask 0x0001 column 52: offset 0, mask 0x8000 column 53: offset 1, mask 0x1000 column 54: offset 0, mask 0x0001 column 55: offset 0, mask 0x0002 column 56: offset 0, mask 0x4000 column 57: offset 4, mask 0x0002 column 58: offset 3, mask 0x0200 column 59: offset 2, mask 0x0400 column 60: offset 2, mask 0x0080 column 61: offset 4, mask 0x0001 column 62: offset 2, mask 0x4000 column 63: offset 2, mask 0x0040 column 64: offset 4, mask 0x1000 column 65: offset 2, mask 0x0020 column 66: offset 4, mask 0x0004 direction bits (1=input) 0x52A3 0x1589 0x943A 0x0680 0x50FC pullup bits (1=pullup) 0x0000 0x0000 0x0000 0x0000 0x0000 test step out_data dont care 1: 0x0000 0x0008 0x700A 0x0400 0x0005 0x5203 0x1481 0x8420 0x0200 0x1000 2: 0x0000 0x8008 0x700A 0x0400 0x0005 0x5003 0x1081 0x8420 0x0200 0x1000 3: 0x0000 0x0008 0x700A 0x0400 0x0005 0x5003 0x1081 0x8420 0x0200 0x1000 4: 0x0000 0x0008 0x700B 0x0400 0x0005 0x4003 0x1001 0x8420 0x0200 0x1000 5: 0x0000 0x0008 0x700A 0x0400 0x0005 0x4003 0x1001 0x8420 0x0200 0x1000 6: 0x0100 0x0008 0x700A 0x0400 0x0005 0x4003 0x1000 0x0420 0x0200 0x1000 7: 0x0000 0x0008 0x700A 0x0400 0x0005 0x4003 0x1000 0x0420 0x0200 0x1000 8: 0xC001 0x0008 0x700A 0x0400 0x0005 0x0000 0x0000 0x0420 0x0200 0x1000 9: 0x4001 0x0008 0x700A 0x0400 0x0005 0x0000 0x0000 0x0420 0x0200 0x1000 10: 0x4001 0x0008 0x700A 0x0400 0x0007 0x0000 0x0000 0x0020 0x0000 0x1000 11: 0x4001 0x0008 0x700A 0x0400 0x0005 0x0000 0x0000 0x0020 0x0000 0x1000 12: 0x4001 0x0008 0x708A 0x0400 0x0005 13: 0x4001 0x0008 0x700A 0x0400 0x0005 14: 0x4001 0x0008 0x700A 0x0400 0x0005 15: 0x4401 0x0008 0x7002 0x0480 0x0005 16: 0x4401 0x0010 0x7002 0x0480 0x000D 17: 0x4601 0x8410 0x7002 0x0480 0x000D 18: 0x4601 0x0410 0x7002 0x0480 0x000D 19: 0x5601 0x0490 0x7003 0x0480 0x000D 20: 0x5601 0x0490 0x7002 0x0480 0x000D 21: 0x5701 0x0491 0xF002 0x0480 0x000D 22: 0x5601 0x0491 0xF002 0x0480 0x000D 23: 0x9602 0x1491 0xF002 0x0480 0x000D 24: 0x1602 0x1491 0xF002 0x0480 0x000D 25: 0x1602 0x1491 0xF402 0x0680 0x000F 26: 0x1602 0x1491 0xF402 0x0680 0x000D 27: 0x1602 0x1491 0xF4A2 0x0680 0x100D 28: 0x1602 0x1491 0xF422 0x0680 0x100D 29: 0x1202 0x1491 0xF42A 0x0600 0x100D 30: 0x1202 0x1489 0xF42A 0x0600 0x1005 31: 0x1202 0x1489 0xF42A 0x0600 0x1005 32: 0x1202 0x1489 0xF42A 0x0600 0x1005 33: 0x1602 0x1489 0xF422 0x0680 0x1005 34: 0x1602 0x9089 0xF422 0x0680 0x1005 35: 0x1602 0x1089 0xF422 0x0680 0x1005 36: 0x1602 0x1091 0xF422 0x0680 0x100D 37: 0x1602 0x9491 0xF422 0x0680 0x100D 38: 0x1602 0x1491 0xF422 0x0680 0x100D 39: 0x1602 0x1491 0xF422 0x0680 0x100D 40: 0x1202 0x1491 0xF42A 0x0600 0x100D 41: 0x1002 0x9491 0xF42A 0x0600 0x100D 42: 0x1002 0x1491 0xF42A 0x0600 0x100D 43: 0x1402 0x1491 0xF422 0x0680 0x100D 44: 0x1602 0x9491 0xF422 0x0680 0x100D 45: 0x1602 0x1491 0xF422 0x0680 0x100D 46: 0x1602 0x1489 0xF422 0x0680 0x1005 47: 0x1602 0x1489 0xF422 0x0680 0x1005 48: 0x1602 0x1409 0xF423 0x0680 0x1005 49: 0x1602 0x1409 0xF422 0x0680 0x1005 50: 0x1602 0x1411 0xF422 0x0680 0x100D 51: 0x1602 0x1491 0xF423 0x0680 0x100D 52: 0x1602 0x1491 0xF422 0x0680 0x100D 53: 0x1602 0x1491 0xF422 0x0680 0x100D 54: 0x1202 0x1491 0xF42A 0x0600 0x100D 55: 0x0202 0x1491 0xF42B 0x0600 0x100D 56: 0x0202 0x1491 0xF42A 0x0600 0x100D 57: 0x0602 0x1491 0xF422 0x0680 0x100D 58: 0x1602 0x1491 0xF423 0x0680 0x100D 59: 0x1602 0x1491 0xF422 0x0680 0x100D 60: 0x1602 0x1489 0xF422 0x0680 0x1005 61: 0x1602 0x1489 0xF422 0x0680 0x1005 62: 0x1702 0x1489 0x7422 0x0680 0x1005 63: 0x1602 0x1489 0x7422 0x0680 0x1005 64: 0x1602 0x1491 0x7422 0x0680 0x100D 65: 0x1702 0x1491 0xF422 0x0680 0x100D 66: 0x1602 0x1491 0xF422 0x0680 0x100D 67: 0x1602 0x1491 0xF422 0x0680 0x100D 68: 0x1202 0x1491 0xF42A 0x0600 0x100D 69: 0x1302 0x1490 0xF42A 0x0600 0x100D 70: 0x1202 0x1490 0xF42A 0x0600 0x100D 71: 0x1602 0x1490 0xF422 0x0680 0x100D 72: 0x1702 0x1491 0xF422 0x0680 0x100D 73: 0x1602 0x1491 0xF422 0x0680 0x100D 74: 0x1602 0x1489 0xF422 0x0680 0x1005 75: 0x1602 0x1489 0xF422 0x0680 0x1005 76: 0x9603 0x0489 0xF422 0x0680 0x1005 77: 0x1603 0x0489 0xF422 0x0680 0x1005 78: 0x1603 0x0491 0xF422 0x0680 0x100D 79: 0x9602 0x1491 0xF422 0x0680 0x100D 80: 0x1602 0x1491 0xF422 0x0680 0x100D 81: 0x1602 0x1491 0xF422 0x0680 0x100D 82: 0x1202 0x1491 0xF42A 0x0600 0x100D 83: 0xD200 0x1491 0xF42A 0x0600 0x100D 84: 0x5200 0x1491 0xF42A 0x0600 0x100D 85: 0x5600 0x1491 0xF422 0x0680 0x100D 86: 0x9602 0x1491 0xF422 0x0680 0x100D 87: 0x1602 0x1491 0xF422 0x0680 0x100D 88: 0x1602 0x1489 0xF422 0x0680 0x1005 89: 0x1602 0x1489 0xF422 0x0680 0x1005 90: 0x1602 0x1489 0xF422 0x0480 0x1007 91: 0x1602 0x1489 0xF422 0x0480 0x1005 92: 0x1602 0x1491 0xF422 0x0480 0x100D 93: 0x1602 0x1491 0xF422 0x0680 0x100F 94: 0x1602 0x1491 0xF422 0x0680 0x100D 95: 0x1602 0x1491 0xF422 0x0680 0x100D 96: 0x1202 0x1491 0xF42A 0x0600 0x100D 97: 0x1202 0x1491 0xF02A 0x0600 0x100F 98: 0x1202 0x1491 0xF02A 0x0600 0x100D 99: 0x1602 0x1491 0xF022 0x0680 0x100D 100: 0x1602 0x1491 0xF422 0x0680 0x100F 101: 0x1602 0x1491 0xF422 0x0680 0x100D 102: 0x1602 0x1489 0xF422 0x0680 0x1005 103: 0x1602 0x1489 0xF422 0x0680 0x1005 104: 0x1602 0x1489 0xF422 0x0480 0x1007 105: 0x1602 0x1489 0xF422 0x0480 0x1005 106: 0x1602 0x1489 0xF4A2 0x0480 0x0005 107: 0x1602 0x1489 0xF422 0x0480 0x0005 108: 0x1602 0x1491 0xF422 0x0480 0x000D 109: 0x1602 0x1491 0xF422 0x0680 0x000F 110: 0x1602 0x1491 0xF422 0x0680 0x000D 111: 0x1602 0x1491 0xF4A2 0x0680 0x100D 112: 0x1602 0x1491 0xF422 0x0680 0x100D 113: 0x1602 0x1491 0xF422 0x0680 0x100D 114: 0x1202 0x1491 0xF42A 0x0600 0x100D 115: 0x1202 0x1491 0xF02A 0x0600 0x100F 116: 0x1202 0x1491 0xF02A 0x0600 0x100D 117: 0x1202 0x1491 0xF08A 0x0600 0x100D 118: 0x1202 0x1491 0xF00A 0x0600 0x100D 119: 0x1602 0x1491 0xF002 0x0680 0x100D 120: 0x1602 0x1491 0xF402 0x0680 0x100F 121: 0x1602 0x1491 0xF402 0x0680 0x100D 122: 0x1602 0x1491 0xF4A2 0x0680 0x100D 123: 0x1602 0x1491 0xF422 0x0680 0x100D 124: 0x1606 0x1491 0xF422 0x0680 0x100D 125: 0x1606 0x3491 0xF422 0x0680 0x100D 126: 0x1E06 0x3491 0xF422 0x0680 0x100D 127: 0x1E06 0x3495 0xF422 0x0680 0x100D 128: 0x1E46 0x3495 0xF422 0x0680 0x100D 129: 0x1E46 0x3695 0xF422 0x0680 0x100D 130: 0x1E46 0x3695 0xF622 0x0680 0x100D 131: 0x1E46 0x3695 0xF622 0x0E80 0x100D 132: 0x1E46 0x3695 0xF622 0x8E80 0x100D 133: 0x1E46 0x3695 0xF622 0x8F80 0x100D 134: 0x1E46 0x3695 0xFE22 0x8F80 0x100D 135: 0x1E46 0x3695 0xFE22 0x8F82 0x100D 136: 0x1E46 0x3695 0xFE22 0xCF82 0x100D 137: 0x1E46 0x3695 0xFE22 0xCF86 0x100D 138: 0x1E46 0x3695 0xFE22 0xCF87 0x100D 139: 0x1E46 0x3695 0xFE22 0xCFC7 0x100D 140: 0x1E46 0x3695 0xFE22 0xCFE7 0x100D 141: 0x1E46 0x3697 0xFE22 0xCFE7 0x100D 142: 0x1E46 0x369D 0xFE2A 0xCF67 0x1005 143: 0x1E46 0x3E95 0xFE22 0xCFE7 0x100D 144: 0x1E46 0x369D 0xFE2A 0xCF67 0x1005 145: 0x1E46 0x36D5 0xFE22 0xCFE7 0x100D 146: 0x1E46 0x369D 0xFE2A 0xCF67 0x1005 147: 0x1E46 0x7695 0xFE22 0xCFE7 0x100D 148: 0x1E46 0x369D 0xFE2A 0xCF67 0x1005 149: 0x1E56 0x3695 0xFE22 0xCFE7 0x100D 150: 0x1E46 0x369D 0xFE2A 0xCF67 0x1005 151: 0x1E4E 0x3695 0xFE22 0xCFE7 0x100D 152: 0x1E46 0x369D 0xFE2A 0xCF67 0x1005 153: 0x3E46 0x369D 0xFE22 0xCFE7 0x1005 154: 0x1E46 0x369D 0xFE2A 0xCF67 0x1005 155: 0x1E46 0x369D 0xFE22 0xCFE7 0x1005 156: 0x1A46 0x369D 0xFE2A 0xCF67 0x1005 157: 0x1A46 0x36B5 0xFE2A 0xCF67 0x100D 158: 0x1A46 0x369D 0xFE2A 0xCF67 0x1005 159: 0x1A46 0x3695 0xFE2A 0xCF67 0x100D 160: 0x1A46 0x368D 0xFE2A 0xCF67 0x1005 161: 0x1A46 0x368D 0xEE2A 0xEBE7 0x100D 162: 0x1A46 0x368D 0xFE2A 0xCF67 0x1005 163: 0x1A46 0x368D 0xEE2A 0xDBE7 0x100D 164: 0x1A46 0x368D 0xFE2A 0xCF67 0x1005 165: 0x1A46 0x368D 0xEF2A 0xCBE7 0x100D 166: 0x1A46 0x368D 0xFE2A 0xCF67 0x1005 167: 0x1A46 0x368D 0xEE2A 0xCBE7 0x900D 168: 0x1A46 0x368D 0xFE2A 0xCF67 0x1005 169: 0x1A46 0x368D 0xEE2A 0xCBEF 0x100D 170: 0x1A46 0x368D 0xFE2A 0xCF67 0x1005 171: 0x1A46 0x368D 0xEE2A 0xCBE7 0x300D 172: 0x1A46 0x368D 0xFE2A 0xCF67 0x1005 173: 0x1A46 0x368D 0xFE2A 0xCB77 0x100D 174: 0x1A46 0x368D 0xFE2A 0xCF67 0x1005 175: 0x1202 0x1489 0xF42A 0x0600 0x1005 176: 0x1202 0x1489 0xB42A 0x0600 0x1005 177: 0x1202 0x1489 0xB44A 0x0600 0x1005 178: 0x1202 0x1489 0xB40A 0x0600 0x1005 179: 0x1202 0x1489 0xB40A 0x0600 0x0004 180: 0x1202 0x1489 0xB40A 0x0600 0x1005 181: 0x1202 0x1489 0xB40A 0x0600 0x1005 182: 0x1202 0x1489 0xB44A 0x0600 0x0005 183: 0x1202 0x1489 0xB40A 0x0600 0x0005 184: 0x1202 0x1489 0xB40A 0x0600 0x1004 185: 0x1202 0x1489 0xB40A 0x0600 0x0005 186: 0x1202 0x1489 0xB40A 0x0600 0x0005 187: 0x1202 0x1489 0xB44A 0x0600 0x0005 188: 0x1202 0x1489 0xB40A 0x0600 0x0005 189: 0x1202 0x1489 0xF40A 0x0600 0x0005 190: 0x1202 0x1489 0xF46A 0x0600 0x0005 191: 0x1202 0x1489 0xF42A 0x0600 0x0005 192: 0x1202 0x1489 0xF42A 0x0600 0x0005 193: 0x1202 0x1489 0xF46A 0x0600 0x1005 194: 0x1202 0x1489 0xF42A 0x0600 0x1005 195: 0x1202 0x1489 0xF42A 0x0600 0x1005 196: 0x1202 0x1489 0xF46A 0x0600 0x1005 197: 0x1202 0x1489 0xF42A 0x0600 0x1005 198: 0x1202 0x1489 0xB42A 0x0600 0x1005 199: 0x1202 0x1489 0xB44A 0x0600 0x1005 200: 0x1202 0x1489 0xB40A 0x0600 0x1005 201: 0x1202 0x1489 0xF40A 0x0600 0x1005 202: 0x1202 0x1489 0xF46A 0x0600 0x0005 203: 0x1202 0x1489 0xF42A 0x0600 0x0005 204: 0x1202 0x1489 0xB42A 0x0600 0x0005 205: 0x1202 0x1489 0xB44A 0x0600 0x1005 206: 0x1202 0x1489 0xB40A 0x0600 0x1005 207: 0x1202 0x1489 0xF40A 0x0600 0x1005 208: 0x1202 0x1489 0xF46A 0x0600 0x0005 209: 0x1202 0x1489 0xF42A 0x0600 0x0005 210: 0x1202 0x1489 0xF42A 0x0600 0x0005 211: 0x1202 0x1489 0xF46A 0x0600 0x1005 212: 0x1202 0x1489 0xF42A 0x0600 0x1005 213: 0x1202 0x1489 0xF42A 0x0600 0x1005 PINs used (in edge connector order) (G=ground,P=power) SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBB LETTER ABCDEFHJKLMNPRSTUVABCDEFHJKLMNPRSTUVABCDEFHJKLMNPRSTUVABCDEFHJKLMNPRSTUV SIDE 111111111111111111222222222222222222111111111111111111222222222222222222 USAGE IOIOIIOIIIIOIOIGOIPIGIIIOOOIIOIIIOIOIOIOIIIIIIIOOIIGIOPOGOIIIIIIIIIOIIOO UUT has 44 inputs UUT has 22 outputs contains 66 pins/columns 0 pins are not used contains 213 'test steps' M222 PCB REV B SCHEMATIC REV A LINC TAPE REGISTERS TERMINOLOGY- SIGNALS REFER TO PDP12 MAINT VOL4 M222 SCHEMATIC. BUT... DEC USES AND-NOR GATES TO ROUTE THE ADDER A AND B INPUTS, SO... DEC RENAMED THE ADDER TO NEGATIVE LOGIC TERMS (I.E. A-N + B-N + C-N -> SUM-N, C1-N). (NOT THE 7482 DATASHEET NAMES OF A + B + C -> SUM, C1). SO, WITH ALL 'AND ENABLES' LOW, THE AND-NOR OUTPUTS = HIGH. WITH C-L HIGH, THE ADDER OUTPUT IS SUM-N=1, C1-N=1; THE INVERTED ADDER OUTPUT IS LOW (TAPE BUS). AND THERE IS NO CARRY (C1-N IS HI). THE TWO ADDERS, TWO REGISTER BITS, ETC ARE LABELED BIT 2 (EVEN, MSB) AND BIT 3 (ODD, LSB). THE ADDERS ARE REFERRED TO AS 'ADDER2' (MSB) AND 'ADDER3' (LSB). POWER PINS: AA2 +5V AT1 GROUND AC2 GROUND BA2 +5V BT1 GROUND BC2 GROUND (ALL PINS ARE USED). PINS Main menu Thu Aug 20 18:51:58 2015 test file is: tests\m222.new delay is: 0 trigger is: 1 1 read test file 2 set test delay 3 set test trigger 4 run test 5 output loading test 8 diags 9 exit UUT power is okay Thu Aug 20 18:52:00 2015 space single step O run once (one test, all steps) F run, stop on fail G go (run tests N run, stop on fail, no print S scope (run, no print) C toggle comment printout + increase speed (less delay) - decrease speed (more delay)(slower) Q quit test comment_flag is 1 space single step O run once (one test, all steps) F run, stop on fail G go (run tests N run, stop on fail, no print S scope (run, no print) C toggle comment printout + increase speed (less delay) - decrease speed (more delay)(slower) Q quit test source: ; all registers are unknown source: ; turn on C0, PHASE source: ; with no ENABLES, BUS2,BUS3 is 11, C2 is 1 source: 1000000000000000000000000000000000011111000XX0XX0XX0XXXX0XX0110XX1 changed: step 1 100000000000000000000000000000000001111100011011011010100110110111 source: source: ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; source: ; source: ; set all registers LOW source: ; source: ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; source: source: ; load TMA SETUP from tape bus (00) source: 100 changed: 100 step 2 100000000000000000000000000000000001111100100011011010100110110111 source: 0 changed: 0 step 3 100000000000000000000000000000000001111100000011011010100110110111 source: ; load TMA from tape bus (00) source: 100 changed: 100 step 4 100000000000000000000000000000000001111100000100011010100110110111 source: 0 changed: 0 step 5 100000000000000000000000000000000001111100000000011010100110110111 source: ; load TBN from tape bus (00) source: 100 changed: 100 step 6 100000000000000000000000000000000001111100000000100010100110110111 source: 0 changed: 0 step 7 100000000000000000000000000000000001111100000000000010100110110111 source: ; load TAC from tape bus (00) source: 10101 changed: 10101 step 8 100000000000000000000000000000000001111100000000000101010110110111 source: 0 changed: 0 step 9 100000000000000000000000000000000001111100000000000001010110110111 source: ; load TB from tape bus (00) source: 100 changed: 100 step 10 100000000000000000000000000000000001111100000000000001011000110111 source: 0 changed: 0 step 11 100000000000000000000000000000000001111100000000000001010000110111 source: ; load RWB from TB (JAMS CLEAR AND PRESET) source: 1 00 changed: 1 00 step 12 100000000000000000000000000000000001111100000000000001010001110001 source: 0 changed: 0 step 13 100000000000000000000000000000000001111100000000000001010000110001 source: ; (no change) source: 100000000000000000000000000000000001111100000000000001010000110001 changed: step 14 100000000000000000000000000000000001111100000000000001010000110001 source: source: source: ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; source: ; source: ; set all registers HIGH source: ; source: ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; source: source: ; set pin AF1 which clears pin BB2 and sets pin BR2 TAPE BUS 3 OUTPUT source: 1 0 1 changed: 1 0 1 step 15 100000000000010000000000000000000000111101000000000001010000110001 source: ; set pin AP2 which clears pin AN2 and sets pin BV2 TAPE BUS 2 OUTPUT source: 1 0 1 changed: 1 0 1 step 16 100000000000010010000000000000000000110111000000000001010000110001 source: source: source: ; load TMA SETUP from tape bus (11) source: 111 changed: 111 step 17 100000000000010010000000000000000000110111111000000001010000110001 source: 0 changed: 0 step 18 100000000000010010000000000000000000110111011000000001010000110001 source: ; load TMA from tape bus (11) source: 111 changed: 111 step 19 100000000000010010000000000000000000110111011111000001010000110001 source: 0 changed: 0 step 20 100000000000010010000000000000000000110111011011000001010000110001 source: ; load TBN from tape bus (11) source: 111 changed: 111 step 21 100000000000010010000000000000000000110111011011111001010000110001 source: 0 changed: 0 step 22 100000000000010010000000000000000000110111011011011001010000110001 source: ; load TAC from tape bus (11) source: 11010 changed: 11010 step 23 100000000000010010000000000000000000110111011011011110100000110001 source: 0 changed: 0 step 24 100000000000010010000000000000000000110111011011011010100000110001 source: ; load TB from tape bus (11) source: 111 changed: 111 step 25 100000000000010010000000000000000000110111011011011010101110110001 source: 0 changed: 0 step 26 100000000000010010000000000000000000110111011011011010100110110001 source: ; load RWB from TB (JAMS CLEAR AND PRESET) source: 1 11 changed: 1 11 step 27 100000000000010010000000000000000000110111011011011010100111110111 source: 0 changed: 0 step 28 100000000000010010000000000000000000110111011011011010100110110111 source: ; clear pin AF1 (AND with itself) to set pin BB2 (AND-NOR output) and clear pin BR2 TAPE BUS 3 OUTPUT source: 0 1 0 changed: 0 1 0 step 29 100000000000000010000000000000000001110110011011011010100110110111 source: ; clear pin AP2 (AND with itself) to set pin AN2 (AND-NOR output) and clear pin BV2 TAPE BUS 2 OUTPUT source: 0 1 0 changed: 0 1 0 step 30 100000000000000000000000000000000001111100011011011010100110110111 source: ; (no change) source: 100000000000000000000000000000000001111100011011011010100110110111 changed: step 31 100000000000000000000000000000000001111100011011011010100110110111 source: source: ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; source: ; source: ; will all registers high, walk a 0 source: ; source: ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; source: source: source: ; walk a 0, TMA SETUP 2 source: source: source: ; clear pin AP2 which sets pin AN2 and clears pin BV2 TAPE BUS 2 OUTPUT source: 0 1 0 changed: step 32 100000000000000000000000000000000001111100011011011010100110110111 source: ; set pin AF1 which clears pin BB2 and sets pin BR2 TAPE BUS 3 OUTPUT source: 1 0 1 changed: 1 0 1 step 33 100000000000010000000000000000000000111101011011011010100110110111 source: ; load TMA SETUP from tape bus (01) source: 101 changed: 10 step 34 100000000000010000000000000000000000111101101011011010100110110111 source: 0 changed: 0 step 35 100000000000010000000000000000000000111101001011011010100110110111 source: ; restore TMA SETUP 2 source: ; set pin AP2 which clears pin AN2 and sets pin BV2 TAPE BUS 2 OUTPUT source: 1 0 1 changed: 1 0 1 step 36 100000000000010010000000000000000000110111001011011010100110110111 source: ; load TMA SETUP from tape bus (11) source: 111 changed: 11 step 37 100000000000010010000000000000000000110111111011011010100110110111 source: 0 changed: 0 step 38 100000000000010010000000000000000000110111011011011010100110110111 source: source: source: ; walk a 0, TMA SETUP 3 source: source: source: ; set pin AP2 which clears pin AN2 and sets pin BV2 TAPE BUS 2 OUTPUT source: 1 0 1 changed: step 39 100000000000010010000000000000000000110111011011011010100110110111 source: ; clear pin AF1 which sets pin BB2 and clears pin BR2 TAPE BUS 3 OUTPUT source: 0 1 0 changed: 0 1 0 step 40 100000000000000010000000000000000001110110011011011010100110110111 source: ; load TMA SETUP from tape bus (10) source: 110 changed: 1 0 step 41 100000000000000010000000000000000001110110110011011010100110110111 source: 0 changed: 0 step 42 100000000000000010000000000000000001110110010011011010100110110111 source: ; restore TMA SETUP 3 source: ; set pin AF1 which clears pin BB2 and sets pin BR2 TAPE BUS 3 OUTPUT source: 1 0 1 changed: 1 0 1 step 43 100000000000010010000000000000000000110111010011011010100110110111 source: ; load TMA SETUP from tape bus (11) source: 111 changed: 1 1 step 44 100000000000010010000000000000000000110111111011011010100110110111 source: 0 changed: 0 step 45 100000000000010010000000000000000000110111011011011010100110110111 source: source: source: ; walk a 0, TMA 2 source: source: source: ; clear pin AP2 which sets pin AN2 and clears pin BV2 TAPE BUS 2 OUTPUT source: 0 1 0 changed: 0 1 0 step 46 100000000000010000000000000000000000111101011011011010100110110111 source: ; set pin AF1 which clears pin BB2 and sets pin BR2 TAPE BUS 3 OUTPUT source: 1 0 1 changed: step 47 100000000000010000000000000000000000111101011011011010100110110111 source: ; load TMA from tape bus (01) source: 101 changed: 10 step 48 100000000000010000000000000000000000111101011101011010100110110111 source: 0 changed: 0 step 49 100000000000010000000000000000000000111101011001011010100110110111 source: ; restore TMA 2 source: ; set pin AP2 which clears pin AN2 and sets pin BV2 TAPE BUS 2 OUTPUT source: 1 0 1 changed: 1 0 1 step 50 100000000000010010000000000000000000110111011001011010100110110111 source: ; load TMA from tape bus (11) source: 111 changed: 11 step 51 100000000000010010000000000000000000110111011111011010100110110111 source: 0 changed: 0 step 52 100000000000010010000000000000000000110111011011011010100110110111 source: source: source: ; walk a 0, TMA 3 source: source: source: ; set pin AP2 which clears pin AN2 and sets pin BV2 TAPE BUS 2 OUTPUT source: 1 0 1 changed: step 53 100000000000010010000000000000000000110111011011011010100110110111 source: ; clear pin AF1 which sets pin BB2 and clears pin BR2 TAPE BUS 3 OUTPUT source: 0 1 0 changed: 0 1 0 step 54 100000000000000010000000000000000001110110011011011010100110110111 source: ; load TMA from tape bus (10) source: 110 changed: 1 0 step 55 100000000000000010000000000000000001110110011110011010100110110111 source: 0 changed: 0 step 56 100000000000000010000000000000000001110110011010011010100110110111 source: ; restore TMA 3 source: ; set pin AF1 which clears pin BB2 and sets pin BR2 TAPE BUS 3 OUTPUT source: 1 0 1 changed: 1 0 1 step 57 100000000000010010000000000000000000110111011010011010100110110111 source: ; load TMA from tape bus (11) source: 111 changed: 1 1 step 58 100000000000010010000000000000000000110111011111011010100110110111 source: 0 changed: 0 step 59 100000000000010010000000000000000000110111011011011010100110110111 source: source: source: ; walk a 0, TBN 2 source: source: source: ; clear pin AP2 which sets pin AN2 and clears pin BV2 TAPE BUS 2 OUTPUT source: 0 1 0 changed: 0 1 0 step 60 100000000000010000000000000000000000111101011011011010100110110111 source: ; set pin AF1 which clears pin BB2 and sets pin BR2 TAPE BUS 3 OUTPUT source: 1 0 1 changed: step 61 100000000000010000000000000000000000111101011011011010100110110111 source: ; load TBN from tape bus (01) source: 101 changed: 10 step 62 100000000000010000000000000000000000111101011011101010100110110111 source: 0 changed: 0 step 63 100000000000010000000000000000000000111101011011001010100110110111 source: ; restore TBN 2 source: ; set pin AP2 which clears pin AN2 and sets pin BV2 TAPE BUS 2 OUTPUT source: 1 0 1 changed: 1 0 1 step 64 100000000000010010000000000000000000110111011011001010100110110111 source: ; load TBN from tape bus (11) source: 111 changed: 11 step 65 100000000000010010000000000000000000110111011011111010100110110111 source: 0 changed: 0 step 66 100000000000010010000000000000000000110111011011011010100110110111 source: source: source: ; walk a 0, TBN 3 source: source: source: ; set pin AP2 which clears pin AN2 and sets pin BV2 TAPE BUS 2 OUTPUT source: 1 0 1 changed: step 67 100000000000010010000000000000000000110111011011011010100110110111 source: ; clear pin AF1 which sets pin BB2 and clears pin BR2 TAPE BUS 3 OUTPUT source: 0 1 0 changed: 0 1 0 step 68 100000000000000010000000000000000001110110011011011010100110110111 source: ; load TBN from tape bus (10) source: 110 changed: 1 0 step 69 100000000000000010000000000000000001110110011011110010100110110111 source: 0 changed: 0 step 70 100000000000000010000000000000000001110110011011010010100110110111 source: ; restore TBN 3 source: ; set pin AF1 which clears pin BB2 and sets pin BR2 TAPE BUS 3 OUTPUT source: 1 0 1 changed: 1 0 1 step 71 100000000000010010000000000000000000110111011011010010100110110111 source: ; load TBN from tape bus (11) source: 111 changed: 1 1 step 72 100000000000010010000000000000000000110111011011111010100110110111 source: 0 changed: 0 step 73 100000000000010010000000000000000000110111011011011010100110110111 source: source: source: ; walk a 0, TAC 2 source: source: source: ; clear pin AP2 which sets pin AN2 and clears pin BV2 TAPE BUS 2 OUTPUT source: 0 1 0 changed: 0 1 0 step 74 100000000000010000000000000000000000111101011011011010100110110111 source: ; set pin AF1 which clears pin BB2 and sets pin BR2 TAPE BUS 3 OUTPUT source: 1 0 1 changed: step 75 100000000000010000000000000000000000111101011011011010100110110111 source: ; load TAC from tape bus (01) source: 10110 changed: 101 step 76 100000000000010000000000000000000000111101011011011101100110110111 source: 0 changed: 0 step 77 100000000000010000000000000000000000111101011011011001100110110111 source: ; restore TAC 2 source: ; set pin AP2 which clears pin AN2 and sets pin BV2 TAPE BUS 2 OUTPUT source: 1 0 1 changed: 1 0 1 step 78 100000000000010010000000000000000000110111011011011001100110110111 source: ; load TAC from tape bus (11) source: 11010 changed: 110 step 79 100000000000010010000000000000000000110111011011011110100110110111 source: 0 changed: 0 step 80 100000000000010010000000000000000000110111011011011010100110110111 source: source: source: ; walk a 0, TAC 3 source: source: source: ; set pin AP2 which clears pin AN2 and sets pin BV2 TAPE BUS 2 OUTPUT source: 1 0 1 changed: step 81 100000000000010010000000000000000000110111011011011010100110110111 source: ; clear pin AF1 which sets pin BB2 and clears pin BR2 TAPE BUS 3 OUTPUT source: 0 1 0 changed: 0 1 0 step 82 100000000000000010000000000000000001110110011011011010100110110111 source: ; load TAC from tape bus (10) source: 11001 changed: 1 01 step 83 100000000000000010000000000000000001110110011011011110010110110111 source: 0 changed: 0 step 84 100000000000000010000000000000000001110110011011011010010110110111 source: ; restore TAC 3 source: ; set pin AF1 which clears pin BB2 and sets pin BR2 TAPE BUS 3 OUTPUT source: 1 0 1 changed: 1 0 1 step 85 100000000000010010000000000000000000110111011011011010010110110111 source: ; load TAC from tape bus (11) source: 11010 changed: 1 10 step 86 100000000000010010000000000000000000110111011011011110100110110111 source: 0 changed: 0 step 87 100000000000010010000000000000000000110111011011011010100110110111 source: source: source: ; walk a 0, TB 2 source: source: source: ; clear pin AP2 which sets pin AN2 and clears pin BV2 TAPE BUS 2 OUTPUT source: 0 1 0 changed: 0 1 0 step 88 100000000000010000000000000000000000111101011011011010100110110111 source: ; set pin AF1 which clears pin BB2 and sets pin BR2 TAPE BUS 3 OUTPUT source: 1 0 1 changed: step 89 100000000000010000000000000000000000111101011011011010100110110111 source: ; load TB from tape bus (01) source: 101 changed: 10 step 90 100000000000010000000000000000000000111101011011011010101010110111 source: 0 changed: 0 step 91 100000000000010000000000000000000000111101011011011010100010110111 source: ; restore TB 2 source: ; set pin AP2 which clears pin AN2 and sets pin BV2 TAPE BUS 2 OUTPUT source: 1 0 1 changed: 1 0 1 step 92 100000000000010010000000000000000000110111011011011010100010110111 source: ; load TB from tape bus (11) source: 111 changed: 11 step 93 100000000000010010000000000000000000110111011011011010101110110111 source: 0 changed: 0 step 94 100000000000010010000000000000000000110111011011011010100110110111 source: source: source: ; walk a 0, TB 3 source: source: source: ; set pin AP2 which clears pin AN2 and sets pin BV2 TAPE BUS 2 OUTPUT source: 1 0 1 changed: step 95 100000000000010010000000000000000000110111011011011010100110110111 source: ; clear pin AF1 which sets pin BB2 and clears pin BR2 TAPE BUS 3 OUTPUT source: 0 1 0 changed: 0 1 0 step 96 100000000000000010000000000000000001110110011011011010100110110111 source: ; load TB from tape bus (10) source: 110 changed: 1 0 step 97 100000000000000010000000000000000001110110011011011010101100110111 source: 0 changed: 0 step 98 100000000000000010000000000000000001110110011011011010100100110111 source: ; restore TB 3 source: ; set pin AF1 which clears pin BB2 and sets pin BR2 TAPE BUS 3 OUTPUT source: 1 0 1 changed: 1 0 1 step 99 100000000000010010000000000000000000110111011011011010100100110111 source: ; load TB from tape bus (11) source: 111 changed: 1 1 step 100 100000000000010010000000000000000000110111011011011010101110110111 source: 0 changed: 0 step 101 100000000000010010000000000000000000110111011011011010100110110111 source: source: source: ; walk a 0, RWB 2 source: source: source: ; clear pin AP2 which sets pin AN2 and clears pin BV2 TAPE BUS 2 OUTPUT source: 0 1 0 changed: 0 1 0 step 102 100000000000010000000000000000000000111101011011011010100110110111 source: ; set pin AF1 which clears pin BB2 and sets pin BR2 TAPE BUS 3 OUTPUT source: 1 0 1 changed: step 103 100000000000010000000000000000000000111101011011011010100110110111 source: ; load TB from tape bus (01) source: 101 changed: 10 step 104 100000000000010000000000000000000000111101011011011010101010110111 source: 0 changed: 0 step 105 100000000000010000000000000000000000111101011011011010100010110111 source: ; load RWB from TB (JAMS CLEAR AND PRESET) source: 1 01 changed: 1 0 step 106 100000000000010000000000000000000000111101011011011010100011110011 source: 0 changed: 0 step 107 100000000000010000000000000000000000111101011011011010100010110011 source: ; restore TB 2 and RWB 2 source: ; set pin AP2 which clears pin AN2 and sets pin BV2 TAPE BUS 2 OUTPUT source: 1 0 1 changed: 1 0 1 step 108 100000000000010010000000000000000000110111011011011010100010110011 source: ; load TB from tape bus (11) source: 111 changed: 11 step 109 100000000000010010000000000000000000110111011011011010101110110011 source: 0 changed: 0 step 110 100000000000010010000000000000000000110111011011011010100110110011 source: ; load RWB from TB (JAMS CLEAR AND PRESET) source: 1 11 changed: 1 1 step 111 100000000000010010000000000000000000110111011011011010100111110111 source: 0 changed: 0 step 112 100000000000010010000000000000000000110111011011011010100110110111 source: source: source: ; walk a 0, RWB 3 source: source: source: ; set pin AP2 which clears pin AN2 and sets pin BV2 TAPE BUS 2 OUTPUT source: 1 0 1 changed: step 113 100000000000010010000000000000000000110111011011011010100110110111 source: ; clear pin AF1 which sets pin BB2 and clears pin BR2 TAPE BUS 3 OUTPUT source: 0 1 0 changed: 0 1 0 step 114 100000000000000010000000000000000001110110011011011010100110110111 source: ; load TB from tape bus (10) source: 110 changed: 1 0 step 115 100000000000000010000000000000000001110110011011011010101100110111 source: 0 changed: 0 step 116 100000000000000010000000000000000001110110011011011010100100110111 source: ; load RWB from TB (JAMS CLEAR AND PRESET) source: 1 10 changed: 1 0 step 117 100000000000000010000000000000000001110110011011011010100101110101 source: 0 changed: 0 step 118 100000000000000010000000000000000001110110011011011010100100110101 source: ; restore TB 3 and RWB 3 source: ; set pin AF1 which clears pin BB2 and sets pin BR2 TAPE BUS 3 OUTPUT source: 1 0 1 changed: 1 0 1 step 119 100000000000010010000000000000000000110111011011011010100100110101 source: ; load TB from tape bus (11) source: 111 changed: 1 1 step 120 100000000000010010000000000000000000110111011011011010101110110101 source: 0 changed: 0 step 121 100000000000010010000000000000000000110111011011011010100110110101 source: ; load RWB from TB (JAMS CLEAR AND PRESET) source: 1 11 changed: 1 1 step 122 100000000000010010000000000000000000110111011011011010100111110111 source: 0 changed: 0 step 123 100000000000010010000000000000000000110111011011011010100110110111 source: source: source: ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; source: ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; source: ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; source: ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; source: ;********************* need to walk a one ********************** source: ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; source: ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; source: ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; source: ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; source: source: ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; source: ; source: ; test AND-NOR logic source: ; source: ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; source: source: ; (all registers are HIGH) source: ; set all pins HIGH except ENABLES source: source: ; set pin AF2 HIGH source: 1 changed: 1 step 124 100001000000010010000000000000000000110111011011011010100110110111 source: ; set pin AM1 HIGH source: 1 changed: 1 step 125 100001100000010010000000000000000000110111011011011010100110110111 source: ; set pin AE1 HIGH source: 1 changed: 1 step 126 100001100100010010000000000000000000110111011011011010100110110111 source: ; set pin AM2 HIGH source: 1 changed: 1 step 127 100001100110010010000000000000000000110111011011011010100110110111 source: ; set pin AB2 HIGH source: 1 changed: 1 step 128 100001100110110010000000000000000000110111011011011010100110110111 source: ; set pin AS1 HIGH source: 1 changed: 1 step 129 100001100110110110000000000000000000110111011011011010100110110111 source: ; set pin BE1 HIGH source: 1 changed: 1 step 130 100001100110110110010000000000000000110111011011011010100110110111 source: ; set pin BM1 HIGH source: 1 changed: 1 step 131 100001100110110110011000000000000000110111011011011010100110110111 source: ; set pin BH1 HIGH source: 1 changed: 1 step 132 100001100110110110011010000000000000110111011011011010100110110111 source: ; set pin BR1 HIGH source: 1 changed: 1 step 133 100001100110110110011011000000000000110111011011011010100110110111 source: ; set pin BC1 HIGH source: 1 changed: 1 step 134 100001100110110110011011010000000000110111011011011010100110110111 source: ; set pin BJ2 HIGH source: 1 changed: 1 step 135 100001100110110110011011011000000000110111011011011010100110110111 source: ; set pin BJ1 HIGH source: 1 changed: 1 step 136 100001100110110110011011011010000000110111011011011010100110110111 source: ; set pin BK2 HIGH source: 1 changed: 1 step 137 100001100110110110011011011011000000110111011011011010100110110111 source: ; set pin BH2 HIGH source: 1 changed: 1 step 138 100001100110110110011011011011010000110111011011011010100110110111 source: ; set pin BP2 HIGH source: 1 changed: 1 step 139 100001100110110110011011011011011000110111011011011010100110110111 source: ; set pin BN2 HIGH source: 1 changed: 1 step 140 100001100110110110011011011011011100110111011011011010100110110111 source: ; toggle each ENABLE source: source: ; set pin AL2 to clear pin BB2 and pin AN2 AND-NOR OUTPUTS and set TAPE BUS 2 OUTPUT and TAPE BUS 3 OUTPUT source: 1 0 0 11 changed: 1 step 141 110001100110110110011011011011011100110111011011011010100110110111 SLOT BAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBAABBAAAAAAAAAAAAAABBBBBABBBB LETTER ALPSLFMDEEMCBFRSPKLEMFHRSCJLJKUHPNMBBNNVVRKRHUTDJUKANJHBTPDFSVEVDU SIDE 121212122121212121111111112212122222112222111221112112212112212122 DIRECTION IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIOOOOOOOIOOIOOIOOIOOOOIOOIIIIOOO source: 0 1 1 00 changed: 0 step 142 100001100110110110011011011011011100110111011011011010100110110111 fail ^ ^ ^^ space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C toggle comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT BAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBAABBAAAAAAAAAAAAAABBBBBABBBB LETTER ALPSLFMDEEMCBFRSPKLEMFHRSCJLJKUHPNMBBNNVVRKRHUTDJUKANJHBTPDFSVEVDU SIDE 121212122121212121111111112212122222112222111221112112212112212122 DIRECTION IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIOOOOOOOIOOIOOIOOIOOOOIOOIIIIOOO source: ; set pin AP1 to clear pin BB2 and pin AN2 AND-NOR OUTPUTS and set TAPE BUS 2 OUTPUT and TAPE BUS 3 OUTPUT source: 1 0 0 11 changed: 1 step 143 101001100110110110011011011011011100110111011011011010100110110111 okay space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C toggle comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT BAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBAABBAAAAAAAAAAAAAABBBBBABBBB LETTER ALPSLFMDEEMCBFRSPKLEMFHRSCJLJKUHPNMBBNNVVRKRHUTDJUKANJHBTPDFSVEVDU SIDE 121212122121212121111111112212122222112222111221112112212112212122 DIRECTION IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIOOOOOOOIOOIOOIOOIOOOOIOOIIIIOOO all fails O O OO was lo 00000000000000000000000000000000000 0 00000000000000000000 000 falling v v v v v vvvvvvvvvvvvvvvvvvvv vv rising ^^ ^^ ^^ ^^ ^^ ^^ ^^ ^^ ^^ ^^^ ^ ^ ^^^^^^^^^^^^^^^^^^^^ ^^ was hi 111 11 11 11 11 11 11 11 11 111 111111111111111111111111111 111 total fails 0, total passes 0 Main menu Thu Aug 20 18:54:05 2015 test file is: tests\m222.new delay is: 0 trigger is: 1 1 read test file 2 set test delay 3 set test trigger 4 run test 5 output loading test 8 diags 9 exit Enter test file name? trying to open test file: tests\m222.new reading test file: tests\m222.new comment: M222 PCB REV B SCHEMATIC REV A LINC TAPE REGISTERS comment: comment: TERMINOLOGY- SIGNALS REFER TO PDP12 MAINT VOL4 M222 SCHEMATIC. comment: comment: BUT... comment: comment: DEC USES AND-NOR GATES TO ROUTE THE ADDER A AND B INPUTS, SO... comment: DEC RENAMED THE ADDER TO NEGATIVE LOGIC TERMS (I.E. A-N + B-N + C-N -> SUM-N, C1-N). comment: (NOT THE 7482 DATASHEET NAMES OF A + B + C -> SUM, C1). comment: comment: SO, WITH ALL 'AND ENABLES' LOW, THE AND-NOR OUTPUTS = HIGH. comment: WITH C-L HIGH, THE ADDER OUTPUT IS SUM-N=1, C1-N=1; comment: THE INVERTED ADDER OUTPUT IS LOW (TAPE BUS). comment: AND THERE IS NO CARRY (C1-N IS HI). comment: comment: THE TWO ADDERS, TWO REGISTER BITS, ETC ARE LABELED BIT 2 (EVEN, MSB) AND BIT 3 (ODD, LSB). comment: THE ADDERS ARE REFERRED TO AS 'ADDER2' (MSB) AND 'ADDER3' (LSB). comment: comment: POWER PINS: comment: AA2 +5V comment: AT1 GROUND comment: AC2 GROUND comment: BA2 +5V comment: BT1 GROUND comment: BC2 GROUND comment: comment: (ALL PINS ARE USED). comment: comment: pins: PINS pins: 1 I BA1 CARRY IN-N, (TO E9-5 7482 C0) C-N TO ADDER2 pins: 2 I AL2 AND-NOR ENABLE: TAC TAC3 TO PIN BB2 (TO ADDER3) TAC2 TO PIN AN2 (TO ADDER2) pins: 3 I AP1 AND-NOR ENABLE: TMA SETUP (TMAS)3 TO PIN BB2 (TO ADDER3), (TMAS)3 TO PIN AN2 (TO ADDER2) pins: 4 I AS2 AND-NOR ENABLE: TMA TMA3 TO PIN BB2 (TO ADDER3), TMA2 TO PIN AN2 (TO ADDER2) pins: 5 I AL1 AND-NOR ENABLE: PIN AF2 TO PIN BB2 (TO ADDER3), PIN AM1 TO PIN AN2 (TO ADDER2) pins: 6 I AF2 AND-NOR INPUT (AL1 ENABLES) TO PIN BB2 (TO ADDER3). pins: 7 I AM1 AND-NOR INPUT (AL1 ENABLES) TO PIN AN2 (TO ADDER2) pins: 8 I AD2 AND-NOR ENABLE: RWB RWB3 TO PIN BB2 (TO ADDER3), RWB2 TO PIN AN2 (TO ADDER2) pins: 9 I AE2 AND-NOR ENABLE: PIN AE1 TO PIN BB2 (TO ADDER3), PIN AM2 TO PIN AN2 (TO ADDER2) pins: 10 I AE1 AND-NOR INPUT (AE2 ENABLES) TO PIN BB2 (TO ADDER3). pins: 11 I AM2 AND-NOR INPUT (AE2 ENABLES) TO PIN AN2 (TO ADDER2) pins: 12 I AC1 AND-NOR INPUT, AND WITH PIN AB2 TO PIN BB2 (TO ADDER3) pins: 13 I AB2 AND-NOR INPUT, AND WITH PIN AC1 TO PIN BB2 (TO ADDER3) pins: 14 I AF1 AND-NOR INPUT (AND WITH ITSELF) TO PIN BB2 (TO ADDER3) pins: 15 I AR2 AND-NOR INPUT, AND WITH PIN AS1 TO PIN AN2 (TO ADDER2) pins: 16 I AS1 AND-NOR INPUT, AND WITH PIN AR2 TO PIN AN2 (TO ADDER2) pins: 17 I AP2 AND-NOR INPUT (AND WITH ITSELF) TO PIN AN2 (TO ADDER2) pins: 18 I BK1 AND-NOR ENABLE: TB3 TO PIN BB1 (TO ADDER3), TB2 TO PIN BN1 (TO ADDER2) pins: 19 I BL1 AND-NOR ENABLE: PIN BE1 TO PIN BB1 (TO ADDER3), PIN BM1 TO PIN BN1 (TO ADDER2) pins: 20 I BE1 AND-NOR INPUT (BL1 ENABLES) TO PIN BB1 (TO ADDER3). pins: 21 I BM1 AND-NOR INPUT (BL1 ENABLES) TO PIN BN1 (TO ADDER2) pins: 22 I BF1 AND-NOR ENABLE: PIN BH1 TO PIN BB1 (TO ADDER3), PIN BR1 TO PIN BN1 (TO ADDER2) pins: 23 I BH1 AND-NOR INPUT (BF1 ENABLES): TO PIN BB1 (TO ADDER3), pins: 24 I BR1 AND-NOR INPUT (BF1 ENABLES): TO PIN BN1 (TO ADDER2) pins: 25 I BS1 AND-NOR ENABLE: PIN BC1 TO PIN BB1 (TO ADDER3), PIN BJ2 TO PIN BN1 (TO ADDER2) pins: 26 I BC1 AND-NOR INPUT (BS1 ENABLES): TO PIN BB1 (TO ADDER3), pins: 27 I BJ2 AND-NOR INPUT (BS1 ENABLES): TO PIN BN1 (TO ADDER2) pins: 28 I BL2 AND-NOR ENABLE: PIN BJ1 TO PIN BB1 (TO ADDER3), PIN BK2 TO PIN BN1 (TO ADDER2) pins: 29 I BJ1 AND-NOR INPUT (BL2 ENABLES): TO PIN BB1 (TO ADDER3), pins: 30 I BK2 AND-NOR INPUT (BL2 ENABLES): TO PIN BN1 (TO ADDER2) pins: 31 I BU1 AND-NOR ENABLE: PIN BH2 TO PIN BB1 (TO ADDER3), PIN BP2 TO PIN BN1 (TO ADDER2) pins: 32 I BH2 AND-NOR INPUT (BU1 ENABLES): TO PIN BB1 (TO ADDER3), pins: 33 I BP2 AND-NOR INPUT (BU1 ENABLES): TO PIN BN1 (TO ADDER2) pins: 34 I BN2 AND-NOR INPUT (AND WITH BM2): TO PIN BN1 (TO ADDER2) pins: 35 I BM2 AND-NOR INPUT (AND WITH BM2): TO PIN BN1 (TO ADDER2) pins: 36 O BB2 AND-NOR OUTPUT, (DRIVES E9-2 7482 A1) TO ADDER3 INPUT pins: 37 O BB1 AND-NOR OUTPUT, (DRIVES E9-3 7482 B1) TO ADDER3 INPUT pins: 38 O BN1 AND-NOR OUTPUT, (DRIVES E9-14 7482 A2) TO ADDER2 INPUT pins: 39 O AN2 AND-NOR OUTPUT, (DRIVES E9-13 7482 B2) TO ADDER2 INPUT pins: 40 O AV2 CARRY OUT-N (E9-10 7482 C2) pins: 41 O BV2 TAPE BUS 2 OUTPUT (INVERTED ADDER2 SUM-N (E9-12 7482 SUM2) pins: 42 O BR2 TAPE BUS 3 OUTPUT (INVERTED ADDER3 SUM-N (E9-1 7482 SUM1) pins: 43 I AK1 LOAD TMA SETUP (FROM TAPE BUS) (RISING EDGE CLOCK) pins: 44 O AR1 TMA SETUP 2 pins: 45 O AH1 TMA SETUP 3 pins: 46 I AU2 LOAD TMA (FROM TAPE BUS) (RISING EDGE CLOCK) pins: 47 O AT2 TMA 2 pins: 48 O AD1 TMA 3 pins: 49 I AJ1 LOAD TBN (FROM TAPE BUS) (RISING EDGE CLOCK) pins: 50 O AU1 TBN 2 pins: 51 O AK2 TBN 3 pins: 52 I AA1 LOAD TAC (FROM TAPE BUS) (RISING EDGE CLOCK) pins: 53 O AN1 TAC 2 pins: 54 O AJ2 TAC 2-N pins: 55 O AH2 TAC 3 pins: 56 O AB1 TAC 3-N pins: 57 I BT2 LOAD TB (FROM TAPE BUS) (RISING EDGE CLOCK) pins: 58 O BP1 TB 2 pins: 59 O BD1 TB 3 pins: 60 I BF2 LOAD RWB (FROM TB) (JAMS CLEAR,SET) pins: 61 I BS2 PHASE (SELECTS POLARITY OF RWB OUT, 0 -> INVERTED) pins: 62 I AV1 RWB IN (SHIFTED INTO RWB 3) pins: 63 I BE2 SHIFT RWB (SHIFTS PIN AV1 INTO RWB 3, SHIFTS RWB3 TO RWB2) (RISING CLOCK) pins: 64 O BV1 RWB OUT (IF PHASE=1, =RWB 2; IF PHASE=0; =RWB 2-N) pins: 65 O BD2 RWB 3 pins: 66 O BU2 +3.5V pins: direction: IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIOOOOOOOIOOIOOIOOIOOOOIOOIIIIOOO comment: ; all registers are unknown comment: ; turn on C0, PHASE comment: ; with no ENABLES, BUS2,BUS3 is 11, C2 is 1 test 1: 1000000000000000000000000000000000011111000XX0XX0XX0XXXX0XX0110XX1 comment: comment: ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; comment: ; comment: ; set all registers LOW comment: ; comment: ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; comment: comment: ; load TMA SETUP from tape bus (00) test 2: 100 test 3: 0 comment: ; load TMA from tape bus (00) test 4: 100 test 5: 0 comment: ; load TBN from tape bus (00) test 6: 100 test 7: 0 comment: ; load TAC from tape bus (00) test 8: 10101 test 9: 0 comment: ; load TB from tape bus (00) test 10: 100 test 11: 0 comment: ; load RWB from TB (JAMS CLEAR AND PRESET) test 12: 1 00 test 13: 0 comment: ; (no change) test 14: 100000000000000000000000000000000001111100000000000001010000110001 comment: comment: comment: ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; comment: ; comment: ; set all registers HIGH comment: ; comment: ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; comment: comment: ; set pin AF1 which clears pin BB2 and sets pin BR2 TAPE BUS 3 OUTPUT test 15: 1 0 1 comment: ; set pin AP2 which clears pin AN2 and sets pin BV2 TAPE BUS 2 OUTPUT test 16: 1 0 1 comment: comment: comment: ; load TMA SETUP from tape bus (11) test 17: 111 test 18: 0 comment: ; load TMA from tape bus (11) test 19: 111 test 20: 0 comment: ; load TBN from tape bus (11) test 21: 111 test 22: 0 comment: ; load TAC from tape bus (11) test 23: 11010 test 24: 0 comment: ; load TB from tape bus (11) test 25: 111 test 26: 0 comment: ; load RWB from TB (JAMS CLEAR AND PRESET) test 27: 1 11 test 28: 0 comment: ; clear pin AF1 (AND with itself) to set pin BB2 (AND-NOR output) and clear pin BR2 TAPE BUS 3 OUTPUT test 29: 0 1 0 comment: ; clear pin AP2 (AND with itself) to set pin AN2 (AND-NOR output) and clear pin BV2 TAPE BUS 2 OUTPUT test 30: 0 1 0 comment: ; (no change) test 31: 100000000000000000000000000000000001111100011011011010100110110111 comment: comment: ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; comment: ; comment: ; will all registers high, walk a 0 comment: ; comment: ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; comment: comment: comment: ; walk a 0, TMA SETUP 2 comment: comment: comment: ; clear pin AP2 which sets pin AN2 and clears pin BV2 TAPE BUS 2 OUTPUT test 32: 0 1 0 comment: ; set pin AF1 which clears pin BB2 and sets pin BR2 TAPE BUS 3 OUTPUT test 33: 1 0 1 comment: ; load TMA SETUP from tape bus (01) test 34: 101 test 35: 0 comment: ; restore TMA SETUP 2 comment: ; set pin AP2 which clears pin AN2 and sets pin BV2 TAPE BUS 2 OUTPUT test 36: 1 0 1 comment: ; load TMA SETUP from tape bus (11) test 37: 111 test 38: 0 comment: comment: comment: ; walk a 0, TMA SETUP 3 comment: comment: comment: ; set pin AP2 which clears pin AN2 and sets pin BV2 TAPE BUS 2 OUTPUT test 39: 1 0 1 comment: ; clear pin AF1 which sets pin BB2 and clears pin BR2 TAPE BUS 3 OUTPUT test 40: 0 1 0 comment: ; load TMA SETUP from tape bus (10) test 41: 110 test 42: 0 comment: ; restore TMA SETUP 3 comment: ; set pin AF1 which clears pin BB2 and sets pin BR2 TAPE BUS 3 OUTPUT test 43: 1 0 1 comment: ; load TMA SETUP from tape bus (11) test 44: 111 test 45: 0 comment: comment: comment: ; walk a 0, TMA 2 comment: comment: comment: ; clear pin AP2 which sets pin AN2 and clears pin BV2 TAPE BUS 2 OUTPUT test 46: 0 1 0 comment: ; set pin AF1 which clears pin BB2 and sets pin BR2 TAPE BUS 3 OUTPUT test 47: 1 0 1 comment: ; load TMA from tape bus (01) test 48: 101 test 49: 0 comment: ; restore TMA 2 comment: ; set pin AP2 which clears pin AN2 and sets pin BV2 TAPE BUS 2 OUTPUT test 50: 1 0 1 comment: ; load TMA from tape bus (11) test 51: 111 test 52: 0 comment: comment: comment: ; walk a 0, TMA 3 comment: comment: comment: ; set pin AP2 which clears pin AN2 and sets pin BV2 TAPE BUS 2 OUTPUT test 53: 1 0 1 comment: ; clear pin AF1 which sets pin BB2 and clears pin BR2 TAPE BUS 3 OUTPUT test 54: 0 1 0 comment: ; load TMA from tape bus (10) test 55: 110 test 56: 0 comment: ; restore TMA 3 comment: ; set pin AF1 which clears pin BB2 and sets pin BR2 TAPE BUS 3 OUTPUT test 57: 1 0 1 comment: ; load TMA from tape bus (11) test 58: 111 test 59: 0 comment: comment: comment: ; walk a 0, TBN 2 comment: comment: comment: ; clear pin AP2 which sets pin AN2 and clears pin BV2 TAPE BUS 2 OUTPUT test 60: 0 1 0 comment: ; set pin AF1 which clears pin BB2 and sets pin BR2 TAPE BUS 3 OUTPUT test 61: 1 0 1 comment: ; load TBN from tape bus (01) test 62: 101 test 63: 0 comment: ; restore TBN 2 comment: ; set pin AP2 which clears pin AN2 and sets pin BV2 TAPE BUS 2 OUTPUT test 64: 1 0 1 comment: ; load TBN from tape bus (11) test 65: 111 test 66: 0 comment: comment: comment: ; walk a 0, TBN 3 comment: comment: comment: ; set pin AP2 which clears pin AN2 and sets pin BV2 TAPE BUS 2 OUTPUT test 67: 1 0 1 comment: ; clear pin AF1 which sets pin BB2 and clears pin BR2 TAPE BUS 3 OUTPUT test 68: 0 1 0 comment: ; load TBN from tape bus (10) test 69: 110 test 70: 0 comment: ; restore TBN 3 comment: ; set pin AF1 which clears pin BB2 and sets pin BR2 TAPE BUS 3 OUTPUT test 71: 1 0 1 comment: ; load TBN from tape bus (11) test 72: 111 test 73: 0 comment: comment: comment: ; walk a 0, TAC 2 comment: comment: comment: ; clear pin AP2 which sets pin AN2 and clears pin BV2 TAPE BUS 2 OUTPUT test 74: 0 1 0 comment: ; set pin AF1 which clears pin BB2 and sets pin BR2 TAPE BUS 3 OUTPUT test 75: 1 0 1 comment: ; load TAC from tape bus (01) test 76: 10110 test 77: 0 comment: ; restore TAC 2 comment: ; set pin AP2 which clears pin AN2 and sets pin BV2 TAPE BUS 2 OUTPUT test 78: 1 0 1 comment: ; load TAC from tape bus (11) test 79: 11010 test 80: 0 comment: comment: comment: ; walk a 0, TAC 3 comment: comment: comment: ; set pin AP2 which clears pin AN2 and sets pin BV2 TAPE BUS 2 OUTPUT test 81: 1 0 1 comment: ; clear pin AF1 which sets pin BB2 and clears pin BR2 TAPE BUS 3 OUTPUT test 82: 0 1 0 comment: ; load TAC from tape bus (10) test 83: 11001 test 84: 0 comment: ; restore TAC 3 comment: ; set pin AF1 which clears pin BB2 and sets pin BR2 TAPE BUS 3 OUTPUT test 85: 1 0 1 comment: ; load TAC from tape bus (11) test 86: 11010 test 87: 0 comment: comment: comment: ; walk a 0, TB 2 comment: comment: comment: ; clear pin AP2 which sets pin AN2 and clears pin BV2 TAPE BUS 2 OUTPUT test 88: 0 1 0 comment: ; set pin AF1 which clears pin BB2 and sets pin BR2 TAPE BUS 3 OUTPUT test 89: 1 0 1 comment: ; load TB from tape bus (01) test 90: 101 test 91: 0 comment: ; restore TB 2 comment: ; set pin AP2 which clears pin AN2 and sets pin BV2 TAPE BUS 2 OUTPUT test 92: 1 0 1 comment: ; load TB from tape bus (11) test 93: 111 test 94: 0 comment: comment: comment: ; walk a 0, TB 3 comment: comment: comment: ; set pin AP2 which clears pin AN2 and sets pin BV2 TAPE BUS 2 OUTPUT test 95: 1 0 1 comment: ; clear pin AF1 which sets pin BB2 and clears pin BR2 TAPE BUS 3 OUTPUT test 96: 0 1 0 comment: ; load TB from tape bus (10) test 97: 110 test 98: 0 comment: ; restore TB 3 comment: ; set pin AF1 which clears pin BB2 and sets pin BR2 TAPE BUS 3 OUTPUT test 99: 1 0 1 comment: ; load TB from tape bus (11) test 100: 111 test 101: 0 comment: comment: comment: ; walk a 0, RWB 2 comment: comment: comment: ; clear pin AP2 which sets pin AN2 and clears pin BV2 TAPE BUS 2 OUTPUT test 102: 0 1 0 comment: ; set pin AF1 which clears pin BB2 and sets pin BR2 TAPE BUS 3 OUTPUT test 103: 1 0 1 comment: ; load TB from tape bus (01) test 104: 101 test 105: 0 comment: ; load RWB from TB (JAMS CLEAR AND PRESET) test 106: 1 01 test 107: 0 comment: ; restore TB 2 and RWB 2 comment: ; set pin AP2 which clears pin AN2 and sets pin BV2 TAPE BUS 2 OUTPUT test 108: 1 0 1 comment: ; load TB from tape bus (11) test 109: 111 test 110: 0 comment: ; load RWB from TB (JAMS CLEAR AND PRESET) test 111: 1 11 test 112: 0 comment: comment: comment: ; walk a 0, RWB 3 comment: comment: comment: ; set pin AP2 which clears pin AN2 and sets pin BV2 TAPE BUS 2 OUTPUT test 113: 1 0 1 comment: ; clear pin AF1 which sets pin BB2 and clears pin BR2 TAPE BUS 3 OUTPUT test 114: 0 1 0 comment: ; load TB from tape bus (10) test 115: 110 test 116: 0 comment: ; load RWB from TB (JAMS CLEAR AND PRESET) test 117: 1 10 test 118: 0 comment: ; restore TB 3 and RWB 3 comment: ; set pin AF1 which clears pin BB2 and sets pin BR2 TAPE BUS 3 OUTPUT test 119: 1 0 1 comment: ; load TB from tape bus (11) test 120: 111 test 121: 0 comment: ; load RWB from TB (JAMS CLEAR AND PRESET) test 122: 1 11 test 123: 0 comment: comment: ; (no change) test 124: 100000000000000000000000000000000001111100011011011010100110110111 comment: comment: comment: ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; comment: ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; comment: ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; comment: ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; comment: ;********************* need to walk a one ********************** comment: ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; comment: ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; comment: ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; comment: ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; comment: comment: ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; comment: ; comment: ; test AND-NOR logic comment: ; comment: ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; comment: comment: ; (all registers are HIGH) comment: ; set all pins HIGH except ENABLES comment: comment: ; set pin AF2 HIGH test 125: 1 comment: ; set pin AM1 HIGH test 126: 1 comment: ; set pin AE1 HIGH test 127: 1 comment: ; set pin AM2 HIGH test 128: 1 comment: ; set pin AB2 HIGH test 129: 1 comment: ; set pin AS1 HIGH test 130: 1 comment: ; set pin BE1 HIGH test 131: 1 comment: ; set pin BM1 HIGH test 132: 1 comment: ; set pin BH1 HIGH test 133: 1 comment: ; set pin BR1 HIGH test 134: 1 comment: ; set pin BC1 HIGH test 135: 1 comment: ; set pin BJ2 HIGH test 136: 1 comment: ; set pin BJ1 HIGH test 137: 1 comment: ; set pin BK2 HIGH test 138: 1 comment: ; set pin BH2 HIGH test 139: 1 comment: ; set pin BP2 HIGH test 140: 1 comment: ; set pin BN2 HIGH test 141: 1 comment: ; toggle each ENABLE comment: comment: ; set pin AL2 to clear pin BB2 and pin AN2 AND-NOR OUTPUTS and set TAPE BUS 2 OUTPUT and TAPE BUS 3 OUTPUT test 142: 1 0 0 11 test 143: 0 1 1 00 comment: ; set pin AP1 to clear pin BB2 and pin AN2 AND-NOR OUTPUTS and set TAPE BUS 2 OUTPUT and TAPE BUS 3 OUTPUT test 144: 1 0 0 11 test 145: 0 1 1 00 comment: ; set pin AS2 to clear pin BB2 and pin AN2 AND-NOR OUTPUTS and set TAPE BUS 2 OUTPUT and TAPE BUS 3 OUTPUT test 146: 1 0 0 11 test 147: 0 1 1 00 comment: ; set pin AL1 to clear pin BB2 and pin AN2 AND-NOR OUTPUTS and set TAPE BUS 2 OUTPUT and TAPE BUS 3 OUTPUT test 148: 1 0 0 11 test 149: 0 1 1 00 comment: ; set pin AL1 to clear pin BB2 and pin AN2 AND-NOR OUTPUTS and set TAPE BUS 2 OUTPUT and TAPE BUS 3 OUTPUT test 150: 1 0 0 11 test 151: 0 1 1 00 comment: ; set pin AE2 to clear pin BB2 and pin AN2 AND-NOR OUTPUTS and set TAPE BUS 2 OUTPUT and TAPE BUS 3 OUTPUT test 152: 1 0 0 11 test 153: 0 1 1 00 comment: ; set pin AC1 to clear pin BB2 and set TAPE BUS 3 OUTPUT test 154: 1 0 1 test 155: 0 1 0 comment: ; set pin AF1 to clear pin BB2 and set TAPE BUS 3 OUTPUT test 156: 1 0 1 test 157: 0 1 0 comment: ; set pin AR2 to clear pin AN2 AND-NOR OUTPUTS and set TAPE BUS 2 OUTPUT test 158: 1 0 1 test 159: 0 1 0 comment: ; set pin AP2 to clear pin AN2 AND-NOR OUTPUTS and set TAPE BUS 2 OUTPUT test 160: 1 0 1 test 161: 0 1 0 comment: comment: ; set pin BK1 to clear pin BB1 and pin BN1 AND-NOR OUTPUTS and set TAPE BUS 2 OUTPUT and TAPE BUS 3 OUTPUT test 162: 1 00 11 test 163: 0 11 00 comment: ; set pin BL1 to clear pin BB1 and pin BN1 AND-NOR OUTPUTS and set TAPE BUS 2 OUTPUT and TAPE BUS 3 OUTPUT test 164: 1 00 11 test 165: 0 11 00 comment: ; set pin BF1 to clear pin BB1 and pin BN1 AND-NOR OUTPUTS and set TAPE BUS 2 OUTPUT and TAPE BUS 3 OUTPUT test 166: 1 00 11 test 167: 0 11 00 comment: ; set pin BS1 to clear pin BB1 and pin BN1 AND-NOR OUTPUTS and set TAPE BUS 2 OUTPUT and TAPE BUS 3 OUTPUT test 168: 1 00 11 test 169: 0 11 00 comment: ; set pin BL2 to clear pin BB1 and pin BN1 AND-NOR OUTPUTS and set TAPE BUS 2 OUTPUT and TAPE BUS 3 OUTPUT test 170: 1 00 11 test 171: 0 11 00 comment: ; set pin BU1 to clear pin BB1 and pin BN1 AND-NOR OUTPUTS and set TAPE BUS 2 OUTPUT and TAPE BUS 3 OUTPUT test 172: 1 00 11 test 173: 0 11 00 comment: ; set pin BM2 to clear pin BB1 and TAPE BUS 3 OUTPUT test 174: 1 0 1 test 175: 0 1 0 comment: ; no change test 176: 100000000000000000000000000000000001111100011011011010100110110111 comment: comment: comment: ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; comment: ; test shifting the RWB comment: ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; comment: comment: ; shift in 0, expect 10 test 177: 0 test 178: 110 test 179: 0 comment: ; toggle phase should toggle RWB 2 test 180: 0 0 test 181: 1 1 comment: comment: ; shift in 0, expect 00 test 182: 0 test 183: 100 test 184: 0 comment: ; toggle phase should toggle RWB 2 test 185: 0 1 test 186: 1 0 comment: comment: ; shift in 0, expect 00 test 187: 0 test 188: 100 test 189: 0 comment: ; shift in 1, expect 01 test 190: 1 test 191: 101 test 192: 0 comment: ; shift in 1, expect 11 test 193: 1 test 194: 111 test 195: 0 comment: ; shift in 1, expect 11 test 196: 1 test 197: 111 test 198: 0 comment: ; shift in 0, expect 10 test 199: 0 test 200: 110 test 201: 0 comment: ; shift in 1, expect 01 test 202: 1 test 203: 101 test 204: 0 comment: ; shift in 0, expect 10 test 205: 0 test 206: 110 test 207: 0 comment: ; shift in 1, expect 01 test 208: 1 test 209: 101 test 210: 0 comment: ; shift in 1, expect 11 test 211: 1 test 212: 111 test 213: 0 comment: ; no change test 214: 100000000000000000000000000000000001111100011011011010100110110111 comment: comment: ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; comment: ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; comment: ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; comment: ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; comment: ; needs work (more adder tests, more register tests) comment: ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; comment: ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; comment: ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; comment: ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; end: END summary column 1: offset 2, mask 0x2000 column 2: offset 1, mask 0x0002 column 3: offset 1, mask 0x0800 column 4: offset 1, mask 0x0040 column 5: offset 1, mask 0x4000 column 6: offset 0, mask 0x0004 column 7: offset 1, mask 0x2000 column 8: offset 0, mask 0x0010 column 9: offset 0, mask 0x0008 column 10: offset 0, mask 0x0800 column 11: offset 1, mask 0x0004 column 12: offset 0, mask 0x2000 column 13: offset 0, mask 0x0040 column 14: offset 0, mask 0x0400 column 15: offset 1, mask 0x0020 column 16: offset 1, mask 0x0200 column 17: offset 1, mask 0x0010 column 18: offset 3, mask 0x2000 column 19: offset 3, mask 0x1000 column 20: offset 2, mask 0x0200 column 21: offset 3, mask 0x0800 column 22: offset 2, mask 0x0100 column 23: offset 3, mask 0x8000 column 24: offset 3, mask 0x0100 column 25: offset 4, mask 0x8000 column 26: offset 2, mask 0x0800 column 27: offset 3, mask 0x0002 column 28: offset 3, mask 0x0008 column 29: offset 3, mask 0x4000 column 30: offset 3, mask 0x0004 column 31: offset 4, mask 0x2000 column 32: offset 3, mask 0x0001 column 33: offset 3, mask 0x0040 column 34: offset 3, mask 0x0020 column 35: offset 3, mask 0x0010 column 36: offset 2, mask 0x0008 column 37: offset 2, mask 0x1000 column 38: offset 3, mask 0x0400 column 39: offset 1, mask 0x0008 column 40: offset 2, mask 0x0002 column 41: offset 4, mask 0x0008 column 42: offset 3, mask 0x0080 column 43: offset 1, mask 0x8000 column 44: offset 1, mask 0x0400 column 45: offset 0, mask 0x0200 column 46: offset 2, mask 0x0001 column 47: offset 1, mask 0x0080 column 48: offset 0, mask 0x1000 column 49: offset 0, mask 0x0100 column 50: offset 2, mask 0x8000 column 51: offset 1, mask 0x0001 column 52: offset 0, mask 0x8000 column 53: offset 1, mask 0x1000 column 54: offset 0, mask 0x0001 column 55: offset 0, mask 0x0002 column 56: offset 0, mask 0x4000 column 57: offset 4, mask 0x0002 column 58: offset 3, mask 0x0200 column 59: offset 2, mask 0x0400 column 60: offset 2, mask 0x0080 column 61: offset 4, mask 0x0001 column 62: offset 2, mask 0x4000 column 63: offset 2, mask 0x0040 column 64: offset 4, mask 0x1000 column 65: offset 2, mask 0x0020 column 66: offset 4, mask 0x0004 direction bits (1=input) 0x52A3 0x1589 0x943A 0x0680 0x50FC pullup bits (1=pullup) 0x0000 0x0000 0x0000 0x0000 0x0000 test step out_data dont care 1: 0x0000 0x0008 0x700A 0x0400 0x0005 0x5203 0x1481 0x8420 0x0200 0x1000 2: 0x0000 0x8008 0x700A 0x0400 0x0005 0x5003 0x1081 0x8420 0x0200 0x1000 3: 0x0000 0x0008 0x700A 0x0400 0x0005 0x5003 0x1081 0x8420 0x0200 0x1000 4: 0x0000 0x0008 0x700B 0x0400 0x0005 0x4003 0x1001 0x8420 0x0200 0x1000 5: 0x0000 0x0008 0x700A 0x0400 0x0005 0x4003 0x1001 0x8420 0x0200 0x1000 6: 0x0100 0x0008 0x700A 0x0400 0x0005 0x4003 0x1000 0x0420 0x0200 0x1000 7: 0x0000 0x0008 0x700A 0x0400 0x0005 0x4003 0x1000 0x0420 0x0200 0x1000 8: 0xC001 0x0008 0x700A 0x0400 0x0005 0x0000 0x0000 0x0420 0x0200 0x1000 9: 0x4001 0x0008 0x700A 0x0400 0x0005 0x0000 0x0000 0x0420 0x0200 0x1000 10: 0x4001 0x0008 0x700A 0x0400 0x0007 0x0000 0x0000 0x0020 0x0000 0x1000 11: 0x4001 0x0008 0x700A 0x0400 0x0005 0x0000 0x0000 0x0020 0x0000 0x1000 12: 0x4001 0x0008 0x708A 0x0400 0x0005 13: 0x4001 0x0008 0x700A 0x0400 0x0005 14: 0x4001 0x0008 0x700A 0x0400 0x0005 15: 0x4401 0x0008 0x7002 0x0480 0x0005 16: 0x4401 0x0010 0x7002 0x0480 0x000D 17: 0x4601 0x8410 0x7002 0x0480 0x000D 18: 0x4601 0x0410 0x7002 0x0480 0x000D 19: 0x5601 0x0490 0x7003 0x0480 0x000D 20: 0x5601 0x0490 0x7002 0x0480 0x000D 21: 0x5701 0x0491 0xF002 0x0480 0x000D 22: 0x5601 0x0491 0xF002 0x0480 0x000D 23: 0x9602 0x1491 0xF002 0x0480 0x000D 24: 0x1602 0x1491 0xF002 0x0480 0x000D 25: 0x1602 0x1491 0xF402 0x0680 0x000F 26: 0x1602 0x1491 0xF402 0x0680 0x000D 27: 0x1602 0x1491 0xF4A2 0x0680 0x100D 28: 0x1602 0x1491 0xF422 0x0680 0x100D 29: 0x1202 0x1491 0xF42A 0x0600 0x100D 30: 0x1202 0x1489 0xF42A 0x0600 0x1005 31: 0x1202 0x1489 0xF42A 0x0600 0x1005 32: 0x1202 0x1489 0xF42A 0x0600 0x1005 33: 0x1602 0x1489 0xF422 0x0680 0x1005 34: 0x1602 0x9089 0xF422 0x0680 0x1005 35: 0x1602 0x1089 0xF422 0x0680 0x1005 36: 0x1602 0x1091 0xF422 0x0680 0x100D 37: 0x1602 0x9491 0xF422 0x0680 0x100D 38: 0x1602 0x1491 0xF422 0x0680 0x100D 39: 0x1602 0x1491 0xF422 0x0680 0x100D 40: 0x1202 0x1491 0xF42A 0x0600 0x100D 41: 0x1002 0x9491 0xF42A 0x0600 0x100D 42: 0x1002 0x1491 0xF42A 0x0600 0x100D 43: 0x1402 0x1491 0xF422 0x0680 0x100D 44: 0x1602 0x9491 0xF422 0x0680 0x100D 45: 0x1602 0x1491 0xF422 0x0680 0x100D 46: 0x1602 0x1489 0xF422 0x0680 0x1005 47: 0x1602 0x1489 0xF422 0x0680 0x1005 48: 0x1602 0x1409 0xF423 0x0680 0x1005 49: 0x1602 0x1409 0xF422 0x0680 0x1005 50: 0x1602 0x1411 0xF422 0x0680 0x100D 51: 0x1602 0x1491 0xF423 0x0680 0x100D 52: 0x1602 0x1491 0xF422 0x0680 0x100D 53: 0x1602 0x1491 0xF422 0x0680 0x100D 54: 0x1202 0x1491 0xF42A 0x0600 0x100D 55: 0x0202 0x1491 0xF42B 0x0600 0x100D 56: 0x0202 0x1491 0xF42A 0x0600 0x100D 57: 0x0602 0x1491 0xF422 0x0680 0x100D 58: 0x1602 0x1491 0xF423 0x0680 0x100D 59: 0x1602 0x1491 0xF422 0x0680 0x100D 60: 0x1602 0x1489 0xF422 0x0680 0x1005 61: 0x1602 0x1489 0xF422 0x0680 0x1005 62: 0x1702 0x1489 0x7422 0x0680 0x1005 63: 0x1602 0x1489 0x7422 0x0680 0x1005 64: 0x1602 0x1491 0x7422 0x0680 0x100D 65: 0x1702 0x1491 0xF422 0x0680 0x100D 66: 0x1602 0x1491 0xF422 0x0680 0x100D 67: 0x1602 0x1491 0xF422 0x0680 0x100D 68: 0x1202 0x1491 0xF42A 0x0600 0x100D 69: 0x1302 0x1490 0xF42A 0x0600 0x100D 70: 0x1202 0x1490 0xF42A 0x0600 0x100D 71: 0x1602 0x1490 0xF422 0x0680 0x100D 72: 0x1702 0x1491 0xF422 0x0680 0x100D 73: 0x1602 0x1491 0xF422 0x0680 0x100D 74: 0x1602 0x1489 0xF422 0x0680 0x1005 75: 0x1602 0x1489 0xF422 0x0680 0x1005 76: 0x9603 0x0489 0xF422 0x0680 0x1005 77: 0x1603 0x0489 0xF422 0x0680 0x1005 78: 0x1603 0x0491 0xF422 0x0680 0x100D 79: 0x9602 0x1491 0xF422 0x0680 0x100D 80: 0x1602 0x1491 0xF422 0x0680 0x100D 81: 0x1602 0x1491 0xF422 0x0680 0x100D 82: 0x1202 0x1491 0xF42A 0x0600 0x100D 83: 0xD200 0x1491 0xF42A 0x0600 0x100D 84: 0x5200 0x1491 0xF42A 0x0600 0x100D 85: 0x5600 0x1491 0xF422 0x0680 0x100D 86: 0x9602 0x1491 0xF422 0x0680 0x100D 87: 0x1602 0x1491 0xF422 0x0680 0x100D 88: 0x1602 0x1489 0xF422 0x0680 0x1005 89: 0x1602 0x1489 0xF422 0x0680 0x1005 90: 0x1602 0x1489 0xF422 0x0480 0x1007 91: 0x1602 0x1489 0xF422 0x0480 0x1005 92: 0x1602 0x1491 0xF422 0x0480 0x100D 93: 0x1602 0x1491 0xF422 0x0680 0x100F 94: 0x1602 0x1491 0xF422 0x0680 0x100D 95: 0x1602 0x1491 0xF422 0x0680 0x100D 96: 0x1202 0x1491 0xF42A 0x0600 0x100D 97: 0x1202 0x1491 0xF02A 0x0600 0x100F 98: 0x1202 0x1491 0xF02A 0x0600 0x100D 99: 0x1602 0x1491 0xF022 0x0680 0x100D 100: 0x1602 0x1491 0xF422 0x0680 0x100F 101: 0x1602 0x1491 0xF422 0x0680 0x100D 102: 0x1602 0x1489 0xF422 0x0680 0x1005 103: 0x1602 0x1489 0xF422 0x0680 0x1005 104: 0x1602 0x1489 0xF422 0x0480 0x1007 105: 0x1602 0x1489 0xF422 0x0480 0x1005 106: 0x1602 0x1489 0xF4A2 0x0480 0x0005 107: 0x1602 0x1489 0xF422 0x0480 0x0005 108: 0x1602 0x1491 0xF422 0x0480 0x000D 109: 0x1602 0x1491 0xF422 0x0680 0x000F 110: 0x1602 0x1491 0xF422 0x0680 0x000D 111: 0x1602 0x1491 0xF4A2 0x0680 0x100D 112: 0x1602 0x1491 0xF422 0x0680 0x100D 113: 0x1602 0x1491 0xF422 0x0680 0x100D 114: 0x1202 0x1491 0xF42A 0x0600 0x100D 115: 0x1202 0x1491 0xF02A 0x0600 0x100F 116: 0x1202 0x1491 0xF02A 0x0600 0x100D 117: 0x1202 0x1491 0xF08A 0x0600 0x100D 118: 0x1202 0x1491 0xF00A 0x0600 0x100D 119: 0x1602 0x1491 0xF002 0x0680 0x100D 120: 0x1602 0x1491 0xF402 0x0680 0x100F 121: 0x1602 0x1491 0xF402 0x0680 0x100D 122: 0x1602 0x1491 0xF4A2 0x0680 0x100D 123: 0x1602 0x1491 0xF422 0x0680 0x100D 124: 0x1202 0x1489 0xF42A 0x0600 0x1005 125: 0x1206 0x1489 0xF42A 0x0600 0x1005 126: 0x1206 0x3489 0xF42A 0x0600 0x1005 127: 0x1A06 0x3489 0xF42A 0x0600 0x1005 128: 0x1A06 0x348D 0xF42A 0x0600 0x1005 129: 0x1A46 0x348D 0xF42A 0x0600 0x1005 130: 0x1A46 0x368D 0xF42A 0x0600 0x1005 131: 0x1A46 0x368D 0xF62A 0x0600 0x1005 132: 0x1A46 0x368D 0xF62A 0x0E00 0x1005 133: 0x1A46 0x368D 0xF62A 0x8E00 0x1005 134: 0x1A46 0x368D 0xF62A 0x8F00 0x1005 135: 0x1A46 0x368D 0xFE2A 0x8F00 0x1005 136: 0x1A46 0x368D 0xFE2A 0x8F02 0x1005 137: 0x1A46 0x368D 0xFE2A 0xCF02 0x1005 138: 0x1A46 0x368D 0xFE2A 0xCF06 0x1005 139: 0x1A46 0x368D 0xFE2A 0xCF07 0x1005 140: 0x1A46 0x368D 0xFE2A 0xCF47 0x1005 141: 0x1A46 0x368D 0xFE2A 0xCF67 0x1005 142: 0x1A46 0x3687 0xFE22 0xCFE7 0x100D 143: 0x1A46 0x368D 0xFE2A 0xCF67 0x1005 144: 0x1A46 0x3E85 0xFE22 0xCFE7 0x100D 145: 0x1A46 0x368D 0xFE2A 0xCF67 0x1005 146: 0x1A46 0x36C5 0xFE22 0xCFE7 0x100D 147: 0x1A46 0x368D 0xFE2A 0xCF67 0x1005 148: 0x1A46 0x7685 0xFE22 0xCFE7 0x100D 149: 0x1A46 0x368D 0xFE2A 0xCF67 0x1005 150: 0x1A56 0x3685 0xFE22 0xCFE7 0x100D 151: 0x1A46 0x368D 0xFE2A 0xCF67 0x1005 152: 0x1A4E 0x3685 0xFE22 0xCFE7 0x100D 153: 0x1A46 0x368D 0xFE2A 0xCF67 0x1005 154: 0x3A46 0x368D 0xFE22 0xCFE7 0x1005 155: 0x1A46 0x368D 0xFE2A 0xCF67 0x1005 156: 0x1E46 0x368D 0xFE22 0xCFE7 0x1005 157: 0x1A46 0x368D 0xFE2A 0xCF67 0x1005 158: 0x1A46 0x36A5 0xFE2A 0xCF67 0x100D 159: 0x1A46 0x368D 0xFE2A 0xCF67 0x1005 160: 0x1A46 0x3695 0xFE2A 0xCF67 0x100D 161: 0x1A46 0x368D 0xFE2A 0xCF67 0x1005 162: 0x1A46 0x368D 0xEE2A 0xEBE7 0x100D 163: 0x1A46 0x368D 0xFE2A 0xCF67 0x1005 164: 0x1A46 0x368D 0xEE2A 0xDBE7 0x100D 165: 0x1A46 0x368D 0xFE2A 0xCF67 0x1005 166: 0x1A46 0x368D 0xEF2A 0xCBE7 0x100D 167: 0x1A46 0x368D 0xFE2A 0xCF67 0x1005 168: 0x1A46 0x368D 0xEE2A 0xCBE7 0x900D 169: 0x1A46 0x368D 0xFE2A 0xCF67 0x1005 170: 0x1A46 0x368D 0xEE2A 0xCBEF 0x100D 171: 0x1A46 0x368D 0xFE2A 0xCF67 0x1005 172: 0x1A46 0x368D 0xEE2A 0xCBE7 0x300D 173: 0x1A46 0x368D 0xFE2A 0xCF67 0x1005 174: 0x1A46 0x368D 0xFE2A 0xCB77 0x100D 175: 0x1A46 0x368D 0xFE2A 0xCF67 0x1005 176: 0x1202 0x1489 0xF42A 0x0600 0x1005 177: 0x1202 0x1489 0xB42A 0x0600 0x1005 178: 0x1202 0x1489 0xB44A 0x0600 0x1005 179: 0x1202 0x1489 0xB40A 0x0600 0x1005 180: 0x1202 0x1489 0xB40A 0x0600 0x0004 181: 0x1202 0x1489 0xB40A 0x0600 0x1005 182: 0x1202 0x1489 0xB40A 0x0600 0x1005 183: 0x1202 0x1489 0xB44A 0x0600 0x0005 184: 0x1202 0x1489 0xB40A 0x0600 0x0005 185: 0x1202 0x1489 0xB40A 0x0600 0x1004 186: 0x1202 0x1489 0xB40A 0x0600 0x0005 187: 0x1202 0x1489 0xB40A 0x0600 0x0005 188: 0x1202 0x1489 0xB44A 0x0600 0x0005 189: 0x1202 0x1489 0xB40A 0x0600 0x0005 190: 0x1202 0x1489 0xF40A 0x0600 0x0005 191: 0x1202 0x1489 0xF46A 0x0600 0x0005 192: 0x1202 0x1489 0xF42A 0x0600 0x0005 193: 0x1202 0x1489 0xF42A 0x0600 0x0005 194: 0x1202 0x1489 0xF46A 0x0600 0x1005 195: 0x1202 0x1489 0xF42A 0x0600 0x1005 196: 0x1202 0x1489 0xF42A 0x0600 0x1005 197: 0x1202 0x1489 0xF46A 0x0600 0x1005 198: 0x1202 0x1489 0xF42A 0x0600 0x1005 199: 0x1202 0x1489 0xB42A 0x0600 0x1005 200: 0x1202 0x1489 0xB44A 0x0600 0x1005 201: 0x1202 0x1489 0xB40A 0x0600 0x1005 202: 0x1202 0x1489 0xF40A 0x0600 0x1005 203: 0x1202 0x1489 0xF46A 0x0600 0x0005 204: 0x1202 0x1489 0xF42A 0x0600 0x0005 205: 0x1202 0x1489 0xB42A 0x0600 0x0005 206: 0x1202 0x1489 0xB44A 0x0600 0x1005 207: 0x1202 0x1489 0xB40A 0x0600 0x1005 208: 0x1202 0x1489 0xF40A 0x0600 0x1005 209: 0x1202 0x1489 0xF46A 0x0600 0x0005 210: 0x1202 0x1489 0xF42A 0x0600 0x0005 211: 0x1202 0x1489 0xF42A 0x0600 0x0005 212: 0x1202 0x1489 0xF46A 0x0600 0x1005 213: 0x1202 0x1489 0xF42A 0x0600 0x1005 214: 0x1202 0x1489 0xF42A 0x0600 0x1005 PINs used (in edge connector order) (G=ground,P=power) SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBB LETTER ABCDEFHJKLMNPRSTUVABCDEFHJKLMNPRSTUVABCDEFHJKLMNPRSTUVABCDEFHJKLMNPRSTUV SIDE 111111111111111111222222222222222222111111111111111111222222222222222222 USAGE IOIOIIOIIIIOIOIGOIPIGIIIOOOIIOIIIOIOIOIOIIIIIIIOOIIGIOPOGOIIIIIIIIIOIIOO UUT has 44 inputs UUT has 22 outputs contains 66 pins/columns 0 pins are not used contains 214 'test steps' M222 PCB REV B SCHEMATIC REV A LINC TAPE REGISTERS TERMINOLOGY- SIGNALS REFER TO PDP12 MAINT VOL4 M222 SCHEMATIC. BUT... DEC USES AND-NOR GATES TO ROUTE THE ADDER A AND B INPUTS, SO... DEC RENAMED THE ADDER TO NEGATIVE LOGIC TERMS (I.E. A-N + B-N + C-N -> SUM-N, C1-N). (NOT THE 7482 DATASHEET NAMES OF A + B + C -> SUM, C1). SO, WITH ALL 'AND ENABLES' LOW, THE AND-NOR OUTPUTS = HIGH. WITH C-L HIGH, THE ADDER OUTPUT IS SUM-N=1, C1-N=1; THE INVERTED ADDER OUTPUT IS LOW (TAPE BUS). AND THERE IS NO CARRY (C1-N IS HI). THE TWO ADDERS, TWO REGISTER BITS, ETC ARE LABELED BIT 2 (EVEN, MSB) AND BIT 3 (ODD, LSB). THE ADDERS ARE REFERRED TO AS 'ADDER2' (MSB) AND 'ADDER3' (LSB). POWER PINS: AA2 +5V AT1 GROUND AC2 GROUND BA2 +5V BT1 GROUND BC2 GROUND (ALL PINS ARE USED). PINS Main menu Thu Aug 20 18:55:33 2015 test file is: tests\m222.new delay is: 0 trigger is: 1 1 read test file 2 set test delay 3 set test trigger 4 run test 5 output loading test 8 diags 9 exit UUT power is okay Thu Aug 20 18:55:34 2015 space single step O run once (one test, all steps) F run, stop on fail G go (run tests N run, stop on fail, no print S scope (run, no print) C toggle comment printout + increase speed (less delay) - decrease speed (more delay)(slower) Q quit test comment_flag is 1 space single step O run once (one test, all steps) F run, stop on fail G go (run tests N run, stop on fail, no print S scope (run, no print) C toggle comment printout + increase speed (less delay) - decrease speed (more delay)(slower) Q quit test source: ; all registers are unknown source: ; turn on C0, PHASE source: ; with no ENABLES, BUS2,BUS3 is 11, C2 is 1 source: 1000000000000000000000000000000000011111000XX0XX0XX0XXXX0XX0110XX1 changed: step 1 100000000000000000000000000000000001111100010010010010010100110101 source: source: ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; source: ; source: ; set all registers LOW source: ; source: ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; source: source: ; load TMA SETUP from tape bus (00) source: 100 changed: 10 step 2 100000000000000000000000000000000001111100100010010010010100110101 source: 0 changed: 0 step 3 100000000000000000000000000000000001111100000010010010010100110101 source: ; load TMA from tape bus (00) source: 100 changed: 10 step 4 100000000000000000000000000000000001111100000100010010010100110101 source: 0 changed: 0 step 5 100000000000000000000000000000000001111100000000010010010100110101 source: ; load TBN from tape bus (00) source: 100 changed: 10 step 6 100000000000000000000000000000000001111100000000100010010100110101 source: 0 changed: 0 step 7 100000000000000000000000000000000001111100000000000010010100110101 source: ; load TAC from tape bus (00) source: 10101 changed: 101 step 8 100000000000000000000000000000000001111100000000000101010100110101 source: 0 changed: 0 step 9 100000000000000000000000000000000001111100000000000001010100110101 source: ; load TB from tape bus (00) source: 100 changed: 10 step 10 100000000000000000000000000000000001111100000000000001011000110101 source: 0 changed: 0 step 11 100000000000000000000000000000000001111100000000000001010000110101 source: ; load RWB from TB (JAMS CLEAR AND PRESET) source: 1 00 changed: 1 0 step 12 100000000000000000000000000000000001111100000000000001010001110001 source: 0 changed: 0 step 13 100000000000000000000000000000000001111100000000000001010000110001 source: ; (no change) source: 100000000000000000000000000000000001111100000000000001010000110001 changed: step 14 100000000000000000000000000000000001111100000000000001010000110001 source: source: source: ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; source: ; source: ; set all registers HIGH source: ; source: ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; source: source: ; set pin AF1 which clears pin BB2 and sets pin BR2 TAPE BUS 3 OUTPUT source: 1 0 1 changed: 1 0 1 step 15 100000000000010000000000000000000000111101000000000001010000110001 source: ; set pin AP2 which clears pin AN2 and sets pin BV2 TAPE BUS 2 OUTPUT source: 1 0 1 changed: 1 0 1 step 16 100000000000010010000000000000000000110111000000000001010000110001 source: source: source: ; load TMA SETUP from tape bus (11) source: 111 changed: 111 step 17 100000000000010010000000000000000000110111111000000001010000110001 source: 0 changed: 0 step 18 100000000000010010000000000000000000110111011000000001010000110001 source: ; load TMA from tape bus (11) source: 111 changed: 111 step 19 100000000000010010000000000000000000110111011111000001010000110001 source: 0 changed: 0 step 20 100000000000010010000000000000000000110111011011000001010000110001 source: ; load TBN from tape bus (11) source: 111 changed: 111 step 21 100000000000010010000000000000000000110111011011111001010000110001 source: 0 changed: 0 step 22 100000000000010010000000000000000000110111011011011001010000110001 source: ; load TAC from tape bus (11) source: 11010 changed: 11010 step 23 100000000000010010000000000000000000110111011011011110100000110001 source: 0 changed: 0 step 24 100000000000010010000000000000000000110111011011011010100000110001 source: ; load TB from tape bus (11) source: 111 changed: 111 step 25 100000000000010010000000000000000000110111011011011010101110110001 source: 0 changed: 0 step 26 100000000000010010000000000000000000110111011011011010100110110001 source: ; load RWB from TB (JAMS CLEAR AND PRESET) source: 1 11 changed: 1 11 step 27 100000000000010010000000000000000000110111011011011010100111110111 source: 0 changed: 0 step 28 100000000000010010000000000000000000110111011011011010100110110111 source: ; clear pin AF1 (AND with itself) to set pin BB2 (AND-NOR output) and clear pin BR2 TAPE BUS 3 OUTPUT source: 0 1 0 changed: 0 1 0 step 29 100000000000000010000000000000000001110110011011011010100110110111 source: ; clear pin AP2 (AND with itself) to set pin AN2 (AND-NOR output) and clear pin BV2 TAPE BUS 2 OUTPUT source: 0 1 0 changed: 0 1 0 step 30 100000000000000000000000000000000001111100011011011010100110110111 source: ; (no change) source: 100000000000000000000000000000000001111100011011011010100110110111 changed: step 31 100000000000000000000000000000000001111100011011011010100110110111 source: source: ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; source: ; source: ; will all registers high, walk a 0 source: ; source: ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; source: source: source: ; walk a 0, TMA SETUP 2 source: source: source: ; clear pin AP2 which sets pin AN2 and clears pin BV2 TAPE BUS 2 OUTPUT source: 0 1 0 changed: step 32 100000000000000000000000000000000001111100011011011010100110110111 source: ; set pin AF1 which clears pin BB2 and sets pin BR2 TAPE BUS 3 OUTPUT source: 1 0 1 changed: 1 0 1 step 33 100000000000010000000000000000000000111101011011011010100110110111 source: ; load TMA SETUP from tape bus (01) source: 101 changed: 10 step 34 100000000000010000000000000000000000111101101011011010100110110111 source: 0 changed: 0 step 35 100000000000010000000000000000000000111101001011011010100110110111 source: ; restore TMA SETUP 2 source: ; set pin AP2 which clears pin AN2 and sets pin BV2 TAPE BUS 2 OUTPUT source: 1 0 1 changed: 1 0 1 step 36 100000000000010010000000000000000000110111001011011010100110110111 source: ; load TMA SETUP from tape bus (11) source: 111 changed: 11 step 37 100000000000010010000000000000000000110111111011011010100110110111 source: 0 changed: 0 step 38 100000000000010010000000000000000000110111011011011010100110110111 source: source: source: ; walk a 0, TMA SETUP 3 source: source: source: ; set pin AP2 which clears pin AN2 and sets pin BV2 TAPE BUS 2 OUTPUT source: 1 0 1 changed: step 39 100000000000010010000000000000000000110111011011011010100110110111 source: ; clear pin AF1 which sets pin BB2 and clears pin BR2 TAPE BUS 3 OUTPUT source: 0 1 0 changed: 0 1 0 step 40 100000000000000010000000000000000001110110011011011010100110110111 source: ; load TMA SETUP from tape bus (10) source: 110 changed: 1 0 step 41 100000000000000010000000000000000001110110110011011010100110110111 source: 0 changed: 0 step 42 100000000000000010000000000000000001110110010011011010100110110111 source: ; restore TMA SETUP 3 source: ; set pin AF1 which clears pin BB2 and sets pin BR2 TAPE BUS 3 OUTPUT source: 1 0 1 changed: 1 0 1 step 43 100000000000010010000000000000000000110111010011011010100110110111 source: ; load TMA SETUP from tape bus (11) source: 111 changed: 1 1 step 44 100000000000010010000000000000000000110111111011011010100110110111 source: 0 changed: 0 step 45 100000000000010010000000000000000000110111011011011010100110110111 source: source: source: ; walk a 0, TMA 2 source: source: source: ; clear pin AP2 which sets pin AN2 and clears pin BV2 TAPE BUS 2 OUTPUT source: 0 1 0 changed: 0 1 0 step 46 100000000000010000000000000000000000111101011011011010100110110111 source: ; set pin AF1 which clears pin BB2 and sets pin BR2 TAPE BUS 3 OUTPUT source: 1 0 1 changed: step 47 100000000000010000000000000000000000111101011011011010100110110111 source: ; load TMA from tape bus (01) source: 101 changed: 10 step 48 100000000000010000000000000000000000111101011101011010100110110111 source: 0 changed: 0 step 49 100000000000010000000000000000000000111101011001011010100110110111 source: ; restore TMA 2 source: ; set pin AP2 which clears pin AN2 and sets pin BV2 TAPE BUS 2 OUTPUT source: 1 0 1 changed: 1 0 1 step 50 100000000000010010000000000000000000110111011001011010100110110111 source: ; load TMA from tape bus (11) source: 111 changed: 11 step 51 100000000000010010000000000000000000110111011111011010100110110111 source: 0 changed: 0 step 52 100000000000010010000000000000000000110111011011011010100110110111 source: source: source: ; walk a 0, TMA 3 source: source: source: ; set pin AP2 which clears pin AN2 and sets pin BV2 TAPE BUS 2 OUTPUT source: 1 0 1 changed: step 53 100000000000010010000000000000000000110111011011011010100110110111 source: ; clear pin AF1 which sets pin BB2 and clears pin BR2 TAPE BUS 3 OUTPUT source: 0 1 0 changed: 0 1 0 step 54 100000000000000010000000000000000001110110011011011010100110110111 source: ; load TMA from tape bus (10) source: 110 changed: 1 0 step 55 100000000000000010000000000000000001110110011110011010100110110111 source: 0 changed: 0 step 56 100000000000000010000000000000000001110110011010011010100110110111 source: ; restore TMA 3 source: ; set pin AF1 which clears pin BB2 and sets pin BR2 TAPE BUS 3 OUTPUT source: 1 0 1 changed: 1 0 1 step 57 100000000000010010000000000000000000110111011010011010100110110111 source: ; load TMA from tape bus (11) source: 111 changed: 1 1 step 58 100000000000010010000000000000000000110111011111011010100110110111 source: 0 changed: 0 step 59 100000000000010010000000000000000000110111011011011010100110110111 source: source: source: ; walk a 0, TBN 2 source: source: source: ; clear pin AP2 which sets pin AN2 and clears pin BV2 TAPE BUS 2 OUTPUT source: 0 1 0 changed: 0 1 0 step 60 100000000000010000000000000000000000111101011011011010100110110111 source: ; set pin AF1 which clears pin BB2 and sets pin BR2 TAPE BUS 3 OUTPUT source: 1 0 1 changed: step 61 100000000000010000000000000000000000111101011011011010100110110111 source: ; load TBN from tape bus (01) source: 101 changed: 10 step 62 100000000000010000000000000000000000111101011011101010100110110111 source: 0 changed: 0 step 63 100000000000010000000000000000000000111101011011001010100110110111 source: ; restore TBN 2 source: ; set pin AP2 which clears pin AN2 and sets pin BV2 TAPE BUS 2 OUTPUT source: 1 0 1 changed: 1 0 1 step 64 100000000000010010000000000000000000110111011011001010100110110111 source: ; load TBN from tape bus (11) source: 111 changed: 11 step 65 100000000000010010000000000000000000110111011011111010100110110111 source: 0 changed: 0 step 66 100000000000010010000000000000000000110111011011011010100110110111 source: source: source: ; walk a 0, TBN 3 source: source: source: ; set pin AP2 which clears pin AN2 and sets pin BV2 TAPE BUS 2 OUTPUT source: 1 0 1 changed: step 67 100000000000010010000000000000000000110111011011011010100110110111 source: ; clear pin AF1 which sets pin BB2 and clears pin BR2 TAPE BUS 3 OUTPUT source: 0 1 0 changed: 0 1 0 step 68 100000000000000010000000000000000001110110011011011010100110110111 source: ; load TBN from tape bus (10) source: 110 changed: 1 0 step 69 100000000000000010000000000000000001110110011011110010100110110111 source: 0 changed: 0 step 70 100000000000000010000000000000000001110110011011010010100110110111 source: ; restore TBN 3 source: ; set pin AF1 which clears pin BB2 and sets pin BR2 TAPE BUS 3 OUTPUT source: 1 0 1 changed: 1 0 1 step 71 100000000000010010000000000000000000110111011011010010100110110111 source: ; load TBN from tape bus (11) source: 111 changed: 1 1 step 72 100000000000010010000000000000000000110111011011111010100110110111 source: 0 changed: 0 step 73 100000000000010010000000000000000000110111011011011010100110110111 source: source: source: ; walk a 0, TAC 2 source: source: source: ; clear pin AP2 which sets pin AN2 and clears pin BV2 TAPE BUS 2 OUTPUT source: 0 1 0 changed: 0 1 0 step 74 100000000000010000000000000000000000111101011011011010100110110111 source: ; set pin AF1 which clears pin BB2 and sets pin BR2 TAPE BUS 3 OUTPUT source: 1 0 1 changed: step 75 100000000000010000000000000000000000111101011011011010100110110111 source: ; load TAC from tape bus (01) source: 10110 changed: 101 step 76 100000000000010000000000000000000000111101011011011101100110110111 source: 0 changed: 0 step 77 100000000000010000000000000000000000111101011011011001100110110111 source: ; restore TAC 2 source: ; set pin AP2 which clears pin AN2 and sets pin BV2 TAPE BUS 2 OUTPUT source: 1 0 1 changed: 1 0 1 step 78 100000000000010010000000000000000000110111011011011001100110110111 source: ; load TAC from tape bus (11) source: 11010 changed: 110 step 79 100000000000010010000000000000000000110111011011011110100110110111 source: 0 changed: 0 step 80 100000000000010010000000000000000000110111011011011010100110110111 source: source: source: ; walk a 0, TAC 3 source: source: source: ; set pin AP2 which clears pin AN2 and sets pin BV2 TAPE BUS 2 OUTPUT source: 1 0 1 changed: step 81 100000000000010010000000000000000000110111011011011010100110110111 source: ; clear pin AF1 which sets pin BB2 and clears pin BR2 TAPE BUS 3 OUTPUT source: 0 1 0 changed: 0 1 0 step 82 100000000000000010000000000000000001110110011011011010100110110111 source: ; load TAC from tape bus (10) source: 11001 changed: 1 01 step 83 100000000000000010000000000000000001110110011011011110010110110111 source: 0 changed: 0 step 84 100000000000000010000000000000000001110110011011011010010110110111 source: ; restore TAC 3 source: ; set pin AF1 which clears pin BB2 and sets pin BR2 TAPE BUS 3 OUTPUT source: 1 0 1 changed: 1 0 1 step 85 100000000000010010000000000000000000110111011011011010010110110111 source: ; load TAC from tape bus (11) source: 11010 changed: 1 10 step 86 100000000000010010000000000000000000110111011011011110100110110111 source: 0 changed: 0 step 87 100000000000010010000000000000000000110111011011011010100110110111 source: source: source: ; walk a 0, TB 2 source: source: source: ; clear pin AP2 which sets pin AN2 and clears pin BV2 TAPE BUS 2 OUTPUT source: 0 1 0 changed: 0 1 0 step 88 100000000000010000000000000000000000111101011011011010100110110111 source: ; set pin AF1 which clears pin BB2 and sets pin BR2 TAPE BUS 3 OUTPUT source: 1 0 1 changed: step 89 100000000000010000000000000000000000111101011011011010100110110111 source: ; load TB from tape bus (01) source: 101 changed: 10 step 90 100000000000010000000000000000000000111101011011011010101010110111 source: 0 changed: 0 step 91 100000000000010000000000000000000000111101011011011010100010110111 source: ; restore TB 2 source: ; set pin AP2 which clears pin AN2 and sets pin BV2 TAPE BUS 2 OUTPUT source: 1 0 1 changed: 1 0 1 step 92 100000000000010010000000000000000000110111011011011010100010110111 source: ; load TB from tape bus (11) source: 111 changed: 11 step 93 100000000000010010000000000000000000110111011011011010101110110111 source: 0 changed: 0 step 94 100000000000010010000000000000000000110111011011011010100110110111 source: source: source: ; walk a 0, TB 3 source: source: source: ; set pin AP2 which clears pin AN2 and sets pin BV2 TAPE BUS 2 OUTPUT source: 1 0 1 changed: step 95 100000000000010010000000000000000000110111011011011010100110110111 source: ; clear pin AF1 which sets pin BB2 and clears pin BR2 TAPE BUS 3 OUTPUT source: 0 1 0 changed: 0 1 0 step 96 100000000000000010000000000000000001110110011011011010100110110111 source: ; load TB from tape bus (10) source: 110 changed: 1 0 step 97 100000000000000010000000000000000001110110011011011010101100110111 source: 0 changed: 0 step 98 100000000000000010000000000000000001110110011011011010100100110111 source: ; restore TB 3 source: ; set pin AF1 which clears pin BB2 and sets pin BR2 TAPE BUS 3 OUTPUT source: 1 0 1 changed: 1 0 1 step 99 100000000000010010000000000000000000110111011011011010100100110111 source: ; load TB from tape bus (11) source: 111 changed: 1 1 step 100 100000000000010010000000000000000000110111011011011010101110110111 source: 0 changed: 0 step 101 100000000000010010000000000000000000110111011011011010100110110111 source: source: source: ; walk a 0, RWB 2 source: source: source: ; clear pin AP2 which sets pin AN2 and clears pin BV2 TAPE BUS 2 OUTPUT source: 0 1 0 changed: 0 1 0 step 102 100000000000010000000000000000000000111101011011011010100110110111 source: ; set pin AF1 which clears pin BB2 and sets pin BR2 TAPE BUS 3 OUTPUT source: 1 0 1 changed: step 103 100000000000010000000000000000000000111101011011011010100110110111 source: ; load TB from tape bus (01) source: 101 changed: 10 step 104 100000000000010000000000000000000000111101011011011010101010110111 source: 0 changed: 0 step 105 100000000000010000000000000000000000111101011011011010100010110111 source: ; load RWB from TB (JAMS CLEAR AND PRESET) source: 1 01 changed: 1 0 step 106 100000000000010000000000000000000000111101011011011010100011110011 source: 0 changed: 0 step 107 100000000000010000000000000000000000111101011011011010100010110011 source: ; restore TB 2 and RWB 2 source: ; set pin AP2 which clears pin AN2 and sets pin BV2 TAPE BUS 2 OUTPUT source: 1 0 1 changed: 1 0 1 step 108 100000000000010010000000000000000000110111011011011010100010110011 source: ; load TB from tape bus (11) source: 111 changed: 11 step 109 100000000000010010000000000000000000110111011011011010101110110011 source: 0 changed: 0 step 110 100000000000010010000000000000000000110111011011011010100110110011 source: ; load RWB from TB (JAMS CLEAR AND PRESET) source: 1 11 changed: 1 1 step 111 100000000000010010000000000000000000110111011011011010100111110111 source: 0 changed: 0 step 112 100000000000010010000000000000000000110111011011011010100110110111 source: source: source: ; walk a 0, RWB 3 source: source: source: ; set pin AP2 which clears pin AN2 and sets pin BV2 TAPE BUS 2 OUTPUT source: 1 0 1 changed: step 113 100000000000010010000000000000000000110111011011011010100110110111 source: ; clear pin AF1 which sets pin BB2 and clears pin BR2 TAPE BUS 3 OUTPUT source: 0 1 0 changed: 0 1 0 step 114 100000000000000010000000000000000001110110011011011010100110110111 source: ; load TB from tape bus (10) source: 110 changed: 1 0 step 115 100000000000000010000000000000000001110110011011011010101100110111 source: 0 changed: 0 step 116 100000000000000010000000000000000001110110011011011010100100110111 source: ; load RWB from TB (JAMS CLEAR AND PRESET) source: 1 10 changed: 1 0 step 117 100000000000000010000000000000000001110110011011011010100101110101 source: 0 changed: 0 step 118 100000000000000010000000000000000001110110011011011010100100110101 source: ; restore TB 3 and RWB 3 source: ; set pin AF1 which clears pin BB2 and sets pin BR2 TAPE BUS 3 OUTPUT source: 1 0 1 changed: 1 0 1 step 119 100000000000010010000000000000000000110111011011011010100100110101 source: ; load TB from tape bus (11) source: 111 changed: 1 1 step 120 100000000000010010000000000000000000110111011011011010101110110101 source: 0 changed: 0 step 121 100000000000010010000000000000000000110111011011011010100110110101 source: ; load RWB from TB (JAMS CLEAR AND PRESET) source: 1 11 changed: 1 1 step 122 100000000000010010000000000000000000110111011011011010100111110111 source: 0 changed: 0 step 123 100000000000010010000000000000000000110111011011011010100110110111 source: source: ; (no change) source: 100000000000000000000000000000000001111100011011011010100110110111 changed: 0 0 1 1 00 step 124 100000000000000000000000000000000001111100011011011010100110110111 source: source: source: ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; source: ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; source: ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; source: ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; source: ;********************* need to walk a one ********************** source: ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; source: ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; source: ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; source: ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; source: source: ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; source: ; source: ; test AND-NOR logic source: ; source: ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; source: source: ; (all registers are HIGH) source: ; set all pins HIGH except ENABLES source: source: ; set pin AF2 HIGH source: 1 changed: 1 step 125 100001000000000000000000000000000001111100011011011010100110110111 source: ; set pin AM1 HIGH source: 1 changed: 1 step 126 100001100000000000000000000000000001111100011011011010100110110111 source: ; set pin AE1 HIGH source: 1 changed: 1 step 127 100001100100000000000000000000000001111100011011011010100110110111 source: ; set pin AM2 HIGH source: 1 changed: 1 step 128 100001100110000000000000000000000001111100011011011010100110110111 source: ; set pin AB2 HIGH source: 1 changed: 1 step 129 100001100110100000000000000000000001111100011011011010100110110111 source: ; set pin AS1 HIGH source: 1 changed: 1 step 130 100001100110100100000000000000000001111100011011011010100110110111 source: ; set pin BE1 HIGH source: 1 changed: 1 step 131 100001100110100100010000000000000001111100011011011010100110110111 source: ; set pin BM1 HIGH source: 1 changed: 1 step 132 100001100110100100011000000000000001111100011011011010100110110111 source: ; set pin BH1 HIGH source: 1 changed: 1 step 133 100001100110100100011010000000000001111100011011011010100110110111 source: ; set pin BR1 HIGH source: 1 changed: 1 step 134 100001100110100100011011000000000001111100011011011010100110110111 source: ; set pin BC1 HIGH source: 1 changed: 1 step 135 100001100110100100011011010000000001111100011011011010100110110111 source: ; set pin BJ2 HIGH source: 1 changed: 1 step 136 100001100110100100011011011000000001111100011011011010100110110111 source: ; set pin BJ1 HIGH source: 1 changed: 1 step 137 100001100110100100011011011010000001111100011011011010100110110111 source: ; set pin BK2 HIGH source: 1 changed: 1 step 138 100001100110100100011011011011000001111100011011011010100110110111 source: ; set pin BH2 HIGH source: 1 changed: 1 step 139 100001100110100100011011011011010001111100011011011010100110110111 source: ; set pin BP2 HIGH source: 1 changed: 1 step 140 100001100110100100011011011011011001111100011011011010100110110111 source: ; set pin BN2 HIGH source: 1 changed: 1 step 141 100001100110100100011011011011011101111100011011011010100110110111 source: ; toggle each ENABLE source: source: ; set pin AL2 to clear pin BB2 and pin AN2 AND-NOR OUTPUTS and set TAPE BUS 2 OUTPUT and TAPE BUS 3 OUTPUT source: 1 0 0 11 changed: 1 0 0 11 step 142 110001100110100100011011011011011100110111011011011010100110110111 source: 0 1 1 00 changed: 0 1 1 00 step 143 100001100110100100011011011011011101111100011011011010100110110111 source: ; set pin AP1 to clear pin BB2 and pin AN2 AND-NOR OUTPUTS and set TAPE BUS 2 OUTPUT and TAPE BUS 3 OUTPUT source: 1 0 0 11 changed: 1 0 0 11 step 144 101001100110100100011011011011011100110111011011011010100110110111 source: 0 1 1 00 changed: 0 1 1 00 step 145 100001100110100100011011011011011101111100011011011010100110110111 source: ; set pin AS2 to clear pin BB2 and pin AN2 AND-NOR OUTPUTS and set TAPE BUS 2 OUTPUT and TAPE BUS 3 OUTPUT source: 1 0 0 11 changed: 1 0 0 11 step 146 100101100110100100011011011011011100110111011011011010100110110111 source: 0 1 1 00 changed: 0 1 1 00 step 147 100001100110100100011011011011011101111100011011011010100110110111 source: ; set pin AL1 to clear pin BB2 and pin AN2 AND-NOR OUTPUTS and set TAPE BUS 2 OUTPUT and TAPE BUS 3 OUTPUT source: 1 0 0 11 changed: 1 0 0 11 step 148 100011100110100100011011011011011100110111011011011010100110110111 source: 0 1 1 00 changed: 0 1 1 00 step 149 100001100110100100011011011011011101111100011011011010100110110111 source: ; set pin AL1 to clear pin BB2 and pin AN2 AND-NOR OUTPUTS and set TAPE BUS 2 OUTPUT and TAPE BUS 3 OUTPUT source: 1 0 0 11 changed: 1 0 0 11 step 150 100001110110100100011011011011011100110111011011011010100110110111 source: 0 1 1 00 changed: 0 1 1 00 step 151 100001100110100100011011011011011101111100011011011010100110110111 source: ; set pin AE2 to clear pin BB2 and pin AN2 AND-NOR OUTPUTS and set TAPE BUS 2 OUTPUT and TAPE BUS 3 OUTPUT source: 1 0 0 11 changed: 1 0 0 11 step 152 100001101110100100011011011011011100110111011011011010100110110111 source: 0 1 1 00 changed: 0 1 1 00 step 153 100001100110100100011011011011011101111100011011011010100110110111 source: ; set pin AC1 to clear pin BB2 and set TAPE BUS 3 OUTPUT source: 1 0 1 changed: 1 0 1 step 154 100001100111100100011011011011011100111101011011011010100110110111 source: 0 1 0 changed: 0 1 0 step 155 100001100110100100011011011011011101111100011011011010100110110111 source: ; set pin AF1 to clear pin BB2 and set TAPE BUS 3 OUTPUT source: 1 0 1 changed: 1 0 1 step 156 100001100110110100011011011011011100111101011011011010100110110111 source: 0 1 0 changed: 0 1 0 step 157 100001100110100100011011011011011101111100011011011010100110110111 source: ; set pin AR2 to clear pin AN2 AND-NOR OUTPUTS and set TAPE BUS 2 OUTPUT source: 1 0 1 changed: 1 0 1 step 158 100001100110101100011011011011011101110110011011011010100110110111 source: 0 1 0 changed: 0 1 0 step 159 100001100110100100011011011011011101111100011011011010100110110111 source: ; set pin AP2 to clear pin AN2 AND-NOR OUTPUTS and set TAPE BUS 2 OUTPUT source: 1 0 1 changed: 1 0 1 step 160 100001100110100110011011011011011101110110011011011010100110110111 source: 0 1 0 changed: 0 1 0 step 161 100001100110100100011011011011011101111100011011011010100110110111 source: source: ; set pin BK1 to clear pin BB1 and pin BN1 AND-NOR OUTPUTS and set TAPE BUS 2 OUTPUT and TAPE BUS 3 OUTPUT source: 1 00 11 changed: 1 00 11 step 162 100001100110100101011011011011011101001111011011011010100110110111 source: 0 11 00 changed: 0 11 00 step 163 100001100110100100011011011011011101111100011011011010100110110111 source: ; set pin BL1 to clear pin BB1 and pin BN1 AND-NOR OUTPUTS and set TAPE BUS 2 OUTPUT and TAPE BUS 3 OUTPUT source: 1 00 11 changed: 1 00 11 step 164 100001100110100100111011011011011101001111011011011010100110110111 source: 0 11 00 changed: 0 11 00 step 165 100001100110100100011011011011011101111100011011011010100110110111 source: ; set pin BF1 to clear pin BB1 and pin BN1 AND-NOR OUTPUTS and set TAPE BUS 2 OUTPUT and TAPE BUS 3 OUTPUT source: 1 00 11 changed: 1 00 11 step 166 100001100110100100011111011011011101001111011011011010100110110111 source: 0 11 00 changed: 0 11 00 step 167 100001100110100100011011011011011101111100011011011010100110110111 source: ; set pin BS1 to clear pin BB1 and pin BN1 AND-NOR OUTPUTS and set TAPE BUS 2 OUTPUT and TAPE BUS 3 OUTPUT source: 1 00 11 changed: 1 00 11 step 168 100001100110100100011011111011011101001111011011011010100110110111 source: 0 11 00 changed: 0 11 00 step 169 100001100110100100011011011011011101111100011011011010100110110111 source: ; set pin BL2 to clear pin BB1 and pin BN1 AND-NOR OUTPUTS and set TAPE BUS 2 OUTPUT and TAPE BUS 3 OUTPUT source: 1 00 11 changed: 1 00 11 step 170 100001100110100100011011011111011101001111011011011010100110110111 source: 0 11 00 changed: 0 11 00 step 171 100001100110100100011011011011011101111100011011011010100110110111 source: ; set pin BU1 to clear pin BB1 and pin BN1 AND-NOR OUTPUTS and set TAPE BUS 2 OUTPUT and TAPE BUS 3 OUTPUT source: 1 00 11 changed: 1 00 11 step 172 100001100110100100011011011011111101001111011011011010100110110111 source: 0 11 00 changed: 0 11 00 step 173 100001100110100100011011011011011101111100011011011010100110110111 source: ; set pin BM2 to clear pin BB1 and TAPE BUS 3 OUTPUT source: 1 0 1 changed: 1 0 1 step 174 100001100110100100011011011011011111101110011011011010100110110111 source: 0 1 0 changed: 0 1 0 step 175 100001100110100100011011011011011101111100011011011010100110110111 source: ; no change source: 100000000000000000000000000000000001111100011011011010100110110111 changed: 00 00 0 0 00 00 00 00 000 step 176 100000000000000000000000000000000001111100011011011010100110110111 source: source: source: ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; source: ; test shifting the RWB source: ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; source: source: ; shift in 0, expect 10 source: 0 changed: 0 step 177 100000000000000000000000000000000001111100011011011010100110100111 source: 110 changed: 1 0 step 178 100000000000000000000000000000000001111100011011011010100110101101 source: 0 changed: 0 step 179 100000000000000000000000000000000001111100011011011010100110100101 source: ; toggle phase should toggle RWB 2 source: 0 0 changed: 0 0 step 180 100000000000000000000000000000000001111100011011011010100110000001 source: 1 1 changed: 1 1 step 181 100000000000000000000000000000000001111100011011011010100110100101 source: source: ; shift in 0, expect 00 source: 0 changed: step 182 100000000000000000000000000000000001111100011011011010100110100101 source: 100 changed: 10 step 183 100000000000000000000000000000000001111100011011011010100110101001 source: 0 changed: 0 step 184 100000000000000000000000000000000001111100011011011010100110100001 source: ; toggle phase should toggle RWB 2 source: 0 1 changed: 0 1 step 185 100000000000000000000000000000000001111100011011011010100110000101 source: 1 0 changed: 1 0 step 186 100000000000000000000000000000000001111100011011011010100110100001 source: source: ; shift in 0, expect 00 source: 0 changed: step 187 100000000000000000000000000000000001111100011011011010100110100001 source: 100 changed: 1 step 188 100000000000000000000000000000000001111100011011011010100110101001 source: 0 changed: 0 step 189 100000000000000000000000000000000001111100011011011010100110100001 source: ; shift in 1, expect 01 source: 1 changed: 1 step 190 100000000000000000000000000000000001111100011011011010100110110001 source: 101 changed: 1 1 step 191 100000000000000000000000000000000001111100011011011010100110111011 source: 0 changed: 0 step 192 100000000000000000000000000000000001111100011011011010100110110011 source: ; shift in 1, expect 11 source: 1 changed: step 193 100000000000000000000000000000000001111100011011011010100110110011 source: 111 changed: 11 step 194 100000000000000000000000000000000001111100011011011010100110111111 source: 0 changed: 0 step 195 100000000000000000000000000000000001111100011011011010100110110111 source: ; shift in 1, expect 11 source: 1 changed: step 196 100000000000000000000000000000000001111100011011011010100110110111 source: 111 changed: 1 step 197 100000000000000000000000000000000001111100011011011010100110111111 source: 0 changed: 0 step 198 100000000000000000000000000000000001111100011011011010100110110111 source: ; shift in 0, expect 10 source: 0 changed: 0 step 199 100000000000000000000000000000000001111100011011011010100110100111 source: 110 changed: 1 0 step 200 100000000000000000000000000000000001111100011011011010100110101101 source: 0 changed: 0 step 201 100000000000000000000000000000000001111100011011011010100110100101 source: ; shift in 1, expect 01 source: 1 changed: 1 step 202 100000000000000000000000000000000001111100011011011010100110110101 source: 101 changed: 101 step 203 100000000000000000000000000000000001111100011011011010100110111011 source: 0 changed: 0 step 204 100000000000000000000000000000000001111100011011011010100110110011 source: ; shift in 0, expect 10 source: 0 changed: 0 step 205 100000000000000000000000000000000001111100011011011010100110100011 source: 110 changed: 110 step 206 100000000000000000000000000000000001111100011011011010100110101101 source: 0 changed: 0 step 207 100000000000000000000000000000000001111100011011011010100110100101 source: ; shift in 1, expect 01 source: 1 changed: 1 step 208 100000000000000000000000000000000001111100011011011010100110110101 source: 101 changed: 101 step 209 100000000000000000000000000000000001111100011011011010100110111011 source: 0 changed: 0 step 210 100000000000000000000000000000000001111100011011011010100110110011 source: ; shift in 1, expect 11 source: 1 changed: step 211 100000000000000000000000000000000001111100011011011010100110110011 source: 111 changed: 11 step 212 100000000000000000000000000000000001111100011011011010100110111111 source: 0 changed: 0 step 213 100000000000000000000000000000000001111100011011011010100110110111 source: ; no change source: 100000000000000000000000000000000001111100011011011010100110110111 changed: step 214 100000000000000000000000000000000001111100011011011010100110110111 test 1: pass SLOT BAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBAABBAAAAAAAAAAAAAABBBBBABBBB LETTER ALPSLFMDEEMCBFRSPKLEMFHRSCJLJKUHPNMBBNNVVRKRHUTDJUKANJHBTPDFSVEVDU SIDE 121212122121212121111111112212122222112222111221112112212112212122 DIRECTION IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIOOOOOOOIOOIOOIOOIOOOOIOOIIIIOOO this fail all fails was hi 111111111111111111111111111111111111111111111111111111111111111111 rising ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ ^^^^^^^^^^^^^^^^^^^^^^^^^ falling vvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvv vvvvvvvvvvvvvvvvvvvvvvvvv was lo 00000000000000000000000000000000000000 0000000000000000000000000 total fails 0, total passes 1 source: ; all registers are unknown source: ; turn on C0, PHASE source: ; with no ENABLES, BUS2,BUS3 is 11, C2 is 1 source: 1000000000000000000000000000000000011111000XX0XX0XX0XXXX0XX0110XX1 changed: step 1 100000000000000000000000000000000001111100011011011010100110110111 source: source: ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; source: ; source: ; set all registers LOW source: ; source: ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; source: source: ; load TMA SETUP from tape bus (00) source: 100 changed: 100 step 2 100000000000000000000000000000000001111100100011011010100110110111 source: 0 changed: 0 step 3 100000000000000000000000000000000001111100000011011010100110110111 source: ; load TMA from tape bus (00) source: 100 changed: 100 step 4 100000000000000000000000000000000001111100000100011010100110110111 source: 0 changed: 0 step 5 100000000000000000000000000000000001111100000000011010100110110111 source: ; load TBN from tape bus (00) source: 100 changed: 100 step 6 100000000000000000000000000000000001111100000000100010100110110111 source: 0 changed: 0 step 7 100000000000000000000000000000000001111100000000000010100110110111 source: ; load TAC from tape bus (00) source: 10101 changed: 10101 step 8 100000000000000000000000000000000001111100000000000101010110110111 source: 0 changed: 0 step 9 100000000000000000000000000000000001111100000000000001010110110111 source: ; load TB from tape bus (00) source: 100 changed: 100 step 10 100000000000000000000000000000000001111100000000000001011000110111 source: 0 changed: 0 step 11 100000000000000000000000000000000001111100000000000001010000110111 source: ; load RWB from TB (JAMS CLEAR AND PRESET) source: 1 00 changed: 1 00 step 12 100000000000000000000000000000000001111100000000000001010001110001 source: 0 changed: 0 step 13 100000000000000000000000000000000001111100000000000001010000110001 source: ; (no change) source: 100000000000000000000000000000000001111100000000000001010000110001 changed: step 14 100000000000000000000000000000000001111100000000000001010000110001 source: source: source: ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; source: ; source: ; set all registers HIGH source: ; source: ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; source: source: ; set pin AF1 which clears pin BB2 and sets pin BR2 TAPE BUS 3 OUTPUT source: 1 0 1 changed: 1 0 1 step 15 100000000000010000000000000000000000111101000000000001010000110001 source: ; set pin AP2 which clears pin AN2 and sets pin BV2 TAPE BUS 2 OUTPUT source: 1 0 1 changed: 1 0 1 step 16 100000000000010010000000000000000000110111000000000001010000110001 source: source: source: ; load TMA SETUP from tape bus (11) source: 111 changed: 111 step 17 100000000000010010000000000000000000110111111000000001010000110001 source: 0 changed: 0 step 18 100000000000010010000000000000000000110111011000000001010000110001 source: ; load TMA from tape bus (11) source: 111 changed: 111 step 19 100000000000010010000000000000000000110111011111000001010000110001 source: 0 changed: 0 step 20 100000000000010010000000000000000000110111011011000001010000110001 source: ; load TBN from tape bus (11) source: 111 changed: 111 step 21 100000000000010010000000000000000000110111011011111001010000110001 source: 0 changed: 0 step 22 100000000000010010000000000000000000110111011011011001010000110001 source: ; load TAC from tape bus (11) source: 11010 changed: 11010 step 23 100000000000010010000000000000000000110111011011011110100000110001 source: 0 changed: 0 step 24 100000000000010010000000000000000000110111011011011010100000110001 source: ; load TB from tape bus (11) source: 111 changed: 111 step 25 100000000000010010000000000000000000110111011011011010101110110001 source: 0 changed: 0 step 26 100000000000010010000000000000000000110111011011011010100110110001 source: ; load RWB from TB (JAMS CLEAR AND PRESET) source: 1 11 changed: 1 11 step 27 100000000000010010000000000000000000110111011011011010100111110111 source: 0 changed: 0 step 28 100000000000010010000000000000000000110111011011011010100110110111 source: ; clear pin AF1 (AND with itself) to set pin BB2 (AND-NOR output) and clear pin BR2 TAPE BUS 3 OUTPUT source: 0 1 0 changed: 0 1 0 step 29 100000000000000010000000000000000001110110011011011010100110110111 source: ; clear pin AP2 (AND with itself) to set pin AN2 (AND-NOR output) and clear pin BV2 TAPE BUS 2 OUTPUT source: 0 1 0 changed: 0 1 0 step 30 100000000000000000000000000000000001111100011011011010100110110111 source: ; (no change) source: 100000000000000000000000000000000001111100011011011010100110110111 changed: step 31 100000000000000000000000000000000001111100011011011010100110110111 source: source: ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; source: ; source: ; will all registers high, walk a 0 source: ; source: ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; source: source: source: ; walk a 0, TMA SETUP 2 source: source: source: ; clear pin AP2 which sets pin AN2 and clears pin BV2 TAPE BUS 2 OUTPUT source: 0 1 0 changed: step 32 100000000000000000000000000000000001111100011011011010100110110111 source: ; set pin AF1 which clears pin BB2 and sets pin BR2 TAPE BUS 3 OUTPUT source: 1 0 1 changed: 1 0 1 step 33 100000000000010000000000000000000000111101011011011010100110110111 source: ; load TMA SETUP from tape bus (01) source: 101 changed: 10 step 34 100000000000010000000000000000000000111101101011011010100110110111 source: 0 changed: 0 step 35 100000000000010000000000000000000000111101001011011010100110110111 source: ; restore TMA SETUP 2 source: ; set pin AP2 which clears pin AN2 and sets pin BV2 TAPE BUS 2 OUTPUT source: 1 0 1 changed: 1 0 1 step 36 100000000000010010000000000000000000110111001011011010100110110111 source: ; load TMA SETUP from tape bus (11) source: 111 changed: 11 step 37 100000000000010010000000000000000000110111111011011010100110110111 source: 0 changed: 0 step 38 100000000000010010000000000000000000110111011011011010100110110111 source: source: source: ; walk a 0, TMA SETUP 3 source: source: source: ; set pin AP2 which clears pin AN2 and sets pin BV2 TAPE BUS 2 OUTPUT source: 1 0 1 changed: step 39 100000000000010010000000000000000000110111011011011010100110110111 source: ; clear pin AF1 which sets pin BB2 and clears pin BR2 TAPE BUS 3 OUTPUT source: 0 1 0 changed: 0 1 0 step 40 100000000000000010000000000000000001110110011011011010100110110111 source: ; load TMA SETUP from tape bus (10) source: 110 changed: 1 0 step 41 100000000000000010000000000000000001110110110011011010100110110111 source: 0 changed: 0 step 42 100000000000000010000000000000000001110110010011011010100110110111 source: ; restore TMA SETUP 3 source: ; set pin AF1 which clears pin BB2 and sets pin BR2 TAPE BUS 3 OUTPUT source: 1 0 1 changed: 1 0 1 step 43 100000000000010010000000000000000000110111010011011010100110110111 source: ; load TMA SETUP from tape bus (11) source: 111 changed: 1 1 step 44 100000000000010010000000000000000000110111111011011010100110110111 source: 0 changed: 0 step 45 100000000000010010000000000000000000110111011011011010100110110111 source: source: source: ; walk a 0, TMA 2 source: source: source: ; clear pin AP2 which sets pin AN2 and clears pin BV2 TAPE BUS 2 OUTPUT source: 0 1 0 changed: 0 1 0 step 46 100000000000010000000000000000000000111101011011011010100110110111 source: ; set pin AF1 which clears pin BB2 and sets pin BR2 TAPE BUS 3 OUTPUT source: 1 0 1 changed: step 47 100000000000010000000000000000000000111101011011011010100110110111 source: ; load TMA from tape bus (01) source: 101 changed: 10 step 48 100000000000010000000000000000000000111101011101011010100110110111 source: 0 changed: 0 step 49 100000000000010000000000000000000000111101011001011010100110110111 source: ; restore TMA 2 source: ; set pin AP2 which clears pin AN2 and sets pin BV2 TAPE BUS 2 OUTPUT source: 1 0 1 changed: 1 0 1 step 50 100000000000010010000000000000000000110111011001011010100110110111 source: ; load TMA from tape bus (11) source: 111 changed: 11 step 51 100000000000010010000000000000000000110111011111011010100110110111 source: 0 changed: 0 step 52 100000000000010010000000000000000000110111011011011010100110110111 source: source: source: ; walk a 0, TMA 3 source: source: source: ; set pin AP2 which clears pin AN2 and sets pin BV2 TAPE BUS 2 OUTPUT source: 1 0 1 changed: step 53 100000000000010010000000000000000000110111011011011010100110110111 source: ; clear pin AF1 which sets pin BB2 and clears pin BR2 TAPE BUS 3 OUTPUT source: 0 1 0 changed: 0 1 0 step 54 100000000000000010000000000000000001110110011011011010100110110111 source: ; load TMA from tape bus (10) source: 110 changed: 1 0 step 55 100000000000000010000000000000000001110110011110011010100110110111 source: 0 changed: 0 step 56 100000000000000010000000000000000001110110011010011010100110110111 source: ; restore TMA 3 source: ; set pin AF1 which clears pin BB2 and sets pin BR2 TAPE BUS 3 OUTPUT source: 1 0 1 changed: 1 0 1 step 57 100000000000010010000000000000000000110111011010011010100110110111 source: ; load TMA from tape bus (11) source: 111 changed: 1 1 step 58 100000000000010010000000000000000000110111011111011010100110110111 source: 0 changed: 0 step 59 100000000000010010000000000000000000110111011011011010100110110111 source: source: source: ; walk a 0, TBN 2 source: source: source: ; clear pin AP2 which sets pin AN2 and clears pin BV2 TAPE BUS 2 OUTPUT source: 0 1 0 changed: 0 1 0 step 60 100000000000010000000000000000000000111101011011011010100110110111 source: ; set pin AF1 which clears pin BB2 and sets pin BR2 TAPE BUS 3 OUTPUT source: 1 0 1 changed: step 61 100000000000010000000000000000000000111101011011011010100110110111 source: ; load TBN from tape bus (01) source: 101 changed: 10 step 62 100000000000010000000000000000000000111101011011101010100110110111 source: 0 changed: 0 step 63 100000000000010000000000000000000000111101011011001010100110110111 source: ; restore TBN 2 source: ; set pin AP2 which clears pin AN2 and sets pin BV2 TAPE BUS 2 OUTPUT source: 1 0 1 changed: 1 0 1 step 64 100000000000010010000000000000000000110111011011001010100110110111 source: ; load TBN from tape bus (11) source: 111 changed: 11 step 65 100000000000010010000000000000000000110111011011111010100110110111 source: 0 changed: 0 step 66 100000000000010010000000000000000000110111011011011010100110110111 source: source: source: ; walk a 0, TBN 3 source: source: source: ; set pin AP2 which clears pin AN2 and sets pin BV2 TAPE BUS 2 OUTPUT source: 1 0 1 changed: step 67 100000000000010010000000000000000000110111011011011010100110110111 source: ; clear pin AF1 which sets pin BB2 and clears pin BR2 TAPE BUS 3 OUTPUT source: 0 1 0 changed: 0 1 0 step 68 100000000000000010000000000000000001110110011011011010100110110111 source: ; load TBN from tape bus (10) source: 110 changed: 1 0 step 69 100000000000000010000000000000000001110110011011110010100110110111 source: 0 changed: 0 step 70 100000000000000010000000000000000001110110011011010010100110110111 source: ; restore TBN 3 source: ; set pin AF1 which clears pin BB2 and sets pin BR2 TAPE BUS 3 OUTPUT source: 1 0 1 changed: 1 0 1 step 71 100000000000010010000000000000000000110111011011010010100110110111 source: ; load TBN from tape bus (11) source: 111 changed: 1 1 step 72 100000000000010010000000000000000000110111011011111010100110110111 source: 0 changed: 0 step 73 100000000000010010000000000000000000110111011011011010100110110111 source: source: source: ; walk a 0, TAC 2 source: source: source: ; clear pin AP2 which sets pin AN2 and clears pin BV2 TAPE BUS 2 OUTPUT source: 0 1 0 changed: 0 1 0 step 74 100000000000010000000000000000000000111101011011011010100110110111 source: ; set pin AF1 which clears pin BB2 and sets pin BR2 TAPE BUS 3 OUTPUT source: 1 0 1 changed: step 75 100000000000010000000000000000000000111101011011011010100110110111 source: ; load TAC from tape bus (01) source: 10110 changed: 101 step 76 100000000000010000000000000000000000111101011011011101100110110111 source: 0 changed: 0 step 77 100000000000010000000000000000000000111101011011011001100110110111 source: ; restore TAC 2 source: ; set pin AP2 which clears pin AN2 and sets pin BV2 TAPE BUS 2 OUTPUT source: 1 0 1 changed: 1 0 1 step 78 100000000000010010000000000000000000110111011011011001100110110111 source: ; load TAC from tape bus (11) source: 11010 changed: 110 step 79 100000000000010010000000000000000000110111011011011110100110110111 source: 0 changed: 0 step 80 100000000000010010000000000000000000110111011011011010100110110111 source: source: source: ; walk a 0, TAC 3 source: source: source: ; set pin AP2 which clears pin AN2 and sets pin BV2 TAPE BUS 2 OUTPUT source: 1 0 1 changed: step 81 100000000000010010000000000000000000110111011011011010100110110111 source: ; clear pin AF1 which sets pin BB2 and clears pin BR2 TAPE BUS 3 OUTPUT source: 0 1 0 changed: 0 1 0 step 82 100000000000000010000000000000000001110110011011011010100110110111 source: ; load TAC from tape bus (10) source: 11001 changed: 1 01 step 83 100000000000000010000000000000000001110110011011011110010110110111 source: 0 changed: 0 step 84 100000000000000010000000000000000001110110011011011010010110110111 source: ; restore TAC 3 source: ; set pin AF1 which clears pin BB2 and sets pin BR2 TAPE BUS 3 OUTPUT source: 1 0 1 changed: 1 0 1 step 85 100000000000010010000000000000000000110111011011011010010110110111 source: ; load TAC from tape bus (11) source: 11010 changed: 1 10 step 86 100000000000010010000000000000000000110111011011011110100110110111 source: 0 changed: 0 step 87 100000000000010010000000000000000000110111011011011010100110110111 source: source: source: ; walk a 0, TB 2 source: source: source: ; clear pin AP2 which sets pin AN2 and clears pin BV2 TAPE BUS 2 OUTPUT source: 0 1 0 changed: 0 1 0 step 88 100000000000010000000000000000000000111101011011011010100110110111 source: ; set pin AF1 which clears pin BB2 and sets pin BR2 TAPE BUS 3 OUTPUT source: 1 0 1 changed: step 89 100000000000010000000000000000000000111101011011011010100110110111 source: ; load TB from tape bus (01) source: 101 changed: 10 step 90 100000000000010000000000000000000000111101011011011010101010110111 source: 0 changed: 0 step 91 100000000000010000000000000000000000111101011011011010100010110111 source: ; restore TB 2 source: ; set pin AP2 which clears pin AN2 and sets pin BV2 TAPE BUS 2 OUTPUT source: 1 0 1 changed: 1 0 1 step 92 100000000000010010000000000000000000110111011011011010100010110111 source: ; load TB from tape bus (11) source: 111 changed: 11 step 93 100000000000010010000000000000000000110111011011011010101110110111 source: 0 changed: 0 step 94 100000000000010010000000000000000000110111011011011010100110110111 source: source: source: ; walk a 0, TB 3 source: source: source: ; set pin AP2 which clears pin AN2 and sets pin BV2 TAPE BUS 2 OUTPUT source: 1 0 1 changed: step 95 100000000000010010000000000000000000110111011011011010100110110111 source: ; clear pin AF1 which sets pin BB2 and clears pin BR2 TAPE BUS 3 OUTPUT source: 0 1 0 changed: 0 1 0 step 96 100000000000000010000000000000000001110110011011011010100110110111 source: ; load TB from tape bus (10) source: 110 changed: 1 0 step 97 100000000000000010000000000000000001110110011011011010101100110111 source: 0 changed: 0 step 98 100000000000000010000000000000000001110110011011011010100100110111 source: ; restore TB 3 source: ; set pin AF1 which clears pin BB2 and sets pin BR2 TAPE BUS 3 OUTPUT source: 1 0 1 changed: 1 0 1 step 99 100000000000010010000000000000000000110111011011011010100100110111 source: ; load TB from tape bus (11) source: 111 changed: 1 1 step 100 100000000000010010000000000000000000110111011011011010101110110111 source: 0 changed: 0 step 101 100000000000010010000000000000000000110111011011011010100110110111 source: source: source: ; walk a 0, RWB 2 source: source: source: ; clear pin AP2 which sets pin AN2 and clears pin BV2 TAPE BUS 2 OUTPUT source: 0 1 0 changed: 0 1 0 step 102 100000000000010000000000000000000000111101011011011010100110110111 source: ; set pin AF1 which clears pin BB2 and sets pin BR2 TAPE BUS 3 OUTPUT source: 1 0 1 changed: step 103 100000000000010000000000000000000000111101011011011010100110110111 source: ; load TB from tape bus (01) source: 101 changed: 10 step 104 100000000000010000000000000000000000111101011011011010101010110111 source: 0 changed: 0 step 105 100000000000010000000000000000000000111101011011011010100010110111 source: ; load RWB from TB (JAMS CLEAR AND PRESET) source: 1 01 changed: 1 0 step 106 100000000000010000000000000000000000111101011011011010100011110011 source: 0 changed: 0 step 107 100000000000010000000000000000000000111101011011011010100010110011 source: ; restore TB 2 and RWB 2 source: ; set pin AP2 which clears pin AN2 and sets pin BV2 TAPE BUS 2 OUTPUT source: 1 0 1 changed: 1 0 1 step 108 100000000000010010000000000000000000110111011011011010100010110011 source: ; load TB from tape bus (11) source: 111 changed: 11 step 109 100000000000010010000000000000000000110111011011011010101110110011 source: 0 changed: 0 step 110 100000000000010010000000000000000000110111011011011010100110110011 source: ; load RWB from TB (JAMS CLEAR AND PRESET) source: 1 11 changed: 1 1 step 111 100000000000010010000000000000000000110111011011011010100111110111 source: 0 changed: 0 step 112 100000000000010010000000000000000000110111011011011010100110110111 source: source: source: ; walk a 0, RWB 3 source: source: source: ; set pin AP2 which clears pin AN2 and sets pin BV2 TAPE BUS 2 OUTPUT source: 1 0 1 changed: step 113 100000000000010010000000000000000000110111011011011010100110110111 source: ; clear pin AF1 which sets pin BB2 and clears pin BR2 TAPE BUS 3 OUTPUT source: 0 1 0 changed: 0 1 0 step 114 100000000000000010000000000000000001110110011011011010100110110111 source: ; load TB from tape bus (10) source: 110 changed: 1 0 step 115 100000000000000010000000000000000001110110011011011010101100110111 source: 0 changed: 0 step 116 100000000000000010000000000000000001110110011011011010100100110111 source: ; load RWB from TB (JAMS CLEAR AND PRESET) source: 1 10 changed: 1 0 step 117 100000000000000010000000000000000001110110011011011010100101110101 source: 0 changed: 0 step 118 100000000000000010000000000000000001110110011011011010100100110101 source: ; restore TB 3 and RWB 3 source: ; set pin AF1 which clears pin BB2 and sets pin BR2 TAPE BUS 3 OUTPUT source: 1 0 1 changed: 1 0 1 step 119 100000000000010010000000000000000000110111011011011010100100110101 source: ; load TB from tape bus (11) source: 111 changed: 1 1 step 120 100000000000010010000000000000000000110111011011011010101110110101 source: 0 changed: 0 step 121 100000000000010010000000000000000000110111011011011010100110110101 source: ; load RWB from TB (JAMS CLEAR AND PRESET) source: 1 11 changed: 1 1 step 122 100000000000010010000000000000000000110111011011011010100111110111 source: 0 changed: 0 step 123 100000000000010010000000000000000000110111011011011010100110110111 source: source: ; (no change) source: 100000000000000000000000000000000001111100011011011010100110110111 changed: 0 0 1 1 00 step 124 100000000000000000000000000000000001111100011011011010100110110111 source: source: source: ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; source: ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; source: ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; source: ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; source: ;********************* need to walk a one ********************** source: ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; source: ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; source: ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; source: ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; source: source: ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; source: ; source: ; test AND-NOR logic source: ; source: ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; source: source: ; (all registers are HIGH) source: ; set all pins HIGH except ENABLES source: source: ; set pin AF2 HIGH source: 1 changed: 1 step 125 100001000000000000000000000000000001111100011011011010100110110111 source: ; set pin AM1 HIGH source: 1 changed: 1 step 126 100001100000000000000000000000000001111100011011011010100110110111 source: ; set pin AE1 HIGH source: 1 changed: 1 step 127 100001100100000000000000000000000001111100011011011010100110110111 source: ; set pin AM2 HIGH source: 1 changed: 1 step 128 100001100110000000000000000000000001111100011011011010100110110111 source: ; set pin AB2 HIGH source: 1 changed: 1 step 129 100001100110100000000000000000000001111100011011011010100110110111 source: ; set pin AS1 HIGH source: 1 changed: 1 step 130 100001100110100100000000000000000001111100011011011010100110110111 source: ; set pin BE1 HIGH source: 1 changed: 1 step 131 100001100110100100010000000000000001111100011011011010100110110111 source: ; set pin BM1 HIGH source: 1 changed: 1 step 132 100001100110100100011000000000000001111100011011011010100110110111 source: ; set pin BH1 HIGH source: 1 changed: 1 step 133 100001100110100100011010000000000001111100011011011010100110110111 source: ; set pin BR1 HIGH source: 1 changed: 1 step 134 100001100110100100011011000000000001111100011011011010100110110111 source: ; set pin BC1 HIGH source: 1 changed: 1 step 135 100001100110100100011011010000000001111100011011011010100110110111 source: ; set pin BJ2 HIGH source: 1 changed: 1 step 136 100001100110100100011011011000000001111100011011011010100110110111 source: ; set pin BJ1 HIGH source: 1 changed: 1 step 137 100001100110100100011011011010000001111100011011011010100110110111 source: ; set pin BK2 HIGH source: 1 changed: 1 step 138 100001100110100100011011011011000001111100011011011010100110110111 source: ; set pin BH2 HIGH source: 1 changed: 1 step 139 100001100110100100011011011011010001111100011011011010100110110111 source: ; set pin BP2 HIGH source: 1 changed: 1 step 140 100001100110100100011011011011011001111100011011011010100110110111 source: ; set pin BN2 HIGH source: 1 changed: 1 step 141 100001100110100100011011011011011101111100011011011010100110110111 source: ; toggle each ENABLE source: source: ; set pin AL2 to clear pin BB2 and pin AN2 AND-NOR OUTPUTS and set TAPE BUS 2 OUTPUT and TAPE BUS 3 OUTPUT source: 1 0 0 11 changed: 1 0 0 11 step 142 110001100110100100011011011011011100110111011011011010100110110111 source: 0 1 1 00 changed: 0 1 1 00 step 143 100001100110100100011011011011011101111100011011011010100110110111 source: ; set pin AP1 to clear pin BB2 and pin AN2 AND-NOR OUTPUTS and set TAPE BUS 2 OUTPUT and TAPE BUS 3 OUTPUT source: 1 0 0 11 changed: 1 0 0 11 step 144 101001100110100100011011011011011100110111011011011010100110110111 source: 0 1 1 00 changed: 0 1 1 00 step 145 100001100110100100011011011011011101111100011011011010100110110111 source: ; set pin AS2 to clear pin BB2 and pin AN2 AND-NOR OUTPUTS and set TAPE BUS 2 OUTPUT and TAPE BUS 3 OUTPUT source: 1 0 0 11 changed: 1 0 0 11 step 146 100101100110100100011011011011011100110111011011011010100110110111 source: 0 1 1 00 changed: 0 1 1 00 step 147 100001100110100100011011011011011101111100011011011010100110110111 source: ; set pin AL1 to clear pin BB2 and pin AN2 AND-NOR OUTPUTS and set TAPE BUS 2 OUTPUT and TAPE BUS 3 OUTPUT source: 1 0 0 11 changed: 1 0 0 11 step 148 100011100110100100011011011011011100110111011011011010100110110111 source: 0 1 1 00 changed: 0 1 1 00 step 149 100001100110100100011011011011011101111100011011011010100110110111 source: ; set pin AL1 to clear pin BB2 and pin AN2 AND-NOR OUTPUTS and set TAPE BUS 2 OUTPUT and TAPE BUS 3 OUTPUT source: 1 0 0 11 changed: 1 0 0 11 step 150 100001110110100100011011011011011100110111011011011010100110110111 source: 0 1 1 00 changed: 0 1 1 00 step 151 100001100110100100011011011011011101111100011011011010100110110111 source: ; set pin AE2 to clear pin BB2 and pin AN2 AND-NOR OUTPUTS and set TAPE BUS 2 OUTPUT and TAPE BUS 3 OUTPUT source: 1 0 0 11 changed: 1 0 0 11 step 152 100001101110100100011011011011011100110111011011011010100110110111 source: 0 1 1 00 changed: 0 1 1 00 step 153 100001100110100100011011011011011101111100011011011010100110110111 source: ; set pin AC1 to clear pin BB2 and set TAPE BUS 3 OUTPUT source: 1 0 1 changed: 1 0 1 step 154 100001100111100100011011011011011100111101011011011010100110110111 source: 0 1 0 changed: 0 1 0 step 155 100001100110100100011011011011011101111100011011011010100110110111 source: ; set pin AF1 to clear pin BB2 and set TAPE BUS 3 OUTPUT source: 1 0 1 changed: 1 0 1 step 156 100001100110110100011011011011011100111101011011011010100110110111 source: 0 1 0 changed: 0 1 0 step 157 100001100110100100011011011011011101111100011011011010100110110111 source: ; set pin AR2 to clear pin AN2 AND-NOR OUTPUTS and set TAPE BUS 2 OUTPUT source: 1 0 1 changed: 1 0 1 step 158 100001100110101100011011011011011101110110011011011010100110110111 source: 0 1 0 changed: 0 1 0 step 159 100001100110100100011011011011011101111100011011011010100110110111 source: ; set pin AP2 to clear pin AN2 AND-NOR OUTPUTS and set TAPE BUS 2 OUTPUT source: 1 0 1 changed: 1 0 1 step 160 100001100110100110011011011011011101110110011011011010100110110111 source: 0 1 0 changed: 0 1 0 step 161 100001100110100100011011011011011101111100011011011010100110110111 source: source: ; set pin BK1 to clear pin BB1 and pin BN1 AND-NOR OUTPUTS and set TAPE BUS 2 OUTPUT and TAPE BUS 3 OUTPUT source: 1 00 11 changed: 1 00 11 step 162 100001100110100101011011011011011101001111011011011010100110110111 source: 0 11 00 changed: 0 11 00 step 163 100001100110100100011011011011011101111100011011011010100110110111 source: ; set pin BL1 to clear pin BB1 and pin BN1 AND-NOR OUTPUTS and set TAPE BUS 2 OUTPUT and TAPE BUS 3 OUTPUT source: 1 00 11 changed: 1 00 11 step 164 100001100110100100111011011011011101001111011011011010100110110111 source: 0 11 00 changed: 0 11 00 step 165 100001100110100100011011011011011101111100011011011010100110110111 source: ; set pin BF1 to clear pin BB1 and pin BN1 AND-NOR OUTPUTS and set TAPE BUS 2 OUTPUT and TAPE BUS 3 OUTPUT source: 1 00 11 changed: 1 00 11 step 166 100001100110100100011111011011011101001111011011011010100110110111 source: 0 11 00 changed: 0 11 00 step 167 100001100110100100011011011011011101111100011011011010100110110111 source: ; set pin BS1 to clear pin BB1 and pin BN1 AND-NOR OUTPUTS and set TAPE BUS 2 OUTPUT and TAPE BUS 3 OUTPUT source: 1 00 11 changed: 1 00 11 step 168 100001100110100100011011111011011101001111011011011010100110110111 source: 0 11 00 changed: 0 11 00 step 169 100001100110100100011011011011011101111100011011011010100110110111 source: ; set pin BL2 to clear pin BB1 and pin BN1 AND-NOR OUTPUTS and set TAPE BUS 2 OUTPUT and TAPE BUS 3 OUTPUT source: 1 00 11 changed: 1 00 11 step 170 100001100110100100011011011111011101001111011011011010100110110111 source: 0 11 00 changed: 0 11 00 step 171 100001100110100100011011011011011101111100011011011010100110110111 source: ; set pin BU1 to clear pin BB1 and pin BN1 AND-NOR OUTPUTS and set TAPE BUS 2 OUTPUT and TAPE BUS 3 OUTPUT source: 1 00 11 changed: 1 00 11 step 172 100001100110100100011011011011111101001111011011011010100110110111 source: 0 11 00 changed: 0 11 00 step 173 100001100110100100011011011011011101111100011011011010100110110111 source: ; set pin BM2 to clear pin BB1 and TAPE BUS 3 OUTPUT source: 1 0 1 changed: 1 0 1 step 174 100001100110100100011011011011011111101110011011011010100110110111 source: 0 1 0 changed: 0 1 0 step 175 100001100110100100011011011011011101111100011011011010100110110111 source: ; no change source: 100000000000000000000000000000000001111100011011011010100110110111 changed: 00 00 0 0 00 00 00 00 000 step 176 100000000000000000000000000000000001111100011011011010100110110111 source: source: source: ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; source: ; test shifting the RWB source: ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; source: source: ; shift in 0, expect 10 source: 0 changed: 0 step 177 100000000000000000000000000000000001111100011011011010100110100111 source: 110 changed: 1 0 step 178 100000000000000000000000000000000001111100011011011010100110101101 source: 0 changed: 0 step 179 100000000000000000000000000000000001111100011011011010100110100101 source: ; toggle phase should toggle RWB 2 source: 0 0 changed: 0 0 step 180 100000000000000000000000000000000001111100011011011010100110000001 source: 1 1 changed: 1 1 step 181 100000000000000000000000000000000001111100011011011010100110100101 source: source: ; shift in 0, expect 00 source: 0 changed: step 182 100000000000000000000000000000000001111100011011011010100110100101 source: 100 changed: 10 step 183 100000000000000000000000000000000001111100011011011010100110101001 source: 0 changed: 0 step 184 100000000000000000000000000000000001111100011011011010100110100001 source: ; toggle phase should toggle RWB 2 source: 0 1 changed: 0 1 step 185 100000000000000000000000000000000001111100011011011010100110000101 source: 1 0 changed: 1 0 step 186 100000000000000000000000000000000001111100011011011010100110100001 source: source: ; shift in 0, expect 00 source: 0 changed: step 187 100000000000000000000000000000000001111100011011011010100110100001 source: 100 changed: 1 step 188 100000000000000000000000000000000001111100011011011010100110101001 source: 0 changed: 0 step 189 100000000000000000000000000000000001111100011011011010100110100001 source: ; shift in 1, expect 01 source: 1 changed: 1 step 190 100000000000000000000000000000000001111100011011011010100110110001 source: 101 changed: 1 1 step 191 100000000000000000000000000000000001111100011011011010100110111011 source: 0 changed: 0 step 192 100000000000000000000000000000000001111100011011011010100110110011 source: ; shift in 1, expect 11 source: 1 changed: step 193 100000000000000000000000000000000001111100011011011010100110110011 source: 111 changed: 11 step 194 100000000000000000000000000000000001111100011011011010100110111111 source: 0 changed: 0 step 195 100000000000000000000000000000000001111100011011011010100110110111 source: ; shift in 1, expect 11 source: 1 changed: step 196 100000000000000000000000000000000001111100011011011010100110110111 source: 111 changed: 1 step 197 100000000000000000000000000000000001111100011011011010100110111111 source: 0 changed: 0 step 198 100000000000000000000000000000000001111100011011011010100110110111 source: ; shift in 0, expect 10 source: 0 changed: 0 step 199 100000000000000000000000000000000001111100011011011010100110100111 source: 110 changed: 1 0 step 200 100000000000000000000000000000000001111100011011011010100110101101 source: 0 changed: 0 step 201 100000000000000000000000000000000001111100011011011010100110100101 source: ; shift in 1, expect 01 source: 1 changed: 1 step 202 100000000000000000000000000000000001111100011011011010100110110101 source: 101 changed: 101 step 203 100000000000000000000000000000000001111100011011011010100110111011 source: 0 changed: 0 step 204 100000000000000000000000000000000001111100011011011010100110110011 source: ; shift in 0, expect 10 source: 0 changed: 0 step 205 100000000000000000000000000000000001111100011011011010100110100011 source: 110 changed: 110 step 206 100000000000000000000000000000000001111100011011011010100110101101 source: 0 changed: 0 step 207 100000000000000000000000000000000001111100011011011010100110100101 source: ; shift in 1, expect 01 source: 1 changed: 1 step 208 100000000000000000000000000000000001111100011011011010100110110101 source: 101 changed: 101 step 209 100000000000000000000000000000000001111100011011011010100110111011 source: 0 changed: 0 step 210 100000000000000000000000000000000001111100011011011010100110110011 source: ; shift in 1, expect 11 source: 1 changed: step 211 100000000000000000000000000000000001111100011011011010100110110011 source: 111 changed: 11 step 212 100000000000000000000000000000000001111100011011011010100110111111 source: 0 changed: 0 step 213 100000000000000000000000000000000001111100011011011010100110110111 source: ; no change source: 100000000000000000000000000000000001111100011011011010100110110111 changed: step 214 100000000000000000000000000000000001111100011011011010100110110111 test 2: pass SLOT BAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBAABBAAAAAAAAAAAAAABBBBBABBBB LETTER ALPSLFMDEEMCBFRSPKLEMFHRSCJLJKUHPNMBBNNVVRKRHUTDJUKANJHBTPDFSVEVDU SIDE 121212122121212121111111112212122222112222111221112112212112212122 DIRECTION IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIOOOOOOOIOOIOOIOOIOOOOIOOIIIIOOO this fail all fails was hi 111111111111111111111111111111111111111111111111111111111111111111 rising ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ ^^^^^^^^^^^^^^^^^^^^^^^^^ falling vvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvv vvvvvvvvvvvvvvvvvvvvvvvvv was lo 00000000000000000000000000000000000000 0000000000000000000000000 total fails 0, total passes 2 source: ; all registers are unknown source: ; turn on C0, PHASE source: ; with no ENABLES, BUS2,BUS3 is 11, C2 is 1 source: 1000000000000000000000000000000000011111000XX0XX0XX0XXXX0XX0110XX1 changed: step 1 100000000000000000000000000000000001111100011011011010100110110111 source: source: ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; source: ; source: ; set all registers LOW source: ; source: ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; source: source: ; load TMA SETUP from tape bus (00) source: 100 changed: 100 step 2 100000000000000000000000000000000001111100100011011010100110110111 source: 0 changed: 0 step 3 100000000000000000000000000000000001111100000011011010100110110111 source: ; load TMA from tape bus (00) source: 100 changed: 100 step 4 100000000000000000000000000000000001111100000100011010100110110111 source: 0 changed: 0 step 5 100000000000000000000000000000000001111100000000011010100110110111 source: ; load TBN from tape bus (00) source: 100 changed: 100 step 6 100000000000000000000000000000000001111100000000100010100110110111 source: 0 changed: 0 step 7 100000000000000000000000000000000001111100000000000010100110110111 source: ; load TAC from tape bus (00) source: 10101 changed: 10101 step 8 100000000000000000000000000000000001111100000000000101010110110111 source: 0 changed: 0 step 9 100000000000000000000000000000000001111100000000000001010110110111 source: ; load TB from tape bus (00) source: 100 changed: 100 step 10 100000000000000000000000000000000001111100000000000001011000110111 source: 0 changed: 0 step 11 100000000000000000000000000000000001111100000000000001010000110111 source: ; load RWB from TB (JAMS CLEAR AND PRESET) source: 1 00 changed: 1 00 step 12 100000000000000000000000000000000001111100000000000001010001110001 source: 0 changed: 0 step 13 100000000000000000000000000000000001111100000000000001010000110001 source: ; (no change) source: 100000000000000000000000000000000001111100000000000001010000110001 changed: step 14 100000000000000000000000000000000001111100000000000001010000110001 source: source: source: ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; source: ; source: ; set all registers HIGH source: ; source: ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; source: source: ; set pin AF1 which clears pin BB2 and sets pin BR2 TAPE BUS 3 OUTPUT source: 1 0 1 changed: 1 0 1 step 15 100000000000010000000000000000000000111101000000000001010000110001 source: ; set pin AP2 which clears pin AN2 and sets pin BV2 TAPE BUS 2 OUTPUT source: 1 0 1 changed: 1 0 1 step 16 100000000000010010000000000000000000110111000000000001010000110001 source: source: source: ; load TMA SETUP from tape bus (11) source: 111 changed: 111 step 17 100000000000010010000000000000000000110111111000000001010000110001 source: 0 changed: 0 step 18 100000000000010010000000000000000000110111011000000001010000110001 source: ; load TMA from tape bus (11) source: 111 changed: 111 step 19 100000000000010010000000000000000000110111011111000001010000110001 source: 0 changed: 0 step 20 100000000000010010000000000000000000110111011011000001010000110001 source: ; load TBN from tape bus (11) source: 111 changed: 111 step 21 100000000000010010000000000000000000110111011011111001010000110001 source: 0 changed: 0 step 22 100000000000010010000000000000000000110111011011011001010000110001 source: ; load TAC from tape bus (11) source: 11010 changed: 11010 step 23 100000000000010010000000000000000000110111011011011110100000110001 source: 0 changed: 0 step 24 100000000000010010000000000000000000110111011011011010100000110001 source: ; load TB from tape bus (11) source: 111 changed: 111 step 25 100000000000010010000000000000000000110111011011011010101110110001 source: 0 changed: 0 step 26 100000000000010010000000000000000000110111011011011010100110110001 source: ; load RWB from TB (JAMS CLEAR AND PRESET) source: 1 11 changed: 1 11 step 27 100000000000010010000000000000000000110111011011011010100111110111 source: 0 changed: 0 step 28 100000000000010010000000000000000000110111011011011010100110110111 source: ; clear pin AF1 (AND with itself) to set pin BB2 (AND-NOR output) and clear pin BR2 TAPE BUS 3 OUTPUT source: 0 1 0 changed: 0 1 0 step 29 100000000000000010000000000000000001110110011011011010100110110111 source: ; clear pin AP2 (AND with itself) to set pin AN2 (AND-NOR output) and clear pin BV2 TAPE BUS 2 OUTPUT source: 0 1 0 changed: 0 1 0 step 30 100000000000000000000000000000000001111100011011011010100110110111 source: ; (no change) source: 100000000000000000000000000000000001111100011011011010100110110111 changed: step 31 100000000000000000000000000000000001111100011011011010100110110111 source: source: ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; source: ; source: ; will all registers high, walk a 0 source: ; source: ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; source: source: source: ; walk a 0, TMA SETUP 2 source: source: source: ; clear pin AP2 which sets pin AN2 and clears pin BV2 TAPE BUS 2 OUTPUT source: 0 1 0 changed: step 32 100000000000000000000000000000000001111100011011011010100110110111 source: ; set pin AF1 which clears pin BB2 and sets pin BR2 TAPE BUS 3 OUTPUT source: 1 0 1 changed: 1 0 1 step 33 100000000000010000000000000000000000111101011011011010100110110111 source: ; load TMA SETUP from tape bus (01) source: 101 changed: 10 step 34 100000000000010000000000000000000000111101101011011010100110110111 source: 0 changed: 0 step 35 100000000000010000000000000000000000111101001011011010100110110111 source: ; restore TMA SETUP 2 source: ; set pin AP2 which clears pin AN2 and sets pin BV2 TAPE BUS 2 OUTPUT source: 1 0 1 changed: 1 0 1 step 36 100000000000010010000000000000000000110111001011011010100110110111 source: ; load TMA SETUP from tape bus (11) source: 111 changed: 11 step 37 100000000000010010000000000000000000110111111011011010100110110111 source: 0 changed: 0 step 38 100000000000010010000000000000000000110111011011011010100110110111 source: source: source: ; walk a 0, TMA SETUP 3 source: source: source: ; set pin AP2 which clears pin AN2 and sets pin BV2 TAPE BUS 2 OUTPUT source: 1 0 1 changed: step 39 100000000000010010000000000000000000110111011011011010100110110111 source: ; clear pin AF1 which sets pin BB2 and clears pin BR2 TAPE BUS 3 OUTPUT source: 0 1 0 changed: 0 1 0 step 40 100000000000000010000000000000000001110110011011011010100110110111 source: ; load TMA SETUP from tape bus (10) source: 110 changed: 1 0 step 41 100000000000000010000000000000000001110110110011011010100110110111 source: 0 changed: 0 step 42 100000000000000010000000000000000001110110010011011010100110110111 source: ; restore TMA SETUP 3 source: ; set pin AF1 which clears pin BB2 and sets pin BR2 TAPE BUS 3 OUTPUT source: 1 0 1 changed: 1 0 1 step 43 100000000000010010000000000000000000110111010011011010100110110111 source: ; load TMA SETUP from tape bus (11) source: 111 changed: 1 1 step 44 100000000000010010000000000000000000110111111011011010100110110111 source: 0 changed: 0 step 45 100000000000010010000000000000000000110111011011011010100110110111 source: source: source: ; walk a 0, TMA 2 source: source: source: ; clear pin AP2 which sets pin AN2 and clears pin BV2 TAPE BUS 2 OUTPUT source: 0 1 0 changed: 0 1 0 step 46 100000000000010000000000000000000000111101011011011010100110110111 source: ; set pin AF1 which clears pin BB2 and sets pin BR2 TAPE BUS 3 OUTPUT source: 1 0 1 changed: step 47 100000000000010000000000000000000000111101011011011010100110110111 source: ; load TMA from tape bus (01) source: 101 changed: 10 step 48 100000000000010000000000000000000000111101011101011010100110110111 source: 0 changed: 0 step 49 100000000000010000000000000000000000111101011001011010100110110111 source: ; restore TMA 2 source: ; set pin AP2 which clears pin AN2 and sets pin BV2 TAPE BUS 2 OUTPUT source: 1 0 1 changed: 1 0 1 step 50 100000000000010010000000000000000000110111011001011010100110110111 source: ; load TMA from tape bus (11) source: 111 changed: 11 step 51 100000000000010010000000000000000000110111011111011010100110110111 source: 0 changed: 0 step 52 100000000000010010000000000000000000110111011011011010100110110111 source: source: source: ; walk a 0, TMA 3 source: source: source: ; set pin AP2 which clears pin AN2 and sets pin BV2 TAPE BUS 2 OUTPUT source: 1 0 1 changed: step 53 100000000000010010000000000000000000110111011011011010100110110111 source: ; clear pin AF1 which sets pin BB2 and clears pin BR2 TAPE BUS 3 OUTPUT source: 0 1 0 changed: 0 1 0 step 54 100000000000000010000000000000000001110110011011011010100110110111 source: ; load TMA from tape bus (10) source: 110 changed: 1 0 step 55 100000000000000010000000000000000001110110011110011010100110110111 source: 0 changed: 0 step 56 100000000000000010000000000000000001110110011010011010100110110111 source: ; restore TMA 3 source: ; set pin AF1 which clears pin BB2 and sets pin BR2 TAPE BUS 3 OUTPUT source: 1 0 1 changed: 1 0 1 step 57 100000000000010010000000000000000000110111011010011010100110110111 source: ; load TMA from tape bus (11) source: 111 changed: 1 1 step 58 100000000000010010000000000000000000110111011111011010100110110111 source: 0 changed: 0 step 59 100000000000010010000000000000000000110111011011011010100110110111 source: source: source: ; walk a 0, TBN 2 source: source: source: ; clear pin AP2 which sets pin AN2 and clears pin BV2 TAPE BUS 2 OUTPUT source: 0 1 0 changed: 0 1 0 step 60 100000000000010000000000000000000000111101011011011010100110110111 source: ; set pin AF1 which clears pin BB2 and sets pin BR2 TAPE BUS 3 OUTPUT source: 1 0 1 changed: step 61 100000000000010000000000000000000000111101011011011010100110110111 source: ; load TBN from tape bus (01) source: 101 changed: 10 step 62 100000000000010000000000000000000000111101011011101010100110110111 source: 0 changed: 0 step 63 100000000000010000000000000000000000111101011011001010100110110111 source: ; restore TBN 2 source: ; set pin AP2 which clears pin AN2 and sets pin BV2 TAPE BUS 2 OUTPUT source: 1 0 1 changed: 1 0 1 step 64 100000000000010010000000000000000000110111011011001010100110110111 source: ; load TBN from tape bus (11) source: 111 changed: 11 step 65 100000000000010010000000000000000000110111011011111010100110110111 source: 0 changed: 0 step 66 100000000000010010000000000000000000110111011011011010100110110111 source: source: source: ; walk a 0, TBN 3 source: source: source: ; set pin AP2 which clears pin AN2 and sets pin BV2 TAPE BUS 2 OUTPUT source: 1 0 1 changed: step 67 100000000000010010000000000000000000110111011011011010100110110111 source: ; clear pin AF1 which sets pin BB2 and clears pin BR2 TAPE BUS 3 OUTPUT source: 0 1 0 changed: 0 1 0 step 68 100000000000000010000000000000000001110110011011011010100110110111 source: ; load TBN from tape bus (10) source: 110 changed: 1 0 step 69 100000000000000010000000000000000001110110011011110010100110110111 source: 0 changed: 0 step 70 100000000000000010000000000000000001110110011011010010100110110111 source: ; restore TBN 3 source: ; set pin AF1 which clears pin BB2 and sets pin BR2 TAPE BUS 3 OUTPUT source: 1 0 1 changed: 1 0 1 step 71 100000000000010010000000000000000000110111011011010010100110110111 source: ; load TBN from tape bus (11) source: 111 changed: 1 1 step 72 100000000000010010000000000000000000110111011011111010100110110111 source: 0 changed: 0 step 73 100000000000010010000000000000000000110111011011011010100110110111 source: source: source: ; walk a 0, TAC 2 source: source: source: ; clear pin AP2 which sets pin AN2 and clears pin BV2 TAPE BUS 2 OUTPUT source: 0 1 0 changed: 0 1 0 step 74 100000000000010000000000000000000000111101011011011010100110110111 source: ; set pin AF1 which clears pin BB2 and sets pin BR2 TAPE BUS 3 OUTPUT source: 1 0 1 changed: step 75 100000000000010000000000000000000000111101011011011010100110110111 source: ; load TAC from tape bus (01) source: 10110 changed: 101 step 76 100000000000010000000000000000000000111101011011011101100110110111 source: 0 changed: 0 step 77 100000000000010000000000000000000000111101011011011001100110110111 source: ; restore TAC 2 source: ; set pin AP2 which clears pin AN2 and sets pin BV2 TAPE BUS 2 OUTPUT source: 1 0 1 changed: 1 0 1 step 78 100000000000010010000000000000000000110111011011011001100110110111 source: ; load TAC from tape bus (11) source: 11010 changed: 110 step 79 100000000000010010000000000000000000110111011011011110100110110111 source: 0 changed: 0 step 80 100000000000010010000000000000000000110111011011011010100110110111 source: source: source: ; walk a 0, TAC 3 source: source: source: ; set pin AP2 which clears pin AN2 and sets pin BV2 TAPE BUS 2 OUTPUT source: 1 0 1 changed: step 81 100000000000010010000000000000000000110111011011011010100110110111 source: ; clear pin AF1 which sets pin BB2 and clears pin BR2 TAPE BUS 3 OUTPUT source: 0 1 0 changed: 0 1 0 step 82 100000000000000010000000000000000001110110011011011010100110110111 source: ; load TAC from tape bus (10) source: 11001 changed: 1 01 step 83 100000000000000010000000000000000001110110011011011110010110110111 source: 0 changed: 0 step 84 100000000000000010000000000000000001110110011011011010010110110111 source: ; restore TAC 3 source: ; set pin AF1 which clears pin BB2 and sets pin BR2 TAPE BUS 3 OUTPUT source: 1 0 1 changed: 1 0 1 step 85 100000000000010010000000000000000000110111011011011010010110110111 source: ; load TAC from tape bus (11) source: 11010 changed: 1 10 step 86 100000000000010010000000000000000000110111011011011110100110110111 source: 0 changed: 0 step 87 100000000000010010000000000000000000110111011011011010100110110111 source: source: source: ; walk a 0, TB 2 source: source: source: ; clear pin AP2 which sets pin AN2 and clears pin BV2 TAPE BUS 2 OUTPUT source: 0 1 0 changed: 0 1 0 step 88 100000000000010000000000000000000000111101011011011010100110110111 source: ; set pin AF1 which clears pin BB2 and sets pin BR2 TAPE BUS 3 OUTPUT source: 1 0 1 changed: step 89 100000000000010000000000000000000000111101011011011010100110110111 source: ; load TB from tape bus (01) source: 101 changed: 10 step 90 100000000000010000000000000000000000111101011011011010101010110111 source: 0 changed: 0 step 91 100000000000010000000000000000000000111101011011011010100010110111 source: ; restore TB 2 source: ; set pin AP2 which clears pin AN2 and sets pin BV2 TAPE BUS 2 OUTPUT source: 1 0 1 changed: 1 0 1 step 92 100000000000010010000000000000000000110111011011011010100010110111 source: ; load TB from tape bus (11) source: 111 changed: 11 step 93 100000000000010010000000000000000000110111011011011010101110110111 source: 0 changed: 0 step 94 100000000000010010000000000000000000110111011011011010100110110111 source: source: source: ; walk a 0, TB 3 source: source: source: ; set pin AP2 which clears pin AN2 and sets pin BV2 TAPE BUS 2 OUTPUT source: 1 0 1 changed: step 95 100000000000010010000000000000000000110111011011011010100110110111 source: ; clear pin AF1 which sets pin BB2 and clears pin BR2 TAPE BUS 3 OUTPUT source: 0 1 0 changed: 0 1 0 step 96 100000000000000010000000000000000001110110011011011010100110110111 source: ; load TB from tape bus (10) source: 110 changed: 1 0 step 97 100000000000000010000000000000000001110110011011011010101100110111 source: 0 changed: 0 step 98 100000000000000010000000000000000001110110011011011010100100110111 source: ; restore TB 3 source: ; set pin AF1 which clears pin BB2 and sets pin BR2 TAPE BUS 3 OUTPUT source: 1 0 1 changed: 1 0 1 step 99 100000000000010010000000000000000000110111011011011010100100110111 source: ; load TB from tape bus (11) source: 111 changed: 1 1 step 100 100000000000010010000000000000000000110111011011011010101110110111 source: 0 changed: 0 step 101 100000000000010010000000000000000000110111011011011010100110110111 source: source: source: ; walk a 0, RWB 2 source: source: source: ; clear pin AP2 which sets pin AN2 and clears pin BV2 TAPE BUS 2 OUTPUT source: 0 1 0 changed: 0 1 0 step 102 100000000000010000000000000000000000111101011011011010100110110111 source: ; set pin AF1 which clears pin BB2 and sets pin BR2 TAPE BUS 3 OUTPUT source: 1 0 1 changed: step 103 100000000000010000000000000000000000111101011011011010100110110111 source: ; load TB from tape bus (01) source: 101 changed: 10 step 104 100000000000010000000000000000000000111101011011011010101010110111 source: 0 changed: 0 step 105 100000000000010000000000000000000000111101011011011010100010110111 source: ; load RWB from TB (JAMS CLEAR AND PRESET) source: 1 01 changed: 1 0 step 106 100000000000010000000000000000000000111101011011011010100011110011 source: 0 changed: 0 step 107 100000000000010000000000000000000000111101011011011010100010110011 source: ; restore TB 2 and RWB 2 source: ; set pin AP2 which clears pin AN2 and sets pin BV2 TAPE BUS 2 OUTPUT source: 1 0 1 changed: 1 0 1 step 108 100000000000010010000000000000000000110111011011011010100010110011 source: ; load TB from tape bus (11) source: 111 changed: 11 step 109 100000000000010010000000000000000000110111011011011010101110110011 source: 0 changed: 0 step 110 100000000000010010000000000000000000110111011011011010100110110011 source: ; load RWB from TB (JAMS CLEAR AND PRESET) source: 1 11 changed: 1 1 step 111 100000000000010010000000000000000000110111011011011010100111110111 source: 0 changed: 0 step 112 100000000000010010000000000000000000110111011011011010100110110111 source: source: source: ; walk a 0, RWB 3 source: source: source: ; set pin AP2 which clears pin AN2 and sets pin BV2 TAPE BUS 2 OUTPUT source: 1 0 1 changed: step 113 100000000000010010000000000000000000110111011011011010100110110111 source: ; clear pin AF1 which sets pin BB2 and clears pin BR2 TAPE BUS 3 OUTPUT source: 0 1 0 changed: 0 1 0 step 114 100000000000000010000000000000000001110110011011011010100110110111 source: ; load TB from tape bus (10) source: 110 changed: 1 0 step 115 100000000000000010000000000000000001110110011011011010101100110111 source: 0 changed: 0 step 116 100000000000000010000000000000000001110110011011011010100100110111 source: ; load RWB from TB (JAMS CLEAR AND PRESET) source: 1 10 changed: 1 0 step 117 100000000000000010000000000000000001110110011011011010100101110101 source: 0 changed: 0 step 118 100000000000000010000000000000000001110110011011011010100100110101 source: ; restore TB 3 and RWB 3 source: ; set pin AF1 which clears pin BB2 and sets pin BR2 TAPE BUS 3 OUTPUT source: 1 0 1 changed: 1 0 1 step 119 100000000000010010000000000000000000110111011011011010100100110101 source: ; load TB from tape bus (11) source: 111 changed: 1 1 step 120 100000000000010010000000000000000000110111011011011010101110110101 source: 0 changed: 0 step 121 100000000000010010000000000000000000110111011011011010100110110101 source: ; load RWB from TB (JAMS CLEAR AND PRESET) source: 1 11 changed: 1 1 step 122 100000000000010010000000000000000000110111011011011010100111110111 source: 0 changed: 0 step 123 100000000000010010000000000000000000110111011011011010100110110111 source: source: ; (no change) source: 100000000000000000000000000000000001111100011011011010100110110111 changed: 0 0 1 1 00 step 124 100000000000000000000000000000000001111100011011011010100110110111 source: source: source: ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; source: ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; source: ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; source: ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; source: ;********************* need to walk a one ********************** source: ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; source: ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; source: ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; source: ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; source: source: ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; source: ; source: ; test AND-NOR logic source: ; source: ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; source: source: ; (all registers are HIGH) source: ; set all pins HIGH except ENABLES source: source: ; set pin AF2 HIGH source: 1 changed: 1 step 125 100001000000000000000000000000000001111100011011011010100110110111 source: ; set pin AM1 HIGH source: 1 changed: 1 step 126 100001100000000000000000000000000001111100011011011010100110110111 source: ; set pin AE1 HIGH source: 1 changed: 1 step 127 100001100100000000000000000000000001111100011011011010100110110111 source: ; set pin AM2 HIGH source: 1 changed: 1 step 128 100001100110000000000000000000000001111100011011011010100110110111 source: ; set pin AB2 HIGH source: 1 changed: 1 step 129 100001100110100000000000000000000001111100011011011010100110110111 source: ; set pin AS1 HIGH source: 1 changed: 1 step 130 100001100110100100000000000000000001111100011011011010100110110111 source: ; set pin BE1 HIGH source: 1 changed: 1 step 131 100001100110100100010000000000000001111100011011011010100110110111 source: ; set pin BM1 HIGH source: 1 changed: 1 step 132 100001100110100100011000000000000001111100011011011010100110110111 source: ; set pin BH1 HIGH source: 1 changed: 1 step 133 100001100110100100011010000000000001111100011011011010100110110111 source: ; set pin BR1 HIGH source: 1 changed: 1 step 134 100001100110100100011011000000000001111100011011011010100110110111 source: ; set pin BC1 HIGH source: 1 changed: 1 step 135 100001100110100100011011010000000001111100011011011010100110110111 source: ; set pin BJ2 HIGH source: 1 changed: 1 step 136 100001100110100100011011011000000001111100011011011010100110110111 source: ; set pin BJ1 HIGH source: 1 changed: 1 step 137 100001100110100100011011011010000001111100011011011010100110110111 source: ; set pin BK2 HIGH source: 1 changed: 1 step 138 100001100110100100011011011011000001111100011011011010100110110111 source: ; set pin BH2 HIGH source: 1 changed: 1 step 139 100001100110100100011011011011010001111100011011011010100110110111 source: ; set pin BP2 HIGH source: 1 changed: 1 step 140 100001100110100100011011011011011001111100011011011010100110110111 source: ; set pin BN2 HIGH source: 1 changed: 1 step 141 100001100110100100011011011011011101111100011011011010100110110111 source: ; toggle each ENABLE source: source: ; set pin AL2 to clear pin BB2 and pin AN2 AND-NOR OUTPUTS and set TAPE BUS 2 OUTPUT and TAPE BUS 3 OUTPUT source: 1 0 0 11 changed: 1 0 0 11 step 142 110001100110100100011011011011011100110111011011011010100110110111 source: 0 1 1 00 changed: 0 1 1 00 step 143 100001100110100100011011011011011101111100011011011010100110110111 source: ; set pin AP1 to clear pin BB2 and pin AN2 AND-NOR OUTPUTS and set TAPE BUS 2 OUTPUT and TAPE BUS 3 OUTPUT source: 1 0 0 11 changed: 1 0 0 11 step 144 101001100110100100011011011011011100110111011011011010100110110111 source: 0 1 1 00 changed: 0 1 1 00 step 145 100001100110100100011011011011011101111100011011011010100110110111 source: ; set pin AS2 to clear pin BB2 and pin AN2 AND-NOR OUTPUTS and set TAPE BUS 2 OUTPUT and TAPE BUS 3 OUTPUT source: 1 0 0 11 changed: 1 0 0 11 step 146 100101100110100100011011011011011100110111011011011010100110110111 source: 0 1 1 00 changed: 0 1 1 00 step 147 100001100110100100011011011011011101111100011011011010100110110111 source: ; set pin AL1 to clear pin BB2 and pin AN2 AND-NOR OUTPUTS and set TAPE BUS 2 OUTPUT and TAPE BUS 3 OUTPUT source: 1 0 0 11 changed: 1 0 0 11 step 148 100011100110100100011011011011011100110111011011011010100110110111 source: 0 1 1 00 changed: 0 1 1 00 step 149 100001100110100100011011011011011101111100011011011010100110110111 source: ; set pin AL1 to clear pin BB2 and pin AN2 AND-NOR OUTPUTS and set TAPE BUS 2 OUTPUT and TAPE BUS 3 OUTPUT source: 1 0 0 11 changed: 1 0 0 11 step 150 100001110110100100011011011011011100110111011011011010100110110111 source: 0 1 1 00 changed: 0 1 1 00 step 151 100001100110100100011011011011011101111100011011011010100110110111 source: ; set pin AE2 to clear pin BB2 and pin AN2 AND-NOR OUTPUTS and set TAPE BUS 2 OUTPUT and TAPE BUS 3 OUTPUT source: 1 0 0 11 changed: 1 0 0 11 step 152 100001101110100100011011011011011100110111011011011010100110110111 source: 0 1 1 00 changed: 0 1 1 00 step 153 100001100110100100011011011011011101111100011011011010100110110111 source: ; set pin AC1 to clear pin BB2 and set TAPE BUS 3 OUTPUT source: 1 0 1 changed: 1 0 1 step 154 100001100111100100011011011011011100111101011011011010100110110111 source: 0 1 0 changed: 0 1 0 step 155 100001100110100100011011011011011101111100011011011010100110110111 source: ; set pin AF1 to clear pin BB2 and set TAPE BUS 3 OUTPUT source: 1 0 1 changed: 1 0 1 step 156 100001100110110100011011011011011100111101011011011010100110110111 source: 0 1 0 changed: 0 1 0 step 157 100001100110100100011011011011011101111100011011011010100110110111 source: ; set pin AR2 to clear pin AN2 AND-NOR OUTPUTS and set TAPE BUS 2 OUTPUT source: 1 0 1 changed: 1 0 1 step 158 100001100110101100011011011011011101110110011011011010100110110111 source: 0 1 0 changed: 0 1 0 step 159 100001100110100100011011011011011101111100011011011010100110110111 source: ; set pin AP2 to clear pin AN2 AND-NOR OUTPUTS and set TAPE BUS 2 OUTPUT source: 1 0 1 changed: 1 0 1 step 160 100001100110100110011011011011011101110110011011011010100110110111 source: 0 1 0 changed: 0 1 0 step 161 100001100110100100011011011011011101111100011011011010100110110111 source: source: ; set pin BK1 to clear pin BB1 and pin BN1 AND-NOR OUTPUTS and set TAPE BUS 2 OUTPUT and TAPE BUS 3 OUTPUT source: 1 00 11 changed: 1 00 11 step 162 100001100110100101011011011011011101001111011011011010100110110111 source: 0 11 00 changed: 0 11 00 step 163 100001100110100100011011011011011101111100011011011010100110110111 source: ; set pin BL1 to clear pin BB1 and pin BN1 AND-NOR OUTPUTS and set TAPE BUS 2 OUTPUT and TAPE BUS 3 OUTPUT source: 1 00 11 changed: 1 00 11 step 164 100001100110100100111011011011011101001111011011011010100110110111 source: 0 11 00 changed: 0 11 00 step 165 100001100110100100011011011011011101111100011011011010100110110111 source: ; set pin BF1 to clear pin BB1 and pin BN1 AND-NOR OUTPUTS and set TAPE BUS 2 OUTPUT and TAPE BUS 3 OUTPUT source: 1 00 11 changed: 1 00 11 step 166 100001100110100100011111011011011101001111011011011010100110110111 source: 0 11 00 changed: 0 11 00 step 167 100001100110100100011011011011011101111100011011011010100110110111 source: ; set pin BS1 to clear pin BB1 and pin BN1 AND-NOR OUTPUTS and set TAPE BUS 2 OUTPUT and TAPE BUS 3 OUTPUT source: 1 00 11 changed: 1 00 11 step 168 100001100110100100011011111011011101001111011011011010100110110111 source: 0 11 00 changed: 0 11 00 step 169 100001100110100100011011011011011101111100011011011010100110110111 source: ; set pin BL2 to clear pin BB1 and pin BN1 AND-NOR OUTPUTS and set TAPE BUS 2 OUTPUT and TAPE BUS 3 OUTPUT source: 1 00 11 changed: 1 00 11 step 170 100001100110100100011011011111011101001111011011011010100110110111 source: 0 11 00 changed: 0 11 00 step 171 100001100110100100011011011011011101111100011011011010100110110111 source: ; set pin BU1 to clear pin BB1 and pin BN1 AND-NOR OUTPUTS and set TAPE BUS 2 OUTPUT and TAPE BUS 3 OUTPUT source: 1 00 11 changed: 1 00 11 step 172 100001100110100100011011011011111101001111011011011010100110110111 source: 0 11 00 changed: 0 11 00 step 173 100001100110100100011011011011011101111100011011011010100110110111 source: ; set pin BM2 to clear pin BB1 and TAPE BUS 3 OUTPUT source: 1 0 1 changed: 1 0 1 step 174 100001100110100100011011011011011111101110011011011010100110110111 source: 0 1 0 changed: 0 1 0 step 175 100001100110100100011011011011011101111100011011011010100110110111 source: ; no change source: 100000000000000000000000000000000001111100011011011010100110110111 changed: 00 00 0 0 00 00 00 00 000 step 176 100000000000000000000000000000000001111100011011011010100110110111 source: source: source: ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; source: ; test shifting the RWB source: ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; source: source: ; shift in 0, expect 10 source: 0 changed: 0 step 177 100000000000000000000000000000000001111100011011011010100110100111 source: 110 changed: 1 0 step 178 100000000000000000000000000000000001111100011011011010100110101101 source: 0 changed: 0 step 179 100000000000000000000000000000000001111100011011011010100110100101 source: ; toggle phase should toggle RWB 2 source: 0 0 changed: 0 0 step 180 100000000000000000000000000000000001111100011011011010100110000001 source: 1 1 changed: 1 1 step 181 100000000000000000000000000000000001111100011011011010100110100101 source: source: ; shift in 0, expect 00 source: 0 changed: step 182 100000000000000000000000000000000001111100011011011010100110100101 source: 100 changed: 10 step 183 100000000000000000000000000000000001111100011011011010100110101001 source: 0 changed: 0 step 184 100000000000000000000000000000000001111100011011011010100110100001 source: ; toggle phase should toggle RWB 2 source: 0 1 changed: 0 1 step 185 100000000000000000000000000000000001111100011011011010100110000101 source: 1 0 changed: 1 0 step 186 100000000000000000000000000000000001111100011011011010100110100001 source: source: ; shift in 0, expect 00 source: 0 changed: step 187 100000000000000000000000000000000001111100011011011010100110100001 source: 100 changed: 1 step 188 100000000000000000000000000000000001111100011011011010100110101001 source: 0 changed: 0 step 189 100000000000000000000000000000000001111100011011011010100110100001 source: ; shift in 1, expect 01 source: 1 changed: 1 step 190 100000000000000000000000000000000001111100011011011010100110110001 source: 101 changed: 1 1 step 191 100000000000000000000000000000000001111100011011011010100110111011 source: 0 changed: 0 step 192 100000000000000000000000000000000001111100011011011010100110110011 source: ; shift in 1, expect 11 source: 1 changed: step 193 100000000000000000000000000000000001111100011011011010100110110011 source: 111 changed: 11 step 194 100000000000000000000000000000000001111100011011011010100110111111 source: 0 changed: 0 step 195 100000000000000000000000000000000001111100011011011010100110110111 source: ; shift in 1, expect 11 source: 1 changed: step 196 100000000000000000000000000000000001111100011011011010100110110111 source: 111 changed: 1 step 197 100000000000000000000000000000000001111100011011011010100110111111 source: 0 changed: 0 step 198 100000000000000000000000000000000001111100011011011010100110110111 source: ; shift in 0, expect 10 source: 0 changed: 0 step 199 100000000000000000000000000000000001111100011011011010100110100111 source: 110 changed: 1 0 step 200 100000000000000000000000000000000001111100011011011010100110101101 source: 0 changed: 0 step 201 100000000000000000000000000000000001111100011011011010100110100101 source: ; shift in 1, expect 01 source: 1 changed: 1 step 202 100000000000000000000000000000000001111100011011011010100110110101 source: 101 changed: 101 step 203 100000000000000000000000000000000001111100011011011010100110111011 source: 0 changed: 0 step 204 100000000000000000000000000000000001111100011011011010100110110011 source: ; shift in 0, expect 10 source: 0 changed: 0 step 205 100000000000000000000000000000000001111100011011011010100110100011 source: 110 changed: 110 step 206 100000000000000000000000000000000001111100011011011010100110101101 source: 0 changed: 0 step 207 100000000000000000000000000000000001111100011011011010100110100101 source: ; shift in 1, expect 01 source: 1 changed: 1 step 208 100000000000000000000000000000000001111100011011011010100110110101 source: 101 changed: 101 step 209 100000000000000000000000000000000001111100011011011010100110111011 source: 0 changed: 0 step 210 100000000000000000000000000000000001111100011011011010100110110011 source: ; shift in 1, expect 11 source: 1 changed: step 211 100000000000000000000000000000000001111100011011011010100110110011 source: 111 changed: 11 step 212 100000000000000000000000000000000001111100011011011010100110111111 source: 0 changed: 0 step 213 100000000000000000000000000000000001111100011011011010100110110111 source: ; no change source: 100000000000000000000000000000000001111100011011011010100110110111 changed: step 214 100000000000000000000000000000000001111100011011011010100110110111 test 3: pass SLOT BAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBAABBAAAAAAAAAAAAAABBBBBABBBB LETTER ALPSLFMDEEMCBFRSPKLEMFHRSCJLJKUHPNMBBNNVVRKRHUTDJUKANJHBTPDFSVEVDU SIDE 121212122121212121111111112212122222112222111221112112212112212122 DIRECTION IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIOOOOOOOIOOIOOIOOIOOOOIOOIIIIOOO this fail all fails was hi 111111111111111111111111111111111111111111111111111111111111111111 rising ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ ^^^^^^^^^^^^^^^^^^^^^^^^^ falling vvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvv vvvvvvvvvvvvvvvvvvvvvvvvv was lo 00000000000000000000000000000000000000 0000000000000000000000000 total fails 0, total passes 3 source: ; all registers are unknown source: ; turn on C0, PHASE source: ; with no ENABLES, BUS2,BUS3 is 11, C2 is 1 source: 1000000000000000000000000000000000011111000XX0XX0XX0XXXX0XX0110XX1 changed: step 1 100000000000000000000000000000000001111100011011011010100110110111 source: source: ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; source: ; source: ; set all registers LOW source: ; source: ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; source: source: ; load TMA SETUP from tape bus (00) source: 100 changed: 100 step 2 100000000000000000000000000000000001111100100011011010100110110111 source: 0 changed: 0 step 3 100000000000000000000000000000000001111100000011011010100110110111 source: ; load TMA from tape bus (00) source: 100 changed: 100 step 4 100000000000000000000000000000000001111100000100011010100110110111 source: 0 changed: 0 step 5 100000000000000000000000000000000001111100000000011010100110110111 source: ; load TBN from tape bus (00) source: 100 changed: 100 step 6 100000000000000000000000000000000001111100000000100010100110110111 source: 0 changed: 0 step 7 100000000000000000000000000000000001111100000000000010100110110111 source: ; load TAC from tape bus (00) source: 10101 changed: 10101 step 8 100000000000000000000000000000000001111100000000000101010110110111 source: 0 changed: 0 step 9 100000000000000000000000000000000001111100000000000001010110110111 source: ; load TB from tape bus (00) source: 100 changed: 100 step 10 100000000000000000000000000000000001111100000000000001011000110111 source: 0 changed: 0 step 11 100000000000000000000000000000000001111100000000000001010000110111 source: ; load RWB from TB (JAMS CLEAR AND PRESET) source: 1 00 changed: 1 00 step 12 100000000000000000000000000000000001111100000000000001010001110001 source: 0 changed: 0 step 13 100000000000000000000000000000000001111100000000000001010000110001 source: ; (no change) source: 100000000000000000000000000000000001111100000000000001010000110001 changed: step 14 100000000000000000000000000000000001111100000000000001010000110001 source: source: source: ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; source: ; source: ; set all registers HIGH source: ; source: ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; source: source: ; set pin AF1 which clears pin BB2 and sets pin BR2 TAPE BUS 3 OUTPUT source: 1 0 1 changed: 1 0 1 step 15 100000000000010000000000000000000000111101000000000001010000110001 source: ; set pin AP2 which clears pin AN2 and sets pin BV2 TAPE BUS 2 OUTPUT source: 1 0 1 changed: 1 0 1 step 16 100000000000010010000000000000000000110111000000000001010000110001 source: source: source: ; load TMA SETUP from tape bus (11) source: 111 changed: 111 step 17 100000000000010010000000000000000000110111111000000001010000110001 source: 0 changed: 0 step 18 100000000000010010000000000000000000110111011000000001010000110001 source: ; load TMA from tape bus (11) source: 111 changed: 111 step 19 100000000000010010000000000000000000110111011111000001010000110001 source: 0 changed: 0 step 20 100000000000010010000000000000000000110111011011000001010000110001 source: ; load TBN from tape bus (11) source: 111 changed: 111 step 21 100000000000010010000000000000000000110111011011111001010000110001 source: 0 changed: 0 step 22 100000000000010010000000000000000000110111011011011001010000110001 source: ; load TAC from tape bus (11) source: 11010 changed: 11010 step 23 100000000000010010000000000000000000110111011011011110100000110001 source: 0 changed: 0 step 24 100000000000010010000000000000000000110111011011011010100000110001 source: ; load TB from tape bus (11) source: 111 changed: 111 step 25 100000000000010010000000000000000000110111011011011010101110110001 source: 0 changed: 0 step 26 100000000000010010000000000000000000110111011011011010100110110001 source: ; load RWB from TB (JAMS CLEAR AND PRESET) source: 1 11 changed: 1 11 step 27 100000000000010010000000000000000000110111011011011010100111110111 source: 0 changed: 0 step 28 100000000000010010000000000000000000110111011011011010100110110111 source: ; clear pin AF1 (AND with itself) to set pin BB2 (AND-NOR output) and clear pin BR2 TAPE BUS 3 OUTPUT source: 0 1 0 changed: 0 1 0 step 29 100000000000000010000000000000000001110110011011011010100110110111 source: ; clear pin AP2 (AND with itself) to set pin AN2 (AND-NOR output) and clear pin BV2 TAPE BUS 2 OUTPUT source: 0 1 0 changed: 0 1 0 step 30 100000000000000000000000000000000001111100011011011010100110110111 source: ; (no change) source: 100000000000000000000000000000000001111100011011011010100110110111 changed: step 31 100000000000000000000000000000000001111100011011011010100110110111 source: source: ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; source: ; source: ; will all registers high, walk a 0 source: ; source: ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; source: source: source: ; walk a 0, TMA SETUP 2 source: source: source: ; clear pin AP2 which sets pin AN2 and clears pin BV2 TAPE BUS 2 OUTPUT source: 0 1 0 changed: step 32 100000000000000000000000000000000001111100011011011010100110110111 source: ; set pin AF1 which clears pin BB2 and sets pin BR2 TAPE BUS 3 OUTPUT source: 1 0 1 changed: 1 0 1 step 33 100000000000010000000000000000000000111101011011011010100110110111 source: ; load TMA SETUP from tape bus (01) source: 101 changed: 10 step 34 100000000000010000000000000000000000111101101011011010100110110111 source: 0 changed: 0 step 35 100000000000010000000000000000000000111101001011011010100110110111 source: ; restore TMA SETUP 2 source: ; set pin AP2 which clears pin AN2 and sets pin BV2 TAPE BUS 2 OUTPUT source: 1 0 1 changed: 1 0 1 step 36 100000000000010010000000000000000000110111001011011010100110110111 source: ; load TMA SETUP from tape bus (11) source: 111 changed: 11 step 37 100000000000010010000000000000000000110111111011011010100110110111 source: 0 changed: 0 step 38 100000000000010010000000000000000000110111011011011010100110110111 source: source: source: ; walk a 0, TMA SETUP 3 source: source: source: ; set pin AP2 which clears pin AN2 and sets pin BV2 TAPE BUS 2 OUTPUT source: 1 0 1 changed: step 39 100000000000010010000000000000000000110111011011011010100110110111 source: ; clear pin AF1 which sets pin BB2 and clears pin BR2 TAPE BUS 3 OUTPUT source: 0 1 0 changed: 0 1 0 step 40 100000000000000010000000000000000001110110011011011010100110110111 source: ; load TMA SETUP from tape bus (10) source: 110 changed: 1 0 step 41 100000000000000010000000000000000001110110110011011010100110110111 source: 0 changed: 0 step 42 100000000000000010000000000000000001110110010011011010100110110111 source: ; restore TMA SETUP 3 source: ; set pin AF1 which clears pin BB2 and sets pin BR2 TAPE BUS 3 OUTPUT source: 1 0 1 changed: 1 0 1 step 43 100000000000010010000000000000000000110111010011011010100110110111 source: ; load TMA SETUP from tape bus (11) source: 111 changed: 1 1 step 44 100000000000010010000000000000000000110111111011011010100110110111 source: 0 changed: 0 step 45 100000000000010010000000000000000000110111011011011010100110110111 source: source: source: ; walk a 0, TMA 2 source: source: source: ; clear pin AP2 which sets pin AN2 and clears pin BV2 TAPE BUS 2 OUTPUT source: 0 1 0 changed: 0 1 0 step 46 100000000000010000000000000000000000111101011011011010100110110111 source: ; set pin AF1 which clears pin BB2 and sets pin BR2 TAPE BUS 3 OUTPUT source: 1 0 1 changed: step 47 100000000000010000000000000000000000111101011011011010100110110111 source: ; load TMA from tape bus (01) source: 101 changed: 10 step 48 100000000000010000000000000000000000111101011101011010100110110111 source: 0 changed: 0 step 49 100000000000010000000000000000000000111101011001011010100110110111 source: ; restore TMA 2 source: ; set pin AP2 which clears pin AN2 and sets pin BV2 TAPE BUS 2 OUTPUT source: 1 0 1 changed: 1 0 1 step 50 100000000000010010000000000000000000110111011001011010100110110111 source: ; load TMA from tape bus (11) source: 111 changed: 11 step 51 100000000000010010000000000000000000110111011111011010100110110111 source: 0 changed: 0 step 52 100000000000010010000000000000000000110111011011011010100110110111 source: source: source: ; walk a 0, TMA 3 source: source: source: ; set pin AP2 which clears pin AN2 and sets pin BV2 TAPE BUS 2 OUTPUT source: 1 0 1 changed: step 53 100000000000010010000000000000000000110111011011011010100110110111 source: ; clear pin AF1 which sets pin BB2 and clears pin BR2 TAPE BUS 3 OUTPUT source: 0 1 0 changed: 0 1 0 step 54 100000000000000010000000000000000001110110011011011010100110110111 source: ; load TMA from tape bus (10) source: 110 changed: 1 0 step 55 100000000000000010000000000000000001110110011110011010100110110111 source: 0 changed: 0 step 56 100000000000000010000000000000000001110110011010011010100110110111 source: ; restore TMA 3 source: ; set pin AF1 which clears pin BB2 and sets pin BR2 TAPE BUS 3 OUTPUT source: 1 0 1 changed: 1 0 1 step 57 100000000000010010000000000000000000110111011010011010100110110111 source: ; load TMA from tape bus (11) source: 111 changed: 1 1 step 58 100000000000010010000000000000000000110111011111011010100110110111 source: 0 changed: 0 step 59 100000000000010010000000000000000000110111011011011010100110110111 source: source: source: ; walk a 0, TBN 2 source: source: source: ; clear pin AP2 which sets pin AN2 and clears pin BV2 TAPE BUS 2 OUTPUT source: 0 1 0 changed: 0 1 0 step 60 100000000000010000000000000000000000111101011011011010100110110111 source: ; set pin AF1 which clears pin BB2 and sets pin BR2 TAPE BUS 3 OUTPUT source: 1 0 1 changed: step 61 100000000000010000000000000000000000111101011011011010100110110111 source: ; load TBN from tape bus (01) source: 101 changed: 10 step 62 100000000000010000000000000000000000111101011011101010100110110111 source: 0 changed: 0 step 63 100000000000010000000000000000000000111101011011001010100110110111 source: ; restore TBN 2 source: ; set pin AP2 which clears pin AN2 and sets pin BV2 TAPE BUS 2 OUTPUT source: 1 0 1 changed: 1 0 1 step 64 100000000000010010000000000000000000110111011011001010100110110111 source: ; load TBN from tape bus (11) source: 111 changed: 11 step 65 100000000000010010000000000000000000110111011011111010100110110111 source: 0 changed: 0 step 66 100000000000010010000000000000000000110111011011011010100110110111 source: source: source: ; walk a 0, TBN 3 source: source: source: ; set pin AP2 which clears pin AN2 and sets pin BV2 TAPE BUS 2 OUTPUT source: 1 0 1 changed: step 67 100000000000010010000000000000000000110111011011011010100110110111 source: ; clear pin AF1 which sets pin BB2 and clears pin BR2 TAPE BUS 3 OUTPUT source: 0 1 0 changed: 0 1 0 step 68 100000000000000010000000000000000001110110011011011010100110110111 source: ; load TBN from tape bus (10) source: 110 changed: 1 0 step 69 100000000000000010000000000000000001110110011011110010100110110111 source: 0 changed: 0 step 70 100000000000000010000000000000000001110110011011010010100110110111 source: ; restore TBN 3 source: ; set pin AF1 which clears pin BB2 and sets pin BR2 TAPE BUS 3 OUTPUT source: 1 0 1 changed: 1 0 1 step 71 100000000000010010000000000000000000110111011011010010100110110111 source: ; load TBN from tape bus (11) source: 111 changed: 1 1 step 72 100000000000010010000000000000000000110111011011111010100110110111 source: 0 changed: 0 step 73 100000000000010010000000000000000000110111011011011010100110110111 source: source: source: ; walk a 0, TAC 2 source: source: source: ; clear pin AP2 which sets pin AN2 and clears pin BV2 TAPE BUS 2 OUTPUT source: 0 1 0 changed: 0 1 0 step 74 100000000000010000000000000000000000111101011011011010100110110111 source: ; set pin AF1 which clears pin BB2 and sets pin BR2 TAPE BUS 3 OUTPUT source: 1 0 1 changed: step 75 100000000000010000000000000000000000111101011011011010100110110111 source: ; load TAC from tape bus (01) source: 10110 changed: 101 step 76 100000000000010000000000000000000000111101011011011101100110110111 source: 0 changed: 0 step 77 100000000000010000000000000000000000111101011011011001100110110111 source: ; restore TAC 2 source: ; set pin AP2 which clears pin AN2 and sets pin BV2 TAPE BUS 2 OUTPUT source: 1 0 1 changed: 1 0 1 step 78 100000000000010010000000000000000000110111011011011001100110110111 source: ; load TAC from tape bus (11) source: 11010 changed: 110 step 79 100000000000010010000000000000000000110111011011011110100110110111 source: 0 changed: 0 step 80 100000000000010010000000000000000000110111011011011010100110110111 source: source: source: ; walk a 0, TAC 3 source: source: source: ; set pin AP2 which clears pin AN2 and sets pin BV2 TAPE BUS 2 OUTPUT source: 1 0 1 changed: step 81 100000000000010010000000000000000000110111011011011010100110110111 source: ; clear pin AF1 which sets pin BB2 and clears pin BR2 TAPE BUS 3 OUTPUT source: 0 1 0 changed: 0 1 0 step 82 100000000000000010000000000000000001110110011011011010100110110111 source: ; load TAC from tape bus (10) source: 11001 changed: 1 01 step 83 100000000000000010000000000000000001110110011011011110010110110111 source: 0 changed: 0 step 84 100000000000000010000000000000000001110110011011011010010110110111 source: ; restore TAC 3 source: ; set pin AF1 which clears pin BB2 and sets pin BR2 TAPE BUS 3 OUTPUT source: 1 0 1 changed: 1 0 1 step 85 100000000000010010000000000000000000110111011011011010010110110111 source: ; load TAC from tape bus (11) source: 11010 changed: 1 10 step 86 100000000000010010000000000000000000110111011011011110100110110111 source: 0 changed: 0 step 87 100000000000010010000000000000000000110111011011011010100110110111 source: source: source: ; walk a 0, TB 2 source: source: source: ; clear pin AP2 which sets pin AN2 and clears pin BV2 TAPE BUS 2 OUTPUT source: 0 1 0 changed: 0 1 0 step 88 100000000000010000000000000000000000111101011011011010100110110111 source: ; set pin AF1 which clears pin BB2 and sets pin BR2 TAPE BUS 3 OUTPUT source: 1 0 1 changed: step 89 100000000000010000000000000000000000111101011011011010100110110111 source: ; load TB from tape bus (01) source: 101 changed: 10 step 90 100000000000010000000000000000000000111101011011011010101010110111 source: 0 changed: 0 step 91 100000000000010000000000000000000000111101011011011010100010110111 source: ; restore TB 2 source: ; set pin AP2 which clears pin AN2 and sets pin BV2 TAPE BUS 2 OUTPUT source: 1 0 1 changed: 1 0 1 step 92 100000000000010010000000000000000000110111011011011010100010110111 source: ; load TB from tape bus (11) source: 111 changed: 11 step 93 100000000000010010000000000000000000110111011011011010101110110111 source: 0 changed: 0 step 94 100000000000010010000000000000000000110111011011011010100110110111 source: source: source: ; walk a 0, TB 3 source: source: source: ; set pin AP2 which clears pin AN2 and sets pin BV2 TAPE BUS 2 OUTPUT source: 1 0 1 changed: step 95 100000000000010010000000000000000000110111011011011010100110110111 source: ; clear pin AF1 which sets pin BB2 and clears pin BR2 TAPE BUS 3 OUTPUT source: 0 1 0 changed: 0 1 0 step 96 100000000000000010000000000000000001110110011011011010100110110111 source: ; load TB from tape bus (10) source: 110 changed: 1 0 step 97 100000000000000010000000000000000001110110011011011010101100110111 source: 0 changed: 0 step 98 100000000000000010000000000000000001110110011011011010100100110111 source: ; restore TB 3 source: ; set pin AF1 which clears pin BB2 and sets pin BR2 TAPE BUS 3 OUTPUT source: 1 0 1 changed: 1 0 1 step 99 100000000000010010000000000000000000110111011011011010100100110111 source: ; load TB from tape bus (11) source: 111 changed: 1 1 step 100 100000000000010010000000000000000000110111011011011010101110110111 source: 0 changed: 0 step 101 100000000000010010000000000000000000110111011011011010100110110111 source: source: source: ; walk a 0, RWB 2 source: source: source: ; clear pin AP2 which sets pin AN2 and clears pin BV2 TAPE BUS 2 OUTPUT source: 0 1 0 changed: 0 1 0 step 102 100000000000010000000000000000000000111101011011011010100110110111 source: ; set pin AF1 which clears pin BB2 and sets pin BR2 TAPE BUS 3 OUTPUT source: 1 0 1 changed: step 103 100000000000010000000000000000000000111101011011011010100110110111 source: ; load TB from tape bus (01) source: 101 changed: 10 step 104 100000000000010000000000000000000000111101011011011010101010110111 source: 0 changed: 0 step 105 100000000000010000000000000000000000111101011011011010100010110111 source: ; load RWB from TB (JAMS CLEAR AND PRESET) source: 1 01 changed: 1 0 step 106 100000000000010000000000000000000000111101011011011010100011110011 source: 0 changed: 0 step 107 100000000000010000000000000000000000111101011011011010100010110011 source: ; restore TB 2 and RWB 2 source: ; set pin AP2 which clears pin AN2 and sets pin BV2 TAPE BUS 2 OUTPUT source: 1 0 1 changed: 1 0 1 step 108 100000000000010010000000000000000000110111011011011010100010110011 source: ; load TB from tape bus (11) source: 111 changed: 11 step 109 100000000000010010000000000000000000110111011011011010101110110011 source: 0 changed: 0 step 110 100000000000010010000000000000000000110111011011011010100110110011 source: ; load RWB from TB (JAMS CLEAR AND PRESET) source: 1 11 changed: 1 1 step 111 100000000000010010000000000000000000110111011011011010100111110111 source: 0 changed: 0 step 112 100000000000010010000000000000000000110111011011011010100110110111 source: source: source: ; walk a 0, RWB 3 source: source: source: ; set pin AP2 which clears pin AN2 and sets pin BV2 TAPE BUS 2 OUTPUT source: 1 0 1 changed: step 113 100000000000010010000000000000000000110111011011011010100110110111 source: ; clear pin AF1 which sets pin BB2 and clears pin BR2 TAPE BUS 3 OUTPUT source: 0 1 0 changed: 0 1 0 step 114 100000000000000010000000000000000001110110011011011010100110110111 source: ; load TB from tape bus (10) source: 110 changed: 1 0 step 115 100000000000000010000000000000000001110110011011011010101100110111 source: 0 changed: 0 step 116 100000000000000010000000000000000001110110011011011010100100110111 source: ; load RWB from TB (JAMS CLEAR AND PRESET) source: 1 10 changed: 1 0 step 117 100000000000000010000000000000000001110110011011011010100101110101 source: 0 changed: 0 step 118 100000000000000010000000000000000001110110011011011010100100110101 source: ; restore TB 3 and RWB 3 source: ; set pin AF1 which clears pin BB2 and sets pin BR2 TAPE BUS 3 OUTPUT source: 1 0 1 changed: 1 0 1 step 119 100000000000010010000000000000000000110111011011011010100100110101 source: ; load TB from tape bus (11) source: 111 changed: 1 1 step 120 100000000000010010000000000000000000110111011011011010101110110101 source: 0 changed: 0 step 121 100000000000010010000000000000000000110111011011011010100110110101 source: ; load RWB from TB (JAMS CLEAR AND PRESET) source: 1 11 changed: 1 1 step 122 100000000000010010000000000000000000110111011011011010100111110111 source: 0 changed: 0 step 123 100000000000010010000000000000000000110111011011011010100110110111 source: source: ; (no change) source: 100000000000000000000000000000000001111100011011011010100110110111 changed: 0 0 1 1 00 step 124 100000000000000000000000000000000001111100011011011010100110110111 source: source: source: ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; source: ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; source: ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; source: ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; source: ;********************* need to walk a one ********************** source: ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; source: ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; source: ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; source: ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; source: source: ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; source: ; source: ; test AND-NOR logic source: ; source: ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; source: source: ; (all registers are HIGH) source: ; set all pins HIGH except ENABLES source: source: ; set pin AF2 HIGH source: 1 changed: 1 step 125 100001000000000000000000000000000001111100011011011010100110110111 source: ; set pin AM1 HIGH source: 1 changed: 1 step 126 100001100000000000000000000000000001111100011011011010100110110111 source: ; set pin AE1 HIGH source: 1 changed: 1 step 127 100001100100000000000000000000000001111100011011011010100110110111 source: ; set pin AM2 HIGH source: 1 changed: 1 step 128 100001100110000000000000000000000001111100011011011010100110110111 source: ; set pin AB2 HIGH source: 1 changed: 1 step 129 100001100110100000000000000000000001111100011011011010100110110111 source: ; set pin AS1 HIGH source: 1 changed: 1 step 130 100001100110100100000000000000000001111100011011011010100110110111 source: ; set pin BE1 HIGH source: 1 changed: 1 step 131 100001100110100100010000000000000001111100011011011010100110110111 source: ; set pin BM1 HIGH source: 1 changed: 1 step 132 100001100110100100011000000000000001111100011011011010100110110111 source: ; set pin BH1 HIGH source: 1 changed: 1 step 133 100001100110100100011010000000000001111100011011011010100110110111 source: ; set pin BR1 HIGH source: 1 changed: 1 step 134 100001100110100100011011000000000001111100011011011010100110110111 source: ; set pin BC1 HIGH source: 1 changed: 1 step 135 100001100110100100011011010000000001111100011011011010100110110111 source: ; set pin BJ2 HIGH source: 1 changed: 1 step 136 100001100110100100011011011000000001111100011011011010100110110111 source: ; set pin BJ1 HIGH source: 1 changed: 1 step 137 100001100110100100011011011010000001111100011011011010100110110111 source: ; set pin BK2 HIGH source: 1 changed: 1 step 138 100001100110100100011011011011000001111100011011011010100110110111 source: ; set pin BH2 HIGH source: 1 changed: 1 step 139 100001100110100100011011011011010001111100011011011010100110110111 source: ; set pin BP2 HIGH source: 1 changed: 1 step 140 100001100110100100011011011011011001111100011011011010100110110111 source: ; set pin BN2 HIGH source: 1 changed: 1 step 141 100001100110100100011011011011011101111100011011011010100110110111 source: ; toggle each ENABLE source: source: ; set pin AL2 to clear pin BB2 and pin AN2 AND-NOR OUTPUTS and set TAPE BUS 2 OUTPUT and TAPE BUS 3 OUTPUT source: 1 0 0 11 changed: 1 0 0 11 step 142 110001100110100100011011011011011100110111011011011010100110110111 source: 0 1 1 00 changed: 0 1 1 00 step 143 100001100110100100011011011011011101111100011011011010100110110111 source: ; set pin AP1 to clear pin BB2 and pin AN2 AND-NOR OUTPUTS and set TAPE BUS 2 OUTPUT and TAPE BUS 3 OUTPUT source: 1 0 0 11 changed: 1 0 0 11 step 144 101001100110100100011011011011011100110111011011011010100110110111 source: 0 1 1 00 changed: 0 1 1 00 step 145 100001100110100100011011011011011101111100011011011010100110110111 source: ; set pin AS2 to clear pin BB2 and pin AN2 AND-NOR OUTPUTS and set TAPE BUS 2 OUTPUT and TAPE BUS 3 OUTPUT source: 1 0 0 11 changed: 1 0 0 11 step 146 100101100110100100011011011011011100110111011011011010100110110111 source: 0 1 1 00 changed: 0 1 1 00 step 147 100001100110100100011011011011011101111100011011011010100110110111 source: ; set pin AL1 to clear pin BB2 and pin AN2 AND-NOR OUTPUTS and set TAPE BUS 2 OUTPUT and TAPE BUS 3 OUTPUT source: 1 0 0 11 changed: 1 0 0 11 step 148 100011100110100100011011011011011100110111011011011010100110110111 source: 0 1 1 00 changed: 0 1 1 00 step 149 100001100110100100011011011011011101111100011011011010100110110111 source: ; set pin AL1 to clear pin BB2 and pin AN2 AND-NOR OUTPUTS and set TAPE BUS 2 OUTPUT and TAPE BUS 3 OUTPUT source: 1 0 0 11 changed: 1 0 0 11 step 150 100001110110100100011011011011011100110111011011011010100110110111 source: 0 1 1 00 changed: 0 1 1 00 step 151 100001100110100100011011011011011101111100011011011010100110110111 source: ; set pin AE2 to clear pin BB2 and pin AN2 AND-NOR OUTPUTS and set TAPE BUS 2 OUTPUT and TAPE BUS 3 OUTPUT source: 1 0 0 11 changed: 1 0 0 11 step 152 100001101110100100011011011011011100110111011011011010100110110111 source: 0 1 1 00 changed: 0 1 1 00 step 153 100001100110100100011011011011011101111100011011011010100110110111 source: ; set pin AC1 to clear pin BB2 and set TAPE BUS 3 OUTPUT source: 1 0 1 changed: 1 0 1 step 154 100001100111100100011011011011011100111101011011011010100110110111 source: 0 1 0 changed: 0 1 0 step 155 100001100110100100011011011011011101111100011011011010100110110111 source: ; set pin AF1 to clear pin BB2 and set TAPE BUS 3 OUTPUT source: 1 0 1 changed: 1 0 1 step 156 100001100110110100011011011011011100111101011011011010100110110111 source: 0 1 0 changed: 0 1 0 step 157 100001100110100100011011011011011101111100011011011010100110110111 source: ; set pin AR2 to clear pin AN2 AND-NOR OUTPUTS and set TAPE BUS 2 OUTPUT source: 1 0 1 changed: 1 0 1 step 158 100001100110101100011011011011011101110110011011011010100110110111 source: 0 1 0 changed: 0 1 0 step 159 100001100110100100011011011011011101111100011011011010100110110111 source: ; set pin AP2 to clear pin AN2 AND-NOR OUTPUTS and set TAPE BUS 2 OUTPUT source: 1 0 1 changed: 1 0 1 step 160 100001100110100110011011011011011101110110011011011010100110110111 source: 0 1 0 changed: 0 1 0 step 161 100001100110100100011011011011011101111100011011011010100110110111 source: source: ; set pin BK1 to clear pin BB1 and pin BN1 AND-NOR OUTPUTS and set TAPE BUS 2 OUTPUT and TAPE BUS 3 OUTPUT source: 1 00 11 changed: 1 00 11 step 162 100001100110100101011011011011011101001111011011011010100110110111 source: 0 11 00 changed: 0 11 00 step 163 100001100110100100011011011011011101111100011011011010100110110111 source: ; set pin BL1 to clear pin BB1 and pin BN1 AND-NOR OUTPUTS and set TAPE BUS 2 OUTPUT and TAPE BUS 3 OUTPUT source: 1 00 11 changed: 1 00 11 step 164 100001100110100100111011011011011101001111011011011010100110110111 source: 0 11 00 changed: 0 11 00 step 165 100001100110100100011011011011011101111100011011011010100110110111 source: ; set pin BF1 to clear pin BB1 and pin BN1 AND-NOR OUTPUTS and set TAPE BUS 2 OUTPUT and TAPE BUS 3 OUTPUT source: 1 00 11 changed: 1 00 11 step 166 100001100110100100011111011011011101001111011011011010100110110111 source: 0 11 00 changed: 0 11 00 step 167 100001100110100100011011011011011101111100011011011010100110110111 source: ; set pin BS1 to clear pin BB1 and pin BN1 AND-NOR OUTPUTS and set TAPE BUS 2 OUTPUT and TAPE BUS 3 OUTPUT source: 1 00 11 changed: 1 00 11 step 168 100001100110100100011011111011011101001111011011011010100110110111 source: 0 11 00 changed: 0 11 00 step 169 100001100110100100011011011011011101111100011011011010100110110111 source: ; set pin BL2 to clear pin BB1 and pin BN1 AND-NOR OUTPUTS and set TAPE BUS 2 OUTPUT and TAPE BUS 3 OUTPUT source: 1 00 11 changed: 1 00 11 step 170 100001100110100100011011011111011101001111011011011010100110110111 source: 0 11 00 changed: 0 11 00 step 171 100001100110100100011011011011011101111100011011011010100110110111 source: ; set pin BU1 to clear pin BB1 and pin BN1 AND-NOR OUTPUTS and set TAPE BUS 2 OUTPUT and TAPE BUS 3 OUTPUT source: 1 00 11 changed: 1 00 11 step 172 100001100110100100011011011011111101001111011011011010100110110111 source: 0 11 00 changed: 0 11 00 step 173 100001100110100100011011011011011101111100011011011010100110110111 source: ; set pin BM2 to clear pin BB1 and TAPE BUS 3 OUTPUT source: 1 0 1 changed: 1 0 1 step 174 100001100110100100011011011011011111101110011011011010100110110111 source: 0 1 0 changed: 0 1 0 step 175 100001100110100100011011011011011101111100011011011010100110110111 source: ; no change source: 100000000000000000000000000000000001111100011011011010100110110111 changed: 00 00 0 0 00 00 00 00 000 step 176 100000000000000000000000000000000001111100011011011010100110110111 source: source: source: ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; source: ; test shifting the RWB source: ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; source: source: ; shift in 0, expect 10 source: 0 changed: 0 step 177 100000000000000000000000000000000001111100011011011010100110100111 source: 110 changed: 1 0 step 178 100000000000000000000000000000000001111100011011011010100110101101 source: 0 changed: 0 step 179 100000000000000000000000000000000001111100011011011010100110100101 source: ; toggle phase should toggle RWB 2 source: 0 0 changed: 0 0 step 180 100000000000000000000000000000000001111100011011011010100110000001 source: 1 1 changed: 1 1 step 181 100000000000000000000000000000000001111100011011011010100110100101 source: source: ; shift in 0, expect 00 source: 0 changed: step 182 100000000000000000000000000000000001111100011011011010100110100101 source: 100 changed: 10 step 183 100000000000000000000000000000000001111100011011011010100110101001 source: 0 changed: 0 step 184 100000000000000000000000000000000001111100011011011010100110100001 source: ; toggle phase should toggle RWB 2 source: 0 1 changed: 0 1 step 185 100000000000000000000000000000000001111100011011011010100110000101 source: 1 0 changed: 1 0 step 186 100000000000000000000000000000000001111100011011011010100110100001 source: source: ; shift in 0, expect 00 source: 0 changed: step 187 100000000000000000000000000000000001111100011011011010100110100001 source: 100 changed: 1 step 188 100000000000000000000000000000000001111100011011011010100110101001 source: 0 changed: 0 step 189 100000000000000000000000000000000001111100011011011010100110100001 source: ; shift in 1, expect 01 source: 1 changed: 1 step 190 100000000000000000000000000000000001111100011011011010100110110001 source: 101 changed: 1 1 step 191 100000000000000000000000000000000001111100011011011010100110111011 source: 0 changed: 0 step 192 100000000000000000000000000000000001111100011011011010100110110011 source: ; shift in 1, expect 11 source: 1 changed: step 193 100000000000000000000000000000000001111100011011011010100110110011 source: 111 changed: 11 step 194 100000000000000000000000000000000001111100011011011010100110111111 source: 0 changed: 0 step 195 100000000000000000000000000000000001111100011011011010100110110111 source: ; shift in 1, expect 11 source: 1 changed: step 196 100000000000000000000000000000000001111100011011011010100110110111 source: 111 changed: 1 step 197 100000000000000000000000000000000001111100011011011010100110111111 source: 0 changed: 0 step 198 100000000000000000000000000000000001111100011011011010100110110111 source: ; shift in 0, expect 10 source: 0 changed: 0 step 199 100000000000000000000000000000000001111100011011011010100110100111 source: 110 changed: 1 0 step 200 100000000000000000000000000000000001111100011011011010100110101101 source: 0 changed: 0 step 201 100000000000000000000000000000000001111100011011011010100110100101 source: ; shift in 1, expect 01 source: 1 changed: 1 step 202 100000000000000000000000000000000001111100011011011010100110110101 source: 101 changed: 101 step 203 100000000000000000000000000000000001111100011011011010100110111011 source: 0 changed: 0 step 204 100000000000000000000000000000000001111100011011011010100110110011 source: ; shift in 0, expect 10 source: 0 changed: 0 step 205 100000000000000000000000000000000001111100011011011010100110100011 source: 110 changed: 110 step 206 100000000000000000000000000000000001111100011011011010100110101101 source: 0 changed: 0 step 207 100000000000000000000000000000000001111100011011011010100110100101 source: ; shift in 1, expect 01 source: 1 changed: 1 step 208 100000000000000000000000000000000001111100011011011010100110110101 source: 101 changed: 101 step 209 100000000000000000000000000000000001111100011011011010100110111011 source: 0 changed: 0 step 210 100000000000000000000000000000000001111100011011011010100110110011 source: ; shift in 1, expect 11 source: 1 changed: step 211 100000000000000000000000000000000001111100011011011010100110110011 source: 111 changed: 11 step 212 100000000000000000000000000000000001111100011011011010100110111111 source: 0 changed: 0 step 213 100000000000000000000000000000000001111100011011011010100110110111 source: ; no change source: 100000000000000000000000000000000001111100011011011010100110110111 changed: step 214 100000000000000000000000000000000001111100011011011010100110110111 test 4: pass SLOT BAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBAABBAAAAAAAAAAAAAABBBBBABBBB LETTER ALPSLFMDEEMCBFRSPKLEMFHRSCJLJKUHPNMBBNNVVRKRHUTDJUKANJHBTPDFSVEVDU SIDE 121212122121212121111111112212122222112222111221112112212112212122 DIRECTION IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIOOOOOOOIOOIOOIOOIOOOOIOOIIIIOOO this fail all fails was hi 111111111111111111111111111111111111111111111111111111111111111111 rising ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ ^^^^^^^^^^^^^^^^^^^^^^^^^ falling vvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvv vvvvvvvvvvvvvvvvvvvvvvvvv was lo 00000000000000000000000000000000000000 0000000000000000000000000 total fails 0, total passes 4 source: ; all registers are unknown source: ; turn on C0, PHASE source: ; with no ENABLES, BUS2,BUS3 is 11, C2 is 1 source: 1000000000000000000000000000000000011111000XX0XX0XX0XXXX0XX0110XX1 changed: step 1 100000000000000000000000000000000001111100011011011010100110110111 source: source: ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; source: ; source: ; set all registers LOW source: ; source: ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; source: source: ; load TMA SETUP from tape bus (00) source: 100 changed: 100 step 2 100000000000000000000000000000000001111100100011011010100110110111 source: 0 changed: 0 step 3 100000000000000000000000000000000001111100000011011010100110110111 source: ; load TMA from tape bus (00) source: 100 changed: 100 step 4 100000000000000000000000000000000001111100000100011010100110110111 source: 0 changed: 0 step 5 100000000000000000000000000000000001111100000000011010100110110111 source: ; load TBN from tape bus (00) source: 100 changed: 100 step 6 100000000000000000000000000000000001111100000000100010100110110111 source: 0 changed: 0 step 7 100000000000000000000000000000000001111100000000000010100110110111 source: ; load TAC from tape bus (00) source: 10101 changed: 10101 step 8 100000000000000000000000000000000001111100000000000101010110110111 source: 0 changed: 0 step 9 100000000000000000000000000000000001111100000000000001010110110111 source: ; load TB from tape bus (00) source: 100 changed: 100 step 10 100000000000000000000000000000000001111100000000000001011000110111 source: 0 changed: 0 step 11 100000000000000000000000000000000001111100000000000001010000110111 source: ; load RWB from TB (JAMS CLEAR AND PRESET) source: 1 00 changed: 1 00 step 12 100000000000000000000000000000000001111100000000000001010001110001 source: 0 changed: 0 step 13 100000000000000000000000000000000001111100000000000001010000110001 source: ; (no change) source: 100000000000000000000000000000000001111100000000000001010000110001 changed: step 14 100000000000000000000000000000000001111100000000000001010000110001 source: source: source: ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; source: ; source: ; set all registers HIGH source: ; source: ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; source: source: ; set pin AF1 which clears pin BB2 and sets pin BR2 TAPE BUS 3 OUTPUT source: 1 0 1 changed: 1 0 1 step 15 100000000000010000000000000000000000111101000000000001010000110001 source: ; set pin AP2 which clears pin AN2 and sets pin BV2 TAPE BUS 2 OUTPUT source: 1 0 1 changed: 1 0 1 step 16 100000000000010010000000000000000000110111000000000001010000110001 source: source: source: ; load TMA SETUP from tape bus (11) source: 111 changed: 111 step 17 100000000000010010000000000000000000110111111000000001010000110001 source: 0 changed: 0 step 18 100000000000010010000000000000000000110111011000000001010000110001 source: ; load TMA from tape bus (11) source: 111 changed: 111 step 19 100000000000010010000000000000000000110111011111000001010000110001 source: 0 changed: 0 step 20 100000000000010010000000000000000000110111011011000001010000110001 source: ; load TBN from tape bus (11) source: 111 changed: 111 step 21 100000000000010010000000000000000000110111011011111001010000110001 source: 0 changed: 0 step 22 100000000000010010000000000000000000110111011011011001010000110001 source: ; load TAC from tape bus (11) source: 11010 changed: 11010 step 23 100000000000010010000000000000000000110111011011011110100000110001 source: 0 changed: 0 step 24 100000000000010010000000000000000000110111011011011010100000110001 source: ; load TB from tape bus (11) source: 111 changed: 111 step 25 100000000000010010000000000000000000110111011011011010101110110001 source: 0 changed: 0 step 26 100000000000010010000000000000000000110111011011011010100110110001 source: ; load RWB from TB (JAMS CLEAR AND PRESET) source: 1 11 changed: 1 11 step 27 100000000000010010000000000000000000110111011011011010100111110111 source: 0 changed: 0 step 28 100000000000010010000000000000000000110111011011011010100110110111 source: ; clear pin AF1 (AND with itself) to set pin BB2 (AND-NOR output) and clear pin BR2 TAPE BUS 3 OUTPUT source: 0 1 0 changed: 0 1 0 step 29 100000000000000010000000000000000001110110011011011010100110110111 source: ; clear pin AP2 (AND with itself) to set pin AN2 (AND-NOR output) and clear pin BV2 TAPE BUS 2 OUTPUT source: 0 1 0 changed: 0 1 0 step 30 100000000000000000000000000000000001111100011011011010100110110111 source: ; (no change) source: 100000000000000000000000000000000001111100011011011010100110110111 changed: step 31 100000000000000000000000000000000001111100011011011010100110110111 source: source: ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; source: ; source: ; will all registers high, walk a 0 source: ; source: ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; source: source: source: ; walk a 0, TMA SETUP 2 source: source: source: ; clear pin AP2 which sets pin AN2 and clears pin BV2 TAPE BUS 2 OUTPUT source: 0 1 0 changed: step 32 100000000000000000000000000000000001111100011011011010100110110111 source: ; set pin AF1 which clears pin BB2 and sets pin BR2 TAPE BUS 3 OUTPUT source: 1 0 1 changed: 1 0 1 step 33 100000000000010000000000000000000000111101011011011010100110110111 source: ; load TMA SETUP from tape bus (01) source: 101 changed: 10 step 34 100000000000010000000000000000000000111101101011011010100110110111 source: 0 changed: 0 step 35 100000000000010000000000000000000000111101001011011010100110110111 source: ; restore TMA SETUP 2 source: ; set pin AP2 which clears pin AN2 and sets pin BV2 TAPE BUS 2 OUTPUT source: 1 0 1 changed: 1 0 1 step 36 100000000000010010000000000000000000110111001011011010100110110111 source: ; load TMA SETUP from tape bus (11) source: 111 changed: 11 step 37 100000000000010010000000000000000000110111111011011010100110110111 source: 0 changed: 0 step 38 100000000000010010000000000000000000110111011011011010100110110111 space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C toggle comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit comment_flag is 0 space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C toggle comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit comment_flag is 1 space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C toggle comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit source: source: source: ; walk a 0, TMA SETUP 3 source: source: source: ; set pin AP2 which clears pin AN2 and sets pin BV2 TAPE BUS 2 OUTPUT source: 1 0 1 changed: step 39 100000000000010010000000000000000000110111011011011010100110110111 source: ; clear pin AF1 which sets pin BB2 and clears pin BR2 TAPE BUS 3 OUTPUT source: 0 1 0 changed: 0 1 0 step 40 100000000000000010000000000000000001110110011011011010100110110111 source: ; load TMA SETUP from tape bus (10) source: 110 changed: 1 0 step 41 100000000000000010000000000000000001110110110011011010100110110111 source: 0 changed: 0 step 42 100000000000000010000000000000000001110110010011011010100110110111 source: ; restore TMA SETUP 3 source: ; set pin AF1 which clears pin BB2 and sets pin BR2 TAPE BUS 3 OUTPUT source: 1 0 1 changed: 1 0 1 step 43 100000000000010010000000000000000000110111010011011010100110110111 source: ; load TMA SETUP from tape bus (11) source: 111 changed: 1 1 step 44 100000000000010010000000000000000000110111111011011010100110110111 source: 0 changed: 0 step 45 100000000000010010000000000000000000110111011011011010100110110111 source: source: source: ; walk a 0, TMA 2 source: source: source: ; clear pin AP2 which sets pin AN2 and clears pin BV2 TAPE BUS 2 OUTPUT source: 0 1 0 changed: 0 1 0 step 46 100000000000010000000000000000000000111101011011011010100110110111 source: ; set pin AF1 which clears pin BB2 and sets pin BR2 TAPE BUS 3 OUTPUT source: 1 0 1 changed: step 47 100000000000010000000000000000000000111101011011011010100110110111 source: ; load TMA from tape bus (01) source: 101 changed: 10 step 48 100000000000010000000000000000000000111101011101011010100110110111 source: 0 changed: 0 step 49 100000000000010000000000000000000000111101011001011010100110110111 source: ; restore TMA 2 source: ; set pin AP2 which clears pin AN2 and sets pin BV2 TAPE BUS 2 OUTPUT source: 1 0 1 changed: 1 0 1 step 50 100000000000010010000000000000000000110111011001011010100110110111 source: ; load TMA from tape bus (11) source: 111 changed: 11 step 51 100000000000010010000000000000000000110111011111011010100110110111 source: 0 changed: 0 step 52 100000000000010010000000000000000000110111011011011010100110110111 source: source: source: ; walk a 0, TMA 3 source: source: source: ; set pin AP2 which clears pin AN2 and sets pin BV2 TAPE BUS 2 OUTPUT source: 1 0 1 changed: step 53 100000000000010010000000000000000000110111011011011010100110110111 source: ; clear pin AF1 which sets pin BB2 and clears pin BR2 TAPE BUS 3 OUTPUT source: 0 1 0 changed: 0 1 0 step 54 100000000000000010000000000000000001110110011011011010100110110111 source: ; load TMA from tape bus (10) source: 110 changed: 1 0 step 55 100000000000000010000000000000000001110110011110011010100110110111 source: 0 changed: 0 step 56 100000000000000010000000000000000001110110011010011010100110110111 source: ; restore TMA 3 source: ; set pin AF1 which clears pin BB2 and sets pin BR2 TAPE BUS 3 OUTPUT source: 1 0 1 changed: 1 0 1 step 57 100000000000010010000000000000000000110111011010011010100110110111 source: ; load TMA from tape bus (11) source: 111 changed: 1 1 step 58 100000000000010010000000000000000000110111011111011010100110110111 source: 0 changed: 0 step 59 100000000000010010000000000000000000110111011011011010100110110111 source: source: source: ; walk a 0, TBN 2 source: source: source: ; clear pin AP2 which sets pin AN2 and clears pin BV2 TAPE BUS 2 OUTPUT source: 0 1 0 changed: 0 1 0 step 60 100000000000010000000000000000000000111101011011011010100110110111 source: ; set pin AF1 which clears pin BB2 and sets pin BR2 TAPE BUS 3 OUTPUT source: 1 0 1 changed: step 61 100000000000010000000000000000000000111101011011011010100110110111 source: ; load TBN from tape bus (01) source: 101 changed: 10 step 62 100000000000010000000000000000000000111101011011101010100110110111 source: 0 changed: 0 step 63 100000000000010000000000000000000000111101011011001010100110110111 source: ; restore TBN 2 source: ; set pin AP2 which clears pin AN2 and sets pin BV2 TAPE BUS 2 OUTPUT source: 1 0 1 changed: 1 0 1 step 64 100000000000010010000000000000000000110111011011001010100110110111 source: ; load TBN from tape bus (11) source: 111 changed: 11 step 65 100000000000010010000000000000000000110111011011111010100110110111 source: 0 changed: 0 step 66 100000000000010010000000000000000000110111011011011010100110110111 source: source: source: ; walk a 0, TBN 3 source: source: source: ; set pin AP2 which clears pin AN2 and sets pin BV2 TAPE BUS 2 OUTPUT source: 1 0 1 changed: step 67 100000000000010010000000000000000000110111011011011010100110110111 source: ; clear pin AF1 which sets pin BB2 and clears pin BR2 TAPE BUS 3 OUTPUT source: 0 1 0 changed: 0 1 0 step 68 100000000000000010000000000000000001110110011011011010100110110111 source: ; load TBN from tape bus (10) source: 110 changed: 1 0 step 69 100000000000000010000000000000000001110110011011110010100110110111 source: 0 changed: 0 step 70 100000000000000010000000000000000001110110011011010010100110110111 source: ; restore TBN 3 source: ; set pin AF1 which clears pin BB2 and sets pin BR2 TAPE BUS 3 OUTPUT source: 1 0 1 changed: 1 0 1 step 71 100000000000010010000000000000000000110111011011010010100110110111 source: ; load TBN from tape bus (11) source: 111 changed: 1 1 step 72 100000000000010010000000000000000000110111011011111010100110110111 source: 0 changed: 0 step 73 100000000000010010000000000000000000110111011011011010100110110111 source: source: source: ; walk a 0, TAC 2 source: source: source: ; clear pin AP2 which sets pin AN2 and clears pin BV2 TAPE BUS 2 OUTPUT source: 0 1 0 changed: 0 1 0 step 74 100000000000010000000000000000000000111101011011011010100110110111 source: ; set pin AF1 which clears pin BB2 and sets pin BR2 TAPE BUS 3 OUTPUT source: 1 0 1 changed: step 75 100000000000010000000000000000000000111101011011011010100110110111 source: ; load TAC from tape bus (01) source: 10110 changed: 101 step 76 100000000000010000000000000000000000111101011011011101100110110111 source: 0 changed: 0 step 77 100000000000010000000000000000000000111101011011011001100110110111 source: ; restore TAC 2 source: ; set pin AP2 which clears pin AN2 and sets pin BV2 TAPE BUS 2 OUTPUT source: 1 0 1 changed: 1 0 1 step 78 100000000000010010000000000000000000110111011011011001100110110111 source: ; load TAC from tape bus (11) source: 11010 changed: 110 step 79 100000000000010010000000000000000000110111011011011110100110110111 source: 0 changed: 0 step 80 100000000000010010000000000000000000110111011011011010100110110111 source: source: source: ; walk a 0, TAC 3 source: source: source: ; set pin AP2 which clears pin AN2 and sets pin BV2 TAPE BUS 2 OUTPUT source: 1 0 1 changed: step 81 100000000000010010000000000000000000110111011011011010100110110111 source: ; clear pin AF1 which sets pin BB2 and clears pin BR2 TAPE BUS 3 OUTPUT source: 0 1 0 changed: 0 1 0 step 82 100000000000000010000000000000000001110110011011011010100110110111 source: ; load TAC from tape bus (10) source: 11001 changed: 1 01 step 83 100000000000000010000000000000000001110110011011011110010110110111 source: 0 changed: 0 step 84 100000000000000010000000000000000001110110011011011010010110110111 source: ; restore TAC 3 source: ; set pin AF1 which clears pin BB2 and sets pin BR2 TAPE BUS 3 OUTPUT source: 1 0 1 changed: 1 0 1 step 85 100000000000010010000000000000000000110111011011011010010110110111 source: ; load TAC from tape bus (11) source: 11010 changed: 1 10 step 86 100000000000010010000000000000000000110111011011011110100110110111 source: 0 changed: 0 step 87 100000000000010010000000000000000000110111011011011010100110110111 source: source: source: ; walk a 0, TB 2 source: source: source: ; clear pin AP2 which sets pin AN2 and clears pin BV2 TAPE BUS 2 OUTPUT source: 0 1 0 changed: 0 1 0 step 88 100000000000010000000000000000000000111101011011011010100110110111 source: ; set pin AF1 which clears pin BB2 and sets pin BR2 TAPE BUS 3 OUTPUT source: 1 0 1 changed: step 89 100000000000010000000000000000000000111101011011011010100110110111 source: ; load TB from tape bus (01) source: 101 changed: 10 step 90 100000000000010000000000000000000000111101011011011010101010110111 source: 0 changed: 0 step 91 100000000000010000000000000000000000111101011011011010100010110111 source: ; restore TB 2 source: ; set pin AP2 which clears pin AN2 and sets pin BV2 TAPE BUS 2 OUTPUT source: 1 0 1 changed: 1 0 1 step 92 100000000000010010000000000000000000110111011011011010100010110111 source: ; load TB from tape bus (11) source: 111 changed: 11 step 93 100000000000010010000000000000000000110111011011011010101110110111 source: 0 changed: 0 step 94 100000000000010010000000000000000000110111011011011010100110110111 source: source: source: ; walk a 0, TB 3 source: source: source: ; set pin AP2 which clears pin AN2 and sets pin BV2 TAPE BUS 2 OUTPUT source: 1 0 1 changed: step 95 100000000000010010000000000000000000110111011011011010100110110111 source: ; clear pin AF1 which sets pin BB2 and clears pin BR2 TAPE BUS 3 OUTPUT source: 0 1 0 changed: 0 1 0 step 96 100000000000000010000000000000000001110110011011011010100110110111 source: ; load TB from tape bus (10) source: 110 changed: 1 0 step 97 100000000000000010000000000000000001110110011011011010101100110111 source: 0 changed: 0 step 98 100000000000000010000000000000000001110110011011011010100100110111 source: ; restore TB 3 source: ; set pin AF1 which clears pin BB2 and sets pin BR2 TAPE BUS 3 OUTPUT source: 1 0 1 changed: 1 0 1 step 99 100000000000010010000000000000000000110111011011011010100100110111 source: ; load TB from tape bus (11) source: 111 changed: 1 1 step 100 100000000000010010000000000000000000110111011011011010101110110111 source: 0 changed: 0 step 101 100000000000010010000000000000000000110111011011011010100110110111 source: source: source: ; walk a 0, RWB 2 source: source: source: ; clear pin AP2 which sets pin AN2 and clears pin BV2 TAPE BUS 2 OUTPUT source: 0 1 0 changed: 0 1 0 step 102 100000000000010000000000000000000000111101011011011010100110110111 source: ; set pin AF1 which clears pin BB2 and sets pin BR2 TAPE BUS 3 OUTPUT source: 1 0 1 changed: step 103 100000000000010000000000000000000000111101011011011010100110110111 source: ; load TB from tape bus (01) source: 101 changed: 10 step 104 100000000000010000000000000000000000111101011011011010101010110111 source: 0 changed: 0 step 105 100000000000010000000000000000000000111101011011011010100010110111 source: ; load RWB from TB (JAMS CLEAR AND PRESET) source: 1 01 changed: 1 0 step 106 100000000000010000000000000000000000111101011011011010100011110011 source: 0 changed: 0 step 107 100000000000010000000000000000000000111101011011011010100010110011 source: ; restore TB 2 and RWB 2 source: ; set pin AP2 which clears pin AN2 and sets pin BV2 TAPE BUS 2 OUTPUT source: 1 0 1 changed: 1 0 1 step 108 100000000000010010000000000000000000110111011011011010100010110011 source: ; load TB from tape bus (11) source: 111 changed: 11 step 109 100000000000010010000000000000000000110111011011011010101110110011 source: 0 changed: 0 step 110 100000000000010010000000000000000000110111011011011010100110110011 source: ; load RWB from TB (JAMS CLEAR AND PRESET) source: 1 11 changed: 1 1 step 111 100000000000010010000000000000000000110111011011011010100111110111 source: 0 changed: 0 step 112 100000000000010010000000000000000000110111011011011010100110110111 source: source: source: ; walk a 0, RWB 3 source: source: source: ; set pin AP2 which clears pin AN2 and sets pin BV2 TAPE BUS 2 OUTPUT source: 1 0 1 changed: step 113 100000000000010010000000000000000000110111011011011010100110110111 source: ; clear pin AF1 which sets pin BB2 and clears pin BR2 TAPE BUS 3 OUTPUT source: 0 1 0 changed: 0 1 0 step 114 100000000000000010000000000000000001110110011011011010100110110111 source: ; load TB from tape bus (10) source: 110 changed: 1 0 step 115 100000000000000010000000000000000001110110011011011010101100110111 source: 0 changed: 0 step 116 100000000000000010000000000000000001110110011011011010100100110111 source: ; load RWB from TB (JAMS CLEAR AND PRESET) source: 1 10 changed: 1 0 step 117 100000000000000010000000000000000001110110011011011010100101110101 source: 0 changed: 0 step 118 100000000000000010000000000000000001110110011011011010100100110101 source: ; restore TB 3 and RWB 3 source: ; set pin AF1 which clears pin BB2 and sets pin BR2 TAPE BUS 3 OUTPUT source: 1 0 1 changed: 1 0 1 step 119 100000000000010010000000000000000000110111011011011010100100110101 source: ; load TB from tape bus (11) source: 111 changed: 1 1 step 120 100000000000010010000000000000000000110111011011011010101110110101 source: 0 changed: 0 step 121 100000000000010010000000000000000000110111011011011010100110110101 source: ; load RWB from TB (JAMS CLEAR AND PRESET) source: 1 11 changed: 1 1 step 122 100000000000010010000000000000000000110111011011011010100111110111 source: 0 changed: 0 step 123 100000000000010010000000000000000000110111011011011010100110110111 source: source: ; (no change) source: 100000000000000000000000000000000001111100011011011010100110110111 changed: 0 0 1 1 00 step 124 100000000000000000000000000000000001111100011011011010100110110111 source: source: source: ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; source: ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; source: ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; source: ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; source: ;********************* need to walk a one ********************** source: ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; source: ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; source: ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; source: ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; source: source: ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; source: ; source: ; test AND-NOR logic source: ; source: ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; source: source: ; (all registers are HIGH) source: ; set all pins HIGH except ENABLES source: source: ; set pin AF2 HIGH source: 1 changed: 1 step 125 100001000000000000000000000000000001111100011011011010100110110111 source: ; set pin AM1 HIGH source: 1 changed: 1 step 126 100001100000000000000000000000000001111100011011011010100110110111 source: ; set pin AE1 HIGH source: 1 changed: 1 step 127 100001100100000000000000000000000001111100011011011010100110110111 source: ; set pin AM2 HIGH source: 1 changed: 1 step 128 100001100110000000000000000000000001111100011011011010100110110111 source: ; set pin AB2 HIGH source: 1 changed: 1 step 129 100001100110100000000000000000000001111100011011011010100110110111 source: ; set pin AS1 HIGH source: 1 changed: 1 step 130 100001100110100100000000000000000001111100011011011010100110110111 source: ; set pin BE1 HIGH source: 1 changed: 1 step 131 100001100110100100010000000000000001111100011011011010100110110111 source: ; set pin BM1 HIGH source: 1 changed: 1 step 132 100001100110100100011000000000000001111100011011011010100110110111 source: ; set pin BH1 HIGH source: 1 changed: 1 step 133 100001100110100100011010000000000001111100011011011010100110110111 source: ; set pin BR1 HIGH source: 1 changed: 1 step 134 100001100110100100011011000000000001111100011011011010100110110111 source: ; set pin BC1 HIGH source: 1 changed: 1 step 135 100001100110100100011011010000000001111100011011011010100110110111 source: ; set pin BJ2 HIGH source: 1 changed: 1 step 136 100001100110100100011011011000000001111100011011011010100110110111 source: ; set pin BJ1 HIGH source: 1 changed: 1 step 137 100001100110100100011011011010000001111100011011011010100110110111 source: ; set pin BK2 HIGH source: 1 changed: 1 step 138 100001100110100100011011011011000001111100011011011010100110110111 source: ; set pin BH2 HIGH source: 1 changed: 1 step 139 100001100110100100011011011011010001111100011011011010100110110111 source: ; set pin BP2 HIGH source: 1 changed: 1 step 140 100001100110100100011011011011011001111100011011011010100110110111 source: ; set pin BN2 HIGH source: 1 changed: 1 step 141 100001100110100100011011011011011101111100011011011010100110110111 source: ; toggle each ENABLE source: source: ; set pin AL2 to clear pin BB2 and pin AN2 AND-NOR OUTPUTS and set TAPE BUS 2 OUTPUT and TAPE BUS 3 OUTPUT source: 1 0 0 11 changed: 1 0 0 11 step 142 110001100110100100011011011011011100110111011011011010100110110111 source: 0 1 1 00 changed: 0 1 1 00 step 143 100001100110100100011011011011011101111100011011011010100110110111 source: ; set pin AP1 to clear pin BB2 and pin AN2 AND-NOR OUTPUTS and set TAPE BUS 2 OUTPUT and TAPE BUS 3 OUTPUT source: 1 0 0 11 changed: 1 0 0 11 step 144 101001100110100100011011011011011100110111011011011010100110110111 source: 0 1 1 00 changed: 0 1 1 00 step 145 100001100110100100011011011011011101111100011011011010100110110111 source: ; set pin AS2 to clear pin BB2 and pin AN2 AND-NOR OUTPUTS and set TAPE BUS 2 OUTPUT and TAPE BUS 3 OUTPUT source: 1 0 0 11 changed: 1 0 0 11 step 146 100101100110100100011011011011011100110111011011011010100110110111 source: 0 1 1 00 changed: 0 1 1 00 step 147 100001100110100100011011011011011101111100011011011010100110110111 source: ; set pin AL1 to clear pin BB2 and pin AN2 AND-NOR OUTPUTS and set TAPE BUS 2 OUTPUT and TAPE BUS 3 OUTPUT source: 1 0 0 11 changed: 1 0 0 11 step 148 100011100110100100011011011011011100110111011011011010100110110111 source: 0 1 1 00 changed: 0 1 1 00 step 149 100001100110100100011011011011011101111100011011011010100110110111 source: ; set pin AL1 to clear pin BB2 and pin AN2 AND-NOR OUTPUTS and set TAPE BUS 2 OUTPUT and TAPE BUS 3 OUTPUT source: 1 0 0 11 changed: 1 0 0 11 step 150 100001110110100100011011011011011100110111011011011010100110110111 source: 0 1 1 00 changed: 0 1 1 00 step 151 100001100110100100011011011011011101111100011011011010100110110111 source: ; set pin AE2 to clear pin BB2 and pin AN2 AND-NOR OUTPUTS and set TAPE BUS 2 OUTPUT and TAPE BUS 3 OUTPUT source: 1 0 0 11 changed: 1 0 0 11 step 152 100001101110100100011011011011011100110111011011011010100110110111 source: 0 1 1 00 changed: 0 1 1 00 step 153 100001100110100100011011011011011101111100011011011010100110110111 source: ; set pin AC1 to clear pin BB2 and set TAPE BUS 3 OUTPUT source: 1 0 1 changed: 1 0 1 step 154 100001100111100100011011011011011100111101011011011010100110110111 source: 0 1 0 changed: 0 1 0 step 155 100001100110100100011011011011011101111100011011011010100110110111 source: ; set pin AF1 to clear pin BB2 and set TAPE BUS 3 OUTPUT source: 1 0 1 changed: 1 0 1 step 156 100001100110110100011011011011011100111101011011011010100110110111 source: 0 1 0 changed: 0 1 0 step 157 100001100110100100011011011011011101111100011011011010100110110111 source: ; set pin AR2 to clear pin AN2 AND-NOR OUTPUTS and set TAPE BUS 2 OUTPUT source: 1 0 1 changed: 1 0 1 step 158 100001100110101100011011011011011101110110011011011010100110110111 source: 0 1 0 changed: 0 1 0 step 159 100001100110100100011011011011011101111100011011011010100110110111 source: ; set pin AP2 to clear pin AN2 AND-NOR OUTPUTS and set TAPE BUS 2 OUTPUT source: 1 0 1 changed: 1 0 1 step 160 100001100110100110011011011011011101110110011011011010100110110111 source: 0 1 0 changed: 0 1 0 step 161 100001100110100100011011011011011101111100011011011010100110110111 source: source: ; set pin BK1 to clear pin BB1 and pin BN1 AND-NOR OUTPUTS and set TAPE BUS 2 OUTPUT and TAPE BUS 3 OUTPUT source: 1 00 11 changed: 1 00 11 step 162 100001100110100101011011011011011101001111011011011010100110110111 source: 0 11 00 changed: 0 11 00 step 163 100001100110100100011011011011011101111100011011011010100110110111 source: ; set pin BL1 to clear pin BB1 and pin BN1 AND-NOR OUTPUTS and set TAPE BUS 2 OUTPUT and TAPE BUS 3 OUTPUT source: 1 00 11 changed: 1 00 11 step 164 100001100110100100111011011011011101001111011011011010100110110111 source: 0 11 00 changed: 0 11 00 step 165 100001100110100100011011011011011101111100011011011010100110110111 source: ; set pin BF1 to clear pin BB1 and pin BN1 AND-NOR OUTPUTS and set TAPE BUS 2 OUTPUT and TAPE BUS 3 OUTPUT source: 1 00 11 changed: 1 00 11 step 166 100001100110100100011111011011011101001111011011011010100110110111 source: 0 11 00 changed: 0 11 00 step 167 100001100110100100011011011011011101111100011011011010100110110111 source: ; set pin BS1 to clear pin BB1 and pin BN1 AND-NOR OUTPUTS and set TAPE BUS 2 OUTPUT and TAPE BUS 3 OUTPUT source: 1 00 11 changed: 1 00 11 step 168 100001100110100100011011111011011101001111011011011010100110110111 source: 0 11 00 changed: 0 11 00 step 169 100001100110100100011011011011011101111100011011011010100110110111 source: ; set pin BL2 to clear pin BB1 and pin BN1 AND-NOR OUTPUTS and set TAPE BUS 2 OUTPUT and TAPE BUS 3 OUTPUT source: 1 00 11 changed: 1 00 11 step 170 100001100110100100011011011111011101001111011011011010100110110111 source: 0 11 00 changed: 0 11 00 step 171 100001100110100100011011011011011101111100011011011010100110110111 source: ; set pin BU1 to clear pin BB1 and pin BN1 AND-NOR OUTPUTS and set TAPE BUS 2 OUTPUT and TAPE BUS 3 OUTPUT source: 1 00 11 changed: 1 00 11 step 172 100001100110100100011011011011111101001111011011011010100110110111 source: 0 11 00 changed: 0 11 00 step 173 100001100110100100011011011011011101111100011011011010100110110111 source: ; set pin BM2 to clear pin BB1 and TAPE BUS 3 OUTPUT source: 1 0 1 changed: 1 0 1 step 174 100001100110100100011011011011011111101110011011011010100110110111 source: 0 1 0 changed: 0 1 0 step 175 100001100110100100011011011011011101111100011011011010100110110111 source: ; no change source: 100000000000000000000000000000000001111100011011011010100110110111 changed: 00 00 0 0 00 00 00 00 000 step 176 100000000000000000000000000000000001111100011011011010100110110111 source: source: source: ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; source: ; test shifting the RWB source: ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; source: source: ; shift in 0, expect 10 source: 0 changed: 0 step 177 100000000000000000000000000000000001111100011011011010100110100111 source: 110 changed: 1 0 step 178 100000000000000000000000000000000001111100011011011010100110101101 source: 0 changed: 0 step 179 100000000000000000000000000000000001111100011011011010100110100101 source: ; toggle phase should toggle RWB 2 source: 0 0 changed: 0 0 step 180 100000000000000000000000000000000001111100011011011010100110000001 source: 1 1 changed: 1 1 step 181 100000000000000000000000000000000001111100011011011010100110100101 source: source: ; shift in 0, expect 00 source: 0 changed: step 182 100000000000000000000000000000000001111100011011011010100110100101 source: 100 changed: 10 step 183 100000000000000000000000000000000001111100011011011010100110101001 source: 0 changed: 0 step 184 100000000000000000000000000000000001111100011011011010100110100001 source: ; toggle phase should toggle RWB 2 source: 0 1 changed: 0 1 step 185 100000000000000000000000000000000001111100011011011010100110000101 source: 1 0 changed: 1 0 step 186 100000000000000000000000000000000001111100011011011010100110100001 source: source: ; shift in 0, expect 00 source: 0 changed: step 187 100000000000000000000000000000000001111100011011011010100110100001 source: 100 changed: 1 step 188 100000000000000000000000000000000001111100011011011010100110101001 source: 0 changed: 0 step 189 100000000000000000000000000000000001111100011011011010100110100001 source: ; shift in 1, expect 01 source: 1 changed: 1 step 190 100000000000000000000000000000000001111100011011011010100110110001 source: 101 changed: 1 1 step 191 100000000000000000000000000000000001111100011011011010100110111011 source: 0 changed: 0 step 192 100000000000000000000000000000000001111100011011011010100110110011 source: ; shift in 1, expect 11 source: 1 changed: step 193 100000000000000000000000000000000001111100011011011010100110110011 source: 111 changed: 11 step 194 100000000000000000000000000000000001111100011011011010100110111111 source: 0 changed: 0 step 195 100000000000000000000000000000000001111100011011011010100110110111 source: ; shift in 1, expect 11 source: 1 changed: step 196 100000000000000000000000000000000001111100011011011010100110110111 source: 111 changed: 1 step 197 100000000000000000000000000000000001111100011011011010100110111111 source: 0 changed: 0 step 198 100000000000000000000000000000000001111100011011011010100110110111 source: ; shift in 0, expect 10 source: 0 changed: 0 step 199 100000000000000000000000000000000001111100011011011010100110100111 source: 110 changed: 1 0 step 200 100000000000000000000000000000000001111100011011011010100110101101 source: 0 changed: 0 step 201 100000000000000000000000000000000001111100011011011010100110100101 source: ; shift in 1, expect 01 source: 1 changed: 1 step 202 100000000000000000000000000000000001111100011011011010100110110101 source: 101 changed: 101 step 203 100000000000000000000000000000000001111100011011011010100110111011 source: 0 changed: 0 step 204 100000000000000000000000000000000001111100011011011010100110110011 source: ; shift in 0, expect 10 source: 0 changed: 0 step 205 100000000000000000000000000000000001111100011011011010100110100011 source: 110 changed: 110 step 206 100000000000000000000000000000000001111100011011011010100110101101 source: 0 changed: 0 step 207 100000000000000000000000000000000001111100011011011010100110100101 source: ; shift in 1, expect 01 source: 1 changed: 1 step 208 100000000000000000000000000000000001111100011011011010100110110101 source: 101 changed: 101 step 209 100000000000000000000000000000000001111100011011011010100110111011 source: 0 changed: 0 step 210 100000000000000000000000000000000001111100011011011010100110110011 source: ; shift in 1, expect 11 source: 1 changed: step 211 100000000000000000000000000000000001111100011011011010100110110011 source: 111 changed: 11 step 212 100000000000000000000000000000000001111100011011011010100110111111 source: 0 changed: 0 step 213 100000000000000000000000000000000001111100011011011010100110110111 source: ; no change source: 100000000000000000000000000000000001111100011011011010100110110111 changed: step 214 100000000000000000000000000000000001111100011011011010100110110111 test 5: pass SLOT BAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBAABBAAAAAAAAAAAAAABBBBBABBBB LETTER ALPSLFMDEEMCBFRSPKLEMFHRSCJLJKUHPNMBBNNVVRKRHUTDJUKANJHBTPDFSVEVDU SIDE 121212122121212121111111112212122222112222111221112112212112212122 DIRECTION IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIOOOOOOOIOOIOOIOOIOOOOIOOIIIIOOO this fail all fails was hi 111111111111111111111111111111111111111111111111111111111111111111 rising ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ ^^^^^^^^^^^^^^^^^^^^^^^^^ falling vvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvv vvvvvvvvvvvvvvvvvvvvvvvvv was lo 00000000000000000000000000000000000000 0000000000000000000000000 total fails 0, total passes 5 space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C toggle comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT BAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBAABBAAAAAAAAAAAAAABBBBBABBBB LETTER ALPSLFMDEEMCBFRSPKLEMFHRSCJLJKUHPNMBBNNVVRKRHUTDJUKANJHBTPDFSVEVDU SIDE 121212122121212121111111112212122222112222111221112112212112212122 DIRECTION IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIOOOOOOOIOOIOOIOOIOOOOIOOIIIIOOO all fails was lo 00000000000000000000000000000000000000 0000000000000000000000000 falling vvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvv vvvvvvvvvvvvvvvvvvvvvvvvv rising ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ ^^^^^^^^^^^^^^^^^^^^^^^^^ was hi 111111111111111111111111111111111111111111111111111111111111111111 total fails 0, total passes 5 Main menu Thu Aug 20 18:57:43 2015 test file is: tests\m222.new delay is: 0 trigger is: 1 1 read test file 2 set test delay 3 set test trigger 4 run test 5 output loading test 8 diags 9 exit Enter test file name? trying to open test file: tests\m222.new reading test file: tests\m222.new comment: M222 PCB REV B SCHEMATIC REV A LINC TAPE REGISTERS comment: comment: TERMINOLOGY- SIGNALS REFER TO PDP12 MAINT VOL4 M222 SCHEMATIC. comment: comment: BUT... comment: comment: DEC USES AND-NOR GATES TO ROUTE THE ADDER A AND B INPUTS, SO... comment: DEC RENAMED THE ADDER TO NEGATIVE LOGIC TERMS (I.E. A-N + B-N + C-N -> SUM-N, C1-N). comment: (NOT THE 7482 DATASHEET NAMES OF A + B + C -> SUM, C1). comment: comment: SO, WITH ALL 'AND ENABLES' LOW, THE AND-NOR OUTPUTS = HIGH. comment: WITH C-L HIGH, THE ADDER OUTPUT IS SUM-N=1, C1-N=1; comment: THE INVERTED ADDER OUTPUT IS LOW (TAPE BUS). comment: AND THERE IS NO CARRY (C1-N IS HI). comment: comment: THE TWO ADDERS, TWO REGISTER BITS, ETC ARE LABELED BIT 2 (EVEN, MSB) AND BIT 3 (ODD, LSB). comment: THE ADDERS ARE REFERRED TO AS 'ADDER2' (MSB) AND 'ADDER3' (LSB). comment: comment: POWER PINS: comment: AA2 +5V comment: AT1 GROUND comment: AC2 GROUND comment: BA2 +5V comment: BT1 GROUND comment: BC2 GROUND comment: comment: (ALL PINS ARE USED). comment: comment: pins: PINS pins: 1 I BA1 CARRY IN-N, (TO E9-5 7482 C0) C-N TO ADDER2 pins: 2 I AL2 AND-NOR ENABLE: TAC TAC3 TO PIN BB2 (TO ADDER3) TAC2 TO PIN AN2 (TO ADDER2) pins: 3 I AP1 AND-NOR ENABLE: TMA SETUP (TMAS)3 TO PIN BB2 (TO ADDER3), (TMAS)3 TO PIN AN2 (TO ADDER2) pins: 4 I AS2 AND-NOR ENABLE: TMA TMA3 TO PIN BB2 (TO ADDER3), TMA2 TO PIN AN2 (TO ADDER2) pins: 5 I AL1 AND-NOR ENABLE: PIN AF2 TO PIN BB2 (TO ADDER3), PIN AM1 TO PIN AN2 (TO ADDER2) pins: 6 I AF2 AND-NOR INPUT (AL1 ENABLES) TO PIN BB2 (TO ADDER3). pins: 7 I AM1 AND-NOR INPUT (AL1 ENABLES) TO PIN AN2 (TO ADDER2) pins: 8 I AD2 AND-NOR ENABLE: RWB RWB3 TO PIN BB2 (TO ADDER3), RWB2 TO PIN AN2 (TO ADDER2) pins: 9 I AE2 AND-NOR ENABLE: PIN AE1 TO PIN BB2 (TO ADDER3), PIN AM2 TO PIN AN2 (TO ADDER2) pins: 10 I AE1 AND-NOR INPUT (AE2 ENABLES) TO PIN BB2 (TO ADDER3). pins: 11 I AM2 AND-NOR INPUT (AE2 ENABLES) TO PIN AN2 (TO ADDER2) pins: 12 I AC1 AND-NOR INPUT, AND WITH PIN AB2 TO PIN BB2 (TO ADDER3) pins: 13 I AB2 AND-NOR INPUT, AND WITH PIN AC1 TO PIN BB2 (TO ADDER3) pins: 14 I AF1 AND-NOR INPUT (AND WITH ITSELF) TO PIN BB2 (TO ADDER3) pins: 15 I AR2 AND-NOR INPUT, AND WITH PIN AS1 TO PIN AN2 (TO ADDER2) pins: 16 I AS1 AND-NOR INPUT, AND WITH PIN AR2 TO PIN AN2 (TO ADDER2) pins: 17 I AP2 AND-NOR INPUT (AND WITH ITSELF) TO PIN AN2 (TO ADDER2) pins: 18 I BK1 AND-NOR ENABLE: TB3 TO PIN BB1 (TO ADDER3), TB2 TO PIN BN1 (TO ADDER2) pins: 19 I BL1 AND-NOR ENABLE: PIN BE1 TO PIN BB1 (TO ADDER3), PIN BM1 TO PIN BN1 (TO ADDER2) pins: 20 I BE1 AND-NOR INPUT (BL1 ENABLES) TO PIN BB1 (TO ADDER3). pins: 21 I BM1 AND-NOR INPUT (BL1 ENABLES) TO PIN BN1 (TO ADDER2) pins: 22 I BF1 AND-NOR ENABLE: PIN BH1 TO PIN BB1 (TO ADDER3), PIN BR1 TO PIN BN1 (TO ADDER2) pins: 23 I BH1 AND-NOR INPUT (BF1 ENABLES): TO PIN BB1 (TO ADDER3), pins: 24 I BR1 AND-NOR INPUT (BF1 ENABLES): TO PIN BN1 (TO ADDER2) pins: 25 I BS1 AND-NOR ENABLE: PIN BC1 TO PIN BB1 (TO ADDER3), PIN BJ2 TO PIN BN1 (TO ADDER2) pins: 26 I BC1 AND-NOR INPUT (BS1 ENABLES): TO PIN BB1 (TO ADDER3), pins: 27 I BJ2 AND-NOR INPUT (BS1 ENABLES): TO PIN BN1 (TO ADDER2) pins: 28 I BL2 AND-NOR ENABLE: PIN BJ1 TO PIN BB1 (TO ADDER3), PIN BK2 TO PIN BN1 (TO ADDER2) pins: 29 I BJ1 AND-NOR INPUT (BL2 ENABLES): TO PIN BB1 (TO ADDER3), pins: 30 I BK2 AND-NOR INPUT (BL2 ENABLES): TO PIN BN1 (TO ADDER2) pins: 31 I BU1 AND-NOR ENABLE: PIN BH2 TO PIN BB1 (TO ADDER3), PIN BP2 TO PIN BN1 (TO ADDER2) pins: 32 I BH2 AND-NOR INPUT (BU1 ENABLES): TO PIN BB1 (TO ADDER3), pins: 33 I BP2 AND-NOR INPUT (BU1 ENABLES): TO PIN BN1 (TO ADDER2) pins: 34 I BN2 AND-NOR INPUT (AND WITH BM2): TO PIN BN1 (TO ADDER2) pins: 35 I BM2 AND-NOR INPUT (AND WITH BM2): TO PIN BN1 (TO ADDER2) pins: 36 O BB2 AND-NOR OUTPUT, (DRIVES E9-2 7482 A1) TO ADDER3 INPUT pins: 37 O BB1 AND-NOR OUTPUT, (DRIVES E9-3 7482 B1) TO ADDER3 INPUT pins: 38 O BN1 AND-NOR OUTPUT, (DRIVES E9-14 7482 A2) TO ADDER2 INPUT pins: 39 O AN2 AND-NOR OUTPUT, (DRIVES E9-13 7482 B2) TO ADDER2 INPUT pins: 40 O AV2 CARRY OUT-N (E9-10 7482 C2) pins: 41 O BV2 TAPE BUS 2 OUTPUT (INVERTED ADDER2 SUM-N (E9-12 7482 SUM2) pins: 42 O BR2 TAPE BUS 3 OUTPUT (INVERTED ADDER3 SUM-N (E9-1 7482 SUM1) pins: 43 I AK1 LOAD TMA SETUP (FROM TAPE BUS) (RISING EDGE CLOCK) pins: 44 O AR1 TMA SETUP 2 pins: 45 O AH1 TMA SETUP 3 pins: 46 I AU2 LOAD TMA (FROM TAPE BUS) (RISING EDGE CLOCK) pins: 47 O AT2 TMA 2 pins: 48 O AD1 TMA 3 pins: 49 I AJ1 LOAD TBN (FROM TAPE BUS) (RISING EDGE CLOCK) pins: 50 O AU1 TBN 2 pins: 51 O AK2 TBN 3 pins: 52 I AA1 LOAD TAC (FROM TAPE BUS) (RISING EDGE CLOCK) pins: 53 O AN1 TAC 2 pins: 54 O AJ2 TAC 2-N pins: 55 O AH2 TAC 3 pins: 56 O AB1 TAC 3-N pins: 57 I BT2 LOAD TB (FROM TAPE BUS) (RISING EDGE CLOCK) pins: 58 O BP1 TB 2 pins: 59 O BD1 TB 3 pins: 60 I BF2 LOAD RWB (FROM TB) (JAMS CLEAR,SET) pins: 61 I BS2 PHASE (SELECTS POLARITY OF RWB OUT, 0 -> INVERTED) pins: 62 I AV1 RWB IN (SHIFTED INTO RWB 3) pins: 63 I BE2 SHIFT RWB (SHIFTS PIN AV1 INTO RWB 3, SHIFTS RWB3 TO RWB2) (RISING CLOCK) pins: 64 O BV1 RWB OUT (IF PHASE=1, =RWB 2; IF PHASE=0; =RWB 2-N) pins: 65 O BD2 RWB 3 pins: 66 O BU2 +3.5V pins: direction: IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIOOOOOOOIOOIOOIOOIOOOOIOOIIIIOOO comment: ; all registers are unknown comment: ; turn on C0, PHASE comment: ; with no ENABLES, BUS2,BUS3 is 11, C2 is 1 test 1: 1000000000000000000000000000000000011111000XX0XX0XX0XXXX0XX0110XX1 comment: comment: ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; comment: ; comment: ; set all registers LOW comment: ; comment: ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; comment: comment: ; load TMA SETUP from tape bus (00) test 2: 100 test 3: 0 comment: ; load TMA from tape bus (00) test 4: 100 test 5: 0 comment: ; load TBN from tape bus (00) test 6: 100 test 7: 0 comment: ; load TAC from tape bus (00) test 8: 10101 test 9: 0 comment: ; load TB from tape bus (00) test 10: 100 test 11: 0 comment: ; load RWB from TB (JAMS CLEAR AND PRESET) test 12: 1 00 test 13: 0 comment: ; (no change) test 14: 100000000000000000000000000000000001111100000000000001010000110001 comment: comment: comment: ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; comment: ; comment: ; set all registers HIGH comment: ; comment: ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; comment: comment: ; set pin AF1 which clears pin BB2 and sets pin BR2 TAPE BUS 3 OUTPUT test 15: 1 0 1 comment: ; set pin AP2 which clears pin AN2 and sets pin BV2 TAPE BUS 2 OUTPUT test 16: 1 0 1 comment: comment: comment: ; load TMA SETUP from tape bus (11) test 17: 111 test 18: 0 comment: ; load TMA from tape bus (11) test 19: 111 test 20: 0 comment: ; load TBN from tape bus (11) test 21: 111 test 22: 0 comment: ; load TAC from tape bus (11) test 23: 11010 test 24: 0 comment: ; load TB from tape bus (11) test 25: 111 test 26: 0 comment: ; load RWB from TB (JAMS CLEAR AND PRESET) test 27: 1 11 test 28: 0 comment: ; clear pin AF1 (AND with itself) to set pin BB2 (AND-NOR output) and clear pin BR2 TAPE BUS 3 OUTPUT test 29: 0 1 0 comment: ; clear pin AP2 (AND with itself) to set pin AN2 (AND-NOR output) and clear pin BV2 TAPE BUS 2 OUTPUT test 30: 0 1 0 comment: ; (no change) test 31: 100000000000000000000000000000000001111100011011011010100110110111 comment: comment: ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; comment: ; comment: ; will all registers high, walk a 0 comment: ; comment: ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; comment: comment: comment: ; walk a 0, TMA SETUP 2 comment: comment: comment: ; clear pin AP2 which sets pin AN2 and clears pin BV2 TAPE BUS 2 OUTPUT test 32: 0 1 0 comment: ; set pin AF1 which clears pin BB2 and sets pin BR2 TAPE BUS 3 OUTPUT test 33: 1 0 1 comment: ; load TMA SETUP from tape bus (01) test 34: 101 test 35: 0 comment: ; restore TMA SETUP 2 comment: ; set pin AP2 which clears pin AN2 and sets pin BV2 TAPE BUS 2 OUTPUT test 36: 1 0 1 comment: ; load TMA SETUP from tape bus (11) test 37: 111 test 38: 0 comment: comment: comment: ; walk a 0, TMA SETUP 3 comment: comment: comment: ; set pin AP2 which clears pin AN2 and sets pin BV2 TAPE BUS 2 OUTPUT test 39: 1 0 1 comment: ; clear pin AF1 which sets pin BB2 and clears pin BR2 TAPE BUS 3 OUTPUT test 40: 0 1 0 comment: ; load TMA SETUP from tape bus (10) test 41: 110 test 42: 0 comment: ; restore TMA SETUP 3 comment: ; set pin AF1 which clears pin BB2 and sets pin BR2 TAPE BUS 3 OUTPUT test 43: 1 0 1 comment: ; load TMA SETUP from tape bus (11) test 44: 111 test 45: 0 comment: comment: comment: ; walk a 0, TMA 2 comment: comment: comment: ; clear pin AP2 which sets pin AN2 and clears pin BV2 TAPE BUS 2 OUTPUT test 46: 0 1 0 comment: ; set pin AF1 which clears pin BB2 and sets pin BR2 TAPE BUS 3 OUTPUT test 47: 1 0 1 comment: ; load TMA from tape bus (01) test 48: 101 test 49: 0 comment: ; restore TMA 2 comment: ; set pin AP2 which clears pin AN2 and sets pin BV2 TAPE BUS 2 OUTPUT test 50: 1 0 1 comment: ; load TMA from tape bus (11) test 51: 111 test 52: 0 comment: comment: comment: ; walk a 0, TMA 3 comment: comment: comment: ; set pin AP2 which clears pin AN2 and sets pin BV2 TAPE BUS 2 OUTPUT test 53: 1 0 1 comment: ; clear pin AF1 which sets pin BB2 and clears pin BR2 TAPE BUS 3 OUTPUT test 54: 0 1 0 comment: ; load TMA from tape bus (10) test 55: 110 test 56: 0 comment: ; restore TMA 3 comment: ; set pin AF1 which clears pin BB2 and sets pin BR2 TAPE BUS 3 OUTPUT test 57: 1 0 1 comment: ; load TMA from tape bus (11) test 58: 111 test 59: 0 comment: comment: comment: ; walk a 0, TBN 2 comment: comment: comment: ; clear pin AP2 which sets pin AN2 and clears pin BV2 TAPE BUS 2 OUTPUT test 60: 0 1 0 comment: ; set pin AF1 which clears pin BB2 and sets pin BR2 TAPE BUS 3 OUTPUT test 61: 1 0 1 comment: ; load TBN from tape bus (01) test 62: 101 test 63: 0 comment: ; restore TBN 2 comment: ; set pin AP2 which clears pin AN2 and sets pin BV2 TAPE BUS 2 OUTPUT test 64: 1 0 1 comment: ; load TBN from tape bus (11) test 65: 111 test 66: 0 comment: comment: comment: ; walk a 0, TBN 3 comment: comment: comment: ; set pin AP2 which clears pin AN2 and sets pin BV2 TAPE BUS 2 OUTPUT test 67: 1 0 1 comment: ; clear pin AF1 which sets pin BB2 and clears pin BR2 TAPE BUS 3 OUTPUT test 68: 0 1 0 comment: ; load TBN from tape bus (10) test 69: 110 test 70: 0 comment: ; restore TBN 3 comment: ; set pin AF1 which clears pin BB2 and sets pin BR2 TAPE BUS 3 OUTPUT test 71: 1 0 1 comment: ; load TBN from tape bus (11) test 72: 111 test 73: 0 comment: comment: comment: ; walk a 0, TAC 2 comment: comment: comment: ; clear pin AP2 which sets pin AN2 and clears pin BV2 TAPE BUS 2 OUTPUT test 74: 0 1 0 comment: ; set pin AF1 which clears pin BB2 and sets pin BR2 TAPE BUS 3 OUTPUT test 75: 1 0 1 comment: ; load TAC from tape bus (01) test 76: 10110 test 77: 0 comment: ; restore TAC 2 comment: ; set pin AP2 which clears pin AN2 and sets pin BV2 TAPE BUS 2 OUTPUT test 78: 1 0 1 comment: ; load TAC from tape bus (11) test 79: 11010 test 80: 0 comment: comment: comment: ; walk a 0, TAC 3 comment: comment: comment: ; set pin AP2 which clears pin AN2 and sets pin BV2 TAPE BUS 2 OUTPUT test 81: 1 0 1 comment: ; clear pin AF1 which sets pin BB2 and clears pin BR2 TAPE BUS 3 OUTPUT test 82: 0 1 0 comment: ; load TAC from tape bus (10) test 83: 11001 test 84: 0 comment: ; restore TAC 3 comment: ; set pin AF1 which clears pin BB2 and sets pin BR2 TAPE BUS 3 OUTPUT test 85: 1 0 1 comment: ; load TAC from tape bus (11) test 86: 11010 test 87: 0 comment: comment: comment: ; walk a 0, TB 2 comment: comment: comment: ; clear pin AP2 which sets pin AN2 and clears pin BV2 TAPE BUS 2 OUTPUT test 88: 0 1 0 comment: ; set pin AF1 which clears pin BB2 and sets pin BR2 TAPE BUS 3 OUTPUT test 89: 1 0 1 comment: ; load TB from tape bus (01) test 90: 101 test 91: 0 comment: ; restore TB 2 comment: ; set pin AP2 which clears pin AN2 and sets pin BV2 TAPE BUS 2 OUTPUT test 92: 1 0 1 comment: ; load TB from tape bus (11) test 93: 111 test 94: 0 comment: comment: comment: ; walk a 0, TB 3 comment: comment: comment: ; set pin AP2 which clears pin AN2 and sets pin BV2 TAPE BUS 2 OUTPUT test 95: 1 0 1 comment: ; clear pin AF1 which sets pin BB2 and clears pin BR2 TAPE BUS 3 OUTPUT test 96: 0 1 0 comment: ; load TB from tape bus (10) test 97: 110 test 98: 0 comment: ; restore TB 3 comment: ; set pin AF1 which clears pin BB2 and sets pin BR2 TAPE BUS 3 OUTPUT test 99: 1 0 1 comment: ; load TB from tape bus (11) test 100: 111 test 101: 0 comment: comment: comment: ; walk a 0, RWB 2 comment: comment: comment: ; clear pin AP2 which sets pin AN2 and clears pin BV2 TAPE BUS 2 OUTPUT test 102: 0 1 0 comment: ; set pin AF1 which clears pin BB2 and sets pin BR2 TAPE BUS 3 OUTPUT test 103: 1 0 1 comment: ; load TB from tape bus (01) test 104: 101 test 105: 0 comment: ; load RWB from TB (JAMS CLEAR AND PRESET) test 106: 1 01 test 107: 0 comment: ; restore TB 2 and RWB 2 comment: ; set pin AP2 which clears pin AN2 and sets pin BV2 TAPE BUS 2 OUTPUT test 108: 1 0 1 comment: ; load TB from tape bus (11) test 109: 111 test 110: 0 comment: ; load RWB from TB (JAMS CLEAR AND PRESET) test 111: 1 11 test 112: 0 comment: comment: comment: ; walk a 0, RWB 3 comment: comment: comment: ; set pin AP2 which clears pin AN2 and sets pin BV2 TAPE BUS 2 OUTPUT test 113: 1 0 1 comment: ; clear pin AF1 which sets pin BB2 and clears pin BR2 TAPE BUS 3 OUTPUT test 114: 0 1 0 comment: ; load TB from tape bus (10) test 115: 110 test 116: 0 comment: ; load RWB from TB (JAMS CLEAR AND PRESET) test 117: 1 10 test 118: 0 comment: ; restore TB 3 and RWB 3 comment: ; set pin AF1 which clears pin BB2 and sets pin BR2 TAPE BUS 3 OUTPUT test 119: 1 0 1 comment: ; load TB from tape bus (11) test 120: 111 test 121: 0 comment: ; load RWB from TB (JAMS CLEAR AND PRESET) test 122: 1 11 test 123: 0 comment: comment: ; clear pin AF1 (AND with itself) to set pin BB2 (AND-NOR output) and clear pin BR2 TAPE BUS 3 OUTPUT test 124: 0 1 0 comment: ; clear pin AP2 (AND with itself) to set pin AN2 (AND-NOR output) and clear pin BV2 TAPE BUS 2 OUTPUT test 125: 0 1 0 comment: ; (no change) test 126: 100000000000000000000000000000000001111100011011011010100110110111 comment: comment: comment: ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; comment: ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; comment: ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; comment: ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; comment: ;********************* need to walk a one ********************** comment: ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; comment: ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; comment: ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; comment: ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; comment: comment: ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; comment: ; comment: ; test AND-NOR logic comment: ; comment: ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; comment: comment: ; (all registers are HIGH) comment: ; set all pins HIGH except ENABLES comment: comment: ; set pin AF2 HIGH test 127: 1 comment: ; set pin AM1 HIGH test 128: 1 comment: ; set pin AE1 HIGH test 129: 1 comment: ; set pin AM2 HIGH test 130: 1 comment: ; set pin AB2 HIGH test 131: 1 comment: ; set pin AS1 HIGH test 132: 1 comment: ; set pin BE1 HIGH test 133: 1 comment: ; set pin BM1 HIGH test 134: 1 comment: ; set pin BH1 HIGH test 135: 1 comment: ; set pin BR1 HIGH test 136: 1 comment: ; set pin BC1 HIGH test 137: 1 comment: ; set pin BJ2 HIGH test 138: 1 comment: ; set pin BJ1 HIGH test 139: 1 comment: ; set pin BK2 HIGH test 140: 1 comment: ; set pin BH2 HIGH test 141: 1 comment: ; set pin BP2 HIGH test 142: 1 comment: ; set pin BN2 HIGH test 143: 1 comment: ; toggle each ENABLE comment: comment: ; set pin AL2 to clear pin BB2 and pin AN2 AND-NOR OUTPUTS and set TAPE BUS 2 OUTPUT and TAPE BUS 3 OUTPUT test 144: 1 0 0 11 test 145: 0 1 1 00 comment: ; set pin AP1 to clear pin BB2 and pin AN2 AND-NOR OUTPUTS and set TAPE BUS 2 OUTPUT and TAPE BUS 3 OUTPUT test 146: 1 0 0 11 test 147: 0 1 1 00 comment: ; set pin AS2 to clear pin BB2 and pin AN2 AND-NOR OUTPUTS and set TAPE BUS 2 OUTPUT and TAPE BUS 3 OUTPUT test 148: 1 0 0 11 test 149: 0 1 1 00 comment: ; set pin AL1 to clear pin BB2 and pin AN2 AND-NOR OUTPUTS and set TAPE BUS 2 OUTPUT and TAPE BUS 3 OUTPUT test 150: 1 0 0 11 test 151: 0 1 1 00 comment: ; set pin AL1 to clear pin BB2 and pin AN2 AND-NOR OUTPUTS and set TAPE BUS 2 OUTPUT and TAPE BUS 3 OUTPUT test 152: 1 0 0 11 test 153: 0 1 1 00 comment: ; set pin AE2 to clear pin BB2 and pin AN2 AND-NOR OUTPUTS and set TAPE BUS 2 OUTPUT and TAPE BUS 3 OUTPUT test 154: 1 0 0 11 test 155: 0 1 1 00 comment: ; set pin AC1 to clear pin BB2 and set TAPE BUS 3 OUTPUT test 156: 1 0 1 test 157: 0 1 0 comment: ; set pin AF1 to clear pin BB2 and set TAPE BUS 3 OUTPUT test 158: 1 0 1 test 159: 0 1 0 comment: ; set pin AR2 to clear pin AN2 AND-NOR OUTPUTS and set TAPE BUS 2 OUTPUT test 160: 1 0 1 test 161: 0 1 0 comment: ; set pin AP2 to clear pin AN2 AND-NOR OUTPUTS and set TAPE BUS 2 OUTPUT test 162: 1 0 1 test 163: 0 1 0 comment: comment: ; set pin BK1 to clear pin BB1 and pin BN1 AND-NOR OUTPUTS and set TAPE BUS 2 OUTPUT and TAPE BUS 3 OUTPUT test 164: 1 00 11 test 165: 0 11 00 comment: ; set pin BL1 to clear pin BB1 and pin BN1 AND-NOR OUTPUTS and set TAPE BUS 2 OUTPUT and TAPE BUS 3 OUTPUT test 166: 1 00 11 test 167: 0 11 00 comment: ; set pin BF1 to clear pin BB1 and pin BN1 AND-NOR OUTPUTS and set TAPE BUS 2 OUTPUT and TAPE BUS 3 OUTPUT test 168: 1 00 11 test 169: 0 11 00 comment: ; set pin BS1 to clear pin BB1 and pin BN1 AND-NOR OUTPUTS and set TAPE BUS 2 OUTPUT and TAPE BUS 3 OUTPUT test 170: 1 00 11 test 171: 0 11 00 comment: ; set pin BL2 to clear pin BB1 and pin BN1 AND-NOR OUTPUTS and set TAPE BUS 2 OUTPUT and TAPE BUS 3 OUTPUT test 172: 1 00 11 test 173: 0 11 00 comment: ; set pin BU1 to clear pin BB1 and pin BN1 AND-NOR OUTPUTS and set TAPE BUS 2 OUTPUT and TAPE BUS 3 OUTPUT test 174: 1 00 11 test 175: 0 11 00 comment: ; set pin BM2 to clear pin BB1 and TAPE BUS 3 OUTPUT test 176: 1 0 1 test 177: 0 1 0 comment: ; no change test 178: 100000000000000000000000000000000001111100011011011010100110110111 comment: comment: comment: ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; comment: ; test shifting the RWB comment: ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; comment: comment: ; shift in 0, expect 10 test 179: 0 test 180: 110 test 181: 0 comment: ; toggle phase should toggle RWB 2 test 182: 0 0 test 183: 1 1 comment: comment: ; shift in 0, expect 00 test 184: 0 test 185: 100 test 186: 0 comment: ; toggle phase should toggle RWB 2 test 187: 0 1 test 188: 1 0 comment: comment: ; shift in 0, expect 00 test 189: 0 test 190: 100 test 191: 0 comment: ; shift in 1, expect 01 test 192: 1 test 193: 101 test 194: 0 comment: ; shift in 1, expect 11 test 195: 1 test 196: 111 test 197: 0 comment: ; shift in 1, expect 11 test 198: 1 test 199: 111 test 200: 0 comment: ; shift in 0, expect 10 test 201: 0 test 202: 110 test 203: 0 comment: ; shift in 1, expect 01 test 204: 1 test 205: 101 test 206: 0 comment: ; shift in 0, expect 10 test 207: 0 test 208: 110 test 209: 0 comment: ; shift in 1, expect 01 test 210: 1 test 211: 101 test 212: 0 comment: ; shift in 1, expect 11 test 213: 1 test 214: 111 test 215: 0 comment: ; no change test 216: 100000000000000000000000000000000001111100011011011010100110110111 comment: comment: ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; comment: ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; comment: ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; comment: ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; comment: ; needs work (more adder tests, more register tests) comment: ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; comment: ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; comment: ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; comment: ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; end: END summary column 1: offset 2, mask 0x2000 column 2: offset 1, mask 0x0002 column 3: offset 1, mask 0x0800 column 4: offset 1, mask 0x0040 column 5: offset 1, mask 0x4000 column 6: offset 0, mask 0x0004 column 7: offset 1, mask 0x2000 column 8: offset 0, mask 0x0010 column 9: offset 0, mask 0x0008 column 10: offset 0, mask 0x0800 column 11: offset 1, mask 0x0004 column 12: offset 0, mask 0x2000 column 13: offset 0, mask 0x0040 column 14: offset 0, mask 0x0400 column 15: offset 1, mask 0x0020 column 16: offset 1, mask 0x0200 column 17: offset 1, mask 0x0010 column 18: offset 3, mask 0x2000 column 19: offset 3, mask 0x1000 column 20: offset 2, mask 0x0200 column 21: offset 3, mask 0x0800 column 22: offset 2, mask 0x0100 column 23: offset 3, mask 0x8000 column 24: offset 3, mask 0x0100 column 25: offset 4, mask 0x8000 column 26: offset 2, mask 0x0800 column 27: offset 3, mask 0x0002 column 28: offset 3, mask 0x0008 column 29: offset 3, mask 0x4000 column 30: offset 3, mask 0x0004 column 31: offset 4, mask 0x2000 column 32: offset 3, mask 0x0001 column 33: offset 3, mask 0x0040 column 34: offset 3, mask 0x0020 column 35: offset 3, mask 0x0010 column 36: offset 2, mask 0x0008 column 37: offset 2, mask 0x1000 column 38: offset 3, mask 0x0400 column 39: offset 1, mask 0x0008 column 40: offset 2, mask 0x0002 column 41: offset 4, mask 0x0008 column 42: offset 3, mask 0x0080 column 43: offset 1, mask 0x8000 column 44: offset 1, mask 0x0400 column 45: offset 0, mask 0x0200 column 46: offset 2, mask 0x0001 column 47: offset 1, mask 0x0080 column 48: offset 0, mask 0x1000 column 49: offset 0, mask 0x0100 column 50: offset 2, mask 0x8000 column 51: offset 1, mask 0x0001 column 52: offset 0, mask 0x8000 column 53: offset 1, mask 0x1000 column 54: offset 0, mask 0x0001 column 55: offset 0, mask 0x0002 column 56: offset 0, mask 0x4000 column 57: offset 4, mask 0x0002 column 58: offset 3, mask 0x0200 column 59: offset 2, mask 0x0400 column 60: offset 2, mask 0x0080 column 61: offset 4, mask 0x0001 column 62: offset 2, mask 0x4000 column 63: offset 2, mask 0x0040 column 64: offset 4, mask 0x1000 column 65: offset 2, mask 0x0020 column 66: offset 4, mask 0x0004 direction bits (1=input) 0x52A3 0x1589 0x943A 0x0680 0x50FC pullup bits (1=pullup) 0x0000 0x0000 0x0000 0x0000 0x0000 test step out_data dont care 1: 0x0000 0x0008 0x700A 0x0400 0x0005 0x5203 0x1481 0x8420 0x0200 0x1000 2: 0x0000 0x8008 0x700A 0x0400 0x0005 0x5003 0x1081 0x8420 0x0200 0x1000 3: 0x0000 0x0008 0x700A 0x0400 0x0005 0x5003 0x1081 0x8420 0x0200 0x1000 4: 0x0000 0x0008 0x700B 0x0400 0x0005 0x4003 0x1001 0x8420 0x0200 0x1000 5: 0x0000 0x0008 0x700A 0x0400 0x0005 0x4003 0x1001 0x8420 0x0200 0x1000 6: 0x0100 0x0008 0x700A 0x0400 0x0005 0x4003 0x1000 0x0420 0x0200 0x1000 7: 0x0000 0x0008 0x700A 0x0400 0x0005 0x4003 0x1000 0x0420 0x0200 0x1000 8: 0xC001 0x0008 0x700A 0x0400 0x0005 0x0000 0x0000 0x0420 0x0200 0x1000 9: 0x4001 0x0008 0x700A 0x0400 0x0005 0x0000 0x0000 0x0420 0x0200 0x1000 10: 0x4001 0x0008 0x700A 0x0400 0x0007 0x0000 0x0000 0x0020 0x0000 0x1000 11: 0x4001 0x0008 0x700A 0x0400 0x0005 0x0000 0x0000 0x0020 0x0000 0x1000 12: 0x4001 0x0008 0x708A 0x0400 0x0005 13: 0x4001 0x0008 0x700A 0x0400 0x0005 14: 0x4001 0x0008 0x700A 0x0400 0x0005 15: 0x4401 0x0008 0x7002 0x0480 0x0005 16: 0x4401 0x0010 0x7002 0x0480 0x000D 17: 0x4601 0x8410 0x7002 0x0480 0x000D 18: 0x4601 0x0410 0x7002 0x0480 0x000D 19: 0x5601 0x0490 0x7003 0x0480 0x000D 20: 0x5601 0x0490 0x7002 0x0480 0x000D 21: 0x5701 0x0491 0xF002 0x0480 0x000D 22: 0x5601 0x0491 0xF002 0x0480 0x000D 23: 0x9602 0x1491 0xF002 0x0480 0x000D 24: 0x1602 0x1491 0xF002 0x0480 0x000D 25: 0x1602 0x1491 0xF402 0x0680 0x000F 26: 0x1602 0x1491 0xF402 0x0680 0x000D 27: 0x1602 0x1491 0xF4A2 0x0680 0x100D 28: 0x1602 0x1491 0xF422 0x0680 0x100D 29: 0x1202 0x1491 0xF42A 0x0600 0x100D 30: 0x1202 0x1489 0xF42A 0x0600 0x1005 31: 0x1202 0x1489 0xF42A 0x0600 0x1005 32: 0x1202 0x1489 0xF42A 0x0600 0x1005 33: 0x1602 0x1489 0xF422 0x0680 0x1005 34: 0x1602 0x9089 0xF422 0x0680 0x1005 35: 0x1602 0x1089 0xF422 0x0680 0x1005 36: 0x1602 0x1091 0xF422 0x0680 0x100D 37: 0x1602 0x9491 0xF422 0x0680 0x100D 38: 0x1602 0x1491 0xF422 0x0680 0x100D 39: 0x1602 0x1491 0xF422 0x0680 0x100D 40: 0x1202 0x1491 0xF42A 0x0600 0x100D 41: 0x1002 0x9491 0xF42A 0x0600 0x100D 42: 0x1002 0x1491 0xF42A 0x0600 0x100D 43: 0x1402 0x1491 0xF422 0x0680 0x100D 44: 0x1602 0x9491 0xF422 0x0680 0x100D 45: 0x1602 0x1491 0xF422 0x0680 0x100D 46: 0x1602 0x1489 0xF422 0x0680 0x1005 47: 0x1602 0x1489 0xF422 0x0680 0x1005 48: 0x1602 0x1409 0xF423 0x0680 0x1005 49: 0x1602 0x1409 0xF422 0x0680 0x1005 50: 0x1602 0x1411 0xF422 0x0680 0x100D 51: 0x1602 0x1491 0xF423 0x0680 0x100D 52: 0x1602 0x1491 0xF422 0x0680 0x100D 53: 0x1602 0x1491 0xF422 0x0680 0x100D 54: 0x1202 0x1491 0xF42A 0x0600 0x100D 55: 0x0202 0x1491 0xF42B 0x0600 0x100D 56: 0x0202 0x1491 0xF42A 0x0600 0x100D 57: 0x0602 0x1491 0xF422 0x0680 0x100D 58: 0x1602 0x1491 0xF423 0x0680 0x100D 59: 0x1602 0x1491 0xF422 0x0680 0x100D 60: 0x1602 0x1489 0xF422 0x0680 0x1005 61: 0x1602 0x1489 0xF422 0x0680 0x1005 62: 0x1702 0x1489 0x7422 0x0680 0x1005 63: 0x1602 0x1489 0x7422 0x0680 0x1005 64: 0x1602 0x1491 0x7422 0x0680 0x100D 65: 0x1702 0x1491 0xF422 0x0680 0x100D 66: 0x1602 0x1491 0xF422 0x0680 0x100D 67: 0x1602 0x1491 0xF422 0x0680 0x100D 68: 0x1202 0x1491 0xF42A 0x0600 0x100D 69: 0x1302 0x1490 0xF42A 0x0600 0x100D 70: 0x1202 0x1490 0xF42A 0x0600 0x100D 71: 0x1602 0x1490 0xF422 0x0680 0x100D 72: 0x1702 0x1491 0xF422 0x0680 0x100D 73: 0x1602 0x1491 0xF422 0x0680 0x100D 74: 0x1602 0x1489 0xF422 0x0680 0x1005 75: 0x1602 0x1489 0xF422 0x0680 0x1005 76: 0x9603 0x0489 0xF422 0x0680 0x1005 77: 0x1603 0x0489 0xF422 0x0680 0x1005 78: 0x1603 0x0491 0xF422 0x0680 0x100D 79: 0x9602 0x1491 0xF422 0x0680 0x100D 80: 0x1602 0x1491 0xF422 0x0680 0x100D 81: 0x1602 0x1491 0xF422 0x0680 0x100D 82: 0x1202 0x1491 0xF42A 0x0600 0x100D 83: 0xD200 0x1491 0xF42A 0x0600 0x100D 84: 0x5200 0x1491 0xF42A 0x0600 0x100D 85: 0x5600 0x1491 0xF422 0x0680 0x100D 86: 0x9602 0x1491 0xF422 0x0680 0x100D 87: 0x1602 0x1491 0xF422 0x0680 0x100D 88: 0x1602 0x1489 0xF422 0x0680 0x1005 89: 0x1602 0x1489 0xF422 0x0680 0x1005 90: 0x1602 0x1489 0xF422 0x0480 0x1007 91: 0x1602 0x1489 0xF422 0x0480 0x1005 92: 0x1602 0x1491 0xF422 0x0480 0x100D 93: 0x1602 0x1491 0xF422 0x0680 0x100F 94: 0x1602 0x1491 0xF422 0x0680 0x100D 95: 0x1602 0x1491 0xF422 0x0680 0x100D 96: 0x1202 0x1491 0xF42A 0x0600 0x100D 97: 0x1202 0x1491 0xF02A 0x0600 0x100F 98: 0x1202 0x1491 0xF02A 0x0600 0x100D 99: 0x1602 0x1491 0xF022 0x0680 0x100D 100: 0x1602 0x1491 0xF422 0x0680 0x100F 101: 0x1602 0x1491 0xF422 0x0680 0x100D 102: 0x1602 0x1489 0xF422 0x0680 0x1005 103: 0x1602 0x1489 0xF422 0x0680 0x1005 104: 0x1602 0x1489 0xF422 0x0480 0x1007 105: 0x1602 0x1489 0xF422 0x0480 0x1005 106: 0x1602 0x1489 0xF4A2 0x0480 0x0005 107: 0x1602 0x1489 0xF422 0x0480 0x0005 108: 0x1602 0x1491 0xF422 0x0480 0x000D 109: 0x1602 0x1491 0xF422 0x0680 0x000F 110: 0x1602 0x1491 0xF422 0x0680 0x000D 111: 0x1602 0x1491 0xF4A2 0x0680 0x100D 112: 0x1602 0x1491 0xF422 0x0680 0x100D 113: 0x1602 0x1491 0xF422 0x0680 0x100D 114: 0x1202 0x1491 0xF42A 0x0600 0x100D 115: 0x1202 0x1491 0xF02A 0x0600 0x100F 116: 0x1202 0x1491 0xF02A 0x0600 0x100D 117: 0x1202 0x1491 0xF08A 0x0600 0x100D 118: 0x1202 0x1491 0xF00A 0x0600 0x100D 119: 0x1602 0x1491 0xF002 0x0680 0x100D 120: 0x1602 0x1491 0xF402 0x0680 0x100F 121: 0x1602 0x1491 0xF402 0x0680 0x100D 122: 0x1602 0x1491 0xF4A2 0x0680 0x100D 123: 0x1602 0x1491 0xF422 0x0680 0x100D 124: 0x1202 0x1491 0xF42A 0x0600 0x100D 125: 0x1202 0x1489 0xF42A 0x0600 0x1005 126: 0x1202 0x1489 0xF42A 0x0600 0x1005 127: 0x1206 0x1489 0xF42A 0x0600 0x1005 128: 0x1206 0x3489 0xF42A 0x0600 0x1005 129: 0x1A06 0x3489 0xF42A 0x0600 0x1005 130: 0x1A06 0x348D 0xF42A 0x0600 0x1005 131: 0x1A46 0x348D 0xF42A 0x0600 0x1005 132: 0x1A46 0x368D 0xF42A 0x0600 0x1005 133: 0x1A46 0x368D 0xF62A 0x0600 0x1005 134: 0x1A46 0x368D 0xF62A 0x0E00 0x1005 135: 0x1A46 0x368D 0xF62A 0x8E00 0x1005 136: 0x1A46 0x368D 0xF62A 0x8F00 0x1005 137: 0x1A46 0x368D 0xFE2A 0x8F00 0x1005 138: 0x1A46 0x368D 0xFE2A 0x8F02 0x1005 139: 0x1A46 0x368D 0xFE2A 0xCF02 0x1005 140: 0x1A46 0x368D 0xFE2A 0xCF06 0x1005 141: 0x1A46 0x368D 0xFE2A 0xCF07 0x1005 142: 0x1A46 0x368D 0xFE2A 0xCF47 0x1005 143: 0x1A46 0x368D 0xFE2A 0xCF67 0x1005 144: 0x1A46 0x3687 0xFE22 0xCFE7 0x100D 145: 0x1A46 0x368D 0xFE2A 0xCF67 0x1005 146: 0x1A46 0x3E85 0xFE22 0xCFE7 0x100D 147: 0x1A46 0x368D 0xFE2A 0xCF67 0x1005 148: 0x1A46 0x36C5 0xFE22 0xCFE7 0x100D 149: 0x1A46 0x368D 0xFE2A 0xCF67 0x1005 150: 0x1A46 0x7685 0xFE22 0xCFE7 0x100D 151: 0x1A46 0x368D 0xFE2A 0xCF67 0x1005 152: 0x1A56 0x3685 0xFE22 0xCFE7 0x100D 153: 0x1A46 0x368D 0xFE2A 0xCF67 0x1005 154: 0x1A4E 0x3685 0xFE22 0xCFE7 0x100D 155: 0x1A46 0x368D 0xFE2A 0xCF67 0x1005 156: 0x3A46 0x368D 0xFE22 0xCFE7 0x1005 157: 0x1A46 0x368D 0xFE2A 0xCF67 0x1005 158: 0x1E46 0x368D 0xFE22 0xCFE7 0x1005 159: 0x1A46 0x368D 0xFE2A 0xCF67 0x1005 160: 0x1A46 0x36A5 0xFE2A 0xCF67 0x100D 161: 0x1A46 0x368D 0xFE2A 0xCF67 0x1005 162: 0x1A46 0x3695 0xFE2A 0xCF67 0x100D 163: 0x1A46 0x368D 0xFE2A 0xCF67 0x1005 164: 0x1A46 0x368D 0xEE2A 0xEBE7 0x100D 165: 0x1A46 0x368D 0xFE2A 0xCF67 0x1005 166: 0x1A46 0x368D 0xEE2A 0xDBE7 0x100D 167: 0x1A46 0x368D 0xFE2A 0xCF67 0x1005 168: 0x1A46 0x368D 0xEF2A 0xCBE7 0x100D 169: 0x1A46 0x368D 0xFE2A 0xCF67 0x1005 170: 0x1A46 0x368D 0xEE2A 0xCBE7 0x900D 171: 0x1A46 0x368D 0xFE2A 0xCF67 0x1005 172: 0x1A46 0x368D 0xEE2A 0xCBEF 0x100D 173: 0x1A46 0x368D 0xFE2A 0xCF67 0x1005 174: 0x1A46 0x368D 0xEE2A 0xCBE7 0x300D 175: 0x1A46 0x368D 0xFE2A 0xCF67 0x1005 176: 0x1A46 0x368D 0xFE2A 0xCB77 0x100D 177: 0x1A46 0x368D 0xFE2A 0xCF67 0x1005 178: 0x1202 0x1489 0xF42A 0x0600 0x1005 179: 0x1202 0x1489 0xB42A 0x0600 0x1005 180: 0x1202 0x1489 0xB44A 0x0600 0x1005 181: 0x1202 0x1489 0xB40A 0x0600 0x1005 182: 0x1202 0x1489 0xB40A 0x0600 0x0004 183: 0x1202 0x1489 0xB40A 0x0600 0x1005 184: 0x1202 0x1489 0xB40A 0x0600 0x1005 185: 0x1202 0x1489 0xB44A 0x0600 0x0005 186: 0x1202 0x1489 0xB40A 0x0600 0x0005 187: 0x1202 0x1489 0xB40A 0x0600 0x1004 188: 0x1202 0x1489 0xB40A 0x0600 0x0005 189: 0x1202 0x1489 0xB40A 0x0600 0x0005 190: 0x1202 0x1489 0xB44A 0x0600 0x0005 191: 0x1202 0x1489 0xB40A 0x0600 0x0005 192: 0x1202 0x1489 0xF40A 0x0600 0x0005 193: 0x1202 0x1489 0xF46A 0x0600 0x0005 194: 0x1202 0x1489 0xF42A 0x0600 0x0005 195: 0x1202 0x1489 0xF42A 0x0600 0x0005 196: 0x1202 0x1489 0xF46A 0x0600 0x1005 197: 0x1202 0x1489 0xF42A 0x0600 0x1005 198: 0x1202 0x1489 0xF42A 0x0600 0x1005 199: 0x1202 0x1489 0xF46A 0x0600 0x1005 200: 0x1202 0x1489 0xF42A 0x0600 0x1005 201: 0x1202 0x1489 0xB42A 0x0600 0x1005 202: 0x1202 0x1489 0xB44A 0x0600 0x1005 203: 0x1202 0x1489 0xB40A 0x0600 0x1005 204: 0x1202 0x1489 0xF40A 0x0600 0x1005 205: 0x1202 0x1489 0xF46A 0x0600 0x0005 206: 0x1202 0x1489 0xF42A 0x0600 0x0005 207: 0x1202 0x1489 0xB42A 0x0600 0x0005 208: 0x1202 0x1489 0xB44A 0x0600 0x1005 209: 0x1202 0x1489 0xB40A 0x0600 0x1005 210: 0x1202 0x1489 0xF40A 0x0600 0x1005 211: 0x1202 0x1489 0xF46A 0x0600 0x0005 212: 0x1202 0x1489 0xF42A 0x0600 0x0005 213: 0x1202 0x1489 0xF42A 0x0600 0x0005 214: 0x1202 0x1489 0xF46A 0x0600 0x1005 215: 0x1202 0x1489 0xF42A 0x0600 0x1005 216: 0x1202 0x1489 0xF42A 0x0600 0x1005 PINs used (in edge connector order) (G=ground,P=power) SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBB LETTER ABCDEFHJKLMNPRSTUVABCDEFHJKLMNPRSTUVABCDEFHJKLMNPRSTUVABCDEFHJKLMNPRSTUV SIDE 111111111111111111222222222222222222111111111111111111222222222222222222 USAGE IOIOIIOIIIIOIOIGOIPIGIIIOOOIIOIIIOIOIOIOIIIIIIIOOIIGIOPOGOIIIIIIIIIOIIOO UUT has 44 inputs UUT has 22 outputs contains 66 pins/columns 0 pins are not used contains 216 'test steps' M222 PCB REV B SCHEMATIC REV A LINC TAPE REGISTERS TERMINOLOGY- SIGNALS REFER TO PDP12 MAINT VOL4 M222 SCHEMATIC. BUT... DEC USES AND-NOR GATES TO ROUTE THE ADDER A AND B INPUTS, SO... DEC RENAMED THE ADDER TO NEGATIVE LOGIC TERMS (I.E. A-N + B-N + C-N -> SUM-N, C1-N). (NOT THE 7482 DATASHEET NAMES OF A + B + C -> SUM, C1). SO, WITH ALL 'AND ENABLES' LOW, THE AND-NOR OUTPUTS = HIGH. WITH C-L HIGH, THE ADDER OUTPUT IS SUM-N=1, C1-N=1; THE INVERTED ADDER OUTPUT IS LOW (TAPE BUS). AND THERE IS NO CARRY (C1-N IS HI). THE TWO ADDERS, TWO REGISTER BITS, ETC ARE LABELED BIT 2 (EVEN, MSB) AND BIT 3 (ODD, LSB). THE ADDERS ARE REFERRED TO AS 'ADDER2' (MSB) AND 'ADDER3' (LSB). POWER PINS: AA2 +5V AT1 GROUND AC2 GROUND BA2 +5V BT1 GROUND BC2 GROUND (ALL PINS ARE USED). PINS Main menu Thu Aug 20 18:57:49 2015 test file is: tests\m222.new delay is: 0 trigger is: 1 1 read test file 2 set test delay 3 set test trigger 4 run test 5 output loading test 8 diags 9 exit UUT power is okay Thu Aug 20 18:57:52 2015 space single step O run once (one test, all steps) F run, stop on fail G go (run tests N run, stop on fail, no print S scope (run, no print) C toggle comment printout + increase speed (less delay) - decrease speed (more delay)(slower) Q quit test comment_flag is 1 space single step O run once (one test, all steps) F run, stop on fail G go (run tests N run, stop on fail, no print S scope (run, no print) C toggle comment printout + increase speed (less delay) - decrease speed (more delay)(slower) Q quit test scope (run, no print) pppppppppppppppppppp space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C toggle comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit source: ; load TMA SETUP from tape bus (10) source: 110 changed: 1 0 step 41 100000000000000010000000000000000001110110110011011010100110110111 source: 0 changed: 0 step 42 100000000000000010000000000000000001110110010011011010100110110111 source: ; restore TMA SETUP 3 source: ; set pin AF1 which clears pin BB2 and sets pin BR2 TAPE BUS 3 OUTPUT source: 1 0 1 changed: 1 0 1 step 43 100000000000010010000000000000000000110111010011011010100110110111 source: ; load TMA SETUP from tape bus (11) source: 111 changed: 1 1 step 44 100000000000010010000000000000000000110111111011011010100110110111 source: 0 changed: 0 step 45 100000000000010010000000000000000000110111011011011010100110110111 source: source: source: ; walk a 0, TMA 2 source: source: source: ; clear pin AP2 which sets pin AN2 and clears pin BV2 TAPE BUS 2 OUTPUT source: 0 1 0 changed: 0 1 0 step 46 100000000000010000000000000000000000111101011011011010100110110111 source: ; set pin AF1 which clears pin BB2 and sets pin BR2 TAPE BUS 3 OUTPUT source: 1 0 1 changed: step 47 100000000000010000000000000000000000111101011011011010100110110111 source: ; load TMA from tape bus (01) source: 101 changed: 10 step 48 100000000000010000000000000000000000111101011101011010100110110111 source: 0 changed: 0 step 49 100000000000010000000000000000000000111101011001011010100110110111 source: ; restore TMA 2 source: ; set pin AP2 which clears pin AN2 and sets pin BV2 TAPE BUS 2 OUTPUT source: 1 0 1 changed: 1 0 1 step 50 100000000000010010000000000000000000110111011001011010100110110111 source: ; load TMA from tape bus (11) source: 111 changed: 11 step 51 100000000000010010000000000000000000110111011111011010100110110111 source: 0 changed: 0 step 52 100000000000010010000000000000000000110111011011011010100110110111 source: source: source: ; walk a 0, TMA 3 source: source: source: ; set pin AP2 which clears pin AN2 and sets pin BV2 TAPE BUS 2 OUTPUT source: 1 0 1 changed: step 53 100000000000010010000000000000000000110111011011011010100110110111 source: ; clear pin AF1 which sets pin BB2 and clears pin BR2 TAPE BUS 3 OUTPUT source: 0 1 0 changed: 0 1 0 step 54 100000000000000010000000000000000001110110011011011010100110110111 source: ; load TMA from tape bus (10) source: 110 changed: 1 0 step 55 100000000000000010000000000000000001110110011110011010100110110111 source: 0 changed: 0 step 56 100000000000000010000000000000000001110110011010011010100110110111 source: ; restore TMA 3 source: ; set pin AF1 which clears pin BB2 and sets pin BR2 TAPE BUS 3 OUTPUT source: 1 0 1 changed: 1 0 1 step 57 100000000000010010000000000000000000110111011010011010100110110111 source: ; load TMA from tape bus (11) source: 111 changed: 1 1 step 58 100000000000010010000000000000000000110111011111011010100110110111 source: 0 changed: 0 step 59 100000000000010010000000000000000000110111011011011010100110110111 source: source: source: ; walk a 0, TBN 2 source: source: source: ; clear pin AP2 which sets pin AN2 and clears pin BV2 TAPE BUS 2 OUTPUT source: 0 1 0 changed: 0 1 0 step 60 100000000000010000000000000000000000111101011011011010100110110111 source: ; set pin AF1 which clears pin BB2 and sets pin BR2 TAPE BUS 3 OUTPUT source: 1 0 1 changed: step 61 100000000000010000000000000000000000111101011011011010100110110111 source: ; load TBN from tape bus (01) source: 101 changed: 10 step 62 100000000000010000000000000000000000111101011011101010100110110111 source: 0 changed: 0 step 63 100000000000010000000000000000000000111101011011001010100110110111 source: ; restore TBN 2 source: ; set pin AP2 which clears pin AN2 and sets pin BV2 TAPE BUS 2 OUTPUT source: 1 0 1 changed: 1 0 1 step 64 100000000000010010000000000000000000110111011011001010100110110111 source: ; load TBN from tape bus (11) source: 111 changed: 11 step 65 100000000000010010000000000000000000110111011011111010100110110111 source: 0 changed: 0 step 66 100000000000010010000000000000000000110111011011011010100110110111 source: source: source: ; walk a 0, TBN 3 source: source: source: ; set pin AP2 which clears pin AN2 and sets pin BV2 TAPE BUS 2 OUTPUT source: 1 0 1 changed: step 67 100000000000010010000000000000000000110111011011011010100110110111 source: ; clear pin AF1 which sets pin BB2 and clears pin BR2 TAPE BUS 3 OUTPUT source: 0 1 0 changed: 0 1 0 step 68 100000000000000010000000000000000001110110011011011010100110110111 source: ; load TBN from tape bus (10) source: 110 changed: 1 0 step 69 100000000000000010000000000000000001110110011011110010100110110111 source: 0 changed: 0 step 70 100000000000000010000000000000000001110110011011010010100110110111 source: ; restore TBN 3 source: ; set pin AF1 which clears pin BB2 and sets pin BR2 TAPE BUS 3 OUTPUT source: 1 0 1 changed: 1 0 1 step 71 100000000000010010000000000000000000110111011011010010100110110111 source: ; load TBN from tape bus (11) source: 111 changed: 1 1 step 72 100000000000010010000000000000000000110111011011111010100110110111 source: 0 changed: 0 step 73 100000000000010010000000000000000000110111011011011010100110110111 source: source: source: ; walk a 0, TAC 2 source: source: source: ; clear pin AP2 which sets pin AN2 and clears pin BV2 TAPE BUS 2 OUTPUT source: 0 1 0 changed: 0 1 0 step 74 100000000000010000000000000000000000111101011011011010100110110111 source: ; set pin AF1 which clears pin BB2 and sets pin BR2 TAPE BUS 3 OUTPUT source: 1 0 1 changed: step 75 100000000000010000000000000000000000111101011011011010100110110111 source: ; load TAC from tape bus (01) source: 10110 changed: 101 step 76 100000000000010000000000000000000000111101011011011101100110110111 source: 0 changed: 0 step 77 100000000000010000000000000000000000111101011011011001100110110111 source: ; restore TAC 2 source: ; set pin AP2 which clears pin AN2 and sets pin BV2 TAPE BUS 2 OUTPUT source: 1 0 1 changed: 1 0 1 step 78 100000000000010010000000000000000000110111011011011001100110110111 source: ; load TAC from tape bus (11) source: 11010 changed: 110 step 79 100000000000010010000000000000000000110111011011011110100110110111 source: 0 changed: 0 step 80 100000000000010010000000000000000000110111011011011010100110110111 source: source: source: ; walk a 0, TAC 3 source: source: source: ; set pin AP2 which clears pin AN2 and sets pin BV2 TAPE BUS 2 OUTPUT source: 1 0 1 changed: step 81 100000000000010010000000000000000000110111011011011010100110110111 source: ; clear pin AF1 which sets pin BB2 and clears pin BR2 TAPE BUS 3 OUTPUT source: 0 1 0 changed: 0 1 0 step 82 100000000000000010000000000000000001110110011011011010100110110111 source: ; load TAC from tape bus (10) source: 11001 changed: 1 01 step 83 100000000000000010000000000000000001110110011011011110010110110111 source: 0 changed: 0 step 84 100000000000000010000000000000000001110110011011011010010110110111 source: ; restore TAC 3 source: ; set pin AF1 which clears pin BB2 and sets pin BR2 TAPE BUS 3 OUTPUT source: 1 0 1 changed: 1 0 1 step 85 100000000000010010000000000000000000110111011011011010010110110111 source: ; load TAC from tape bus (11) source: 11010 changed: 1 10 step 86 100000000000010010000000000000000000110111011011011110100110110111 source: 0 changed: 0 step 87 100000000000010010000000000000000000110111011011011010100110110111 source: source: source: ; walk a 0, TB 2 source: source: source: ; clear pin AP2 which sets pin AN2 and clears pin BV2 TAPE BUS 2 OUTPUT source: 0 1 0 changed: 0 1 0 step 88 100000000000010000000000000000000000111101011011011010100110110111 source: ; set pin AF1 which clears pin BB2 and sets pin BR2 TAPE BUS 3 OUTPUT source: 1 0 1 changed: step 89 100000000000010000000000000000000000111101011011011010100110110111 source: ; load TB from tape bus (01) source: 101 changed: 10 step 90 100000000000010000000000000000000000111101011011011010101010110111 source: 0 changed: 0 step 91 100000000000010000000000000000000000111101011011011010100010110111 source: ; restore TB 2 source: ; set pin AP2 which clears pin AN2 and sets pin BV2 TAPE BUS 2 OUTPUT source: 1 0 1 changed: 1 0 1 step 92 100000000000010010000000000000000000110111011011011010100010110111 source: ; load TB from tape bus (11) source: 111 changed: 11 step 93 100000000000010010000000000000000000110111011011011010101110110111 source: 0 changed: 0 step 94 100000000000010010000000000000000000110111011011011010100110110111 source: source: source: ; walk a 0, TB 3 source: source: source: ; set pin AP2 which clears pin AN2 and sets pin BV2 TAPE BUS 2 OUTPUT source: 1 0 1 changed: step 95 100000000000010010000000000000000000110111011011011010100110110111 source: ; clear pin AF1 which sets pin BB2 and clears pin BR2 TAPE BUS 3 OUTPUT source: 0 1 0 changed: 0 1 0 step 96 100000000000000010000000000000000001110110011011011010100110110111 source: ; load TB from tape bus (10) source: 110 changed: 1 0 step 97 100000000000000010000000000000000001110110011011011010101100110111 source: 0 changed: 0 step 98 100000000000000010000000000000000001110110011011011010100100110111 source: ; restore TB 3 source: ; set pin AF1 which clears pin BB2 and sets pin BR2 TAPE BUS 3 OUTPUT source: 1 0 1 changed: 1 0 1 step 99 100000000000010010000000000000000000110111011011011010100100110111 source: ; load TB from tape bus (11) source: 111 changed: 1 1 step 100 100000000000010010000000000000000000110111011011011010101110110111 source: 0 changed: 0 step 101 100000000000010010000000000000000000110111011011011010100110110111 source: source: source: ; walk a 0, RWB 2 source: source: source: ; clear pin AP2 which sets pin AN2 and clears pin BV2 TAPE BUS 2 OUTPUT source: 0 1 0 changed: 0 1 0 step 102 100000000000010000000000000000000000111101011011011010100110110111 source: ; set pin AF1 which clears pin BB2 and sets pin BR2 TAPE BUS 3 OUTPUT source: 1 0 1 changed: step 103 100000000000010000000000000000000000111101011011011010100110110111 source: ; load TB from tape bus (01) source: 101 changed: 10 step 104 100000000000010000000000000000000000111101011011011010101010110111 source: 0 changed: 0 step 105 100000000000010000000000000000000000111101011011011010100010110111 source: ; load RWB from TB (JAMS CLEAR AND PRESET) source: 1 01 changed: 1 0 step 106 100000000000010000000000000000000000111101011011011010100011110011 source: 0 changed: 0 step 107 100000000000010000000000000000000000111101011011011010100010110011 source: ; restore TB 2 and RWB 2 source: ; set pin AP2 which clears pin AN2 and sets pin BV2 TAPE BUS 2 OUTPUT source: 1 0 1 changed: 1 0 1 step 108 100000000000010010000000000000000000110111011011011010100010110011 source: ; load TB from tape bus (11) source: 111 changed: 11 step 109 100000000000010010000000000000000000110111011011011010101110110011 source: 0 changed: 0 step 110 100000000000010010000000000000000000110111011011011010100110110011 source: ; load RWB from TB (JAMS CLEAR AND PRESET) source: 1 11 changed: 1 1 step 111 100000000000010010000000000000000000110111011011011010100111110111 source: 0 changed: 0 step 112 100000000000010010000000000000000000110111011011011010100110110111 source: source: source: ; walk a 0, RWB 3 source: source: source: ; set pin AP2 which clears pin AN2 and sets pin BV2 TAPE BUS 2 OUTPUT source: 1 0 1 changed: step 113 100000000000010010000000000000000000110111011011011010100110110111 source: ; clear pin AF1 which sets pin BB2 and clears pin BR2 TAPE BUS 3 OUTPUT source: 0 1 0 changed: 0 1 0 step 114 100000000000000010000000000000000001110110011011011010100110110111 source: ; load TB from tape bus (10) source: 110 changed: 1 0 step 115 100000000000000010000000000000000001110110011011011010101100110111 source: 0 changed: 0 step 116 100000000000000010000000000000000001110110011011011010100100110111 source: ; load RWB from TB (JAMS CLEAR AND PRESET) source: 1 10 changed: 1 0 step 117 100000000000000010000000000000000001110110011011011010100101110101 source: 0 changed: 0 step 118 100000000000000010000000000000000001110110011011011010100100110101 source: ; restore TB 3 and RWB 3 source: ; set pin AF1 which clears pin BB2 and sets pin BR2 TAPE BUS 3 OUTPUT source: 1 0 1 changed: 1 0 1 step 119 100000000000010010000000000000000000110111011011011010100100110101 source: ; load TB from tape bus (11) source: 111 changed: 1 1 step 120 100000000000010010000000000000000000110111011011011010101110110101 source: 0 changed: 0 step 121 100000000000010010000000000000000000110111011011011010100110110101 source: ; load RWB from TB (JAMS CLEAR AND PRESET) source: 1 11 changed: 1 1 step 122 100000000000010010000000000000000000110111011011011010100111110111 source: 0 changed: 0 step 123 100000000000010010000000000000000000110111011011011010100110110111 source: source: ; clear pin AF1 (AND with itself) to set pin BB2 (AND-NOR output) and clear pin BR2 TAPE BUS 3 OUTPUT source: 0 1 0 changed: 0 1 0 step 124 100000000000000010000000000000000001110110011011011010100110110111 source: ; clear pin AP2 (AND with itself) to set pin AN2 (AND-NOR output) and clear pin BV2 TAPE BUS 2 OUTPUT source: 0 1 0 changed: 0 1 0 step 125 100000000000000000000000000000000001111100011011011010100110110111 source: ; (no change) source: 100000000000000000000000000000000001111100011011011010100110110111 changed: step 126 100000000000000000000000000000000001111100011011011010100110110111 source: source: source: ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; source: ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; source: ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; source: ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; source: ;********************* need to walk a one ********************** source: ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; source: ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; source: ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; source: ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; source: source: ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; source: ; source: ; test AND-NOR logic source: ; source: ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; source: source: ; (all registers are HIGH) source: ; set all pins HIGH except ENABLES source: source: ; set pin AF2 HIGH source: 1 changed: 1 step 127 100001000000000000000000000000000001111100011011011010100110110111 source: ; set pin AM1 HIGH source: 1 changed: 1 step 128 100001100000000000000000000000000001111100011011011010100110110111 source: ; set pin AE1 HIGH source: 1 changed: 1 step 129 100001100100000000000000000000000001111100011011011010100110110111 source: ; set pin AM2 HIGH source: 1 changed: 1 step 130 100001100110000000000000000000000001111100011011011010100110110111 source: ; set pin AB2 HIGH source: 1 changed: 1 step 131 100001100110100000000000000000000001111100011011011010100110110111 source: ; set pin AS1 HIGH source: 1 changed: 1 step 132 100001100110100100000000000000000001111100011011011010100110110111 source: ; set pin BE1 HIGH source: 1 changed: 1 step 133 100001100110100100010000000000000001111100011011011010100110110111 source: ; set pin BM1 HIGH source: 1 changed: 1 step 134 100001100110100100011000000000000001111100011011011010100110110111 source: ; set pin BH1 HIGH source: 1 changed: 1 step 135 100001100110100100011010000000000001111100011011011010100110110111 source: ; set pin BR1 HIGH source: 1 changed: 1 step 136 100001100110100100011011000000000001111100011011011010100110110111 source: ; set pin BC1 HIGH source: 1 changed: 1 step 137 100001100110100100011011010000000001111100011011011010100110110111 source: ; set pin BJ2 HIGH source: 1 changed: 1 step 138 100001100110100100011011011000000001111100011011011010100110110111 source: ; set pin BJ1 HIGH source: 1 changed: 1 step 139 100001100110100100011011011010000001111100011011011010100110110111 source: ; set pin BK2 HIGH source: 1 changed: 1 step 140 100001100110100100011011011011000001111100011011011010100110110111 source: ; set pin BH2 HIGH source: 1 changed: 1 step 141 100001100110100100011011011011010001111100011011011010100110110111 source: ; set pin BP2 HIGH source: 1 changed: 1 step 142 100001100110100100011011011011011001111100011011011010100110110111 source: ; set pin BN2 HIGH source: 1 changed: 1 step 143 100001100110100100011011011011011101111100011011011010100110110111 source: ; toggle each ENABLE source: source: ; set pin AL2 to clear pin BB2 and pin AN2 AND-NOR OUTPUTS and set TAPE BUS 2 OUTPUT and TAPE BUS 3 OUTPUT source: 1 0 0 11 changed: 1 0 0 11 step 144 110001100110100100011011011011011100110111011011011010100110110111 source: 0 1 1 00 changed: 0 1 1 00 step 145 100001100110100100011011011011011101111100011011011010100110110111 source: ; set pin AP1 to clear pin BB2 and pin AN2 AND-NOR OUTPUTS and set TAPE BUS 2 OUTPUT and TAPE BUS 3 OUTPUT source: 1 0 0 11 changed: 1 0 0 11 step 146 101001100110100100011011011011011100110111011011011010100110110111 source: 0 1 1 00 changed: 0 1 1 00 step 147 100001100110100100011011011011011101111100011011011010100110110111 source: ; set pin AS2 to clear pin BB2 and pin AN2 AND-NOR OUTPUTS and set TAPE BUS 2 OUTPUT and TAPE BUS 3 OUTPUT source: 1 0 0 11 changed: 1 0 0 11 step 148 100101100110100100011011011011011100110111011011011010100110110111 source: 0 1 1 00 changed: 0 1 1 00 step 149 100001100110100100011011011011011101111100011011011010100110110111 source: ; set pin AL1 to clear pin BB2 and pin AN2 AND-NOR OUTPUTS and set TAPE BUS 2 OUTPUT and TAPE BUS 3 OUTPUT source: 1 0 0 11 changed: 1 0 0 11 step 150 100011100110100100011011011011011100110111011011011010100110110111 source: 0 1 1 00 changed: 0 1 1 00 step 151 100001100110100100011011011011011101111100011011011010100110110111 source: ; set pin AL1 to clear pin BB2 and pin AN2 AND-NOR OUTPUTS and set TAPE BUS 2 OUTPUT and TAPE BUS 3 OUTPUT source: 1 0 0 11 changed: 1 0 0 11 step 152 100001110110100100011011011011011100110111011011011010100110110111 source: 0 1 1 00 changed: 0 1 1 00 step 153 100001100110100100011011011011011101111100011011011010100110110111 source: ; set pin AE2 to clear pin BB2 and pin AN2 AND-NOR OUTPUTS and set TAPE BUS 2 OUTPUT and TAPE BUS 3 OUTPUT source: 1 0 0 11 changed: 1 0 0 11 step 154 100001101110100100011011011011011100110111011011011010100110110111 source: 0 1 1 00 changed: 0 1 1 00 step 155 100001100110100100011011011011011101111100011011011010100110110111 source: ; set pin AC1 to clear pin BB2 and set TAPE BUS 3 OUTPUT source: 1 0 1 changed: 1 0 1 step 156 100001100111100100011011011011011100111101011011011010100110110111 source: 0 1 0 changed: 0 1 0 step 157 100001100110100100011011011011011101111100011011011010100110110111 source: ; set pin AF1 to clear pin BB2 and set TAPE BUS 3 OUTPUT source: 1 0 1 changed: 1 0 1 step 158 100001100110110100011011011011011100111101011011011010100110110111 source: 0 1 0 changed: 0 1 0 step 159 100001100110100100011011011011011101111100011011011010100110110111 source: ; set pin AR2 to clear pin AN2 AND-NOR OUTPUTS and set TAPE BUS 2 OUTPUT source: 1 0 1 changed: 1 0 1 step 160 100001100110101100011011011011011101110110011011011010100110110111 source: 0 1 0 changed: 0 1 0 step 161 100001100110100100011011011011011101111100011011011010100110110111 source: ; set pin AP2 to clear pin AN2 AND-NOR OUTPUTS and set TAPE BUS 2 OUTPUT source: 1 0 1 changed: 1 0 1 step 162 100001100110100110011011011011011101110110011011011010100110110111 source: 0 1 0 changed: 0 1 0 step 163 100001100110100100011011011011011101111100011011011010100110110111 source: source: ; set pin BK1 to clear pin BB1 and pin BN1 AND-NOR OUTPUTS and set TAPE BUS 2 OUTPUT and TAPE BUS 3 OUTPUT source: 1 00 11 changed: 1 00 11 step 164 100001100110100101011011011011011101001111011011011010100110110111 source: 0 11 00 changed: 0 11 00 step 165 100001100110100100011011011011011101111100011011011010100110110111 source: ; set pin BL1 to clear pin BB1 and pin BN1 AND-NOR OUTPUTS and set TAPE BUS 2 OUTPUT and TAPE BUS 3 OUTPUT source: 1 00 11 changed: 1 00 11 step 166 100001100110100100111011011011011101001111011011011010100110110111 source: 0 11 00 changed: 0 11 00 step 167 100001100110100100011011011011011101111100011011011010100110110111 source: ; set pin BF1 to clear pin BB1 and pin BN1 AND-NOR OUTPUTS and set TAPE BUS 2 OUTPUT and TAPE BUS 3 OUTPUT source: 1 00 11 changed: 1 00 11 step 168 100001100110100100011111011011011101001111011011011010100110110111 source: 0 11 00 changed: 0 11 00 step 169 100001100110100100011011011011011101111100011011011010100110110111 source: ; set pin BS1 to clear pin BB1 and pin BN1 AND-NOR OUTPUTS and set TAPE BUS 2 OUTPUT and TAPE BUS 3 OUTPUT source: 1 00 11 changed: 1 00 11 step 170 100001100110100100011011111011011101001111011011011010100110110111 source: 0 11 00 changed: 0 11 00 step 171 100001100110100100011011011011011101111100011011011010100110110111 source: ; set pin BL2 to clear pin BB1 and pin BN1 AND-NOR OUTPUTS and set TAPE BUS 2 OUTPUT and TAPE BUS 3 OUTPUT source: 1 00 11 changed: 1 00 11 step 172 100001100110100100011011011111011101001111011011011010100110110111 source: 0 11 00 changed: 0 11 00 step 173 100001100110100100011011011011011101111100011011011010100110110111 source: ; set pin BU1 to clear pin BB1 and pin BN1 AND-NOR OUTPUTS and set TAPE BUS 2 OUTPUT and TAPE BUS 3 OUTPUT source: 1 00 11 changed: 1 00 11 step 174 100001100110100100011011011011111101001111011011011010100110110111 source: 0 11 00 changed: 0 11 00 step 175 100001100110100100011011011011011101111100011011011010100110110111 source: ; set pin BM2 to clear pin BB1 and TAPE BUS 3 OUTPUT source: 1 0 1 changed: 1 0 1 step 176 100001100110100100011011011011011111101110011011011010100110110111 source: 0 1 0 changed: 0 1 0 step 177 100001100110100100011011011011011101111100011011011010100110110111 source: ; no change source: 100000000000000000000000000000000001111100011011011010100110110111 changed: 00 00 0 0 00 00 00 00 000 step 178 100000000000000000000000000000000001111100011011011010100110110111 source: source: source: ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; source: ; test shifting the RWB source: ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; source: source: ; shift in 0, expect 10 source: 0 changed: 0 step 179 100000000000000000000000000000000001111100011011011010100110100111 source: 110 changed: 1 0 step 180 100000000000000000000000000000000001111100011011011010100110101101 source: 0 changed: 0 step 181 100000000000000000000000000000000001111100011011011010100110100101 source: ; toggle phase should toggle RWB 2 source: 0 0 changed: 0 0 step 182 100000000000000000000000000000000001111100011011011010100110000001 source: 1 1 changed: 1 1 step 183 100000000000000000000000000000000001111100011011011010100110100101 source: source: ; shift in 0, expect 00 source: 0 changed: step 184 100000000000000000000000000000000001111100011011011010100110100101 source: 100 changed: 10 step 185 100000000000000000000000000000000001111100011011011010100110101001 source: 0 changed: 0 step 186 100000000000000000000000000000000001111100011011011010100110100001 source: ; toggle phase should toggle RWB 2 source: 0 1 changed: 0 1 step 187 100000000000000000000000000000000001111100011011011010100110000101 source: 1 0 changed: 1 0 step 188 100000000000000000000000000000000001111100011011011010100110100001 source: source: ; shift in 0, expect 00 source: 0 changed: step 189 100000000000000000000000000000000001111100011011011010100110100001 source: 100 changed: 1 step 190 100000000000000000000000000000000001111100011011011010100110101001 source: 0 changed: 0 step 191 100000000000000000000000000000000001111100011011011010100110100001 source: ; shift in 1, expect 01 source: 1 changed: 1 step 192 100000000000000000000000000000000001111100011011011010100110110001 source: 101 changed: 1 1 step 193 100000000000000000000000000000000001111100011011011010100110111011 source: 0 changed: 0 step 194 100000000000000000000000000000000001111100011011011010100110110011 source: ; shift in 1, expect 11 source: 1 changed: step 195 100000000000000000000000000000000001111100011011011010100110110011 source: 111 changed: 11 step 196 100000000000000000000000000000000001111100011011011010100110111111 source: 0 changed: 0 step 197 100000000000000000000000000000000001111100011011011010100110110111 source: ; shift in 1, expect 11 source: 1 changed: step 198 100000000000000000000000000000000001111100011011011010100110110111 source: 111 changed: 1 step 199 100000000000000000000000000000000001111100011011011010100110111111 source: 0 changed: 0 step 200 100000000000000000000000000000000001111100011011011010100110110111 source: ; shift in 0, expect 10 source: 0 changed: 0 step 201 100000000000000000000000000000000001111100011011011010100110100111 source: 110 changed: 1 0 step 202 100000000000000000000000000000000001111100011011011010100110101101 source: 0 changed: 0 step 203 100000000000000000000000000000000001111100011011011010100110100101 source: ; shift in 1, expect 01 source: 1 changed: 1 step 204 100000000000000000000000000000000001111100011011011010100110110101 source: 101 changed: 101 step 205 100000000000000000000000000000000001111100011011011010100110111011 source: 0 changed: 0 step 206 100000000000000000000000000000000001111100011011011010100110110011 source: ; shift in 0, expect 10 source: 0 changed: 0 step 207 100000000000000000000000000000000001111100011011011010100110100011 source: 110 changed: 110 step 208 100000000000000000000000000000000001111100011011011010100110101101 source: 0 changed: 0 step 209 100000000000000000000000000000000001111100011011011010100110100101 source: ; shift in 1, expect 01 source: 1 changed: 1 step 210 100000000000000000000000000000000001111100011011011010100110110101 source: 101 changed: 101 step 211 100000000000000000000000000000000001111100011011011010100110111011 source: 0 changed: 0 step 212 100000000000000000000000000000000001111100011011011010100110110011 source: ; shift in 1, expect 11 source: 1 changed: step 213 100000000000000000000000000000000001111100011011011010100110110011 source: 111 changed: 11 step 214 100000000000000000000000000000000001111100011011011010100110111111 source: 0 changed: 0 step 215 100000000000000000000000000000000001111100011011011010100110110111 source: ; no change source: 100000000000000000000000000000000001111100011011011010100110110111 changed: step 216 100000000000000000000000000000000001111100011011011010100110110111 test 21: pass SLOT BAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBAABBAAAAAAAAAAAAAABBBBBABBBB LETTER ALPSLFMDEEMCBFRSPKLEMFHRSCJLJKUHPNMBBNNVVRKRHUTDJUKANJHBTPDFSVEVDU SIDE 121212122121212121111111112212122222112222111221112112212112212122 DIRECTION IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIOOOOOOOIOOIOOIOOIOOOOIOOIIIIOOO this fail all fails was hi 111111111111111111111111111111111111111111111111111111111111111111 rising ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ ^^^^^^^^^^^^^^^^^^^^^^^^^ falling vvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvv vvvvvvvvvvvvvvvvvvvvvvvvv was lo 00000000000000000000000000000000000000 0000000000000000000000000 total fails 0, total passes 21 space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C toggle comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit source: ; all registers are unknown source: ; turn on C0, PHASE source: ; with no ENABLES, BUS2,BUS3 is 11, C2 is 1 source: 1000000000000000000000000000000000011111000XX0XX0XX0XXXX0XX0110XX1 changed: step 1 100000000000000000000000000000000001111100011011011010100110110111 source: source: ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; source: ; source: ; set all registers LOW source: ; source: ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; source: source: ; load TMA SETUP from tape bus (00) source: 100 changed: 100 step 2 100000000000000000000000000000000001111100100011011010100110110111 source: 0 changed: 0 step 3 100000000000000000000000000000000001111100000011011010100110110111 source: ; load TMA from tape bus (00) source: 100 changed: 100 step 4 100000000000000000000000000000000001111100000100011010100110110111 source: 0 changed: 0 step 5 100000000000000000000000000000000001111100000000011010100110110111 source: ; load TBN from tape bus (00) source: 100 changed: 100 step 6 100000000000000000000000000000000001111100000000100010100110110111 source: 0 changed: 0 step 7 100000000000000000000000000000000001111100000000000010100110110111 source: ; load TAC from tape bus (00) source: 10101 changed: 10101 step 8 100000000000000000000000000000000001111100000000000101010110110111 source: 0 changed: 0 step 9 100000000000000000000000000000000001111100000000000001010110110111 source: ; load TB from tape bus (00) source: 100 changed: 100 step 10 100000000000000000000000000000000001111100000000000001011000110111 source: 0 changed: 0 step 11 100000000000000000000000000000000001111100000000000001010000110111 source: ; load RWB from TB (JAMS CLEAR AND PRESET) source: 1 00 changed: 1 00 step 12 100000000000000000000000000000000001111100000000000001010001110001 source: 0 changed: 0 step 13 100000000000000000000000000000000001111100000000000001010000110001 source: ; (no change) source: 100000000000000000000000000000000001111100000000000001010000110001 changed: step 14 100000000000000000000000000000000001111100000000000001010000110001 source: source: source: ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; source: ; source: ; set all registers HIGH source: ; source: ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; source: source: ; set pin AF1 which clears pin BB2 and sets pin BR2 TAPE BUS 3 OUTPUT source: 1 0 1 changed: 1 0 1 step 15 100000000000010000000000000000000000111101000000000001010000110001 source: ; set pin AP2 which clears pin AN2 and sets pin BV2 TAPE BUS 2 OUTPUT source: 1 0 1 changed: 1 0 1 step 16 100000000000010010000000000000000000110111000000000001010000110001 source: source: source: ; load TMA SETUP from tape bus (11) source: 111 changed: 111 step 17 100000000000010010000000000000000000110111111000000001010000110001 source: 0 changed: 0 step 18 100000000000010010000000000000000000110111011000000001010000110001 source: ; load TMA from tape bus (11) source: 111 changed: 111 step 19 100000000000010010000000000000000000110111011111000001010000110001 source: 0 changed: 0 step 20 100000000000010010000000000000000000110111011011000001010000110001 source: ; load TBN from tape bus (11) source: 111 changed: 111 step 21 100000000000010010000000000000000000110111011011111001010000110001 source: 0 changed: 0 step 22 100000000000010010000000000000000000110111011011011001010000110001 source: ; load TAC from tape bus (11) source: 11010 changed: 11010 step 23 100000000000010010000000000000000000110111011011011110100000110001 source: 0 changed: 0 step 24 100000000000010010000000000000000000110111011011011010100000110001 source: ; load TB from tape bus (11) source: 111 changed: 111 step 25 100000000000010010000000000000000000110111011011011010101110110001 source: 0 changed: 0 step 26 100000000000010010000000000000000000110111011011011010100110110001 source: ; load RWB from TB (JAMS CLEAR AND PRESET) source: 1 11 changed: 1 11 step 27 100000000000010010000000000000000000110111011011011010100111110111 source: 0 changed: 0 step 28 100000000000010010000000000000000000110111011011011010100110110111 source: ; clear pin AF1 (AND with itself) to set pin BB2 (AND-NOR output) and clear pin BR2 TAPE BUS 3 OUTPUT source: 0 1 0 changed: 0 1 0 step 29 100000000000000010000000000000000001110110011011011010100110110111 source: ; clear pin AP2 (AND with itself) to set pin AN2 (AND-NOR output) and clear pin BV2 TAPE BUS 2 OUTPUT source: 0 1 0 changed: 0 1 0 step 30 100000000000000000000000000000000001111100011011011010100110110111 source: ; (no change) source: 100000000000000000000000000000000001111100011011011010100110110111 changed: step 31 100000000000000000000000000000000001111100011011011010100110110111 source: source: ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; source: ; source: ; will all registers high, walk a 0 source: ; source: ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; source: source: source: ; walk a 0, TMA SETUP 2 source: source: source: ; clear pin AP2 which sets pin AN2 and clears pin BV2 TAPE BUS 2 OUTPUT source: 0 1 0 changed: step 32 100000000000000000000000000000000001111100011011011010100110110111 source: ; set pin AF1 which clears pin BB2 and sets pin BR2 TAPE BUS 3 OUTPUT source: 1 0 1 changed: 1 0 1 step 33 100000000000010000000000000000000000111101011011011010100110110111 source: ; load TMA SETUP from tape bus (01) source: 101 changed: 10 step 34 100000000000010000000000000000000000111101101011011010100110110111 source: 0 changed: 0 step 35 100000000000010000000000000000000000111101001011011010100110110111 source: ; restore TMA SETUP 2 source: ; set pin AP2 which clears pin AN2 and sets pin BV2 TAPE BUS 2 OUTPUT source: 1 0 1 changed: 1 0 1 step 36 100000000000010010000000000000000000110111001011011010100110110111 source: ; load TMA SETUP from tape bus (11) source: 111 changed: 11 step 37 100000000000010010000000000000000000110111111011011010100110110111 source: 0 changed: 0 step 38 100000000000010010000000000000000000110111011011011010100110110111 source: source: source: ; walk a 0, TMA SETUP 3 source: source: source: ; set pin AP2 which clears pin AN2 and sets pin BV2 TAPE BUS 2 OUTPUT source: 1 0 1 changed: step 39 100000000000010010000000000000000000110111011011011010100110110111 source: ; clear pin AF1 which sets pin BB2 and clears pin BR2 TAPE BUS 3 OUTPUT source: 0 1 0 changed: 0 1 0 step 40 100000000000000010000000000000000001110110011011011010100110110111 source: ; load TMA SETUP from tape bus (10) source: 110 changed: 1 0 step 41 100000000000000010000000000000000001110110110011011010100110110111 source: 0 changed: 0 step 42 100000000000000010000000000000000001110110010011011010100110110111 source: ; restore TMA SETUP 3 source: ; set pin AF1 which clears pin BB2 and sets pin BR2 TAPE BUS 3 OUTPUT source: 1 0 1 changed: 1 0 1 step 43 100000000000010010000000000000000000110111010011011010100110110111 source: ; load TMA SETUP from tape bus (11) source: 111 changed: 1 1 step 44 100000000000010010000000000000000000110111111011011010100110110111 source: 0 changed: 0 step 45 100000000000010010000000000000000000110111011011011010100110110111 source: source: source: ; walk a 0, TMA 2 source: source: source: ; clear pin AP2 which sets pin AN2 and clears pin BV2 TAPE BUS 2 OUTPUT source: 0 1 0 changed: 0 1 0 step 46 100000000000010000000000000000000000111101011011011010100110110111 source: ; set pin AF1 which clears pin BB2 and sets pin BR2 TAPE BUS 3 OUTPUT source: 1 0 1 changed: step 47 100000000000010000000000000000000000111101011011011010100110110111 source: ; load TMA from tape bus (01) source: 101 changed: 10 step 48 100000000000010000000000000000000000111101011101011010100110110111 source: 0 changed: 0 step 49 100000000000010000000000000000000000111101011001011010100110110111 source: ; restore TMA 2 source: ; set pin AP2 which clears pin AN2 and sets pin BV2 TAPE BUS 2 OUTPUT source: 1 0 1 changed: 1 0 1 step 50 100000000000010010000000000000000000110111011001011010100110110111 source: ; load TMA from tape bus (11) source: 111 changed: 11 step 51 100000000000010010000000000000000000110111011111011010100110110111 source: 0 changed: 0 step 52 100000000000010010000000000000000000110111011011011010100110110111 source: source: source: ; walk a 0, TMA 3 source: source: source: ; set pin AP2 which clears pin AN2 and sets pin BV2 TAPE BUS 2 OUTPUT source: 1 0 1 changed: step 53 100000000000010010000000000000000000110111011011011010100110110111 source: ; clear pin AF1 which sets pin BB2 and clears pin BR2 TAPE BUS 3 OUTPUT source: 0 1 0 changed: 0 1 0 step 54 100000000000000010000000000000000001110110011011011010100110110111 source: ; load TMA from tape bus (10) source: 110 changed: 1 0 step 55 100000000000000010000000000000000001110110011110011010100110110111 source: 0 changed: 0 step 56 100000000000000010000000000000000001110110011010011010100110110111 source: ; restore TMA 3 source: ; set pin AF1 which clears pin BB2 and sets pin BR2 TAPE BUS 3 OUTPUT source: 1 0 1 changed: 1 0 1 step 57 100000000000010010000000000000000000110111011010011010100110110111 source: ; load TMA from tape bus (11) source: 111 changed: 1 1 step 58 100000000000010010000000000000000000110111011111011010100110110111 source: 0 changed: 0 step 59 100000000000010010000000000000000000110111011011011010100110110111 source: source: source: ; walk a 0, TBN 2 source: source: source: ; clear pin AP2 which sets pin AN2 and clears pin BV2 TAPE BUS 2 OUTPUT source: 0 1 0 changed: 0 1 0 step 60 100000000000010000000000000000000000111101011011011010100110110111 source: ; set pin AF1 which clears pin BB2 and sets pin BR2 TAPE BUS 3 OUTPUT source: 1 0 1 changed: step 61 100000000000010000000000000000000000111101011011011010100110110111 source: ; load TBN from tape bus (01) source: 101 changed: 10 step 62 100000000000010000000000000000000000111101011011101010100110110111 source: 0 changed: 0 step 63 100000000000010000000000000000000000111101011011001010100110110111 source: ; restore TBN 2 source: ; set pin AP2 which clears pin AN2 and sets pin BV2 TAPE BUS 2 OUTPUT source: 1 0 1 changed: 1 0 1 step 64 100000000000010010000000000000000000110111011011001010100110110111 source: ; load TBN from tape bus (11) source: 111 changed: 11 step 65 100000000000010010000000000000000000110111011011111010100110110111 source: 0 changed: 0 step 66 100000000000010010000000000000000000110111011011011010100110110111 source: source: source: ; walk a 0, TBN 3 source: source: source: ; set pin AP2 which clears pin AN2 and sets pin BV2 TAPE BUS 2 OUTPUT source: 1 0 1 changed: step 67 100000000000010010000000000000000000110111011011011010100110110111 source: ; clear pin AF1 which sets pin BB2 and clears pin BR2 TAPE BUS 3 OUTPUT source: 0 1 0 changed: 0 1 0 step 68 100000000000000010000000000000000001110110011011011010100110110111 source: ; load TBN from tape bus (10) source: 110 changed: 1 0 step 69 100000000000000010000000000000000001110110011011110010100110110111 source: 0 changed: 0 step 70 100000000000000010000000000000000001110110011011010010100110110111 source: ; restore TBN 3 source: ; set pin AF1 which clears pin BB2 and sets pin BR2 TAPE BUS 3 OUTPUT source: 1 0 1 changed: 1 0 1 step 71 100000000000010010000000000000000000110111011011010010100110110111 source: ; load TBN from tape bus (11) source: 111 changed: 1 1 step 72 100000000000010010000000000000000000110111011011111010100110110111 source: 0 changed: 0 step 73 100000000000010010000000000000000000110111011011011010100110110111 source: source: source: ; walk a 0, TAC 2 source: source: source: ; clear pin AP2 which sets pin AN2 and clears pin BV2 TAPE BUS 2 OUTPUT source: 0 1 0 changed: 0 1 0 step 74 100000000000010000000000000000000000111101011011011010100110110111 source: ; set pin AF1 which clears pin BB2 and sets pin BR2 TAPE BUS 3 OUTPUT source: 1 0 1 changed: step 75 100000000000010000000000000000000000111101011011011010100110110111 source: ; load TAC from tape bus (01) source: 10110 changed: 101 step 76 100000000000010000000000000000000000111101011011011101100110110111 source: 0 changed: 0 step 77 100000000000010000000000000000000000111101011011011001100110110111 source: ; restore TAC 2 source: ; set pin AP2 which clears pin AN2 and sets pin BV2 TAPE BUS 2 OUTPUT source: 1 0 1 changed: 1 0 1 step 78 100000000000010010000000000000000000110111011011011001100110110111 source: ; load TAC from tape bus (11) source: 11010 changed: 110 step 79 100000000000010010000000000000000000110111011011011110100110110111 source: 0 changed: 0 step 80 100000000000010010000000000000000000110111011011011010100110110111 source: source: source: ; walk a 0, TAC 3 source: source: source: ; set pin AP2 which clears pin AN2 and sets pin BV2 TAPE BUS 2 OUTPUT source: 1 0 1 changed: step 81 100000000000010010000000000000000000110111011011011010100110110111 source: ; clear pin AF1 which sets pin BB2 and clears pin BR2 TAPE BUS 3 OUTPUT source: 0 1 0 changed: 0 1 0 step 82 100000000000000010000000000000000001110110011011011010100110110111 source: ; load TAC from tape bus (10) source: 11001 changed: 1 01 step 83 100000000000000010000000000000000001110110011011011110010110110111 source: 0 changed: 0 step 84 100000000000000010000000000000000001110110011011011010010110110111 source: ; restore TAC 3 source: ; set pin AF1 which clears pin BB2 and sets pin BR2 TAPE BUS 3 OUTPUT source: 1 0 1 changed: 1 0 1 step 85 100000000000010010000000000000000000110111011011011010010110110111 source: ; load TAC from tape bus (11) source: 11010 changed: 1 10 step 86 100000000000010010000000000000000000110111011011011110100110110111 source: 0 changed: 0 step 87 100000000000010010000000000000000000110111011011011010100110110111 source: source: source: ; walk a 0, TB 2 source: source: source: ; clear pin AP2 which sets pin AN2 and clears pin BV2 TAPE BUS 2 OUTPUT source: 0 1 0 changed: 0 1 0 step 88 100000000000010000000000000000000000111101011011011010100110110111 source: ; set pin AF1 which clears pin BB2 and sets pin BR2 TAPE BUS 3 OUTPUT source: 1 0 1 changed: step 89 100000000000010000000000000000000000111101011011011010100110110111 source: ; load TB from tape bus (01) source: 101 changed: 10 step 90 100000000000010000000000000000000000111101011011011010101010110111 source: 0 changed: 0 step 91 100000000000010000000000000000000000111101011011011010100010110111 source: ; restore TB 2 source: ; set pin AP2 which clears pin AN2 and sets pin BV2 TAPE BUS 2 OUTPUT source: 1 0 1 changed: 1 0 1 step 92 100000000000010010000000000000000000110111011011011010100010110111 source: ; load TB from tape bus (11) source: 111 changed: 11 step 93 100000000000010010000000000000000000110111011011011010101110110111 source: 0 changed: 0 step 94 100000000000010010000000000000000000110111011011011010100110110111 source: source: source: ; walk a 0, TB 3 source: source: source: ; set pin AP2 which clears pin AN2 and sets pin BV2 TAPE BUS 2 OUTPUT source: 1 0 1 changed: step 95 100000000000010010000000000000000000110111011011011010100110110111 source: ; clear pin AF1 which sets pin BB2 and clears pin BR2 TAPE BUS 3 OUTPUT source: 0 1 0 changed: 0 1 0 step 96 100000000000000010000000000000000001110110011011011010100110110111 source: ; load TB from tape bus (10) source: 110 changed: 1 0 step 97 100000000000000010000000000000000001110110011011011010101100110111 source: 0 changed: 0 step 98 100000000000000010000000000000000001110110011011011010100100110111 source: ; restore TB 3 source: ; set pin AF1 which clears pin BB2 and sets pin BR2 TAPE BUS 3 OUTPUT source: 1 0 1 changed: 1 0 1 step 99 100000000000010010000000000000000000110111011011011010100100110111 source: ; load TB from tape bus (11) source: 111 changed: 1 1 step 100 100000000000010010000000000000000000110111011011011010101110110111 source: 0 changed: 0 step 101 100000000000010010000000000000000000110111011011011010100110110111 source: source: source: ; walk a 0, RWB 2 source: source: source: ; clear pin AP2 which sets pin AN2 and clears pin BV2 TAPE BUS 2 OUTPUT source: 0 1 0 changed: 0 1 0 step 102 100000000000010000000000000000000000111101011011011010100110110111 source: ; set pin AF1 which clears pin BB2 and sets pin BR2 TAPE BUS 3 OUTPUT source: 1 0 1 changed: step 103 100000000000010000000000000000000000111101011011011010100110110111 source: ; load TB from tape bus (01) source: 101 changed: 10 step 104 100000000000010000000000000000000000111101011011011010101010110111 source: 0 changed: 0 step 105 100000000000010000000000000000000000111101011011011010100010110111 source: ; load RWB from TB (JAMS CLEAR AND PRESET) source: 1 01 changed: 1 0 step 106 100000000000010000000000000000000000111101011011011010100011110011 source: 0 changed: 0 step 107 100000000000010000000000000000000000111101011011011010100010110011 source: ; restore TB 2 and RWB 2 source: ; set pin AP2 which clears pin AN2 and sets pin BV2 TAPE BUS 2 OUTPUT source: 1 0 1 changed: 1 0 1 step 108 100000000000010010000000000000000000110111011011011010100010110011 source: ; load TB from tape bus (11) source: 111 changed: 11 step 109 100000000000010010000000000000000000110111011011011010101110110011 source: 0 changed: 0 step 110 100000000000010010000000000000000000110111011011011010100110110011 source: ; load RWB from TB (JAMS CLEAR AND PRESET) source: 1 11 changed: 1 1 step 111 100000000000010010000000000000000000110111011011011010100111110111 source: 0 changed: 0 step 112 100000000000010010000000000000000000110111011011011010100110110111 source: source: source: ; walk a 0, RWB 3 source: source: source: ; set pin AP2 which clears pin AN2 and sets pin BV2 TAPE BUS 2 OUTPUT source: 1 0 1 changed: step 113 100000000000010010000000000000000000110111011011011010100110110111 source: ; clear pin AF1 which sets pin BB2 and clears pin BR2 TAPE BUS 3 OUTPUT source: 0 1 0 changed: 0 1 0 step 114 100000000000000010000000000000000001110110011011011010100110110111 source: ; load TB from tape bus (10) source: 110 changed: 1 0 step 115 100000000000000010000000000000000001110110011011011010101100110111 source: 0 changed: 0 step 116 100000000000000010000000000000000001110110011011011010100100110111 source: ; load RWB from TB (JAMS CLEAR AND PRESET) source: 1 10 changed: 1 0 step 117 100000000000000010000000000000000001110110011011011010100101110101 source: 0 changed: 0 step 118 100000000000000010000000000000000001110110011011011010100100110101 source: ; restore TB 3 and RWB 3 source: ; set pin AF1 which clears pin BB2 and sets pin BR2 TAPE BUS 3 OUTPUT source: 1 0 1 changed: 1 0 1 step 119 100000000000010010000000000000000000110111011011011010100100110101 source: ; load TB from tape bus (11) source: 111 changed: 1 1 step 120 100000000000010010000000000000000000110111011011011010101110110101 source: 0 changed: 0 step 121 100000000000010010000000000000000000110111011011011010100110110101 source: ; load RWB from TB (JAMS CLEAR AND PRESET) source: 1 11 changed: 1 1 step 122 100000000000010010000000000000000000110111011011011010100111110111 source: 0 changed: 0 step 123 100000000000010010000000000000000000110111011011011010100110110111 source: source: ; clear pin AF1 (AND with itself) to set pin BB2 (AND-NOR output) and clear pin BR2 TAPE BUS 3 OUTPUT source: 0 1 0 changed: 0 1 0 step 124 100000000000000010000000000000000001110110011011011010100110110111 source: ; clear pin AP2 (AND with itself) to set pin AN2 (AND-NOR output) and clear pin BV2 TAPE BUS 2 OUTPUT source: 0 1 0 changed: 0 1 0 step 125 100000000000000000000000000000000001111100011011011010100110110111 source: ; (no change) source: 100000000000000000000000000000000001111100011011011010100110110111 changed: step 126 100000000000000000000000000000000001111100011011011010100110110111 source: source: source: ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; source: ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; source: ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; source: ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; source: ;********************* need to walk a one ********************** source: ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; source: ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; source: ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; source: ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; source: source: ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; source: ; source: ; test AND-NOR logic source: ; source: ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; source: source: ; (all registers are HIGH) source: ; set all pins HIGH except ENABLES source: source: ; set pin AF2 HIGH source: 1 changed: 1 step 127 100001000000000000000000000000000001111100011011011010100110110111 source: ; set pin AM1 HIGH source: 1 changed: 1 step 128 100001100000000000000000000000000001111100011011011010100110110111 source: ; set pin AE1 HIGH source: 1 changed: 1 step 129 100001100100000000000000000000000001111100011011011010100110110111 source: ; set pin AM2 HIGH source: 1 changed: 1 step 130 100001100110000000000000000000000001111100011011011010100110110111 source: ; set pin AB2 HIGH source: 1 changed: 1 step 131 100001100110100000000000000000000001111100011011011010100110110111 source: ; set pin AS1 HIGH source: 1 changed: 1 step 132 100001100110100100000000000000000001111100011011011010100110110111 source: ; set pin BE1 HIGH source: 1 changed: 1 step 133 100001100110100100010000000000000001111100011011011010100110110111 source: ; set pin BM1 HIGH source: 1 changed: 1 step 134 100001100110100100011000000000000001111100011011011010100110110111 source: ; set pin BH1 HIGH source: 1 changed: 1 step 135 100001100110100100011010000000000001111100011011011010100110110111 source: ; set pin BR1 HIGH source: 1 changed: 1 step 136 100001100110100100011011000000000001111100011011011010100110110111 source: ; set pin BC1 HIGH source: 1 changed: 1 step 137 100001100110100100011011010000000001111100011011011010100110110111 source: ; set pin BJ2 HIGH source: 1 changed: 1 step 138 100001100110100100011011011000000001111100011011011010100110110111 source: ; set pin BJ1 HIGH source: 1 changed: 1 step 139 100001100110100100011011011010000001111100011011011010100110110111 source: ; set pin BK2 HIGH source: 1 changed: 1 step 140 100001100110100100011011011011000001111100011011011010100110110111 source: ; set pin BH2 HIGH source: 1 changed: 1 step 141 100001100110100100011011011011010001111100011011011010100110110111 source: ; set pin BP2 HIGH source: 1 changed: 1 step 142 100001100110100100011011011011011001111100011011011010100110110111 source: ; set pin BN2 HIGH source: 1 changed: 1 step 143 100001100110100100011011011011011101111100011011011010100110110111 source: ; toggle each ENABLE source: source: ; set pin AL2 to clear pin BB2 and pin AN2 AND-NOR OUTPUTS and set TAPE BUS 2 OUTPUT and TAPE BUS 3 OUTPUT source: 1 0 0 11 changed: 1 0 0 11 step 144 110001100110100100011011011011011100110111011011011010100110110111 source: 0 1 1 00 changed: 0 1 1 00 step 145 100001100110100100011011011011011101111100011011011010100110110111 source: ; set pin AP1 to clear pin BB2 and pin AN2 AND-NOR OUTPUTS and set TAPE BUS 2 OUTPUT and TAPE BUS 3 OUTPUT source: 1 0 0 11 changed: 1 0 0 11 step 146 101001100110100100011011011011011100110111011011011010100110110111 source: 0 1 1 00 changed: 0 1 1 00 step 147 100001100110100100011011011011011101111100011011011010100110110111 source: ; set pin AS2 to clear pin BB2 and pin AN2 AND-NOR OUTPUTS and set TAPE BUS 2 OUTPUT and TAPE BUS 3 OUTPUT source: 1 0 0 11 changed: 1 0 0 11 step 148 100101100110100100011011011011011100110111011011011010100110110111 source: 0 1 1 00 changed: 0 1 1 00 step 149 100001100110100100011011011011011101111100011011011010100110110111 source: ; set pin AL1 to clear pin BB2 and pin AN2 AND-NOR OUTPUTS and set TAPE BUS 2 OUTPUT and TAPE BUS 3 OUTPUT source: 1 0 0 11 changed: 1 0 0 11 step 150 100011100110100100011011011011011100110111011011011010100110110111 source: 0 1 1 00 changed: 0 1 1 00 step 151 100001100110100100011011011011011101111100011011011010100110110111 source: ; set pin AL1 to clear pin BB2 and pin AN2 AND-NOR OUTPUTS and set TAPE BUS 2 OUTPUT and TAPE BUS 3 OUTPUT source: 1 0 0 11 changed: 1 0 0 11 step 152 100001110110100100011011011011011100110111011011011010100110110111 source: 0 1 1 00 changed: 0 1 1 00 step 153 100001100110100100011011011011011101111100011011011010100110110111 source: ; set pin AE2 to clear pin BB2 and pin AN2 AND-NOR OUTPUTS and set TAPE BUS 2 OUTPUT and TAPE BUS 3 OUTPUT source: 1 0 0 11 changed: 1 0 0 11 step 154 100001101110100100011011011011011100110111011011011010100110110111 source: 0 1 1 00 changed: 0 1 1 00 step 155 100001100110100100011011011011011101111100011011011010100110110111 source: ; set pin AC1 to clear pin BB2 and set TAPE BUS 3 OUTPUT source: 1 0 1 changed: 1 0 1 step 156 100001100111100100011011011011011100111101011011011010100110110111 source: 0 1 0 changed: 0 1 0 step 157 100001100110100100011011011011011101111100011011011010100110110111 source: ; set pin AF1 to clear pin BB2 and set TAPE BUS 3 OUTPUT source: 1 0 1 changed: 1 0 1 step 158 100001100110110100011011011011011100111101011011011010100110110111 source: 0 1 0 changed: 0 1 0 step 159 100001100110100100011011011011011101111100011011011010100110110111 source: ; set pin AR2 to clear pin AN2 AND-NOR OUTPUTS and set TAPE BUS 2 OUTPUT source: 1 0 1 changed: 1 0 1 step 160 100001100110101100011011011011011101110110011011011010100110110111 source: 0 1 0 changed: 0 1 0 step 161 100001100110100100011011011011011101111100011011011010100110110111 source: ; set pin AP2 to clear pin AN2 AND-NOR OUTPUTS and set TAPE BUS 2 OUTPUT source: 1 0 1 changed: 1 0 1 step 162 100001100110100110011011011011011101110110011011011010100110110111 source: 0 1 0 changed: 0 1 0 step 163 100001100110100100011011011011011101111100011011011010100110110111 source: source: ; set pin BK1 to clear pin BB1 and pin BN1 AND-NOR OUTPUTS and set TAPE BUS 2 OUTPUT and TAPE BUS 3 OUTPUT source: 1 00 11 changed: 1 00 11 step 164 100001100110100101011011011011011101001111011011011010100110110111 source: 0 11 00 changed: 0 11 00 step 165 100001100110100100011011011011011101111100011011011010100110110111 source: ; set pin BL1 to clear pin BB1 and pin BN1 AND-NOR OUTPUTS and set TAPE BUS 2 OUTPUT and TAPE BUS 3 OUTPUT source: 1 00 11 changed: 1 00 11 step 166 100001100110100100111011011011011101001111011011011010100110110111 source: 0 11 00 changed: 0 11 00 step 167 100001100110100100011011011011011101111100011011011010100110110111 source: ; set pin BF1 to clear pin BB1 and pin BN1 AND-NOR OUTPUTS and set TAPE BUS 2 OUTPUT and TAPE BUS 3 OUTPUT source: 1 00 11 changed: 1 00 11 step 168 100001100110100100011111011011011101001111011011011010100110110111 source: 0 11 00 changed: 0 11 00 step 169 100001100110100100011011011011011101111100011011011010100110110111 source: ; set pin BS1 to clear pin BB1 and pin BN1 AND-NOR OUTPUTS and set TAPE BUS 2 OUTPUT and TAPE BUS 3 OUTPUT source: 1 00 11 changed: 1 00 11 step 170 100001100110100100011011111011011101001111011011011010100110110111 source: 0 11 00 changed: 0 11 00 step 171 100001100110100100011011011011011101111100011011011010100110110111 source: ; set pin BL2 to clear pin BB1 and pin BN1 AND-NOR OUTPUTS and set TAPE BUS 2 OUTPUT and TAPE BUS 3 OUTPUT source: 1 00 11 changed: 1 00 11 step 172 100001100110100100011011011111011101001111011011011010100110110111 source: 0 11 00 changed: 0 11 00 step 173 100001100110100100011011011011011101111100011011011010100110110111 source: ; set pin BU1 to clear pin BB1 and pin BN1 AND-NOR OUTPUTS and set TAPE BUS 2 OUTPUT and TAPE BUS 3 OUTPUT source: 1 00 11 changed: 1 00 11 step 174 100001100110100100011011011011111101001111011011011010100110110111 source: 0 11 00 changed: 0 11 00 step 175 100001100110100100011011011011011101111100011011011010100110110111 source: ; set pin BM2 to clear pin BB1 and TAPE BUS 3 OUTPUT source: 1 0 1 changed: 1 0 1 step 176 100001100110100100011011011011011111101110011011011010100110110111 source: 0 1 0 changed: 0 1 0 step 177 100001100110100100011011011011011101111100011011011010100110110111 source: ; no change source: 100000000000000000000000000000000001111100011011011010100110110111 changed: 00 00 0 0 00 00 00 00 000 step 178 100000000000000000000000000000000001111100011011011010100110110111 source: source: source: ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; source: ; test shifting the RWB source: ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; source: source: ; shift in 0, expect 10 source: 0 changed: 0 step 179 100000000000000000000000000000000001111100011011011010100110100111 source: 110 changed: 1 0 step 180 100000000000000000000000000000000001111100011011011010100110101101 source: 0 changed: 0 step 181 100000000000000000000000000000000001111100011011011010100110100101 source: ; toggle phase should toggle RWB 2 source: 0 0 changed: 0 0 step 182 100000000000000000000000000000000001111100011011011010100110000001 source: 1 1 changed: 1 1 step 183 100000000000000000000000000000000001111100011011011010100110100101 source: source: ; shift in 0, expect 00 source: 0 changed: step 184 100000000000000000000000000000000001111100011011011010100110100101 source: 100 changed: 10 step 185 100000000000000000000000000000000001111100011011011010100110101001 source: 0 changed: 0 step 186 100000000000000000000000000000000001111100011011011010100110100001 source: ; toggle phase should toggle RWB 2 source: 0 1 changed: 0 1 step 187 100000000000000000000000000000000001111100011011011010100110000101 source: 1 0 changed: 1 0 step 188 100000000000000000000000000000000001111100011011011010100110100001 source: source: ; shift in 0, expect 00 source: 0 changed: step 189 100000000000000000000000000000000001111100011011011010100110100001 source: 100 changed: 1 step 190 100000000000000000000000000000000001111100011011011010100110101001 source: 0 changed: 0 step 191 100000000000000000000000000000000001111100011011011010100110100001 source: ; shift in 1, expect 01 source: 1 changed: 1 step 192 100000000000000000000000000000000001111100011011011010100110110001 source: 101 changed: 1 1 step 193 100000000000000000000000000000000001111100011011011010100110111011 source: 0 changed: 0 step 194 100000000000000000000000000000000001111100011011011010100110110011 source: ; shift in 1, expect 11 source: 1 changed: step 195 100000000000000000000000000000000001111100011011011010100110110011 source: 111 changed: 11 step 196 100000000000000000000000000000000001111100011011011010100110111111 source: 0 changed: 0 step 197 100000000000000000000000000000000001111100011011011010100110110111 source: ; shift in 1, expect 11 source: 1 changed: step 198 100000000000000000000000000000000001111100011011011010100110110111 source: 111 changed: 1 step 199 100000000000000000000000000000000001111100011011011010100110111111 source: 0 changed: 0 step 200 100000000000000000000000000000000001111100011011011010100110110111 source: ; shift in 0, expect 10 source: 0 changed: 0 step 201 100000000000000000000000000000000001111100011011011010100110100111 source: 110 changed: 1 0 step 202 100000000000000000000000000000000001111100011011011010100110101101 source: 0 changed: 0 step 203 100000000000000000000000000000000001111100011011011010100110100101 source: ; shift in 1, expect 01 source: 1 changed: 1 step 204 100000000000000000000000000000000001111100011011011010100110110101 source: 101 changed: 101 step 205 100000000000000000000000000000000001111100011011011010100110111011 source: 0 changed: 0 step 206 100000000000000000000000000000000001111100011011011010100110110011 source: ; shift in 0, expect 10 source: 0 changed: 0 step 207 100000000000000000000000000000000001111100011011011010100110100011 source: 110 changed: 110 step 208 100000000000000000000000000000000001111100011011011010100110101101 source: 0 changed: 0 step 209 100000000000000000000000000000000001111100011011011010100110100101 source: ; shift in 1, expect 01 source: 1 changed: 1 step 210 100000000000000000000000000000000001111100011011011010100110110101 source: 101 changed: 101 step 211 100000000000000000000000000000000001111100011011011010100110111011 source: 0 changed: 0 step 212 100000000000000000000000000000000001111100011011011010100110110011 source: ; shift in 1, expect 11 source: 1 changed: step 213 100000000000000000000000000000000001111100011011011010100110110011 source: 111 changed: 11 step 214 100000000000000000000000000000000001111100011011011010100110111111 source: 0 changed: 0 step 215 100000000000000000000000000000000001111100011011011010100110110111 source: ; no change source: 100000000000000000000000000000000001111100011011011010100110110111 changed: step 216 100000000000000000000000000000000001111100011011011010100110110111 test 22: pass SLOT BAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBAABBAAAAAAAAAAAAAABBBBBABBBB LETTER ALPSLFMDEEMCBFRSPKLEMFHRSCJLJKUHPNMBBNNVVRKRHUTDJUKANJHBTPDFSVEVDU SIDE 121212122121212121111111112212122222112222111221112112212112212122 DIRECTION IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIOOOOOOOIOOIOOIOOIOOOOIOOIIIIOOO this fail all fails was hi 111111111111111111111111111111111111111111111111111111111111111111 rising ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ ^^^^^^^^^^^^^^^^^^^^^^^^^ falling vvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvv vvvvvvvvvvvvvvvvvvvvvvvvv was lo 00000000000000000000000000000000000000 0000000000000000000000000 total fails 0, total passes 22 space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C toggle comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit run, stop on fail, no print ppppppppppppppppppppppppppppppppp space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C toggle comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit scope (run, no print) pppppppppppppppppppppppppp ppppppp space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C toggle comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT BAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBAABBAAAAAAAAAAAAAABBBBBABBBB LETTER ALPSLFMDEEMCBFRSPKLEMFHRSCJLJKUHPNMBBNNVVRKRHUTDJUKANJHBTPDFSVEVDU SIDE 121212122121212121111111112212122222112222111221112112212112212122 DIRECTION IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIOOOOOOOIOOIOOIOOIOOOOIOOIIIIOOO all fails was lo 00000000000000000000000000000000000000 0000000000000000000000000 falling vvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvv vvvvvvvvvvvvvvvvvvvvvvvvv rising ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ ^^^^^^^^^^^^^^^^^^^^^^^^^ was hi 111111111111111111111111111111111111111111111111111111111111111111 total fails 0, total passes 88 Main menu Thu Aug 20 18:59:43 2015 test file is: tests\m222.new delay is: 0 trigger is: 1 1 read test file 2 set test delay 3 set test trigger 4 run test 5 output loading test 8 diags 9 exit ***************************** UUT power is OFF * ***************************** Main menu Thu Aug 20 19:00:09 2015 test file is: tests\m222.new delay is: 0 trigger is: 1 1 read test file 2 set test delay 3 set test trigger 4 run test 5 output loading test 8 diags 9 exit key is 0x0073 Main menu Thu Aug 20 19:00:10 2015 test file is: tests\m222.new delay is: 0 trigger is: 1 1 read test file 2 set test delay 3 set test trigger 4 run test 5 output loading test 8 diags 9 exit UUT power is okay Thu Aug 20 19:00:15 2015 space single step O run once (one test, all steps) F run, stop on fail G go (run tests N run, stop on fail, no print S scope (run, no print) C toggle comment printout + increase speed (less delay) - decrease speed (more delay)(slower) Q quit test scope (run, no print) ppppppppppppppppppppppppppppppppppppppppppppppppppppppp space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C toggle comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT BAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBAABBAAAAAAAAAAAAAABBBBBABBBB LETTER ALPSLFMDEEMCBFRSPKLEMFHRSCJLJKUHPNMBBNNVVRKRHUTDJUKANJHBTPDFSVEVDU SIDE 121212122121212121111111112212122222112222111221112112212112212122 DIRECTION IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIOOOOOOOIOOIOOIOOIOOOOIOOIIIIOOO all fails was lo 00000000000000000000000000000000000000 0000000000000000000000000 falling vvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvv vvvvvvvvvvvvvvvvvvvvvvvvv rising ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ ^^^^^^^^^^^^^^^^^^^^^^^^^ was hi 111111111111111111111111111111111111111111111111111111111111111111 total fails 0, total passes 55 Main menu Thu Aug 20 19:00:39 2015 test file is: tests\m222.new delay is: 0 trigger is: 1 1 read test file 2 set test delay 3 set test trigger 4 run test 5 output loading test 8 diags 9 exit ***************************** UUT power is OFF * ***************************** Main menu Thu Aug 20 19:00:40 2015 test file is: tests\m222.new delay is: 0 trigger is: 1 1 read test file 2 set test delay 3 set test trigger 4 run test 5 output loading test 8 diags 9 exit key is 0x0073 Main menu Thu Aug 20 19:00:41 2015 test file is: tests\m222.new delay is: 0 trigger is: 1 1 read test file 2 set test delay 3 set test trigger 4 run test 5 output loading test 8 diags 9 exit UUT power is okay Thu Aug 20 19:00:43 2015 space single step O run once (one test, all steps) F run, stop on fail G go (run tests N run, stop on fail, no print S scope (run, no print) C toggle comment printout + increase speed (less delay) - decrease speed (more delay)(slower) Q quit test scope (run, no print) ppppppFpppppppppppppppppppppppppppppppppppppppppppppppppppppppp space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C toggle comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT BAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBAABBAAAAAAAAAAAAAABBBBBABBBB LETTER ALPSLFMDEEMCBFRSPKLEMFHRSCJLJKUHPNMBBNNVVRKRHUTDJUKANJHBTPDFSVEVDU SIDE 121212122121212121111111112212122222112222111221112112212112212122 DIRECTION IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIOOOOOOOIOOIOOIOOIOOOOIOOIIIIOOO all fails I II I O O O was lo 00000000000000000000000000000000000000 00000000000000000000000000 falling vvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvv vvvvvvvvvvvvvvvvvvvvvvvvvv rising ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ ^^^^^^^^^^^^^^^^^^^^^^^^^^ was hi 111111111111111111111111111111111111111111111111111111111111111111 total fails 1, total passes 62 Main menu Thu Aug 20 19:00:52 2015 test file is: tests\m222.new delay is: 0 trigger is: 1 1 read test file 2 set test delay 3 set test trigger 4 run test 5 output loading test 8 diags 9 exit UUT power is okay Thu Aug 20 19:01:07 2015 space single step O run once (one test, all steps) F run, stop on fail G go (run tests N run, stop on fail, no print S scope (run, no print) C toggle comment printout + increase speed (less delay) - decrease speed (more delay)(slower) Q quit test scope (run, no print) pppppppppppppppFppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppp ppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppp ppppp space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C toggle comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT BAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBAABBAAAAAAAAAAAAAABBBBBABBBB LETTER ALPSLFMDEEMCBFRSPKLEMFHRSCJLJKUHPNMBBNNVVRKRHUTDJUKANJHBTPDFSVEVDU SIDE 121212122121212121111111112212122222112222111221112112212112212122 DIRECTION IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIOOOOOOOIOOIOOIOOIOOOOIOOIIIIOOO all fails I I I O O was lo 00000000000000000000000000000000000000 0000000000000000000000000 falling vvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvv vvvvvvvvvvvvvvvvvvvvvvvvv rising ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ ^^^^^^^^^^^^^^^^^^^^^^^^^ was hi 111111111111111111111111111111111111111111111111111111111111111111 total fails 1, total passes 162 Main menu Thu Aug 20 19:01:27 2015 test file is: tests\m222.new delay is: 0 trigger is: 1 1 read test file 2 set test delay 3 set test trigger 4 run test 5 output loading test 8 diags 9 exit exiting tester- PDP8 card tester via printer port version 0.85 June 4, 2015 mapping[] is verified Main menu Sun Aug 23 15:09:13 2015 test file is: delay is: 0 trigger is: 1 1 read test file 2 set test delay 3 set test trigger 4 run test 5 output loading test 8 diags 9 exit exiting