tester- PDP8 card tester via printer port version 0.90 September 13, 2015 mapping[] is verified Main menu Sun Nov 22 18:42:57 2015 test file is: delay is: 0 trigger is: 1 1 read test file 2 set test delay 3 set test trigger 4 run test 5 output loading test 8 diags 9 exit Enter test file name? trying to open test file: tests\m7102_1.tst reading test file: tests\m7102_1.tst comment: M7102 PCB REV D SCHEMATIC REV C Positive I/O Bus Converter (DW08E) comment: comment: PART 1 Tests Posibus driving Omnibus DATA BUS. comment: (See PART 2 for Omnibus driving Posibus. comment: comment: (Two parts are necessary due to the Omnibus DATA00:02-N is a bidirectional bus). comment: comment: Needs 3.3k ohm pullups to +5v on pin: comment: BK2 Omnibus DATA00 (bidirectional, input + open collector output) comment: BL2 Omnibus DATA01 (bidirectional, input + open collector output) comment: BM2 Omnibus DATA02 (bidirectional, input + open collector output) comment: pins: PINS pins: 1 I AN1 E6-9 INPUT 1 pins: 2 P BF2 E13-8 OUTPUT A-N (7416 OPEN COLLECTOR OUTPUT) pins: 3 I AP1 E6-6 INPUT 2 pins: 4 P BH2 E13-7 OUTPUT 2-N (7416 OPEN COLLECTOR OUTPUT) pins: 5 I AR1 E6-5 INPUT 3 pins: 6 P BJ2 E13-6 OUTPUT 3-N (7416 OPEN COLLECTOR OUTPUT) pins: 7 I AK2 E9-11 INPUT 4 pins: 8 O AN2 E9-13 OUTPUT 4 (384 OUTPUT) pins: 9 I AL2 E9-9 INPUT 5 pins: 10 O AM2 E9-14 OUTPUT 5 (384 OUTPUT) pins: 11 I AP2 E9-6 INPUT 6 pins: 12 O AT2 E9-2 OUTPUT 6 (384 OUTPUT) pins: 13 O BB1 E11-6 OUTPUT 6-N (74H04 OUTPUT) pins: 14 I AR2 E9-5 INPUT 7 pins: 15 O AS2 E9-3 OUTPUT 7 (384 OUTPUT) pins: 16 O BA1 E11-10 OUTPUT 7-N (74H04 OUTPUT) pins: 17 I BD1 E11-1 INPUT 8 pins: 18 P BV2 E13-12 OUTPUT 8 (7416 OPEN COLLECTOR OUTPUT) pins: 19 O BC1 E11-2 OUTPUT 8-N (74H04 OUTPUT) pins: 20 I AV1 E11-13 INPUT 9 pins: 21 O AU1 E11-12 OUTPUT 9-N (74H04 OUTPUT) pins: 22 I BL1 E12-4 INPUT 10A pins: 23 I BK1 E12-5 INPUT 10B pins: 24 O BM1 E12-3 OUTPUT 10 = INPUT 10A NOR INPUT 10B (380 OUTPUT) pins: 25 I BJ1 E12-9 INPUT 11A pins: 26 I BH1 E12-10 INPUT 11B pins: 27 O BF1 E12-14 OUTPUT 11 = INPUT 11A NOR INPUT 11B (M380 OUTPUT) pins: 28 I BR1 E15-12 INPUT 12A pins: 29 I BS1 E15-11 INPUT 12B pins: 30 O BP1 E15-? OUTPUT 12 = INPUT 12A NAND INPUT 12B (8881 OPEN COLLECTOR OUTPUT WITH 3.3K PULLUP) pins: 31 I BN2 E10-6,7 INPUT 13 pins: 32 P AD1 E1-3 OUTPUT 13 (75452 OPEN COLLECTOR OUTPUT) pins: 33 I BP2 E14-11,12 INPUT 14 pins: 34 P AE1 E2-3 OUTPUT 14 (75452 OPEN COLLECTOR OUTPUT) pins: 35 I BR2 E14-9,10 INPUT 15 pins: 36 P AD2 E5-5 OUTPUT 15 (75452 OPEN COLLECTOR OUTPUT) pins: 37 I BS2 E14-6,7 INPUT 16 pins: 38 P AE2 E4-5 OUTPUT 16 (75452 OPEN COLLECTOR OUTPUT) pins: 39 I BU1 E14-4,5 INPUT 17 pins: 40 P AB1 E4-5 OUTPUT 17 (75452 OPEN COLLECTOR OUTPUT) pins: 41 O BU2 E14-3 OUTPUT 17-N (380 OUTPUT) pins: 42 I BV1 E2-6,7 INPUT 18 pins: 43 P AA1 E2-5 OUTPUT 18-N (75452 OPEN COLLECTOR OUTPUT) pins: 44 I BD2 E11-3 OMNIBUS DATA TO I/O DATA-N (LOW ALSO DISABLES BAC <> OMNIBUS) pins: 45 O BE1 E11-4 OMNIBUS DATA TO I/O DATA (74H04 OUTPUT) pins: 46 I BE2 E12-12 INPUT OUT-N (L -> BAC TO OMNIBUS, H -> OMNIBUS TO BAC) pins: 47 I AK1 E3-6 INPUT BAC0 (DATA FROM I/O BUS) pins: 48 I AL1 E3-5 INPUT BAC1 (DATA FROM I/O BUS) pins: 49 I AM1 E6-11 INPUT BAC2 (DATA FROM I/O BUS) pins: 50 O BK2 E15-1 OUTPUT DATA00-N (OMNIBUS DATA00) (8881 OPEN COLLECTOR OUTPUT) pins: 51 O BL2 E15-4 OUTPUT DATA01-N (OMNIBUS DATA01) (8881 OPEN COLLECTOR OUTPUT) pins: 52 O BM2 E15-10 OUTPUT DATA02-N (OMNIBUS DATA02) (8881 OPEN COLLECTOR OUTPUT) pins: 53 P AF1 E4-3 OUTPUT I/O BUS ACIN0-N (75452 OPEN COLLECTOR OUTPUT) pins: 54 P AH1 E5-3 OUTPUT I/O BUS ACIN1-N (75452 OPEN COLLECTOR OUTPUT) pins: 55 P AJ1 E8-5 OUTPUT I/O BUS ACIN2-N (75452 OPEN COLLECTOR OUTPUT) pins: 56 P AF2 E7-5 OUTPUT I/O BUS DATA0-N (75452 OPEN COLLECTOR OUTPUT) pins: 57 P AH2 E3-3 OUTPUT I/O BUS DATA1-N (75452 OPEN COLLECTOR OUTPUT) pins: 58 P AJ2 E7-3 OUTPUT I/O BUS DATA2-N (75452 OPEN COLLECTOR OUTPUT) pins: direction: IPIPIPIOIOIOOIOOIPOIOIIOIIOIIOIPIPIPIPIPOIPIOIIIIOOOPPPPPP test 1: 0101010000001001001010010010010000000000101010000111111111 comment: comment: ; INPUT 1 -> OUTPUT 1-N test 2: 10 test 3: 01 comment: comment: ; INPUT 2 -> OUTPUT 2-N test 4: 10 test 5: 01 comment: comment: ; INPUT 3 -> OUTPUT 3-N test 6: 10 test 7: 01 comment: comment: ; INPUT 4 -> OUTPUT 4 test 8: 11 test 9: 00 comment: comment: ; INPUT 5 -> OUTPUT 5 test 10: 11 test 11: 00 comment: comment: ; INPUT 6 -> OUTPUT 6, OUTPUT 6-N test 12: 110 test 13: 001 comment: comment: ; INPUT 7 -> OUTPUT 7, OUTPUT 7-N test 14: 110 test 15: 001 comment: comment: ; INPUT 8 -> OUTPUT 8, OUTPUT 8-N test 16: 110 test 17: 001 comment: comment: ; INPUT 9 -> OOUTPUT 9-N test 18: 10 test 19: 01 comment: comment: ; INPUT 10A NOR INPUT 10B -> OUTPUT 10 test 20: 010 test 21: 110 test 22: 100 test 23: 001 comment: comment: ; INPUT 11A NOR INPUT 11B -> OUTPUT 11 test 24: 010 test 25: 110 test 26: 100 test 27: 001 comment: comment: ; INPUT 12A NAND INPUT 12B -> OUTPUT 12 test 28: 011 test 29: 110 test 30: 101 test 31: 001 comment: comment: ; INPUT 13 -> OUTPUT 13 test 32: 11 test 33: 00 comment: comment: ; INPUT 14 -> OUTPUT 14 test 34: 11 test 35: 00 comment: comment: ; INPUT 15 -> OUTPUT 15 test 36: 11 test 37: 00 comment: comment: ; INPUT 16 -> OUTPUT 16 test 38: 11 test 39: 00 comment: comment: ; INPUT 17 -> OUTPUT 17, OUTPUT 17-N test 40: 110 test 41: 001 comment: comment: ; INPUT 18 -> OUTPUT 18-N test 42: 10 test 43: 01 comment: comment: ; (no change) test 44: 0101010000001001001010010010010000000000101010000111111111 comment: comment: comment: comment: ; PART 1 unique tests (Posibus BAC0:2 driving Omnibus DATA00:02-N). comment: comment: ; (See PART 2 for Omnibus DATA00:02-N driving). comment: comment: comment: comment: ; Select Omnibus DATA00:02-N -> Posibus DATA0:2-N comment: comment: ; OMNIBUS DATA TO I/O DATA-N LO, OUT-N HI; OMNIBUS DATA TO I/O DATA -> HI test 45: 011 comment: ; (no change) test 46: 000111111111 comment: comment: ; All BAC0:2 patterns (Omnibus DATA00:02-N, Posibus ACIN0:2-N, Posibus DATA0:2-N always HI). comment: ; (Omnibus DATA00:02-N always high due to pullups and no drivers in PART 1 tests) test 47: 001 test 48: 011 test 49: 010 test 50: 110 test 51: 111 test 52: 101 test 53: 100 test 54: 000 comment: comment: comment: comment: ; Select Omnibus DATA00:02-N -> PosiBus ACIN0:2-N comment: comment: ; OMNIBUS DATA TO I/O DATA-N HI, OUT-N HI; OMNIBUS DATA TO I/O DATA -> LO test 55: 101 comment: ; (no change) test 56: 000111111111 comment: comment: ; All BAC0:2 patterns (Omnibus DATA00:02-N, Posibus ACIN0:2-N, Posibus DATA0:2-N always HI). comment: ; (Omnibus DATA00:02-N always high due to pullups and no drivers in PART 1 tests) test 57: 001 test 58: 011 test 59: 010 test 60: 110 test 61: 111 test 62: 101 test 63: 100 test 64: 000 comment: comment: comment: comment: ; Select Posibus BAC0:2 -> Omnibus DATA00:02-N comment: comment: ; OMNIBUS DATA TO I/O DATA-N HI, OUT-N LO; OMNIBUS DATA TO I/O DATA -> LO test 65: 100 comment: ; (no change) test 66: 000111111111 comment: comment: ; All BAC0:2 patterns (PosibusACIN0:2-N and Posibus DATA0:2-N always HI). test 67: 001110 test 68: 011100 test 69: 010101 test 70: 110001 test 71: 111000 test 72: 101010 test 73: 100011 test 74: 000111 comment: comment: comment: comment: ; Select Omnibus DATA00:02-N -> Posibus DATA0:2-N comment: comment: ; OMNIBUS DATA TO I/O DATA-N LO, OUT-N LO; OMNIBUS DATA TO I/O DATA -> HI test 75: 010 comment: ; (no change) test 76: 000111111111 comment: comment: ; All BAC0:2 patterns (Omnibus DATA00:02-N, Posibus ACIN0:2-N, Posibus DATA0:2-N always HI). comment: ; (Omnibus DATA00:02-N always high due to pullups and no drivers in PART 1 tests) test 77: 001 test 78: 011 test 79: 010 test 80: 110 test 81: 111 test 82: 101 test 83: 100 test 84: 000 test 85: comment: ; (no change) test 86: 0101010000001001001010010010010000000000101010000111111111 end: END summary column 1: offset 1, mask 0x1000 column 2: offset 2, mask 0x0080 column 3: offset 1, mask 0x0800 column 4: offset 3, mask 0x0001 column 5: offset 1, mask 0x0400 column 6: offset 3, mask 0x0002 column 7: offset 1, mask 0x0001 column 8: offset 1, mask 0x0008 column 9: offset 1, mask 0x0002 column 10: offset 1, mask 0x0004 column 11: offset 1, mask 0x0010 column 12: offset 1, mask 0x0080 column 13: offset 2, mask 0x1000 column 14: offset 1, mask 0x0020 column 15: offset 1, mask 0x0040 column 16: offset 2, mask 0x2000 column 17: offset 2, mask 0x0400 column 18: offset 4, mask 0x0008 column 19: offset 2, mask 0x0800 column 20: offset 2, mask 0x4000 column 21: offset 2, mask 0x8000 column 22: offset 3, mask 0x1000 column 23: offset 3, mask 0x2000 column 24: offset 3, mask 0x0800 column 25: offset 3, mask 0x4000 column 26: offset 3, mask 0x8000 column 27: offset 2, mask 0x0100 column 28: offset 3, mask 0x0100 column 29: offset 4, mask 0x8000 column 30: offset 3, mask 0x0200 column 31: offset 3, mask 0x0020 column 32: offset 0, mask 0x1000 column 33: offset 3, mask 0x0040 column 34: offset 0, mask 0x0800 column 35: offset 3, mask 0x0080 column 36: offset 0, mask 0x0010 column 37: offset 4, mask 0x0001 column 38: offset 0, mask 0x0008 column 39: offset 4, mask 0x2000 column 40: offset 0, mask 0x4000 column 41: offset 4, mask 0x0004 column 42: offset 4, mask 0x1000 column 43: offset 0, mask 0x8000 column 44: offset 2, mask 0x0020 column 45: offset 2, mask 0x0200 column 46: offset 2, mask 0x0040 column 47: offset 1, mask 0x8000 column 48: offset 1, mask 0x4000 column 49: offset 1, mask 0x2000 column 50: offset 3, mask 0x0004 column 51: offset 3, mask 0x0008 column 52: offset 3, mask 0x0010 column 53: offset 0, mask 0x0400 column 54: offset 0, mask 0x0200 column 55: offset 0, mask 0x0100 column 56: offset 0, mask 0x0004 column 57: offset 0, mask 0x0002 column 58: offset 0, mask 0x0001 direction bits (1=input) 0xFFFF 0x03CC 0xBB9B 0x0E1F 0x40FE pullup bits (1=pullup) 0xDF1F 0x0000 0x0080 0x0003 0x0008 test step out_data dont care 1: 0x8707 0x0000 0xBB80 0x0A1F 0x0004 2: 0x8707 0x1000 0xBB00 0x0A1F 0x0004 3: 0x8707 0x0000 0xBB80 0x0A1F 0x0004 4: 0x8707 0x0800 0xBB80 0x0A1E 0x0004 5: 0x8707 0x0000 0xBB80 0x0A1F 0x0004 6: 0x8707 0x0400 0xBB80 0x0A1D 0x0004 7: 0x8707 0x0000 0xBB80 0x0A1F 0x0004 8: 0x8707 0x0009 0xBB80 0x0A1F 0x0004 9: 0x8707 0x0000 0xBB80 0x0A1F 0x0004 10: 0x8707 0x0006 0xBB80 0x0A1F 0x0004 11: 0x8707 0x0000 0xBB80 0x0A1F 0x0004 12: 0x8707 0x0090 0xAB80 0x0A1F 0x0004 13: 0x8707 0x0000 0xBB80 0x0A1F 0x0004 14: 0x8707 0x0060 0x9B80 0x0A1F 0x0004 15: 0x8707 0x0000 0xBB80 0x0A1F 0x0004 16: 0x8707 0x0000 0xB780 0x0A1F 0x000C 17: 0x8707 0x0000 0xBB80 0x0A1F 0x0004 18: 0x8707 0x0000 0x7B80 0x0A1F 0x0004 19: 0x8707 0x0000 0xBB80 0x0A1F 0x0004 20: 0x8707 0x0000 0xBB80 0x221F 0x0004 21: 0x8707 0x0000 0xBB80 0x321F 0x0004 22: 0x8707 0x0000 0xBB80 0x121F 0x0004 23: 0x8707 0x0000 0xBB80 0x0A1F 0x0004 24: 0x8707 0x0000 0xBA80 0x8A1F 0x0004 25: 0x8707 0x0000 0xBA80 0xCA1F 0x0004 26: 0x8707 0x0000 0xBA80 0x4A1F 0x0004 27: 0x8707 0x0000 0xBB80 0x0A1F 0x0004 28: 0x8707 0x0000 0xBB80 0x0A1F 0x8004 29: 0x8707 0x0000 0xBB80 0x091F 0x8004 30: 0x8707 0x0000 0xBB80 0x0B1F 0x0004 31: 0x8707 0x0000 0xBB80 0x0A1F 0x0004 32: 0x9707 0x0000 0xBB80 0x0A3F 0x0004 33: 0x8707 0x0000 0xBB80 0x0A1F 0x0004 34: 0x8F07 0x0000 0xBB80 0x0A5F 0x0004 35: 0x8707 0x0000 0xBB80 0x0A1F 0x0004 36: 0x8717 0x0000 0xBB80 0x0A9F 0x0004 37: 0x8707 0x0000 0xBB80 0x0A1F 0x0004 38: 0x870F 0x0000 0xBB80 0x0A1F 0x0005 39: 0x8707 0x0000 0xBB80 0x0A1F 0x0004 40: 0xC707 0x0000 0xBB80 0x0A1F 0x2000 41: 0x8707 0x0000 0xBB80 0x0A1F 0x0004 42: 0x0707 0x0000 0xBB80 0x0A1F 0x1004 43: 0x8707 0x0000 0xBB80 0x0A1F 0x0004 44: 0x8707 0x0000 0xBB80 0x0A1F 0x0004 45: 0x8707 0x0000 0xBBC0 0x0A1F 0x0004 46: 0x8707 0x0000 0xBBC0 0x0A1F 0x0004 47: 0x8707 0x2000 0xBBC0 0x0A1F 0x0004 48: 0x8707 0x6000 0xBBC0 0x0A1F 0x0004 49: 0x8707 0x4000 0xBBC0 0x0A1F 0x0004 50: 0x8707 0xC000 0xBBC0 0x0A1F 0x0004 51: 0x8707 0xE000 0xBBC0 0x0A1F 0x0004 52: 0x8707 0xA000 0xBBC0 0x0A1F 0x0004 53: 0x8707 0x8000 0xBBC0 0x0A1F 0x0004 54: 0x8707 0x0000 0xBBC0 0x0A1F 0x0004 55: 0x8707 0x0000 0xB9E0 0x0A1F 0x0004 56: 0x8707 0x0000 0xB9E0 0x0A1F 0x0004 57: 0x8707 0x2000 0xB9E0 0x0A1F 0x0004 58: 0x8707 0x6000 0xB9E0 0x0A1F 0x0004 59: 0x8707 0x4000 0xB9E0 0x0A1F 0x0004 60: 0x8707 0xC000 0xB9E0 0x0A1F 0x0004 61: 0x8707 0xE000 0xB9E0 0x0A1F 0x0004 62: 0x8707 0xA000 0xB9E0 0x0A1F 0x0004 63: 0x8707 0x8000 0xB9E0 0x0A1F 0x0004 64: 0x8707 0x0000 0xB9E0 0x0A1F 0x0004 65: 0x8707 0x0000 0xB9A0 0x0A1F 0x0004 66: 0x8707 0x0000 0xB9A0 0x0A1F 0x0004 67: 0x8707 0x2000 0xB9A0 0x0A0F 0x0004 68: 0x8707 0x6000 0xB9A0 0x0A07 0x0004 69: 0x8707 0x4000 0xB9A0 0x0A17 0x0004 70: 0x8707 0xC000 0xB9A0 0x0A13 0x0004 71: 0x8707 0xE000 0xB9A0 0x0A03 0x0004 72: 0x8707 0xA000 0xB9A0 0x0A0B 0x0004 73: 0x8707 0x8000 0xB9A0 0x0A1B 0x0004 74: 0x8707 0x0000 0xB9A0 0x0A1F 0x0004 75: 0x8707 0x0000 0xBB80 0x0A1F 0x0004 76: 0x8707 0x0000 0xBB80 0x0A1F 0x0004 77: 0x8707 0x2000 0xBB80 0x0A1F 0x0004 78: 0x8707 0x6000 0xBB80 0x0A1F 0x0004 79: 0x8707 0x4000 0xBB80 0x0A1F 0x0004 80: 0x8707 0xC000 0xBB80 0x0A1F 0x0004 81: 0x8707 0xE000 0xBB80 0x0A1F 0x0004 82: 0x8707 0xA000 0xBB80 0x0A1F 0x0004 83: 0x8707 0x8000 0xBB80 0x0A1F 0x0004 84: 0x8707 0x0000 0xBB80 0x0A1F 0x0004 85: 0x8707 0x0000 0xBB80 0x0A1F 0x0004 86: 0x8707 0x0000 0xBB80 0x0A1F 0x0004 PINs used (in edge connector order) (G=ground,P=power) SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBB LETTER ABCDEFHJKLMNPRSTUVABCDEFHJKLMNPRSTUVABCDEFHJKLMNPRSTUVABCDEFHJKLMNPRSTUV SIDE 111111111111111111222222222222222222111111111111111111222222222222222222 USAGE PP PPPPPIIIIII GOIP GPPPPPIIOOIIOO OOOIOOIIIIO OIIGIIP GIIPPPOOOIIII OP UUT inputs: 26 UUT outputs: 32 pins used: 58 not used: 8 86 'test steps' 244 lines M7102 PCB REV D SCHEMATIC REV C Positive I/O Bus Converter (DW08E) PART 1 Tests Posibus driving Omnibus DATA BUS. (See PART 2 for Omnibus driving Posibus. (Two parts are necessary due to the Omnibus DATA00:02-N is a bidirectional bus). Needs 3.3k ohm pullups to +5v on pin: BK2 Omnibus DATA00 (bidirectional, input + open collector output) BL2 Omnibus DATA01 (bidirectional, input + open collector output) BM2 Omnibus DATA02 (bidirectional, input + open collector output) PINS Main menu Sun Nov 22 18:43:06 2015 test file is: tests\m7102_1.tst delay is: 0 trigger is: 1 1 read test file 2 set test delay 3 set test trigger 4 run test 5 output loading test 8 diags 9 exit UUT power is okay Sun Nov 22 18:43:07 2015 space single step O run once (one test, all steps) F run, stop on fail G go (run tests N run, stop on fail, no print S scope (run, no print) C toggle comment printout + increase speed (less delay) - decrease speed (more delay)(slower) Q quit test scope (run, no print) pppppppppppppppppppppppppppppppppppppppppppppppppppp space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C toggle comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT ABABABAAAAAABAABBBBAABBBBBBBBBBABABABABABBABBBAAABBBAAAAAA LETTER NFPHRJKNLMPTBRSADVCVULKMJHFRSPNDPERDSEUBUVADEEKLMKLMFHJFHJ SIDE 1212122222221221121111111111112121222211211212111222111222 DIRECTION IPIPIPIOIOIOOIOOIPOIOIIOIIOIIOIPIPIPIPIPOIPIOIIIIOOOPPPPPP all fails was lo 0000000000000000000000000000000000000000000000000000 falling vvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvv rising ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ was hi 1111111111111111111111111111111111111111111111111111111111 total fails 0, total passes 52 Main menu Sun Nov 22 18:43:12 2015 test file is: tests\m7102_1.tst delay is: 0 trigger is: 1 1 read test file 2 set test delay 3 set test trigger 4 run test 5 output loading test 8 diags 9 exit Enter test file name? trying to open test file: tests\m7102_2.tst reading test file: tests\m7102_2.tst comment: M7102 PCB REV D SCHEMATIC REV C Positive I/O Bus Converter (DW08E) comment: comment: PART 2 Tests Omnibus DATA BUS driving Posibus ACIN and DATA. comment: (See PART 1 for Posibus driving Omnibus. comment: comment: (Two parts are necessary due to the Omnibus DATA00:02-N is a bidirectional bus). comment: comment: Tolerates 3.3k ohm pullups to +5v on pin (are needed for PART 1): comment: BK2 Omnibus DATA00 (bidirectional, input + open collector output) comment: BL2 Omnibus DATA01 (bidirectional, input + open collector output) comment: BM2 Omnibus DATA02 (bidirectional, input + open collector output) comment: pins: PINS pins: 1 I AN1 E6-9 INPUT 1 pins: 2 P BF2 E13-8 OUTPUT A-N (7416 OPEN COLLECTOR OUTPUT) pins: 3 I AP1 E6-6 INPUT 2 pins: 4 P BH2 E13-7 OUTPUT 2-N (7416 OPEN COLLECTOR OUTPUT) pins: 5 I AR1 E6-5 INPUT 3 pins: 6 P BJ2 E13-6 OUTPUT 3-N (7416 OPEN COLLECTOR OUTPUT) pins: 7 I AK2 E9-11 INPUT 4 pins: 8 O AN2 E9-13 OUTPUT 4 (384 OUTPUT) pins: 9 I AL2 E9-9 INPUT 5 pins: 10 O AM2 E9-14 OUTPUT 5 (384 OUTPUT) pins: 11 I AP2 E9-6 INPUT 6 pins: 12 O AT2 E9-2 OUTPUT 6 (384 OUTPUT) pins: 13 O BB1 E11-6 OUTPUT 6-N (74H04 OUTPUT) pins: 14 I AR2 E9-5 INPUT 7 pins: 15 O AS2 E9-3 OUTPUT 7 (384 OUTPUT) pins: 16 O BA1 E11-10 OUTPUT 7-N (74H04 OUTPUT) pins: 17 I BD1 E11-1 INPUT 8 pins: 18 P BV2 E13-12 OUTPUT 8 (7416 OPEN COLLECTOR OUTPUT) pins: 19 O BC1 E11-2 OUTPUT 8-N (74H04 OUTPUT) pins: 20 I AV1 E11-13 INPUT 9 pins: 21 O AU1 E11-12 OUTPUT 9-N (74H04 OUTPUT) pins: 22 I BL1 E12-4 INPUT 10A pins: 23 I BK1 E12-5 INPUT 10B pins: 24 O BM1 E12-3 OUTPUT 10 = INPUT 10A NOR INPUT 10B (380 OUTPUT) pins: 25 I BJ1 E12-9 INPUT 11A pins: 26 I BH1 E12-10 INPUT 11B pins: 27 O BF1 E12-14 OUTPUT 11 = INPUT 11A NOR INPUT 11B (M380 OUTPUT) pins: 28 I BR1 E15-12 INPUT 12A pins: 29 I BS1 E15-11 INPUT 12B pins: 30 O BP1 E15-? OUTPUT 12 = INPUT 12A NAND INPUT 12B (8881 OPEN COLLECTOR OUTPUT WITH 3.3K PULLUP) pins: 31 I BN2 E10-6,7 INPUT 13 pins: 32 P AD1 E1-3 OUTPUT 13 (75452 OPEN COLLECTOR OUTPUT) pins: 33 I BP2 E14-11,12 INPUT 14 pins: 34 P AE1 E2-3 OUTPUT 14 (75452 OPEN COLLECTOR OUTPUT) pins: 35 I BR2 E14-9,10 INPUT 15 pins: 36 P AD2 E5-5 OUTPUT 15 (75452 OPEN COLLECTOR OUTPUT) pins: 37 I BS2 E14-6,7 INPUT 16 pins: 38 P AE2 E4-5 OUTPUT 16 (75452 OPEN COLLECTOR OUTPUT) pins: 39 I BU1 E14-4,5 INPUT 17 pins: 40 P AB1 E4-5 OUTPUT 17 (75452 OPEN COLLECTOR OUTPUT) pins: 41 O BU2 E14-3 OUTPUT 17-N (380 OUTPUT) pins: 42 I BV1 E2-6,7 INPUT 18 pins: 43 P AA1 E2-5 OUTPUT 18-N (75452 OPEN COLLECTOR OUTPUT) pins: 44 I BD2 E11-3 OMNIBUS DATA TO I/O DATA-N (LOW ALSO DISABLES BAC <> OMNIBUS) pins: 45 O BE1 E11-4 OMNIBUS DATA TO I/O DATA (74H04 OUTPUT) pins: 46 I BE2 E12-12 INPUT OUT-N (L -> BAC TO OMNIBUS, H -> OMNIBUS TO BAC) pins: 47 I AK1 E3-6 INPUT BAC0 (DATA FROM I/O BUS) pins: 48 I AL1 E3-5 INPUT BAC1 (DATA FROM I/O BUS) pins: 49 I AM1 E6-11 INPUT BAC2 (DATA FROM I/O BUS) pins: 50 I BK2 E15-1 INPUT DATA00-N (OMNIBUS DATA00) (8881 OPEN COLLECTOR OUTPUT) pins: 51 I BL2 E15-4 INPUT DATA01-N (OMNIBUS DATA01) (8881 OPEN COLLECTOR OUTPUT) pins: 52 I BM2 E15-10 INPUT DATA02-N (OMNIBUS DATA02) (8881 OPEN COLLECTOR OUTPUT) pins: 53 P AF1 E4-3 OUTPUT I/O BUS ACIN0-N (75452 OPEN COLLECTOR OUTPUT) pins: 54 P AH1 E5-3 OUTPUT I/O BUS ACIN1-N (75452 OPEN COLLECTOR OUTPUT) pins: 55 P AJ1 E8-5 OUTPUT I/O BUS ACIN2-N (75452 OPEN COLLECTOR OUTPUT) pins: 56 P AF2 E7-5 OUTPUT I/O BUS DATA0-N (75452 OPEN COLLECTOR OUTPUT) pins: 57 P AH2 E3-3 OUTPUT I/O BUS DATA1-N (75452 OPEN COLLECTOR OUTPUT) pins: 58 P AJ2 E7-3 OUTPUT I/O BUS DATA2-N (75452 OPEN COLLECTOR OUTPUT) pins: direction: IPIPIPIOIOIOOIOOIPOIOIIOIIOIIOIPIPIPIPIPOIPIOIIIIIIIPPPPPP test 1: 0101010000001001001010010010010000000000101010000111111111 comment: comment: ; INPUT 1 -> OUTPUT 1-N test 2: 10 test 3: 01 comment: comment: ; INPUT 2 -> OUTPUT 2-N test 4: 10 test 5: 01 comment: comment: ; INPUT 3 -> OUTPUT 3-N test 6: 10 test 7: 01 comment: comment: ; INPUT 4 -> OUTPUT 4 test 8: 11 test 9: 00 comment: comment: ; INPUT 5 -> OUTPUT 5 test 10: 11 test 11: 00 comment: comment: ; INPUT 6 -> OUTPUT 6, OUTPUT 6-N test 12: 110 test 13: 001 comment: comment: ; INPUT 7 -> OUTPUT 7, OUTPUT 7-N test 14: 110 test 15: 001 comment: comment: ; INPUT 8 -> OUTPUT 8, OUTPUT 8-N test 16: 110 test 17: 001 comment: comment: ; INPUT 9 -> OOUTPUT 9-N test 18: 10 test 19: 01 comment: comment: ; INPUT 10A NOR INPUT 10B -> OUTPUT 10 test 20: 010 test 21: 110 test 22: 100 test 23: 001 comment: comment: ; INPUT 11A NOR INPUT 11B -> OUTPUT 11 test 24: 010 test 25: 110 test 26: 100 test 27: 001 comment: comment: ; INPUT 12A NAND INPUT 12B -> OUTPUT 12 test 28: 011 test 29: 110 test 30: 101 test 31: 001 comment: comment: ; INPUT 13 -> OUTPUT 13 test 32: 11 test 33: 00 comment: comment: ; INPUT 14 -> OUTPUT 14 test 34: 11 test 35: 00 comment: comment: ; INPUT 15 -> OUTPUT 15 test 36: 11 test 37: 00 comment: comment: ; INPUT 16 -> OUTPUT 16 test 38: 11 test 39: 00 comment: comment: ; INPUT 17 -> OUTPUT 17, OUTPUT 17-N test 40: 110 test 41: 001 comment: comment: ; INPUT 18 -> OUTPUT 18-N test 42: 10 test 43: 01 comment: comment: ; (no change) test 44: 0101010000001001001010010010010000000000101010000111111111 comment: comment: comment: comment: ; PART 2 unique tests (Omnibus DATA00:02-N driving Posibus ACIN and DATA) comment: comment: ; (See PART 1 for Posibus driving Omnibus). comment: comment: comment: comment: ; Select Omnibus DATA00:02-N -> Posibus DATA0:2-N comment: comment: ; OMNIBUS DATA TO I/O DATA-N LO, OUT-N HI; OMNIBUS DATA TO I/O DATA -> HI test 45: 011 comment: ; (no change) test 46: 000111111111 comment: comment: ; All DATA00:02-N patterns (Posibus ACIN0:2-N always HI). test 47: 101 101 test 48: 100 100 test 49: 000 000 test 50: 001 001 test 51: 011 011 test 52: 010 010 test 53: 110 110 test 54: 111 111 comment: comment: comment: comment: ; Select Omnibus DATA00:02-N -> PosiBus ACIN0:2-N comment: comment: ; OMNIBUS DATA TO I/O DATA-N HI, OUT-N HI; OMNIBUS DATA TO I/O DATA -> LO test 55: 101 comment: ; (no change) test 56: 000111111111 comment: comment: ; All DATA00:02-N patterns (Posibus DATA0:2-N always HI). test 57: 101101 test 58: 100100 test 59: 000000 test 60: 001001 test 61: 011011 test 62: 010010 test 63: 110110 test 64: 111111 comment: comment: comment: ; Do not select Posibus BAC0:2 -> Omnibus DATA00:02-N comment: ; (we drive Omnibus DATA00:02-N in PART 2). comment: ; skip >>>>> 100 comment: comment: comment: comment: ; Select Omnibus DATA00:02-N -> Posibus DATA0:2-N comment: comment: ; Do 2 steps to avoid >>>>> 100 comment: ; OMNIBUS DATA TO I/O DATA-N LO, OUT-N HI; OMNIBUS DATA TO I/O DATA -> HI test 65: 011 comment: comment: ; OMNIBUS DATA TO I/O DATA-N LO, OUT-N LO; OMNIBUS DATA TO I/O DATA -> HI test 66: 010 comment: ; (no change) test 67: 000111111111 comment: comment: ; All DATA00:02-N patterns (Posibus ACIN0:2-N always HI). test 68: 101 101 test 69: 100 100 test 70: 000 000 test 71: 001 001 test 72: 011 011 test 73: 010 010 test 74: 110 110 test 75: 111 111 comment: comment: ; (no change) test 76: 0101010000001001001010010010010000000000101010000111111111 end: END summary column 1: offset 1, mask 0x1000 column 2: offset 2, mask 0x0080 column 3: offset 1, mask 0x0800 column 4: offset 3, mask 0x0001 column 5: offset 1, mask 0x0400 column 6: offset 3, mask 0x0002 column 7: offset 1, mask 0x0001 column 8: offset 1, mask 0x0008 column 9: offset 1, mask 0x0002 column 10: offset 1, mask 0x0004 column 11: offset 1, mask 0x0010 column 12: offset 1, mask 0x0080 column 13: offset 2, mask 0x1000 column 14: offset 1, mask 0x0020 column 15: offset 1, mask 0x0040 column 16: offset 2, mask 0x2000 column 17: offset 2, mask 0x0400 column 18: offset 4, mask 0x0008 column 19: offset 2, mask 0x0800 column 20: offset 2, mask 0x4000 column 21: offset 2, mask 0x8000 column 22: offset 3, mask 0x1000 column 23: offset 3, mask 0x2000 column 24: offset 3, mask 0x0800 column 25: offset 3, mask 0x4000 column 26: offset 3, mask 0x8000 column 27: offset 2, mask 0x0100 column 28: offset 3, mask 0x0100 column 29: offset 4, mask 0x8000 column 30: offset 3, mask 0x0200 column 31: offset 3, mask 0x0020 column 32: offset 0, mask 0x1000 column 33: offset 3, mask 0x0040 column 34: offset 0, mask 0x0800 column 35: offset 3, mask 0x0080 column 36: offset 0, mask 0x0010 column 37: offset 4, mask 0x0001 column 38: offset 0, mask 0x0008 column 39: offset 4, mask 0x2000 column 40: offset 0, mask 0x4000 column 41: offset 4, mask 0x0004 column 42: offset 4, mask 0x1000 column 43: offset 0, mask 0x8000 column 44: offset 2, mask 0x0020 column 45: offset 2, mask 0x0200 column 46: offset 2, mask 0x0040 column 47: offset 1, mask 0x8000 column 48: offset 1, mask 0x4000 column 49: offset 1, mask 0x2000 column 50: offset 3, mask 0x0004 column 51: offset 3, mask 0x0008 column 52: offset 3, mask 0x0010 column 53: offset 0, mask 0x0400 column 54: offset 0, mask 0x0200 column 55: offset 0, mask 0x0100 column 56: offset 0, mask 0x0004 column 57: offset 0, mask 0x0002 column 58: offset 0, mask 0x0001 direction bits (1=input) 0xFFFF 0x03CC 0xBB9B 0x0E03 0x40FE pullup bits (1=pullup) 0xDF1F 0x0000 0x0080 0x0003 0x0008 test step out_data dont care 1: 0x8707 0x0000 0xBB80 0x0A1F 0x0004 2: 0x8707 0x1000 0xBB00 0x0A1F 0x0004 3: 0x8707 0x0000 0xBB80 0x0A1F 0x0004 4: 0x8707 0x0800 0xBB80 0x0A1E 0x0004 5: 0x8707 0x0000 0xBB80 0x0A1F 0x0004 6: 0x8707 0x0400 0xBB80 0x0A1D 0x0004 7: 0x8707 0x0000 0xBB80 0x0A1F 0x0004 8: 0x8707 0x0009 0xBB80 0x0A1F 0x0004 9: 0x8707 0x0000 0xBB80 0x0A1F 0x0004 10: 0x8707 0x0006 0xBB80 0x0A1F 0x0004 11: 0x8707 0x0000 0xBB80 0x0A1F 0x0004 12: 0x8707 0x0090 0xAB80 0x0A1F 0x0004 13: 0x8707 0x0000 0xBB80 0x0A1F 0x0004 14: 0x8707 0x0060 0x9B80 0x0A1F 0x0004 15: 0x8707 0x0000 0xBB80 0x0A1F 0x0004 16: 0x8707 0x0000 0xB780 0x0A1F 0x000C 17: 0x8707 0x0000 0xBB80 0x0A1F 0x0004 18: 0x8707 0x0000 0x7B80 0x0A1F 0x0004 19: 0x8707 0x0000 0xBB80 0x0A1F 0x0004 20: 0x8707 0x0000 0xBB80 0x221F 0x0004 21: 0x8707 0x0000 0xBB80 0x321F 0x0004 22: 0x8707 0x0000 0xBB80 0x121F 0x0004 23: 0x8707 0x0000 0xBB80 0x0A1F 0x0004 24: 0x8707 0x0000 0xBA80 0x8A1F 0x0004 25: 0x8707 0x0000 0xBA80 0xCA1F 0x0004 26: 0x8707 0x0000 0xBA80 0x4A1F 0x0004 27: 0x8707 0x0000 0xBB80 0x0A1F 0x0004 28: 0x8707 0x0000 0xBB80 0x0A1F 0x8004 29: 0x8707 0x0000 0xBB80 0x091F 0x8004 30: 0x8707 0x0000 0xBB80 0x0B1F 0x0004 31: 0x8707 0x0000 0xBB80 0x0A1F 0x0004 32: 0x9707 0x0000 0xBB80 0x0A3F 0x0004 33: 0x8707 0x0000 0xBB80 0x0A1F 0x0004 34: 0x8F07 0x0000 0xBB80 0x0A5F 0x0004 35: 0x8707 0x0000 0xBB80 0x0A1F 0x0004 36: 0x8717 0x0000 0xBB80 0x0A9F 0x0004 37: 0x8707 0x0000 0xBB80 0x0A1F 0x0004 38: 0x870F 0x0000 0xBB80 0x0A1F 0x0005 39: 0x8707 0x0000 0xBB80 0x0A1F 0x0004 40: 0xC707 0x0000 0xBB80 0x0A1F 0x2000 41: 0x8707 0x0000 0xBB80 0x0A1F 0x0004 42: 0x0707 0x0000 0xBB80 0x0A1F 0x1004 43: 0x8707 0x0000 0xBB80 0x0A1F 0x0004 44: 0x8707 0x0000 0xBB80 0x0A1F 0x0004 45: 0x8707 0x0000 0xBBC0 0x0A1F 0x0004 46: 0x8707 0x0000 0xBBC0 0x0A1F 0x0004 47: 0x8705 0x0000 0xBBC0 0x0A17 0x0004 48: 0x8704 0x0000 0xBBC0 0x0A07 0x0004 49: 0x8700 0x0000 0xBBC0 0x0A03 0x0004 50: 0x8701 0x0000 0xBBC0 0x0A13 0x0004 51: 0x8703 0x0000 0xBBC0 0x0A1B 0x0004 52: 0x8702 0x0000 0xBBC0 0x0A0B 0x0004 53: 0x8706 0x0000 0xBBC0 0x0A0F 0x0004 54: 0x8707 0x0000 0xBBC0 0x0A1F 0x0004 55: 0x8707 0x0000 0xB9E0 0x0A1F 0x0004 56: 0x8707 0x0000 0xB9E0 0x0A1F 0x0004 57: 0x8507 0x0000 0xB9E0 0x0A17 0x0004 58: 0x8407 0x0000 0xB9E0 0x0A07 0x0004 59: 0x8007 0x0000 0xB9E0 0x0A03 0x0004 60: 0x8107 0x0000 0xB9E0 0x0A13 0x0004 61: 0x8307 0x0000 0xB9E0 0x0A1B 0x0004 62: 0x8207 0x0000 0xB9E0 0x0A0B 0x0004 63: 0x8607 0x0000 0xB9E0 0x0A0F 0x0004 64: 0x8707 0x0000 0xB9E0 0x0A1F 0x0004 65: 0x8707 0x0000 0xBBC0 0x0A1F 0x0004 66: 0x8707 0x0000 0xBB80 0x0A1F 0x0004 67: 0x8707 0x0000 0xBB80 0x0A1F 0x0004 68: 0x8705 0x0000 0xBB80 0x0A17 0x0004 69: 0x8704 0x0000 0xBB80 0x0A07 0x0004 70: 0x8700 0x0000 0xBB80 0x0A03 0x0004 71: 0x8701 0x0000 0xBB80 0x0A13 0x0004 72: 0x8703 0x0000 0xBB80 0x0A1B 0x0004 73: 0x8702 0x0000 0xBB80 0x0A0B 0x0004 74: 0x8706 0x0000 0xBB80 0x0A0F 0x0004 75: 0x8707 0x0000 0xBB80 0x0A1F 0x0004 76: 0x8707 0x0000 0xBB80 0x0A1F 0x0004 PINs used (in edge connector order) (G=ground,P=power) SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBB LETTER ABCDEFHJKLMNPRSTUVABCDEFHJKLMNPRSTUVABCDEFHJKLMNPRSTUVABCDEFHJKLMNPRSTUV SIDE 111111111111111111222222222222222222111111111111111111222222222222222222 USAGE PP PPPPPIIIIII GOIP GPPPPPIIOOIIOO OOOIOOIIIIO OIIGIIP GIIPPPIIIIIII OP UUT inputs: 29 UUT outputs: 29 pins used: 58 not used: 8 76 'test steps' 231 lines M7102 PCB REV D SCHEMATIC REV C Positive I/O Bus Converter (DW08E) PART 2 Tests Omnibus DATA BUS driving Posibus ACIN and DATA. (See PART 1 for Posibus driving Omnibus. (Two parts are necessary due to the Omnibus DATA00:02-N is a bidirectional bus). Tolerates 3.3k ohm pullups to +5v on pin (are needed for PART 1): BK2 Omnibus DATA00 (bidirectional, input + open collector output) BL2 Omnibus DATA01 (bidirectional, input + open collector output) BM2 Omnibus DATA02 (bidirectional, input + open collector output) PINS Main menu Sun Nov 22 18:43:20 2015 test file is: tests\m7102_2.tst delay is: 0 trigger is: 1 1 read test file 2 set test delay 3 set test trigger 4 run test 5 output loading test 8 diags 9 exit UUT power is okay Sun Nov 22 18:43:21 2015 space single step O run once (one test, all steps) F run, stop on fail G go (run tests N run, stop on fail, no print S scope (run, no print) C toggle comment printout + increase speed (less delay) - decrease speed (more delay)(slower) Q quit test scope (run, no print) ppppppppppppppppppppppppppppppppppppppppppppppppppppppp space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C toggle comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT ABABABAAAAAABAABBBBAABBBBBBBBBBABABABABABBABBBAAABBBAAAAAA LETTER NFPHRJKNLMPTBRSADVCVULKMJHFRSPNDPERDSEUBUVADEEKLMKLMFHJFHJ SIDE 1212122222221221121111111111112121222211211212111222111222 DIRECTION IPIPIPIOIOIOOIOOIPOIOIIOIIOIIOIPIPIPIPIPOIPIOIIIIIIIPPPPPP all fails was lo 0000000000000000000000000000000000000000000000000000000000 falling vvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvv vvvvvvvvv rising ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ ^^^^^^^^^ was hi 1111111111111111111111111111111111111111111111 111111111 total fails 0, total passes 55 Main menu Sun Nov 22 18:43:25 2015 test file is: tests\m7102_2.tst delay is: 0 trigger is: 1 1 read test file 2 set test delay 3 set test trigger 4 run test 5 output loading test 8 diags 9 exit UUT power is okay Sun Nov 22 18:52:42 2015 space single step O run once (one test, all steps) F run, stop on fail G go (run tests N run, stop on fail, no print S scope (run, no print) C toggle comment printout + increase speed (less delay) - decrease speed (more delay)(slower) Q quit test scope (run, no print) ppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppp p space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C toggle comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT ABABABAAAAAABAABBBBAABBBBBBBBBBABABABABABBABBBAAABBBAAAAAA LETTER NFPHRJKNLMPTBRSADVCVULKMJHFRSPNDPERDSEUBUVADEEKLMKLMFHJFHJ SIDE 1212122222221221121111111111112121222211211212111222111222 DIRECTION IPIPIPIOIOIOOIOOIPOIOIIOIIOIIOIPIPIPIPIPOIPIOIIIIIIIPPPPPP all fails was lo 0000000000000000000000000000000000000000000000000000000000 falling vvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvv vvvvvvvvv rising ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ ^^^^^^^^^ was hi 1111111111111111111111111111111111111111111111 111111111 total fails 0, total passes 80 Main menu Sun Nov 22 18:52:50 2015 test file is: tests\m7102_2.tst delay is: 0 trigger is: 1 1 read test file 2 set test delay 3 set test trigger 4 run test 5 output loading test 8 diags 9 exit Enter test file name? trying to open test file: tests\m7102_1.tst reading test file: tests\m7102_1.tst comment: M7102 PCB REV D SCHEMATIC REV C Positive I/O Bus Converter (DW08E) comment: comment: PART 1 Tests Posibus driving Omnibus DATA BUS. comment: (See PART 2 for Omnibus driving Posibus. comment: comment: (Two parts are necessary due to the Omnibus DATA00:02-N is a bidirectional bus). comment: comment: Needs 3.3k ohm pullups to +5v on pin: comment: BK2 Omnibus DATA00 (bidirectional, input + open collector output) comment: BL2 Omnibus DATA01 (bidirectional, input + open collector output) comment: BM2 Omnibus DATA02 (bidirectional, input + open collector output) comment: pins: PINS pins: 1 I AN1 E6-9 INPUT 1 pins: 2 P BF2 E13-8 OUTPUT A-N (7416 OPEN COLLECTOR OUTPUT) pins: 3 I AP1 E6-6 INPUT 2 pins: 4 P BH2 E13-7 OUTPUT 2-N (7416 OPEN COLLECTOR OUTPUT) pins: 5 I AR1 E6-5 INPUT 3 pins: 6 P BJ2 E13-6 OUTPUT 3-N (7416 OPEN COLLECTOR OUTPUT) pins: 7 I AK2 E9-11 INPUT 4 pins: 8 O AN2 E9-13 OUTPUT 4 (384 OUTPUT) pins: 9 I AL2 E9-9 INPUT 5 pins: 10 O AM2 E9-14 OUTPUT 5 (384 OUTPUT) pins: 11 I AP2 E9-6 INPUT 6 pins: 12 O AT2 E9-2 OUTPUT 6 (384 OUTPUT) pins: 13 O BB1 E11-6 OUTPUT 6-N (74H04 OUTPUT) pins: 14 I AR2 E9-5 INPUT 7 pins: 15 O AS2 E9-3 OUTPUT 7 (384 OUTPUT) pins: 16 O BA1 E11-10 OUTPUT 7-N (74H04 OUTPUT) pins: 17 I BD1 E11-1 INPUT 8 pins: 18 P BV2 E13-12 OUTPUT 8 (7416 OPEN COLLECTOR OUTPUT) pins: 19 O BC1 E11-2 OUTPUT 8-N (74H04 OUTPUT) pins: 20 I AV1 E11-13 INPUT 9 pins: 21 O AU1 E11-12 OUTPUT 9-N (74H04 OUTPUT) pins: 22 I BL1 E12-4 INPUT 10A pins: 23 I BK1 E12-5 INPUT 10B pins: 24 O BM1 E12-3 OUTPUT 10 = INPUT 10A NOR INPUT 10B (380 OUTPUT) pins: 25 I BJ1 E12-9 INPUT 11A pins: 26 I BH1 E12-10 INPUT 11B pins: 27 O BF1 E12-14 OUTPUT 11 = INPUT 11A NOR INPUT 11B (M380 OUTPUT) pins: 28 I BR1 E15-12 INPUT 12A pins: 29 I BS1 E15-11 INPUT 12B pins: 30 O BP1 E15-? OUTPUT 12 = INPUT 12A NAND INPUT 12B (8881 OPEN COLLECTOR OUTPUT WITH 3.3K PULLUP) pins: 31 I BN2 E10-6,7 INPUT 13 pins: 32 P AD1 E1-3 OUTPUT 13 (75452 OPEN COLLECTOR OUTPUT) pins: 33 I BP2 E14-11,12 INPUT 14 pins: 34 P AE1 E2-3 OUTPUT 14 (75452 OPEN COLLECTOR OUTPUT) pins: 35 I BR2 E14-9,10 INPUT 15 pins: 36 P AD2 E5-5 OUTPUT 15 (75452 OPEN COLLECTOR OUTPUT) pins: 37 I BS2 E14-6,7 INPUT 16 pins: 38 P AE2 E4-5 OUTPUT 16 (75452 OPEN COLLECTOR OUTPUT) pins: 39 I BU1 E14-4,5 INPUT 17 pins: 40 P AB1 E4-5 OUTPUT 17 (75452 OPEN COLLECTOR OUTPUT) pins: 41 O BU2 E14-3 OUTPUT 17-N (380 OUTPUT) pins: 42 I BV1 E2-6,7 INPUT 18 pins: 43 P AA1 E2-5 OUTPUT 18-N (75452 OPEN COLLECTOR OUTPUT) pins: 44 I BD2 E11-3 OMNIBUS DATA TO I/O DATA-N (LOW ALSO DISABLES BAC <> OMNIBUS) pins: 45 O BE1 E11-4 OMNIBUS DATA TO I/O DATA (74H04 OUTPUT) pins: 46 I BE2 E12-12 INPUT OUT-N (L -> BAC TO OMNIBUS, H -> OMNIBUS TO BAC) pins: 47 I AK1 E3-6 INPUT BAC0 (DATA FROM I/O BUS) pins: 48 I AL1 E3-5 INPUT BAC1 (DATA FROM I/O BUS) pins: 49 I AM1 E6-11 INPUT BAC2 (DATA FROM I/O BUS) pins: 50 O BK2 E15-1 OUTPUT DATA00-N (OMNIBUS DATA00) (8881 OPEN COLLECTOR OUTPUT) pins: 51 O BL2 E15-4 OUTPUT DATA01-N (OMNIBUS DATA01) (8881 OPEN COLLECTOR OUTPUT) pins: 52 O BM2 E15-10 OUTPUT DATA02-N (OMNIBUS DATA02) (8881 OPEN COLLECTOR OUTPUT) pins: 53 P AF1 E4-3 OUTPUT I/O BUS ACIN0-N (75452 OPEN COLLECTOR OUTPUT) pins: 54 P AH1 E5-3 OUTPUT I/O BUS ACIN1-N (75452 OPEN COLLECTOR OUTPUT) pins: 55 P AJ1 E8-5 OUTPUT I/O BUS ACIN2-N (75452 OPEN COLLECTOR OUTPUT) pins: 56 P AF2 E7-5 OUTPUT I/O BUS DATA0-N (75452 OPEN COLLECTOR OUTPUT) pins: 57 P AH2 E3-3 OUTPUT I/O BUS DATA1-N (75452 OPEN COLLECTOR OUTPUT) pins: 58 P AJ2 E7-3 OUTPUT I/O BUS DATA2-N (75452 OPEN COLLECTOR OUTPUT) pins: direction: IPIPIPIOIOIOOIOOIPOIOIIOIIOIIOIPIPIPIPIPOIPIOIIIIOOOPPPPPP test 1: 0101010000001001001010010010010000000000101010000111111111 comment: comment: ; INPUT 1 -> OUTPUT 1-N test 2: 10 test 3: 01 comment: comment: ; INPUT 2 -> OUTPUT 2-N test 4: 10 test 5: 01 comment: comment: ; INPUT 3 -> OUTPUT 3-N test 6: 10 test 7: 01 comment: comment: ; INPUT 4 -> OUTPUT 4 test 8: 11 test 9: 00 comment: comment: ; INPUT 5 -> OUTPUT 5 test 10: 11 test 11: 00 comment: comment: ; INPUT 6 -> OUTPUT 6, OUTPUT 6-N test 12: 110 test 13: 001 comment: comment: ; INPUT 7 -> OUTPUT 7, OUTPUT 7-N test 14: 110 test 15: 001 comment: comment: ; INPUT 8 -> OUTPUT 8, OUTPUT 8-N test 16: 110 test 17: 001 comment: comment: ; INPUT 9 -> OOUTPUT 9-N test 18: 10 test 19: 01 comment: comment: ; INPUT 10A NOR INPUT 10B -> OUTPUT 10 test 20: 010 test 21: 110 test 22: 100 test 23: 001 comment: comment: ; INPUT 11A NOR INPUT 11B -> OUTPUT 11 test 24: 010 test 25: 110 test 26: 100 test 27: 001 comment: comment: ; INPUT 12A NAND INPUT 12B -> OUTPUT 12 test 28: 011 test 29: 110 test 30: 101 test 31: 001 comment: comment: ; INPUT 13 -> OUTPUT 13 test 32: 11 test 33: 00 comment: comment: ; INPUT 14 -> OUTPUT 14 test 34: 11 test 35: 00 comment: comment: ; INPUT 15 -> OUTPUT 15 test 36: 11 test 37: 00 comment: comment: ; INPUT 16 -> OUTPUT 16 test 38: 11 test 39: 00 comment: comment: ; INPUT 17 -> OUTPUT 17, OUTPUT 17-N test 40: 110 test 41: 001 comment: comment: ; INPUT 18 -> OUTPUT 18-N test 42: 10 test 43: 01 comment: comment: ; (no change) test 44: 0101010000001001001010010010010000000000101010000111111111 comment: comment: comment: comment: ; PART 1 unique tests (Posibus BAC0:2 driving Omnibus DATA00:02-N). comment: comment: ; (See PART 2 for Omnibus DATA00:02-N driving). comment: comment: comment: comment: ; Select Omnibus DATA00:02-N -> Posibus DATA0:2-N comment: comment: ; OMNIBUS DATA TO I/O DATA-N LO, OUT-N HI; OMNIBUS DATA TO I/O DATA -> HI test 45: 011 comment: ; (no change) test 46: 000111111111 comment: comment: ; All BAC0:2 patterns (Omnibus DATA00:02-N, Posibus ACIN0:2-N, Posibus DATA0:2-N always HI). comment: ; (Omnibus DATA00:02-N always high due to pullups and no drivers in PART 1 tests) test 47: 001 test 48: 011 test 49: 010 test 50: 110 test 51: 111 test 52: 101 test 53: 100 test 54: 000 comment: comment: comment: comment: ; Select Omnibus DATA00:02-N -> PosiBus ACIN0:2-N comment: comment: ; OMNIBUS DATA TO I/O DATA-N HI, OUT-N HI; OMNIBUS DATA TO I/O DATA -> LO test 55: 101 comment: ; (no change) test 56: 000111111111 comment: comment: ; All BAC0:2 patterns (Omnibus DATA00:02-N, Posibus ACIN0:2-N, Posibus DATA0:2-N always HI). comment: ; (Omnibus DATA00:02-N always high due to pullups and no drivers in PART 1 tests) test 57: 001 test 58: 011 test 59: 010 test 60: 110 test 61: 111 test 62: 101 test 63: 100 test 64: 000 comment: comment: comment: comment: ; Select Posibus BAC0:2 -> Omnibus DATA00:02-N comment: comment: ; OMNIBUS DATA TO I/O DATA-N HI, OUT-N LO; OMNIBUS DATA TO I/O DATA -> LO test 65: 100 comment: ; (no change) test 66: 000111111111 comment: comment: ; All BAC0:2 patterns (PosibusACIN0:2-N and Posibus DATA0:2-N always HI). test 67: 001110 test 68: 011100 test 69: 010101 test 70: 110001 test 71: 111000 test 72: 101010 test 73: 100011 test 74: 000111 comment: comment: comment: comment: ; Select Omnibus DATA00:02-N -> Posibus DATA0:2-N comment: comment: ; OMNIBUS DATA TO I/O DATA-N LO, OUT-N LO; OMNIBUS DATA TO I/O DATA -> HI test 75: 010 comment: ; (no change) test 76: 000111111111 comment: comment: ; All BAC0:2 patterns (Omnibus DATA00:02-N, Posibus ACIN0:2-N, Posibus DATA0:2-N always HI). comment: ; (Omnibus DATA00:02-N always high due to pullups and no drivers in PART 1 tests) test 77: 001 test 78: 011 test 79: 010 test 80: 110 test 81: 111 test 82: 101 test 83: 100 test 84: 000 test 85: comment: ; (no change) test 86: 0101010000001001001010010010010000000000101010000111111111 end: END summary column 1: offset 1, mask 0x1000 column 2: offset 2, mask 0x0080 column 3: offset 1, mask 0x0800 column 4: offset 3, mask 0x0001 column 5: offset 1, mask 0x0400 column 6: offset 3, mask 0x0002 column 7: offset 1, mask 0x0001 column 8: offset 1, mask 0x0008 column 9: offset 1, mask 0x0002 column 10: offset 1, mask 0x0004 column 11: offset 1, mask 0x0010 column 12: offset 1, mask 0x0080 column 13: offset 2, mask 0x1000 column 14: offset 1, mask 0x0020 column 15: offset 1, mask 0x0040 column 16: offset 2, mask 0x2000 column 17: offset 2, mask 0x0400 column 18: offset 4, mask 0x0008 column 19: offset 2, mask 0x0800 column 20: offset 2, mask 0x4000 column 21: offset 2, mask 0x8000 column 22: offset 3, mask 0x1000 column 23: offset 3, mask 0x2000 column 24: offset 3, mask 0x0800 column 25: offset 3, mask 0x4000 column 26: offset 3, mask 0x8000 column 27: offset 2, mask 0x0100 column 28: offset 3, mask 0x0100 column 29: offset 4, mask 0x8000 column 30: offset 3, mask 0x0200 column 31: offset 3, mask 0x0020 column 32: offset 0, mask 0x1000 column 33: offset 3, mask 0x0040 column 34: offset 0, mask 0x0800 column 35: offset 3, mask 0x0080 column 36: offset 0, mask 0x0010 column 37: offset 4, mask 0x0001 column 38: offset 0, mask 0x0008 column 39: offset 4, mask 0x2000 column 40: offset 0, mask 0x4000 column 41: offset 4, mask 0x0004 column 42: offset 4, mask 0x1000 column 43: offset 0, mask 0x8000 column 44: offset 2, mask 0x0020 column 45: offset 2, mask 0x0200 column 46: offset 2, mask 0x0040 column 47: offset 1, mask 0x8000 column 48: offset 1, mask 0x4000 column 49: offset 1, mask 0x2000 column 50: offset 3, mask 0x0004 column 51: offset 3, mask 0x0008 column 52: offset 3, mask 0x0010 column 53: offset 0, mask 0x0400 column 54: offset 0, mask 0x0200 column 55: offset 0, mask 0x0100 column 56: offset 0, mask 0x0004 column 57: offset 0, mask 0x0002 column 58: offset 0, mask 0x0001 direction bits (1=input) 0xFFFF 0x03CC 0xBB9B 0x0E1F 0x40FE pullup bits (1=pullup) 0xDF1F 0x0000 0x0080 0x0003 0x0008 test step out_data dont care 1: 0x8707 0x0000 0xBB80 0x0A1F 0x0004 2: 0x8707 0x1000 0xBB00 0x0A1F 0x0004 3: 0x8707 0x0000 0xBB80 0x0A1F 0x0004 4: 0x8707 0x0800 0xBB80 0x0A1E 0x0004 5: 0x8707 0x0000 0xBB80 0x0A1F 0x0004 6: 0x8707 0x0400 0xBB80 0x0A1D 0x0004 7: 0x8707 0x0000 0xBB80 0x0A1F 0x0004 8: 0x8707 0x0009 0xBB80 0x0A1F 0x0004 9: 0x8707 0x0000 0xBB80 0x0A1F 0x0004 10: 0x8707 0x0006 0xBB80 0x0A1F 0x0004 11: 0x8707 0x0000 0xBB80 0x0A1F 0x0004 12: 0x8707 0x0090 0xAB80 0x0A1F 0x0004 13: 0x8707 0x0000 0xBB80 0x0A1F 0x0004 14: 0x8707 0x0060 0x9B80 0x0A1F 0x0004 15: 0x8707 0x0000 0xBB80 0x0A1F 0x0004 16: 0x8707 0x0000 0xB780 0x0A1F 0x000C 17: 0x8707 0x0000 0xBB80 0x0A1F 0x0004 18: 0x8707 0x0000 0x7B80 0x0A1F 0x0004 19: 0x8707 0x0000 0xBB80 0x0A1F 0x0004 20: 0x8707 0x0000 0xBB80 0x221F 0x0004 21: 0x8707 0x0000 0xBB80 0x321F 0x0004 22: 0x8707 0x0000 0xBB80 0x121F 0x0004 23: 0x8707 0x0000 0xBB80 0x0A1F 0x0004 24: 0x8707 0x0000 0xBA80 0x8A1F 0x0004 25: 0x8707 0x0000 0xBA80 0xCA1F 0x0004 26: 0x8707 0x0000 0xBA80 0x4A1F 0x0004 27: 0x8707 0x0000 0xBB80 0x0A1F 0x0004 28: 0x8707 0x0000 0xBB80 0x0A1F 0x8004 29: 0x8707 0x0000 0xBB80 0x091F 0x8004 30: 0x8707 0x0000 0xBB80 0x0B1F 0x0004 31: 0x8707 0x0000 0xBB80 0x0A1F 0x0004 32: 0x9707 0x0000 0xBB80 0x0A3F 0x0004 33: 0x8707 0x0000 0xBB80 0x0A1F 0x0004 34: 0x8F07 0x0000 0xBB80 0x0A5F 0x0004 35: 0x8707 0x0000 0xBB80 0x0A1F 0x0004 36: 0x8717 0x0000 0xBB80 0x0A9F 0x0004 37: 0x8707 0x0000 0xBB80 0x0A1F 0x0004 38: 0x870F 0x0000 0xBB80 0x0A1F 0x0005 39: 0x8707 0x0000 0xBB80 0x0A1F 0x0004 40: 0xC707 0x0000 0xBB80 0x0A1F 0x2000 41: 0x8707 0x0000 0xBB80 0x0A1F 0x0004 42: 0x0707 0x0000 0xBB80 0x0A1F 0x1004 43: 0x8707 0x0000 0xBB80 0x0A1F 0x0004 44: 0x8707 0x0000 0xBB80 0x0A1F 0x0004 45: 0x8707 0x0000 0xBBC0 0x0A1F 0x0004 46: 0x8707 0x0000 0xBBC0 0x0A1F 0x0004 47: 0x8707 0x2000 0xBBC0 0x0A1F 0x0004 48: 0x8707 0x6000 0xBBC0 0x0A1F 0x0004 49: 0x8707 0x4000 0xBBC0 0x0A1F 0x0004 50: 0x8707 0xC000 0xBBC0 0x0A1F 0x0004 51: 0x8707 0xE000 0xBBC0 0x0A1F 0x0004 52: 0x8707 0xA000 0xBBC0 0x0A1F 0x0004 53: 0x8707 0x8000 0xBBC0 0x0A1F 0x0004 54: 0x8707 0x0000 0xBBC0 0x0A1F 0x0004 55: 0x8707 0x0000 0xB9E0 0x0A1F 0x0004 56: 0x8707 0x0000 0xB9E0 0x0A1F 0x0004 57: 0x8707 0x2000 0xB9E0 0x0A1F 0x0004 58: 0x8707 0x6000 0xB9E0 0x0A1F 0x0004 59: 0x8707 0x4000 0xB9E0 0x0A1F 0x0004 60: 0x8707 0xC000 0xB9E0 0x0A1F 0x0004 61: 0x8707 0xE000 0xB9E0 0x0A1F 0x0004 62: 0x8707 0xA000 0xB9E0 0x0A1F 0x0004 63: 0x8707 0x8000 0xB9E0 0x0A1F 0x0004 64: 0x8707 0x0000 0xB9E0 0x0A1F 0x0004 65: 0x8707 0x0000 0xB9A0 0x0A1F 0x0004 66: 0x8707 0x0000 0xB9A0 0x0A1F 0x0004 67: 0x8707 0x2000 0xB9A0 0x0A0F 0x0004 68: 0x8707 0x6000 0xB9A0 0x0A07 0x0004 69: 0x8707 0x4000 0xB9A0 0x0A17 0x0004 70: 0x8707 0xC000 0xB9A0 0x0A13 0x0004 71: 0x8707 0xE000 0xB9A0 0x0A03 0x0004 72: 0x8707 0xA000 0xB9A0 0x0A0B 0x0004 73: 0x8707 0x8000 0xB9A0 0x0A1B 0x0004 74: 0x8707 0x0000 0xB9A0 0x0A1F 0x0004 75: 0x8707 0x0000 0xBB80 0x0A1F 0x0004 76: 0x8707 0x0000 0xBB80 0x0A1F 0x0004 77: 0x8707 0x2000 0xBB80 0x0A1F 0x0004 78: 0x8707 0x6000 0xBB80 0x0A1F 0x0004 79: 0x8707 0x4000 0xBB80 0x0A1F 0x0004 80: 0x8707 0xC000 0xBB80 0x0A1F 0x0004 81: 0x8707 0xE000 0xBB80 0x0A1F 0x0004 82: 0x8707 0xA000 0xBB80 0x0A1F 0x0004 83: 0x8707 0x8000 0xBB80 0x0A1F 0x0004 84: 0x8707 0x0000 0xBB80 0x0A1F 0x0004 85: 0x8707 0x0000 0xBB80 0x0A1F 0x0004 86: 0x8707 0x0000 0xBB80 0x0A1F 0x0004 PINs used (in edge connector order) (G=ground,P=power) SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBB LETTER ABCDEFHJKLMNPRSTUVABCDEFHJKLMNPRSTUVABCDEFHJKLMNPRSTUVABCDEFHJKLMNPRSTUV SIDE 111111111111111111222222222222222222111111111111111111222222222222222222 USAGE PP PPPPPIIIIII GOIP GPPPPPIIOOIIOO OOOIOOIIIIO OIIGIIP GIIPPPOOOIIII OP UUT inputs: 26 UUT outputs: 32 pins used: 58 not used: 8 86 'test steps' 244 lines M7102 PCB REV D SCHEMATIC REV C Positive I/O Bus Converter (DW08E) PART 1 Tests Posibus driving Omnibus DATA BUS. (See PART 2 for Omnibus driving Posibus. (Two parts are necessary due to the Omnibus DATA00:02-N is a bidirectional bus). Needs 3.3k ohm pullups to +5v on pin: BK2 Omnibus DATA00 (bidirectional, input + open collector output) BL2 Omnibus DATA01 (bidirectional, input + open collector output) BM2 Omnibus DATA02 (bidirectional, input + open collector output) PINS Main menu Sun Nov 22 18:53:02 2015 test file is: tests\m7102_1.tst delay is: 0 trigger is: 1 1 read test file 2 set test delay 3 set test trigger 4 run test 5 output loading test 8 diags 9 exit UUT power is okay Sun Nov 22 18:53:03 2015 space single step O run once (one test, all steps) F run, stop on fail G go (run tests N run, stop on fail, no print S scope (run, no print) C toggle comment printout + increase speed (less delay) - decrease speed (more delay)(slower) Q quit test scope (run, no print) pppppppppppppppppppppppppppppppppppppppppppppp space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C toggle comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT ABABABAAAAAABAABBBBAABBBBBBBBBBABABABABABBABBBAAABBBAAAAAA LETTER NFPHRJKNLMPTBRSADVCVULKMJHFRSPNDPERDSEUBUVADEEKLMKLMFHJFHJ SIDE 1212122222221221121111111111112121222211211212111222111222 DIRECTION IPIPIPIOIOIOOIOOIPOIOIIOIIOIIOIPIPIPIPIPOIPIOIIIIOOOPPPPPP all fails was lo 0000000000000000000000000000000000000000000000000000 falling vvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvv rising ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ was hi 1111111111111111111111111111111111111111111111111111111111 total fails 0, total passes 46 Main menu Sun Nov 22 18:53:07 2015 test file is: tests\m7102_1.tst delay is: 0 trigger is: 1 1 read test file 2 set test delay 3 set test trigger 4 run test 5 output loading test 8 diags 9 exit UUT power is okay Sun Nov 22 18:55:31 2015 space single step O run once (one test, all steps) F run, stop on fail G go (run tests N run, stop on fail, no print S scope (run, no print) C toggle comment printout + increase speed (less delay) - decrease speed (more delay)(slower) Q quit test scope (run, no print) ppppppppppppppppppppppppppppppppp space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C toggle comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT ABABABAAAAAABAABBBBAABBBBBBBBBBABABABABABBABBBAAABBBAAAAAA LETTER NFPHRJKNLMPTBRSADVCVULKMJHFRSPNDPERDSEUBUVADEEKLMKLMFHJFHJ SIDE 1212122222221221121111111111112121222211211212111222111222 DIRECTION IPIPIPIOIOIOOIOOIPOIOIIOIIOIIOIPIPIPIPIPOIPIOIIIIOOOPPPPPP all fails was lo 0000000000000000000000000000000000000000000000000000 falling vvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvv rising ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ was hi 1111111111111111111111111111111111111111111111111111111111 total fails 0, total passes 33 Main menu Sun Nov 22 18:55:34 2015 test file is: tests\m7102_1.tst delay is: 0 trigger is: 1 1 read test file 2 set test delay 3 set test trigger 4 run test 5 output loading test 8 diags 9 exit Enter test file name? trying to open test file: tests\m7102_2.tst reading test file: tests\m7102_2.tst comment: M7102 PCB REV D SCHEMATIC REV C Positive I/O Bus Converter (DW08E) comment: comment: PART 2 Tests Omnibus DATA BUS driving Posibus ACIN and DATA. comment: (See PART 1 for Posibus driving Omnibus. comment: comment: (Two parts are necessary due to the Omnibus DATA00:02-N is a bidirectional bus). comment: comment: Tolerates 3.3k ohm pullups to +5v on pin (are needed for PART 1): comment: BK2 Omnibus DATA00 (bidirectional, input + open collector output) comment: BL2 Omnibus DATA01 (bidirectional, input + open collector output) comment: BM2 Omnibus DATA02 (bidirectional, input + open collector output) comment: pins: PINS pins: 1 I AN1 E6-9 INPUT 1 pins: 2 P BF2 E13-8 OUTPUT A-N (7416 OPEN COLLECTOR OUTPUT) pins: 3 I AP1 E6-6 INPUT 2 pins: 4 P BH2 E13-7 OUTPUT 2-N (7416 OPEN COLLECTOR OUTPUT) pins: 5 I AR1 E6-5 INPUT 3 pins: 6 P BJ2 E13-6 OUTPUT 3-N (7416 OPEN COLLECTOR OUTPUT) pins: 7 I AK2 E9-11 INPUT 4 pins: 8 O AN2 E9-13 OUTPUT 4 (384 OUTPUT) pins: 9 I AL2 E9-9 INPUT 5 pins: 10 O AM2 E9-14 OUTPUT 5 (384 OUTPUT) pins: 11 I AP2 E9-6 INPUT 6 pins: 12 O AT2 E9-2 OUTPUT 6 (384 OUTPUT) pins: 13 O BB1 E11-6 OUTPUT 6-N (74H04 OUTPUT) pins: 14 I AR2 E9-5 INPUT 7 pins: 15 O AS2 E9-3 OUTPUT 7 (384 OUTPUT) pins: 16 O BA1 E11-10 OUTPUT 7-N (74H04 OUTPUT) pins: 17 I BD1 E11-1 INPUT 8 pins: 18 P BV2 E13-12 OUTPUT 8 (7416 OPEN COLLECTOR OUTPUT) pins: 19 O BC1 E11-2 OUTPUT 8-N (74H04 OUTPUT) pins: 20 I AV1 E11-13 INPUT 9 pins: 21 O AU1 E11-12 OUTPUT 9-N (74H04 OUTPUT) pins: 22 I BL1 E12-4 INPUT 10A pins: 23 I BK1 E12-5 INPUT 10B pins: 24 O BM1 E12-3 OUTPUT 10 = INPUT 10A NOR INPUT 10B (380 OUTPUT) pins: 25 I BJ1 E12-9 INPUT 11A pins: 26 I BH1 E12-10 INPUT 11B pins: 27 O BF1 E12-14 OUTPUT 11 = INPUT 11A NOR INPUT 11B (M380 OUTPUT) pins: 28 I BR1 E15-12 INPUT 12A pins: 29 I BS1 E15-11 INPUT 12B pins: 30 O BP1 E15-? OUTPUT 12 = INPUT 12A NAND INPUT 12B (8881 OPEN COLLECTOR OUTPUT WITH 3.3K PULLUP) pins: 31 I BN2 E10-6,7 INPUT 13 pins: 32 P AD1 E1-3 OUTPUT 13 (75452 OPEN COLLECTOR OUTPUT) pins: 33 I BP2 E14-11,12 INPUT 14 pins: 34 P AE1 E2-3 OUTPUT 14 (75452 OPEN COLLECTOR OUTPUT) pins: 35 I BR2 E14-9,10 INPUT 15 pins: 36 P AD2 E5-5 OUTPUT 15 (75452 OPEN COLLECTOR OUTPUT) pins: 37 I BS2 E14-6,7 INPUT 16 pins: 38 P AE2 E4-5 OUTPUT 16 (75452 OPEN COLLECTOR OUTPUT) pins: 39 I BU1 E14-4,5 INPUT 17 pins: 40 P AB1 E4-5 OUTPUT 17 (75452 OPEN COLLECTOR OUTPUT) pins: 41 O BU2 E14-3 OUTPUT 17-N (380 OUTPUT) pins: 42 I BV1 E2-6,7 INPUT 18 pins: 43 P AA1 E2-5 OUTPUT 18-N (75452 OPEN COLLECTOR OUTPUT) pins: 44 I BD2 E11-3 OMNIBUS DATA TO I/O DATA-N (LOW ALSO DISABLES BAC <> OMNIBUS) pins: 45 O BE1 E11-4 OMNIBUS DATA TO I/O DATA (74H04 OUTPUT) pins: 46 I BE2 E12-12 INPUT OUT-N (L -> BAC TO OMNIBUS, H -> OMNIBUS TO BAC) pins: 47 I AK1 E3-6 INPUT BAC0 (DATA FROM I/O BUS) pins: 48 I AL1 E3-5 INPUT BAC1 (DATA FROM I/O BUS) pins: 49 I AM1 E6-11 INPUT BAC2 (DATA FROM I/O BUS) pins: 50 I BK2 E15-1 INPUT DATA00-N (OMNIBUS DATA00) (8881 OPEN COLLECTOR OUTPUT) pins: 51 I BL2 E15-4 INPUT DATA01-N (OMNIBUS DATA01) (8881 OPEN COLLECTOR OUTPUT) pins: 52 I BM2 E15-10 INPUT DATA02-N (OMNIBUS DATA02) (8881 OPEN COLLECTOR OUTPUT) pins: 53 P AF1 E4-3 OUTPUT I/O BUS ACIN0-N (75452 OPEN COLLECTOR OUTPUT) pins: 54 P AH1 E5-3 OUTPUT I/O BUS ACIN1-N (75452 OPEN COLLECTOR OUTPUT) pins: 55 P AJ1 E8-5 OUTPUT I/O BUS ACIN2-N (75452 OPEN COLLECTOR OUTPUT) pins: 56 P AF2 E7-5 OUTPUT I/O BUS DATA0-N (75452 OPEN COLLECTOR OUTPUT) pins: 57 P AH2 E3-3 OUTPUT I/O BUS DATA1-N (75452 OPEN COLLECTOR OUTPUT) pins: 58 P AJ2 E7-3 OUTPUT I/O BUS DATA2-N (75452 OPEN COLLECTOR OUTPUT) pins: direction: IPIPIPIOIOIOOIOOIPOIOIIOIIOIIOIPIPIPIPIPOIPIOIIIIIIIPPPPPP test 1: 0101010000001001001010010010010000000000101010000111111111 comment: comment: ; INPUT 1 -> OUTPUT 1-N test 2: 10 test 3: 01 comment: comment: ; INPUT 2 -> OUTPUT 2-N test 4: 10 test 5: 01 comment: comment: ; INPUT 3 -> OUTPUT 3-N test 6: 10 test 7: 01 comment: comment: ; INPUT 4 -> OUTPUT 4 test 8: 11 test 9: 00 comment: comment: ; INPUT 5 -> OUTPUT 5 test 10: 11 test 11: 00 comment: comment: ; INPUT 6 -> OUTPUT 6, OUTPUT 6-N test 12: 110 test 13: 001 comment: comment: ; INPUT 7 -> OUTPUT 7, OUTPUT 7-N test 14: 110 test 15: 001 comment: comment: ; INPUT 8 -> OUTPUT 8, OUTPUT 8-N test 16: 110 test 17: 001 comment: comment: ; INPUT 9 -> OOUTPUT 9-N test 18: 10 test 19: 01 comment: comment: ; INPUT 10A NOR INPUT 10B -> OUTPUT 10 test 20: 010 test 21: 110 test 22: 100 test 23: 001 comment: comment: ; INPUT 11A NOR INPUT 11B -> OUTPUT 11 test 24: 010 test 25: 110 test 26: 100 test 27: 001 comment: comment: ; INPUT 12A NAND INPUT 12B -> OUTPUT 12 test 28: 011 test 29: 110 test 30: 101 test 31: 001 comment: comment: ; INPUT 13 -> OUTPUT 13 test 32: 11 test 33: 00 comment: comment: ; INPUT 14 -> OUTPUT 14 test 34: 11 test 35: 00 comment: comment: ; INPUT 15 -> OUTPUT 15 test 36: 11 test 37: 00 comment: comment: ; INPUT 16 -> OUTPUT 16 test 38: 11 test 39: 00 comment: comment: ; INPUT 17 -> OUTPUT 17, OUTPUT 17-N test 40: 110 test 41: 001 comment: comment: ; INPUT 18 -> OUTPUT 18-N test 42: 10 test 43: 01 comment: comment: ; (no change) test 44: 0101010000001001001010010010010000000000101010000111111111 comment: comment: comment: comment: ; PART 2 unique tests (Omnibus DATA00:02-N driving Posibus ACIN and DATA) comment: comment: ; (See PART 1 for Posibus driving Omnibus). comment: comment: comment: comment: ; Select Omnibus DATA00:02-N -> Posibus DATA0:2-N comment: comment: ; OMNIBUS DATA TO I/O DATA-N LO, OUT-N HI; OMNIBUS DATA TO I/O DATA -> HI test 45: 011 comment: ; (no change) test 46: 000111111111 comment: comment: ; All DATA00:02-N patterns (Posibus ACIN0:2-N always HI). test 47: 101 101 test 48: 100 100 test 49: 000 000 test 50: 001 001 test 51: 011 011 test 52: 010 010 test 53: 110 110 test 54: 111 111 comment: comment: comment: comment: ; Select Omnibus DATA00:02-N -> PosiBus ACIN0:2-N comment: comment: ; OMNIBUS DATA TO I/O DATA-N HI, OUT-N HI; OMNIBUS DATA TO I/O DATA -> LO test 55: 101 comment: ; (no change) test 56: 000111111111 comment: comment: ; All DATA00:02-N patterns (Posibus DATA0:2-N always HI). test 57: 101101 test 58: 100100 test 59: 000000 test 60: 001001 test 61: 011011 test 62: 010010 test 63: 110110 test 64: 111111 comment: comment: comment: ; Do not select Posibus BAC0:2 -> Omnibus DATA00:02-N comment: ; (we drive Omnibus DATA00:02-N in PART 2). comment: ; skip >>>>> 100 comment: comment: comment: comment: ; Select Omnibus DATA00:02-N -> Posibus DATA0:2-N comment: comment: ; Do 2 steps to avoid >>>>> 100 comment: ; OMNIBUS DATA TO I/O DATA-N LO, OUT-N HI; OMNIBUS DATA TO I/O DATA -> HI test 65: 011 comment: comment: ; OMNIBUS DATA TO I/O DATA-N LO, OUT-N LO; OMNIBUS DATA TO I/O DATA -> HI test 66: 010 comment: ; (no change) test 67: 000111111111 comment: comment: ; All DATA00:02-N patterns (Posibus ACIN0:2-N always HI). test 68: 101 101 test 69: 100 100 test 70: 000 000 test 71: 001 001 test 72: 011 011 test 73: 010 010 test 74: 110 110 test 75: 111 111 comment: comment: ; (no change) test 76: 0101010000001001001010010010010000000000101010000111111111 end: END summary column 1: offset 1, mask 0x1000 column 2: offset 2, mask 0x0080 column 3: offset 1, mask 0x0800 column 4: offset 3, mask 0x0001 column 5: offset 1, mask 0x0400 column 6: offset 3, mask 0x0002 column 7: offset 1, mask 0x0001 column 8: offset 1, mask 0x0008 column 9: offset 1, mask 0x0002 column 10: offset 1, mask 0x0004 column 11: offset 1, mask 0x0010 column 12: offset 1, mask 0x0080 column 13: offset 2, mask 0x1000 column 14: offset 1, mask 0x0020 column 15: offset 1, mask 0x0040 column 16: offset 2, mask 0x2000 column 17: offset 2, mask 0x0400 column 18: offset 4, mask 0x0008 column 19: offset 2, mask 0x0800 column 20: offset 2, mask 0x4000 column 21: offset 2, mask 0x8000 column 22: offset 3, mask 0x1000 column 23: offset 3, mask 0x2000 column 24: offset 3, mask 0x0800 column 25: offset 3, mask 0x4000 column 26: offset 3, mask 0x8000 column 27: offset 2, mask 0x0100 column 28: offset 3, mask 0x0100 column 29: offset 4, mask 0x8000 column 30: offset 3, mask 0x0200 column 31: offset 3, mask 0x0020 column 32: offset 0, mask 0x1000 column 33: offset 3, mask 0x0040 column 34: offset 0, mask 0x0800 column 35: offset 3, mask 0x0080 column 36: offset 0, mask 0x0010 column 37: offset 4, mask 0x0001 column 38: offset 0, mask 0x0008 column 39: offset 4, mask 0x2000 column 40: offset 0, mask 0x4000 column 41: offset 4, mask 0x0004 column 42: offset 4, mask 0x1000 column 43: offset 0, mask 0x8000 column 44: offset 2, mask 0x0020 column 45: offset 2, mask 0x0200 column 46: offset 2, mask 0x0040 column 47: offset 1, mask 0x8000 column 48: offset 1, mask 0x4000 column 49: offset 1, mask 0x2000 column 50: offset 3, mask 0x0004 column 51: offset 3, mask 0x0008 column 52: offset 3, mask 0x0010 column 53: offset 0, mask 0x0400 column 54: offset 0, mask 0x0200 column 55: offset 0, mask 0x0100 column 56: offset 0, mask 0x0004 column 57: offset 0, mask 0x0002 column 58: offset 0, mask 0x0001 direction bits (1=input) 0xFFFF 0x03CC 0xBB9B 0x0E03 0x40FE pullup bits (1=pullup) 0xDF1F 0x0000 0x0080 0x0003 0x0008 test step out_data dont care 1: 0x8707 0x0000 0xBB80 0x0A1F 0x0004 2: 0x8707 0x1000 0xBB00 0x0A1F 0x0004 3: 0x8707 0x0000 0xBB80 0x0A1F 0x0004 4: 0x8707 0x0800 0xBB80 0x0A1E 0x0004 5: 0x8707 0x0000 0xBB80 0x0A1F 0x0004 6: 0x8707 0x0400 0xBB80 0x0A1D 0x0004 7: 0x8707 0x0000 0xBB80 0x0A1F 0x0004 8: 0x8707 0x0009 0xBB80 0x0A1F 0x0004 9: 0x8707 0x0000 0xBB80 0x0A1F 0x0004 10: 0x8707 0x0006 0xBB80 0x0A1F 0x0004 11: 0x8707 0x0000 0xBB80 0x0A1F 0x0004 12: 0x8707 0x0090 0xAB80 0x0A1F 0x0004 13: 0x8707 0x0000 0xBB80 0x0A1F 0x0004 14: 0x8707 0x0060 0x9B80 0x0A1F 0x0004 15: 0x8707 0x0000 0xBB80 0x0A1F 0x0004 16: 0x8707 0x0000 0xB780 0x0A1F 0x000C 17: 0x8707 0x0000 0xBB80 0x0A1F 0x0004 18: 0x8707 0x0000 0x7B80 0x0A1F 0x0004 19: 0x8707 0x0000 0xBB80 0x0A1F 0x0004 20: 0x8707 0x0000 0xBB80 0x221F 0x0004 21: 0x8707 0x0000 0xBB80 0x321F 0x0004 22: 0x8707 0x0000 0xBB80 0x121F 0x0004 23: 0x8707 0x0000 0xBB80 0x0A1F 0x0004 24: 0x8707 0x0000 0xBA80 0x8A1F 0x0004 25: 0x8707 0x0000 0xBA80 0xCA1F 0x0004 26: 0x8707 0x0000 0xBA80 0x4A1F 0x0004 27: 0x8707 0x0000 0xBB80 0x0A1F 0x0004 28: 0x8707 0x0000 0xBB80 0x0A1F 0x8004 29: 0x8707 0x0000 0xBB80 0x091F 0x8004 30: 0x8707 0x0000 0xBB80 0x0B1F 0x0004 31: 0x8707 0x0000 0xBB80 0x0A1F 0x0004 32: 0x9707 0x0000 0xBB80 0x0A3F 0x0004 33: 0x8707 0x0000 0xBB80 0x0A1F 0x0004 34: 0x8F07 0x0000 0xBB80 0x0A5F 0x0004 35: 0x8707 0x0000 0xBB80 0x0A1F 0x0004 36: 0x8717 0x0000 0xBB80 0x0A9F 0x0004 37: 0x8707 0x0000 0xBB80 0x0A1F 0x0004 38: 0x870F 0x0000 0xBB80 0x0A1F 0x0005 39: 0x8707 0x0000 0xBB80 0x0A1F 0x0004 40: 0xC707 0x0000 0xBB80 0x0A1F 0x2000 41: 0x8707 0x0000 0xBB80 0x0A1F 0x0004 42: 0x0707 0x0000 0xBB80 0x0A1F 0x1004 43: 0x8707 0x0000 0xBB80 0x0A1F 0x0004 44: 0x8707 0x0000 0xBB80 0x0A1F 0x0004 45: 0x8707 0x0000 0xBBC0 0x0A1F 0x0004 46: 0x8707 0x0000 0xBBC0 0x0A1F 0x0004 47: 0x8705 0x0000 0xBBC0 0x0A17 0x0004 48: 0x8704 0x0000 0xBBC0 0x0A07 0x0004 49: 0x8700 0x0000 0xBBC0 0x0A03 0x0004 50: 0x8701 0x0000 0xBBC0 0x0A13 0x0004 51: 0x8703 0x0000 0xBBC0 0x0A1B 0x0004 52: 0x8702 0x0000 0xBBC0 0x0A0B 0x0004 53: 0x8706 0x0000 0xBBC0 0x0A0F 0x0004 54: 0x8707 0x0000 0xBBC0 0x0A1F 0x0004 55: 0x8707 0x0000 0xB9E0 0x0A1F 0x0004 56: 0x8707 0x0000 0xB9E0 0x0A1F 0x0004 57: 0x8507 0x0000 0xB9E0 0x0A17 0x0004 58: 0x8407 0x0000 0xB9E0 0x0A07 0x0004 59: 0x8007 0x0000 0xB9E0 0x0A03 0x0004 60: 0x8107 0x0000 0xB9E0 0x0A13 0x0004 61: 0x8307 0x0000 0xB9E0 0x0A1B 0x0004 62: 0x8207 0x0000 0xB9E0 0x0A0B 0x0004 63: 0x8607 0x0000 0xB9E0 0x0A0F 0x0004 64: 0x8707 0x0000 0xB9E0 0x0A1F 0x0004 65: 0x8707 0x0000 0xBBC0 0x0A1F 0x0004 66: 0x8707 0x0000 0xBB80 0x0A1F 0x0004 67: 0x8707 0x0000 0xBB80 0x0A1F 0x0004 68: 0x8705 0x0000 0xBB80 0x0A17 0x0004 69: 0x8704 0x0000 0xBB80 0x0A07 0x0004 70: 0x8700 0x0000 0xBB80 0x0A03 0x0004 71: 0x8701 0x0000 0xBB80 0x0A13 0x0004 72: 0x8703 0x0000 0xBB80 0x0A1B 0x0004 73: 0x8702 0x0000 0xBB80 0x0A0B 0x0004 74: 0x8706 0x0000 0xBB80 0x0A0F 0x0004 75: 0x8707 0x0000 0xBB80 0x0A1F 0x0004 76: 0x8707 0x0000 0xBB80 0x0A1F 0x0004 PINs used (in edge connector order) (G=ground,P=power) SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBB LETTER ABCDEFHJKLMNPRSTUVABCDEFHJKLMNPRSTUVABCDEFHJKLMNPRSTUVABCDEFHJKLMNPRSTUV SIDE 111111111111111111222222222222222222111111111111111111222222222222222222 USAGE PP PPPPPIIIIII GOIP GPPPPPIIOOIIOO OOOIOOIIIIO OIIGIIP GIIPPPIIIIIII OP UUT inputs: 29 UUT outputs: 29 pins used: 58 not used: 8 76 'test steps' 231 lines M7102 PCB REV D SCHEMATIC REV C Positive I/O Bus Converter (DW08E) PART 2 Tests Omnibus DATA BUS driving Posibus ACIN and DATA. (See PART 1 for Posibus driving Omnibus. (Two parts are necessary due to the Omnibus DATA00:02-N is a bidirectional bus). Tolerates 3.3k ohm pullups to +5v on pin (are needed for PART 1): BK2 Omnibus DATA00 (bidirectional, input + open collector output) BL2 Omnibus DATA01 (bidirectional, input + open collector output) BM2 Omnibus DATA02 (bidirectional, input + open collector output) PINS Main menu Sun Nov 22 18:55:42 2015 test file is: tests\m7102_2.tst delay is: 0 trigger is: 1 1 read test file 2 set test delay 3 set test trigger 4 run test 5 output loading test 8 diags 9 exit UUT power is okay Sun Nov 22 18:55:43 2015 space single step O run once (one test, all steps) F run, stop on fail G go (run tests N run, stop on fail, no print S scope (run, no print) C toggle comment printout + increase speed (less delay) - decrease speed (more delay)(slower) Q quit test scope (run, no print) pppppppppppppppppppppppppppppppppppppppppppppppppp space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C toggle comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT ABABABAAAAAABAABBBBAABBBBBBBBBBABABABABABBABBBAAABBBAAAAAA LETTER NFPHRJKNLMPTBRSADVCVULKMJHFRSPNDPERDSEUBUVADEEKLMKLMFHJFHJ SIDE 1212122222221221121111111111112121222211211212111222111222 DIRECTION IPIPIPIOIOIOOIOOIPOIOIIOIIOIIOIPIPIPIPIPOIPIOIIIIIIIPPPPPP all fails was lo 0000000000000000000000000000000000000000000000000000000000 falling vvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvv vvvvvvvvv rising ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ ^^^^^^^^^ was hi 1111111111111111111111111111111111111111111111 111111111 total fails 0, total passes 50 Main menu Sun Nov 22 18:55:46 2015 test file is: tests\m7102_2.tst delay is: 0 trigger is: 1 1 read test file 2 set test delay 3 set test trigger 4 run test 5 output loading test 8 diags 9 exit UUT power is okay Sun Nov 22 18:58:30 2015 space single step O run once (one test, all steps) F run, stop on fail G go (run tests N run, stop on fail, no print S scope (run, no print) C toggle comment printout + increase speed (less delay) - decrease speed (more delay)(slower) Q quit test scope (run, no print) FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C toggle comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit step 5 0101010000001001001010010010010000000000101010000111111111 step 6 0101100000001001001010010010010000000000101010000111111111 step 7 0101010000001001001010010010010000000000101010000111111111 step 8 0101011100001001001010010010010000000000101010000111111111 step 9 0101010000001001001010010010010000000000101010000111111111 step 10 0101010011001001001010010010010000000000101010000111111111 step 11 0101010000001001001010010010010000000000101010000111111111 step 12 0101010000110001001010010010010000000000101010000111111111 step 13 0101010000001001001010010010010000000000101010000111111111 step 14 0101010000001110001010010010010000000000101010000111111111 step 15 0101010000001001001010010010010000000000101010000111111111 step 16 0101010000001001110010010010010000000000101010000111111111 step 17 0101010000001001001010010010010000000000101010000111111111 step 18 0101010000001001001100010010010000000000101010000111111111 step 19 0101010000001001001010010010010000000000101010000111111111 step 20 0101010000001001001010100010010000000000101010000111111111 step 21 0101010000001001001011100010010000000000101010000111111111 step 22 0101010000001001001011000010010000000000101010000111111111 step 23 0101010000001001001010010010010000000000101010000111111111 step 24 0101010000001001001010010100010000000000101010000111111111 step 25 0101010000001001001010011100010000000000101010000111111111 step 26 0101010000001001001010011000010000000000101010000111111111 step 27 0101010000001001001010010010010000000000101010000111111111 step 28 0101010000001001001010010010110000000000101010000111111111 step 29 0101010000001001001010010011100000000000101010000111111111 step 30 0101010000001001001010010011010000000000101010000111111111 step 31 0101010000001001001010010010010000000000101010000111111111 step 32 0101010000001001001010010010011100000000101010000111111111 step 33 0101010000001001001010010010010000000000101010000111111111 SLOT ABABABAAAAAABAABBBBAABBBBBBBBBBABABABABABBABBBAAABBBAAAAAA LETTER NFPHRJKNLMPTBRSADVCVULKMJHFRSPNDPERDSEUBUVADEEKLMKLMFHJFHJ SIDE 1212122222221221121111111111112121222211211212111222111222 DIRECTION IPIPIPIOIOIOOIOOIPOIOIIOIIOIIOIPIPIPIPIPOIPIOIIIIIIIPPPPPP changed: 1 step 34 0101010000001001001010010010010010000000101010000111111111 fail ^ step 35 0101010000001001001010010010010000000000101010000111111111 SLOT ABABABAAAAAABAABBBBAABBBBBBBBBBABABABABABBABBBAAABBBAAAAAA LETTER NFPHRJKNLMPTBRSADVCVULKMJHFRSPNDPERDSEUBUVADEEKLMKLMFHJFHJ SIDE 1212122222221221121111111111112121222211211212111222111222 DIRECTION IPIPIPIOIOIOOIOOIPOIOIIOIIOIIOIPIPIPIPIPOIPIOIIIIIIIPPPPPP changed: 1 step 36 0101010000001001001010010010010000100000101010000111111111 fail ^ step 37 0101010000001001001010010010010000000000101010000111111111 SLOT ABABABAAAAAABAABBBBAABBBBBBBBBBABABABABABBABBBAAABBBAAAAAA LETTER NFPHRJKNLMPTBRSADVCVULKMJHFRSPNDPERDSEUBUVADEEKLMKLMFHJFHJ SIDE 1212122222221221121111111111112121222211211212111222111222 DIRECTION IPIPIPIOIOIOOIOOIPOIOIIOIIOIIOIPIPIPIPIPOIPIOIIIIIIIPPPPPP changed: 1 step 38 0101010000001001001010010010010000001000101010000111111111 fail ^ SLOT ABABABAAAAAABAABBBBAABBBBBBBBBBABABABABABBABBBAAABBBAAAAAA LETTER NFPHRJKNLMPTBRSADVCVULKMJHFRSPNDPERDSEUBUVADEEKLMKLMFHJFHJ SIDE 1212122222221221121111111111112121222211211212111222111222 DIRECTION IPIPIPIOIOIOOIOOIPOIOIIOIIOIIOIPIPIPIPIPOIPIOIIIIIIIPPPPPP changed: 0 0 step 39 0101010000001001001010010010010000000000001010000111111111 fail ^ step 40 0101010000001001001010010010010000000011001010000111111111 SLOT ABABABAAAAAABAABBBBAABBBBBBBBBBABABABABABBABBBAAABBBAAAAAA LETTER NFPHRJKNLMPTBRSADVCVULKMJHFRSPNDPERDSEUBUVADEEKLMKLMFHJFHJ SIDE 1212122222221221121111111111112121222211211212111222111222 DIRECTION IPIPIPIOIOIOOIOOIPOIOIIOIIOIIOIPIPIPIPIPOIPIOIIIIIIIPPPPPP changed: 00 step 41 0101010000001001001010010010010000000000001010000111111111 fail ^ SLOT ABABABAAAAAABAABBBBAABBBBBBBBBBABABABABABBABBBAAABBBAAAAAA LETTER NFPHRJKNLMPTBRSADVCVULKMJHFRSPNDPERDSEUBUVADEEKLMKLMFHJFHJ SIDE 1212122222221221121111111111112121222211211212111222111222 DIRECTION IPIPIPIOIOIOOIOOIPOIOIIOIIOIIOIPIPIPIPIPOIPIOIIIIIIIPPPPPP changed: 10 step 42 0101010000001001001010010010010000000000010010000111111111 fail ^ SLOT ABABABAAAAAABAABBBBAABBBBBBBBBBABABABABABBABBBAAABBBAAAAAA LETTER NFPHRJKNLMPTBRSADVCVULKMJHFRSPNDPERDSEUBUVADEEKLMKLMFHJFHJ SIDE 1212122222221221121111111111112121222211211212111222111222 DIRECTION IPIPIPIOIOIOOIOOIPOIOIIOIIOIIOIPIPIPIPIPOIPIOIIIIIIIPPPPPP changed: 01 step 43 0101010000001001001010010010010000000000001010000111111111 fail ^ SLOT ABABABAAAAAABAABBBBAABBBBBBBBBBABABABABABBABBBAAABBBAAAAAA LETTER NFPHRJKNLMPTBRSADVCVULKMJHFRSPNDPERDSEUBUVADEEKLMKLMFHJFHJ SIDE 1212122222221221121111111111112121222211211212111222111222 DIRECTION IPIPIPIOIOIOOIOOIPOIOIIOIIOIIOIPIPIPIPIPOIPIOIIIIIIIPPPPPP changed: step 44 0101010000001001001010010010010000000000001010000111111111 fail ^ SLOT ABABABAAAAAABAABBBBAABBBBBBBBBBABABABABABBABBBAAABBBAAAAAA LETTER NFPHRJKNLMPTBRSADVCVULKMJHFRSPNDPERDSEUBUVADEEKLMKLMFHJFHJ SIDE 1212122222221221121111111111112121222211211212111222111222 DIRECTION IPIPIPIOIOIOOIOOIPOIOIIOIIOIIOIPIPIPIPIPOIPIOIIIIIIIPPPPPP changed: 1 step 45 0101010000001001001010010010010000000000001011000111111111 fail ^ SLOT ABABABAAAAAABAABBBBAABBBBBBBBBBABABABABABBABBBAAABBBAAAAAA LETTER NFPHRJKNLMPTBRSADVCVULKMJHFRSPNDPERDSEUBUVADEEKLMKLMFHJFHJ SIDE 1212122222221221121111111111112121222211211212111222111222 DIRECTION IPIPIPIOIOIOOIOOIPOIOIIOIIOIIOIPIPIPIPIPOIPIOIIIIIIIPPPPPP changed: step 46 0101010000001001001010010010010000000000001011000111111111 fail ^ SLOT ABABABAAAAAABAABBBBAABBBBBBBBBBABABABABABBABBBAAABBBAAAAAA LETTER NFPHRJKNLMPTBRSADVCVULKMJHFRSPNDPERDSEUBUVADEEKLMKLMFHJFHJ SIDE 1212122222221221121111111111112121222211211212111222111222 DIRECTION IPIPIPIOIOIOOIOOIPOIOIIOIIOIIOIPIPIPIPIPOIPIOIIIIIIIPPPPPP changed: 0 0 step 47 0101010000001001001010010010010000000000001011000101111101 fail ^ SLOT ABABABAAAAAABAABBBBAABBBBBBBBBBABABABABABBABBBAAABBBAAAAAA LETTER NFPHRJKNLMPTBRSADVCVULKMJHFRSPNDPERDSEUBUVADEEKLMKLMFHJFHJ SIDE 1212122222221221121111111111112121222211211212111222111222 DIRECTION IPIPIPIOIOIOOIOOIPOIOIIOIIOIIOIPIPIPIPIPOIPIOIIIIIIIPPPPPP changed: 0 0 step 48 0101010000001001001010010010010000000000001011000100111100 fail ^ SLOT ABABABAAAAAABAABBBBAABBBBBBBBBBABABABABABBABBBAAABBBAAAAAA LETTER NFPHRJKNLMPTBRSADVCVULKMJHFRSPNDPERDSEUBUVADEEKLMKLMFHJFHJ SIDE 1212122222221221121111111111112121222211211212111222111222 DIRECTION IPIPIPIOIOIOOIOOIPOIOIIOIIOIIOIPIPIPIPIPOIPIOIIIIIIIPPPPPP changed: 0 0 step 49 0101010000001001001010010010010000000000001011000000111000 fail ^ SLOT ABABABAAAAAABAABBBBAABBBBBBBBBBABABABABABBABBBAAABBBAAAAAA LETTER NFPHRJKNLMPTBRSADVCVULKMJHFRSPNDPERDSEUBUVADEEKLMKLMFHJFHJ SIDE 1212122222221221121111111111112121222211211212111222111222 DIRECTION IPIPIPIOIOIOOIOOIPOIOIIOIIOIIOIPIPIPIPIPOIPIOIIIIIIIPPPPPP changed: 1 1 step 50 0101010000001001001010010010010000000000001011000001111001 fail ^ SLOT ABABABAAAAAABAABBBBAABBBBBBBBBBABABABABABBABBBAAABBBAAAAAA LETTER NFPHRJKNLMPTBRSADVCVULKMJHFRSPNDPERDSEUBUVADEEKLMKLMFHJFHJ SIDE 1212122222221221121111111111112121222211211212111222111222 DIRECTION IPIPIPIOIOIOOIOOIPOIOIIOIIOIIOIPIPIPIPIPOIPIOIIIIIIIPPPPPP changed: 1 1 step 51 0101010000001001001010010010010000000000001011000011111011 fail ^ SLOT ABABABAAAAAABAABBBBAABBBBBBBBBBABABABABABBABBBAAABBBAAAAAA LETTER NFPHRJKNLMPTBRSADVCVULKMJHFRSPNDPERDSEUBUVADEEKLMKLMFHJFHJ SIDE 1212122222221221121111111111112121222211211212111222111222 DIRECTION IPIPIPIOIOIOOIOOIPOIOIIOIIOIIOIPIPIPIPIPOIPIOIIIIIIIPPPPPP changed: 0 0 step 52 0101010000001001001010010010010000000000001011000010111010 fail ^ SLOT ABABABAAAAAABAABBBBAABBBBBBBBBBABABABABABBABBBAAABBBAAAAAA LETTER NFPHRJKNLMPTBRSADVCVULKMJHFRSPNDPERDSEUBUVADEEKLMKLMFHJFHJ SIDE 1212122222221221121111111111112121222211211212111222111222 DIRECTION IPIPIPIOIOIOOIOOIPOIOIIOIIOIIOIPIPIPIPIPOIPIOIIIIIIIPPPPPP changed: 1 1 step 53 0101010000001001001010010010010000000000001011000110111110 fail ^ SLOT ABABABAAAAAABAABBBBAABBBBBBBBBBABABABABABBABBBAAABBBAAAAAA LETTER NFPHRJKNLMPTBRSADVCVULKMJHFRSPNDPERDSEUBUVADEEKLMKLMFHJFHJ SIDE 1212122222221221121111111111112121222211211212111222111222 DIRECTION IPIPIPIOIOIOOIOOIPOIOIIOIIOIIOIPIPIPIPIPOIPIOIIIIIIIPPPPPP changed: 1 1 step 54 0101010000001001001010010010010000000000001011000111111111 fail ^ SLOT ABABABAAAAAABAABBBBAABBBBBBBBBBABABABABABBABBBAAABBBAAAAAA LETTER NFPHRJKNLMPTBRSADVCVULKMJHFRSPNDPERDSEUBUVADEEKLMKLMFHJFHJ SIDE 1212122222221221121111111111112121222211211212111222111222 DIRECTION IPIPIPIOIOIOOIOOIPOIOIIOIIOIIOIPIPIPIPIPOIPIOIIIIIIIPPPPPP changed: 10 step 55 0101010000001001001010010010010000000000001101000111111111 fail ^ SLOT ABABABAAAAAABAABBBBAABBBBBBBBBBABABABABABBABBBAAABBBAAAAAA LETTER NFPHRJKNLMPTBRSADVCVULKMJHFRSPNDPERDSEUBUVADEEKLMKLMFHJFHJ SIDE 1212122222221221121111111111112121222211211212111222111222 DIRECTION IPIPIPIOIOIOOIOOIPOIOIIOIIOIIOIPIPIPIPIPOIPIOIIIIIIIPPPPPP changed: step 56 0101010000001001001010010010010000000000001101000111111111 fail ^ SLOT ABABABAAAAAABAABBBBAABBBBBBBBBBABABABABABBABBBAAABBBAAAAAA LETTER NFPHRJKNLMPTBRSADVCVULKMJHFRSPNDPERDSEUBUVADEEKLMKLMFHJFHJ SIDE 1212122222221221121111111111112121222211211212111222111222 DIRECTION IPIPIPIOIOIOOIOOIPOIOIIOIIOIIOIPIPIPIPIPOIPIOIIIIIIIPPPPPP changed: 0 0 step 57 0101010000001001001010010010010000000000001101000101101111 fail ^ SLOT ABABABAAAAAABAABBBBAABBBBBBBBBBABABABABABBABBBAAABBBAAAAAA LETTER NFPHRJKNLMPTBRSADVCVULKMJHFRSPNDPERDSEUBUVADEEKLMKLMFHJFHJ SIDE 1212122222221221121111111111112121222211211212111222111222 DIRECTION IPIPIPIOIOIOOIOOIPOIOIIOIIOIIOIPIPIPIPIPOIPIOIIIIIIIPPPPPP changed: 0 0 step 58 0101010000001001001010010010010000000000001101000100100111 fail ^ SLOT ABABABAAAAAABAABBBBAABBBBBBBBBBABABABABABBABBBAAABBBAAAAAA LETTER NFPHRJKNLMPTBRSADVCVULKMJHFRSPNDPERDSEUBUVADEEKLMKLMFHJFHJ SIDE 1212122222221221121111111111112121222211211212111222111222 DIRECTION IPIPIPIOIOIOOIOOIPOIOIIOIIOIIOIPIPIPIPIPOIPIOIIIIIIIPPPPPP changed: 0 0 step 59 0101010000001001001010010010010000000000001101000000000111 fail ^ SLOT ABABABAAAAAABAABBBBAABBBBBBBBBBABABABABABBABBBAAABBBAAAAAA LETTER NFPHRJKNLMPTBRSADVCVULKMJHFRSPNDPERDSEUBUVADEEKLMKLMFHJFHJ SIDE 1212122222221221121111111111112121222211211212111222111222 DIRECTION IPIPIPIOIOIOOIOOIPOIOIIOIIOIIOIPIPIPIPIPOIPIOIIIIIIIPPPPPP changed: 1 1 step 60 0101010000001001001010010010010000000000001101000001001111 fail ^ SLOT ABABABAAAAAABAABBBBAABBBBBBBBBBABABABABABBABBBAAABBBAAAAAA LETTER NFPHRJKNLMPTBRSADVCVULKMJHFRSPNDPERDSEUBUVADEEKLMKLMFHJFHJ SIDE 1212122222221221121111111111112121222211211212111222111222 DIRECTION IPIPIPIOIOIOOIOOIPOIOIIOIIOIIOIPIPIPIPIPOIPIOIIIIIIIPPPPPP changed: 1 1 step 61 0101010000001001001010010010010000000000001101000011011111 fail ^ SLOT ABABABAAAAAABAABBBBAABBBBBBBBBBABABABABABBABBBAAABBBAAAAAA LETTER NFPHRJKNLMPTBRSADVCVULKMJHFRSPNDPERDSEUBUVADEEKLMKLMFHJFHJ SIDE 1212122222221221121111111111112121222211211212111222111222 DIRECTION IPIPIPIOIOIOOIOOIPOIOIIOIIOIIOIPIPIPIPIPOIPIOIIIIIIIPPPPPP changed: 0 0 step 62 0101010000001001001010010010010000000000001101000010010111 fail ^ SLOT ABABABAAAAAABAABBBBAABBBBBBBBBBABABABABABBABBBAAABBBAAAAAA LETTER NFPHRJKNLMPTBRSADVCVULKMJHFRSPNDPERDSEUBUVADEEKLMKLMFHJFHJ SIDE 1212122222221221121111111111112121222211211212111222111222 DIRECTION IPIPIPIOIOIOOIOOIPOIOIIOIIOIIOIPIPIPIPIPOIPIOIIIIIIIPPPPPP changed: 1 1 step 63 0101010000001001001010010010010000000000001101000110110111 fail ^ SLOT ABABABAAAAAABAABBBBAABBBBBBBBBBABABABABABBABBBAAABBBAAAAAA LETTER NFPHRJKNLMPTBRSADVCVULKMJHFRSPNDPERDSEUBUVADEEKLMKLMFHJFHJ SIDE 1212122222221221121111111111112121222211211212111222111222 DIRECTION IPIPIPIOIOIOOIOOIPOIOIIOIIOIIOIPIPIPIPIPOIPIOIIIIIIIPPPPPP changed: 1 1 step 64 0101010000001001001010010010010000000000001101000111111111 fail ^ SLOT ABABABAAAAAABAABBBBAABBBBBBBBBBABABABABABBABBBAAABBBAAAAAA LETTER NFPHRJKNLMPTBRSADVCVULKMJHFRSPNDPERDSEUBUVADEEKLMKLMFHJFHJ SIDE 1212122222221221121111111111112121222211211212111222111222 DIRECTION IPIPIPIOIOIOOIOOIPOIOIIOIIOIIOIPIPIPIPIPOIPIOIIIIIIIPPPPPP changed: 01 step 65 0101010000001001001010010010010000000000001011000111111111 fail ^ SLOT ABABABAAAAAABAABBBBAABBBBBBBBBBABABABABABBABBBAAABBBAAAAAA LETTER NFPHRJKNLMPTBRSADVCVULKMJHFRSPNDPERDSEUBUVADEEKLMKLMFHJFHJ SIDE 1212122222221221121111111111112121222211211212111222111222 DIRECTION IPIPIPIOIOIOOIOOIPOIOIIOIIOIIOIPIPIPIPIPOIPIOIIIIIIIPPPPPP changed: 0 step 66 0101010000001001001010010010010000000000001010000111111111 fail ^ SLOT ABABABAAAAAABAABBBBAABBBBBBBBBBABABABABABBABBBAAABBBAAAAAA LETTER NFPHRJKNLMPTBRSADVCVULKMJHFRSPNDPERDSEUBUVADEEKLMKLMFHJFHJ SIDE 1212122222221221121111111111112121222211211212111222111222 DIRECTION IPIPIPIOIOIOOIOOIPOIOIIOIIOIIOIPIPIPIPIPOIPIOIIIIIIIPPPPPP changed: step 67 0101010000001001001010010010010000000000001010000111111111 fail ^ SLOT ABABABAAAAAABAABBBBAABBBBBBBBBBABABABABABBABBBAAABBBAAAAAA LETTER NFPHRJKNLMPTBRSADVCVULKMJHFRSPNDPERDSEUBUVADEEKLMKLMFHJFHJ SIDE 1212122222221221121111111111112121222211211212111222111222 DIRECTION IPIPIPIOIOIOOIOOIPOIOIIOIIOIIOIPIPIPIPIPOIPIOIIIIIIIPPPPPP changed: 0 0 step 68 0101010000001001001010010010010000000000001010000101111101 fail ^ SLOT ABABABAAAAAABAABBBBAABBBBBBBBBBABABABABABBABBBAAABBBAAAAAA LETTER NFPHRJKNLMPTBRSADVCVULKMJHFRSPNDPERDSEUBUVADEEKLMKLMFHJFHJ SIDE 1212122222221221121111111111112121222211211212111222111222 DIRECTION IPIPIPIOIOIOOIOOIPOIOIIOIIOIIOIPIPIPIPIPOIPIOIIIIIIIPPPPPP changed: 0 0 step 69 0101010000001001001010010010010000000000001010000100111100 fail ^ SLOT ABABABAAAAAABAABBBBAABBBBBBBBBBABABABABABBABBBAAABBBAAAAAA LETTER NFPHRJKNLMPTBRSADVCVULKMJHFRSPNDPERDSEUBUVADEEKLMKLMFHJFHJ SIDE 1212122222221221121111111111112121222211211212111222111222 DIRECTION IPIPIPIOIOIOOIOOIPOIOIIOIIOIIOIPIPIPIPIPOIPIOIIIIIIIPPPPPP changed: 0 0 step 70 0101010000001001001010010010010000000000001010000000111000 fail ^ SLOT ABABABAAAAAABAABBBBAABBBBBBBBBBABABABABABBABBBAAABBBAAAAAA LETTER NFPHRJKNLMPTBRSADVCVULKMJHFRSPNDPERDSEUBUVADEEKLMKLMFHJFHJ SIDE 1212122222221221121111111111112121222211211212111222111222 DIRECTION IPIPIPIOIOIOOIOOIPOIOIIOIIOIIOIPIPIPIPIPOIPIOIIIIIIIPPPPPP changed: 1 1 step 71 0101010000001001001010010010010000000000001010000001111001 fail ^ SLOT ABABABAAAAAABAABBBBAABBBBBBBBBBABABABABABBABBBAAABBBAAAAAA LETTER NFPHRJKNLMPTBRSADVCVULKMJHFRSPNDPERDSEUBUVADEEKLMKLMFHJFHJ SIDE 1212122222221221121111111111112121222211211212111222111222 DIRECTION IPIPIPIOIOIOOIOOIPOIOIIOIIOIIOIPIPIPIPIPOIPIOIIIIIIIPPPPPP changed: 1 1 step 72 0101010000001001001010010010010000000000001010000011111011 fail ^ SLOT ABABABAAAAAABAABBBBAABBBBBBBBBBABABABABABBABBBAAABBBAAAAAA LETTER NFPHRJKNLMPTBRSADVCVULKMJHFRSPNDPERDSEUBUVADEEKLMKLMFHJFHJ SIDE 1212122222221221121111111111112121222211211212111222111222 DIRECTION IPIPIPIOIOIOOIOOIPOIOIIOIIOIIOIPIPIPIPIPOIPIOIIIIIIIPPPPPP changed: 0 0 step 73 0101010000001001001010010010010000000000001010000010111010 fail ^ SLOT ABABABAAAAAABAABBBBAABBBBBBBBBBABABABABABBABBBAAABBBAAAAAA LETTER NFPHRJKNLMPTBRSADVCVULKMJHFRSPNDPERDSEUBUVADEEKLMKLMFHJFHJ SIDE 1212122222221221121111111111112121222211211212111222111222 DIRECTION IPIPIPIOIOIOOIOOIPOIOIIOIIOIIOIPIPIPIPIPOIPIOIIIIIIIPPPPPP changed: 1 1 step 74 0101010000001001001010010010010000000000001010000110111110 fail ^ SLOT ABABABAAAAAABAABBBBAABBBBBBBBBBABABABABABBABBBAAABBBAAAAAA LETTER NFPHRJKNLMPTBRSADVCVULKMJHFRSPNDPERDSEUBUVADEEKLMKLMFHJFHJ SIDE 1212122222221221121111111111112121222211211212111222111222 DIRECTION IPIPIPIOIOIOOIOOIPOIOIIOIIOIIOIPIPIPIPIPOIPIOIIIIIIIPPPPPP changed: 1 1 step 75 0101010000001001001010010010010000000000001010000111111111 fail ^ SLOT ABABABAAAAAABAABBBBAABBBBBBBBBBABABABABABBABBBAAABBBAAAAAA LETTER NFPHRJKNLMPTBRSADVCVULKMJHFRSPNDPERDSEUBUVADEEKLMKLMFHJFHJ SIDE 1212122222221221121111111111112121222211211212111222111222 DIRECTION IPIPIPIOIOIOOIOOIPOIOIIOIIOIIOIPIPIPIPIPOIPIOIIIIIIIPPPPPP changed: step 76 0101010000001001001010010010010000000000001010000111111111 fail ^ test 62: *** FAIL *************************** 44 steps failed SLOT ABABABAAAAAABAABBBBAABBBBBBBBBBABABABABABBABBBAAABBBAAAAAA LETTER NFPHRJKNLMPTBRSADVCVULKMJHFRSPNDPERDSEUBUVADEEKLMKLMFHJFHJ SIDE 1212122222221221121111111111112121222211211212111222111222 DIRECTION IPIPIPIOIOIOOIOOIPOIOIIOIIOIIOIPIPIPIPIPOIPIOIIIIIIIPPPPPP this fail P P P O all fails P P P O was hi 111111111111111111111111111111111 1 1 11111111 111111111 rising ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ ^ ^ ^^^^^^^^ ^^^^^^^^^ falling vvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvv v v vvvvvvvv vvvvvvvvv was lo 0000000000000000000000000000000000000000000000000000000000 total fails 62, total passes 0 space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C toggle comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT ABABABAAAAAABAABBBBAABBBBBBBBBBABABABABABBABBBAAABBBAAAAAA LETTER NFPHRJKNLMPTBRSADVCVULKMJHFRSPNDPERDSEUBUVADEEKLMKLMFHJFHJ SIDE 1212122222221221121111111111112121222211211212111222111222 DIRECTION IPIPIPIOIOIOOIOOIPOIOIIOIIOIIOIPIPIPIPIPOIPIOIIIIIIIPPPPPP all fails P P P O was lo 0000000000000000000000000000000000000000000000000000000000 falling vvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvv v v vvvvvvvv vvvvvvvvv rising ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ ^ ^ ^^^^^^^^ ^^^^^^^^^ was hi 111111111111111111111111111111111 1 1 11111111 111111111 total fails 62, total passes 0 Main menu Sun Nov 22 18:58:53 2015 test file is: tests\m7102_2.tst delay is: 0 trigger is: 1 1 read test file 2 set test delay 3 set test trigger 4 run test 5 output loading test 8 diags 9 exit Enter test file name? trying to open test file: tests\m7102_1.tst reading test file: tests\m7102_1.tst comment: M7102 PCB REV D SCHEMATIC REV C Positive I/O Bus Converter (DW08E) comment: comment: PART 1 Tests Posibus driving Omnibus DATA BUS. comment: (See PART 2 for Omnibus driving Posibus. comment: comment: (Two parts are necessary due to the Omnibus DATA00:02-N is a bidirectional bus). comment: comment: Needs 3.3k ohm pullups to +5v on pin: comment: BK2 Omnibus DATA00 (bidirectional, input + open collector output) comment: BL2 Omnibus DATA01 (bidirectional, input + open collector output) comment: BM2 Omnibus DATA02 (bidirectional, input + open collector output) comment: pins: PINS pins: 1 I AN1 E6-9 INPUT 1 pins: 2 P BF2 E13-8 OUTPUT A-N (7416 OPEN COLLECTOR OUTPUT) pins: 3 I AP1 E6-6 INPUT 2 pins: 4 P BH2 E13-7 OUTPUT 2-N (7416 OPEN COLLECTOR OUTPUT) pins: 5 I AR1 E6-5 INPUT 3 pins: 6 P BJ2 E13-6 OUTPUT 3-N (7416 OPEN COLLECTOR OUTPUT) pins: 7 I AK2 E9-11 INPUT 4 pins: 8 O AN2 E9-13 OUTPUT 4 (384 OUTPUT) pins: 9 I AL2 E9-9 INPUT 5 pins: 10 O AM2 E9-14 OUTPUT 5 (384 OUTPUT) pins: 11 I AP2 E9-6 INPUT 6 pins: 12 O AT2 E9-2 OUTPUT 6 (384 OUTPUT) pins: 13 O BB1 E11-6 OUTPUT 6-N (74H04 OUTPUT) pins: 14 I AR2 E9-5 INPUT 7 pins: 15 O AS2 E9-3 OUTPUT 7 (384 OUTPUT) pins: 16 O BA1 E11-10 OUTPUT 7-N (74H04 OUTPUT) pins: 17 I BD1 E11-1 INPUT 8 pins: 18 P BV2 E13-12 OUTPUT 8 (7416 OPEN COLLECTOR OUTPUT) pins: 19 O BC1 E11-2 OUTPUT 8-N (74H04 OUTPUT) pins: 20 I AV1 E11-13 INPUT 9 pins: 21 O AU1 E11-12 OUTPUT 9-N (74H04 OUTPUT) pins: 22 I BL1 E12-4 INPUT 10A pins: 23 I BK1 E12-5 INPUT 10B pins: 24 O BM1 E12-3 OUTPUT 10 = INPUT 10A NOR INPUT 10B (380 OUTPUT) pins: 25 I BJ1 E12-9 INPUT 11A pins: 26 I BH1 E12-10 INPUT 11B pins: 27 O BF1 E12-14 OUTPUT 11 = INPUT 11A NOR INPUT 11B (M380 OUTPUT) pins: 28 I BR1 E15-12 INPUT 12A pins: 29 I BS1 E15-11 INPUT 12B pins: 30 O BP1 E15-? OUTPUT 12 = INPUT 12A NAND INPUT 12B (8881 OPEN COLLECTOR OUTPUT WITH 3.3K PULLUP) pins: 31 I BN2 E10-6,7 INPUT 13 pins: 32 P AD1 E1-3 OUTPUT 13 (75452 OPEN COLLECTOR OUTPUT) pins: 33 I BP2 E14-11,12 INPUT 14 pins: 34 P AE1 E2-3 OUTPUT 14 (75452 OPEN COLLECTOR OUTPUT) pins: 35 I BR2 E14-9,10 INPUT 15 pins: 36 P AD2 E5-5 OUTPUT 15 (75452 OPEN COLLECTOR OUTPUT) pins: 37 I BS2 E14-6,7 INPUT 16 pins: 38 P AE2 E4-5 OUTPUT 16 (75452 OPEN COLLECTOR OUTPUT) pins: 39 I BU1 E14-4,5 INPUT 17 pins: 40 P AB1 E4-5 OUTPUT 17 (75452 OPEN COLLECTOR OUTPUT) pins: 41 O BU2 E14-3 OUTPUT 17-N (380 OUTPUT) pins: 42 I BV1 E2-6,7 INPUT 18 pins: 43 P AA1 E2-5 OUTPUT 18-N (75452 OPEN COLLECTOR OUTPUT) pins: 44 I BD2 E11-3 OMNIBUS DATA TO I/O DATA-N (LOW ALSO DISABLES BAC <> OMNIBUS) pins: 45 O BE1 E11-4 OMNIBUS DATA TO I/O DATA (74H04 OUTPUT) pins: 46 I BE2 E12-12 INPUT OUT-N (L -> BAC TO OMNIBUS, H -> OMNIBUS TO BAC) pins: 47 I AK1 E3-6 INPUT BAC0 (DATA FROM I/O BUS) pins: 48 I AL1 E3-5 INPUT BAC1 (DATA FROM I/O BUS) pins: 49 I AM1 E6-11 INPUT BAC2 (DATA FROM I/O BUS) pins: 50 O BK2 E15-1 OUTPUT DATA00-N (OMNIBUS DATA00) (8881 OPEN COLLECTOR OUTPUT) pins: 51 O BL2 E15-4 OUTPUT DATA01-N (OMNIBUS DATA01) (8881 OPEN COLLECTOR OUTPUT) pins: 52 O BM2 E15-10 OUTPUT DATA02-N (OMNIBUS DATA02) (8881 OPEN COLLECTOR OUTPUT) pins: 53 P AF1 E4-3 OUTPUT I/O BUS ACIN0-N (75452 OPEN COLLECTOR OUTPUT) pins: 54 P AH1 E5-3 OUTPUT I/O BUS ACIN1-N (75452 OPEN COLLECTOR OUTPUT) pins: 55 P AJ1 E8-5 OUTPUT I/O BUS ACIN2-N (75452 OPEN COLLECTOR OUTPUT) pins: 56 P AF2 E7-5 OUTPUT I/O BUS DATA0-N (75452 OPEN COLLECTOR OUTPUT) pins: 57 P AH2 E3-3 OUTPUT I/O BUS DATA1-N (75452 OPEN COLLECTOR OUTPUT) pins: 58 P AJ2 E7-3 OUTPUT I/O BUS DATA2-N (75452 OPEN COLLECTOR OUTPUT) pins: direction: IPIPIPIOIOIOOIOOIPOIOIIOIIOIIOIPIPIPIPIPOIPIOIIIIOOOPPPPPP test 1: 0101010000001001001010010010010000000000101010000111111111 comment: comment: ; INPUT 1 -> OUTPUT 1-N test 2: 10 test 3: 01 comment: comment: ; INPUT 2 -> OUTPUT 2-N test 4: 10 test 5: 01 comment: comment: ; INPUT 3 -> OUTPUT 3-N test 6: 10 test 7: 01 comment: comment: ; INPUT 4 -> OUTPUT 4 test 8: 11 test 9: 00 comment: comment: ; INPUT 5 -> OUTPUT 5 test 10: 11 test 11: 00 comment: comment: ; INPUT 6 -> OUTPUT 6, OUTPUT 6-N test 12: 110 test 13: 001 comment: comment: ; INPUT 7 -> OUTPUT 7, OUTPUT 7-N test 14: 110 test 15: 001 comment: comment: ; INPUT 8 -> OUTPUT 8, OUTPUT 8-N test 16: 110 test 17: 001 comment: comment: ; INPUT 9 -> OOUTPUT 9-N test 18: 10 test 19: 01 comment: comment: ; INPUT 10A NOR INPUT 10B -> OUTPUT 10 test 20: 010 test 21: 110 test 22: 100 test 23: 001 comment: comment: ; INPUT 11A NOR INPUT 11B -> OUTPUT 11 test 24: 010 test 25: 110 test 26: 100 test 27: 001 comment: comment: ; INPUT 12A NAND INPUT 12B -> OUTPUT 12 test 28: 011 test 29: 110 test 30: 101 test 31: 001 comment: comment: ; INPUT 13 -> OUTPUT 13 test 32: 11 test 33: 00 comment: comment: ; INPUT 14 -> OUTPUT 14 test 34: 11 test 35: 00 comment: comment: ; INPUT 15 -> OUTPUT 15 test 36: 11 test 37: 00 comment: comment: ; INPUT 16 -> OUTPUT 16 test 38: 11 test 39: 00 comment: comment: ; INPUT 17 -> OUTPUT 17, OUTPUT 17-N test 40: 110 test 41: 001 comment: comment: ; INPUT 18 -> OUTPUT 18-N test 42: 10 test 43: 01 comment: comment: ; (no change) test 44: 0101010000001001001010010010010000000000101010000111111111 comment: comment: comment: comment: ; PART 1 unique tests (Posibus BAC0:2 driving Omnibus DATA00:02-N). comment: comment: ; (See PART 2 for Omnibus DATA00:02-N driving). comment: comment: comment: comment: ; Select Omnibus DATA00:02-N -> Posibus DATA0:2-N comment: comment: ; OMNIBUS DATA TO I/O DATA-N LO, OUT-N HI; OMNIBUS DATA TO I/O DATA -> HI test 45: 011 comment: ; (no change) test 46: 000111111111 comment: comment: ; All BAC0:2 patterns (Omnibus DATA00:02-N, Posibus ACIN0:2-N, Posibus DATA0:2-N always HI). comment: ; (Omnibus DATA00:02-N always high due to pullups and no drivers in PART 1 tests) test 47: 001 test 48: 011 test 49: 010 test 50: 110 test 51: 111 test 52: 101 test 53: 100 test 54: 000 comment: comment: comment: comment: ; Select Omnibus DATA00:02-N -> PosiBus ACIN0:2-N comment: comment: ; OMNIBUS DATA TO I/O DATA-N HI, OUT-N HI; OMNIBUS DATA TO I/O DATA -> LO test 55: 101 comment: ; (no change) test 56: 000111111111 comment: comment: ; All BAC0:2 patterns (Omnibus DATA00:02-N, Posibus ACIN0:2-N, Posibus DATA0:2-N always HI). comment: ; (Omnibus DATA00:02-N always high due to pullups and no drivers in PART 1 tests) test 57: 001 test 58: 011 test 59: 010 test 60: 110 test 61: 111 test 62: 101 test 63: 100 test 64: 000 comment: comment: comment: comment: ; Select Posibus BAC0:2 -> Omnibus DATA00:02-N comment: comment: ; OMNIBUS DATA TO I/O DATA-N HI, OUT-N LO; OMNIBUS DATA TO I/O DATA -> LO test 65: 100 comment: ; (no change) test 66: 000111111111 comment: comment: ; All BAC0:2 patterns (PosibusACIN0:2-N and Posibus DATA0:2-N always HI). test 67: 001110 test 68: 011100 test 69: 010101 test 70: 110001 test 71: 111000 test 72: 101010 test 73: 100011 test 74: 000111 comment: comment: comment: comment: ; Select Omnibus DATA00:02-N -> Posibus DATA0:2-N comment: comment: ; OMNIBUS DATA TO I/O DATA-N LO, OUT-N LO; OMNIBUS DATA TO I/O DATA -> HI test 75: 010 comment: ; (no change) test 76: 000111111111 comment: comment: ; All BAC0:2 patterns (Omnibus DATA00:02-N, Posibus ACIN0:2-N, Posibus DATA0:2-N always HI). comment: ; (Omnibus DATA00:02-N always high due to pullups and no drivers in PART 1 tests) test 77: 001 test 78: 011 test 79: 010 test 80: 110 test 81: 111 test 82: 101 test 83: 100 test 84: 000 test 85: comment: ; (no change) test 86: 0101010000001001001010010010010000000000101010000111111111 end: END summary column 1: offset 1, mask 0x1000 column 2: offset 2, mask 0x0080 column 3: offset 1, mask 0x0800 column 4: offset 3, mask 0x0001 column 5: offset 1, mask 0x0400 column 6: offset 3, mask 0x0002 column 7: offset 1, mask 0x0001 column 8: offset 1, mask 0x0008 column 9: offset 1, mask 0x0002 column 10: offset 1, mask 0x0004 column 11: offset 1, mask 0x0010 column 12: offset 1, mask 0x0080 column 13: offset 2, mask 0x1000 column 14: offset 1, mask 0x0020 column 15: offset 1, mask 0x0040 column 16: offset 2, mask 0x2000 column 17: offset 2, mask 0x0400 column 18: offset 4, mask 0x0008 column 19: offset 2, mask 0x0800 column 20: offset 2, mask 0x4000 column 21: offset 2, mask 0x8000 column 22: offset 3, mask 0x1000 column 23: offset 3, mask 0x2000 column 24: offset 3, mask 0x0800 column 25: offset 3, mask 0x4000 column 26: offset 3, mask 0x8000 column 27: offset 2, mask 0x0100 column 28: offset 3, mask 0x0100 column 29: offset 4, mask 0x8000 column 30: offset 3, mask 0x0200 column 31: offset 3, mask 0x0020 column 32: offset 0, mask 0x1000 column 33: offset 3, mask 0x0040 column 34: offset 0, mask 0x0800 column 35: offset 3, mask 0x0080 column 36: offset 0, mask 0x0010 column 37: offset 4, mask 0x0001 column 38: offset 0, mask 0x0008 column 39: offset 4, mask 0x2000 column 40: offset 0, mask 0x4000 column 41: offset 4, mask 0x0004 column 42: offset 4, mask 0x1000 column 43: offset 0, mask 0x8000 column 44: offset 2, mask 0x0020 column 45: offset 2, mask 0x0200 column 46: offset 2, mask 0x0040 column 47: offset 1, mask 0x8000 column 48: offset 1, mask 0x4000 column 49: offset 1, mask 0x2000 column 50: offset 3, mask 0x0004 column 51: offset 3, mask 0x0008 column 52: offset 3, mask 0x0010 column 53: offset 0, mask 0x0400 column 54: offset 0, mask 0x0200 column 55: offset 0, mask 0x0100 column 56: offset 0, mask 0x0004 column 57: offset 0, mask 0x0002 column 58: offset 0, mask 0x0001 direction bits (1=input) 0xFFFF 0x03CC 0xBB9B 0x0E1F 0x40FE pullup bits (1=pullup) 0xDF1F 0x0000 0x0080 0x0003 0x0008 test step out_data dont care 1: 0x8707 0x0000 0xBB80 0x0A1F 0x0004 2: 0x8707 0x1000 0xBB00 0x0A1F 0x0004 3: 0x8707 0x0000 0xBB80 0x0A1F 0x0004 4: 0x8707 0x0800 0xBB80 0x0A1E 0x0004 5: 0x8707 0x0000 0xBB80 0x0A1F 0x0004 6: 0x8707 0x0400 0xBB80 0x0A1D 0x0004 7: 0x8707 0x0000 0xBB80 0x0A1F 0x0004 8: 0x8707 0x0009 0xBB80 0x0A1F 0x0004 9: 0x8707 0x0000 0xBB80 0x0A1F 0x0004 10: 0x8707 0x0006 0xBB80 0x0A1F 0x0004 11: 0x8707 0x0000 0xBB80 0x0A1F 0x0004 12: 0x8707 0x0090 0xAB80 0x0A1F 0x0004 13: 0x8707 0x0000 0xBB80 0x0A1F 0x0004 14: 0x8707 0x0060 0x9B80 0x0A1F 0x0004 15: 0x8707 0x0000 0xBB80 0x0A1F 0x0004 16: 0x8707 0x0000 0xB780 0x0A1F 0x000C 17: 0x8707 0x0000 0xBB80 0x0A1F 0x0004 18: 0x8707 0x0000 0x7B80 0x0A1F 0x0004 19: 0x8707 0x0000 0xBB80 0x0A1F 0x0004 20: 0x8707 0x0000 0xBB80 0x221F 0x0004 21: 0x8707 0x0000 0xBB80 0x321F 0x0004 22: 0x8707 0x0000 0xBB80 0x121F 0x0004 23: 0x8707 0x0000 0xBB80 0x0A1F 0x0004 24: 0x8707 0x0000 0xBA80 0x8A1F 0x0004 25: 0x8707 0x0000 0xBA80 0xCA1F 0x0004 26: 0x8707 0x0000 0xBA80 0x4A1F 0x0004 27: 0x8707 0x0000 0xBB80 0x0A1F 0x0004 28: 0x8707 0x0000 0xBB80 0x0A1F 0x8004 29: 0x8707 0x0000 0xBB80 0x091F 0x8004 30: 0x8707 0x0000 0xBB80 0x0B1F 0x0004 31: 0x8707 0x0000 0xBB80 0x0A1F 0x0004 32: 0x9707 0x0000 0xBB80 0x0A3F 0x0004 33: 0x8707 0x0000 0xBB80 0x0A1F 0x0004 34: 0x8F07 0x0000 0xBB80 0x0A5F 0x0004 35: 0x8707 0x0000 0xBB80 0x0A1F 0x0004 36: 0x8717 0x0000 0xBB80 0x0A9F 0x0004 37: 0x8707 0x0000 0xBB80 0x0A1F 0x0004 38: 0x870F 0x0000 0xBB80 0x0A1F 0x0005 39: 0x8707 0x0000 0xBB80 0x0A1F 0x0004 40: 0xC707 0x0000 0xBB80 0x0A1F 0x2000 41: 0x8707 0x0000 0xBB80 0x0A1F 0x0004 42: 0x0707 0x0000 0xBB80 0x0A1F 0x1004 43: 0x8707 0x0000 0xBB80 0x0A1F 0x0004 44: 0x8707 0x0000 0xBB80 0x0A1F 0x0004 45: 0x8707 0x0000 0xBBC0 0x0A1F 0x0004 46: 0x8707 0x0000 0xBBC0 0x0A1F 0x0004 47: 0x8707 0x2000 0xBBC0 0x0A1F 0x0004 48: 0x8707 0x6000 0xBBC0 0x0A1F 0x0004 49: 0x8707 0x4000 0xBBC0 0x0A1F 0x0004 50: 0x8707 0xC000 0xBBC0 0x0A1F 0x0004 51: 0x8707 0xE000 0xBBC0 0x0A1F 0x0004 52: 0x8707 0xA000 0xBBC0 0x0A1F 0x0004 53: 0x8707 0x8000 0xBBC0 0x0A1F 0x0004 54: 0x8707 0x0000 0xBBC0 0x0A1F 0x0004 55: 0x8707 0x0000 0xB9E0 0x0A1F 0x0004 56: 0x8707 0x0000 0xB9E0 0x0A1F 0x0004 57: 0x8707 0x2000 0xB9E0 0x0A1F 0x0004 58: 0x8707 0x6000 0xB9E0 0x0A1F 0x0004 59: 0x8707 0x4000 0xB9E0 0x0A1F 0x0004 60: 0x8707 0xC000 0xB9E0 0x0A1F 0x0004 61: 0x8707 0xE000 0xB9E0 0x0A1F 0x0004 62: 0x8707 0xA000 0xB9E0 0x0A1F 0x0004 63: 0x8707 0x8000 0xB9E0 0x0A1F 0x0004 64: 0x8707 0x0000 0xB9E0 0x0A1F 0x0004 65: 0x8707 0x0000 0xB9A0 0x0A1F 0x0004 66: 0x8707 0x0000 0xB9A0 0x0A1F 0x0004 67: 0x8707 0x2000 0xB9A0 0x0A0F 0x0004 68: 0x8707 0x6000 0xB9A0 0x0A07 0x0004 69: 0x8707 0x4000 0xB9A0 0x0A17 0x0004 70: 0x8707 0xC000 0xB9A0 0x0A13 0x0004 71: 0x8707 0xE000 0xB9A0 0x0A03 0x0004 72: 0x8707 0xA000 0xB9A0 0x0A0B 0x0004 73: 0x8707 0x8000 0xB9A0 0x0A1B 0x0004 74: 0x8707 0x0000 0xB9A0 0x0A1F 0x0004 75: 0x8707 0x0000 0xBB80 0x0A1F 0x0004 76: 0x8707 0x0000 0xBB80 0x0A1F 0x0004 77: 0x8707 0x2000 0xBB80 0x0A1F 0x0004 78: 0x8707 0x6000 0xBB80 0x0A1F 0x0004 79: 0x8707 0x4000 0xBB80 0x0A1F 0x0004 80: 0x8707 0xC000 0xBB80 0x0A1F 0x0004 81: 0x8707 0xE000 0xBB80 0x0A1F 0x0004 82: 0x8707 0xA000 0xBB80 0x0A1F 0x0004 83: 0x8707 0x8000 0xBB80 0x0A1F 0x0004 84: 0x8707 0x0000 0xBB80 0x0A1F 0x0004 85: 0x8707 0x0000 0xBB80 0x0A1F 0x0004 86: 0x8707 0x0000 0xBB80 0x0A1F 0x0004 PINs used (in edge connector order) (G=ground,P=power) SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBB LETTER ABCDEFHJKLMNPRSTUVABCDEFHJKLMNPRSTUVABCDEFHJKLMNPRSTUVABCDEFHJKLMNPRSTUV SIDE 111111111111111111222222222222222222111111111111111111222222222222222222 USAGE PP PPPPPIIIIII GOIP GPPPPPIIOOIIOO OOOIOOIIIIO OIIGIIP GIIPPPOOOIIII OP UUT inputs: 26 UUT outputs: 32 pins used: 58 not used: 8 86 'test steps' 244 lines M7102 PCB REV D SCHEMATIC REV C Positive I/O Bus Converter (DW08E) PART 1 Tests Posibus driving Omnibus DATA BUS. (See PART 2 for Omnibus driving Posibus. (Two parts are necessary due to the Omnibus DATA00:02-N is a bidirectional bus). Needs 3.3k ohm pullups to +5v on pin: BK2 Omnibus DATA00 (bidirectional, input + open collector output) BL2 Omnibus DATA01 (bidirectional, input + open collector output) BM2 Omnibus DATA02 (bidirectional, input + open collector output) PINS Main menu Sun Nov 22 18:59:01 2015 test file is: tests\m7102_1.tst delay is: 0 trigger is: 1 1 read test file 2 set test delay 3 set test trigger 4 run test 5 output loading test 8 diags 9 exit UUT power is okay Sun Nov 22 18:59:03 2015 space single step O run once (one test, all steps) F run, stop on fail G go (run tests N run, stop on fail, no print S scope (run, no print) C toggle comment printout + increase speed (less delay) - decrease speed (more delay)(slower) Q quit test scope (run, no print) FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C toggle comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit step 68 0101010000001001001010010010010000000000101100011100111111 step 69 0101010000001001001010010010010000000000101100010101111111 step 70 0101010000001001001010010010010000000000101100110001111111 step 71 0101010000001001001010010010010000000000101100111000111111 step 72 0101010000001001001010010010010000000000101100101010111111 step 73 0101010000001001001010010010010000000000101100100011111111 step 74 0101010000001001001010010010010000000000101100000111111111 step 75 0101010000001001001010010010010000000000101010000111111111 step 76 0101010000001001001010010010010000000000101010000111111111 step 77 0101010000001001001010010010010000000000101010001111111111 step 78 0101010000001001001010010010010000000000101010011111111111 step 79 0101010000001001001010010010010000000000101010010111111111 step 80 0101010000001001001010010010010000000000101010110111111111 step 81 0101010000001001001010010010010000000000101010111111111111 step 82 0101010000001001001010010010010000000000101010101111111111 step 83 0101010000001001001010010010010000000000101010100111111111 step 84 0101010000001001001010010010010000000000101010000111111111 step 85 0101010000001001001010010010010000000000101010000111111111 step 86 0101010000001001001010010010010000000000101010000111111111 test 61: *** FAIL *************************** 30 steps failed SLOT ABABABAAAAAABAABBBBAABBBBBBBBBBABABABABABBABBBAAABBBAAAAAA LETTER NFPHRJKNLMPTBRSADVCVULKMJHFRSPNDPERDSEUBUVADEEKLMKLMFHJFHJ SIDE 1212122222221221121111111111112121222211211212111222111222 DIRECTION IPIPIPIOIOIOOIOOIPOIOIIOIIOIIOIPIPIPIPIPOIPIOIIIIOOOPPPPPP this fail P P P O all fails P P P O was hi 111111111111111111111111111111111 1 1 11111111111111111111 rising ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ ^ ^ ^^^^^^^^^^^^^^ falling vvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvv v v vvvvvvvvvvvvvv was lo 0000000000000000000000000000000000000000000000000000 total fails 61, total passes 0 space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C toggle comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit up to this point: PINS that are always low 34 P AE1 E2-3 OUTPUT 14 (75452 OPEN COLLECTOR OUTPUT) 36 P AD2 E5-5 OUTPUT 15 (75452 OPEN COLLECTOR OUTPUT) 38 P AE2 E4-5 OUTPUT 16 (75452 OPEN COLLECTOR OUTPUT) PINS that are always high 53 P AF1 E4-3 OUTPUT I/O BUS ACIN0-N (75452 OPEN COLLECTOR OUTPUT) 54 P AH1 E5-3 OUTPUT I/O BUS ACIN1-N (75452 OPEN COLLECTOR OUTPUT) 55 P AJ1 E8-5 OUTPUT I/O BUS ACIN2-N (75452 OPEN COLLECTOR OUTPUT) 56 P AF2 E7-5 OUTPUT I/O BUS DATA0-N (75452 OPEN COLLECTOR OUTPUT) 57 P AH2 E3-3 OUTPUT I/O BUS DATA1-N (75452 OPEN COLLECTOR OUTPUT) 58 P AJ2 E7-3 OUTPUT I/O BUS DATA2-N (75452 OPEN COLLECTOR OUTPUT) space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C toggle comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit failure mode analysis: pin: 34 P AE1 E2-3 OUTPUT 14 (75452 OPEN COLLECTOR OUTPUT) SLOT ABABABAAAAAABAABBBBAABBBBBBBBBBABABABABABBABBBAAABBBAAAAAA LETTER NFPHRJKNLMPTBRSADVCVULKMJHFRSPNDPERDSEUBUVADEEKLMKLMFHJFHJ SIDE 1212122222221221121111111111112121222211211212111222111222 DIRECTION IPIPIPIOIOIOOIOOIPOIOIIOIIOIIOIPIPIPIPIPOIPIOIIIIOOOPPPPPP fails LO: 1 1 1 1 1 1 1 1 1 1 1 1 1 1 111111111 fails LO: 0 0 0 000000 00 00 0 00 00 00 00 000000 0 0 0000 fails HI: fails HI: pin: 36 P AD2 E5-5 OUTPUT 15 (75452 OPEN COLLECTOR OUTPUT) SLOT ABABABAAAAAABAABBBBAABBBBBBBBBBABABABABABBABBBAAABBBAAAAAA LETTER NFPHRJKNLMPTBRSADVCVULKMJHFRSPNDPERDSEUBUVADEEKLMKLMFHJFHJ SIDE 1212122222221221121111111111112121222211211212111222111222 DIRECTION IPIPIPIOIOIOOIOOIPOIOIIOIIOIIOIPIPIPIPIPOIPIOIIIIOOOPPPPPP fails LO: 1 1 1 1 1 1 1 1 1 1 1 1 1 1 111111111 fails LO: 0 0 0 000000 00 00 0 00 00 00 0000 0000 0 0 0000 fails HI: fails HI: pin: 38 P AE2 E4-5 OUTPUT 16 (75452 OPEN COLLECTOR OUTPUT) SLOT ABABABAAAAAABAABBBBAABBBBBBBBBBABABABABABBABBBAAABBBAAAAAA LETTER NFPHRJKNLMPTBRSADVCVULKMJHFRSPNDPERDSEUBUVADEEKLMKLMFHJFHJ SIDE 1212122222221221121111111111112121222211211212111222111222 DIRECTION IPIPIPIOIOIOOIOOIPOIOIIOIIOIIOIPIPIPIPIPOIPIOIIIIOOOPPPPPP fails LO: 1 1 1 1 1 1 1 1 1 1 1 1 1 1 111111111 fails LO: 0 0 0 000000 00 00 0 00 00 00 000000 00 0 0 0000 fails HI: fails HI: pin: 41 O BU2 E14-3 OUTPUT 17-N (380 OUTPUT) SLOT ABABABAAAAAABAABBBBAABBBBBBBBBBABABABABABBABBBAAABBBAAAAAA LETTER NFPHRJKNLMPTBRSADVCVULKMJHFRSPNDPERDSEUBUVADEEKLMKLMFHJFHJ SIDE 1212122222221221121111111111112121222211211212111222111222 DIRECTION IPIPIPIOIOIOOIOOIPOIOIIOIIOIIOIPIPIPIPIPOIPIOIIIIOOOPPPPPP fails LO: 11111111111111111111111111111111 11111111111111111 fails LO: 0000000000000000000000000000000000000000 00000000000 fails HI: fails HI: space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C toggle comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT ABABABAAAAAABAABBBBAABBBBBBBBBBABABABABABBABBBAAABBBAAAAAA LETTER NFPHRJKNLMPTBRSADVCVULKMJHFRSPNDPERDSEUBUVADEEKLMKLMFHJFHJ SIDE 1212122222221221121111111111112121222211211212111222111222 DIRECTION IPIPIPIOIOIOOIOOIPOIOIIOIIOIIOIPIPIPIPIPOIPIOIIIIOOOPPPPPP all fails P P P O was lo 0000000000000000000000000000000000000000000000000000 falling vvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvv v v vvvvvvvvvvvvvv rising ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ ^ ^ ^^^^^^^^^^^^^^ was hi 111111111111111111111111111111111 1 1 11111111111111111111 total fails 61, total passes 0 Main menu Sun Nov 22 18:59:38 2015 test file is: tests\m7102_1.tst delay is: 0 trigger is: 1 1 read test file 2 set test delay 3 set test trigger 4 run test 5 output loading test 8 diags 9 exit Enter test file name? trying to open test file: tests\ could not open test file. valid test files are: reverting back to test file: tests\m7102_1.tst Main menu Sun Nov 22 18:59:48 2015 test file is: tests\m7102_1.tst delay is: 0 trigger is: 1 1 read test file 2 set test delay 3 set test trigger 4 run test 5 output loading test 8 diags 9 exit UUT power is okay Sun Nov 22 18:59:50 2015 space single step O run once (one test, all steps) F run, stop on fail G go (run tests N run, stop on fail, no print S scope (run, no print) C toggle comment printout + increase speed (less delay) - decrease speed (more delay)(slower) Q quit test step 1 0101010000001001001010010010010000000000101010000111111111 step 2 1001010000001001001010010010010000000000101010000111111111 step 3 0101010000001001001010010010010000000000101010000111111111 step 4 0110010000001001001010010010010000000000101010000111111111 step 5 0101010000001001001010010010010000000000101010000111111111 step 6 0101100000001001001010010010010000000000101010000111111111 step 7 0101010000001001001010010010010000000000101010000111111111 step 8 0101011100001001001010010010010000000000101010000111111111 step 9 0101010000001001001010010010010000000000101010000111111111 step 10 0101010011001001001010010010010000000000101010000111111111 step 11 0101010000001001001010010010010000000000101010000111111111 step 12 0101010000110001001010010010010000000000101010000111111111 step 13 0101010000001001001010010010010000000000101010000111111111 step 14 0101010000001110001010010010010000000000101010000111111111 step 15 0101010000001001001010010010010000000000101010000111111111 step 16 0101010000001001110010010010010000000000101010000111111111 step 17 0101010000001001001010010010010000000000101010000111111111 step 18 0101010000001001001100010010010000000000101010000111111111 step 19 0101010000001001001010010010010000000000101010000111111111 step 20 0101010000001001001010100010010000000000101010000111111111 step 21 0101010000001001001011100010010000000000101010000111111111 step 22 0101010000001001001011000010010000000000101010000111111111 step 23 0101010000001001001010010010010000000000101010000111111111 step 24 0101010000001001001010010100010000000000101010000111111111 step 25 0101010000001001001010011100010000000000101010000111111111 step 26 0101010000001001001010011000010000000000101010000111111111 step 27 0101010000001001001010010010010000000000101010000111111111 step 28 0101010000001001001010010010110000000000101010000111111111 step 29 0101010000001001001010010011100000000000101010000111111111 step 30 0101010000001001001010010011010000000000101010000111111111 step 31 0101010000001001001010010010010000000000101010000111111111 step 32 0101010000001001001010010010011100000000101010000111111111 step 33 0101010000001001001010010010010000000000101010000111111111 SLOT ABABABAAAAAABAABBBBAABBBBBBBBBBABABABABABBABBBAAABBBAAAAAA LETTER NFPHRJKNLMPTBRSADVCVULKMJHFRSPNDPERDSEUBUVADEEKLMKLMFHJFHJ SIDE 1212122222221221121111111111112121222211211212111222111222 DIRECTION IPIPIPIOIOIOOIOOIPOIOIIOIIOIIOIPIPIPIPIPOIPIOIIIIOOOPPPPPP changed: 1 step 34 0101010000001001001010010010010010000000101010000111111111 fail ^ step 35 0101010000001001001010010010010000000000101010000111111111 SLOT ABABABAAAAAABAABBBBAABBBBBBBBBBABABABABABBABBBAAABBBAAAAAA LETTER NFPHRJKNLMPTBRSADVCVULKMJHFRSPNDPERDSEUBUVADEEKLMKLMFHJFHJ SIDE 1212122222221221121111111111112121222211211212111222111222 DIRECTION IPIPIPIOIOIOOIOOIPOIOIIOIIOIIOIPIPIPIPIPOIPIOIIIIOOOPPPPPP changed: 1 step 36 0101010000001001001010010010010000100000101010000111111111 fail ^ step 37 0101010000001001001010010010010000000000101010000111111111 SLOT ABABABAAAAAABAABBBBAABBBBBBBBBBABABABABABBABBBAAABBBAAAAAA LETTER NFPHRJKNLMPTBRSADVCVULKMJHFRSPNDPERDSEUBUVADEEKLMKLMFHJFHJ SIDE 1212122222221221121111111111112121222211211212111222111222 DIRECTION IPIPIPIOIOIOOIOOIPOIOIIOIIOIIOIPIPIPIPIPOIPIOIIIIOOOPPPPPP changed: 1 step 38 0101010000001001001010010010010000001000101010000111111111 fail ^ step 39 0101010000001001001010010010010000000000101010000111111111 step 40 0101010000001001001010010010010000000011001010000111111111 step 41 0101010000001001001010010010010000000000101010000111111111 step 42 0101010000001001001010010010010000000000110010000111111111 step 43 0101010000001001001010010010010000000000101010000111111111 step 44 0101010000001001001010010010010000000000101010000111111111 step 45 0101010000001001001010010010010000000000101011000111111111 step 46 0101010000001001001010010010010000000000101011000111111111 step 47 0101010000001001001010010010010000000000101011001111111111 step 48 0101010000001001001010010010010000000000101011011111111111 step 49 0101010000001001001010010010010000000000101011010111111111 step 50 0101010000001001001010010010010000000000101011110111111111 step 51 0101010000001001001010010010010000000000101011111111111111 step 52 0101010000001001001010010010010000000000101011101111111111 step 53 0101010000001001001010010010010000000000101011100111111111 step 54 0101010000001001001010010010010000000000101011000111111111 step 55 0101010000001001001010010010010000000000101101000111111111 step 56 0101010000001001001010010010010000000000101101000111111111 step 57 0101010000001001001010010010010000000000101101001111111111 step 58 0101010000001001001010010010010000000000101101011111111111 step 59 0101010000001001001010010010010000000000101101010111111111 step 60 0101010000001001001010010010010000000000101101110111111111 step 61 0101010000001001001010010010010000000000101101111111111111 step 62 0101010000001001001010010010010000000000101101101111111111 step 63 0101010000001001001010010010010000000000101101100111111111 step 64 0101010000001001001010010010010000000000101101000111111111 step 65 0101010000001001001010010010010000000000101100000111111111 step 66 0101010000001001001010010010010000000000101100000111111111 step 67 0101010000001001001010010010010000000000101100001110111111 step 68 0101010000001001001010010010010000000000101100011100111111 step 69 0101010000001001001010010010010000000000101100010101111111 step 70 0101010000001001001010010010010000000000101100110001111111 step 71 0101010000001001001010010010010000000000101100111000111111 step 72 0101010000001001001010010010010000000000101100101010111111 step 73 0101010000001001001010010010010000000000101100100011111111 step 74 0101010000001001001010010010010000000000101100000111111111 step 75 0101010000001001001010010010010000000000101010000111111111 step 76 0101010000001001001010010010010000000000101010000111111111 step 77 0101010000001001001010010010010000000000101010001111111111 step 78 0101010000001001001010010010010000000000101010011111111111 step 79 0101010000001001001010010010010000000000101010010111111111 step 80 0101010000001001001010010010010000000000101010110111111111 step 81 0101010000001001001010010010010000000000101010111111111111 step 82 0101010000001001001010010010010000000000101010101111111111 step 83 0101010000001001001010010010010000000000101010100111111111 step 84 0101010000001001001010010010010000000000101010000111111111 step 85 0101010000001001001010010010010000000000101010000111111111 step 86 0101010000001001001010010010010000000000101010000111111111 test 1: *** FAIL *************************** 3 steps failed SLOT ABABABAAAAAABAABBBBAABBBBBBBBBBABABABABABBABBBAAABBBAAAAAA LETTER NFPHRJKNLMPTBRSADVCVULKMJHFRSPNDPERDSEUBUVADEEKLMKLMFHJFHJ SIDE 1212122222221221121111111111112121222211211212111222111222 DIRECTION IPIPIPIOIOIOOIOOIPOIOIIOIIOIIOIPIPIPIPIPOIPIOIIIIOOOPPPPPP this fail P P P all fails P P P was hi 111111111111111111111111111111111 1 1 11111111111111111111 rising ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ ^ ^ ^^^^^^^^^^^^^^ falling vvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvv v v vvvvvvvvvvvvvv was lo 0000000000000000000000000000000000000000000000000000 total fails 1, total passes 0 space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C toggle comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit failure mode analysis: pin: 34 P AE1 E2-3 OUTPUT 14 (75452 OPEN COLLECTOR OUTPUT) SLOT ABABABAAAAAABAABBBBAABBBBBBBBBBABABABABABBABBBAAABBBAAAAAA LETTER NFPHRJKNLMPTBRSADVCVULKMJHFRSPNDPERDSEUBUVADEEKLMKLMFHJFHJ SIDE 1212122222221221121111111111112121222211211212111222111222 DIRECTION IPIPIPIOIOIOOIOOIPOIOIIOIIOIIOIPIPIPIPIPOIPIOIIIIOOOPPPPPP fails LO: 1 1 1 1 1 1 1 1 1 1 1 1 1 1 111111111 fails LO: 0 0 0 000000 00 00 0 00 00 00 00 000000 0 0 0000 fails HI: fails HI: pin: 36 P AD2 E5-5 OUTPUT 15 (75452 OPEN COLLECTOR OUTPUT) SLOT ABABABAAAAAABAABBBBAABBBBBBBBBBABABABABABBABBBAAABBBAAAAAA LETTER NFPHRJKNLMPTBRSADVCVULKMJHFRSPNDPERDSEUBUVADEEKLMKLMFHJFHJ SIDE 1212122222221221121111111111112121222211211212111222111222 DIRECTION IPIPIPIOIOIOOIOOIPOIOIIOIIOIIOIPIPIPIPIPOIPIOIIIIOOOPPPPPP fails LO: 1 1 1 1 1 1 1 1 1 1 1 1 1 1 111111111 fails LO: 0 0 0 000000 00 00 0 00 00 00 0000 0000 0 0 0000 fails HI: fails HI: pin: 38 P AE2 E4-5 OUTPUT 16 (75452 OPEN COLLECTOR OUTPUT) SLOT ABABABAAAAAABAABBBBAABBBBBBBBBBABABABABABBABBBAAABBBAAAAAA LETTER NFPHRJKNLMPTBRSADVCVULKMJHFRSPNDPERDSEUBUVADEEKLMKLMFHJFHJ SIDE 1212122222221221121111111111112121222211211212111222111222 DIRECTION IPIPIPIOIOIOOIOOIPOIOIIOIIOIIOIPIPIPIPIPOIPIOIIIIOOOPPPPPP fails LO: 1 1 1 1 1 1 1 1 1 1 1 1 1 1 111111111 fails LO: 0 0 0 000000 00 00 0 00 00 00 000000 00 0 0 0000 fails HI: fails HI: space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C toggle comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit up to this point: PINS that are always low 34 P AE1 E2-3 OUTPUT 14 (75452 OPEN COLLECTOR OUTPUT) 36 P AD2 E5-5 OUTPUT 15 (75452 OPEN COLLECTOR OUTPUT) 38 P AE2 E4-5 OUTPUT 16 (75452 OPEN COLLECTOR OUTPUT) PINS that are always high 53 P AF1 E4-3 OUTPUT I/O BUS ACIN0-N (75452 OPEN COLLECTOR OUTPUT) 54 P AH1 E5-3 OUTPUT I/O BUS ACIN1-N (75452 OPEN COLLECTOR OUTPUT) 55 P AJ1 E8-5 OUTPUT I/O BUS ACIN2-N (75452 OPEN COLLECTOR OUTPUT) 56 P AF2 E7-5 OUTPUT I/O BUS DATA0-N (75452 OPEN COLLECTOR OUTPUT) 57 P AH2 E3-3 OUTPUT I/O BUS DATA1-N (75452 OPEN COLLECTOR OUTPUT) 58 P AJ2 E7-3 OUTPUT I/O BUS DATA2-N (75452 OPEN COLLECTOR OUTPUT) space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C toggle comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT ABABABAAAAAABAABBBBAABBBBBBBBBBABABABABABBABBBAAABBBAAAAAA LETTER NFPHRJKNLMPTBRSADVCVULKMJHFRSPNDPERDSEUBUVADEEKLMKLMFHJFHJ SIDE 1212122222221221121111111111112121222211211212111222111222 DIRECTION IPIPIPIOIOIOOIOOIPOIOIIOIIOIIOIPIPIPIPIPOIPIOIIIIOOOPPPPPP all fails P P P was lo 0000000000000000000000000000000000000000000000000000 falling vvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvv v v vvvvvvvvvvvvvv rising ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ ^ ^ ^^^^^^^^^^^^^^ was hi 111111111111111111111111111111111 1 1 11111111111111111111 total fails 1, total passes 0 Main menu Sun Nov 22 19:00:02 2015 test file is: tests\m7102_1.tst delay is: 0 trigger is: 1 1 read test file 2 set test delay 3 set test trigger 4 run test 5 output loading test 8 diags 9 exit Enter test file name? trying to open test file: tests\m7102_2.tst reading test file: tests\m7102_2.tst comment: M7102 PCB REV D SCHEMATIC REV C Positive I/O Bus Converter (DW08E) comment: comment: PART 2 Tests Omnibus DATA BUS driving Posibus ACIN and DATA. comment: (See PART 1 for Posibus driving Omnibus. comment: comment: (Two parts are necessary due to the Omnibus DATA00:02-N is a bidirectional bus). comment: comment: Tolerates 3.3k ohm pullups to +5v on pin (are needed for PART 1): comment: BK2 Omnibus DATA00 (bidirectional, input + open collector output) comment: BL2 Omnibus DATA01 (bidirectional, input + open collector output) comment: BM2 Omnibus DATA02 (bidirectional, input + open collector output) comment: pins: PINS pins: 1 I AN1 E6-9 INPUT 1 pins: 2 P BF2 E13-8 OUTPUT A-N (7416 OPEN COLLECTOR OUTPUT) pins: 3 I AP1 E6-6 INPUT 2 pins: 4 P BH2 E13-7 OUTPUT 2-N (7416 OPEN COLLECTOR OUTPUT) pins: 5 I AR1 E6-5 INPUT 3 pins: 6 P BJ2 E13-6 OUTPUT 3-N (7416 OPEN COLLECTOR OUTPUT) pins: 7 I AK2 E9-11 INPUT 4 pins: 8 O AN2 E9-13 OUTPUT 4 (384 OUTPUT) pins: 9 I AL2 E9-9 INPUT 5 pins: 10 O AM2 E9-14 OUTPUT 5 (384 OUTPUT) pins: 11 I AP2 E9-6 INPUT 6 pins: 12 O AT2 E9-2 OUTPUT 6 (384 OUTPUT) pins: 13 O BB1 E11-6 OUTPUT 6-N (74H04 OUTPUT) pins: 14 I AR2 E9-5 INPUT 7 pins: 15 O AS2 E9-3 OUTPUT 7 (384 OUTPUT) pins: 16 O BA1 E11-10 OUTPUT 7-N (74H04 OUTPUT) pins: 17 I BD1 E11-1 INPUT 8 pins: 18 P BV2 E13-12 OUTPUT 8 (7416 OPEN COLLECTOR OUTPUT) pins: 19 O BC1 E11-2 OUTPUT 8-N (74H04 OUTPUT) pins: 20 I AV1 E11-13 INPUT 9 pins: 21 O AU1 E11-12 OUTPUT 9-N (74H04 OUTPUT) pins: 22 I BL1 E12-4 INPUT 10A pins: 23 I BK1 E12-5 INPUT 10B pins: 24 O BM1 E12-3 OUTPUT 10 = INPUT 10A NOR INPUT 10B (380 OUTPUT) pins: 25 I BJ1 E12-9 INPUT 11A pins: 26 I BH1 E12-10 INPUT 11B pins: 27 O BF1 E12-14 OUTPUT 11 = INPUT 11A NOR INPUT 11B (M380 OUTPUT) pins: 28 I BR1 E15-12 INPUT 12A pins: 29 I BS1 E15-11 INPUT 12B pins: 30 O BP1 E15-? OUTPUT 12 = INPUT 12A NAND INPUT 12B (8881 OPEN COLLECTOR OUTPUT WITH 3.3K PULLUP) pins: 31 I BN2 E10-6,7 INPUT 13 pins: 32 P AD1 E1-3 OUTPUT 13 (75452 OPEN COLLECTOR OUTPUT) pins: 33 I BP2 E14-11,12 INPUT 14 pins: 34 P AE1 E2-3 OUTPUT 14 (75452 OPEN COLLECTOR OUTPUT) pins: 35 I BR2 E14-9,10 INPUT 15 pins: 36 P AD2 E5-5 OUTPUT 15 (75452 OPEN COLLECTOR OUTPUT) pins: 37 I BS2 E14-6,7 INPUT 16 pins: 38 P AE2 E4-5 OUTPUT 16 (75452 OPEN COLLECTOR OUTPUT) pins: 39 I BU1 E14-4,5 INPUT 17 pins: 40 P AB1 E4-5 OUTPUT 17 (75452 OPEN COLLECTOR OUTPUT) pins: 41 O BU2 E14-3 OUTPUT 17-N (380 OUTPUT) pins: 42 I BV1 E2-6,7 INPUT 18 pins: 43 P AA1 E2-5 OUTPUT 18-N (75452 OPEN COLLECTOR OUTPUT) pins: 44 I BD2 E11-3 OMNIBUS DATA TO I/O DATA-N (LOW ALSO DISABLES BAC <> OMNIBUS) pins: 45 O BE1 E11-4 OMNIBUS DATA TO I/O DATA (74H04 OUTPUT) pins: 46 I BE2 E12-12 INPUT OUT-N (L -> BAC TO OMNIBUS, H -> OMNIBUS TO BAC) pins: 47 I AK1 E3-6 INPUT BAC0 (DATA FROM I/O BUS) pins: 48 I AL1 E3-5 INPUT BAC1 (DATA FROM I/O BUS) pins: 49 I AM1 E6-11 INPUT BAC2 (DATA FROM I/O BUS) pins: 50 I BK2 E15-1 INPUT DATA00-N (OMNIBUS DATA00) (8881 OPEN COLLECTOR OUTPUT) pins: 51 I BL2 E15-4 INPUT DATA01-N (OMNIBUS DATA01) (8881 OPEN COLLECTOR OUTPUT) pins: 52 I BM2 E15-10 INPUT DATA02-N (OMNIBUS DATA02) (8881 OPEN COLLECTOR OUTPUT) pins: 53 P AF1 E4-3 OUTPUT I/O BUS ACIN0-N (75452 OPEN COLLECTOR OUTPUT) pins: 54 P AH1 E5-3 OUTPUT I/O BUS ACIN1-N (75452 OPEN COLLECTOR OUTPUT) pins: 55 P AJ1 E8-5 OUTPUT I/O BUS ACIN2-N (75452 OPEN COLLECTOR OUTPUT) pins: 56 P AF2 E7-5 OUTPUT I/O BUS DATA0-N (75452 OPEN COLLECTOR OUTPUT) pins: 57 P AH2 E3-3 OUTPUT I/O BUS DATA1-N (75452 OPEN COLLECTOR OUTPUT) pins: 58 P AJ2 E7-3 OUTPUT I/O BUS DATA2-N (75452 OPEN COLLECTOR OUTPUT) pins: direction: IPIPIPIOIOIOOIOOIPOIOIIOIIOIIOIPIPIPIPIPOIPIOIIIIIIIPPPPPP test 1: 0101010000001001001010010010010000000000101010000111111111 comment: comment: ; INPUT 1 -> OUTPUT 1-N test 2: 10 test 3: 01 comment: comment: ; INPUT 2 -> OUTPUT 2-N test 4: 10 test 5: 01 comment: comment: ; INPUT 3 -> OUTPUT 3-N test 6: 10 test 7: 01 comment: comment: ; INPUT 4 -> OUTPUT 4 test 8: 11 test 9: 00 comment: comment: ; INPUT 5 -> OUTPUT 5 test 10: 11 test 11: 00 comment: comment: ; INPUT 6 -> OUTPUT 6, OUTPUT 6-N test 12: 110 test 13: 001 comment: comment: ; INPUT 7 -> OUTPUT 7, OUTPUT 7-N test 14: 110 test 15: 001 comment: comment: ; INPUT 8 -> OUTPUT 8, OUTPUT 8-N test 16: 110 test 17: 001 comment: comment: ; INPUT 9 -> OOUTPUT 9-N test 18: 10 test 19: 01 comment: comment: ; INPUT 10A NOR INPUT 10B -> OUTPUT 10 test 20: 010 test 21: 110 test 22: 100 test 23: 001 comment: comment: ; INPUT 11A NOR INPUT 11B -> OUTPUT 11 test 24: 010 test 25: 110 test 26: 100 test 27: 001 comment: comment: ; INPUT 12A NAND INPUT 12B -> OUTPUT 12 test 28: 011 test 29: 110 test 30: 101 test 31: 001 comment: comment: ; INPUT 13 -> OUTPUT 13 test 32: 11 test 33: 00 comment: comment: ; INPUT 14 -> OUTPUT 14 test 34: 11 test 35: 00 comment: comment: ; INPUT 15 -> OUTPUT 15 test 36: 11 test 37: 00 comment: comment: ; INPUT 16 -> OUTPUT 16 test 38: 11 test 39: 00 comment: comment: ; INPUT 17 -> OUTPUT 17, OUTPUT 17-N test 40: 110 test 41: 001 comment: comment: ; INPUT 18 -> OUTPUT 18-N test 42: 10 test 43: 01 comment: comment: ; (no change) test 44: 0101010000001001001010010010010000000000101010000111111111 comment: comment: comment: comment: ; PART 2 unique tests (Omnibus DATA00:02-N driving Posibus ACIN and DATA) comment: comment: ; (See PART 1 for Posibus driving Omnibus). comment: comment: comment: comment: ; Select Omnibus DATA00:02-N -> Posibus DATA0:2-N comment: comment: ; OMNIBUS DATA TO I/O DATA-N LO, OUT-N HI; OMNIBUS DATA TO I/O DATA -> HI test 45: 011 comment: ; (no change) test 46: 000111111111 comment: comment: ; All DATA00:02-N patterns (Posibus ACIN0:2-N always HI). test 47: 101 101 test 48: 100 100 test 49: 000 000 test 50: 001 001 test 51: 011 011 test 52: 010 010 test 53: 110 110 test 54: 111 111 comment: comment: comment: comment: ; Select Omnibus DATA00:02-N -> PosiBus ACIN0:2-N comment: comment: ; OMNIBUS DATA TO I/O DATA-N HI, OUT-N HI; OMNIBUS DATA TO I/O DATA -> LO test 55: 101 comment: ; (no change) test 56: 000111111111 comment: comment: ; All DATA00:02-N patterns (Posibus DATA0:2-N always HI). test 57: 101101 test 58: 100100 test 59: 000000 test 60: 001001 test 61: 011011 test 62: 010010 test 63: 110110 test 64: 111111 comment: comment: comment: ; Do not select Posibus BAC0:2 -> Omnibus DATA00:02-N comment: ; (we drive Omnibus DATA00:02-N in PART 2). comment: ; skip >>>>> 100 comment: comment: comment: comment: ; Select Omnibus DATA00:02-N -> Posibus DATA0:2-N comment: comment: ; Do 2 steps to avoid >>>>> 100 comment: ; OMNIBUS DATA TO I/O DATA-N LO, OUT-N HI; OMNIBUS DATA TO I/O DATA -> HI test 65: 011 comment: comment: ; OMNIBUS DATA TO I/O DATA-N LO, OUT-N LO; OMNIBUS DATA TO I/O DATA -> HI test 66: 010 comment: ; (no change) test 67: 000111111111 comment: comment: ; All DATA00:02-N patterns (Posibus ACIN0:2-N always HI). test 68: 101 101 test 69: 100 100 test 70: 000 000 test 71: 001 001 test 72: 011 011 test 73: 010 010 test 74: 110 110 test 75: 111 111 comment: comment: ; (no change) test 76: 0101010000001001001010010010010000000000101010000111111111 end: END summary column 1: offset 1, mask 0x1000 column 2: offset 2, mask 0x0080 column 3: offset 1, mask 0x0800 column 4: offset 3, mask 0x0001 column 5: offset 1, mask 0x0400 column 6: offset 3, mask 0x0002 column 7: offset 1, mask 0x0001 column 8: offset 1, mask 0x0008 column 9: offset 1, mask 0x0002 column 10: offset 1, mask 0x0004 column 11: offset 1, mask 0x0010 column 12: offset 1, mask 0x0080 column 13: offset 2, mask 0x1000 column 14: offset 1, mask 0x0020 column 15: offset 1, mask 0x0040 column 16: offset 2, mask 0x2000 column 17: offset 2, mask 0x0400 column 18: offset 4, mask 0x0008 column 19: offset 2, mask 0x0800 column 20: offset 2, mask 0x4000 column 21: offset 2, mask 0x8000 column 22: offset 3, mask 0x1000 column 23: offset 3, mask 0x2000 column 24: offset 3, mask 0x0800 column 25: offset 3, mask 0x4000 column 26: offset 3, mask 0x8000 column 27: offset 2, mask 0x0100 column 28: offset 3, mask 0x0100 column 29: offset 4, mask 0x8000 column 30: offset 3, mask 0x0200 column 31: offset 3, mask 0x0020 column 32: offset 0, mask 0x1000 column 33: offset 3, mask 0x0040 column 34: offset 0, mask 0x0800 column 35: offset 3, mask 0x0080 column 36: offset 0, mask 0x0010 column 37: offset 4, mask 0x0001 column 38: offset 0, mask 0x0008 column 39: offset 4, mask 0x2000 column 40: offset 0, mask 0x4000 column 41: offset 4, mask 0x0004 column 42: offset 4, mask 0x1000 column 43: offset 0, mask 0x8000 column 44: offset 2, mask 0x0020 column 45: offset 2, mask 0x0200 column 46: offset 2, mask 0x0040 column 47: offset 1, mask 0x8000 column 48: offset 1, mask 0x4000 column 49: offset 1, mask 0x2000 column 50: offset 3, mask 0x0004 column 51: offset 3, mask 0x0008 column 52: offset 3, mask 0x0010 column 53: offset 0, mask 0x0400 column 54: offset 0, mask 0x0200 column 55: offset 0, mask 0x0100 column 56: offset 0, mask 0x0004 column 57: offset 0, mask 0x0002 column 58: offset 0, mask 0x0001 direction bits (1=input) 0xFFFF 0x03CC 0xBB9B 0x0E03 0x40FE pullup bits (1=pullup) 0xDF1F 0x0000 0x0080 0x0003 0x0008 test step out_data dont care 1: 0x8707 0x0000 0xBB80 0x0A1F 0x0004 2: 0x8707 0x1000 0xBB00 0x0A1F 0x0004 3: 0x8707 0x0000 0xBB80 0x0A1F 0x0004 4: 0x8707 0x0800 0xBB80 0x0A1E 0x0004 5: 0x8707 0x0000 0xBB80 0x0A1F 0x0004 6: 0x8707 0x0400 0xBB80 0x0A1D 0x0004 7: 0x8707 0x0000 0xBB80 0x0A1F 0x0004 8: 0x8707 0x0009 0xBB80 0x0A1F 0x0004 9: 0x8707 0x0000 0xBB80 0x0A1F 0x0004 10: 0x8707 0x0006 0xBB80 0x0A1F 0x0004 11: 0x8707 0x0000 0xBB80 0x0A1F 0x0004 12: 0x8707 0x0090 0xAB80 0x0A1F 0x0004 13: 0x8707 0x0000 0xBB80 0x0A1F 0x0004 14: 0x8707 0x0060 0x9B80 0x0A1F 0x0004 15: 0x8707 0x0000 0xBB80 0x0A1F 0x0004 16: 0x8707 0x0000 0xB780 0x0A1F 0x000C 17: 0x8707 0x0000 0xBB80 0x0A1F 0x0004 18: 0x8707 0x0000 0x7B80 0x0A1F 0x0004 19: 0x8707 0x0000 0xBB80 0x0A1F 0x0004 20: 0x8707 0x0000 0xBB80 0x221F 0x0004 21: 0x8707 0x0000 0xBB80 0x321F 0x0004 22: 0x8707 0x0000 0xBB80 0x121F 0x0004 23: 0x8707 0x0000 0xBB80 0x0A1F 0x0004 24: 0x8707 0x0000 0xBA80 0x8A1F 0x0004 25: 0x8707 0x0000 0xBA80 0xCA1F 0x0004 26: 0x8707 0x0000 0xBA80 0x4A1F 0x0004 27: 0x8707 0x0000 0xBB80 0x0A1F 0x0004 28: 0x8707 0x0000 0xBB80 0x0A1F 0x8004 29: 0x8707 0x0000 0xBB80 0x091F 0x8004 30: 0x8707 0x0000 0xBB80 0x0B1F 0x0004 31: 0x8707 0x0000 0xBB80 0x0A1F 0x0004 32: 0x9707 0x0000 0xBB80 0x0A3F 0x0004 33: 0x8707 0x0000 0xBB80 0x0A1F 0x0004 34: 0x8F07 0x0000 0xBB80 0x0A5F 0x0004 35: 0x8707 0x0000 0xBB80 0x0A1F 0x0004 36: 0x8717 0x0000 0xBB80 0x0A9F 0x0004 37: 0x8707 0x0000 0xBB80 0x0A1F 0x0004 38: 0x870F 0x0000 0xBB80 0x0A1F 0x0005 39: 0x8707 0x0000 0xBB80 0x0A1F 0x0004 40: 0xC707 0x0000 0xBB80 0x0A1F 0x2000 41: 0x8707 0x0000 0xBB80 0x0A1F 0x0004 42: 0x0707 0x0000 0xBB80 0x0A1F 0x1004 43: 0x8707 0x0000 0xBB80 0x0A1F 0x0004 44: 0x8707 0x0000 0xBB80 0x0A1F 0x0004 45: 0x8707 0x0000 0xBBC0 0x0A1F 0x0004 46: 0x8707 0x0000 0xBBC0 0x0A1F 0x0004 47: 0x8705 0x0000 0xBBC0 0x0A17 0x0004 48: 0x8704 0x0000 0xBBC0 0x0A07 0x0004 49: 0x8700 0x0000 0xBBC0 0x0A03 0x0004 50: 0x8701 0x0000 0xBBC0 0x0A13 0x0004 51: 0x8703 0x0000 0xBBC0 0x0A1B 0x0004 52: 0x8702 0x0000 0xBBC0 0x0A0B 0x0004 53: 0x8706 0x0000 0xBBC0 0x0A0F 0x0004 54: 0x8707 0x0000 0xBBC0 0x0A1F 0x0004 55: 0x8707 0x0000 0xB9E0 0x0A1F 0x0004 56: 0x8707 0x0000 0xB9E0 0x0A1F 0x0004 57: 0x8507 0x0000 0xB9E0 0x0A17 0x0004 58: 0x8407 0x0000 0xB9E0 0x0A07 0x0004 59: 0x8007 0x0000 0xB9E0 0x0A03 0x0004 60: 0x8107 0x0000 0xB9E0 0x0A13 0x0004 61: 0x8307 0x0000 0xB9E0 0x0A1B 0x0004 62: 0x8207 0x0000 0xB9E0 0x0A0B 0x0004 63: 0x8607 0x0000 0xB9E0 0x0A0F 0x0004 64: 0x8707 0x0000 0xB9E0 0x0A1F 0x0004 65: 0x8707 0x0000 0xBBC0 0x0A1F 0x0004 66: 0x8707 0x0000 0xBB80 0x0A1F 0x0004 67: 0x8707 0x0000 0xBB80 0x0A1F 0x0004 68: 0x8705 0x0000 0xBB80 0x0A17 0x0004 69: 0x8704 0x0000 0xBB80 0x0A07 0x0004 70: 0x8700 0x0000 0xBB80 0x0A03 0x0004 71: 0x8701 0x0000 0xBB80 0x0A13 0x0004 72: 0x8703 0x0000 0xBB80 0x0A1B 0x0004 73: 0x8702 0x0000 0xBB80 0x0A0B 0x0004 74: 0x8706 0x0000 0xBB80 0x0A0F 0x0004 75: 0x8707 0x0000 0xBB80 0x0A1F 0x0004 76: 0x8707 0x0000 0xBB80 0x0A1F 0x0004 PINs used (in edge connector order) (G=ground,P=power) SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBB LETTER ABCDEFHJKLMNPRSTUVABCDEFHJKLMNPRSTUVABCDEFHJKLMNPRSTUVABCDEFHJKLMNPRSTUV SIDE 111111111111111111222222222222222222111111111111111111222222222222222222 USAGE PP PPPPPIIIIII GOIP GPPPPPIIOOIIOO OOOIOOIIIIO OIIGIIP GIIPPPIIIIIII OP UUT inputs: 29 UUT outputs: 29 pins used: 58 not used: 8 76 'test steps' 231 lines M7102 PCB REV D SCHEMATIC REV C Positive I/O Bus Converter (DW08E) PART 2 Tests Omnibus DATA BUS driving Posibus ACIN and DATA. (See PART 1 for Posibus driving Omnibus. (Two parts are necessary due to the Omnibus DATA00:02-N is a bidirectional bus). Tolerates 3.3k ohm pullups to +5v on pin (are needed for PART 1): BK2 Omnibus DATA00 (bidirectional, input + open collector output) BL2 Omnibus DATA01 (bidirectional, input + open collector output) BM2 Omnibus DATA02 (bidirectional, input + open collector output) PINS Main menu Sun Nov 22 19:00:09 2015 test file is: tests\m7102_2.tst delay is: 0 trigger is: 1 1 read test file 2 set test delay 3 set test trigger 4 run test 5 output loading test 8 diags 9 exit UUT power is okay Sun Nov 22 19:00:26 2015 space single step O run once (one test, all steps) F run, stop on fail G go (run tests N run, stop on fail, no print S scope (run, no print) C toggle comment printout + increase speed (less delay) - decrease speed (more delay)(slower) Q quit test step 1 0101010000001001001010010010010000000000101010000111111111 step 2 1001010000001001001010010010010000000000101010000111111111 step 3 0101010000001001001010010010010000000000101010000111111111 step 4 0110010000001001001010010010010000000000101010000111111111 step 5 0101010000001001001010010010010000000000101010000111111111 step 6 0101100000001001001010010010010000000000101010000111111111 step 7 0101010000001001001010010010010000000000101010000111111111 step 8 0101011100001001001010010010010000000000101010000111111111 step 9 0101010000001001001010010010010000000000101010000111111111 step 10 0101010011001001001010010010010000000000101010000111111111 step 11 0101010000001001001010010010010000000000101010000111111111 step 12 0101010000110001001010010010010000000000101010000111111111 step 13 0101010000001001001010010010010000000000101010000111111111 step 14 0101010000001110001010010010010000000000101010000111111111 step 15 0101010000001001001010010010010000000000101010000111111111 step 16 0101010000001001110010010010010000000000101010000111111111 step 17 0101010000001001001010010010010000000000101010000111111111 step 18 0101010000001001001100010010010000000000101010000111111111 step 19 0101010000001001001010010010010000000000101010000111111111 step 20 0101010000001001001010100010010000000000101010000111111111 step 21 0101010000001001001011100010010000000000101010000111111111 step 22 0101010000001001001011000010010000000000101010000111111111 step 23 0101010000001001001010010010010000000000101010000111111111 step 24 0101010000001001001010010100010000000000101010000111111111 step 25 0101010000001001001010011100010000000000101010000111111111 step 26 0101010000001001001010011000010000000000101010000111111111 step 27 0101010000001001001010010010010000000000101010000111111111 step 28 0101010000001001001010010010110000000000101010000111111111 step 29 0101010000001001001010010011100000000000101010000111111111 step 30 0101010000001001001010010011010000000000101010000111111111 step 31 0101010000001001001010010010010000000000101010000111111111 step 32 0101010000001001001010010010011100000000101010000111111111 step 33 0101010000001001001010010010010000000000101010000111111111 SLOT ABABABAAAAAABAABBBBAABBBBBBBBBBABABABABABBABBBAAABBBAAAAAA LETTER NFPHRJKNLMPTBRSADVCVULKMJHFRSPNDPERDSEUBUVADEEKLMKLMFHJFHJ SIDE 1212122222221221121111111111112121222211211212111222111222 DIRECTION IPIPIPIOIOIOOIOOIPOIOIIOIIOIIOIPIPIPIPIPOIPIOIIIIIIIPPPPPP changed: 1 step 34 0101010000001001001010010010010010000000101010000111111111 fail ^ step 35 0101010000001001001010010010010000000000101010000111111111 SLOT ABABABAAAAAABAABBBBAABBBBBBBBBBABABABABABBABBBAAABBBAAAAAA LETTER NFPHRJKNLMPTBRSADVCVULKMJHFRSPNDPERDSEUBUVADEEKLMKLMFHJFHJ SIDE 1212122222221221121111111111112121222211211212111222111222 DIRECTION IPIPIPIOIOIOOIOOIPOIOIIOIIOIIOIPIPIPIPIPOIPIOIIIIIIIPPPPPP changed: 1 step 36 0101010000001001001010010010010000100000101010000111111111 fail ^ step 37 0101010000001001001010010010010000000000101010000111111111 SLOT ABABABAAAAAABAABBBBAABBBBBBBBBBABABABABABBABBBAAABBBAAAAAA LETTER NFPHRJKNLMPTBRSADVCVULKMJHFRSPNDPERDSEUBUVADEEKLMKLMFHJFHJ SIDE 1212122222221221121111111111112121222211211212111222111222 DIRECTION IPIPIPIOIOIOOIOOIPOIOIIOIIOIIOIPIPIPIPIPOIPIOIIIIIIIPPPPPP changed: 1 step 38 0101010000001001001010010010010000001000101010000111111111 fail ^ step 39 0101010000001001001010010010010000000000101010000111111111 step 40 0101010000001001001010010010010000000011001010000111111111 SLOT ABABABAAAAAABAABBBBAABBBBBBBBBBABABABABABBABBBAAABBBAAAAAA LETTER NFPHRJKNLMPTBRSADVCVULKMJHFRSPNDPERDSEUBUVADEEKLMKLMFHJFHJ SIDE 1212122222221221121111111111112121222211211212111222111222 DIRECTION IPIPIPIOIOIOOIOOIPOIOIIOIIOIIOIPIPIPIPIPOIPIOIIIIIIIPPPPPP changed: 00 step 41 0101010000001001001010010010010000000000001010000111111111 fail ^ step 42 0101010000001001001010010010010000000000110010000111111111 step 43 0101010000001001001010010010010000000000101010000111111111 step 44 0101010000001001001010010010010000000000101010000111111111 step 45 0101010000001001001010010010010000000000101011000111111111 step 46 0101010000001001001010010010010000000000101011000111111111 step 47 0101010000001001001010010010010000000000101011000101111101 step 48 0101010000001001001010010010010000000000101011000100111100 step 49 0101010000001001001010010010010000000000101011000000111000 step 50 0101010000001001001010010010010000000000101011000001111001 step 51 0101010000001001001010010010010000000000101011000011111011 step 52 0101010000001001001010010010010000000000101011000010111010 step 53 0101010000001001001010010010010000000000101011000110111110 step 54 0101010000001001001010010010010000000000101011000111111111 step 55 0101010000001001001010010010010000000000101101000111111111 step 56 0101010000001001001010010010010000000000101101000111111111 step 57 0101010000001001001010010010010000000000101101000101101111 step 58 0101010000001001001010010010010000000000101101000100100111 step 59 0101010000001001001010010010010000000000101101000000000111 step 60 0101010000001001001010010010010000000000101101000001001111 step 61 0101010000001001001010010010010000000000101101000011011111 step 62 0101010000001001001010010010010000000000101101000010010111 step 63 0101010000001001001010010010010000000000101101000110110111 step 64 0101010000001001001010010010010000000000101101000111111111 step 65 0101010000001001001010010010010000000000101011000111111111 step 66 0101010000001001001010010010010000000000101010000111111111 step 67 0101010000001001001010010010010000000000101010000111111111 step 68 0101010000001001001010010010010000000000101010000101111101 step 69 0101010000001001001010010010010000000000101010000100111100 step 70 0101010000001001001010010010010000000000101010000000111000 step 71 0101010000001001001010010010010000000000101010000001111001 step 72 0101010000001001001010010010010000000000101010000011111011 step 73 0101010000001001001010010010010000000000101010000010111010 step 74 0101010000001001001010010010010000000000101010000110111110 step 75 0101010000001001001010010010010000000000101010000111111111 step 76 0101010000001001001010010010010000000000101010000111111111 test 1: *** FAIL *************************** 4 steps failed SLOT ABABABAAAAAABAABBBBAABBBBBBBBBBABABABABABBABBBAAABBBAAAAAA LETTER NFPHRJKNLMPTBRSADVCVULKMJHFRSPNDPERDSEUBUVADEEKLMKLMFHJFHJ SIDE 1212122222221221121111111111112121222211211212111222111222 DIRECTION IPIPIPIOIOIOOIOOIPOIOIIOIIOIIOIPIPIPIPIPOIPIOIIIIIIIPPPPPP this fail P P P O all fails P P P O was hi 111111111111111111111111111111111 1 1 11111111 111111111 rising ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ ^ ^ ^^^^^^^^ ^^^^^^^^^ falling vvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvv v v vvvvvvvv vvvvvvvvv was lo 0000000000000000000000000000000000000000000000000000000000 total fails 1, total passes 0 space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C toggle comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit failure mode analysis: pin: 34 P AE1 E2-3 OUTPUT 14 (75452 OPEN COLLECTOR OUTPUT) SLOT ABABABAAAAAABAABBBBAABBBBBBBBBBABABABABABBABBBAAABBBAAAAAA LETTER NFPHRJKNLMPTBRSADVCVULKMJHFRSPNDPERDSEUBUVADEEKLMKLMFHJFHJ SIDE 1212122222221221121111111111112121222211211212111222111222 DIRECTION IPIPIPIOIOIOOIOOIPOIOIIOIIOIIOIPIPIPIPIPOIPIOIIIIIIIPPPPPP fails LO: 1 1 1 1 1 1 1 1 1 1 1 1 1 1 111111111 fails LO: 0 0 0 000000 00 00 0 00 00 00 00 000000 0 0 0000 fails HI: fails HI: pin: 36 P AD2 E5-5 OUTPUT 15 (75452 OPEN COLLECTOR OUTPUT) SLOT ABABABAAAAAABAABBBBAABBBBBBBBBBABABABABABBABBBAAABBBAAAAAA LETTER NFPHRJKNLMPTBRSADVCVULKMJHFRSPNDPERDSEUBUVADEEKLMKLMFHJFHJ SIDE 1212122222221221121111111111112121222211211212111222111222 DIRECTION IPIPIPIOIOIOOIOOIPOIOIIOIIOIIOIPIPIPIPIPOIPIOIIIIIIIPPPPPP fails LO: 1 1 1 1 1 1 1 1 1 1 1 1 1 1 111111111 fails LO: 0 0 0 000000 00 00 0 00 00 00 0000 0000 0 0 0000 fails HI: fails HI: pin: 38 P AE2 E4-5 OUTPUT 16 (75452 OPEN COLLECTOR OUTPUT) SLOT ABABABAAAAAABAABBBBAABBBBBBBBBBABABABABABBABBBAAABBBAAAAAA LETTER NFPHRJKNLMPTBRSADVCVULKMJHFRSPNDPERDSEUBUVADEEKLMKLMFHJFHJ SIDE 1212122222221221121111111111112121222211211212111222111222 DIRECTION IPIPIPIOIOIOOIOOIPOIOIIOIIOIIOIPIPIPIPIPOIPIOIIIIIIIPPPPPP fails LO: 1 1 1 1 1 1 1 1 1 1 1 1 1 1 111111111 fails LO: 0 0 0 000000 00 00 0 00 00 00 000000 00 0 0 0000 fails HI: fails HI: pin: 41 O BU2 E14-3 OUTPUT 17-N (380 OUTPUT) SLOT ABABABAAAAAABAABBBBAABBBBBBBBBBABABABABABBABBBAAABBBAAAAAA LETTER NFPHRJKNLMPTBRSADVCVULKMJHFRSPNDPERDSEUBUVADEEKLMKLMFHJFHJ SIDE 1212122222221221121111111111112121222211211212111222111222 DIRECTION IPIPIPIOIOIOOIOOIPOIOIIOIIOIIOIPIPIPIPIPOIPIOIIIIIIIPPPPPP fails LO: 1 1 1 1 1 1 1 1 1 1 1 1 111111111 fails LO: 0 0 0 000000 00 00 0 00 00 00 0000000000 0 0 0000 fails HI: fails HI: space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C toggle comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit up to this point: PINS that are always low 34 P AE1 E2-3 OUTPUT 14 (75452 OPEN COLLECTOR OUTPUT) 36 P AD2 E5-5 OUTPUT 15 (75452 OPEN COLLECTOR OUTPUT) 38 P AE2 E4-5 OUTPUT 16 (75452 OPEN COLLECTOR OUTPUT) 47 I AK1 E3-6 INPUT BAC0 (DATA FROM I/O BUS) 48 I AL1 E3-5 INPUT BAC1 (DATA FROM I/O BUS) 49 I AM1 E6-11 INPUT BAC2 (DATA FROM I/O BUS) PINS that are always high space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C toggle comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT ABABABAAAAAABAABBBBAABBBBBBBBBBABABABABABBABBBAAABBBAAAAAA LETTER NFPHRJKNLMPTBRSADVCVULKMJHFRSPNDPERDSEUBUVADEEKLMKLMFHJFHJ SIDE 1212122222221221121111111111112121222211211212111222111222 DIRECTION IPIPIPIOIOIOOIOOIPOIOIIOIIOIIOIPIPIPIPIPOIPIOIIIIIIIPPPPPP all fails P P P O was lo 0000000000000000000000000000000000000000000000000000000000 falling vvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvv v v vvvvvvvv vvvvvvvvv rising ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ ^ ^ ^^^^^^^^ ^^^^^^^^^ was hi 111111111111111111111111111111111 1 1 11111111 111111111 total fails 1, total passes 0 Main menu Sun Nov 22 19:01:02 2015 test file is: tests\m7102_2.tst delay is: 0 trigger is: 1 1 read test file 2 set test delay 3 set test trigger 4 run test 5 output loading test 8 diags 9 exit Enter test file name? trying to open test file: tests\m7102.tst could not open test file. valid test files are: reverting back to test file: tests\m7102_2.tst Main menu Sun Nov 22 19:01:13 2015 test file is: tests\m7102_2.tst delay is: 0 trigger is: 1 1 read test file 2 set test delay 3 set test trigger 4 run test 5 output loading test 8 diags 9 exit UUT power is okay Sun Nov 22 19:01:14 2015 space single step O run once (one test, all steps) F run, stop on fail G go (run tests N run, stop on fail, no print S scope (run, no print) C toggle comment printout + increase speed (less delay) - decrease speed (more delay)(slower) Q quit test SLOT ABABABAAAAAABAABBBBAABBBBBBBBBBABABABABABBABBBAAABBBAAAAAA LETTER NFPHRJKNLMPTBRSADVCVULKMJHFRSPNDPERDSEUBUVADEEKLMKLMFHJFHJ SIDE 1212122222221221121111111111112121222211211212111222111222 DIRECTION IPIPIPIOIOIOOIOOIPOIOIIOIIOIIOIPIPIPIPIPOIPIOIIIIIIIPPPPPP all fails was lo falling rising was hi total fails 0, total passes 0 Main menu Sun Nov 22 19:01:19 2015 test file is: tests\m7102_2.tst delay is: 0 trigger is: 1 1 read test file 2 set test delay 3 set test trigger 4 run test 5 output loading test 8 diags 9 exit Enter test file name? trying to open test file: tests\m7102_1.tst reading test file: tests\m7102_1.tst comment: M7102 PCB REV D SCHEMATIC REV C Positive I/O Bus Converter (DW08E) comment: comment: PART 1 Tests Posibus driving Omnibus DATA BUS. comment: (See PART 2 for Omnibus driving Posibus. comment: comment: (Two parts are necessary due to the Omnibus DATA00:02-N is a bidirectional bus). comment: comment: Needs 3.3k ohm pullups to +5v on pin: comment: BK2 Omnibus DATA00 (bidirectional, input + open collector output) comment: BL2 Omnibus DATA01 (bidirectional, input + open collector output) comment: BM2 Omnibus DATA02 (bidirectional, input + open collector output) comment: pins: PINS pins: 1 I AN1 E6-9 INPUT 1 pins: 2 P BF2 E13-8 OUTPUT A-N (7416 OPEN COLLECTOR OUTPUT) pins: 3 I AP1 E6-6 INPUT 2 pins: 4 P BH2 E13-7 OUTPUT 2-N (7416 OPEN COLLECTOR OUTPUT) pins: 5 I AR1 E6-5 INPUT 3 pins: 6 P BJ2 E13-6 OUTPUT 3-N (7416 OPEN COLLECTOR OUTPUT) pins: 7 I AK2 E9-11 INPUT 4 pins: 8 O AN2 E9-13 OUTPUT 4 (384 OUTPUT) pins: 9 I AL2 E9-9 INPUT 5 pins: 10 O AM2 E9-14 OUTPUT 5 (384 OUTPUT) pins: 11 I AP2 E9-6 INPUT 6 pins: 12 O AT2 E9-2 OUTPUT 6 (384 OUTPUT) pins: 13 O BB1 E11-6 OUTPUT 6-N (74H04 OUTPUT) pins: 14 I AR2 E9-5 INPUT 7 pins: 15 O AS2 E9-3 OUTPUT 7 (384 OUTPUT) pins: 16 O BA1 E11-10 OUTPUT 7-N (74H04 OUTPUT) pins: 17 I BD1 E11-1 INPUT 8 pins: 18 P BV2 E13-12 OUTPUT 8 (7416 OPEN COLLECTOR OUTPUT) pins: 19 O BC1 E11-2 OUTPUT 8-N (74H04 OUTPUT) pins: 20 I AV1 E11-13 INPUT 9 pins: 21 O AU1 E11-12 OUTPUT 9-N (74H04 OUTPUT) pins: 22 I BL1 E12-4 INPUT 10A pins: 23 I BK1 E12-5 INPUT 10B pins: 24 O BM1 E12-3 OUTPUT 10 = INPUT 10A NOR INPUT 10B (380 OUTPUT) pins: 25 I BJ1 E12-9 INPUT 11A pins: 26 I BH1 E12-10 INPUT 11B pins: 27 O BF1 E12-14 OUTPUT 11 = INPUT 11A NOR INPUT 11B (M380 OUTPUT) pins: 28 I BR1 E15-12 INPUT 12A pins: 29 I BS1 E15-11 INPUT 12B pins: 30 O BP1 E15-? OUTPUT 12 = INPUT 12A NAND INPUT 12B (8881 OPEN COLLECTOR OUTPUT WITH 3.3K PULLUP) pins: 31 I BN2 E10-6,7 INPUT 13 pins: 32 P AD1 E1-3 OUTPUT 13 (75452 OPEN COLLECTOR OUTPUT) pins: 33 I BP2 E14-11,12 INPUT 14 pins: 34 P AE1 E2-3 OUTPUT 14 (75452 OPEN COLLECTOR OUTPUT) pins: 35 I BR2 E14-9,10 INPUT 15 pins: 36 P AD2 E5-5 OUTPUT 15 (75452 OPEN COLLECTOR OUTPUT) pins: 37 I BS2 E14-6,7 INPUT 16 pins: 38 P AE2 E4-5 OUTPUT 16 (75452 OPEN COLLECTOR OUTPUT) pins: 39 I BU1 E14-4,5 INPUT 17 pins: 40 P AB1 E4-5 OUTPUT 17 (75452 OPEN COLLECTOR OUTPUT) pins: 41 O BU2 E14-3 OUTPUT 17-N (380 OUTPUT) pins: 42 I BV1 E2-6,7 INPUT 18 pins: 43 P AA1 E2-5 OUTPUT 18-N (75452 OPEN COLLECTOR OUTPUT) pins: 44 I BD2 E11-3 OMNIBUS DATA TO I/O DATA-N (LOW ALSO DISABLES BAC <> OMNIBUS) pins: 45 O BE1 E11-4 OMNIBUS DATA TO I/O DATA (74H04 OUTPUT) pins: 46 I BE2 E12-12 INPUT OUT-N (L -> BAC TO OMNIBUS, H -> OMNIBUS TO BAC) pins: 47 I AK1 E3-6 INPUT BAC0 (DATA FROM I/O BUS) pins: 48 I AL1 E3-5 INPUT BAC1 (DATA FROM I/O BUS) pins: 49 I AM1 E6-11 INPUT BAC2 (DATA FROM I/O BUS) pins: 50 O BK2 E15-1 OUTPUT DATA00-N (OMNIBUS DATA00) (8881 OPEN COLLECTOR OUTPUT) pins: 51 O BL2 E15-4 OUTPUT DATA01-N (OMNIBUS DATA01) (8881 OPEN COLLECTOR OUTPUT) pins: 52 O BM2 E15-10 OUTPUT DATA02-N (OMNIBUS DATA02) (8881 OPEN COLLECTOR OUTPUT) pins: 53 P AF1 E4-3 OUTPUT I/O BUS ACIN0-N (75452 OPEN COLLECTOR OUTPUT) pins: 54 P AH1 E5-3 OUTPUT I/O BUS ACIN1-N (75452 OPEN COLLECTOR OUTPUT) pins: 55 P AJ1 E8-5 OUTPUT I/O BUS ACIN2-N (75452 OPEN COLLECTOR OUTPUT) pins: 56 P AF2 E7-5 OUTPUT I/O BUS DATA0-N (75452 OPEN COLLECTOR OUTPUT) pins: 57 P AH2 E3-3 OUTPUT I/O BUS DATA1-N (75452 OPEN COLLECTOR OUTPUT) pins: 58 P AJ2 E7-3 OUTPUT I/O BUS DATA2-N (75452 OPEN COLLECTOR OUTPUT) pins: direction: IPIPIPIOIOIOOIOOIPOIOIIOIIOIIOIPIPIPIPIPOIPIOIIIIOOOPPPPPP test 1: 0101010000001001001010010010010000000000101010000111111111 comment: comment: ; INPUT 1 -> OUTPUT 1-N test 2: 10 test 3: 01 comment: comment: ; INPUT 2 -> OUTPUT 2-N test 4: 10 test 5: 01 comment: comment: ; INPUT 3 -> OUTPUT 3-N test 6: 10 test 7: 01 comment: comment: ; INPUT 4 -> OUTPUT 4 test 8: 11 test 9: 00 comment: comment: ; INPUT 5 -> OUTPUT 5 test 10: 11 test 11: 00 comment: comment: ; INPUT 6 -> OUTPUT 6, OUTPUT 6-N test 12: 110 test 13: 001 comment: comment: ; INPUT 7 -> OUTPUT 7, OUTPUT 7-N test 14: 110 test 15: 001 comment: comment: ; INPUT 8 -> OUTPUT 8, OUTPUT 8-N test 16: 110 test 17: 001 comment: comment: ; INPUT 9 -> OOUTPUT 9-N test 18: 10 test 19: 01 comment: comment: ; INPUT 10A NOR INPUT 10B -> OUTPUT 10 test 20: 010 test 21: 110 test 22: 100 test 23: 001 comment: comment: ; INPUT 11A NOR INPUT 11B -> OUTPUT 11 test 24: 010 test 25: 110 test 26: 100 test 27: 001 comment: comment: ; INPUT 12A NAND INPUT 12B -> OUTPUT 12 test 28: 011 test 29: 110 test 30: 101 test 31: 001 comment: comment: ; INPUT 13 -> OUTPUT 13 test 32: 11 test 33: 00 comment: comment: ; INPUT 14 -> OUTPUT 14 test 34: 11 test 35: 00 comment: comment: ; INPUT 15 -> OUTPUT 15 test 36: 11 test 37: 00 comment: comment: ; INPUT 16 -> OUTPUT 16 test 38: 11 test 39: 00 comment: comment: ; INPUT 17 -> OUTPUT 17, OUTPUT 17-N test 40: 110 test 41: 001 comment: comment: ; INPUT 18 -> OUTPUT 18-N test 42: 10 test 43: 01 comment: comment: ; (no change) test 44: 0101010000001001001010010010010000000000101010000111111111 comment: comment: comment: comment: ; PART 1 unique tests (Posibus BAC0:2 driving Omnibus DATA00:02-N). comment: comment: ; (See PART 2 for Omnibus DATA00:02-N driving). comment: comment: comment: comment: ; Select Omnibus DATA00:02-N -> Posibus DATA0:2-N comment: comment: ; OMNIBUS DATA TO I/O DATA-N LO, OUT-N HI; OMNIBUS DATA TO I/O DATA -> HI test 45: 011 comment: ; (no change) test 46: 000111111111 comment: comment: ; All BAC0:2 patterns (Omnibus DATA00:02-N, Posibus ACIN0:2-N, Posibus DATA0:2-N always HI). comment: ; (Omnibus DATA00:02-N always high due to pullups and no drivers in PART 1 tests) test 47: 001 test 48: 011 test 49: 010 test 50: 110 test 51: 111 test 52: 101 test 53: 100 test 54: 000 comment: comment: comment: comment: ; Select Omnibus DATA00:02-N -> PosiBus ACIN0:2-N comment: comment: ; OMNIBUS DATA TO I/O DATA-N HI, OUT-N HI; OMNIBUS DATA TO I/O DATA -> LO test 55: 101 comment: ; (no change) test 56: 000111111111 comment: comment: ; All BAC0:2 patterns (Omnibus DATA00:02-N, Posibus ACIN0:2-N, Posibus DATA0:2-N always HI). comment: ; (Omnibus DATA00:02-N always high due to pullups and no drivers in PART 1 tests) test 57: 001 test 58: 011 test 59: 010 test 60: 110 test 61: 111 test 62: 101 test 63: 100 test 64: 000 comment: comment: comment: comment: ; Select Posibus BAC0:2 -> Omnibus DATA00:02-N comment: comment: ; OMNIBUS DATA TO I/O DATA-N HI, OUT-N LO; OMNIBUS DATA TO I/O DATA -> LO test 65: 100 comment: ; (no change) test 66: 000111111111 comment: comment: ; All BAC0:2 patterns (PosibusACIN0:2-N and Posibus DATA0:2-N always HI). test 67: 001110 test 68: 011100 test 69: 010101 test 70: 110001 test 71: 111000 test 72: 101010 test 73: 100011 test 74: 000111 comment: comment: comment: comment: ; Select Omnibus DATA00:02-N -> Posibus DATA0:2-N comment: comment: ; OMNIBUS DATA TO I/O DATA-N LO, OUT-N LO; OMNIBUS DATA TO I/O DATA -> HI test 75: 010 comment: ; (no change) test 76: 000111111111 comment: comment: ; All BAC0:2 patterns (Omnibus DATA00:02-N, Posibus ACIN0:2-N, Posibus DATA0:2-N always HI). comment: ; (Omnibus DATA00:02-N always high due to pullups and no drivers in PART 1 tests) test 77: 001 test 78: 011 test 79: 010 test 80: 110 test 81: 111 test 82: 101 test 83: 100 test 84: 000 test 85: comment: ; (no change) test 86: 0101010000001001001010010010010000000000101010000111111111 end: END summary column 1: offset 1, mask 0x1000 column 2: offset 2, mask 0x0080 column 3: offset 1, mask 0x0800 column 4: offset 3, mask 0x0001 column 5: offset 1, mask 0x0400 column 6: offset 3, mask 0x0002 column 7: offset 1, mask 0x0001 column 8: offset 1, mask 0x0008 column 9: offset 1, mask 0x0002 column 10: offset 1, mask 0x0004 column 11: offset 1, mask 0x0010 column 12: offset 1, mask 0x0080 column 13: offset 2, mask 0x1000 column 14: offset 1, mask 0x0020 column 15: offset 1, mask 0x0040 column 16: offset 2, mask 0x2000 column 17: offset 2, mask 0x0400 column 18: offset 4, mask 0x0008 column 19: offset 2, mask 0x0800 column 20: offset 2, mask 0x4000 column 21: offset 2, mask 0x8000 column 22: offset 3, mask 0x1000 column 23: offset 3, mask 0x2000 column 24: offset 3, mask 0x0800 column 25: offset 3, mask 0x4000 column 26: offset 3, mask 0x8000 column 27: offset 2, mask 0x0100 column 28: offset 3, mask 0x0100 column 29: offset 4, mask 0x8000 column 30: offset 3, mask 0x0200 column 31: offset 3, mask 0x0020 column 32: offset 0, mask 0x1000 column 33: offset 3, mask 0x0040 column 34: offset 0, mask 0x0800 column 35: offset 3, mask 0x0080 column 36: offset 0, mask 0x0010 column 37: offset 4, mask 0x0001 column 38: offset 0, mask 0x0008 column 39: offset 4, mask 0x2000 column 40: offset 0, mask 0x4000 column 41: offset 4, mask 0x0004 column 42: offset 4, mask 0x1000 column 43: offset 0, mask 0x8000 column 44: offset 2, mask 0x0020 column 45: offset 2, mask 0x0200 column 46: offset 2, mask 0x0040 column 47: offset 1, mask 0x8000 column 48: offset 1, mask 0x4000 column 49: offset 1, mask 0x2000 column 50: offset 3, mask 0x0004 column 51: offset 3, mask 0x0008 column 52: offset 3, mask 0x0010 column 53: offset 0, mask 0x0400 column 54: offset 0, mask 0x0200 column 55: offset 0, mask 0x0100 column 56: offset 0, mask 0x0004 column 57: offset 0, mask 0x0002 column 58: offset 0, mask 0x0001 direction bits (1=input) 0xFFFF 0x03CC 0xBB9B 0x0E1F 0x40FE pullup bits (1=pullup) 0xDF1F 0x0000 0x0080 0x0003 0x0008 test step out_data dont care 1: 0x8707 0x0000 0xBB80 0x0A1F 0x0004 2: 0x8707 0x1000 0xBB00 0x0A1F 0x0004 3: 0x8707 0x0000 0xBB80 0x0A1F 0x0004 4: 0x8707 0x0800 0xBB80 0x0A1E 0x0004 5: 0x8707 0x0000 0xBB80 0x0A1F 0x0004 6: 0x8707 0x0400 0xBB80 0x0A1D 0x0004 7: 0x8707 0x0000 0xBB80 0x0A1F 0x0004 8: 0x8707 0x0009 0xBB80 0x0A1F 0x0004 9: 0x8707 0x0000 0xBB80 0x0A1F 0x0004 10: 0x8707 0x0006 0xBB80 0x0A1F 0x0004 11: 0x8707 0x0000 0xBB80 0x0A1F 0x0004 12: 0x8707 0x0090 0xAB80 0x0A1F 0x0004 13: 0x8707 0x0000 0xBB80 0x0A1F 0x0004 14: 0x8707 0x0060 0x9B80 0x0A1F 0x0004 15: 0x8707 0x0000 0xBB80 0x0A1F 0x0004 16: 0x8707 0x0000 0xB780 0x0A1F 0x000C 17: 0x8707 0x0000 0xBB80 0x0A1F 0x0004 18: 0x8707 0x0000 0x7B80 0x0A1F 0x0004 19: 0x8707 0x0000 0xBB80 0x0A1F 0x0004 20: 0x8707 0x0000 0xBB80 0x221F 0x0004 21: 0x8707 0x0000 0xBB80 0x321F 0x0004 22: 0x8707 0x0000 0xBB80 0x121F 0x0004 23: 0x8707 0x0000 0xBB80 0x0A1F 0x0004 24: 0x8707 0x0000 0xBA80 0x8A1F 0x0004 25: 0x8707 0x0000 0xBA80 0xCA1F 0x0004 26: 0x8707 0x0000 0xBA80 0x4A1F 0x0004 27: 0x8707 0x0000 0xBB80 0x0A1F 0x0004 28: 0x8707 0x0000 0xBB80 0x0A1F 0x8004 29: 0x8707 0x0000 0xBB80 0x091F 0x8004 30: 0x8707 0x0000 0xBB80 0x0B1F 0x0004 31: 0x8707 0x0000 0xBB80 0x0A1F 0x0004 32: 0x9707 0x0000 0xBB80 0x0A3F 0x0004 33: 0x8707 0x0000 0xBB80 0x0A1F 0x0004 34: 0x8F07 0x0000 0xBB80 0x0A5F 0x0004 35: 0x8707 0x0000 0xBB80 0x0A1F 0x0004 36: 0x8717 0x0000 0xBB80 0x0A9F 0x0004 37: 0x8707 0x0000 0xBB80 0x0A1F 0x0004 38: 0x870F 0x0000 0xBB80 0x0A1F 0x0005 39: 0x8707 0x0000 0xBB80 0x0A1F 0x0004 40: 0xC707 0x0000 0xBB80 0x0A1F 0x2000 41: 0x8707 0x0000 0xBB80 0x0A1F 0x0004 42: 0x0707 0x0000 0xBB80 0x0A1F 0x1004 43: 0x8707 0x0000 0xBB80 0x0A1F 0x0004 44: 0x8707 0x0000 0xBB80 0x0A1F 0x0004 45: 0x8707 0x0000 0xBBC0 0x0A1F 0x0004 46: 0x8707 0x0000 0xBBC0 0x0A1F 0x0004 47: 0x8707 0x2000 0xBBC0 0x0A1F 0x0004 48: 0x8707 0x6000 0xBBC0 0x0A1F 0x0004 49: 0x8707 0x4000 0xBBC0 0x0A1F 0x0004 50: 0x8707 0xC000 0xBBC0 0x0A1F 0x0004 51: 0x8707 0xE000 0xBBC0 0x0A1F 0x0004 52: 0x8707 0xA000 0xBBC0 0x0A1F 0x0004 53: 0x8707 0x8000 0xBBC0 0x0A1F 0x0004 54: 0x8707 0x0000 0xBBC0 0x0A1F 0x0004 55: 0x8707 0x0000 0xB9E0 0x0A1F 0x0004 56: 0x8707 0x0000 0xB9E0 0x0A1F 0x0004 57: 0x8707 0x2000 0xB9E0 0x0A1F 0x0004 58: 0x8707 0x6000 0xB9E0 0x0A1F 0x0004 59: 0x8707 0x4000 0xB9E0 0x0A1F 0x0004 60: 0x8707 0xC000 0xB9E0 0x0A1F 0x0004 61: 0x8707 0xE000 0xB9E0 0x0A1F 0x0004 62: 0x8707 0xA000 0xB9E0 0x0A1F 0x0004 63: 0x8707 0x8000 0xB9E0 0x0A1F 0x0004 64: 0x8707 0x0000 0xB9E0 0x0A1F 0x0004 65: 0x8707 0x0000 0xB9A0 0x0A1F 0x0004 66: 0x8707 0x0000 0xB9A0 0x0A1F 0x0004 67: 0x8707 0x2000 0xB9A0 0x0A0F 0x0004 68: 0x8707 0x6000 0xB9A0 0x0A07 0x0004 69: 0x8707 0x4000 0xB9A0 0x0A17 0x0004 70: 0x8707 0xC000 0xB9A0 0x0A13 0x0004 71: 0x8707 0xE000 0xB9A0 0x0A03 0x0004 72: 0x8707 0xA000 0xB9A0 0x0A0B 0x0004 73: 0x8707 0x8000 0xB9A0 0x0A1B 0x0004 74: 0x8707 0x0000 0xB9A0 0x0A1F 0x0004 75: 0x8707 0x0000 0xBB80 0x0A1F 0x0004 76: 0x8707 0x0000 0xBB80 0x0A1F 0x0004 77: 0x8707 0x2000 0xBB80 0x0A1F 0x0004 78: 0x8707 0x6000 0xBB80 0x0A1F 0x0004 79: 0x8707 0x4000 0xBB80 0x0A1F 0x0004 80: 0x8707 0xC000 0xBB80 0x0A1F 0x0004 81: 0x8707 0xE000 0xBB80 0x0A1F 0x0004 82: 0x8707 0xA000 0xBB80 0x0A1F 0x0004 83: 0x8707 0x8000 0xBB80 0x0A1F 0x0004 84: 0x8707 0x0000 0xBB80 0x0A1F 0x0004 85: 0x8707 0x0000 0xBB80 0x0A1F 0x0004 86: 0x8707 0x0000 0xBB80 0x0A1F 0x0004 PINs used (in edge connector order) (G=ground,P=power) SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBB LETTER ABCDEFHJKLMNPRSTUVABCDEFHJKLMNPRSTUVABCDEFHJKLMNPRSTUVABCDEFHJKLMNPRSTUV SIDE 111111111111111111222222222222222222111111111111111111222222222222222222 USAGE PP PPPPPIIIIII GOIP GPPPPPIIOOIIOO OOOIOOIIIIO OIIGIIP GIIPPPOOOIIII OP UUT inputs: 26 UUT outputs: 32 pins used: 58 not used: 8 86 'test steps' 244 lines M7102 PCB REV D SCHEMATIC REV C Positive I/O Bus Converter (DW08E) PART 1 Tests Posibus driving Omnibus DATA BUS. (See PART 2 for Omnibus driving Posibus. (Two parts are necessary due to the Omnibus DATA00:02-N is a bidirectional bus). Needs 3.3k ohm pullups to +5v on pin: BK2 Omnibus DATA00 (bidirectional, input + open collector output) BL2 Omnibus DATA01 (bidirectional, input + open collector output) BM2 Omnibus DATA02 (bidirectional, input + open collector output) PINS Main menu Sun Nov 22 19:01:38 2015 test file is: tests\m7102_1.tst delay is: 0 trigger is: 1 1 read test file 2 set test delay 3 set test trigger 4 run test 5 output loading test 8 diags 9 exit UUT power is okay Sun Nov 22 19:01:40 2015 space single step O run once (one test, all steps) F run, stop on fail G go (run tests N run, stop on fail, no print S scope (run, no print) C toggle comment printout + increase speed (less delay) - decrease speed (more delay)(slower) Q quit test step 1 0101010000001001001010010010010000000000101010000111111111 step 2 1001010000001001001010010010010000000000101010000111111111 step 3 0101010000001001001010010010010000000000101010000111111111 step 4 0110010000001001001010010010010000000000101010000111111111 step 5 0101010000001001001010010010010000000000101010000111111111 step 6 0101100000001001001010010010010000000000101010000111111111 step 7 0101010000001001001010010010010000000000101010000111111111 step 8 0101011100001001001010010010010000000000101010000111111111 step 9 0101010000001001001010010010010000000000101010000111111111 step 10 0101010011001001001010010010010000000000101010000111111111 step 11 0101010000001001001010010010010000000000101010000111111111 step 12 0101010000110001001010010010010000000000101010000111111111 step 13 0101010000001001001010010010010000000000101010000111111111 step 14 0101010000001110001010010010010000000000101010000111111111 step 15 0101010000001001001010010010010000000000101010000111111111 step 16 0101010000001001110010010010010000000000101010000111111111 step 17 0101010000001001001010010010010000000000101010000111111111 step 18 0101010000001001001100010010010000000000101010000111111111 step 19 0101010000001001001010010010010000000000101010000111111111 step 20 0101010000001001001010100010010000000000101010000111111111 step 21 0101010000001001001011100010010000000000101010000111111111 step 22 0101010000001001001011000010010000000000101010000111111111 step 23 0101010000001001001010010010010000000000101010000111111111 step 24 0101010000001001001010010100010000000000101010000111111111 step 25 0101010000001001001010011100010000000000101010000111111111 step 26 0101010000001001001010011000010000000000101010000111111111 step 27 0101010000001001001010010010010000000000101010000111111111 step 28 0101010000001001001010010010110000000000101010000111111111 step 29 0101010000001001001010010011100000000000101010000111111111 step 30 0101010000001001001010010011010000000000101010000111111111 step 31 0101010000001001001010010010010000000000101010000111111111 step 32 0101010000001001001010010010011100000000101010000111111111 step 33 0101010000001001001010010010010000000000101010000111111111 SLOT ABABABAAAAAABAABBBBAABBBBBBBBBBABABABABABBABBBAAABBBAAAAAA LETTER NFPHRJKNLMPTBRSADVCVULKMJHFRSPNDPERDSEUBUVADEEKLMKLMFHJFHJ SIDE 1212122222221221121111111111112121222211211212111222111222 DIRECTION IPIPIPIOIOIOOIOOIPOIOIIOIIOIIOIPIPIPIPIPOIPIOIIIIOOOPPPPPP changed: 1 step 34 0101010000001001001010010010010010000000101010000111111111 fail ^ step 35 0101010000001001001010010010010000000000101010000111111111 SLOT ABABABAAAAAABAABBBBAABBBBBBBBBBABABABABABBABBBAAABBBAAAAAA LETTER NFPHRJKNLMPTBRSADVCVULKMJHFRSPNDPERDSEUBUVADEEKLMKLMFHJFHJ SIDE 1212122222221221121111111111112121222211211212111222111222 DIRECTION IPIPIPIOIOIOOIOOIPOIOIIOIIOIIOIPIPIPIPIPOIPIOIIIIOOOPPPPPP changed: 1 step 36 0101010000001001001010010010010000100000101010000111111111 fail ^ step 37 0101010000001001001010010010010000000000101010000111111111 SLOT ABABABAAAAAABAABBBBAABBBBBBBBBBABABABABABBABBBAAABBBAAAAAA LETTER NFPHRJKNLMPTBRSADVCVULKMJHFRSPNDPERDSEUBUVADEEKLMKLMFHJFHJ SIDE 1212122222221221121111111111112121222211211212111222111222 DIRECTION IPIPIPIOIOIOOIOOIPOIOIIOIIOIIOIPIPIPIPIPOIPIOIIIIOOOPPPPPP changed: 1 step 38 0101010000001001001010010010010000001000101010000111111111 fail ^ step 39 0101010000001001001010010010010000000000101010000111111111 step 40 0101010000001001001010010010010000000011001010000111111111 step 41 0101010000001001001010010010010000000000101010000111111111 step 42 0101010000001001001010010010010000000000110010000111111111 step 43 0101010000001001001010010010010000000000101010000111111111 step 44 0101010000001001001010010010010000000000101010000111111111 step 45 0101010000001001001010010010010000000000101011000111111111 step 46 0101010000001001001010010010010000000000101011000111111111 step 47 0101010000001001001010010010010000000000101011001111111111 step 48 0101010000001001001010010010010000000000101011011111111111 step 49 0101010000001001001010010010010000000000101011010111111111 step 50 0101010000001001001010010010010000000000101011110111111111 step 51 0101010000001001001010010010010000000000101011111111111111 step 52 0101010000001001001010010010010000000000101011101111111111 step 53 0101010000001001001010010010010000000000101011100111111111 step 54 0101010000001001001010010010010000000000101011000111111111 step 55 0101010000001001001010010010010000000000101101000111111111 step 56 0101010000001001001010010010010000000000101101000111111111 step 57 0101010000001001001010010010010000000000101101001111111111 step 58 0101010000001001001010010010010000000000101101011111111111 step 59 0101010000001001001010010010010000000000101101010111111111 step 60 0101010000001001001010010010010000000000101101110111111111 step 61 0101010000001001001010010010010000000000101101111111111111 step 62 0101010000001001001010010010010000000000101101101111111111 step 63 0101010000001001001010010010010000000000101101100111111111 step 64 0101010000001001001010010010010000000000101101000111111111 step 65 0101010000001001001010010010010000000000101100000111111111 step 66 0101010000001001001010010010010000000000101100000111111111 step 67 0101010000001001001010010010010000000000101100001110111111 step 68 0101010000001001001010010010010000000000101100011100111111 step 69 0101010000001001001010010010010000000000101100010101111111 step 70 0101010000001001001010010010010000000000101100110001111111 step 71 0101010000001001001010010010010000000000101100111000111111 step 72 0101010000001001001010010010010000000000101100101010111111 step 73 0101010000001001001010010010010000000000101100100011111111 step 74 0101010000001001001010010010010000000000101100000111111111 step 75 0101010000001001001010010010010000000000101010000111111111 step 76 0101010000001001001010010010010000000000101010000111111111 step 77 0101010000001001001010010010010000000000101010001111111111 step 78 0101010000001001001010010010010000000000101010011111111111 step 79 0101010000001001001010010010010000000000101010010111111111 step 80 0101010000001001001010010010010000000000101010110111111111 step 81 0101010000001001001010010010010000000000101010111111111111 step 82 0101010000001001001010010010010000000000101010101111111111 step 83 0101010000001001001010010010010000000000101010100111111111 step 84 0101010000001001001010010010010000000000101010000111111111 step 85 0101010000001001001010010010010000000000101010000111111111 step 86 0101010000001001001010010010010000000000101010000111111111 test 1: *** FAIL *************************** 3 steps failed SLOT ABABABAAAAAABAABBBBAABBBBBBBBBBABABABABABBABBBAAABBBAAAAAA LETTER NFPHRJKNLMPTBRSADVCVULKMJHFRSPNDPERDSEUBUVADEEKLMKLMFHJFHJ SIDE 1212122222221221121111111111112121222211211212111222111222 DIRECTION IPIPIPIOIOIOOIOOIPOIOIIOIIOIIOIPIPIPIPIPOIPIOIIIIOOOPPPPPP this fail P P P all fails P P P was hi 111111111111111111111111111111111 1 1 11111111111111111111 rising ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ ^ ^ ^^^^^^^^^^^^^^ falling vvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvv v v vvvvvvvvvvvvvv was lo 0000000000000000000000000000000000000000000000000000 total fails 1, total passes 0 space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C toggle comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit failure mode analysis: pin: 34 P AE1 E2-3 OUTPUT 14 (75452 OPEN COLLECTOR OUTPUT) SLOT ABABABAAAAAABAABBBBAABBBBBBBBBBABABABABABBABBBAAABBBAAAAAA LETTER NFPHRJKNLMPTBRSADVCVULKMJHFRSPNDPERDSEUBUVADEEKLMKLMFHJFHJ SIDE 1212122222221221121111111111112121222211211212111222111222 DIRECTION IPIPIPIOIOIOOIOOIPOIOIIOIIOIIOIPIPIPIPIPOIPIOIIIIOOOPPPPPP fails LO: 1 1 1 1 1 1 1 1 1 1 1 1 1 1 111111111 fails LO: 0 0 0 000000 00 00 0 00 00 00 00 000000 0 0 0000 fails HI: fails HI: pin: 36 P AD2 E5-5 OUTPUT 15 (75452 OPEN COLLECTOR OUTPUT) SLOT ABABABAAAAAABAABBBBAABBBBBBBBBBABABABABABBABBBAAABBBAAAAAA LETTER NFPHRJKNLMPTBRSADVCVULKMJHFRSPNDPERDSEUBUVADEEKLMKLMFHJFHJ SIDE 1212122222221221121111111111112121222211211212111222111222 DIRECTION IPIPIPIOIOIOOIOOIPOIOIIOIIOIIOIPIPIPIPIPOIPIOIIIIOOOPPPPPP fails LO: 1 1 1 1 1 1 1 1 1 1 1 1 1 1 111111111 fails LO: 0 0 0 000000 00 00 0 00 00 00 0000 0000 0 0 0000 fails HI: fails HI: pin: 38 P AE2 E4-5 OUTPUT 16 (75452 OPEN COLLECTOR OUTPUT) SLOT ABABABAAAAAABAABBBBAABBBBBBBBBBABABABABABBABBBAAABBBAAAAAA LETTER NFPHRJKNLMPTBRSADVCVULKMJHFRSPNDPERDSEUBUVADEEKLMKLMFHJFHJ SIDE 1212122222221221121111111111112121222211211212111222111222 DIRECTION IPIPIPIOIOIOOIOOIPOIOIIOIIOIIOIPIPIPIPIPOIPIOIIIIOOOPPPPPP fails LO: 1 1 1 1 1 1 1 1 1 1 1 1 1 1 111111111 fails LO: 0 0 0 000000 00 00 0 00 00 00 000000 00 0 0 0000 fails HI: fails HI: space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C toggle comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit up to this point: PINS that are always low 34 P AE1 E2-3 OUTPUT 14 (75452 OPEN COLLECTOR OUTPUT) 36 P AD2 E5-5 OUTPUT 15 (75452 OPEN COLLECTOR OUTPUT) 38 P AE2 E4-5 OUTPUT 16 (75452 OPEN COLLECTOR OUTPUT) PINS that are always high 53 P AF1 E4-3 OUTPUT I/O BUS ACIN0-N (75452 OPEN COLLECTOR OUTPUT) 54 P AH1 E5-3 OUTPUT I/O BUS ACIN1-N (75452 OPEN COLLECTOR OUTPUT) 55 P AJ1 E8-5 OUTPUT I/O BUS ACIN2-N (75452 OPEN COLLECTOR OUTPUT) 56 P AF2 E7-5 OUTPUT I/O BUS DATA0-N (75452 OPEN COLLECTOR OUTPUT) 57 P AH2 E3-3 OUTPUT I/O BUS DATA1-N (75452 OPEN COLLECTOR OUTPUT) 58 P AJ2 E7-3 OUTPUT I/O BUS DATA2-N (75452 OPEN COLLECTOR OUTPUT) space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C toggle comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT ABABABAAAAAABAABBBBAABBBBBBBBBBABABABABABBABBBAAABBBAAAAAA LETTER NFPHRJKNLMPTBRSADVCVULKMJHFRSPNDPERDSEUBUVADEEKLMKLMFHJFHJ SIDE 1212122222221221121111111111112121222211211212111222111222 DIRECTION IPIPIPIOIOIOOIOOIPOIOIIOIIOIIOIPIPIPIPIPOIPIOIIIIOOOPPPPPP all fails P P P was lo 0000000000000000000000000000000000000000000000000000 falling vvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvv v v vvvvvvvvvvvvvv rising ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ ^ ^ ^^^^^^^^^^^^^^ was hi 111111111111111111111111111111111 1 1 11111111111111111111 total fails 1, total passes 0 Main menu Sun Nov 22 19:01:51 2015 test file is: tests\m7102_1.tst delay is: 0 trigger is: 1 1 read test file 2 set test delay 3 set test trigger 4 run test 5 output loading test 8 diags 9 exit Enter test file name? trying to open test file: tests\m7102_2.tst reading test file: tests\m7102_2.tst comment: M7102 PCB REV D SCHEMATIC REV C Positive I/O Bus Converter (DW08E) comment: comment: PART 2 Tests Omnibus DATA BUS driving Posibus ACIN and DATA. comment: (See PART 1 for Posibus driving Omnibus. comment: comment: (Two parts are necessary due to the Omnibus DATA00:02-N is a bidirectional bus). comment: comment: Tolerates 3.3k ohm pullups to +5v on pin (are needed for PART 1): comment: BK2 Omnibus DATA00 (bidirectional, input + open collector output) comment: BL2 Omnibus DATA01 (bidirectional, input + open collector output) comment: BM2 Omnibus DATA02 (bidirectional, input + open collector output) comment: pins: PINS pins: 1 I AN1 E6-9 INPUT 1 pins: 2 P BF2 E13-8 OUTPUT A-N (7416 OPEN COLLECTOR OUTPUT) pins: 3 I AP1 E6-6 INPUT 2 pins: 4 P BH2 E13-7 OUTPUT 2-N (7416 OPEN COLLECTOR OUTPUT) pins: 5 I AR1 E6-5 INPUT 3 pins: 6 P BJ2 E13-6 OUTPUT 3-N (7416 OPEN COLLECTOR OUTPUT) pins: 7 I AK2 E9-11 INPUT 4 pins: 8 O AN2 E9-13 OUTPUT 4 (384 OUTPUT) pins: 9 I AL2 E9-9 INPUT 5 pins: 10 O AM2 E9-14 OUTPUT 5 (384 OUTPUT) pins: 11 I AP2 E9-6 INPUT 6 pins: 12 O AT2 E9-2 OUTPUT 6 (384 OUTPUT) pins: 13 O BB1 E11-6 OUTPUT 6-N (74H04 OUTPUT) pins: 14 I AR2 E9-5 INPUT 7 pins: 15 O AS2 E9-3 OUTPUT 7 (384 OUTPUT) pins: 16 O BA1 E11-10 OUTPUT 7-N (74H04 OUTPUT) pins: 17 I BD1 E11-1 INPUT 8 pins: 18 P BV2 E13-12 OUTPUT 8 (7416 OPEN COLLECTOR OUTPUT) pins: 19 O BC1 E11-2 OUTPUT 8-N (74H04 OUTPUT) pins: 20 I AV1 E11-13 INPUT 9 pins: 21 O AU1 E11-12 OUTPUT 9-N (74H04 OUTPUT) pins: 22 I BL1 E12-4 INPUT 10A pins: 23 I BK1 E12-5 INPUT 10B pins: 24 O BM1 E12-3 OUTPUT 10 = INPUT 10A NOR INPUT 10B (380 OUTPUT) pins: 25 I BJ1 E12-9 INPUT 11A pins: 26 I BH1 E12-10 INPUT 11B pins: 27 O BF1 E12-14 OUTPUT 11 = INPUT 11A NOR INPUT 11B (M380 OUTPUT) pins: 28 I BR1 E15-12 INPUT 12A pins: 29 I BS1 E15-11 INPUT 12B pins: 30 O BP1 E15-? OUTPUT 12 = INPUT 12A NAND INPUT 12B (8881 OPEN COLLECTOR OUTPUT WITH 3.3K PULLUP) pins: 31 I BN2 E10-6,7 INPUT 13 pins: 32 P AD1 E1-3 OUTPUT 13 (75452 OPEN COLLECTOR OUTPUT) pins: 33 I BP2 E14-11,12 INPUT 14 pins: 34 P AE1 E2-3 OUTPUT 14 (75452 OPEN COLLECTOR OUTPUT) pins: 35 I BR2 E14-9,10 INPUT 15 pins: 36 P AD2 E5-5 OUTPUT 15 (75452 OPEN COLLECTOR OUTPUT) pins: 37 I BS2 E14-6,7 INPUT 16 pins: 38 P AE2 E4-5 OUTPUT 16 (75452 OPEN COLLECTOR OUTPUT) pins: 39 I BU1 E14-4,5 INPUT 17 pins: 40 P AB1 E4-5 OUTPUT 17 (75452 OPEN COLLECTOR OUTPUT) pins: 41 O BU2 E14-3 OUTPUT 17-N (380 OUTPUT) pins: 42 I BV1 E2-6,7 INPUT 18 pins: 43 P AA1 E2-5 OUTPUT 18-N (75452 OPEN COLLECTOR OUTPUT) pins: 44 I BD2 E11-3 OMNIBUS DATA TO I/O DATA-N (LOW ALSO DISABLES BAC <> OMNIBUS) pins: 45 O BE1 E11-4 OMNIBUS DATA TO I/O DATA (74H04 OUTPUT) pins: 46 I BE2 E12-12 INPUT OUT-N (L -> BAC TO OMNIBUS, H -> OMNIBUS TO BAC) pins: 47 I AK1 E3-6 INPUT BAC0 (DATA FROM I/O BUS) pins: 48 I AL1 E3-5 INPUT BAC1 (DATA FROM I/O BUS) pins: 49 I AM1 E6-11 INPUT BAC2 (DATA FROM I/O BUS) pins: 50 I BK2 E15-1 INPUT DATA00-N (OMNIBUS DATA00) (8881 OPEN COLLECTOR OUTPUT) pins: 51 I BL2 E15-4 INPUT DATA01-N (OMNIBUS DATA01) (8881 OPEN COLLECTOR OUTPUT) pins: 52 I BM2 E15-10 INPUT DATA02-N (OMNIBUS DATA02) (8881 OPEN COLLECTOR OUTPUT) pins: 53 P AF1 E4-3 OUTPUT I/O BUS ACIN0-N (75452 OPEN COLLECTOR OUTPUT) pins: 54 P AH1 E5-3 OUTPUT I/O BUS ACIN1-N (75452 OPEN COLLECTOR OUTPUT) pins: 55 P AJ1 E8-5 OUTPUT I/O BUS ACIN2-N (75452 OPEN COLLECTOR OUTPUT) pins: 56 P AF2 E7-5 OUTPUT I/O BUS DATA0-N (75452 OPEN COLLECTOR OUTPUT) pins: 57 P AH2 E3-3 OUTPUT I/O BUS DATA1-N (75452 OPEN COLLECTOR OUTPUT) pins: 58 P AJ2 E7-3 OUTPUT I/O BUS DATA2-N (75452 OPEN COLLECTOR OUTPUT) pins: direction: IPIPIPIOIOIOOIOOIPOIOIIOIIOIIOIPIPIPIPIPOIPIOIIIIIIIPPPPPP test 1: 0101010000001001001010010010010000000000101010000111111111 comment: comment: ; INPUT 1 -> OUTPUT 1-N test 2: 10 test 3: 01 comment: comment: ; INPUT 2 -> OUTPUT 2-N test 4: 10 test 5: 01 comment: comment: ; INPUT 3 -> OUTPUT 3-N test 6: 10 test 7: 01 comment: comment: ; INPUT 4 -> OUTPUT 4 test 8: 11 test 9: 00 comment: comment: ; INPUT 5 -> OUTPUT 5 test 10: 11 test 11: 00 comment: comment: ; INPUT 6 -> OUTPUT 6, OUTPUT 6-N test 12: 110 test 13: 001 comment: comment: ; INPUT 7 -> OUTPUT 7, OUTPUT 7-N test 14: 110 test 15: 001 comment: comment: ; INPUT 8 -> OUTPUT 8, OUTPUT 8-N test 16: 110 test 17: 001 comment: comment: ; INPUT 9 -> OOUTPUT 9-N test 18: 10 test 19: 01 comment: comment: ; INPUT 10A NOR INPUT 10B -> OUTPUT 10 test 20: 010 test 21: 110 test 22: 100 test 23: 001 comment: comment: ; INPUT 11A NOR INPUT 11B -> OUTPUT 11 test 24: 010 test 25: 110 test 26: 100 test 27: 001 comment: comment: ; INPUT 12A NAND INPUT 12B -> OUTPUT 12 test 28: 011 test 29: 110 test 30: 101 test 31: 001 comment: comment: ; INPUT 13 -> OUTPUT 13 test 32: 11 test 33: 00 comment: comment: ; INPUT 14 -> OUTPUT 14 test 34: 11 test 35: 00 comment: comment: ; INPUT 15 -> OUTPUT 15 test 36: 11 test 37: 00 comment: comment: ; INPUT 16 -> OUTPUT 16 test 38: 11 test 39: 00 comment: comment: ; INPUT 17 -> OUTPUT 17, OUTPUT 17-N test 40: 110 test 41: 001 comment: comment: ; INPUT 18 -> OUTPUT 18-N test 42: 10 test 43: 01 comment: comment: ; (no change) test 44: 0101010000001001001010010010010000000000101010000111111111 comment: comment: comment: comment: ; PART 2 unique tests (Omnibus DATA00:02-N driving Posibus ACIN and DATA) comment: comment: ; (See PART 1 for Posibus driving Omnibus). comment: comment: comment: comment: ; Select Omnibus DATA00:02-N -> Posibus DATA0:2-N comment: comment: ; OMNIBUS DATA TO I/O DATA-N LO, OUT-N HI; OMNIBUS DATA TO I/O DATA -> HI test 45: 011 comment: ; (no change) test 46: 000111111111 comment: comment: ; All DATA00:02-N patterns (Posibus ACIN0:2-N always HI). test 47: 101 101 test 48: 100 100 test 49: 000 000 test 50: 001 001 test 51: 011 011 test 52: 010 010 test 53: 110 110 test 54: 111 111 comment: comment: comment: comment: ; Select Omnibus DATA00:02-N -> PosiBus ACIN0:2-N comment: comment: ; OMNIBUS DATA TO I/O DATA-N HI, OUT-N HI; OMNIBUS DATA TO I/O DATA -> LO test 55: 101 comment: ; (no change) test 56: 000111111111 comment: comment: ; All DATA00:02-N patterns (Posibus DATA0:2-N always HI). test 57: 101101 test 58: 100100 test 59: 000000 test 60: 001001 test 61: 011011 test 62: 010010 test 63: 110110 test 64: 111111 comment: comment: comment: ; Do not select Posibus BAC0:2 -> Omnibus DATA00:02-N comment: ; (we drive Omnibus DATA00:02-N in PART 2). comment: ; skip >>>>> 100 comment: comment: comment: comment: ; Select Omnibus DATA00:02-N -> Posibus DATA0:2-N comment: comment: ; Do 2 steps to avoid >>>>> 100 comment: ; OMNIBUS DATA TO I/O DATA-N LO, OUT-N HI; OMNIBUS DATA TO I/O DATA -> HI test 65: 011 comment: comment: ; OMNIBUS DATA TO I/O DATA-N LO, OUT-N LO; OMNIBUS DATA TO I/O DATA -> HI test 66: 010 comment: ; (no change) test 67: 000111111111 comment: comment: ; All DATA00:02-N patterns (Posibus ACIN0:2-N always HI). test 68: 101 101 test 69: 100 100 test 70: 000 000 test 71: 001 001 test 72: 011 011 test 73: 010 010 test 74: 110 110 test 75: 111 111 comment: comment: ; (no change) test 76: 0101010000001001001010010010010000000000101010000111111111 end: END summary column 1: offset 1, mask 0x1000 column 2: offset 2, mask 0x0080 column 3: offset 1, mask 0x0800 column 4: offset 3, mask 0x0001 column 5: offset 1, mask 0x0400 column 6: offset 3, mask 0x0002 column 7: offset 1, mask 0x0001 column 8: offset 1, mask 0x0008 column 9: offset 1, mask 0x0002 column 10: offset 1, mask 0x0004 column 11: offset 1, mask 0x0010 column 12: offset 1, mask 0x0080 column 13: offset 2, mask 0x1000 column 14: offset 1, mask 0x0020 column 15: offset 1, mask 0x0040 column 16: offset 2, mask 0x2000 column 17: offset 2, mask 0x0400 column 18: offset 4, mask 0x0008 column 19: offset 2, mask 0x0800 column 20: offset 2, mask 0x4000 column 21: offset 2, mask 0x8000 column 22: offset 3, mask 0x1000 column 23: offset 3, mask 0x2000 column 24: offset 3, mask 0x0800 column 25: offset 3, mask 0x4000 column 26: offset 3, mask 0x8000 column 27: offset 2, mask 0x0100 column 28: offset 3, mask 0x0100 column 29: offset 4, mask 0x8000 column 30: offset 3, mask 0x0200 column 31: offset 3, mask 0x0020 column 32: offset 0, mask 0x1000 column 33: offset 3, mask 0x0040 column 34: offset 0, mask 0x0800 column 35: offset 3, mask 0x0080 column 36: offset 0, mask 0x0010 column 37: offset 4, mask 0x0001 column 38: offset 0, mask 0x0008 column 39: offset 4, mask 0x2000 column 40: offset 0, mask 0x4000 column 41: offset 4, mask 0x0004 column 42: offset 4, mask 0x1000 column 43: offset 0, mask 0x8000 column 44: offset 2, mask 0x0020 column 45: offset 2, mask 0x0200 column 46: offset 2, mask 0x0040 column 47: offset 1, mask 0x8000 column 48: offset 1, mask 0x4000 column 49: offset 1, mask 0x2000 column 50: offset 3, mask 0x0004 column 51: offset 3, mask 0x0008 column 52: offset 3, mask 0x0010 column 53: offset 0, mask 0x0400 column 54: offset 0, mask 0x0200 column 55: offset 0, mask 0x0100 column 56: offset 0, mask 0x0004 column 57: offset 0, mask 0x0002 column 58: offset 0, mask 0x0001 direction bits (1=input) 0xFFFF 0x03CC 0xBB9B 0x0E03 0x40FE pullup bits (1=pullup) 0xDF1F 0x0000 0x0080 0x0003 0x0008 test step out_data dont care 1: 0x8707 0x0000 0xBB80 0x0A1F 0x0004 2: 0x8707 0x1000 0xBB00 0x0A1F 0x0004 3: 0x8707 0x0000 0xBB80 0x0A1F 0x0004 4: 0x8707 0x0800 0xBB80 0x0A1E 0x0004 5: 0x8707 0x0000 0xBB80 0x0A1F 0x0004 6: 0x8707 0x0400 0xBB80 0x0A1D 0x0004 7: 0x8707 0x0000 0xBB80 0x0A1F 0x0004 8: 0x8707 0x0009 0xBB80 0x0A1F 0x0004 9: 0x8707 0x0000 0xBB80 0x0A1F 0x0004 10: 0x8707 0x0006 0xBB80 0x0A1F 0x0004 11: 0x8707 0x0000 0xBB80 0x0A1F 0x0004 12: 0x8707 0x0090 0xAB80 0x0A1F 0x0004 13: 0x8707 0x0000 0xBB80 0x0A1F 0x0004 14: 0x8707 0x0060 0x9B80 0x0A1F 0x0004 15: 0x8707 0x0000 0xBB80 0x0A1F 0x0004 16: 0x8707 0x0000 0xB780 0x0A1F 0x000C 17: 0x8707 0x0000 0xBB80 0x0A1F 0x0004 18: 0x8707 0x0000 0x7B80 0x0A1F 0x0004 19: 0x8707 0x0000 0xBB80 0x0A1F 0x0004 20: 0x8707 0x0000 0xBB80 0x221F 0x0004 21: 0x8707 0x0000 0xBB80 0x321F 0x0004 22: 0x8707 0x0000 0xBB80 0x121F 0x0004 23: 0x8707 0x0000 0xBB80 0x0A1F 0x0004 24: 0x8707 0x0000 0xBA80 0x8A1F 0x0004 25: 0x8707 0x0000 0xBA80 0xCA1F 0x0004 26: 0x8707 0x0000 0xBA80 0x4A1F 0x0004 27: 0x8707 0x0000 0xBB80 0x0A1F 0x0004 28: 0x8707 0x0000 0xBB80 0x0A1F 0x8004 29: 0x8707 0x0000 0xBB80 0x091F 0x8004 30: 0x8707 0x0000 0xBB80 0x0B1F 0x0004 31: 0x8707 0x0000 0xBB80 0x0A1F 0x0004 32: 0x9707 0x0000 0xBB80 0x0A3F 0x0004 33: 0x8707 0x0000 0xBB80 0x0A1F 0x0004 34: 0x8F07 0x0000 0xBB80 0x0A5F 0x0004 35: 0x8707 0x0000 0xBB80 0x0A1F 0x0004 36: 0x8717 0x0000 0xBB80 0x0A9F 0x0004 37: 0x8707 0x0000 0xBB80 0x0A1F 0x0004 38: 0x870F 0x0000 0xBB80 0x0A1F 0x0005 39: 0x8707 0x0000 0xBB80 0x0A1F 0x0004 40: 0xC707 0x0000 0xBB80 0x0A1F 0x2000 41: 0x8707 0x0000 0xBB80 0x0A1F 0x0004 42: 0x0707 0x0000 0xBB80 0x0A1F 0x1004 43: 0x8707 0x0000 0xBB80 0x0A1F 0x0004 44: 0x8707 0x0000 0xBB80 0x0A1F 0x0004 45: 0x8707 0x0000 0xBBC0 0x0A1F 0x0004 46: 0x8707 0x0000 0xBBC0 0x0A1F 0x0004 47: 0x8705 0x0000 0xBBC0 0x0A17 0x0004 48: 0x8704 0x0000 0xBBC0 0x0A07 0x0004 49: 0x8700 0x0000 0xBBC0 0x0A03 0x0004 50: 0x8701 0x0000 0xBBC0 0x0A13 0x0004 51: 0x8703 0x0000 0xBBC0 0x0A1B 0x0004 52: 0x8702 0x0000 0xBBC0 0x0A0B 0x0004 53: 0x8706 0x0000 0xBBC0 0x0A0F 0x0004 54: 0x8707 0x0000 0xBBC0 0x0A1F 0x0004 55: 0x8707 0x0000 0xB9E0 0x0A1F 0x0004 56: 0x8707 0x0000 0xB9E0 0x0A1F 0x0004 57: 0x8507 0x0000 0xB9E0 0x0A17 0x0004 58: 0x8407 0x0000 0xB9E0 0x0A07 0x0004 59: 0x8007 0x0000 0xB9E0 0x0A03 0x0004 60: 0x8107 0x0000 0xB9E0 0x0A13 0x0004 61: 0x8307 0x0000 0xB9E0 0x0A1B 0x0004 62: 0x8207 0x0000 0xB9E0 0x0A0B 0x0004 63: 0x8607 0x0000 0xB9E0 0x0A0F 0x0004 64: 0x8707 0x0000 0xB9E0 0x0A1F 0x0004 65: 0x8707 0x0000 0xBBC0 0x0A1F 0x0004 66: 0x8707 0x0000 0xBB80 0x0A1F 0x0004 67: 0x8707 0x0000 0xBB80 0x0A1F 0x0004 68: 0x8705 0x0000 0xBB80 0x0A17 0x0004 69: 0x8704 0x0000 0xBB80 0x0A07 0x0004 70: 0x8700 0x0000 0xBB80 0x0A03 0x0004 71: 0x8701 0x0000 0xBB80 0x0A13 0x0004 72: 0x8703 0x0000 0xBB80 0x0A1B 0x0004 73: 0x8702 0x0000 0xBB80 0x0A0B 0x0004 74: 0x8706 0x0000 0xBB80 0x0A0F 0x0004 75: 0x8707 0x0000 0xBB80 0x0A1F 0x0004 76: 0x8707 0x0000 0xBB80 0x0A1F 0x0004 PINs used (in edge connector order) (G=ground,P=power) SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBB LETTER ABCDEFHJKLMNPRSTUVABCDEFHJKLMNPRSTUVABCDEFHJKLMNPRSTUVABCDEFHJKLMNPRSTUV SIDE 111111111111111111222222222222222222111111111111111111222222222222222222 USAGE PP PPPPPIIIIII GOIP GPPPPPIIOOIIOO OOOIOOIIIIO OIIGIIP GIIPPPIIIIIII OP UUT inputs: 29 UUT outputs: 29 pins used: 58 not used: 8 76 'test steps' 231 lines M7102 PCB REV D SCHEMATIC REV C Positive I/O Bus Converter (DW08E) PART 2 Tests Omnibus DATA BUS driving Posibus ACIN and DATA. (See PART 1 for Posibus driving Omnibus. (Two parts are necessary due to the Omnibus DATA00:02-N is a bidirectional bus). Tolerates 3.3k ohm pullups to +5v on pin (are needed for PART 1): BK2 Omnibus DATA00 (bidirectional, input + open collector output) BL2 Omnibus DATA01 (bidirectional, input + open collector output) BM2 Omnibus DATA02 (bidirectional, input + open collector output) PINS Main menu Sun Nov 22 19:01:58 2015 test file is: tests\m7102_2.tst delay is: 0 trigger is: 1 1 read test file 2 set test delay 3 set test trigger 4 run test 5 output loading test 8 diags 9 exit UUT power is okay Sun Nov 22 19:02:09 2015 space single step O run once (one test, all steps) F run, stop on fail G go (run tests N run, stop on fail, no print S scope (run, no print) C toggle comment printout + increase speed (less delay) - decrease speed (more delay)(slower) Q quit test step 1 0101010000001001001010010010010000000000101010000111111111 step 2 1001010000001001001010010010010000000000101010000111111111 step 3 0101010000001001001010010010010000000000101010000111111111 step 4 0110010000001001001010010010010000000000101010000111111111 step 5 0101010000001001001010010010010000000000101010000111111111 step 6 0101100000001001001010010010010000000000101010000111111111 step 7 0101010000001001001010010010010000000000101010000111111111 step 8 0101011100001001001010010010010000000000101010000111111111 step 9 0101010000001001001010010010010000000000101010000111111111 step 10 0101010011001001001010010010010000000000101010000111111111 step 11 0101010000001001001010010010010000000000101010000111111111 step 12 0101010000110001001010010010010000000000101010000111111111 step 13 0101010000001001001010010010010000000000101010000111111111 step 14 0101010000001110001010010010010000000000101010000111111111 step 15 0101010000001001001010010010010000000000101010000111111111 step 16 0101010000001001110010010010010000000000101010000111111111 step 17 0101010000001001001010010010010000000000101010000111111111 step 18 0101010000001001001100010010010000000000101010000111111111 step 19 0101010000001001001010010010010000000000101010000111111111 step 20 0101010000001001001010100010010000000000101010000111111111 step 21 0101010000001001001011100010010000000000101010000111111111 step 22 0101010000001001001011000010010000000000101010000111111111 step 23 0101010000001001001010010010010000000000101010000111111111 step 24 0101010000001001001010010100010000000000101010000111111111 step 25 0101010000001001001010011100010000000000101010000111111111 step 26 0101010000001001001010011000010000000000101010000111111111 step 27 0101010000001001001010010010010000000000101010000111111111 step 28 0101010000001001001010010010110000000000101010000111111111 step 29 0101010000001001001010010011100000000000101010000111111111 step 30 0101010000001001001010010011010000000000101010000111111111 step 31 0101010000001001001010010010010000000000101010000111111111 step 32 0101010000001001001010010010011100000000101010000111111111 step 33 0101010000001001001010010010010000000000101010000111111111 SLOT ABABABAAAAAABAABBBBAABBBBBBBBBBABABABABABBABBBAAABBBAAAAAA LETTER NFPHRJKNLMPTBRSADVCVULKMJHFRSPNDPERDSEUBUVADEEKLMKLMFHJFHJ SIDE 1212122222221221121111111111112121222211211212111222111222 DIRECTION IPIPIPIOIOIOOIOOIPOIOIIOIIOIIOIPIPIPIPIPOIPIOIIIIIIIPPPPPP changed: 1 step 34 0101010000001001001010010010010010000000101010000111111111 fail ^ step 35 0101010000001001001010010010010000000000101010000111111111 SLOT ABABABAAAAAABAABBBBAABBBBBBBBBBABABABABABBABBBAAABBBAAAAAA LETTER NFPHRJKNLMPTBRSADVCVULKMJHFRSPNDPERDSEUBUVADEEKLMKLMFHJFHJ SIDE 1212122222221221121111111111112121222211211212111222111222 DIRECTION IPIPIPIOIOIOOIOOIPOIOIIOIIOIIOIPIPIPIPIPOIPIOIIIIIIIPPPPPP changed: 1 step 36 0101010000001001001010010010010000100000101010000111111111 fail ^ step 37 0101010000001001001010010010010000000000101010000111111111 SLOT ABABABAAAAAABAABBBBAABBBBBBBBBBABABABABABBABBBAAABBBAAAAAA LETTER NFPHRJKNLMPTBRSADVCVULKMJHFRSPNDPERDSEUBUVADEEKLMKLMFHJFHJ SIDE 1212122222221221121111111111112121222211211212111222111222 DIRECTION IPIPIPIOIOIOOIOOIPOIOIIOIIOIIOIPIPIPIPIPOIPIOIIIIIIIPPPPPP changed: 1 step 38 0101010000001001001010010010010000001000101010000111111111 fail ^ step 39 0101010000001001001010010010010000000000101010000111111111 step 40 0101010000001001001010010010010000000011001010000111111111 SLOT ABABABAAAAAABAABBBBAABBBBBBBBBBABABABABABBABBBAAABBBAAAAAA LETTER NFPHRJKNLMPTBRSADVCVULKMJHFRSPNDPERDSEUBUVADEEKLMKLMFHJFHJ SIDE 1212122222221221121111111111112121222211211212111222111222 DIRECTION IPIPIPIOIOIOOIOOIPOIOIIOIIOIIOIPIPIPIPIPOIPIOIIIIIIIPPPPPP changed: 00 step 41 0101010000001001001010010010010000000000001010000111111111 fail ^ step 42 0101010000001001001010010010010000000000110010000111111111 step 43 0101010000001001001010010010010000000000101010000111111111 step 44 0101010000001001001010010010010000000000101010000111111111 step 45 0101010000001001001010010010010000000000101011000111111111 step 46 0101010000001001001010010010010000000000101011000111111111 step 47 0101010000001001001010010010010000000000101011000101111101 step 48 0101010000001001001010010010010000000000101011000100111100 step 49 0101010000001001001010010010010000000000101011000000111000 step 50 0101010000001001001010010010010000000000101011000001111001 step 51 0101010000001001001010010010010000000000101011000011111011 step 52 0101010000001001001010010010010000000000101011000010111010 step 53 0101010000001001001010010010010000000000101011000110111110 step 54 0101010000001001001010010010010000000000101011000111111111 step 55 0101010000001001001010010010010000000000101101000111111111 step 56 0101010000001001001010010010010000000000101101000111111111 step 57 0101010000001001001010010010010000000000101101000101101111 step 58 0101010000001001001010010010010000000000101101000100100111 step 59 0101010000001001001010010010010000000000101101000000000111 step 60 0101010000001001001010010010010000000000101101000001001111 step 61 0101010000001001001010010010010000000000101101000011011111 step 62 0101010000001001001010010010010000000000101101000010010111 step 63 0101010000001001001010010010010000000000101101000110110111 step 64 0101010000001001001010010010010000000000101101000111111111 step 65 0101010000001001001010010010010000000000101011000111111111 step 66 0101010000001001001010010010010000000000101010000111111111 step 67 0101010000001001001010010010010000000000101010000111111111 step 68 0101010000001001001010010010010000000000101010000101111101 step 69 0101010000001001001010010010010000000000101010000100111100 step 70 0101010000001001001010010010010000000000101010000000111000 step 71 0101010000001001001010010010010000000000101010000001111001 step 72 0101010000001001001010010010010000000000101010000011111011 step 73 0101010000001001001010010010010000000000101010000010111010 step 74 0101010000001001001010010010010000000000101010000110111110 step 75 0101010000001001001010010010010000000000101010000111111111 step 76 0101010000001001001010010010010000000000101010000111111111 test 1: *** FAIL *************************** 4 steps failed SLOT ABABABAAAAAABAABBBBAABBBBBBBBBBABABABABABBABBBAAABBBAAAAAA LETTER NFPHRJKNLMPTBRSADVCVULKMJHFRSPNDPERDSEUBUVADEEKLMKLMFHJFHJ SIDE 1212122222221221121111111111112121222211211212111222111222 DIRECTION IPIPIPIOIOIOOIOOIPOIOIIOIIOIIOIPIPIPIPIPOIPIOIIIIIIIPPPPPP this fail P P P O all fails P P P O was hi 111111111111111111111111111111111 1 1 11111111 111111111 rising ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ ^ ^ ^^^^^^^^ ^^^^^^^^^ falling vvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvv v v vvvvvvvv vvvvvvvvv was lo 0000000000000000000000000000000000000000000000000000000000 total fails 1, total passes 0 space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C toggle comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit failure mode analysis: pin: 34 P AE1 E2-3 OUTPUT 14 (75452 OPEN COLLECTOR OUTPUT) SLOT ABABABAAAAAABAABBBBAABBBBBBBBBBABABABABABBABBBAAABBBAAAAAA LETTER NFPHRJKNLMPTBRSADVCVULKMJHFRSPNDPERDSEUBUVADEEKLMKLMFHJFHJ SIDE 1212122222221221121111111111112121222211211212111222111222 DIRECTION IPIPIPIOIOIOOIOOIPOIOIIOIIOIIOIPIPIPIPIPOIPIOIIIIIIIPPPPPP fails LO: 1 1 1 1 1 1 1 1 1 1 1 1 1 1 111111111 fails LO: 0 0 0 000000 00 00 0 00 00 00 00 000000 0 0 0000 fails HI: fails HI: pin: 36 P AD2 E5-5 OUTPUT 15 (75452 OPEN COLLECTOR OUTPUT) SLOT ABABABAAAAAABAABBBBAABBBBBBBBBBABABABABABBABBBAAABBBAAAAAA LETTER NFPHRJKNLMPTBRSADVCVULKMJHFRSPNDPERDSEUBUVADEEKLMKLMFHJFHJ SIDE 1212122222221221121111111111112121222211211212111222111222 DIRECTION IPIPIPIOIOIOOIOOIPOIOIIOIIOIIOIPIPIPIPIPOIPIOIIIIIIIPPPPPP fails LO: 1 1 1 1 1 1 1 1 1 1 1 1 1 1 111111111 fails LO: 0 0 0 000000 00 00 0 00 00 00 0000 0000 0 0 0000 fails HI: fails HI: pin: 38 P AE2 E4-5 OUTPUT 16 (75452 OPEN COLLECTOR OUTPUT) SLOT ABABABAAAAAABAABBBBAABBBBBBBBBBABABABABABBABBBAAABBBAAAAAA LETTER NFPHRJKNLMPTBRSADVCVULKMJHFRSPNDPERDSEUBUVADEEKLMKLMFHJFHJ SIDE 1212122222221221121111111111112121222211211212111222111222 DIRECTION IPIPIPIOIOIOOIOOIPOIOIIOIIOIIOIPIPIPIPIPOIPIOIIIIIIIPPPPPP fails LO: 1 1 1 1 1 1 1 1 1 1 1 1 1 1 111111111 fails LO: 0 0 0 000000 00 00 0 00 00 00 000000 00 0 0 0000 fails HI: fails HI: pin: 41 O BU2 E14-3 OUTPUT 17-N (380 OUTPUT) SLOT ABABABAAAAAABAABBBBAABBBBBBBBBBABABABABABBABBBAAABBBAAAAAA LETTER NFPHRJKNLMPTBRSADVCVULKMJHFRSPNDPERDSEUBUVADEEKLMKLMFHJFHJ SIDE 1212122222221221121111111111112121222211211212111222111222 DIRECTION IPIPIPIOIOIOOIOOIPOIOIIOIIOIIOIPIPIPIPIPOIPIOIIIIIIIPPPPPP fails LO: 1 1 1 1 1 1 1 1 1 1 1 1 111111111 fails LO: 0 0 0 000000 00 00 0 00 00 00 0000000000 0 0 0000 fails HI: fails HI: space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C toggle comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit up to this point: PINS that are always low 34 P AE1 E2-3 OUTPUT 14 (75452 OPEN COLLECTOR OUTPUT) 36 P AD2 E5-5 OUTPUT 15 (75452 OPEN COLLECTOR OUTPUT) 38 P AE2 E4-5 OUTPUT 16 (75452 OPEN COLLECTOR OUTPUT) 47 I AK1 E3-6 INPUT BAC0 (DATA FROM I/O BUS) 48 I AL1 E3-5 INPUT BAC1 (DATA FROM I/O BUS) 49 I AM1 E6-11 INPUT BAC2 (DATA FROM I/O BUS) PINS that are always high space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C toggle comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit step 1 0101010000001001001010010010010000000000101010000111111111 step 2 1001010000001001001010010010010000000000101010000111111111 step 3 0101010000001001001010010010010000000000101010000111111111 step 4 0110010000001001001010010010010000000000101010000111111111 step 5 0101010000001001001010010010010000000000101010000111111111 step 6 0101100000001001001010010010010000000000101010000111111111 step 7 0101010000001001001010010010010000000000101010000111111111 step 8 0101011100001001001010010010010000000000101010000111111111 step 9 0101010000001001001010010010010000000000101010000111111111 step 10 0101010011001001001010010010010000000000101010000111111111 step 11 0101010000001001001010010010010000000000101010000111111111 step 12 0101010000110001001010010010010000000000101010000111111111 step 13 0101010000001001001010010010010000000000101010000111111111 step 14 0101010000001110001010010010010000000000101010000111111111 step 15 0101010000001001001010010010010000000000101010000111111111 step 16 0101010000001001110010010010010000000000101010000111111111 step 17 0101010000001001001010010010010000000000101010000111111111 step 18 0101010000001001001100010010010000000000101010000111111111 step 19 0101010000001001001010010010010000000000101010000111111111 step 20 0101010000001001001010100010010000000000101010000111111111 step 21 0101010000001001001011100010010000000000101010000111111111 step 22 0101010000001001001011000010010000000000101010000111111111 step 23 0101010000001001001010010010010000000000101010000111111111 step 24 0101010000001001001010010100010000000000101010000111111111 step 25 0101010000001001001010011100010000000000101010000111111111 step 26 0101010000001001001010011000010000000000101010000111111111 step 27 0101010000001001001010010010010000000000101010000111111111 step 28 0101010000001001001010010010110000000000101010000111111111 step 29 0101010000001001001010010011100000000000101010000111111111 step 30 0101010000001001001010010011010000000000101010000111111111 step 31 0101010000001001001010010010010000000000101010000111111111 step 32 0101010000001001001010010010011100000000101010000111111111 step 33 0101010000001001001010010010010000000000101010000111111111 SLOT ABABABAAAAAABAABBBBAABBBBBBBBBBABABABABABBABBBAAABBBAAAAAA LETTER NFPHRJKNLMPTBRSADVCVULKMJHFRSPNDPERDSEUBUVADEEKLMKLMFHJFHJ SIDE 1212122222221221121111111111112121222211211212111222111222 DIRECTION IPIPIPIOIOIOOIOOIPOIOIIOIIOIIOIPIPIPIPIPOIPIOIIIIIIIPPPPPP changed: 1 step 34 0101010000001001001010010010010010000000101010000111111111 fail ^ step 35 0101010000001001001010010010010000000000101010000111111111 SLOT ABABABAAAAAABAABBBBAABBBBBBBBBBABABABABABBABBBAAABBBAAAAAA LETTER NFPHRJKNLMPTBRSADVCVULKMJHFRSPNDPERDSEUBUVADEEKLMKLMFHJFHJ SIDE 1212122222221221121111111111112121222211211212111222111222 DIRECTION IPIPIPIOIOIOOIOOIPOIOIIOIIOIIOIPIPIPIPIPOIPIOIIIIIIIPPPPPP changed: 1 step 36 0101010000001001001010010010010000100000101010000111111111 fail ^ step 37 0101010000001001001010010010010000000000101010000111111111 SLOT ABABABAAAAAABAABBBBAABBBBBBBBBBABABABABABBABBBAAABBBAAAAAA LETTER NFPHRJKNLMPTBRSADVCVULKMJHFRSPNDPERDSEUBUVADEEKLMKLMFHJFHJ SIDE 1212122222221221121111111111112121222211211212111222111222 DIRECTION IPIPIPIOIOIOOIOOIPOIOIIOIIOIIOIPIPIPIPIPOIPIOIIIIIIIPPPPPP changed: 1 step 38 0101010000001001001010010010010000001000101010000111111111 fail ^ step 39 0101010000001001001010010010010000000000101010000111111111 step 40 0101010000001001001010010010010000000011001010000111111111 SLOT ABABABAAAAAABAABBBBAABBBBBBBBBBABABABABABBABBBAAABBBAAAAAA LETTER NFPHRJKNLMPTBRSADVCVULKMJHFRSPNDPERDSEUBUVADEEKLMKLMFHJFHJ SIDE 1212122222221221121111111111112121222211211212111222111222 DIRECTION IPIPIPIOIOIOOIOOIPOIOIIOIIOIIOIPIPIPIPIPOIPIOIIIIIIIPPPPPP changed: 00 step 41 0101010000001001001010010010010000000000001010000111111111 fail ^ step 42 0101010000001001001010010010010000000000110010000111111111 step 43 0101010000001001001010010010010000000000101010000111111111 step 44 0101010000001001001010010010010000000000101010000111111111 step 45 0101010000001001001010010010010000000000101011000111111111 step 46 0101010000001001001010010010010000000000101011000111111111 step 47 0101010000001001001010010010010000000000101011000101111101 step 48 0101010000001001001010010010010000000000101011000100111100 step 49 0101010000001001001010010010010000000000101011000000111000 step 50 0101010000001001001010010010010000000000101011000001111001 step 51 0101010000001001001010010010010000000000101011000011111011 step 52 0101010000001001001010010010010000000000101011000010111010 step 53 0101010000001001001010010010010000000000101011000110111110 step 54 0101010000001001001010010010010000000000101011000111111111 step 55 0101010000001001001010010010010000000000101101000111111111 step 56 0101010000001001001010010010010000000000101101000111111111 step 57 0101010000001001001010010010010000000000101101000101101111 step 58 0101010000001001001010010010010000000000101101000100100111 step 59 0101010000001001001010010010010000000000101101000000000111 step 60 0101010000001001001010010010010000000000101101000001001111 step 61 0101010000001001001010010010010000000000101101000011011111 step 62 0101010000001001001010010010010000000000101101000010010111 step 63 0101010000001001001010010010010000000000101101000110110111 step 64 0101010000001001001010010010010000000000101101000111111111 step 65 0101010000001001001010010010010000000000101011000111111111 step 66 0101010000001001001010010010010000000000101010000111111111 step 67 0101010000001001001010010010010000000000101010000111111111 step 68 0101010000001001001010010010010000000000101010000101111101 step 69 0101010000001001001010010010010000000000101010000100111100 step 70 0101010000001001001010010010010000000000101010000000111000 step 71 0101010000001001001010010010010000000000101010000001111001 step 72 0101010000001001001010010010010000000000101010000011111011 step 73 0101010000001001001010010010010000000000101010000010111010 step 74 0101010000001001001010010010010000000000101010000110111110 step 75 0101010000001001001010010010010000000000101010000111111111 step 76 0101010000001001001010010010010000000000101010000111111111 test 2: *** FAIL *************************** 4 steps failed SLOT ABABABAAAAAABAABBBBAABBBBBBBBBBABABABABABBABBBAAABBBAAAAAA LETTER NFPHRJKNLMPTBRSADVCVULKMJHFRSPNDPERDSEUBUVADEEKLMKLMFHJFHJ SIDE 1212122222221221121111111111112121222211211212111222111222 DIRECTION IPIPIPIOIOIOOIOOIPOIOIIOIIOIIOIPIPIPIPIPOIPIOIIIIIIIPPPPPP this fail P P P O all fails P P P O was hi 111111111111111111111111111111111 1 1 11111111 111111111 rising ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ ^ ^ ^^^^^^^^ ^^^^^^^^^ falling vvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvv v v vvvvvvvv vvvvvvvvv was lo 0000000000000000000000000000000000000000000000000000000000 total fails 2, total passes 0 space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C toggle comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit step 1 0101010000001001001010010010010000000000101010000111111111 step 2 1001010000001001001010010010010000000000101010000111111111 step 3 0101010000001001001010010010010000000000101010000111111111 step 4 0110010000001001001010010010010000000000101010000111111111 step 5 0101010000001001001010010010010000000000101010000111111111 step 6 0101100000001001001010010010010000000000101010000111111111 step 7 0101010000001001001010010010010000000000101010000111111111 step 8 0101011100001001001010010010010000000000101010000111111111 step 9 0101010000001001001010010010010000000000101010000111111111 step 10 0101010011001001001010010010010000000000101010000111111111 step 11 0101010000001001001010010010010000000000101010000111111111 step 12 0101010000110001001010010010010000000000101010000111111111 step 13 0101010000001001001010010010010000000000101010000111111111 step 14 0101010000001110001010010010010000000000101010000111111111 step 15 0101010000001001001010010010010000000000101010000111111111 step 16 0101010000001001110010010010010000000000101010000111111111 step 17 0101010000001001001010010010010000000000101010000111111111 step 18 0101010000001001001100010010010000000000101010000111111111 step 19 0101010000001001001010010010010000000000101010000111111111 step 20 0101010000001001001010100010010000000000101010000111111111 step 21 0101010000001001001011100010010000000000101010000111111111 step 22 0101010000001001001011000010010000000000101010000111111111 step 23 0101010000001001001010010010010000000000101010000111111111 step 24 0101010000001001001010010100010000000000101010000111111111 step 25 0101010000001001001010011100010000000000101010000111111111 step 26 0101010000001001001010011000010000000000101010000111111111 step 27 0101010000001001001010010010010000000000101010000111111111 step 28 0101010000001001001010010010110000000000101010000111111111 step 29 0101010000001001001010010011100000000000101010000111111111 step 30 0101010000001001001010010011010000000000101010000111111111 step 31 0101010000001001001010010010010000000000101010000111111111 step 32 0101010000001001001010010010011100000000101010000111111111 step 33 0101010000001001001010010010010000000000101010000111111111 SLOT ABABABAAAAAABAABBBBAABBBBBBBBBBABABABABABBABBBAAABBBAAAAAA LETTER NFPHRJKNLMPTBRSADVCVULKMJHFRSPNDPERDSEUBUVADEEKLMKLMFHJFHJ SIDE 1212122222221221121111111111112121222211211212111222111222 DIRECTION IPIPIPIOIOIOOIOOIPOIOIIOIIOIIOIPIPIPIPIPOIPIOIIIIIIIPPPPPP changed: 1 step 34 0101010000001001001010010010010010000000101010000111111111 fail ^ step 35 0101010000001001001010010010010000000000101010000111111111 SLOT ABABABAAAAAABAABBBBAABBBBBBBBBBABABABABABBABBBAAABBBAAAAAA LETTER NFPHRJKNLMPTBRSADVCVULKMJHFRSPNDPERDSEUBUVADEEKLMKLMFHJFHJ SIDE 1212122222221221121111111111112121222211211212111222111222 DIRECTION IPIPIPIOIOIOOIOOIPOIOIIOIIOIIOIPIPIPIPIPOIPIOIIIIIIIPPPPPP changed: 1 step 36 0101010000001001001010010010010000100000101010000111111111 fail ^ step 37 0101010000001001001010010010010000000000101010000111111111 SLOT ABABABAAAAAABAABBBBAABBBBBBBBBBABABABABABBABBBAAABBBAAAAAA LETTER NFPHRJKNLMPTBRSADVCVULKMJHFRSPNDPERDSEUBUVADEEKLMKLMFHJFHJ SIDE 1212122222221221121111111111112121222211211212111222111222 DIRECTION IPIPIPIOIOIOOIOOIPOIOIIOIIOIIOIPIPIPIPIPOIPIOIIIIIIIPPPPPP changed: 1 step 38 0101010000001001001010010010010000001000101010000111111111 fail ^ step 39 0101010000001001001010010010010000000000101010000111111111 step 40 0101010000001001001010010010010000000011001010000111111111 SLOT ABABABAAAAAABAABBBBAABBBBBBBBBBABABABABABBABBBAAABBBAAAAAA LETTER NFPHRJKNLMPTBRSADVCVULKMJHFRSPNDPERDSEUBUVADEEKLMKLMFHJFHJ SIDE 1212122222221221121111111111112121222211211212111222111222 DIRECTION IPIPIPIOIOIOOIOOIPOIOIIOIIOIIOIPIPIPIPIPOIPIOIIIIIIIPPPPPP changed: 00 step 41 0101010000001001001010010010010000000000001010000111111111 fail ^ step 42 0101010000001001001010010010010000000000110010000111111111 step 43 0101010000001001001010010010010000000000101010000111111111 step 44 0101010000001001001010010010010000000000101010000111111111 step 45 0101010000001001001010010010010000000000101011000111111111 step 46 0101010000001001001010010010010000000000101011000111111111 step 47 0101010000001001001010010010010000000000101011000101111101 step 48 0101010000001001001010010010010000000000101011000100111100 step 49 0101010000001001001010010010010000000000101011000000111000 step 50 0101010000001001001010010010010000000000101011000001111001 step 51 0101010000001001001010010010010000000000101011000011111011 step 52 0101010000001001001010010010010000000000101011000010111010 step 53 0101010000001001001010010010010000000000101011000110111110 step 54 0101010000001001001010010010010000000000101011000111111111 step 55 0101010000001001001010010010010000000000101101000111111111 step 56 0101010000001001001010010010010000000000101101000111111111 step 57 0101010000001001001010010010010000000000101101000101101111 step 58 0101010000001001001010010010010000000000101101000100100111 step 59 0101010000001001001010010010010000000000101101000000000111 step 60 0101010000001001001010010010010000000000101101000001001111 step 61 0101010000001001001010010010010000000000101101000011011111 step 62 0101010000001001001010010010010000000000101101000010010111 step 63 0101010000001001001010010010010000000000101101000110110111 step 64 0101010000001001001010010010010000000000101101000111111111 step 65 0101010000001001001010010010010000000000101011000111111111 step 66 0101010000001001001010010010010000000000101010000111111111 step 67 0101010000001001001010010010010000000000101010000111111111 step 68 0101010000001001001010010010010000000000101010000101111101 step 69 0101010000001001001010010010010000000000101010000100111100 step 70 0101010000001001001010010010010000000000101010000000111000 step 71 0101010000001001001010010010010000000000101010000001111001 step 72 0101010000001001001010010010010000000000101010000011111011 step 73 0101010000001001001010010010010000000000101010000010111010 step 74 0101010000001001001010010010010000000000101010000110111110 step 75 0101010000001001001010010010010000000000101010000111111111 step 76 0101010000001001001010010010010000000000101010000111111111 test 3: *** FAIL *************************** 4 steps failed SLOT ABABABAAAAAABAABBBBAABBBBBBBBBBABABABABABBABBBAAABBBAAAAAA LETTER NFPHRJKNLMPTBRSADVCVULKMJHFRSPNDPERDSEUBUVADEEKLMKLMFHJFHJ SIDE 1212122222221221121111111111112121222211211212111222111222 DIRECTION IPIPIPIOIOIOOIOOIPOIOIIOIIOIIOIPIPIPIPIPOIPIOIIIIIIIPPPPPP this fail P P P O all fails P P P O was hi 111111111111111111111111111111111 1 1 11111111 111111111 rising ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ ^ ^ ^^^^^^^^ ^^^^^^^^^ falling vvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvv v v vvvvvvvv vvvvvvvvv was lo 0000000000000000000000000000000000000000000000000000000000 total fails 3, total passes 0 space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C toggle comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit step 1 0101010000001001001010010010010000000000101010000111111111 step 2 1001010000001001001010010010010000000000101010000111111111 step 3 0101010000001001001010010010010000000000101010000111111111 step 4 0110010000001001001010010010010000000000101010000111111111 step 5 0101010000001001001010010010010000000000101010000111111111 step 6 0101100000001001001010010010010000000000101010000111111111 step 7 0101010000001001001010010010010000000000101010000111111111 step 8 0101011100001001001010010010010000000000101010000111111111 step 9 0101010000001001001010010010010000000000101010000111111111 step 10 0101010011001001001010010010010000000000101010000111111111 step 11 0101010000001001001010010010010000000000101010000111111111 step 12 0101010000110001001010010010010000000000101010000111111111 step 13 0101010000001001001010010010010000000000101010000111111111 step 14 0101010000001110001010010010010000000000101010000111111111 step 15 0101010000001001001010010010010000000000101010000111111111 step 16 0101010000001001110010010010010000000000101010000111111111 step 17 0101010000001001001010010010010000000000101010000111111111 step 18 0101010000001001001100010010010000000000101010000111111111 step 19 0101010000001001001010010010010000000000101010000111111111 step 20 0101010000001001001010100010010000000000101010000111111111 step 21 0101010000001001001011100010010000000000101010000111111111 step 22 0101010000001001001011000010010000000000101010000111111111 step 23 0101010000001001001010010010010000000000101010000111111111 step 24 0101010000001001001010010100010000000000101010000111111111 step 25 0101010000001001001010011100010000000000101010000111111111 step 26 0101010000001001001010011000010000000000101010000111111111 step 27 0101010000001001001010010010010000000000101010000111111111 step 28 0101010000001001001010010010110000000000101010000111111111 step 29 0101010000001001001010010011100000000000101010000111111111 step 30 0101010000001001001010010011010000000000101010000111111111 step 31 0101010000001001001010010010010000000000101010000111111111 step 32 0101010000001001001010010010011100000000101010000111111111 step 33 0101010000001001001010010010010000000000101010000111111111 SLOT ABABABAAAAAABAABBBBAABBBBBBBBBBABABABABABBABBBAAABBBAAAAAA LETTER NFPHRJKNLMPTBRSADVCVULKMJHFRSPNDPERDSEUBUVADEEKLMKLMFHJFHJ SIDE 1212122222221221121111111111112121222211211212111222111222 DIRECTION IPIPIPIOIOIOOIOOIPOIOIIOIIOIIOIPIPIPIPIPOIPIOIIIIIIIPPPPPP changed: 1 step 34 0101010000001001001010010010010010000000101010000111111111 fail ^ space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C toggle comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit step 35 0101010000001001001010010010010000000000101010000111111111 SLOT ABABABAAAAAABAABBBBAABBBBBBBBBBABABABABABBABBBAAABBBAAAAAA LETTER NFPHRJKNLMPTBRSADVCVULKMJHFRSPNDPERDSEUBUVADEEKLMKLMFHJFHJ SIDE 1212122222221221121111111111112121222211211212111222111222 DIRECTION IPIPIPIOIOIOOIOOIPOIOIIOIIOIIOIPIPIPIPIPOIPIOIIIIIIIPPPPPP changed: 1 step 36 0101010000001001001010010010010000100000101010000111111111 fail ^ space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C toggle comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit step 37 0101010000001001001010010010010000000000101010000111111111 SLOT ABABABAAAAAABAABBBBAABBBBBBBBBBABABABABABBABBBAAABBBAAAAAA LETTER NFPHRJKNLMPTBRSADVCVULKMJHFRSPNDPERDSEUBUVADEEKLMKLMFHJFHJ SIDE 1212122222221221121111111111112121222211211212111222111222 DIRECTION IPIPIPIOIOIOOIOOIPOIOIIOIIOIIOIPIPIPIPIPOIPIOIIIIIIIPPPPPP changed: 1 step 38 0101010000001001001010010010010000001000101010000111111111 fail ^ space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C toggle comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit step 39 0101010000001001001010010010010000000000101010000111111111 step 40 0101010000001001001010010010010000000011001010000111111111 SLOT ABABABAAAAAABAABBBBAABBBBBBBBBBABABABABABBABBBAAABBBAAAAAA LETTER NFPHRJKNLMPTBRSADVCVULKMJHFRSPNDPERDSEUBUVADEEKLMKLMFHJFHJ SIDE 1212122222221221121111111111112121222211211212111222111222 DIRECTION IPIPIPIOIOIOOIOOIPOIOIIOIIOIIOIPIPIPIPIPOIPIOIIIIIIIPPPPPP changed: 00 step 41 0101010000001001001010010010010000000000001010000111111111 fail ^ space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C toggle comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit step 42 0101010000001001001010010010010000000000110010000111111111 step 43 0101010000001001001010010010010000000000101010000111111111 step 44 0101010000001001001010010010010000000000101010000111111111 step 45 0101010000001001001010010010010000000000101011000111111111 step 46 0101010000001001001010010010010000000000101011000111111111 step 47 0101010000001001001010010010010000000000101011000101111101 step 48 0101010000001001001010010010010000000000101011000100111100 step 49 0101010000001001001010010010010000000000101011000000111000 step 50 0101010000001001001010010010010000000000101011000001111001 step 51 0101010000001001001010010010010000000000101011000011111011 step 52 0101010000001001001010010010010000000000101011000010111010 step 53 0101010000001001001010010010010000000000101011000110111110 step 54 0101010000001001001010010010010000000000101011000111111111 step 55 0101010000001001001010010010010000000000101101000111111111 step 56 0101010000001001001010010010010000000000101101000111111111 step 57 0101010000001001001010010010010000000000101101000101101111 step 58 0101010000001001001010010010010000000000101101000100100111 step 59 0101010000001001001010010010010000000000101101000000000111 step 60 0101010000001001001010010010010000000000101101000001001111 step 61 0101010000001001001010010010010000000000101101000011011111 step 62 0101010000001001001010010010010000000000101101000010010111 step 63 0101010000001001001010010010010000000000101101000110110111 step 64 0101010000001001001010010010010000000000101101000111111111 step 65 0101010000001001001010010010010000000000101011000111111111 step 66 0101010000001001001010010010010000000000101010000111111111 step 67 0101010000001001001010010010010000000000101010000111111111 step 68 0101010000001001001010010010010000000000101010000101111101 step 69 0101010000001001001010010010010000000000101010000100111100 step 70 0101010000001001001010010010010000000000101010000000111000 step 71 0101010000001001001010010010010000000000101010000001111001 step 72 0101010000001001001010010010010000000000101010000011111011 step 73 0101010000001001001010010010010000000000101010000010111010 step 74 0101010000001001001010010010010000000000101010000110111110 step 75 0101010000001001001010010010010000000000101010000111111111 step 76 0101010000001001001010010010010000000000101010000111111111 test 4: *** FAIL *************************** 4 steps failed SLOT ABABABAAAAAABAABBBBAABBBBBBBBBBABABABABABBABBBAAABBBAAAAAA LETTER NFPHRJKNLMPTBRSADVCVULKMJHFRSPNDPERDSEUBUVADEEKLMKLMFHJFHJ SIDE 1212122222221221121111111111112121222211211212111222111222 DIRECTION IPIPIPIOIOIOOIOOIPOIOIIOIIOIIOIPIPIPIPIPOIPIOIIIIIIIPPPPPP this fail P P P O all fails P P P O was hi 111111111111111111111111111111111 1 1 11111111 111111111 rising ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ ^ ^ ^^^^^^^^ ^^^^^^^^^ falling vvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvv v v vvvvvvvv vvvvvvvvv was lo 0000000000000000000000000000000000000000000000000000000000 total fails 4, total passes 0 step 1 0101010000001001001010010010010000000000101010000111111111 step 2 1001010000001001001010010010010000000000101010000111111111 step 3 0101010000001001001010010010010000000000101010000111111111 step 4 0110010000001001001010010010010000000000101010000111111111 step 5 0101010000001001001010010010010000000000101010000111111111 step 6 0101100000001001001010010010010000000000101010000111111111 step 7 0101010000001001001010010010010000000000101010000111111111 step 8 0101011100001001001010010010010000000000101010000111111111 step 9 0101010000001001001010010010010000000000101010000111111111 step 10 0101010011001001001010010010010000000000101010000111111111 step 11 0101010000001001001010010010010000000000101010000111111111 step 12 0101010000110001001010010010010000000000101010000111111111 step 13 0101010000001001001010010010010000000000101010000111111111 step 14 0101010000001110001010010010010000000000101010000111111111 step 15 0101010000001001001010010010010000000000101010000111111111 step 16 0101010000001001110010010010010000000000101010000111111111 step 17 0101010000001001001010010010010000000000101010000111111111 step 18 0101010000001001001100010010010000000000101010000111111111 step 19 0101010000001001001010010010010000000000101010000111111111 step 20 0101010000001001001010100010010000000000101010000111111111 step 21 0101010000001001001011100010010000000000101010000111111111 step 22 0101010000001001001011000010010000000000101010000111111111 step 23 0101010000001001001010010010010000000000101010000111111111 step 24 0101010000001001001010010100010000000000101010000111111111 step 25 0101010000001001001010011100010000000000101010000111111111 step 26 0101010000001001001010011000010000000000101010000111111111 step 27 0101010000001001001010010010010000000000101010000111111111 step 28 0101010000001001001010010010110000000000101010000111111111 step 29 0101010000001001001010010011100000000000101010000111111111 step 30 0101010000001001001010010011010000000000101010000111111111 step 31 0101010000001001001010010010010000000000101010000111111111 step 32 0101010000001001001010010010011100000000101010000111111111 step 33 0101010000001001001010010010010000000000101010000111111111 SLOT ABABABAAAAAABAABBBBAABBBBBBBBBBABABABABABBABBBAAABBBAAAAAA LETTER NFPHRJKNLMPTBRSADVCVULKMJHFRSPNDPERDSEUBUVADEEKLMKLMFHJFHJ SIDE 1212122222221221121111111111112121222211211212111222111222 DIRECTION IPIPIPIOIOIOOIOOIPOIOIIOIIOIIOIPIPIPIPIPOIPIOIIIIIIIPPPPPP changed: 1 step 34 0101010000001001001010010010010010000000101010000111111111 fail ^ space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C toggle comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit step 35 0101010000001001001010010010010000000000101010000111111111 SLOT ABABABAAAAAABAABBBBAABBBBBBBBBBABABABABABBABBBAAABBBAAAAAA LETTER NFPHRJKNLMPTBRSADVCVULKMJHFRSPNDPERDSEUBUVADEEKLMKLMFHJFHJ SIDE 1212122222221221121111111111112121222211211212111222111222 DIRECTION IPIPIPIOIOIOOIOOIPOIOIIOIIOIIOIPIPIPIPIPOIPIOIIIIIIIPPPPPP changed: 1 step 36 0101010000001001001010010010010000100000101010000111111111 fail ^ space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C toggle comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit step 37 0101010000001001001010010010010000000000101010000111111111 SLOT ABABABAAAAAABAABBBBAABBBBBBBBBBABABABABABBABBBAAABBBAAAAAA LETTER NFPHRJKNLMPTBRSADVCVULKMJHFRSPNDPERDSEUBUVADEEKLMKLMFHJFHJ SIDE 1212122222221221121111111111112121222211211212111222111222 DIRECTION IPIPIPIOIOIOOIOOIPOIOIIOIIOIIOIPIPIPIPIPOIPIOIIIIIIIPPPPPP changed: 1 step 38 0101010000001001001010010010010000001000101010000111111111 fail ^ space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C toggle comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit step 39 0101010000001001001010010010010000000000101010000111111111 step 40 0101010000001001001010010010010000000011001010000111111111 SLOT ABABABAAAAAABAABBBBAABBBBBBBBBBABABABABABBABBBAAABBBAAAAAA LETTER NFPHRJKNLMPTBRSADVCVULKMJHFRSPNDPERDSEUBUVADEEKLMKLMFHJFHJ SIDE 1212122222221221121111111111112121222211211212111222111222 DIRECTION IPIPIPIOIOIOOIOOIPOIOIIOIIOIIOIPIPIPIPIPOIPIOIIIIIIIPPPPPP changed: 00 step 41 0101010000001001001010010010010000000000001010000111111111 fail ^ space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C toggle comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit step 42 0101010000001001001010010010010000000000110010000111111111 step 43 0101010000001001001010010010010000000000101010000111111111 step 44 0101010000001001001010010010010000000000101010000111111111 step 45 0101010000001001001010010010010000000000101011000111111111 step 46 0101010000001001001010010010010000000000101011000111111111 step 47 0101010000001001001010010010010000000000101011000101111101 step 48 0101010000001001001010010010010000000000101011000100111100 step 49 0101010000001001001010010010010000000000101011000000111000 step 50 0101010000001001001010010010010000000000101011000001111001 step 51 0101010000001001001010010010010000000000101011000011111011 step 52 0101010000001001001010010010010000000000101011000010111010 step 53 0101010000001001001010010010010000000000101011000110111110 step 54 0101010000001001001010010010010000000000101011000111111111 step 55 0101010000001001001010010010010000000000101101000111111111 step 56 0101010000001001001010010010010000000000101101000111111111 step 57 0101010000001001001010010010010000000000101101000101101111 step 58 0101010000001001001010010010010000000000101101000100100111 step 59 0101010000001001001010010010010000000000101101000000000111 step 60 0101010000001001001010010010010000000000101101000001001111 step 61 0101010000001001001010010010010000000000101101000011011111 step 62 0101010000001001001010010010010000000000101101000010010111 step 63 0101010000001001001010010010010000000000101101000110110111 step 64 0101010000001001001010010010010000000000101101000111111111 step 65 0101010000001001001010010010010000000000101011000111111111 step 66 0101010000001001001010010010010000000000101010000111111111 step 67 0101010000001001001010010010010000000000101010000111111111 step 68 0101010000001001001010010010010000000000101010000101111101 step 69 0101010000001001001010010010010000000000101010000100111100 step 70 0101010000001001001010010010010000000000101010000000111000 step 71 0101010000001001001010010010010000000000101010000001111001 step 72 0101010000001001001010010010010000000000101010000011111011 step 73 0101010000001001001010010010010000000000101010000010111010 step 74 0101010000001001001010010010010000000000101010000110111110 step 75 0101010000001001001010010010010000000000101010000111111111 step 76 0101010000001001001010010010010000000000101010000111111111 test 5: *** FAIL *************************** 4 steps failed SLOT ABABABAAAAAABAABBBBAABBBBBBBBBBABABABABABBABBBAAABBBAAAAAA LETTER NFPHRJKNLMPTBRSADVCVULKMJHFRSPNDPERDSEUBUVADEEKLMKLMFHJFHJ SIDE 1212122222221221121111111111112121222211211212111222111222 DIRECTION IPIPIPIOIOIOOIOOIPOIOIIOIIOIIOIPIPIPIPIPOIPIOIIIIIIIPPPPPP this fail P P P O all fails P P P O was hi 111111111111111111111111111111111 1 1 11111111 111111111 rising ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ ^ ^ ^^^^^^^^ ^^^^^^^^^ falling vvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvv v v vvvvvvvv vvvvvvvvv was lo 0000000000000000000000000000000000000000000000000000000000 total fails 5, total passes 0 step 1 0101010000001001001010010010010000000000101010000111111111 step 2 1001010000001001001010010010010000000000101010000111111111 step 3 0101010000001001001010010010010000000000101010000111111111 step 4 0110010000001001001010010010010000000000101010000111111111 step 5 0101010000001001001010010010010000000000101010000111111111 step 6 0101100000001001001010010010010000000000101010000111111111 step 7 0101010000001001001010010010010000000000101010000111111111 step 8 0101011100001001001010010010010000000000101010000111111111 step 9 0101010000001001001010010010010000000000101010000111111111 step 10 0101010011001001001010010010010000000000101010000111111111 step 11 0101010000001001001010010010010000000000101010000111111111 step 12 0101010000110001001010010010010000000000101010000111111111 step 13 0101010000001001001010010010010000000000101010000111111111 step 14 0101010000001110001010010010010000000000101010000111111111 step 15 0101010000001001001010010010010000000000101010000111111111 step 16 0101010000001001110010010010010000000000101010000111111111 step 17 0101010000001001001010010010010000000000101010000111111111 step 18 0101010000001001001100010010010000000000101010000111111111 step 19 0101010000001001001010010010010000000000101010000111111111 step 20 0101010000001001001010100010010000000000101010000111111111 step 21 0101010000001001001011100010010000000000101010000111111111 step 22 0101010000001001001011000010010000000000101010000111111111 step 23 0101010000001001001010010010010000000000101010000111111111 step 24 0101010000001001001010010100010000000000101010000111111111 step 25 0101010000001001001010011100010000000000101010000111111111 step 26 0101010000001001001010011000010000000000101010000111111111 step 27 0101010000001001001010010010010000000000101010000111111111 step 28 0101010000001001001010010010110000000000101010000111111111 step 29 0101010000001001001010010011100000000000101010000111111111 step 30 0101010000001001001010010011010000000000101010000111111111 step 31 0101010000001001001010010010010000000000101010000111111111 step 32 0101010000001001001010010010011100000000101010000111111111 step 33 0101010000001001001010010010010000000000101010000111111111 SLOT ABABABAAAAAABAABBBBAABBBBBBBBBBABABABABABBABBBAAABBBAAAAAA LETTER NFPHRJKNLMPTBRSADVCVULKMJHFRSPNDPERDSEUBUVADEEKLMKLMFHJFHJ SIDE 1212122222221221121111111111112121222211211212111222111222 DIRECTION IPIPIPIOIOIOOIOOIPOIOIIOIIOIIOIPIPIPIPIPOIPIOIIIIIIIPPPPPP changed: 1 step 34 0101010000001001001010010010010010000000101010000111111111 fail ^ space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C toggle comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit step 35 0101010000001001001010010010010000000000101010000111111111 SLOT ABABABAAAAAABAABBBBAABBBBBBBBBBABABABABABBABBBAAABBBAAAAAA LETTER NFPHRJKNLMPTBRSADVCVULKMJHFRSPNDPERDSEUBUVADEEKLMKLMFHJFHJ SIDE 1212122222221221121111111111112121222211211212111222111222 DIRECTION IPIPIPIOIOIOOIOOIPOIOIIOIIOIIOIPIPIPIPIPOIPIOIIIIIIIPPPPPP changed: 1 step 36 0101010000001001001010010010010000100000101010000111111111 fail ^ space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C toggle comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit step 37 0101010000001001001010010010010000000000101010000111111111 SLOT ABABABAAAAAABAABBBBAABBBBBBBBBBABABABABABBABBBAAABBBAAAAAA LETTER NFPHRJKNLMPTBRSADVCVULKMJHFRSPNDPERDSEUBUVADEEKLMKLMFHJFHJ SIDE 1212122222221221121111111111112121222211211212111222111222 DIRECTION IPIPIPIOIOIOOIOOIPOIOIIOIIOIIOIPIPIPIPIPOIPIOIIIIIIIPPPPPP changed: 1 step 38 0101010000001001001010010010010000001000101010000111111111 fail ^ space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C toggle comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit step 39 0101010000001001001010010010010000000000101010000111111111 step 40 0101010000001001001010010010010000000011001010000111111111 step 41 0101010000001001001010010010010000000000101010000111111111 step 42 0101010000001001001010010010010000000000110010000111111111 step 43 0101010000001001001010010010010000000000101010000111111111 step 44 0101010000001001001010010010010000000000101010000111111111 step 45 0101010000001001001010010010010000000000101011000111111111 step 46 0101010000001001001010010010010000000000101011000111111111 step 47 0101010000001001001010010010010000000000101011000101111101 step 48 0101010000001001001010010010010000000000101011000100111100 step 49 0101010000001001001010010010010000000000101011000000111000 step 50 0101010000001001001010010010010000000000101011000001111001 step 51 0101010000001001001010010010010000000000101011000011111011 step 52 0101010000001001001010010010010000000000101011000010111010 step 53 0101010000001001001010010010010000000000101011000110111110 step 54 0101010000001001001010010010010000000000101011000111111111 step 55 0101010000001001001010010010010000000000101101000111111111 step 56 0101010000001001001010010010010000000000101101000111111111 step 57 0101010000001001001010010010010000000000101101000101101111 step 58 0101010000001001001010010010010000000000101101000100100111 step 59 0101010000001001001010010010010000000000101101000000000111 step 60 0101010000001001001010010010010000000000101101000001001111 step 61 0101010000001001001010010010010000000000101101000011011111 step 62 0101010000001001001010010010010000000000101101000010010111 step 63 0101010000001001001010010010010000000000101101000110110111 step 64 0101010000001001001010010010010000000000101101000111111111 step 65 0101010000001001001010010010010000000000101011000111111111 step 66 0101010000001001001010010010010000000000101010000111111111 step 67 0101010000001001001010010010010000000000101010000111111111 step 68 0101010000001001001010010010010000000000101010000101111101 step 69 0101010000001001001010010010010000000000101010000100111100 step 70 0101010000001001001010010010010000000000101010000000111000 step 71 0101010000001001001010010010010000000000101010000001111001 step 72 0101010000001001001010010010010000000000101010000011111011 step 73 0101010000001001001010010010010000000000101010000010111010 step 74 0101010000001001001010010010010000000000101010000110111110 step 75 0101010000001001001010010010010000000000101010000111111111 step 76 0101010000001001001010010010010000000000101010000111111111 test 6: *** FAIL *************************** 3 steps failed SLOT ABABABAAAAAABAABBBBAABBBBBBBBBBABABABABABBABBBAAABBBAAAAAA LETTER NFPHRJKNLMPTBRSADVCVULKMJHFRSPNDPERDSEUBUVADEEKLMKLMFHJFHJ SIDE 1212122222221221121111111111112121222211211212111222111222 DIRECTION IPIPIPIOIOIOOIOOIPOIOIIOIIOIIOIPIPIPIPIPOIPIOIIIIIIIPPPPPP this fail P P P all fails P P P O was hi 111111111111111111111111111111111 1 1 11111111 111111111 rising ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ ^ ^ ^^^^^^^^ ^^^^^^^^^ falling vvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvv v v vvvvvvvv vvvvvvvvv was lo 0000000000000000000000000000000000000000000000000000000000 total fails 6, total passes 0 step 1 0101010000001001001010010010010000000000101010000111111111 step 2 1001010000001001001010010010010000000000101010000111111111 step 3 0101010000001001001010010010010000000000101010000111111111 step 4 0110010000001001001010010010010000000000101010000111111111 step 5 0101010000001001001010010010010000000000101010000111111111 step 6 0101100000001001001010010010010000000000101010000111111111 step 7 0101010000001001001010010010010000000000101010000111111111 step 8 0101011100001001001010010010010000000000101010000111111111 step 9 0101010000001001001010010010010000000000101010000111111111 step 10 0101010011001001001010010010010000000000101010000111111111 step 11 0101010000001001001010010010010000000000101010000111111111 step 12 0101010000110001001010010010010000000000101010000111111111 step 13 0101010000001001001010010010010000000000101010000111111111 step 14 0101010000001110001010010010010000000000101010000111111111 step 15 0101010000001001001010010010010000000000101010000111111111 step 16 0101010000001001110010010010010000000000101010000111111111 step 17 0101010000001001001010010010010000000000101010000111111111 step 18 0101010000001001001100010010010000000000101010000111111111 step 19 0101010000001001001010010010010000000000101010000111111111 step 20 0101010000001001001010100010010000000000101010000111111111 step 21 0101010000001001001011100010010000000000101010000111111111 step 22 0101010000001001001011000010010000000000101010000111111111 step 23 0101010000001001001010010010010000000000101010000111111111 step 24 0101010000001001001010010100010000000000101010000111111111 step 25 0101010000001001001010011100010000000000101010000111111111 step 26 0101010000001001001010011000010000000000101010000111111111 step 27 0101010000001001001010010010010000000000101010000111111111 step 28 0101010000001001001010010010110000000000101010000111111111 step 29 0101010000001001001010010011100000000000101010000111111111 step 30 0101010000001001001010010011010000000000101010000111111111 step 31 0101010000001001001010010010010000000000101010000111111111 step 32 0101010000001001001010010010011100000000101010000111111111 step 33 0101010000001001001010010010010000000000101010000111111111 SLOT ABABABAAAAAABAABBBBAABBBBBBBBBBABABABABABBABBBAAABBBAAAAAA LETTER NFPHRJKNLMPTBRSADVCVULKMJHFRSPNDPERDSEUBUVADEEKLMKLMFHJFHJ SIDE 1212122222221221121111111111112121222211211212111222111222 DIRECTION IPIPIPIOIOIOOIOOIPOIOIIOIIOIIOIPIPIPIPIPOIPIOIIIIIIIPPPPPP changed: 1 step 34 0101010000001001001010010010010010000000101010000111111111 fail ^ space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C toggle comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT ABABABAAAAAABAABBBBAABBBBBBBBBBABABABABABBABBBAAABBBAAAAAA LETTER NFPHRJKNLMPTBRSADVCVULKMJHFRSPNDPERDSEUBUVADEEKLMKLMFHJFHJ SIDE 1212122222221221121111111111112121222211211212111222111222 DIRECTION IPIPIPIOIOIOOIOOIPOIOIIOIIOIIOIPIPIPIPIPOIPIOIIIIIIIPPPPPP all fails P P P O was lo 0000000000000000000000000000000000000000000000000000000000 falling vvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvv v v vvvvvvvv vvvvvvvvv rising ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ ^ ^ ^^^^^^^^ ^^^^^^^^^ was hi 111111111111111111111111111111111 1 1 11111111 111111111 total fails 6, total passes 0 Main menu Sun Nov 22 19:02:37 2015 test file is: tests\m7102_2.tst delay is: 0 trigger is: 1 1 read test file 2 set test delay 3 set test trigger 4 run test 5 output loading test 8 diags 9 exit exiting